構文
構文struct vxge_hw_vpath_reg
ファイル名
ファイル名構造体情報
構造体情報| No. | 名称 | 属性 | 説明 |
|---|---|---|---|
1 |
vxge_hw_vpath_reg | ||
| unused00300[0x00300] | u8 | ||
| usdc_vpath | u64 | 0x00300 | |
| vxge_vBIT(val, 0, 32) u8 unused00a00[0x00a00-0x00308] | |||
| wrdma_alarm_status | u64 | 0x00a00 | |
| wrdma_alarm_mask | 0x00a08 | ||
| unused00a30[0x00a30-0x00a10] | u8 | ||
| prc_alarm_reg | u64 | 0x00a30 | |
| prc_alarm_mask | 0x00a38 | ||
| prc_alarm_alarm | u64 | 0x00a40 | |
| prc_cfg1 | u64 | 0x00a48 | |
| vxge_vBIT(val, 3, 29) #define VXGE_HW_PRC_CFG1_TIM_RING_BUMP_INT_ENABLE vxge_mBIT(34) #define VXGE_HW_PRC_CFG1_RTI_TINT_DISABLE | |||
| prc_cfg4 | u64 | 0x00a60 | |
| vxge_vBIT(val, 14, 2) #define VXGE_HW_PRC_CFG4_RXD_NO_SNOOP vxge_mBIT(22) #define VXGE_HW_PRC_CFG4_FRM_NO_SNOOP vxge_mBIT(23) # | 0x00a68 | ||
| vxge_vBIT(val, 0, 61) u64 prc_cfg6 | 0x00a70 | ||
| vxge_vBIT(val, 23, 9) #define VXGE_HW_PRC_CFG6_GET_RXD_CRXDT(val) vxge_bVALn(val, 23, 9) #define VXGE_HW_PRC_CFG6_RXD_SPAT(val) | 0x00a78 | ||
| vxge_vBIT(val, 6, 2) #define VXGE_HW_PRC_CFG7_SMART_SCAT_EN vxge_mBIT(11) #define VXGE_HW_PRC_CFG7_RXD_NS_CHG_EN vxge_mBIT(12) | 0x00a80 | ||
| vxge_vBIT(val, 0, 64) u64 prc_rxd_doorbell | 0x00a88 | ||
| vxge_vBIT(val, 48, 16) u64 rqa_prty_for_vp | 0x00a90 | ||
| vxge_vBIT(val, 59, 5) u64 rxdmem_size | 0x00a98 | ||
| vxge_vBIT(val, 51, 13) u64 frm_in_progress_cnt | 0x00aa0 | ||
| vxge_vBIT(val, 59, 5) u64 rx_multi_cast_stats | 0x00aa8 | ||
| vxge_vBIT(val, 48, 16) u64 rx_frm_transferred | 0x00ab0 | ||
| vxge_vBIT(val, 32, 32) u64 rxd_returned | 0x00ab8 | ||
| vxge_vBIT(val, 48, 16) u8 unused00c00[0x00c00-0x00ac0] | |||
| kdfc_fifo_trpl_partition | u64 | 0x00c00 | |
| vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_FIFO_TRPL_PARTITION_LENGTH_1(val) vxge_vBIT(val, 33, 15) #define VXGE_HW_KDFC_FIFO_ | 0x00c08 | ||
| kdfc_trpl_fifo_0_ctrl | 0x00c10 | ||
| vxge_vBIT(val, 14, 2) #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_FLIP_EN vxge_mBIT(22) #define VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_SWAP_EN | 0x00c18 | ||
| vxge_vBIT(val, 14, 2) #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_FLIP_EN vxge_mBIT(22) #define VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_SWAP_EN | 0x00c20 | ||
| vxge_vBIT(val, 26, 2) #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_CTRL_STRUC vxge_mBIT(28) #define VXGE_HW_KDFC_TRPL_FIFO_2_CTRL_ADD_ | 0x00c28 | ||
| vxge_vBIT(val, 0, 64) u64 kdfc_trpl_fifo_1_wb_address | 0x00c30 | ||
| vxge_vBIT(val, 0, 64) u64 kdfc_trpl_fifo_2_wb_address | 0x00c38 | ||
| vxge_vBIT(val, 0, 64) u64 kdfc_trpl_fifo_offset | 0x00c40 | ||
| vxge_vBIT(val, 1, 15) #define VXGE_HW_KDFC_TRPL_FIFO_OFFSET_KDFC_RCTR1(val) vxge_vBIT(val, 17, 15) #define VXGE_HW_KDFC_TRPL_FI | 0x00c48 | ||
| vxge_vBIT(val, 17, 15) u8 unused00c60[0x00c60-0x00c50] | |||
| usdc_drbl_ctrl | u64 | 0x00c60 | |
| usdc_vp_ready | 0x00c68 | ||
| kdfc_status | 0x00c70 | ||
| unused00c80[0x00c80-0x00c78] | |||
| xmac_rpa_vcfg | u64 | 0x00c80 | |
| rxmac_vcfg0 | 0x00c88 | ||
| vxge_vBIT(val, 42, 2) #define VXGE_HW_RXMAC_VCFG1_RTS_RTH_MULTI_IT_EN_MODE vxge_mBIT(47) #define VXGE_HW_RXMAC_VCFG1_CONTRIB_L2 | 0x00c98 | ||
| vxge_vBIT(val, 1, 7) #define VXGE_HW_RTS_ACCESS_STEER_CTRL_DATA_STRUCT_SEL(val) vxge_vBIT(val, 8, 4) #define VXGE_HW_RTS_ACCESS | 0x00ca0 | ||
| vxge_vBIT(val, 0, 64) u64 rts_access_steer_data1 | 0x00ca8 | ||
| vxge_vBIT(val, 0, 64) #define VXGE_HW_RTS_ACCESS_STEER_DATA1_PRIV_MODE_EN vxge_mBIT(54) #define VXGE_HW_RTS_ACCESS_STEER_DATA1_ | |||
| xmac_vsport_choice | u64 | 0x00d00 | |
| vxge_vBIT(val, 3, 5) u64 xmac_stats_cfg | 0x00d08 | ||
| xmac_stats_access_cmd | u64 | 0x00d10 | |
| vxge_vBIT(val, 6, 2) #define VXGE_HW_XMAC_STATS_ACCESS_CMD_STROBE vxge_mBIT(15) #define VXGE_HW_XMAC_STATS_ACCESS_CMD_OFFSET_SE | 0x00d18 | ||
| vxge_vBIT(val, 0, 64) u64 asic_ntwk_vp_ctrl | 0x00d20 | ||
| unused00d30[0x00d30-0x00d28] | |||
| xgmac_vp_int_status | u64 | 0x00d30 | |
| xgmac_vp_int_mask | 0x00d38 | ||
| asic_ntwk_vp_err_reg | u64 | 0x00d40 | |
| asic_ntwk_vp_err_mask | 0x00d48 | ||
| asic_ntwk_vp_err_alarm | u64 | 0x00d50 | |
| unused00d80[0x00d80-0x00d58] | u8 | ||
| rtdma_bw_ctrl | u64 | 0x00d80 | |
| vxge_vBIT(val, 46, 18) u64 rtdma_rd_optimization_ctrl | 0x00d88 | ||
| vxge_vBIT(val, 6, 2) #define VXGE_HW_RTDMA_RD_OPTIMIZATION_CTRL_PAD_PATTERN(val) vxge_vBIT(val, 8, 8) #define VXGE_HW_RTDMA_RD_ | 0x00d90 | ||
| tx_protocol_assist_cfg | 0x00d98 | ||
| unused01000[0x01000-0x00da0] | |||
| tim_cfg1_int_num[4] | u64 | 0x01000 | |
| vxge_vBIT(val, 6, 26) #define VXGE_HW_TIM_CFG1_INT_NUM_BITMP_EN vxge_mBIT(35) #define VXGE_HW_TIM_CFG1_INT_NUM_TXFRM_CNT_EN vxg | 0x01020 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_B(val) vxge_vBIT(val, 16, 16) #define VXGE_HW_TIM_CFG2_INT_NUM_UEC_C | 0x01040 | ||
| vxge_vBIT(val, 1, 4) #define VXGE_HW_TIM_CFG3_INT_NUM_RTIMER_VAL(val) vxge_vBIT(val, 6, 26) #define VXGE_HW_TIM_CFG3_INT_NUM_UT | 0x01060 | ||
| vxge_vBIT(val, 0, 32) #define VXGE_HW_TIM_WRKLD_CLC_WRKLD_EVAL_DIV(val) vxge_vBIT(val, 35, 5) #define VXGE_HW_TIM_WRKLD_CLC_CNT | 0x01068 | ||
| vxge_vBIT(val, 0, 32) #define VXGE_HW_TIM_BITMAP_LLROOT_RXD_EN vxge_mBIT(32) #define VXGE_HW_TIM_BITMAP_LLROOT_TXD_EN vxge_mBIT | 0x01070 | ||
| vxge_vBIT(val, 6, 2) u64 tim_remap | 0x01078 | ||
| vxge_vBIT(val, 11, 5) u64 tim_vpath_map | 0x01080 | ||
| vxge_vBIT(val, 0, 32) u64 tim_pci_cfg | 0x01088 | ||
| unused01100[0x01100-0x01090] | |||
| sgrp_assign | u64 | 0x01100 | |
| vxge_vBIT(val, 0, 64) u64 sgrp_aoa_and_result | 0x01108 | ||
| vxge_vBIT(val, 0, 64) u64 rpe_pci_cfg | 0x01110 | ||
| rpe_lro_cfg | 0x01118 | ||
| pe_mr2vp_ack_blk_limit | 0x01120 | ||
| vxge_vBIT(val, 32, 32) u64 pe_mr2vp_rirr_lirr_blk_limit | 0x01128 | ||
| vxge_vBIT(val, 0, 32) #define VXGE_HW_PE_MR2VP_RIRR_LIRR_BLK_LIMIT_LIRR_BLK_LIMIT(val) \ vxge_vBIT(val, 32, 32) u64 txpe_pci_nc | 0x01130 | ||
| vxge_vBIT(val, 0, 32) #define VXGE_HW_TXPE_PCI_NCE_CFG_PAD_TOWI_ENABLE vxge_mBIT(55) #define VXGE_HW_TXPE_PCI_NCE_CFG_NOSNOOP_T | |||
| msg_qpad_en_cfg | u64 | 0x01180 | |
| msg_pci_cfg | 0x01188 | ||
| umqdmq_ir_init | 0x01190 | ||
| vxge_vBIT(val, 0, 64) u64 dmq_ir_int | 0x01198 | ||
| vxge_vBIT(val, 9, 7) #define VXGE_HW_DMQ_IR_INT_BITMAP(val) vxge_vBIT(val, 16, 16) u64 dmq_bwr_init_add | 0x011a0 | ||
| vxge_vBIT(val, 0, 64) u64 dmq_bwr_init_byte | 0x011a8 | ||
| vxge_vBIT(val, 0, 32) u64 dmq_ir | 0x011b0 | ||
| vxge_vBIT(val, 0, 8) u64 umq_int | 0x011b8 | ||
| vxge_vBIT(val, 9, 7) #define VXGE_HW_UMQ_INT_BITMAP(val) vxge_vBIT(val, 16, 16) u64 umq_mr2vp_bwr_pfch_init | 0x011c0 | ||
| vxge_vBIT(val, 0, 8) u64 umq_bwr_pfch_ctrl | 0x011c8 | ||
| umq_mr2vp_bwr_eol | 0x011d0 | ||
| vxge_vBIT(val, 32, 32) u64 umq_bwr_init_add | 0x011d8 | ||
| vxge_vBIT(val, 0, 64) u64 umq_bwr_init_byte | 0x011e0 | ||
| vxge_vBIT(val, 0, 32) u64 gendma_int | 0x011e8 | ||
| umqdmq_ir_init_notify | u64 | 0x011f0 | |
| dmq_init_notify | 0x011f8 | ||
| umq_init_notify | 0x01200 | ||
| unused01380[0x01380-0x01208] | |||
| tpa_cfg | u64 | 0x01380 | |
| unused01400[0x01400-0x01388] | |||
| tx_vp_reset_discarded_frms | u64 | 0x01400 | |
| vxge_vBIT(val, 48, 16) u8 unused01480[0x01480-0x01408] | |||
| fau_rpa_vcfg | u64 | 0x01480 | |
| unused014d0[0x014d0-0x01488] | |||
| dbg_stats_rx_mpa | u64 | 0x014d0 | |
| vxge_vBIT(val, 0, 16) #define VXGE_HW_DBG_STATS_RX_MPA_MRK_FAIL_FRMS(val) vxge_vBIT(val, 16, 16) #define VXGE_HW_DBG_STATS_RX_M | 0x014d8 | ||
| vxge_vBIT(val, 0, 16) #define VXGE_HW_DBG_STATS_RX_FAU_RX_VP_RESET_DISCARDED_FRMS(val) \ vxge_vBIT(val, 16, 16) #define VXGE_HW | |||
| fbmc_vp_rdy | u64 | 0x014f0 | |
| unused01e00[0x01e00-0x014f8] | |||
| vpath_pcipif_int_status | u64 | 0x01e00 | |
| vpath_pcipif_int_mask | 0x01e08 | ||
| unused01e20[0x01e20-0x01e10] | u8 | ||
| srpcim_msg_to_vpath_reg | u64 | 0x01e20 | |
| srpcim_msg_to_vpath_mask | 0x01e28 | ||
| srpcim_msg_to_vpath_alarm | u64 | 0x01e30 | |
| unused01ea0[0x01ea0-0x01e38] | u8 | ||
| vpath_to_srpcim_wmsg | u64 | 0x01ea0 | |
| vxge_vBIT(val, 0, 64) u64 vpath_to_srpcim_wmsg_trig | 0x01ea8 | ||
| unused02000[0x02000-0x01eb0] | |||
| vpath_general_int_status | u64 | 0x02000 | |
| vpath_general_int_mask | 0x02008 | ||
| vpath_ppif_int_status | 0x02010 | ||
| vpath_ppif_int_mask | 0x02018 | ||
| kdfcctl_errors_reg | u64 | 0x02020 | |
| kdfcctl_errors_mask | 0x02028 | ||
| kdfcctl_errors_alarm | u64 | 0x02030 | |
| unused02040[0x02040-0x02038] | u8 | ||
| general_errors_reg | u64 | 0x02040 | |
| general_errors_mask | 0x02048 | ||
| general_errors_alarm | u64 | 0x02050 | |
| pci_config_errors_reg | u64 | 0x02058 | |
| pci_config_errors_mask | 0x02060 | ||
| pci_config_errors_alarm | u64 | 0x02068 | |
| mrpcim_to_vpath_alarm_reg | u64 | 0x02070 | |
| mrpcim_to_vpath_alarm_mask | 0x02078 | ||
| mrpcim_to_vpath_alarm_alarm | u64 | 0x02080 | |
| srpcim_to_vpath_alarm_reg | u64 | 0x02088 | |
| vxge_vBIT(val, 0, 17) u64 srpcim_to_vpath_alarm_mask | 0x02090 | ||
| srpcim_to_vpath_alarm_alarm | u64 | 0x02098 | |
| unused02108[0x02108-0x020a0] | u8 | ||
| kdfcctl_status | u64 | 0x02108 | |
| vxge_vBIT(val, 0, 8) #define VXGE_HW_KDFCCTL_STATUS_KDFCCTL_FIFO1_PRES(val) vxge_vBIT(val, 8, 8) #define VXGE_HW_KDFCCTL_STATUS | 0x02110 | ||
| vxge_vBIT(val, 6, 2) u64 fifo0_status | 0x02118 | ||
| vxge_vBIT(val, 0, 12) u64 fifo1_status | 0x02120 | ||
| vxge_vBIT(val, 0, 12) u64 fifo2_status | 0x02128 | ||
| vxge_vBIT(val, 0, 12) u8 unused02158[0x02158-0x02130] | |||
| tgt_illegal_access | u64 | 0x02158 | |
| vxge_vBIT(val, 1, 7) u8 unused02200[0x02200-0x02160] | |||
| vpath_general_cfg1 | u64 | 0x02200 | |
| vxge_vBIT(val, 1, 3) #define VXGE_HW_VPATH_GENERAL_CFG1_DATA_BYTE_SWAPEN vxge_mBIT(7) #define VXGE_HW_VPATH_GENERAL_CFG1_DATA_F | 0x02208 | ||
| vxge_vBIT(val, 1, 3) u64 vpath_general_cfg3 | 0x02210 | ||
| unused02220[0x02220-0x02218] | |||
| kdfcctl_cfg0 | u64 | 0x02220 | |
| unused02268[0x02268-0x02228] | |||
| stats_cfg | u64 | 0x02268 | |
| vxge_vBIT(val, 0, 57) u64 interrupt_cfg0 | 0x02270 | ||
| vxge_vBIT(val, 1, 7) #define VXGE_HW_INTERRUPT_CFG0_GROUP0_MSIX_FOR_TXTI(val) vxge_vBIT(val, 9, 7) #define VXGE_HW_INTERRUPT_CF | |||
| interrupt_cfg2 | u64 | 0x02280 | |
| vxge_vBIT(val, 1, 7) u64 one_shot_vect0_en | 0x02288 | ||
| one_shot_vect1_en | 0x02290 | ||
| one_shot_vect2_en | 0x02298 | ||
| one_shot_vect3_en | 0x022a0 | ||
| unused022b0[0x022b0-0x022a8] | |||
| pci_config_access_cfg1 | u64 | 0x022b0 | |
| vxge_vBIT(val, 0, 12) #define VXGE_HW_PCI_CONFIG_ACCESS_CFG1_SEL_FUNC0 vxge_mBIT(15) u64 pci_config_access_cfg2 | 0x022b8 | ||
| pci_config_access_status | 0x022c0 | ||
| vxge_vBIT(val, 32, 32) u8 unused02300[0x02300-0x022c8] | |||
| vpath_debug_stats0 | u64 | 0x02300 | |
| vxge_vBIT(val, 0, 32) u64 vpath_debug_stats1 | 0x02308 | ||
| vxge_vBIT(val, 0, 32) u64 vpath_debug_stats2 | 0x02310 | ||
| vxge_vBIT(val, 0, 32) u64 vpath_debug_stats3 | 0x02318 | ||
| vxge_vBIT(val, 0, 64) u64 vpath_debug_stats4 | 0x02320 | ||
| vxge_vBIT(val, 0, 64) u64 vpath_debug_stats5 | 0x02328 | ||
| vxge_vBIT(val, 32, 32) u64 vpath_debug_stats6 | 0x02330 | ||
| vxge_vBIT(val, 32, 32) u64 vpath_genstats_count01 | 0x02338 | ||
| vxge_vBIT(val, 0, 32) #define VXGE_HW_VPATH_GENSTATS_COUNT01_PPIF_VPATH_GENSTATS_COUNT0(val) \ vxge_vBIT(val, 32, 32) u64 vpath | 0x02340 | ||
| vxge_vBIT(val, 0, 32) #define VXGE_HW_VPATH_GENSTATS_COUNT23_PPIF_VPATH_GENSTATS_COUNT2(val) \ vxge_vBIT(val, 32, 32) u64 vpath | 0x02348 | ||
| vxge_vBIT(val, 32, 32) u64 vpath_genstats_count5 | 0x02350 | ||
| vxge_vBIT(val, 32, 32) u8 unused02648[0x02648-0x02358] |
See Also
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