enum jme_iomap_regs
No. | 名称 | 属性 | 説明 |
---|---|---|---|
1 |
jme_iomap_regs | ||
JME_TXCS | JME_MAC | 0x00 | Transmit Control and Status | |
JME_TXDBA_LO | JME_MAC | 0x04 | Transmit Queue Desc Base Addr | |
JME_TXDBA_HI | JME_MAC | 0x08 | Transmit Queue Desc Base Addr | |
JME_TXQDC | JME_MAC | 0x0C | Transmit Queue Desc Count | |
JME_TXNDA | JME_MAC | 0x10 | Transmit Queue Next Desc Addr | |
JME_TXMCS | JME_MAC | 0x14 | Transmit MAC Control Status | |
JME_TXPFC | JME_MAC | 0x18 | Transmit Pause Frame Control | |
JME_TXTRHD | JME_MAC | 0x1C | Transmit Timer/Retry@Half-Dup | |
JME_RXCS | JME_MAC | 0x20 | Receive Control and Status | |
JME_RXDBA_LO | JME_MAC | 0x24 | Receive Queue Desc Base Addr | |
JME_RXDBA_HI | JME_MAC | 0x28 | Receive Queue Desc Base Addr | |
JME_RXQDC | JME_MAC | 0x2C | Receive Queue Desc Count | |
JME_RXNDA | JME_MAC | 0x30 | Receive Queue Next Desc Addr | |
JME_RXMCS | JME_MAC | 0x34 | Receive MAC Control Status | |
JME_RXUMA_LO | JME_MAC | 0x38 | Receive Unicast MAC Address | |
JME_RXUMA_HI | JME_MAC | 0x3C | Receive Unicast MAC Address | |
JME_RXMCHT_LO | JME_MAC | 0x40 | Recv Multicast Addr HashTable | |
JME_RXMCHT_HI | JME_MAC | 0x44 | Recv Multicast Addr HashTable | |
JME_WFODP | JME_MAC | 0x48 | Wakeup Frame Output Data Port | |
JME_WFOI | JME_MAC | 0x4C | Wakeup Frame Output Interface | |
JME_SMI | JME_MAC | 0x50 | Station Management Interface | |
JME_GHC | JME_MAC | 0x54 | Global Host Control | |
JME_PMCS | JME_MAC | 0x60 | Power Management Control/Stat | |
JME_PHY_CS | JME_PHY | 0x28 | PHY Ctrl and Status Register | |
JME_PHY_LINK | JME_PHY | 0x30 | PHY Link Status Register | |
JME_SMBCSR | JME_PHY | 0x40 | SMB Control and Status | |
JME_SMBINTF | JME_PHY | 0x44 | SMB Interface | |
JME_TMCSR | JME_MISC | 0x00 | Timer Control/Status Register | |
JME_GPREG0 | JME_MISC | 0x08 | General purpose REG-0 | |
JME_GPREG1 | JME_MISC | 0x0C | General purpose REG-1 | |
JME_IEVE | JME_MISC | 0x20 | Interrupt Event Status | |
JME_IREQ | JME_MISC | 0x24 | Intr Req Status(For Debug) | |
JME_IENS | JME_MISC | 0x28 | Intr Enable - Setting Port | |
JME_IENC | JME_MISC | 0x2C | Interrupt Enable - Clear Port | |
JME_PCCRX0 | JME_MISC | 0x30 | PCC Control for RX Queue 0 | |
JME_PCCTX | JME_MISC | 0x40 | PCC Control for TX Queues | |
JME_CHIPMODE | JME_MISC | 0x44 | Identify FPGA Version | |
JME_SHBA_HI | JME_MISC | 0x48 | Shadow Register Base HI | |
JME_SHBA_LO | JME_MISC | 0x4C | Shadow Register Base LO | |
JME_TIMER1 | JME_MISC | 0x70 | Timer1 | |
JME_TIMER2 | JME_MISC | 0x74 | Timer2 | |
JME_APMC | JME_MISC | 0x7C | Aggressive Power Mode Control | |
JME_PCCSRX0 | JME_MISC | 0x80 | PCC Status of RX0 |
目次 | ファイル一覧 | 関数一覧 | ネームスペース一覧 | クラス一覧 | #define一覧 | マクロ一覧 | 外部変数一覧 | 構造体一覧 | 共用体一覧 | 列挙体一覧 | Const一覧 | 索引 | サイドメニュー