#define一覧 VC2010

VisualCpp2010

No. 名称 値 ファイル名 説明
1
 FCS_LENFCS_LEN 4 ath5k_desc.c 　
2
 ERRFILEERRFILE ERRFILE_ath5k ath5k.h 　
3
 PCI_DEVICE_ID_ATHEROS_AR5210PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 ath5k.h AR5210
4
 PCI_DEVICE_ID_ATHEROS_AR5311PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 ath5k.h AR5311
5
 PCI_DEVICE_ID_ATHEROS_AR5211PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 ath5k.h AR5211
6
 PCI_DEVICE_ID_ATHEROS_AR5212PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 ath5k.h AR5212
7
 PCI_DEVICE_ID_3COM_3CRDAG675PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 ath5k.h 3CRDAG675 (Atheros AR5212)
8
 PCI_DEVICE_ID_3COM_2_3CRPAG175PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 ath5k.h 3CRPAG175 (Atheros AR5212)
9
 PCI_DEVICE_ID_ATHEROS_AR5210_APPCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 ath5k.h AR5210 (Early)
10
 PCI_DEVICE_ID_ATHEROS_AR5212_IBPCI_DEVICE_ID_ATHEROS_AR5212_IB 0x1014 ath5k.h AR5212 (IBM MiniPCI)
11
 PCI_DEVICE_ID_ATHEROS_AR5210_DEPCI_DEVICE_ID_ATHEROS_AR5210_DE 0x1107 ath5k.h AR5210 (no eeprom)
12
 PCI_DEVICE_ID_ATHEROS_AR5212_DEPCI_DEVICE_ID_ATHEROS_AR5212_DE 0x1113 ath5k.h AR5212 (no eeprom)
13
 PCI_DEVICE_ID_ATHEROS_AR5211_DEPCI_DEVICE_ID_ATHEROS_AR5211_DE 0x1112 ath5k.h AR5211 (no eeprom)
14
 PCI_DEVICE_ID_ATHEROS_AR5212_FPPCI_DEVICE_ID_ATHEROS_AR5212_FP 0xf013 ath5k.h AR5212 (emulation board)
15
 PCI_DEVICE_ID_ATHEROS_AR5211_LEPCI_DEVICE_ID_ATHEROS_AR5211_LE 0xff12 ath5k.h AR5211 (emulation board)
16
 PCI_DEVICE_ID_ATHEROS_AR5211_FPPCI_DEVICE_ID_ATHEROS_AR5211_FP 0xf11b ath5k.h AR5211 (emulation board)
17
 PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0052 ath5k.h AR5312 WMAC (AP31)
18
 PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0057 ath5k.h AR5312 WMAC (AP30-040)
19
 PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0058 ath5k.h AR5312 WMAC (AP43-030)
20
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0014 ath5k.h AR5212 compatible
21
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0015 ath5k.h AR5212 compatible
22
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0016 ath5k.h AR5212 compatible
23
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0017 ath5k.h AR5212 compatible
24
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0018 ath5k.h AR5212 compatible
25
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0019 ath5k.h AR5212 compatible
26
 PCI_DEVICE_ID_ATHEROS_AR2413PCI_DEVICE_ID_ATHEROS_AR2413 0x001a ath5k.h AR2413 (Griffin-lite)
27
 PCI_DEVICE_ID_ATHEROS_AR5413PCI_DEVICE_ID_ATHEROS_AR5413 0x001b ath5k.h AR5413 (Eagle)
28
 PCI_DEVICE_ID_ATHEROS_AR5424PCI_DEVICE_ID_ATHEROS_AR5424 0x001c ath5k.h AR5424 (Condor PCI-E)
29
 PCI_DEVICE_ID_ATHEROS_AR5416PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 ath5k.h AR5416
30
 PCI_DEVICE_ID_ATHEROS_AR5418PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 ath5k.h AR5418
31
 AR5K_INI_RFGAIN_5GHZAR5K_INI_RFGAIN_5GHZ 0 ath5k.h 　
32
 AR5K_INI_RFGAIN_2GHZAR5K_INI_RFGAIN_2GHZ 1 ath5k.h 　
33
 AR5K_INI_VAL_11AAR5K_INI_VAL_11A 0 ath5k.h 　
34
 AR5K_INI_VAL_11A_TURBOAR5K_INI_VAL_11A_TURBO 1 ath5k.h 　
35
 AR5K_INI_VAL_11BAR5K_INI_VAL_11B 2 ath5k.h 　
36
 AR5K_INI_VAL_11GAR5K_INI_VAL_11G 3 ath5k.h 　
37
 AR5K_INI_VAL_11G_TURBOAR5K_INI_VAL_11G_TURBO 4 ath5k.h 　
38
 AR5K_INI_VAL_XRAR5K_INI_VAL_XR 0 ath5k.h 　
39
 AR5K_INI_VAL_MAXAR5K_INI_VAL_MAX 5 ath5k.h 　
40
 IEEE80211_MAX_LENIEEE80211_MAX_LEN 2352 ath5k.h 　
41
 AR5K_TUNE_DMA_BEACON_RESPAR5K_TUNE_DMA_BEACON_RESP 2 ath5k.h 　
42
 AR5K_TUNE_SW_BEACON_RESPAR5K_TUNE_SW_BEACON_RESP 10 ath5k.h 　
43
 AR5K_TUNE_ADDITIONAL_SWBA_BACKOAR5K_TUNE_ADDITIONAL_SWBA_BACKO 0 ath5k.h 　
44
 AR5K_TUNE_RADAR_ALERTAR5K_TUNE_RADAR_ALERT 0 ath5k.h 　
45
 AR5K_TUNE_MIN_TX_FIFO_THRESAR5K_TUNE_MIN_TX_FIFO_THRES 1 ath5k.h 　
46
 AR5K_TUNE_MAX_TX_FIFO_THRESAR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) ath5k.h 　
47
 AR5K_TUNE_REGISTER_TIMEOUTAR5K_TUNE_REGISTER_TIMEOUT 20000 ath5k.h 　
48
 AR5K_TUNE_RSSI_THRESAR5K_TUNE_RSSI_THRES 129 ath5k.h 　
49
 AR5K_TUNE_BMISS_THRESAR5K_TUNE_BMISS_THRES 7 ath5k.h 　
50
 AR5K_TUNE_REGISTER_DWELL_TIMEAR5K_TUNE_REGISTER_DWELL_TIME 20000 ath5k.h 　
51
 AR5K_TUNE_BEACON_INTERVALAR5K_TUNE_BEACON_INTERVAL 100 ath5k.h 　
52
 AR5K_TUNE_AIFSAR5K_TUNE_AIFS 2 ath5k.h 　
53
 AR5K_TUNE_AIFS_11BAR5K_TUNE_AIFS_11B 2 ath5k.h 　
54
 AR5K_TUNE_AIFS_XRAR5K_TUNE_AIFS_XR 0 ath5k.h 　
55
 AR5K_TUNE_CWMINAR5K_TUNE_CWMIN 15 ath5k.h 　
56
 AR5K_TUNE_CWMIN_11BAR5K_TUNE_CWMIN_11B 31 ath5k.h 　
57
 AR5K_TUNE_CWMIN_XRAR5K_TUNE_CWMIN_XR 3 ath5k.h 　
58
 AR5K_TUNE_CWMAXAR5K_TUNE_CWMAX 1023 ath5k.h 　
59
 AR5K_TUNE_CWMAX_11BAR5K_TUNE_CWMAX_11B 1023 ath5k.h 　
60
 AR5K_TUNE_CWMAX_XRAR5K_TUNE_CWMAX_XR 7 ath5k.h 　
61
 AR5K_TUNE_NOISE_FLOORAR5K_TUNE_NOISE_FLOOR -72 ath5k.h 　
62
 AR5K_TUNE_MAX_TXPOWERAR5K_TUNE_MAX_TXPOWER 63 ath5k.h 　
63
 AR5K_TUNE_DEFAULT_TXPOWERAR5K_TUNE_DEFAULT_TXPOWER 25 ath5k.h 　
64
 AR5K_TUNE_TPC_TXPOWERAR5K_TUNE_TPC_TXPOWER 0 ath5k.h 　
65
 AR5K_TUNE_ANT_DIVERSITYAR5K_TUNE_ANT_DIVERSITY 1 ath5k.h 　
66
 AR5K_TUNE_HWTXTRIESAR5K_TUNE_HWTXTRIES 4 ath5k.h 　
67
 AR5K_INIT_CARR_SENSE_ENAR5K_INIT_CARR_SENSE_EN 1 ath5k.h 　
68
 AR5K_INIT_CFGAR5K_INIT_CFG ( \ AR5K_CFG_SWTD | AR5K_CFG_SWRD \ ) ath5k.h 　
69
 AR5K_INIT_CFGAR5K_INIT_CFG 0x00000000 ath5k.h 　
70
 AR5K_INIT_CYCRSSI_THR1AR5K_INIT_CYCRSSI_THR1 2 ath5k.h 　
71
 AR5K_INIT_TX_LATENCYAR5K_INIT_TX_LATENCY 502 ath5k.h 　
72
 AR5K_INIT_USECAR5K_INIT_USEC 39 ath5k.h 　
73
 AR5K_INIT_USEC_TURBOAR5K_INIT_USEC_TURBO 79 ath5k.h 　
74
 AR5K_INIT_USEC_32AR5K_INIT_USEC_32 31 ath5k.h 　
75
 AR5K_INIT_SLOT_TIMEAR5K_INIT_SLOT_TIME 396 ath5k.h 　
76
 AR5K_INIT_SLOT_TIME_TURBOAR5K_INIT_SLOT_TIME_TURBO 480 ath5k.h 　
77
 AR5K_INIT_ACK_CTS_TIMEOUTAR5K_INIT_ACK_CTS_TIMEOUT 1024 ath5k.h 　
78
 AR5K_INIT_ACK_CTS_TIMEOUT_TURBOAR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 ath5k.h 　
79
 AR5K_INIT_PROG_IFSAR5K_INIT_PROG_IFS 920 ath5k.h 　
80
 AR5K_INIT_PROG_IFS_TURBOAR5K_INIT_PROG_IFS_TURBO 960 ath5k.h 　
81
 AR5K_INIT_EIFSAR5K_INIT_EIFS 3440 ath5k.h 　
82
 AR5K_INIT_EIFS_TURBOAR5K_INIT_EIFS_TURBO 6880 ath5k.h 　
83
 AR5K_INIT_SIFSAR5K_INIT_SIFS 560 ath5k.h 　
84
 AR5K_INIT_SIFS_TURBOAR5K_INIT_SIFS_TURBO 480 ath5k.h 　
85
 AR5K_INIT_SH_RETRYAR5K_INIT_SH_RETRY 10 ath5k.h 　
86
 AR5K_INIT_LG_RETRYAR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY ath5k.h 　
87
 AR5K_INIT_SSH_RETRYAR5K_INIT_SSH_RETRY 32 ath5k.h 　
88
 AR5K_INIT_SLG_RETRYAR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY ath5k.h 　
89
 AR5K_INIT_TX_RETRYAR5K_INIT_TX_RETRY 10 ath5k.h 　
90
 AR5K_INIT_TRANSMIT_LATENCYAR5K_INIT_TRANSMIT_LATENCY ( \ (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ (AR5K_INIT_USEC) \ ) ath5k.h 　
91
 AR5K_INIT_TRANSMIT_LATENCY_TURBAR5K_INIT_TRANSMIT_LATENCY_TURB ( \ (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ (AR5K_INIT_USEC_TURBO) \ ) ath5k.h 　
92
 AR5K_INIT_PROTO_TIME_CNTRLAR5K_INIT_PROTO_TIME_CNTRL ( \ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ (AR5K_INIT_PROG_IFS) \ ) ath5k.h 　
93
 AR5K_INIT_PROTO_TIME_CNTRL_TURBAR5K_INIT_PROTO_TIME_CNTRL_TURB ( \ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ (AR5K_INIT_PROG_IFS_TURBO) \ ) ath5k.h 　
94
 AR5K_TXQ_USEDEFAULTAR5K_TXQ_USEDEFAULT ((u32) -1) ath5k.h 　
95
 AR5K_SREV_UNKNOWNAR5K_SREV_UNKNOWN 0xffff ath5k.h 　
96
 AR5K_SREV_AR5210AR5K_SREV_AR5210 0x00 ath5k.h Crete
97
 AR5K_SREV_AR5311AR5K_SREV_AR5311 0x10 ath5k.h Maui 1
98
 AR5K_SREV_AR5311AAR5K_SREV_AR5311A 0x20 ath5k.h Maui 2
99
 AR5K_SREV_AR5311BAR5K_SREV_AR5311B 0x30 ath5k.h Spirit
100
 AR5K_SREV_AR5211AR5K_SREV_AR5211 0x40 ath5k.h Oahu
101
 AR5K_SREV_AR5212AR5K_SREV_AR5212 0x50 ath5k.h Venice
102
 AR5K_SREV_AR5213AR5K_SREV_AR5213 0x55 ath5k.h ???
103
 AR5K_SREV_AR5213AAR5K_SREV_AR5213A 0x59 ath5k.h Hainan
104
 AR5K_SREV_AR2413AR5K_SREV_AR2413 0x78 ath5k.h Griffin lite
105
 AR5K_SREV_AR2414AR5K_SREV_AR2414 0x70 ath5k.h Griffin
106
 AR5K_SREV_AR5424AR5K_SREV_AR5424 0x90 ath5k.h Condor
107
 AR5K_SREV_AR5413AR5K_SREV_AR5413 0xa4 ath5k.h Eagle lite
108
 AR5K_SREV_AR5414AR5K_SREV_AR5414 0xa0 ath5k.h Eagle
109
 AR5K_SREV_AR2415AR5K_SREV_AR2415 0xb0 ath5k.h Talon
110
 AR5K_SREV_AR5416AR5K_SREV_AR5416 0xc0 ath5k.h PCI-E
111
 AR5K_SREV_AR5418AR5K_SREV_AR5418 0xca ath5k.h PCI-E
112
 AR5K_SREV_AR2425AR5K_SREV_AR2425 0xe0 ath5k.h Swan
113
 AR5K_SREV_AR2417AR5K_SREV_AR2417 0xf0 ath5k.h Nala
114
 AR5K_SREV_RAD_5110AR5K_SREV_RAD_5110 0x00 ath5k.h 　
115
 AR5K_SREV_RAD_5111AR5K_SREV_RAD_5111 0x10 ath5k.h 　
116
 AR5K_SREV_RAD_5111AAR5K_SREV_RAD_5111A 0x15 ath5k.h 　
117
 AR5K_SREV_RAD_2111AR5K_SREV_RAD_2111 0x20 ath5k.h 　
118
 AR5K_SREV_RAD_5112AR5K_SREV_RAD_5112 0x30 ath5k.h 　
119
 AR5K_SREV_RAD_5112AAR5K_SREV_RAD_5112A 0x35 ath5k.h 　
120
 AR5K_SREV_RAD_5112BAR5K_SREV_RAD_5112B 0x36 ath5k.h 　
121
 AR5K_SREV_RAD_2112AR5K_SREV_RAD_2112 0x40 ath5k.h 　
122
 AR5K_SREV_RAD_2112AAR5K_SREV_RAD_2112A 0x45 ath5k.h 　
123
 AR5K_SREV_RAD_2112BAR5K_SREV_RAD_2112B 0x46 ath5k.h 　
124
 AR5K_SREV_RAD_2413AR5K_SREV_RAD_2413 0x50 ath5k.h 　
125
 AR5K_SREV_RAD_5413AR5K_SREV_RAD_5413 0x60 ath5k.h 　
126
 AR5K_SREV_RAD_2316AR5K_SREV_RAD_2316 0x70 ath5k.h Cobra SoC
127
 AR5K_SREV_RAD_2317AR5K_SREV_RAD_2317 0x80 ath5k.h 　
128
 AR5K_SREV_RAD_5424AR5K_SREV_RAD_5424 0xa0 ath5k.h Mostly same as 5413
129
 AR5K_SREV_RAD_2425AR5K_SREV_RAD_2425 0xa2 ath5k.h 　
130
 AR5K_SREV_RAD_5133AR5K_SREV_RAD_5133 0xc0 ath5k.h 　
131
 AR5K_SREV_PHY_5211AR5K_SREV_PHY_5211 0x30 ath5k.h 　
132
 AR5K_SREV_PHY_5212AR5K_SREV_PHY_5212 0x41 ath5k.h 　
133
 AR5K_SREV_PHY_5212AAR5K_SREV_PHY_5212A 0x42 ath5k.h 　
134
 AR5K_SREV_PHY_5212BAR5K_SREV_PHY_5212B 0x43 ath5k.h 　
135
 AR5K_SREV_PHY_2413AR5K_SREV_PHY_2413 0x45 ath5k.h 　
136
 AR5K_SREV_PHY_5413AR5K_SREV_PHY_5413 0x61 ath5k.h 　
137
 AR5K_SREV_PHY_2425AR5K_SREV_PHY_2425 0x70 ath5k.h 　
138
 MODULATION_XRMODULATION_XR 0x00000200 ath5k.h 　
139
 MODULATION_TURBOMODULATION_TURBO 0x00000080 ath5k.h 　
140
 AR5K_TXSTAT_ALTRATEAR5K_TXSTAT_ALTRATE 0x80 ath5k.h 　
141
 AR5K_TXERR_XRETRYAR5K_TXERR_XRETRY 0x01 ath5k.h 　
142
 AR5K_TXERR_FILTAR5K_TXERR_FILT 0x02 ath5k.h 　
143
 AR5K_TXERR_FIFOAR5K_TXERR_FIFO 0x04 ath5k.h 　
144
 AR5K_TXQ_FLAG_TXOKINT_ENABLEAR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 ath5k.h Enable TXOK interrupt
145
 AR5K_TXQ_FLAG_TXERRINT_ENABLEAR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 ath5k.h Enable TXERR interrupt
146
 AR5K_TXQ_FLAG_TXEOLINT_ENABLEAR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 ath5k.h Enable TXEOL interrupt -not used-
147
 AR5K_TXQ_FLAG_TXDESCINT_ENABLEAR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 ath5k.h Enable TXDESC interrupt -not used-
148
 AR5K_TXQ_FLAG_TXURNINT_ENABLEAR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 ath5k.h Enable TXURN interrupt
149
 AR5K_TXQ_FLAG_CBRORNINT_ENABLEAR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 ath5k.h Enable CBRORN interrupt
150
 AR5K_TXQ_FLAG_CBRURNINT_ENABLEAR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 ath5k.h Enable CBRURN interrupt
151
 AR5K_TXQ_FLAG_QTRIGINT_ENABLEAR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 ath5k.h Enable QTRIG interrupt
152
 AR5K_TXQ_FLAG_TXNOFRMINT_ENABLEAR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 ath5k.h Enable TXNOFRM interrupt
153
 AR5K_TXQ_FLAG_BACKOFF_DISABLEAR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 ath5k.h Disable random post-backoff
154
 AR5K_TXQ_FLAG_RDYTIME_EXP_POLICAR5K_TXQ_FLAG_RDYTIME_EXP_POLIC 0x0300 ath5k.h Enable ready time expiry policy (?)
155
 AR5K_TXQ_FLAG_FRAG_BURST_BACKOFAR5K_TXQ_FLAG_FRAG_BURST_BACKOF 0x0800 ath5k.h Enable backoff while bursting
156
 AR5K_TXQ_FLAG_POST_FR_BKOFF_DISAR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 ath5k.h Disable backoff while bursting
157
 AR5K_TXQ_FLAG_COMPRESSION_ENABLAR5K_TXQ_FLAG_COMPRESSION_ENABL 0x2000 ath5k.h Enable hw compression -not implemented-
158
 AR5K_RXERR_CRCAR5K_RXERR_CRC 0x01 ath5k.h 　
159
 AR5K_RXERR_PHYAR5K_RXERR_PHY 0x02 ath5k.h 　
160
 AR5K_RXERR_FIFOAR5K_RXERR_FIFO 0x04 ath5k.h 　
161
 AR5K_RXERR_DECRYPTAR5K_RXERR_DECRYPT 0x08 ath5k.h 　
162
 AR5K_RXERR_MICAR5K_RXERR_MIC 0x10 ath5k.h 　
163
 AR5K_RXKEYIX_INVALIDAR5K_RXKEYIX_INVALID ((u8) - 1) ath5k.h 　
164
 AR5K_TXKEYIX_INVALIDAR5K_TXKEYIX_INVALID ((u32) - 1) ath5k.h 　
165
 AR5K_SLOT_TIME_9AR5K_SLOT_TIME_9 396 ath5k.h 　
166
 AR5K_SLOT_TIME_20AR5K_SLOT_TIME_20 880 ath5k.h 　
167
 AR5K_SLOT_TIME_MAXAR5K_SLOT_TIME_MAX 0xffff ath5k.h 　
168
 CHANNEL_CW_INTCHANNEL_CW_INT 0x0008 ath5k.h Contention Window interference detected
169
 CHANNEL_TURBOCHANNEL_TURBO 0x0010 ath5k.h Turbo Channel
170
 CHANNEL_CCKCHANNEL_CCK 0x0020 ath5k.h CCK channel
171
 CHANNEL_OFDMCHANNEL_OFDM 0x0040 ath5k.h OFDM channel
172
 CHANNEL_2GHZCHANNEL_2GHZ 0x0080 ath5k.h 2GHz channel.
173
 CHANNEL_5GHZCHANNEL_5GHZ 0x0100 ath5k.h 5GHz channel
174
 CHANNEL_PASSIVECHANNEL_PASSIVE 0x0200 ath5k.h Only passive scan allowed
175
 CHANNEL_DYNCHANNEL_DYN 0x0400 ath5k.h Dynamic CCK-OFDM channel (for g operation)
176
 CHANNEL_XRCHANNEL_XR 0x0800 ath5k.h XR channel
177
 CHANNEL_ACHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) ath5k.h 　
178
 CHANNEL_BCHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) ath5k.h 　
179
 CHANNEL_GCHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) ath5k.h 　
180
 CHANNEL_TCHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) ath5k.h 　
181
 CHANNEL_TGCHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) ath5k.h 　
182
 CHANNEL_108ACHANNEL_108A CHANNEL_T ath5k.h 　
183
 CHANNEL_108GCHANNEL_108G CHANNEL_TG ath5k.h 　
184
 CHANNEL_XCHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) ath5k.h 　
185
 CHANNEL_ALLCHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ CHANNEL_TURBO) ath5k.h 　
186
 CHANNEL_ALL_NOTURBOCHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) ath5k.h 　
187
 CHANNEL_MODESCHANNEL_MODES CHANNEL_ALL ath5k.h 　
188
 AR5K_MAX_RATESAR5K_MAX_RATES 32 ath5k.h 　
189
 ATH5K_RATE_CODE_1MATH5K_RATE_CODE_1M 0x1B ath5k.h 　
190
 ATH5K_RATE_CODE_2MATH5K_RATE_CODE_2M 0x1A ath5k.h 　
191
 ATH5K_RATE_CODE_5_5MATH5K_RATE_CODE_5_5M 0x19 ath5k.h 　
192
 ATH5K_RATE_CODE_11MATH5K_RATE_CODE_11M 0x18 ath5k.h 　
193
 ATH5K_RATE_CODE_6MATH5K_RATE_CODE_6M 0x0B ath5k.h 　
194
 ATH5K_RATE_CODE_9MATH5K_RATE_CODE_9M 0x0F ath5k.h 　
195
 ATH5K_RATE_CODE_12MATH5K_RATE_CODE_12M 0x0A ath5k.h 　
196
 ATH5K_RATE_CODE_18MATH5K_RATE_CODE_18M 0x0E ath5k.h 　
197
 ATH5K_RATE_CODE_24MATH5K_RATE_CODE_24M 0x09 ath5k.h 　
198
 ATH5K_RATE_CODE_36MATH5K_RATE_CODE_36M 0x0D ath5k.h 　
199
 ATH5K_RATE_CODE_48MATH5K_RATE_CODE_48M 0x08 ath5k.h 　
200
 ATH5K_RATE_CODE_54MATH5K_RATE_CODE_54M 0x0C ath5k.h 　
201
 ATH5K_RATE_CODE_XR_500KATH5K_RATE_CODE_XR_500K 0x07 ath5k.h 　
202
 ATH5K_RATE_CODE_XR_1MATH5K_RATE_CODE_XR_1M 0x02 ath5k.h 　
203
 ATH5K_RATE_CODE_XR_2MATH5K_RATE_CODE_XR_2M 0x06 ath5k.h 　
204
 ATH5K_RATE_CODE_XR_3MATH5K_RATE_CODE_XR_3M 0x01 ath5k.h 　
205
 AR5K_SET_SHORT_PREAMBLEAR5K_SET_SHORT_PREAMBLE 0x04 ath5k.h 　
206
 AR5K_KEYCACHE_SIZEAR5K_KEYCACHE_SIZE 8 ath5k.h 　
207
 AR5K_RSSI_EP_MULTIPLIERAR5K_RSSI_EP_MULTIPLIER (1<<7) ath5k.h 　
208
 AR5K_SOFTLED_PINAR5K_SOFTLED_PIN 0 ath5k.h 　
209
 AR5K_SOFTLED_ONAR5K_SOFTLED_ON 0 ath5k.h 　
210
 AR5K_SOFTLED_OFFAR5K_SOFTLED_OFF 1 ath5k.h 　
211
 AR5K_MAX_GPIOAR5K_MAX_GPIO 10 ath5k.h 　
212
 AR5K_MAX_RF_BANKSAR5K_MAX_RF_BANKS 8 ath5k.h 　
213
 ATH_RXBUFATH_RXBUF 16 base.h number of RX buffers
214
 ATH_TXBUFATH_TXBUF 16 base.h number of TX buffers
215
 ATH_CHAN_MAXATH_CHAN_MAX (26+26+26+200+200) base.h 　
216
 ATH_CHAN_MAXATH_CHAN_MAX (14+14+14+252+20) base.h 　
217
 AR5K_DESC_RX_CTL0AR5K_DESC_RX_CTL0 0x00000000 desc.h 　
218
 AR5K_DESC_RX_CTL1_BUF_LENAR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff desc.h 　
219
 AR5K_DESC_RX_CTL1_INTREQAR5K_DESC_RX_CTL1_INTREQ 0x00002000 desc.h 　
220
 AR5K_5210_RX_DESC_STATUS0_DATA_AR5K_5210_RX_DESC_STATUS0_DATA_ 0x00000fff desc.h 　
221
 AR5K_5210_RX_DESC_STATUS0_MOREAR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 desc.h 　
222
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x00078000 desc.h 　
223
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 15 desc.h 　
224
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x07f80000 desc.h 　
225
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 19 desc.h 　
226
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x38000000 desc.h 　
227
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 27 desc.h 　
228
 AR5K_5210_RX_DESC_STATUS1_DONEAR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 desc.h 　
229
 AR5K_5210_RX_DESC_STATUS1_FRAMEAR5K_5210_RX_DESC_STATUS1_FRAME 0x00000002 desc.h 　
230
 AR5K_5210_RX_DESC_STATUS1_CRC_EAR5K_5210_RX_DESC_STATUS1_CRC_E 0x00000004 desc.h 　
231
 AR5K_5210_RX_DESC_STATUS1_FIFO_AR5K_5210_RX_DESC_STATUS1_FIFO_ 0x00000008 desc.h 　
232
 AR5K_5210_RX_DESC_STATUS1_DECRYAR5K_5210_RX_DESC_STATUS1_DECRY 0x00000010 desc.h 　
233
 AR5K_5210_RX_DESC_STATUS1_PHY_EAR5K_5210_RX_DESC_STATUS1_PHY_E 0x000000e0 desc.h 　
234
 AR5K_5210_RX_DESC_STATUS1_PHY_EAR5K_5210_RX_DESC_STATUS1_PHY_E 5 desc.h 　
235
 AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 0x00000100 desc.h 　
236
 AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 0x00007e00 desc.h 　
237
 AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 9 desc.h 　
238
 AR5K_5210_RX_DESC_STATUS1_RECEIAR5K_5210_RX_DESC_STATUS1_RECEI 0x0fff8000 desc.h 　
239
 AR5K_5210_RX_DESC_STATUS1_RECEIAR5K_5210_RX_DESC_STATUS1_RECEI 15 desc.h 　
240
 AR5K_5210_RX_DESC_STATUS1_KEY_CAR5K_5210_RX_DESC_STATUS1_KEY_C 0x10000000 desc.h 　
241
 AR5K_5212_RX_DESC_STATUS0_DATA_AR5K_5212_RX_DESC_STATUS0_DATA_ 0x00000fff desc.h 　
242
 AR5K_5212_RX_DESC_STATUS0_MOREAR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 desc.h 　
243
 AR5K_5212_RX_DESC_STATUS0_DECOMAR5K_5212_RX_DESC_STATUS0_DECOM 0x00002000 desc.h 　
244
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0x000f8000 desc.h 　
245
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 15 desc.h 　
246
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0x0ff00000 desc.h 　
247
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 20 desc.h 　
248
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0xf0000000 desc.h 　
249
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 28 desc.h 　
250
 AR5K_5212_RX_DESC_STATUS1_DONEAR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 desc.h 　
251
 AR5K_5212_RX_DESC_STATUS1_FRAMEAR5K_5212_RX_DESC_STATUS1_FRAME 0x00000002 desc.h 　
252
 AR5K_5212_RX_DESC_STATUS1_CRC_EAR5K_5212_RX_DESC_STATUS1_CRC_E 0x00000004 desc.h 　
253
 AR5K_5212_RX_DESC_STATUS1_DECRYAR5K_5212_RX_DESC_STATUS1_DECRY 0x00000008 desc.h 　
254
 AR5K_5212_RX_DESC_STATUS1_PHY_EAR5K_5212_RX_DESC_STATUS1_PHY_E 0x00000010 desc.h 　
255
 AR5K_5212_RX_DESC_STATUS1_MIC_EAR5K_5212_RX_DESC_STATUS1_MIC_E 0x00000020 desc.h 　
256
 AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 0x00000100 desc.h 　
257
 AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 0x0000fe00 desc.h 　
258
 AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 9 desc.h 　
259
 AR5K_5212_RX_DESC_STATUS1_RECEIAR5K_5212_RX_DESC_STATUS1_RECEI 0x7fff0000 desc.h 　
260
 AR5K_5212_RX_DESC_STATUS1_RECEIAR5K_5212_RX_DESC_STATUS1_RECEI 16 desc.h 　
261
 AR5K_5212_RX_DESC_STATUS1_KEY_CAR5K_5212_RX_DESC_STATUS1_KEY_C 0x80000000 desc.h 　
262
 AR5K_RX_DESC_ERROR0AR5K_RX_DESC_ERROR0 0x00000000 desc.h 　
263
 AR5K_RX_DESC_ERROR1_PHY_ERROR_CAR5K_RX_DESC_ERROR1_PHY_ERROR_C 0x0000ff00 desc.h 　
264
 AR5K_RX_DESC_ERROR1_PHY_ERROR_CAR5K_RX_DESC_ERROR1_PHY_ERROR_C 8 desc.h 　
265
 AR5K_DESC_RX_PHY_ERROR_NONEAR5K_DESC_RX_PHY_ERROR_NONE 0x00 desc.h 　
266
 AR5K_DESC_RX_PHY_ERROR_TIMINGAR5K_DESC_RX_PHY_ERROR_TIMING 0x20 desc.h 　
267
 AR5K_DESC_RX_PHY_ERROR_PARITYAR5K_DESC_RX_PHY_ERROR_PARITY 0x40 desc.h 　
268
 AR5K_DESC_RX_PHY_ERROR_RATEAR5K_DESC_RX_PHY_ERROR_RATE 0x60 desc.h 　
269
 AR5K_DESC_RX_PHY_ERROR_LENGTHAR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 desc.h 　
270
 AR5K_DESC_RX_PHY_ERROR_64QAMAR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 desc.h 　
271
 AR5K_DESC_RX_PHY_ERROR_SERVICEAR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 desc.h 　
272
 AR5K_DESC_RX_PHY_ERROR_TRANSMITAR5K_DESC_RX_PHY_ERROR_TRANSMIT 0xe0 desc.h 　
273
 AR5K_2W_TX_DESC_CTL0_FRAME_LENAR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff desc.h 　
274
 AR5K_2W_TX_DESC_CTL0_HEADER_LENAR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 desc.h [5210 ?]
275
 AR5K_2W_TX_DESC_CTL0_HEADER_LENAR5K_2W_TX_DESC_CTL0_HEADER_LEN 12 desc.h 　
276
 AR5K_2W_TX_DESC_CTL0_XMIT_RATEAR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 desc.h 　
277
 AR5K_2W_TX_DESC_CTL0_XMIT_RATE_AR5K_2W_TX_DESC_CTL0_XMIT_RATE_ 18 desc.h 　
278
 AR5K_2W_TX_DESC_CTL0_RTSENAAR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 desc.h 　
279
 AR5K_2W_TX_DESC_CTL0_CLRDMASKAR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 desc.h 　
280
 AR5K_2W_TX_DESC_CTL0_LONG_PACKEAR5K_2W_TX_DESC_CTL0_LONG_PACKE 0x00800000 desc.h [5210]
281
 AR5K_2W_TX_DESC_CTL0_VEOLAR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 desc.h [5211]
282
 AR5K_2W_TX_DESC_CTL0_FRAME_TYPEAR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 desc.h [5210]
283
 AR5K_2W_TX_DESC_CTL0_FRAME_TYPEAR5K_2W_TX_DESC_CTL0_FRAME_TYPE 26 desc.h 　
284
 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 0x02000000 desc.h 　
285
 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 0x1e000000 desc.h 　
286
 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X (ah->ah_version == AR5K_AR5210 ? \ AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) desc.h 　
287
 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 25 desc.h 　
288
 AR5K_2W_TX_DESC_CTL0_INTREQAR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 desc.h 　
289
 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEAR5K_2W_TX_DESC_CTL0_ENCRYPT_KE 0x40000000 desc.h 　
290
 AR5K_2W_TX_DESC_CTL1_BUF_LENAR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff desc.h 　
291
 AR5K_2W_TX_DESC_CTL1_MOREAR5K_2W_TX_DESC_CTL1_MORE 0x00001000 desc.h 　
292
 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 0x0007e000 desc.h 　
293
 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 0x000fe000 desc.h 　
294
 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE (ah->ah_version == AR5K_AR5210 ? \ AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_52 desc.h 　
295
 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 13 desc.h 　
296
 AR5K_2W_TX_DESC_CTL1_FRAME_TYPEAR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 desc.h [5211]
297
 AR5K_2W_TX_DESC_CTL1_FRAME_TYPEAR5K_2W_TX_DESC_CTL1_FRAME_TYPE 20 desc.h 　
298
 AR5K_2W_TX_DESC_CTL1_NOACKAR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 desc.h [5211]
299
 AR5K_2W_TX_DESC_CTL1_RTS_DURATIAR5K_2W_TX_DESC_CTL1_RTS_DURATI 0xfff80000 desc.h [5210 ?]
300
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x00 desc.h 　
301
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x04 desc.h 　
302
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x08 desc.h 　
303
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x0c desc.h 　
304
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x10 desc.h 　
305
 AR5K_DESC_TX_STATUS0_FRAME_XMITAR5K_DESC_TX_STATUS0_FRAME_XMIT 0x00000001 desc.h 　
306
 AR5K_DESC_TX_STATUS0_EXCESSIVE_AR5K_DESC_TX_STATUS0_EXCESSIVE_ 0x00000002 desc.h 　
307
 AR5K_DESC_TX_STATUS0_FIFO_UNDERAR5K_DESC_TX_STATUS0_FIFO_UNDER 0x00000004 desc.h 　
308
 AR5K_DESC_TX_STATUS0_FILTEREDAR5K_DESC_TX_STATUS0_FILTERED 0x00000008 desc.h 　
309
 AR5K_DESC_TX_STATUS0_SHORT_RETRAR5K_DESC_TX_STATUS0_SHORT_RETR 0x000000f0 desc.h 　
310
 AR5K_DESC_TX_STATUS0_SHORT_RETRAR5K_DESC_TX_STATUS0_SHORT_RETR 4 desc.h 　
311
 AR5K_DESC_TX_STATUS0_LONG_RETRYAR5K_DESC_TX_STATUS0_LONG_RETRY 0x00000f00 desc.h 　
312
 AR5K_DESC_TX_STATUS0_LONG_RETRYAR5K_DESC_TX_STATUS0_LONG_RETRY 8 desc.h 　
313
 AR5K_DESC_TX_STATUS0_VIRT_COLL_AR5K_DESC_TX_STATUS0_VIRT_COLL_ 0x0000f000 desc.h 　
314
 AR5K_DESC_TX_STATUS0_VIRT_COLL_AR5K_DESC_TX_STATUS0_VIRT_COLL_ 12 desc.h 　
315
 AR5K_DESC_TX_STATUS0_SEND_TIMESAR5K_DESC_TX_STATUS0_SEND_TIMES 0xffff0000 desc.h 　
316
 AR5K_DESC_TX_STATUS0_SEND_TIMESAR5K_DESC_TX_STATUS0_SEND_TIMES 16 desc.h 　
317
 AR5K_DESC_TX_STATUS1_DONEAR5K_DESC_TX_STATUS1_DONE 0x00000001 desc.h 　
318
 AR5K_DESC_TX_STATUS1_SEQ_NUMAR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe desc.h 　
319
 AR5K_DESC_TX_STATUS1_SEQ_NUM_SAR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 desc.h 　
320
 AR5K_DESC_TX_STATUS1_ACK_SIG_STAR5K_DESC_TX_STATUS1_ACK_SIG_ST 0x001fe000 desc.h 　
321
 AR5K_DESC_TX_STATUS1_ACK_SIG_STAR5K_DESC_TX_STATUS1_ACK_SIG_ST 13 desc.h 　
322
 AR5K_DESC_TX_STATUS1_FINAL_TS_IAR5K_DESC_TX_STATUS1_FINAL_TS_I 0x00600000 desc.h 　
323
 AR5K_DESC_TX_STATUS1_FINAL_TS_IAR5K_DESC_TX_STATUS1_FINAL_TS_I 21 desc.h 　
324
 AR5K_DESC_TX_STATUS1_COMP_SUCCEAR5K_DESC_TX_STATUS1_COMP_SUCCE 0x00800000 desc.h 　
325
 AR5K_DESC_TX_STATUS1_XMIT_ANTENAR5K_DESC_TX_STATUS1_XMIT_ANTEN 0x01000000 desc.h 　
326
 AR5K_RXDESC_INTREQAR5K_RXDESC_INTREQ 0x0020 desc.h 　
327
 AR5K_TXDESC_CLRDMASKAR5K_TXDESC_CLRDMASK 0x0001 desc.h 　
328
 AR5K_TXDESC_NOACKAR5K_TXDESC_NOACK 0x0002 desc.h [5211+]
329
 AR5K_TXDESC_RTSENAAR5K_TXDESC_RTSENA 0x0004 desc.h 　
330
 AR5K_TXDESC_CTSENAAR5K_TXDESC_CTSENA 0x0008 desc.h 　
331
 AR5K_TXDESC_INTREQAR5K_TXDESC_INTREQ 0x0010 desc.h 　
332
 AR5K_TXDESC_VEOLAR5K_TXDESC_VEOL 0x0020 desc.h [5211+]
333
 AR5K_EEPROM_MAGICAR5K_EEPROM_MAGIC 0x003d eeprom.h EEPROM Magic number
334
 AR5K_EEPROM_MAGIC_VALUEAR5K_EEPROM_MAGIC_VALUE 0x5aa5 eeprom.h Default - found on EEPROM
335
 AR5K_EEPROM_MAGIC_5212AR5K_EEPROM_MAGIC_5212 0x0000145c eeprom.h 5212
336
 AR5K_EEPROM_MAGIC_5211AR5K_EEPROM_MAGIC_5211 0x0000145b eeprom.h 5211
337
 AR5K_EEPROM_MAGIC_5210AR5K_EEPROM_MAGIC_5210 0x0000145a eeprom.h 5210
338
 AR5K_EEPROM_IS_HB63AR5K_EEPROM_IS_HB63 0x000b eeprom.h Talon detect
339
 AR5K_EEPROM_RFKILLAR5K_EEPROM_RFKILL 0x0f eeprom.h 　
340
 AR5K_EEPROM_RFKILL_GPIO_SELAR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c eeprom.h 　
341
 AR5K_EEPROM_RFKILL_GPIO_SEL_SAR5K_EEPROM_RFKILL_GPIO_SEL_S 2 eeprom.h 　
342
 AR5K_EEPROM_RFKILL_POLARITYAR5K_EEPROM_RFKILL_POLARITY 0x00000002 eeprom.h 　
343
 AR5K_EEPROM_RFKILL_POLARITY_SAR5K_EEPROM_RFKILL_POLARITY_S 1 eeprom.h 　
344
 AR5K_EEPROM_REG_DOMAINAR5K_EEPROM_REG_DOMAIN 0x00bf eeprom.h EEPROM regdom
345
 AR5K_EEPROM_CHECKSUMAR5K_EEPROM_CHECKSUM 0x00c0 eeprom.h EEPROM checksum
346
 AR5K_EEPROM_INFO_BASEAR5K_EEPROM_INFO_BASE 0x00c0 eeprom.h EEPROM header
347
 AR5K_EEPROM_INFO_MAXAR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) eeprom.h 　
348
 AR5K_EEPROM_INFO_CKSUMAR5K_EEPROM_INFO_CKSUM 0xffff eeprom.h 　
349
 AR5K_EEPROM_VERSIONAR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) eeprom.h EEPROM Version
350
 AR5K_EEPROM_VERSION_3_0AR5K_EEPROM_VERSION_3_0 0x3000 eeprom.h No idea what's going on before this version
351
 AR5K_EEPROM_VERSION_3_1AR5K_EEPROM_VERSION_3_1 0x3001 eeprom.h ob/db values for 2Ghz (ar5211_rfregs)
352
 AR5K_EEPROM_VERSION_3_2AR5K_EEPROM_VERSION_3_2 0x3002 eeprom.h different frequency representation (eeprom_bin2freq)
353
 AR5K_EEPROM_VERSION_3_3AR5K_EEPROM_VERSION_3_3 0x3003 eeprom.h offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes)
354
 AR5K_EEPROM_VERSION_3_4AR5K_EEPROM_VERSION_3_4 0x3004 eeprom.h has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes)
355
 AR5K_EEPROM_VERSION_4_0AR5K_EEPROM_VERSION_4_0 0x4000 eeprom.h has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init)
356
 AR5K_EEPROM_VERSION_4_1AR5K_EEPROM_VERSION_4_1 0x4001 eeprom.h has ee_margin_tx_rx (eeprom_init)
357
 AR5K_EEPROM_VERSION_4_2AR5K_EEPROM_VERSION_4_2 0x4002 eeprom.h has ee_cck_ofdm_gain_delta (eeprom_init)
358
 AR5K_EEPROM_VERSION_4_3AR5K_EEPROM_VERSION_4_3 0x4003 eeprom.h power calibration changes
359
 AR5K_EEPROM_VERSION_4_4AR5K_EEPROM_VERSION_4_4 0x4004 eeprom.h 　
360
 AR5K_EEPROM_VERSION_4_5AR5K_EEPROM_VERSION_4_5 0x4005 eeprom.h 　
361
 AR5K_EEPROM_VERSION_4_6AR5K_EEPROM_VERSION_4_6 0x4006 eeprom.h has ee_scaled_cck_delta
362
 AR5K_EEPROM_VERSION_4_7AR5K_EEPROM_VERSION_4_7 0x3007 eeprom.h 4007 ?
363
 AR5K_EEPROM_VERSION_4_9AR5K_EEPROM_VERSION_4_9 0x4009 eeprom.h EAR futureproofing
364
 AR5K_EEPROM_VERSION_5_0AR5K_EEPROM_VERSION_5_0 0x5000 eeprom.h Has 2413 PDADC calibration etc
365
 AR5K_EEPROM_VERSION_5_1AR5K_EEPROM_VERSION_5_1 0x5001 eeprom.h Has capability values
366
 AR5K_EEPROM_VERSION_5_3AR5K_EEPROM_VERSION_5_3 0x5003 eeprom.h Has spur mitigation tables
367
 AR5K_EEPROM_MODE_11AAR5K_EEPROM_MODE_11A 0 eeprom.h 　
368
 AR5K_EEPROM_MODE_11BAR5K_EEPROM_MODE_11B 1 eeprom.h 　
369
 AR5K_EEPROM_MODE_11GAR5K_EEPROM_MODE_11G 2 eeprom.h 　
370
 AR5K_EEPROM_HDRAR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) eeprom.h Header that contains the device caps
371
 AR5K_EEPROM_RFKILL_GPIO_SELAR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c eeprom.h 　
372
 AR5K_EEPROM_RFKILL_GPIO_SEL_SAR5K_EEPROM_RFKILL_GPIO_SEL_S 2 eeprom.h 　
373
 AR5K_EEPROM_RFKILL_POLARITYAR5K_EEPROM_RFKILL_POLARITY 0x00000002 eeprom.h 　
374
 AR5K_EEPROM_RFKILL_POLARITY_SAR5K_EEPROM_RFKILL_POLARITY_S 1 eeprom.h 　
375
 AR5K_EEPROM_MISC0AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4) eeprom.h 　
376
 AR5K_EEPROM_MISC1AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) eeprom.h 　
377
 AR5K_EEPROM_MISC2AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) eeprom.h 　
378
 AR5K_EEPROM_MISC3AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7) eeprom.h 　
379
 AR5K_EEPROM_MISC4AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) eeprom.h 　
380
 AR5K_EEPROM_MISC5AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) eeprom.h 　
381
 AR5K_EEPROM_MISC6AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) eeprom.h 　
382
 AR5K_EEPROM_TX_CHAIN_DISAR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8) eeprom.h 　
383
 AR5K_EEPROM_RX_CHAIN_DISAR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8) eeprom.h 　
384
 AR5K_EEPROM_FCC_MID_ENAR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) eeprom.h 　
385
 AR5K_EEPROM_JAP_U1EVEN_ENAR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) eeprom.h 　
386
 AR5K_EEPROM_JAP_U2_ENAR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) eeprom.h 　
387
 AR5K_EEPROM_JAP_U1ODD_ENAR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1) eeprom.h 　
388
 AR5K_EEPROM_JAP_11A_NEW_ENAR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1) eeprom.h 　
389
 AR5K_EEPROM_GROUP1_OFFSETAR5K_EEPROM_GROUP1_OFFSET 0x0 eeprom.h 　
390
 AR5K_EEPROM_GROUP2_OFFSETAR5K_EEPROM_GROUP2_OFFSET 0x5 eeprom.h 　
391
 AR5K_EEPROM_GROUP3_OFFSETAR5K_EEPROM_GROUP3_OFFSET 0x37 eeprom.h 　
392
 AR5K_EEPROM_GROUP4_OFFSETAR5K_EEPROM_GROUP4_OFFSET 0x46 eeprom.h 　
393
 AR5K_EEPROM_GROUP5_OFFSETAR5K_EEPROM_GROUP5_OFFSET 0x55 eeprom.h 　
394
 AR5K_EEPROM_GROUP6_OFFSETAR5K_EEPROM_GROUP6_OFFSET 0x65 eeprom.h 　
395
 AR5K_EEPROM_GROUP7_OFFSETAR5K_EEPROM_GROUP7_OFFSET 0x69 eeprom.h 　
396
 AR5K_EEPROM_GROUP8_OFFSETAR5K_EEPROM_GROUP8_OFFSET 0x6f eeprom.h 　
397
 AR5K_EEPROM_OBDB0_2GHZAR5K_EEPROM_OBDB0_2GHZ 0x00ec eeprom.h 　
398
 AR5K_EEPROM_OBDB1_2GHZAR5K_EEPROM_OBDB1_2GHZ 0x00ed eeprom.h 　
399
 AR5K_EEPROM_PROTECTAR5K_EEPROM_PROTECT 0x003f eeprom.h EEPROM protect status
400
 AR5K_EEPROM_PROTECT_RD_0_31AR5K_EEPROM_PROTECT_RD_0_31 0x0001 eeprom.h Read protection bit for offsets 0x0 - 0x1f
401
 AR5K_EEPROM_PROTECT_WR_0_31AR5K_EEPROM_PROTECT_WR_0_31 0x0002 eeprom.h Write protection bit for offsets 0x0 - 0x1f
402
 AR5K_EEPROM_PROTECT_RD_32_63AR5K_EEPROM_PROTECT_RD_32_63 0x0004 eeprom.h 0x20 - 0x3f
403
 AR5K_EEPROM_PROTECT_WR_32_63AR5K_EEPROM_PROTECT_WR_32_63 0x0008 eeprom.h 　
404
 AR5K_EEPROM_PROTECT_RD_64_127AR5K_EEPROM_PROTECT_RD_64_127 0x0010 eeprom.h 0x40 - 0x7f
405
 AR5K_EEPROM_PROTECT_WR_64_127AR5K_EEPROM_PROTECT_WR_64_127 0x0020 eeprom.h 　
406
 AR5K_EEPROM_PROTECT_RD_128_191AR5K_EEPROM_PROTECT_RD_128_191 0x0040 eeprom.h 0x80 - 0xbf (regdom)
407
 AR5K_EEPROM_PROTECT_WR_128_191AR5K_EEPROM_PROTECT_WR_128_191 0x0080 eeprom.h 　
408
 AR5K_EEPROM_PROTECT_RD_192_207AR5K_EEPROM_PROTECT_RD_192_207 0x0100 eeprom.h 0xc0 - 0xcf
409
 AR5K_EEPROM_PROTECT_WR_192_207AR5K_EEPROM_PROTECT_WR_192_207 0x0200 eeprom.h 　
410
 AR5K_EEPROM_PROTECT_RD_208_223AR5K_EEPROM_PROTECT_RD_208_223 0x0400 eeprom.h 0xd0 - 0xdf
411
 AR5K_EEPROM_PROTECT_WR_208_223AR5K_EEPROM_PROTECT_WR_208_223 0x0800 eeprom.h 　
412
 AR5K_EEPROM_PROTECT_RD_224_239AR5K_EEPROM_PROTECT_RD_224_239 0x1000 eeprom.h 0xe0 - 0xef
413
 AR5K_EEPROM_PROTECT_WR_224_239AR5K_EEPROM_PROTECT_WR_224_239 0x2000 eeprom.h 　
414
 AR5K_EEPROM_PROTECT_RD_240_255AR5K_EEPROM_PROTECT_RD_240_255 0x4000 eeprom.h 0xf0 - 0xff
415
 AR5K_EEPROM_PROTECT_WR_240_255AR5K_EEPROM_PROTECT_WR_240_255 0x8000 eeprom.h 　
416
 AR5K_EEPROM_EEP_SCALEAR5K_EEPROM_EEP_SCALE 100 eeprom.h 　
417
 AR5K_EEPROM_EEP_DELTAAR5K_EEPROM_EEP_DELTA 10 eeprom.h 　
418
 AR5K_EEPROM_N_MODESAR5K_EEPROM_N_MODES 3 eeprom.h 　
419
 AR5K_EEPROM_N_5GHZ_CHANAR5K_EEPROM_N_5GHZ_CHAN 10 eeprom.h 　
420
 AR5K_EEPROM_N_2GHZ_CHANAR5K_EEPROM_N_2GHZ_CHAN 3 eeprom.h 　
421
 AR5K_EEPROM_N_2GHZ_CHAN_2413AR5K_EEPROM_N_2GHZ_CHAN_2413 4 eeprom.h 　
422
 AR5K_EEPROM_N_2GHZ_CHAN_MAXAR5K_EEPROM_N_2GHZ_CHAN_MAX 4 eeprom.h 　
423
 AR5K_EEPROM_MAX_CHANAR5K_EEPROM_MAX_CHAN 10 eeprom.h 　
424
 AR5K_EEPROM_N_PWR_POINTS_5111AR5K_EEPROM_N_PWR_POINTS_5111 11 eeprom.h 　
425
 AR5K_EEPROM_N_PCDACAR5K_EEPROM_N_PCDAC 11 eeprom.h 　
426
 AR5K_EEPROM_N_PHASE_CALAR5K_EEPROM_N_PHASE_CAL 5 eeprom.h 　
427
 AR5K_EEPROM_N_TEST_FREQAR5K_EEPROM_N_TEST_FREQ 8 eeprom.h 　
428
 AR5K_EEPROM_N_EDGESAR5K_EEPROM_N_EDGES 8 eeprom.h 　
429
 AR5K_EEPROM_N_INTERCEPTSAR5K_EEPROM_N_INTERCEPTS 11 eeprom.h 　
430
 AR5K_EEPROM_PCDAC_MAR5K_EEPROM_PCDAC_M 0x3f eeprom.h 　
431
 AR5K_EEPROM_PCDAC_STARTAR5K_EEPROM_PCDAC_START 1 eeprom.h 　
432
 AR5K_EEPROM_PCDAC_STOPAR5K_EEPROM_PCDAC_STOP 63 eeprom.h 　
433
 AR5K_EEPROM_PCDAC_STEPAR5K_EEPROM_PCDAC_STEP 1 eeprom.h 　
434
 AR5K_EEPROM_NON_EDGE_MAR5K_EEPROM_NON_EDGE_M 0x40 eeprom.h 　
435
 AR5K_EEPROM_CHANNEL_POWERAR5K_EEPROM_CHANNEL_POWER 8 eeprom.h 　
436
 AR5K_EEPROM_N_OBDBAR5K_EEPROM_N_OBDB 4 eeprom.h 　
437
 AR5K_EEPROM_OBDB_DISAR5K_EEPROM_OBDB_DIS 0xffff eeprom.h 　
438
 AR5K_EEPROM_CHANNEL_DISAR5K_EEPROM_CHANNEL_DIS 0xff eeprom.h 　
439
 AR5K_EEPROM_MAX_CTLSAR5K_EEPROM_MAX_CTLS 32 eeprom.h 　
440
 AR5K_EEPROM_N_PD_CURVESAR5K_EEPROM_N_PD_CURVES 4 eeprom.h 　
441
 AR5K_EEPROM_N_XPD0_POINTSAR5K_EEPROM_N_XPD0_POINTS 4 eeprom.h 　
442
 AR5K_EEPROM_N_XPD3_POINTSAR5K_EEPROM_N_XPD3_POINTS 3 eeprom.h 　
443
 AR5K_EEPROM_N_PD_GAINSAR5K_EEPROM_N_PD_GAINS 4 eeprom.h 　
444
 AR5K_EEPROM_N_PD_POINTSAR5K_EEPROM_N_PD_POINTS 5 eeprom.h 　
445
 AR5K_EEPROM_N_INTERCEPT_10_2GHZAR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 eeprom.h 　
446
 AR5K_EEPROM_N_INTERCEPT_10_5GHZAR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 eeprom.h 　
447
 AR5K_EEPROM_POWER_MAR5K_EEPROM_POWER_M 0x3f eeprom.h 　
448
 AR5K_EEPROM_POWER_MINAR5K_EEPROM_POWER_MIN 0 eeprom.h 　
449
 AR5K_EEPROM_POWER_MAXAR5K_EEPROM_POWER_MAX 3150 eeprom.h 　
450
 AR5K_EEPROM_POWER_STEPAR5K_EEPROM_POWER_STEP 50 eeprom.h 　
451
 AR5K_EEPROM_POWER_TABLE_SIZEAR5K_EEPROM_POWER_TABLE_SIZE 64 eeprom.h 　
452
 AR5K_EEPROM_N_POWER_LOC_11BAR5K_EEPROM_N_POWER_LOC_11B 4 eeprom.h 　
453
 AR5K_EEPROM_N_POWER_LOC_11GAR5K_EEPROM_N_POWER_LOC_11G 6 eeprom.h 　
454
 AR5K_EEPROM_I_GAINAR5K_EEPROM_I_GAIN 10 eeprom.h 　
455
 AR5K_EEPROM_CCK_OFDM_DELTAAR5K_EEPROM_CCK_OFDM_DELTA 15 eeprom.h 　
456
 AR5K_EEPROM_N_IQ_CALAR5K_EEPROM_N_IQ_CAL 2 eeprom.h 　
457
 AR5K_CTL_FCCAR5K_CTL_FCC 0x10 eeprom.h 　
458
 AR5K_CTL_CUSTOMAR5K_CTL_CUSTOM 0x20 eeprom.h 　
459
 AR5K_CTL_ETSIAR5K_CTL_ETSI 0x30 eeprom.h 　
460
 AR5K_CTL_MKKAR5K_CTL_MKK 0x40 eeprom.h 　
461
 AR5K_CTL_NO_REGDOMAINAR5K_CTL_NO_REGDOMAIN 0xf0 eeprom.h 　
462
 AR5K_CTL_NO_CTLAR5K_CTL_NO_CTL 0xff eeprom.h 　
463
 AR5K_NOQCU_TXDP0AR5K_NOQCU_TXDP0 0x0000 reg.h Queue 0 - data
464
 AR5K_NOQCU_TXDP1AR5K_NOQCU_TXDP1 0x0004 reg.h Queue 1 - beacons
465
 AR5K_CRAR5K_CR 0x0008 reg.h Register Address
466
 AR5K_CR_TXE0AR5K_CR_TXE0 0x00000001 reg.h TX Enable for queue 0 on 5210
467
 AR5K_CR_TXE1AR5K_CR_TXE1 0x00000002 reg.h TX Enable for queue 1 on 5210
468
 AR5K_CR_RXEAR5K_CR_RXE 0x00000004 reg.h RX Enable
469
 AR5K_CR_TXD0AR5K_CR_TXD0 0x00000008 reg.h TX Disable for queue 0 on 5210
470
 AR5K_CR_TXD1AR5K_CR_TXD1 0x00000010 reg.h TX Disable for queue 1 on 5210
471
 AR5K_CR_RXDAR5K_CR_RXD 0x00000020 reg.h RX Disable
472
 AR5K_CR_SWIAR5K_CR_SWI 0x00000040 reg.h Software Interrupt
473
 AR5K_RXDPAR5K_RXDP 0x000c reg.h 　
474
 AR5K_CFGAR5K_CFG 0x0014 reg.h Register Address
475
 AR5K_CFG_SWTDAR5K_CFG_SWTD 0x00000001 reg.h Byte-swap TX descriptor (for big endian archs)
476
 AR5K_CFG_SWTBAR5K_CFG_SWTB 0x00000002 reg.h Byte-swap TX buffer
477
 AR5K_CFG_SWRDAR5K_CFG_SWRD 0x00000004 reg.h Byte-swap RX descriptor
478
 AR5K_CFG_SWRBAR5K_CFG_SWRB 0x00000008 reg.h Byte-swap RX buffer
479
 AR5K_CFG_SWRGAR5K_CFG_SWRG 0x00000010 reg.h Byte-swap Register access
480
 AR5K_CFG_IBSSAR5K_CFG_IBSS 0x00000020 reg.h 0-BSS, 1-IBSS [5211+]
481
 AR5K_CFG_PHY_OKAR5K_CFG_PHY_OK 0x00000100 reg.h [5211+]
482
 AR5K_CFG_EEBSAR5K_CFG_EEBS 0x00000200 reg.h EEPROM is busy
483
 AR5K_CFG_CLKGDAR5K_CFG_CLKGD 0x00000400 reg.h Clock gated (Disable dynamic clock)
484
 AR5K_CFG_TXCNTAR5K_CFG_TXCNT 0x00007800 reg.h Tx frame count (?) [5210]
485
 AR5K_CFG_TXCNT_SAR5K_CFG_TXCNT_S 11 reg.h 　
486
 AR5K_CFG_TXFSTATAR5K_CFG_TXFSTAT 0x00008000 reg.h Tx frame status (?) [5210]
487
 AR5K_CFG_TXFSTRTAR5K_CFG_TXFSTRT 0x00010000 reg.h [5210]
488
 AR5K_CFG_PCI_THRESAR5K_CFG_PCI_THRES 0x00060000 reg.h PCI Master req q threshold [5211+]
489
 AR5K_CFG_PCI_THRES_SAR5K_CFG_PCI_THRES_S 17 reg.h 　
490
 AR5K_IERAR5K_IER 0x0024 reg.h Register Address
491
 AR5K_IER_DISABLEAR5K_IER_DISABLE 0x00000000 reg.h Disable card interrupts
492
 AR5K_IER_ENABLEAR5K_IER_ENABLE 0x00000001 reg.h Enable card interrupts
493
 AR5K_BCRAR5K_BCR 0x0028 reg.h Register Address
494
 AR5K_BCR_APAR5K_BCR_AP 0x00000000 reg.h AP mode
495
 AR5K_BCR_ADHOCAR5K_BCR_ADHOC 0x00000001 reg.h Ad-Hoc mode
496
 AR5K_BCR_BDMAEAR5K_BCR_BDMAE 0x00000002 reg.h DMA enable
497
 AR5K_BCR_TQ1FVAR5K_BCR_TQ1FV 0x00000004 reg.h Use Queue1 for CAB traffic
498
 AR5K_BCR_TQ1VAR5K_BCR_TQ1V 0x00000008 reg.h Use Queue1 for Beacon traffic
499
 AR5K_BCR_BCGETAR5K_BCR_BCGET 0x00000010 reg.h 　
500
 AR5K_RTSD0AR5K_RTSD0 0x0028 reg.h Register Address
501
 AR5K_RTSD0_6AR5K_RTSD0_6 0x000000ff reg.h 6Mb RTS duration mask (?)
502
 AR5K_RTSD0_6_SAR5K_RTSD0_6_S 0 reg.h 6Mb RTS duration shift (?)
503
 AR5K_RTSD0_9AR5K_RTSD0_9 0x0000ff00 reg.h 9Mb
504
 AR5K_RTSD0_9_SAR5K_RTSD0_9_S 8 reg.h 　
505
 AR5K_RTSD0_12AR5K_RTSD0_12 0x00ff0000 reg.h 12Mb
506
 AR5K_RTSD0_12_SAR5K_RTSD0_12_S 16 reg.h 　
507
 AR5K_RTSD0_18AR5K_RTSD0_18 0xff000000 reg.h 16Mb
508
 AR5K_RTSD0_18_SAR5K_RTSD0_18_S 24 reg.h 　
509
 AR5K_BSRAR5K_BSR 0x002c reg.h Register Address
510
 AR5K_BSR_BDLYSWAR5K_BSR_BDLYSW 0x00000001 reg.h SW Beacon delay (?)
511
 AR5K_BSR_BDLYDMAAR5K_BSR_BDLYDMA 0x00000002 reg.h DMA Beacon delay (?)
512
 AR5K_BSR_TXQ1FAR5K_BSR_TXQ1F 0x00000004 reg.h Beacon queue (1) finished
513
 AR5K_BSR_ATIMDLYAR5K_BSR_ATIMDLY 0x00000008 reg.h ATIM delay (?)
514
 AR5K_BSR_SNPADHOCAR5K_BSR_SNPADHOC 0x00000100 reg.h Ad-hoc mode set (?)
515
 AR5K_BSR_SNPBDMAEAR5K_BSR_SNPBDMAE 0x00000200 reg.h Beacon DMA enabled (?)
516
 AR5K_BSR_SNPTQ1FVAR5K_BSR_SNPTQ1FV 0x00000400 reg.h Queue1 is used for CAB traffic (?)
517
 AR5K_BSR_SNPTQ1VAR5K_BSR_SNPTQ1V 0x00000800 reg.h Queue1 is used for Beacon traffic (?)
518
 AR5K_BSR_SNAPSHOTSVALIDAR5K_BSR_SNAPSHOTSVALID 0x00001000 reg.h BCR snapshots are valid (?)
519
 AR5K_BSR_SWBA_CNTAR5K_BSR_SWBA_CNT 0x00ff0000 reg.h 　
520
 AR5K_RTSD1AR5K_RTSD1 0x002c reg.h Register Address
521
 AR5K_RTSD1_24AR5K_RTSD1_24 0x000000ff reg.h 24Mb
522
 AR5K_RTSD1_24_SAR5K_RTSD1_24_S 0 reg.h 　
523
 AR5K_RTSD1_36AR5K_RTSD1_36 0x0000ff00 reg.h 36Mb
524
 AR5K_RTSD1_36_SAR5K_RTSD1_36_S 8 reg.h 　
525
 AR5K_RTSD1_48AR5K_RTSD1_48 0x00ff0000 reg.h 48Mb
526
 AR5K_RTSD1_48_SAR5K_RTSD1_48_S 16 reg.h 　
527
 AR5K_RTSD1_54AR5K_RTSD1_54 0xff000000 reg.h 54Mb
528
 AR5K_RTSD1_54_SAR5K_RTSD1_54_S 24 reg.h 　
529
 AR5K_TXCFGAR5K_TXCFG 0x0030 reg.h Register Address
530
 AR5K_TXCFG_SDMAMRAR5K_TXCFG_SDMAMR 0x00000007 reg.h DMA size (read)
531
 AR5K_TXCFG_SDMAMR_SAR5K_TXCFG_SDMAMR_S 0 reg.h 　
532
 AR5K_TXCFG_B_MODEAR5K_TXCFG_B_MODE 0x00000008 reg.h Set b mode for 5111 (enable 2111)
533
 AR5K_TXCFG_TXFSTPAR5K_TXCFG_TXFSTP 0x00000008 reg.h TX DMA full Stop [5210]
534
 AR5K_TXCFG_TXFULLAR5K_TXCFG_TXFULL 0x000003f0 reg.h TX Triger level mask
535
 AR5K_TXCFG_TXFULL_SAR5K_TXCFG_TXFULL_S 4 reg.h 　
536
 AR5K_TXCFG_TXFULL_0BAR5K_TXCFG_TXFULL_0B 0x00000000 reg.h 　
537
 AR5K_TXCFG_TXFULL_64BAR5K_TXCFG_TXFULL_64B 0x00000010 reg.h 　
538
 AR5K_TXCFG_TXFULL_128BAR5K_TXCFG_TXFULL_128B 0x00000020 reg.h 　
539
 AR5K_TXCFG_TXFULL_192BAR5K_TXCFG_TXFULL_192B 0x00000030 reg.h 　
540
 AR5K_TXCFG_TXFULL_256BAR5K_TXCFG_TXFULL_256B 0x00000040 reg.h 　
541
 AR5K_TXCFG_TXCONT_ENAR5K_TXCFG_TXCONT_EN 0x00000080 reg.h 　
542
 AR5K_TXCFG_DMASIZEAR5K_TXCFG_DMASIZE 0x00000100 reg.h Flag for passing DMA size [5210]
543
 AR5K_TXCFG_JUMBO_DESC_ENAR5K_TXCFG_JUMBO_DESC_EN 0x00000400 reg.h Enable jumbo tx descriptors [5211+]
544
 AR5K_TXCFG_ADHOC_BCN_ATIMAR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 reg.h Adhoc Beacon ATIM Policy
545
 AR5K_TXCFG_ATIM_WINDOW_DEF_DISAR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 reg.h Disable ATIM window defer [5211+]
546
 AR5K_TXCFG_RTSRNDAR5K_TXCFG_RTSRND 0x00001000 reg.h [5211+]
547
 AR5K_TXCFG_FRMPAD_DISAR5K_TXCFG_FRMPAD_DIS 0x00002000 reg.h [5211+]
548
 AR5K_TXCFG_RDY_CBR_DISAR5K_TXCFG_RDY_CBR_DIS 0x00004000 reg.h Ready time CBR disable [5211+]
549
 AR5K_TXCFG_JUMBO_FRM_MODEAR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 reg.h Jumbo frame mode [5211+]
550
 AR5K_TXCFG_DCU_DBL_BUF_DISAR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 reg.h Disable double buffering on DCU
551
 AR5K_TXCFG_DCU_CACHING_DISAR5K_TXCFG_DCU_CACHING_DIS 0x00010000 reg.h Disable DCU caching
552
 AR5K_RXCFGAR5K_RXCFG 0x0034 reg.h Register Address
553
 AR5K_RXCFG_SDMAMWAR5K_RXCFG_SDMAMW 0x00000007 reg.h DMA size (write)
554
 AR5K_RXCFG_SDMAMW_SAR5K_RXCFG_SDMAMW_S 0 reg.h 　
555
 AR5K_RXCFG_ZLFDMAAR5K_RXCFG_ZLFDMA 0x00000008 reg.h Enable Zero-length frame DMA
556
 AR5K_RXCFG_DEF_ANTENNAAR5K_RXCFG_DEF_ANTENNA 0x00000010 reg.h Default antenna (?)
557
 AR5K_RXCFG_JUMBO_RXEAR5K_RXCFG_JUMBO_RXE 0x00000020 reg.h Enable jumbo rx descriptors [5211+]
558
 AR5K_RXCFG_JUMBO_WRAPAR5K_RXCFG_JUMBO_WRAP 0x00000040 reg.h Wrap jumbo frames [5211+]
559
 AR5K_RXCFG_SLE_ENTRYAR5K_RXCFG_SLE_ENTRY 0x00000080 reg.h Sleep entry policy
560
 AR5K_RXJLAAR5K_RXJLA 0x0038 reg.h 　
561
 AR5K_MIBCAR5K_MIBC 0x0040 reg.h Register Address
562
 AR5K_MIBC_COWAR5K_MIBC_COW 0x00000001 reg.h Warn test indicator
563
 AR5K_MIBC_FMCAR5K_MIBC_FMC 0x00000002 reg.h Freeze MIB Counters
564
 AR5K_MIBC_CMCAR5K_MIBC_CMC 0x00000004 reg.h Clean MIB Counters
565
 AR5K_MIBC_MCSAR5K_MIBC_MCS 0x00000008 reg.h MIB counter strobe
566
 AR5K_TOPSAR5K_TOPS 0x0044 reg.h 　
567
 AR5K_TOPS_MAR5K_TOPS_M 0x0000ffff reg.h 　
568
 AR5K_RXNOFRMAR5K_RXNOFRM 0x0048 reg.h 　
569
 AR5K_RXNOFRM_MAR5K_RXNOFRM_M 0x000003ff reg.h 　
570
 AR5K_TXNOFRMAR5K_TXNOFRM 0x004c reg.h 　
571
 AR5K_TXNOFRM_MAR5K_TXNOFRM_M 0x000003ff reg.h 　
572
 AR5K_TXNOFRM_QCUAR5K_TXNOFRM_QCU 0x000ffc00 reg.h 　
573
 AR5K_TXNOFRM_QCU_SAR5K_TXNOFRM_QCU_S 10 reg.h 　
574
 AR5K_RPGTOAR5K_RPGTO 0x0050 reg.h 　
575
 AR5K_RPGTO_MAR5K_RPGTO_M 0x000003ff reg.h 　
576
 AR5K_RFCNTAR5K_RFCNT 0x0054 reg.h 　
577
 AR5K_RFCNT_MAR5K_RFCNT_M 0x0000001f reg.h [5211+] (?)
578
 AR5K_RFCNT_RFCLAR5K_RFCNT_RFCL 0x0000000f reg.h [5210]
579
 AR5K_MISCAR5K_MISC 0x0058 reg.h Register Address
580
 AR5K_MISC_DMA_OBS_MAR5K_MISC_DMA_OBS_M 0x000001e0 reg.h 　
581
 AR5K_MISC_DMA_OBS_SAR5K_MISC_DMA_OBS_S 5 reg.h 　
582
 AR5K_MISC_MISC_OBS_MAR5K_MISC_MISC_OBS_M 0x00000e00 reg.h 　
583
 AR5K_MISC_MISC_OBS_SAR5K_MISC_MISC_OBS_S 9 reg.h 　
584
 AR5K_MISC_MAC_OBS_LSB_MAR5K_MISC_MAC_OBS_LSB_M 0x00007000 reg.h 　
585
 AR5K_MISC_MAC_OBS_LSB_SAR5K_MISC_MAC_OBS_LSB_S 12 reg.h 　
586
 AR5K_MISC_MAC_OBS_MSB_MAR5K_MISC_MAC_OBS_MSB_M 0x00038000 reg.h 　
587
 AR5K_MISC_MAC_OBS_MSB_SAR5K_MISC_MAC_OBS_MSB_S 15 reg.h 　
588
 AR5K_MISC_LED_DECAYAR5K_MISC_LED_DECAY 0x001c0000 reg.h [5210]
589
 AR5K_MISC_LED_BLINKAR5K_MISC_LED_BLINK 0x00e00000 reg.h [5210]
590
 AR5K_QCUDCU_CLKGTAR5K_QCUDCU_CLKGT 0x005c reg.h Register Address (?)
591
 AR5K_QCUDCU_CLKGT_QCUAR5K_QCUDCU_CLKGT_QCU 0x0000ffff reg.h Mask for QCU clock
592
 AR5K_QCUDCU_CLKGT_DCUAR5K_QCUDCU_CLKGT_DCU 0x07ff0000 reg.h Mask for DCU clock
593
 AR5K_ISRAR5K_ISR 0x001c reg.h Register Address [5210]
594
 AR5K_PISRAR5K_PISR 0x0080 reg.h Register Address [5211+]
595
 AR5K_ISR_RXOKAR5K_ISR_RXOK 0x00000001 reg.h Frame successfuly recieved
596
 AR5K_ISR_RXDESCAR5K_ISR_RXDESC 0x00000002 reg.h RX descriptor request
597
 AR5K_ISR_RXERRAR5K_ISR_RXERR 0x00000004 reg.h Receive error
598
 AR5K_ISR_RXNOFRMAR5K_ISR_RXNOFRM 0x00000008 reg.h No frame received (receive timeout)
599
 AR5K_ISR_RXEOLAR5K_ISR_RXEOL 0x00000010 reg.h Empty RX descriptor
600
 AR5K_ISR_RXORNAR5K_ISR_RXORN 0x00000020 reg.h Receive FIFO overrun
601
 AR5K_ISR_TXOKAR5K_ISR_TXOK 0x00000040 reg.h Frame successfuly transmited
602
 AR5K_ISR_TXDESCAR5K_ISR_TXDESC 0x00000080 reg.h TX descriptor request
603
 AR5K_ISR_TXERRAR5K_ISR_TXERR 0x00000100 reg.h Transmit error
604
 AR5K_ISR_TXNOFRMAR5K_ISR_TXNOFRM 0x00000200 reg.h No frame transmited (transmit timeout)
605
 AR5K_ISR_TXEOLAR5K_ISR_TXEOL 0x00000400 reg.h Empty TX descriptor
606
 AR5K_ISR_TXURNAR5K_ISR_TXURN 0x00000800 reg.h Transmit FIFO underrun
607
 AR5K_ISR_MIBAR5K_ISR_MIB 0x00001000 reg.h Update MIB counters
608
 AR5K_ISR_SWIAR5K_ISR_SWI 0x00002000 reg.h Software interrupt
609
 AR5K_ISR_RXPHYAR5K_ISR_RXPHY 0x00004000 reg.h PHY error
610
 AR5K_ISR_RXKCMAR5K_ISR_RXKCM 0x00008000 reg.h RX Key cache miss
611
 AR5K_ISR_SWBAAR5K_ISR_SWBA 0x00010000 reg.h Software beacon alert
612
 AR5K_ISR_BRSSIAR5K_ISR_BRSSI 0x00020000 reg.h Beacon rssi below threshold (?)
613
 AR5K_ISR_BMISSAR5K_ISR_BMISS 0x00040000 reg.h Beacon missed
614
 AR5K_ISR_HIUERRAR5K_ISR_HIUERR 0x00080000 reg.h Host Interface Unit error [5211+]
615
 AR5K_ISR_BNRAR5K_ISR_BNR 0x00100000 reg.h Beacon not ready [5211+]
616
 AR5K_ISR_MCABTAR5K_ISR_MCABT 0x00100000 reg.h Master Cycle Abort [5210]
617
 AR5K_ISR_RXCHIRPAR5K_ISR_RXCHIRP 0x00200000 reg.h CHIRP Received [5212+]
618
 AR5K_ISR_SSERRAR5K_ISR_SSERR 0x00200000 reg.h Signaled System Error [5210]
619
 AR5K_ISR_DPERRAR5K_ISR_DPERR 0x00400000 reg.h Det par Error (?) [5210]
620
 AR5K_ISR_RXDOPPLERAR5K_ISR_RXDOPPLER 0x00400000 reg.h Doppler chirp received [5212+]
621
 AR5K_ISR_TIMAR5K_ISR_TIM 0x00800000 reg.h [5211+]
622
 AR5K_ISR_BCNMISCAR5K_ISR_BCNMISC 0x00800000 reg.h 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
623
 AR5K_ISR_GPIOAR5K_ISR_GPIO 0x01000000 reg.h GPIO (rf kill)
624
 AR5K_ISR_QCBRORNAR5K_ISR_QCBRORN 0x02000000 reg.h QCU CBR overrun [5211+]
625
 AR5K_ISR_QCBRURNAR5K_ISR_QCBRURN 0x04000000 reg.h QCU CBR underrun [5211+]
626
 AR5K_ISR_QTRIGAR5K_ISR_QTRIG 0x08000000 reg.h QCU scheduling trigger [5211+]
627
 AR5K_SISR0AR5K_SISR0 0x0084 reg.h Register Address [5211+]
628
 AR5K_SISR0_QCU_TXOKAR5K_SISR0_QCU_TXOK 0x000003ff reg.h Mask for QCU_TXOK
629
 AR5K_SISR0_QCU_TXOK_SAR5K_SISR0_QCU_TXOK_S 0 reg.h 　
630
 AR5K_SISR0_QCU_TXDESCAR5K_SISR0_QCU_TXDESC 0x03ff0000 reg.h Mask for QCU_TXDESC
631
 AR5K_SISR0_QCU_TXDESC_SAR5K_SISR0_QCU_TXDESC_S 16 reg.h 　
632
 AR5K_SISR1AR5K_SISR1 0x0088 reg.h Register Address [5211+]
633
 AR5K_SISR1_QCU_TXERRAR5K_SISR1_QCU_TXERR 0x000003ff reg.h Mask for QCU_TXERR
634
 AR5K_SISR1_QCU_TXERR_SAR5K_SISR1_QCU_TXERR_S 0 reg.h 　
635
 AR5K_SISR1_QCU_TXEOLAR5K_SISR1_QCU_TXEOL 0x03ff0000 reg.h Mask for QCU_TXEOL
636
 AR5K_SISR1_QCU_TXEOL_SAR5K_SISR1_QCU_TXEOL_S 16 reg.h 　
637
 AR5K_SISR2AR5K_SISR2 0x008c reg.h Register Address [5211+]
638
 AR5K_SISR2_QCU_TXURNAR5K_SISR2_QCU_TXURN 0x000003ff reg.h Mask for QCU_TXURN
639
 AR5K_SISR2_QCU_TXURN_SAR5K_SISR2_QCU_TXURN_S 0 reg.h 　
640
 AR5K_SISR2_MCABTAR5K_SISR2_MCABT 0x00100000 reg.h Master Cycle Abort
641
 AR5K_SISR2_SSERRAR5K_SISR2_SSERR 0x00200000 reg.h Signaled System Error
642
 AR5K_SISR2_DPERRAR5K_SISR2_DPERR 0x00400000 reg.h Bus parity error
643
 AR5K_SISR2_TIMAR5K_SISR2_TIM 0x01000000 reg.h [5212+]
644
 AR5K_SISR2_CAB_ENDAR5K_SISR2_CAB_END 0x02000000 reg.h [5212+]
645
 AR5K_SISR2_DTIM_SYNCAR5K_SISR2_DTIM_SYNC 0x04000000 reg.h DTIM sync lost [5212+]
646
 AR5K_SISR2_BCN_TIMEOUTAR5K_SISR2_BCN_TIMEOUT 0x08000000 reg.h Beacon Timeout [5212+]
647
 AR5K_SISR2_CAB_TIMEOUTAR5K_SISR2_CAB_TIMEOUT 0x10000000 reg.h CAB Timeout [5212+]
648
 AR5K_SISR2_DTIMAR5K_SISR2_DTIM 0x20000000 reg.h [5212+]
649
 AR5K_SISR2_TSFOORAR5K_SISR2_TSFOOR 0x80000000 reg.h TSF OOR (?)
650
 AR5K_SISR3AR5K_SISR3 0x0090 reg.h Register Address [5211+]
651
 AR5K_SISR3_QCBRORNAR5K_SISR3_QCBRORN 0x000003ff reg.h Mask for QCBRORN
652
 AR5K_SISR3_QCBRORN_SAR5K_SISR3_QCBRORN_S 0 reg.h 　
653
 AR5K_SISR3_QCBRURNAR5K_SISR3_QCBRURN 0x03ff0000 reg.h Mask for QCBRURN
654
 AR5K_SISR3_QCBRURN_SAR5K_SISR3_QCBRURN_S 16 reg.h 　
655
 AR5K_SISR4AR5K_SISR4 0x0094 reg.h Register Address [5211+]
656
 AR5K_SISR4_QTRIGAR5K_SISR4_QTRIG 0x000003ff reg.h Mask for QTRIG
657
 AR5K_SISR4_QTRIG_SAR5K_SISR4_QTRIG_S 0 reg.h 　
658
 AR5K_RAC_PISRAR5K_RAC_PISR 0x00c0 reg.h Read and clear PISR
659
 AR5K_RAC_SISR0AR5K_RAC_SISR0 0x00c4 reg.h Read and clear SISR0
660
 AR5K_RAC_SISR1AR5K_RAC_SISR1 0x00c8 reg.h Read and clear SISR1
661
 AR5K_RAC_SISR2AR5K_RAC_SISR2 0x00cc reg.h Read and clear SISR2
662
 AR5K_RAC_SISR3AR5K_RAC_SISR3 0x00d0 reg.h Read and clear SISR3
663
 AR5K_RAC_SISR4AR5K_RAC_SISR4 0x00d4 reg.h Read and clear SISR4
664
 AR5K_IMRAR5K_IMR 0x0020 reg.h Register Address [5210]
665
 AR5K_PIMRAR5K_PIMR 0x00a0 reg.h Register Address [5211+]
666
 AR5K_IMR_RXOKAR5K_IMR_RXOK 0x00000001 reg.h Frame successfuly recieved
667
 AR5K_IMR_RXDESCAR5K_IMR_RXDESC 0x00000002 reg.h RX descriptor request
668
 AR5K_IMR_RXERRAR5K_IMR_RXERR 0x00000004 reg.h Receive error
669
 AR5K_IMR_RXNOFRMAR5K_IMR_RXNOFRM 0x00000008 reg.h No frame received (receive timeout)
670
 AR5K_IMR_RXEOLAR5K_IMR_RXEOL 0x00000010 reg.h Empty RX descriptor
671
 AR5K_IMR_RXORNAR5K_IMR_RXORN 0x00000020 reg.h Receive FIFO overrun
672
 AR5K_IMR_TXOKAR5K_IMR_TXOK 0x00000040 reg.h Frame successfuly transmited
673
 AR5K_IMR_TXDESCAR5K_IMR_TXDESC 0x00000080 reg.h TX descriptor request
674
 AR5K_IMR_TXERRAR5K_IMR_TXERR 0x00000100 reg.h Transmit error
675
 AR5K_IMR_TXNOFRMAR5K_IMR_TXNOFRM 0x00000200 reg.h No frame transmited (transmit timeout)
676
 AR5K_IMR_TXEOLAR5K_IMR_TXEOL 0x00000400 reg.h Empty TX descriptor
677
 AR5K_IMR_TXURNAR5K_IMR_TXURN 0x00000800 reg.h Transmit FIFO underrun
678
 AR5K_IMR_MIBAR5K_IMR_MIB 0x00001000 reg.h Update MIB counters
679
 AR5K_IMR_SWIAR5K_IMR_SWI 0x00002000 reg.h Software interrupt
680
 AR5K_IMR_RXPHYAR5K_IMR_RXPHY 0x00004000 reg.h PHY error
681
 AR5K_IMR_RXKCMAR5K_IMR_RXKCM 0x00008000 reg.h RX Key cache miss
682
 AR5K_IMR_SWBAAR5K_IMR_SWBA 0x00010000 reg.h Software beacon alert
683
 AR5K_IMR_BRSSIAR5K_IMR_BRSSI 0x00020000 reg.h Beacon rssi below threshold (?)
684
 AR5K_IMR_BMISSAR5K_IMR_BMISS 0x00040000 reg.h Beacon missed
685
 AR5K_IMR_HIUERRAR5K_IMR_HIUERR 0x00080000 reg.h Host Interface Unit error [5211+]
686
 AR5K_IMR_BNRAR5K_IMR_BNR 0x00100000 reg.h Beacon not ready [5211+]
687
 AR5K_IMR_MCABTAR5K_IMR_MCABT 0x00100000 reg.h Master Cycle Abort [5210]
688
 AR5K_IMR_RXCHIRPAR5K_IMR_RXCHIRP 0x00200000 reg.h CHIRP Received [5212+]
689
 AR5K_IMR_SSERRAR5K_IMR_SSERR 0x00200000 reg.h Signaled System Error [5210]
690
 AR5K_IMR_DPERRAR5K_IMR_DPERR 0x00400000 reg.h Det par Error (?) [5210]
691
 AR5K_IMR_RXDOPPLERAR5K_IMR_RXDOPPLER 0x00400000 reg.h Doppler chirp received [5212+]
692
 AR5K_IMR_TIMAR5K_IMR_TIM 0x00800000 reg.h [5211+]
693
 AR5K_IMR_BCNMISCAR5K_IMR_BCNMISC 0x00800000 reg.h 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
694
 AR5K_IMR_GPIOAR5K_IMR_GPIO 0x01000000 reg.h GPIO (rf kill)
695
 AR5K_IMR_QCBRORNAR5K_IMR_QCBRORN 0x02000000 reg.h QCU CBR overrun (?) [5211+]
696
 AR5K_IMR_QCBRURNAR5K_IMR_QCBRURN 0x04000000 reg.h QCU CBR underrun (?) [5211+]
697
 AR5K_IMR_QTRIGAR5K_IMR_QTRIG 0x08000000 reg.h QCU scheduling trigger [5211+]
698
 AR5K_SIMR0AR5K_SIMR0 0x00a4 reg.h Register Address [5211+]
699
 AR5K_SIMR0_QCU_TXOKAR5K_SIMR0_QCU_TXOK 0x000003ff reg.h Mask for QCU_TXOK
700
 AR5K_SIMR0_QCU_TXOK_SAR5K_SIMR0_QCU_TXOK_S 0 reg.h 　
701
 AR5K_SIMR0_QCU_TXDESCAR5K_SIMR0_QCU_TXDESC 0x03ff0000 reg.h Mask for QCU_TXDESC
702
 AR5K_SIMR0_QCU_TXDESC_SAR5K_SIMR0_QCU_TXDESC_S 16 reg.h 　
703
 AR5K_SIMR1AR5K_SIMR1 0x00a8 reg.h Register Address [5211+]
704
 AR5K_SIMR1_QCU_TXERRAR5K_SIMR1_QCU_TXERR 0x000003ff reg.h Mask for QCU_TXERR
705
 AR5K_SIMR1_QCU_TXERR_SAR5K_SIMR1_QCU_TXERR_S 0 reg.h 　
706
 AR5K_SIMR1_QCU_TXEOLAR5K_SIMR1_QCU_TXEOL 0x03ff0000 reg.h Mask for QCU_TXEOL
707
 AR5K_SIMR1_QCU_TXEOL_SAR5K_SIMR1_QCU_TXEOL_S 16 reg.h 　
708
 AR5K_SIMR2AR5K_SIMR2 0x00ac reg.h Register Address [5211+]
709
 AR5K_SIMR2_QCU_TXURNAR5K_SIMR2_QCU_TXURN 0x000003ff reg.h Mask for QCU_TXURN
710
 AR5K_SIMR2_QCU_TXURN_SAR5K_SIMR2_QCU_TXURN_S 0 reg.h 　
711
 AR5K_SIMR2_MCABTAR5K_SIMR2_MCABT 0x00100000 reg.h Master Cycle Abort
712
 AR5K_SIMR2_SSERRAR5K_SIMR2_SSERR 0x00200000 reg.h Signaled System Error
713
 AR5K_SIMR2_DPERRAR5K_SIMR2_DPERR 0x00400000 reg.h Bus parity error
714
 AR5K_SIMR2_TIMAR5K_SIMR2_TIM 0x01000000 reg.h [5212+]
715
 AR5K_SIMR2_CAB_ENDAR5K_SIMR2_CAB_END 0x02000000 reg.h [5212+]
716
 AR5K_SIMR2_DTIM_SYNCAR5K_SIMR2_DTIM_SYNC 0x04000000 reg.h DTIM Sync lost [5212+]
717
 AR5K_SIMR2_BCN_TIMEOUTAR5K_SIMR2_BCN_TIMEOUT 0x08000000 reg.h Beacon Timeout [5212+]
718
 AR5K_SIMR2_CAB_TIMEOUTAR5K_SIMR2_CAB_TIMEOUT 0x10000000 reg.h CAB Timeout [5212+]
719
 AR5K_SIMR2_DTIMAR5K_SIMR2_DTIM 0x20000000 reg.h [5212+]
720
 AR5K_SIMR2_TSFOORAR5K_SIMR2_TSFOOR 0x80000000 reg.h TSF OOR (?)
721
 AR5K_SIMR3AR5K_SIMR3 0x00b0 reg.h Register Address [5211+]
722
 AR5K_SIMR3_QCBRORNAR5K_SIMR3_QCBRORN 0x000003ff reg.h Mask for QCBRORN
723
 AR5K_SIMR3_QCBRORN_SAR5K_SIMR3_QCBRORN_S 0 reg.h 　
724
 AR5K_SIMR3_QCBRURNAR5K_SIMR3_QCBRURN 0x03ff0000 reg.h Mask for QCBRURN
725
 AR5K_SIMR3_QCBRURN_SAR5K_SIMR3_QCBRURN_S 16 reg.h 　
726
 AR5K_SIMR4AR5K_SIMR4 0x00b4 reg.h Register Address [5211+]
727
 AR5K_SIMR4_QTRIGAR5K_SIMR4_QTRIG 0x000003ff reg.h Mask for QTRIG
728
 AR5K_SIMR4_QTRIG_SAR5K_SIMR4_QTRIG_S 0 reg.h 　
729
 AR5K_DCM_ADDRAR5K_DCM_ADDR 0x0400 reg.h Decompression mask address (index)
730
 AR5K_DCM_DATAAR5K_DCM_DATA 0x0404 reg.h Decompression mask data
731
 AR5K_WOW_PCFGAR5K_WOW_PCFG 0x0410 reg.h Register Address
732
 AR5K_WOW_PCFG_PAT_MATCH_ENAR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 reg.h Pattern match enable
733
 AR5K_WOW_PCFG_LONG_FRAME_POLAR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 reg.h Long frame policy
734
 AR5K_WOW_PCFG_WOBMISSAR5K_WOW_PCFG_WOBMISS 0x00000004 reg.h Wake on bea(con) miss (?)
735
 AR5K_WOW_PCFG_PAT_0_ENAR5K_WOW_PCFG_PAT_0_EN 0x00000100 reg.h Enable pattern 0
736
 AR5K_WOW_PCFG_PAT_1_ENAR5K_WOW_PCFG_PAT_1_EN 0x00000200 reg.h Enable pattern 1
737
 AR5K_WOW_PCFG_PAT_2_ENAR5K_WOW_PCFG_PAT_2_EN 0x00000400 reg.h Enable pattern 2
738
 AR5K_WOW_PCFG_PAT_3_ENAR5K_WOW_PCFG_PAT_3_EN 0x00000800 reg.h Enable pattern 3
739
 AR5K_WOW_PCFG_PAT_4_ENAR5K_WOW_PCFG_PAT_4_EN 0x00001000 reg.h Enable pattern 4
740
 AR5K_WOW_PCFG_PAT_5_ENAR5K_WOW_PCFG_PAT_5_EN 0x00002000 reg.h Enable pattern 5
741
 AR5K_WOW_PAT_IDXAR5K_WOW_PAT_IDX 0x0414 reg.h 　
742
 AR5K_WOW_PAT_DATAAR5K_WOW_PAT_DATA 0x0418 reg.h Register Address
743
 AR5K_WOW_PAT_DATA_0_3_VAR5K_WOW_PAT_DATA_0_3_V 0x00000001 reg.h Pattern 0, 3 value
744
 AR5K_WOW_PAT_DATA_1_4_VAR5K_WOW_PAT_DATA_1_4_V 0x00000100 reg.h Pattern 1, 4 value
745
 AR5K_WOW_PAT_DATA_2_5_VAR5K_WOW_PAT_DATA_2_5_V 0x00010000 reg.h Pattern 2, 5 value
746
 AR5K_WOW_PAT_DATA_0_3_MAR5K_WOW_PAT_DATA_0_3_M 0x01000000 reg.h Pattern 0, 3 mask
747
 AR5K_WOW_PAT_DATA_1_4_MAR5K_WOW_PAT_DATA_1_4_M 0x04000000 reg.h Pattern 1, 4 mask
748
 AR5K_WOW_PAT_DATA_2_5_MAR5K_WOW_PAT_DATA_2_5_M 0x10000000 reg.h Pattern 2, 5 mask
749
 AR5K_DCCFGAR5K_DCCFG 0x0420 reg.h Register Address
750
 AR5K_DCCFG_GLOBAL_ENAR5K_DCCFG_GLOBAL_EN 0x00000001 reg.h Enable decompression on all queues
751
 AR5K_DCCFG_BYPASS_ENAR5K_DCCFG_BYPASS_EN 0x00000002 reg.h Bypass decompression
752
 AR5K_DCCFG_BCAST_ENAR5K_DCCFG_BCAST_EN 0x00000004 reg.h Enable decompression for bcast frames
753
 AR5K_DCCFG_MCAST_ENAR5K_DCCFG_MCAST_EN 0x00000008 reg.h Enable decompression for mcast frames
754
 AR5K_CCFGAR5K_CCFG 0x0600 reg.h Register Address
755
 AR5K_CCFG_WINDOW_SIZEAR5K_CCFG_WINDOW_SIZE 0x00000007 reg.h Compression window size
756
 AR5K_CCFG_CPC_ENAR5K_CCFG_CPC_EN 0x00000008 reg.h Enable performance counters
757
 AR5K_CCFG_CCUAR5K_CCFG_CCU 0x0604 reg.h Register Address
758
 AR5K_CCFG_CCU_CUP_ENAR5K_CCFG_CCU_CUP_EN 0x00000001 reg.h CCU Catchup enable
759
 AR5K_CCFG_CCU_CREDITAR5K_CCFG_CCU_CREDIT 0x00000002 reg.h CCU Credit (field)
760
 AR5K_CCFG_CCU_CD_THRESAR5K_CCFG_CCU_CD_THRES 0x00000080 reg.h CCU Cyc(lic?) debt threshold (field)
761
 AR5K_CCFG_CCU_CUP_LCNTAR5K_CCFG_CCU_CUP_LCNT 0x00010000 reg.h CCU Catchup lit(?) count
762
 AR5K_CCFG_CCU_INITAR5K_CCFG_CCU_INIT 0x00100200 reg.h Initial value during reset
763
 AR5K_CPC0AR5K_CPC0 0x0610 reg.h Compression performance counter 0
764
 AR5K_CPC1AR5K_CPC1 0x0614 reg.h Compression performance counter 1
765
 AR5K_CPC2AR5K_CPC2 0x0618 reg.h Compression performance counter 2
766
 AR5K_CPC3AR5K_CPC3 0x061c reg.h Compression performance counter 3
767
 AR5K_CPCOVFAR5K_CPCOVF 0x0620 reg.h Compression performance overflow
768
 AR5K_QCU_TXDP_BASEAR5K_QCU_TXDP_BASE 0x0800 reg.h Register Address - Queue0 TXDP
769
 AR5K_QCU_TXEAR5K_QCU_TXE 0x0840 reg.h 　
770
 AR5K_QCU_TXDAR5K_QCU_TXD 0x0880 reg.h 　
771
 AR5K_QCU_CBRCFG_BASEAR5K_QCU_CBRCFG_BASE 0x08c0 reg.h Register Address - Queue0 CBRCFG
772
 AR5K_QCU_CBRCFG_INTVALAR5K_QCU_CBRCFG_INTVAL 0x00ffffff reg.h CBR Interval mask
773
 AR5K_QCU_CBRCFG_INTVAL_SAR5K_QCU_CBRCFG_INTVAL_S 0 reg.h 　
774
 AR5K_QCU_CBRCFG_ORN_THRESAR5K_QCU_CBRCFG_ORN_THRES 0xff000000 reg.h CBR overrun threshold mask
775
 AR5K_QCU_CBRCFG_ORN_THRES_SAR5K_QCU_CBRCFG_ORN_THRES_S 24 reg.h 　
776
 AR5K_QCU_RDYTIMECFG_BASEAR5K_QCU_RDYTIMECFG_BASE 0x0900 reg.h Register Address - Queue0 RDYTIMECFG
777
 AR5K_QCU_RDYTIMECFG_INTVALAR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff reg.h Ready time interval mask
778
 AR5K_QCU_RDYTIMECFG_INTVAL_SAR5K_QCU_RDYTIMECFG_INTVAL_S 0 reg.h 　
779
 AR5K_QCU_RDYTIMECFG_ENABLEAR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 reg.h Ready time enable mask
780
 AR5K_QCU_ONESHOTARM_SETAR5K_QCU_ONESHOTARM_SET 0x0940 reg.h Register Address -QCU "one shot arm set (?)"
781
 AR5K_QCU_ONESHOTARM_SET_MAR5K_QCU_ONESHOTARM_SET_M 0x0000ffff reg.h 　
782
 AR5K_QCU_ONESHOTARM_CLEARAR5K_QCU_ONESHOTARM_CLEAR 0x0980 reg.h Register Address -QCU "one shot arm clear (?)"
783
 AR5K_QCU_ONESHOTARM_CLEAR_MAR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff reg.h 　
784
 AR5K_QCU_MISC_BASEAR5K_QCU_MISC_BASE 0x09c0 reg.h Register Address -Queue0 MISC
785
 AR5K_QCU_MISC_FRSHED_MAR5K_QCU_MISC_FRSHED_M 0x0000000f reg.h Frame sheduling mask
786
 AR5K_QCU_MISC_FRSHED_ASAPAR5K_QCU_MISC_FRSHED_ASAP 0 reg.h ASAP
787
 AR5K_QCU_MISC_FRSHED_CBRAR5K_QCU_MISC_FRSHED_CBR 1 reg.h Constant Bit Rate
788
 AR5K_QCU_MISC_FRSHED_DBA_GTAR5K_QCU_MISC_FRSHED_DBA_GT 2 reg.h DMA Beacon alert gated
789
 AR5K_QCU_MISC_FRSHED_TIM_GTAR5K_QCU_MISC_FRSHED_TIM_GT 3 reg.h TIMT gated
790
 AR5K_QCU_MISC_FRSHED_BCN_SENT_GAR5K_QCU_MISC_FRSHED_BCN_SENT_G 4 reg.h Beacon sent gated
791
 AR5K_QCU_MISC_ONESHOT_ENABLEAR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 reg.h Oneshot enable
792
 AR5K_QCU_MISC_CBREXP_DISAR5K_QCU_MISC_CBREXP_DIS 0x00000020 reg.h Disable CBR expired counter (normal queue)
793
 AR5K_QCU_MISC_CBREXP_BCN_DISAR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 reg.h Disable CBR expired counter (beacon queue)
794
 AR5K_QCU_MISC_BCN_ENABLEAR5K_QCU_MISC_BCN_ENABLE 0x00000080 reg.h Enable Beacon use
795
 AR5K_QCU_MISC_CBR_THRES_ENABLEAR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 reg.h CBR expired threshold enabled
796
 AR5K_QCU_MISC_RDY_VEOL_POLICYAR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 reg.h TXE reset when RDYTIME expired or VEOL
797
 AR5K_QCU_MISC_CBR_RESET_CNTAR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 reg.h CBR threshold (counter) reset
798
 AR5K_QCU_MISC_DCU_EARLYAR5K_QCU_MISC_DCU_EARLY 0x00000800 reg.h DCU early termination
799
 AR5K_QCU_MISC_DCU_CMP_ENAR5K_QCU_MISC_DCU_CMP_EN 0x00001000 reg.h Enable frame compression
800
 AR5K_QCU_STS_BASEAR5K_QCU_STS_BASE 0x0a00 reg.h Register Address - Queue0 STS
801
 AR5K_QCU_STS_FRMPENDCNTAR5K_QCU_STS_FRMPENDCNT 0x00000003 reg.h Frames pending counter
802
 AR5K_QCU_STS_CBREXPCNTAR5K_QCU_STS_CBREXPCNT 0x0000ff00 reg.h CBR expired counter
803
 AR5K_QCU_RDYTIMESHDNAR5K_QCU_RDYTIMESHDN 0x0a40 reg.h 　
804
 AR5K_QCU_RDYTIMESHDN_MAR5K_QCU_RDYTIMESHDN_M 0x000003ff reg.h 　
805
 AR5K_QCU_CBB_SELECTAR5K_QCU_CBB_SELECT 0x0b00 reg.h 　
806
 AR5K_QCU_CBB_ADDRAR5K_QCU_CBB_ADDR 0x0b04 reg.h 　
807
 AR5K_QCU_CBB_ADDR_SAR5K_QCU_CBB_ADDR_S 9 reg.h 　
808
 AR5K_QCU_CBCFGAR5K_QCU_CBCFG 0x0b08 reg.h 　
809
 AR5K_DCU_QCUMASK_BASEAR5K_DCU_QCUMASK_BASE 0x1000 reg.h Register Address -Queue0 DCU_QCUMASK
810
 AR5K_DCU_QCUMASK_MAR5K_DCU_QCUMASK_M 0x000003ff reg.h 　
811
 AR5K_DCU_LCL_IFS_BASEAR5K_DCU_LCL_IFS_BASE 0x1040 reg.h Register Address -Queue0 DCU_LCL_IFS
812
 AR5K_DCU_LCL_IFS_CW_MINAR5K_DCU_LCL_IFS_CW_MIN 0x000003ff reg.h Minimum Contention Window
813
 AR5K_DCU_LCL_IFS_CW_MIN_SAR5K_DCU_LCL_IFS_CW_MIN_S 0 reg.h 　
814
 AR5K_DCU_LCL_IFS_CW_MAXAR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 reg.h Maximum Contention Window
815
 AR5K_DCU_LCL_IFS_CW_MAX_SAR5K_DCU_LCL_IFS_CW_MAX_S 10 reg.h 　
816
 AR5K_DCU_LCL_IFS_AIFSAR5K_DCU_LCL_IFS_AIFS 0x0ff00000 reg.h Arbitrated Interframe Space
817
 AR5K_DCU_LCL_IFS_AIFS_SAR5K_DCU_LCL_IFS_AIFS_S 20 reg.h 　
818
 AR5K_DCU_LCL_IFS_AIFS_MAXAR5K_DCU_LCL_IFS_AIFS_MAX 0xfc reg.h Anything above that can cause DCU to hang
819
 AR5K_DCU_RETRY_LMT_BASEAR5K_DCU_RETRY_LMT_BASE 0x1080 reg.h Register Address -Queue0 DCU_RETRY_LMT
820
 AR5K_DCU_RETRY_LMT_SH_RETRYAR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f reg.h Short retry limit mask
821
 AR5K_DCU_RETRY_LMT_SH_RETRY_SAR5K_DCU_RETRY_LMT_SH_RETRY_S 0 reg.h 　
822
 AR5K_DCU_RETRY_LMT_LG_RETRYAR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 reg.h Long retry limit mask
823
 AR5K_DCU_RETRY_LMT_LG_RETRY_SAR5K_DCU_RETRY_LMT_LG_RETRY_S 4 reg.h 　
824
 AR5K_DCU_RETRY_LMT_SSH_RETRYAR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 reg.h Station short retry limit mask (?)
825
 AR5K_DCU_RETRY_LMT_SSH_RETRY_SAR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 reg.h 　
826
 AR5K_DCU_RETRY_LMT_SLG_RETRYAR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 reg.h Station long retry limit mask (?)
827
 AR5K_DCU_RETRY_LMT_SLG_RETRY_SAR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 reg.h 　
828
 AR5K_DCU_CHAN_TIME_BASEAR5K_DCU_CHAN_TIME_BASE 0x10c0 reg.h Register Address -Queue0 DCU_CHAN_TIME
829
 AR5K_DCU_CHAN_TIME_DURAR5K_DCU_CHAN_TIME_DUR 0x000fffff reg.h Channel time duration
830
 AR5K_DCU_CHAN_TIME_DUR_SAR5K_DCU_CHAN_TIME_DUR_S 0 reg.h 　
831
 AR5K_DCU_CHAN_TIME_ENABLEAR5K_DCU_CHAN_TIME_ENABLE 0x00100000 reg.h Enable channel time
832
 AR5K_DCU_MISC_BASEAR5K_DCU_MISC_BASE 0x1100 reg.h Register Address -Queue0 DCU_MISC
833
 AR5K_DCU_MISC_BACKOFFAR5K_DCU_MISC_BACKOFF 0x0000003f reg.h Mask for backoff threshold
834
 AR5K_DCU_MISC_ETS_RTS_POLAR5K_DCU_MISC_ETS_RTS_POL 0x00000040 reg.h End of transmission series
835
 AR5K_DCU_MISC_ETS_CW_POLAR5K_DCU_MISC_ETS_CW_POL 0x00000080 reg.h End of transmission series
836
 AR5K_DCU_MISC_FRAG_WAITAR5K_DCU_MISC_FRAG_WAIT 0x00000100 reg.h Wait for next fragment
837
 AR5K_DCU_MISC_BACKOFF_FRAGAR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 reg.h Enable backoff while bursting
838
 AR5K_DCU_MISC_HCFPOLL_ENABLEAR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 reg.h CF - Poll enable
839
 AR5K_DCU_MISC_BACKOFF_PERSISTAR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 reg.h Persistent backoff
840
 AR5K_DCU_MISC_FRMPRFTCH_ENABLEAR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 reg.h Enable frame pre-fetch
841
 AR5K_DCU_MISC_VIRTCOLAR5K_DCU_MISC_VIRTCOL 0x0000c000 reg.h Mask for Virtual Collision (?)
842
 AR5K_DCU_MISC_VIRTCOL_NORMALAR5K_DCU_MISC_VIRTCOL_NORMAL 0 reg.h 　
843
 AR5K_DCU_MISC_VIRTCOL_IGNOREAR5K_DCU_MISC_VIRTCOL_IGNORE 1 reg.h 　
844
 AR5K_DCU_MISC_BCN_ENABLEAR5K_DCU_MISC_BCN_ENABLE 0x00010000 reg.h Enable Beacon use
845
 AR5K_DCU_MISC_ARBLOCK_CTLAR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 reg.h Arbiter lockout control mask
846
 AR5K_DCU_MISC_ARBLOCK_CTL_SAR5K_DCU_MISC_ARBLOCK_CTL_S 17 reg.h 　
847
 AR5K_DCU_MISC_ARBLOCK_CTL_NONEAR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 reg.h No arbiter lockout
848
 AR5K_DCU_MISC_ARBLOCK_CTL_INTFRAR5K_DCU_MISC_ARBLOCK_CTL_INTFR 1 reg.h Intra-frame lockout
849
 AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAAR5K_DCU_MISC_ARBLOCK_CTL_GLOBA 2 reg.h Global lockout
850
 AR5K_DCU_MISC_ARBLOCK_IGNOREAR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 reg.h Ignore Arbiter lockout
851
 AR5K_DCU_MISC_SEQ_NUM_INCR_DISAR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 reg.h Disable sequence number increment
852
 AR5K_DCU_MISC_POST_FR_BKOFF_DISAR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 reg.h Disable post-frame backoff
853
 AR5K_DCU_MISC_VIRT_COLL_POLICYAR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 reg.h Virtual Collision cw policy
854
 AR5K_DCU_MISC_BLOWN_IFS_POLICYAR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 reg.h Blown IFS policy (?)
855
 AR5K_DCU_MISC_SEQNUM_CTLAR5K_DCU_MISC_SEQNUM_CTL 0x01000000 reg.h Sequence number control (?)
856
 AR5K_DCU_SEQNUM_BASEAR5K_DCU_SEQNUM_BASE 0x1140 reg.h 　
857
 AR5K_DCU_SEQNUM_MAR5K_DCU_SEQNUM_M 0x00000fff reg.h 　
858
 AR5K_DCU_GBL_IFS_SIFSAR5K_DCU_GBL_IFS_SIFS 0x1030 reg.h 　
859
 AR5K_DCU_GBL_IFS_SIFS_MAR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff reg.h 　
860
 AR5K_DCU_GBL_IFS_SLOTAR5K_DCU_GBL_IFS_SLOT 0x1070 reg.h 　
861
 AR5K_DCU_GBL_IFS_SLOT_MAR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff reg.h 　
862
 AR5K_DCU_GBL_IFS_EIFSAR5K_DCU_GBL_IFS_EIFS 0x10b0 reg.h 　
863
 AR5K_DCU_GBL_IFS_EIFS_MAR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff reg.h 　
864
 AR5K_DCU_GBL_IFS_MISCAR5K_DCU_GBL_IFS_MISC 0x10f0 reg.h Register Address
865
 AR5K_DCU_GBL_IFS_MISC_LFSR_SLICAR5K_DCU_GBL_IFS_MISC_LFSR_SLIC 0x00000007 reg.h LFSR Slice Select
866
 AR5K_DCU_GBL_IFS_MISC_TURBO_MODAR5K_DCU_GBL_IFS_MISC_TURBO_MOD 0x00000008 reg.h Turbo mode
867
 AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_ 0x000003f0 reg.h SIFS Duration mask
868
 AR5K_DCU_GBL_IFS_MISC_USEC_DURAR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 reg.h USEC Duration mask
869
 AR5K_DCU_GBL_IFS_MISC_USEC_DUR_AR5K_DCU_GBL_IFS_MISC_USEC_DUR_ 10 reg.h 　
870
 AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DAR5K_DCU_GBL_IFS_MISC_DCU_ARB_D 0x00300000 reg.h DCU Arbiter delay mask
871
 AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_ 0x00400000 reg.h SIFS cnt reset policy (?)
872
 AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_ 0x00800000 reg.h AIFS cnt reset policy (?)
873
 AR5K_DCU_GBL_IFS_MISC_RND_LFSR_AR5K_DCU_GBL_IFS_MISC_RND_LFSR_ 0x01000000 reg.h Disable random LFSR slice
874
 AR5K_DCU_FPAR5K_DCU_FP 0x1230 reg.h Register Address
875
 AR5K_DCU_FP_NOBURST_DCU_ENAR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 reg.h Enable non-burst prefetch on DCU (?)
876
 AR5K_DCU_FP_NOBURST_ENAR5K_DCU_FP_NOBURST_EN 0x00000010 reg.h Enable non-burst prefetch (?)
877
 AR5K_DCU_FP_BURST_DCU_ENAR5K_DCU_FP_BURST_DCU_EN 0x00000020 reg.h Enable burst prefetch on DCU (?)
878
 AR5K_DCU_TXPAR5K_DCU_TXP 0x1270 reg.h Register Address
879
 AR5K_DCU_TXP_MAR5K_DCU_TXP_M 0x000003ff reg.h Tx pause mask
880
 AR5K_DCU_TXP_STATUSAR5K_DCU_TXP_STATUS 0x00010000 reg.h Tx pause status
881
 AR5K_DCU_TX_FILTER_0_BASEAR5K_DCU_TX_FILTER_0_BASE 0x1038 reg.h 　
882
 AR5K_DCU_TX_FILTER_1_BASEAR5K_DCU_TX_FILTER_1_BASE 0x103c reg.h 　
883
 AR5K_DCU_TX_FILTER_CLRAR5K_DCU_TX_FILTER_CLR 0x143c reg.h 　
884
 AR5K_DCU_TX_FILTER_SETAR5K_DCU_TX_FILTER_SET 0x147c reg.h 　
885
 AR5K_RESET_CTLAR5K_RESET_CTL 0x4000 reg.h Register Address
886
 AR5K_RESET_CTL_PCUAR5K_RESET_CTL_PCU 0x00000001 reg.h Protocol Control Unit reset
887
 AR5K_RESET_CTL_DMAAR5K_RESET_CTL_DMA 0x00000002 reg.h DMA (Rx/Tx) reset [5210]
888
 AR5K_RESET_CTL_BASEBANDAR5K_RESET_CTL_BASEBAND 0x00000002 reg.h Baseband reset [5211+]
889
 AR5K_RESET_CTL_MACAR5K_RESET_CTL_MAC 0x00000004 reg.h MAC reset (PCU+Baseband ?) [5210]
890
 AR5K_RESET_CTL_PHYAR5K_RESET_CTL_PHY 0x00000008 reg.h PHY reset [5210]
891
 AR5K_RESET_CTL_PCIAR5K_RESET_CTL_PCI 0x00000010 reg.h PCI Core reset (interrupts etc)
892
 AR5K_SLEEP_CTLAR5K_SLEEP_CTL 0x4004 reg.h Register Address
893
 AR5K_SLEEP_CTL_SLDURAR5K_SLEEP_CTL_SLDUR 0x0000ffff reg.h Sleep duration mask
894
 AR5K_SLEEP_CTL_SLDUR_SAR5K_SLEEP_CTL_SLDUR_S 0 reg.h 　
895
 AR5K_SLEEP_CTL_SLEAR5K_SLEEP_CTL_SLE 0x00030000 reg.h Sleep enable mask
896
 AR5K_SLEEP_CTL_SLE_SAR5K_SLEEP_CTL_SLE_S 16 reg.h 　
897
 AR5K_SLEEP_CTL_SLE_WAKEAR5K_SLEEP_CTL_SLE_WAKE 0x00000000 reg.h Force chip awake
898
 AR5K_SLEEP_CTL_SLE_SLPAR5K_SLEEP_CTL_SLE_SLP 0x00010000 reg.h Force chip sleep
899
 AR5K_SLEEP_CTL_SLE_ALLOWAR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 reg.h Normal sleep policy
900
 AR5K_SLEEP_CTL_SLE_UNITSAR5K_SLEEP_CTL_SLE_UNITS 0x00000008 reg.h [5211+]
901
 AR5K_SLEEP_CTL_DUR_TIM_POLAR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 reg.h Sleep duration timing policy
902
 AR5K_SLEEP_CTL_DUR_WRITE_POLAR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 reg.h Sleep duration write policy
903
 AR5K_SLEEP_CTL_SLE_POLAR5K_SLEEP_CTL_SLE_POL 0x00100000 reg.h Sleep policy mode
904
 AR5K_INTPENDAR5K_INTPEND 0x4008 reg.h 　
905
 AR5K_INTPEND_MAR5K_INTPEND_M 0x00000001 reg.h 　
906
 AR5K_SFRAR5K_SFR 0x400c reg.h 　
907
 AR5K_SFR_ENAR5K_SFR_EN 0x00000001 reg.h 　
908
 AR5K_PCICFGAR5K_PCICFG 0x4010 reg.h Register Address
909
 AR5K_PCICFG_EEAEAR5K_PCICFG_EEAE 0x00000001 reg.h Eeprom access enable [5210]
910
 AR5K_PCICFG_SLEEP_CLOCK_ENAR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 reg.h Enable sleep clock
911
 AR5K_PCICFG_CLKRUNENAR5K_PCICFG_CLKRUNEN 0x00000004 reg.h CLKRUN enable [5211+]
912
 AR5K_PCICFG_EESIZEAR5K_PCICFG_EESIZE 0x00000018 reg.h Mask for EEPROM size [5211+]
913
 AR5K_PCICFG_EESIZE_SAR5K_PCICFG_EESIZE_S 3 reg.h 　
914
 AR5K_PCICFG_EESIZE_4KAR5K_PCICFG_EESIZE_4K 0 reg.h 4K
915
 AR5K_PCICFG_EESIZE_8KAR5K_PCICFG_EESIZE_8K 1 reg.h 8K
916
 AR5K_PCICFG_EESIZE_16KAR5K_PCICFG_EESIZE_16K 2 reg.h 16K
917
 AR5K_PCICFG_EESIZE_FAILAR5K_PCICFG_EESIZE_FAIL 3 reg.h Failed to get size [5211+]
918
 AR5K_PCICFG_LEDAR5K_PCICFG_LED 0x00000060 reg.h Led status [5211+]
919
 AR5K_PCICFG_LED_NONEAR5K_PCICFG_LED_NONE 0x00000000 reg.h Default [5211+]
920
 AR5K_PCICFG_LED_PENDAR5K_PCICFG_LED_PEND 0x00000020 reg.h Scan / Auth pending
921
 AR5K_PCICFG_LED_ASSOCAR5K_PCICFG_LED_ASSOC 0x00000040 reg.h Associated
922
 AR5K_PCICFG_BUS_SELAR5K_PCICFG_BUS_SEL 0x00000380 reg.h Mask for "bus select" [5211+] (?)
923
 AR5K_PCICFG_CBEFIX_DISAR5K_PCICFG_CBEFIX_DIS 0x00000400 reg.h Disable CBE fix
924
 AR5K_PCICFG_SL_INTENAR5K_PCICFG_SL_INTEN 0x00000800 reg.h Enable interrupts when asleep
925
 AR5K_PCICFG_LED_BCTLAR5K_PCICFG_LED_BCTL 0x00001000 reg.h Led blink (?) [5210]
926
 AR5K_PCICFG_RETRY_FIXAR5K_PCICFG_RETRY_FIX 0x00001000 reg.h Enable pci core retry fix
927
 AR5K_PCICFG_SL_INPENAR5K_PCICFG_SL_INPEN 0x00002000 reg.h Sleep even whith pending interrupts
928
 AR5K_PCICFG_SPWR_DNAR5K_PCICFG_SPWR_DN 0x00010000 reg.h Mask for power status
929
 AR5K_PCICFG_LEDMODEAR5K_PCICFG_LEDMODE 0x000e0000 reg.h Ledmode [5211+]
930
 AR5K_PCICFG_LEDMODE_PROPAR5K_PCICFG_LEDMODE_PROP 0x00000000 reg.h Blink on standard traffic [5211+]
931
 AR5K_PCICFG_LEDMODE_PROMAR5K_PCICFG_LEDMODE_PROM 0x00020000 reg.h Default mode (blink on any traffic) [5211+]
932
 AR5K_PCICFG_LEDMODE_PWRAR5K_PCICFG_LEDMODE_PWR 0x00040000 reg.h Some other blinking mode (?) [5211+]
933
 AR5K_PCICFG_LEDMODE_RANDAR5K_PCICFG_LEDMODE_RAND 0x00060000 reg.h Random blinking (?) [5211+]
934
 AR5K_PCICFG_LEDBLINKAR5K_PCICFG_LEDBLINK 0x00700000 reg.h Led blink rate
935
 AR5K_PCICFG_LEDBLINK_SAR5K_PCICFG_LEDBLINK_S 20 reg.h 　
936
 AR5K_PCICFG_LEDSLOWAR5K_PCICFG_LEDSLOW 0x00800000 reg.h Slowest led blink rate [5211+]
937
 AR5K_PCICFG_LEDSTATEAR5K_PCICFG_LEDSTATE (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) reg.h 　
938
 AR5K_PCICFG_SLEEP_CLOCK_RATEAR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 reg.h Sleep clock rate
939
 AR5K_PCICFG_SLEEP_CLOCK_RATE_SAR5K_PCICFG_SLEEP_CLOCK_RATE_S 24 reg.h 　
940
 AR5K_NUM_GPIOAR5K_NUM_GPIO 6 reg.h 　
941
 AR5K_GPIOCRAR5K_GPIOCR 0x4014 reg.h Register Address
942
 AR5K_GPIOCR_INT_ENAAR5K_GPIOCR_INT_ENA 0x00008000 reg.h Enable GPIO interrupt
943
 AR5K_GPIOCR_INT_SELLAR5K_GPIOCR_INT_SELL 0x00000000 reg.h Generate interrupt when pin is low
944
 AR5K_GPIOCR_INT_SELHAR5K_GPIOCR_INT_SELH 0x00010000 reg.h Generate interrupt when pin is high
945
 AR5K_GPIODOAR5K_GPIODO 0x4018 reg.h 　
946
 AR5K_GPIODIAR5K_GPIODI 0x401c reg.h 　
947
 AR5K_GPIODI_MAR5K_GPIODI_M 0x0000002f reg.h 　
948
 AR5K_SREVAR5K_SREV 0x4020 reg.h Register Address
949
 AR5K_SREV_REVAR5K_SREV_REV 0x0000000f reg.h Mask for revision
950
 AR5K_SREV_REV_SAR5K_SREV_REV_S 0 reg.h 　
951
 AR5K_SREV_VERAR5K_SREV_VER 0x000000ff reg.h Mask for version
952
 AR5K_SREV_VER_SAR5K_SREV_VER_S 4 reg.h 　
953
 AR5K_TXEPOSTAR5K_TXEPOST 0x4028 reg.h 　
954
 AR5K_QCU_SLEEP_MASKAR5K_QCU_SLEEP_MASK 0x402c reg.h 　
955
 AR5K_5414_CBCFGAR5K_5414_CBCFG 0x4068 reg.h 　
956
 AR5K_5414_CBCFG_BUF_DISAR5K_5414_CBCFG_BUF_DIS 0x10 reg.h Disable buffer
957
 AR5K_PCIE_PM_CTLAR5K_PCIE_PM_CTL 0x4068 reg.h Register address
958
 AR5K_PCIE_PM_CTL_L1_WHEN_D2AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 reg.h enable PCIe core enter L1
959
 AR5K_PCIE_PM_CTL_L0_L0S_CLEARAR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 reg.h Clear L0 and L0S counters
960
 AR5K_PCIE_PM_CTL_L0_L0S_ENAR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 reg.h Start L0 nd L0S counters
961
 AR5K_PCIE_PM_CTL_LDRESET_ENAR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 reg.h Enable reset when link goes
962
 AR5K_PCIE_PM_CTL_PME_ENAR5K_PCIE_PM_CTL_PME_EN 0x00000010 reg.h PME Enable
963
 AR5K_PCIE_PM_CTL_AUX_PWR_DETAR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 reg.h Aux power detect
964
 AR5K_PCIE_PM_CTL_PME_CLEARAR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 reg.h Clear PME
965
 AR5K_PCIE_PM_CTL_PSM_D0AR5K_PCIE_PM_CTL_PSM_D0 0x00000080 reg.h 　
966
 AR5K_PCIE_PM_CTL_PSM_D1AR5K_PCIE_PM_CTL_PSM_D1 0x00000100 reg.h 　
967
 AR5K_PCIE_PM_CTL_PSM_D2AR5K_PCIE_PM_CTL_PSM_D2 0x00000200 reg.h 　
968
 AR5K_PCIE_PM_CTL_PSM_D3AR5K_PCIE_PM_CTL_PSM_D3 0x00000400 reg.h 　
969
 AR5K_PCIE_WAENAR5K_PCIE_WAEN 0x407c reg.h 　
970
 AR5K_PCIE_SERDESAR5K_PCIE_SERDES 0x4080 reg.h 　
971
 AR5K_PCIE_SERDES_RESETAR5K_PCIE_SERDES_RESET 0x4084 reg.h 　
972
 AR5K_EEPROM_BASEAR5K_EEPROM_BASE 0x6000 reg.h 　
973
 AR5K_EEPROM_DATA_5211AR5K_EEPROM_DATA_5211 0x6004 reg.h 　
974
 AR5K_EEPROM_DATA_5210AR5K_EEPROM_DATA_5210 0x6800 reg.h 　
975
 AR5K_EEPROM_DATAAR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \ AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) reg.h 　
976
 AR5K_EEPROM_CMDAR5K_EEPROM_CMD 0x6008 reg.h Register Addres
977
 AR5K_EEPROM_CMD_READAR5K_EEPROM_CMD_READ 0x00000001 reg.h EEPROM read
978
 AR5K_EEPROM_CMD_WRITEAR5K_EEPROM_CMD_WRITE 0x00000002 reg.h EEPROM write
979
 AR5K_EEPROM_CMD_RESETAR5K_EEPROM_CMD_RESET 0x00000004 reg.h EEPROM reset
980
 AR5K_EEPROM_STAT_5210AR5K_EEPROM_STAT_5210 0x6c00 reg.h Register Address [5210]
981
 AR5K_EEPROM_STAT_5211AR5K_EEPROM_STAT_5211 0x600c reg.h Register Address [5211+]
982
 AR5K_EEPROM_STATUSAR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \ AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) reg.h 　
983
 AR5K_EEPROM_STAT_RDERRAR5K_EEPROM_STAT_RDERR 0x00000001 reg.h EEPROM read failed
984
 AR5K_EEPROM_STAT_RDDONEAR5K_EEPROM_STAT_RDDONE 0x00000002 reg.h EEPROM read successful
985
 AR5K_EEPROM_STAT_WRERRAR5K_EEPROM_STAT_WRERR 0x00000004 reg.h EEPROM write failed
986
 AR5K_EEPROM_STAT_WRDONEAR5K_EEPROM_STAT_WRDONE 0x00000008 reg.h EEPROM write successful
987
 AR5K_EEPROM_CFGAR5K_EEPROM_CFG 0x6010 reg.h Register Addres
988
 AR5K_EEPROM_CFG_SIZEAR5K_EEPROM_CFG_SIZE 0x00000003 reg.h Size determination override
989
 AR5K_EEPROM_CFG_SIZE_AUTOAR5K_EEPROM_CFG_SIZE_AUTO 0 reg.h 　
990
 AR5K_EEPROM_CFG_SIZE_4KBITAR5K_EEPROM_CFG_SIZE_4KBIT 1 reg.h 　
991
 AR5K_EEPROM_CFG_SIZE_8KBITAR5K_EEPROM_CFG_SIZE_8KBIT 2 reg.h 　
992
 AR5K_EEPROM_CFG_SIZE_16KBITAR5K_EEPROM_CFG_SIZE_16KBIT 3 reg.h 　
993
 AR5K_EEPROM_CFG_WR_WAIT_DISAR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 reg.h Disable write wait
994
 AR5K_EEPROM_CFG_CLK_RATEAR5K_EEPROM_CFG_CLK_RATE 0x00000018 reg.h Clock rate
995
 AR5K_EEPROM_CFG_CLK_RATE_SAR5K_EEPROM_CFG_CLK_RATE_S 3 reg.h 　
996
 AR5K_EEPROM_CFG_CLK_RATE_156KHZAR5K_EEPROM_CFG_CLK_RATE_156KHZ 0 reg.h 　
997
 AR5K_EEPROM_CFG_CLK_RATE_312KHZAR5K_EEPROM_CFG_CLK_RATE_312KHZ 1 reg.h 　
998
 AR5K_EEPROM_CFG_CLK_RATE_625KHZAR5K_EEPROM_CFG_CLK_RATE_625KHZ 2 reg.h 　
999
 AR5K_EEPROM_CFG_PROT_KEYAR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 reg.h Protection key
1000
 AR5K_EEPROM_CFG_PROT_KEY_SAR5K_EEPROM_CFG_PROT_KEY_S 8 reg.h 　
1001
 AR5K_EEPROM_CFG_LIND_ENAR5K_EEPROM_CFG_LIND_EN 0x01000000 reg.h Enable length indicator (?)
1002
 AR5K_PCU_MINAR5K_PCU_MIN 0x8000 reg.h 　
1003
 AR5K_PCU_MAXAR5K_PCU_MAX 0x8fff reg.h 　
1004
 AR5K_STA_ID0AR5K_STA_ID0 0x8000 reg.h 　
1005
 AR5K_STA_ID0_ARRD_L32AR5K_STA_ID0_ARRD_L32 0xffffffff reg.h 　
1006
 AR5K_STA_ID1AR5K_STA_ID1 0x8004 reg.h Register Address
1007
 AR5K_STA_ID1_ADDR_U16AR5K_STA_ID1_ADDR_U16 0x0000ffff reg.h Upper 16 bits of MAC addres
1008
 AR5K_STA_ID1_APAR5K_STA_ID1_AP 0x00010000 reg.h Set AP mode
1009
 AR5K_STA_ID1_ADHOCAR5K_STA_ID1_ADHOC 0x00020000 reg.h Set Ad-Hoc mode
1010
 AR5K_STA_ID1_PWR_SVAR5K_STA_ID1_PWR_SV 0x00040000 reg.h Power save reporting
1011
 AR5K_STA_ID1_NO_KEYSRCHAR5K_STA_ID1_NO_KEYSRCH 0x00080000 reg.h No key search
1012
 AR5K_STA_ID1_NO_PSPOLLAR5K_STA_ID1_NO_PSPOLL 0x00100000 reg.h No power save polling [5210]
1013
 AR5K_STA_ID1_PCF_5211AR5K_STA_ID1_PCF_5211 0x00100000 reg.h Enable PCF on [5211+]
1014
 AR5K_STA_ID1_PCF_5210AR5K_STA_ID1_PCF_5210 0x00200000 reg.h Enable PCF on [5210]
1015
 AR5K_STA_ID1_PCFAR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \ AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) reg.h 　
1016
 AR5K_STA_ID1_DEFAULT_ANTENNAAR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 reg.h Use default antenna
1017
 AR5K_STA_ID1_DESC_ANTENNAAR5K_STA_ID1_DESC_ANTENNA 0x00400000 reg.h Update antenna from descriptor
1018
 AR5K_STA_ID1_RTS_DEF_ANTENNAAR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 reg.h Use default antenna for RTS
1019
 AR5K_STA_ID1_ACKCTS_6MBAR5K_STA_ID1_ACKCTS_6MB 0x01000000 reg.h Use 6Mbit/s for ACK/CTS
1020
 AR5K_STA_ID1_BASE_RATE_11BAR5K_STA_ID1_BASE_RATE_11B 0x02000000 reg.h Use 11b base rate for ACK/CTS [5211+]
1021
 AR5K_STA_ID1_SELFGEN_DEF_ANTAR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 reg.h Use def. antenna for self generated frames
1022
 AR5K_STA_ID1_CRYPT_MIC_ENAR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 reg.h Enable MIC
1023
 AR5K_STA_ID1_KEYSRCH_MODEAR5K_STA_ID1_KEYSRCH_MODE 0x10000000 reg.h Look up key when key id != 0
1024
 AR5K_STA_ID1_PRESERVE_SEQ_NUMAR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 reg.h Preserve sequence number
1025
 AR5K_STA_ID1_CBCIV_ENDIANAR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 reg.h ???
1026
 AR5K_STA_ID1_KEYSRCH_MCASTAR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 reg.h Do key cache search for mcast frames
1027
 AR5K_BSS_ID0AR5K_BSS_ID0 0x8008 reg.h 　
1028
 AR5K_BSS_ID1AR5K_BSS_ID1 0x800c reg.h 　
1029
 AR5K_BSS_ID1_AIDAR5K_BSS_ID1_AID 0xffff0000 reg.h 　
1030
 AR5K_BSS_ID1_AID_SAR5K_BSS_ID1_AID_S 16 reg.h 　
1031
 AR5K_SLOT_TIMEAR5K_SLOT_TIME 0x8010 reg.h 　
1032
 AR5K_TIME_OUTAR5K_TIME_OUT 0x8014 reg.h Register Address
1033
 AR5K_TIME_OUT_ACKAR5K_TIME_OUT_ACK 0x00001fff reg.h ACK timeout mask
1034
 AR5K_TIME_OUT_ACK_SAR5K_TIME_OUT_ACK_S 0 reg.h 　
1035
 AR5K_TIME_OUT_CTSAR5K_TIME_OUT_CTS 0x1fff0000 reg.h CTS timeout mask
1036
 AR5K_TIME_OUT_CTS_SAR5K_TIME_OUT_CTS_S 16 reg.h 　
1037
 AR5K_RSSI_THRAR5K_RSSI_THR 0x8018 reg.h Register Address
1038
 AR5K_RSSI_THR_MAR5K_RSSI_THR_M 0x000000ff reg.h Mask for RSSI threshold [5211+]
1039
 AR5K_RSSI_THR_BMISS_5210AR5K_RSSI_THR_BMISS_5210 0x00000700 reg.h Mask for Beacon Missed threshold [5210]
1040
 AR5K_RSSI_THR_BMISS_5210_SAR5K_RSSI_THR_BMISS_5210_S 8 reg.h 　
1041
 AR5K_RSSI_THR_BMISS_5211AR5K_RSSI_THR_BMISS_5211 0x0000ff00 reg.h Mask for Beacon Missed threshold [5211+]
1042
 AR5K_RSSI_THR_BMISS_5211_SAR5K_RSSI_THR_BMISS_5211_S 8 reg.h 　
1043
 AR5K_RSSI_THR_BMISSAR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \ AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) reg.h 　
1044
 AR5K_RSSI_THR_BMISS_SAR5K_RSSI_THR_BMISS_S 8 reg.h 　
1045
 AR5K_NODCU_RETRY_LMTAR5K_NODCU_RETRY_LMT 0x801c reg.h Register Address
1046
 AR5K_NODCU_RETRY_LMT_SH_RETRYAR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f reg.h Short retry limit mask
1047
 AR5K_NODCU_RETRY_LMT_SH_RETRY_SAR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 reg.h 　
1048
 AR5K_NODCU_RETRY_LMT_LG_RETRYAR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 reg.h Long retry mask
1049
 AR5K_NODCU_RETRY_LMT_LG_RETRY_SAR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 reg.h 　
1050
 AR5K_NODCU_RETRY_LMT_SSH_RETRYAR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 reg.h Station short retry limit mask
1051
 AR5K_NODCU_RETRY_LMT_SSH_RETRY_AR5K_NODCU_RETRY_LMT_SSH_RETRY_ 8 reg.h 　
1052
 AR5K_NODCU_RETRY_LMT_SLG_RETRYAR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 reg.h Station long retry limit mask
1053
 AR5K_NODCU_RETRY_LMT_SLG_RETRY_AR5K_NODCU_RETRY_LMT_SLG_RETRY_ 14 reg.h 　
1054
 AR5K_NODCU_RETRY_LMT_CW_MINAR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 reg.h Minimum contention window mask
1055
 AR5K_NODCU_RETRY_LMT_CW_MIN_SAR5K_NODCU_RETRY_LMT_CW_MIN_S 20 reg.h 　
1056
 AR5K_USEC_5210AR5K_USEC_5210 0x8020 reg.h Register Address [5210]
1057
 AR5K_USEC_5211AR5K_USEC_5211 0x801c reg.h Register Address [5211+]
1058
 AR5K_USECAR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ AR5K_USEC_5210 : AR5K_USEC_5211) reg.h 　
1059
 AR5K_USEC_1AR5K_USEC_1 0x0000007f reg.h clock cycles for 1us
1060
 AR5K_USEC_1_SAR5K_USEC_1_S 0 reg.h 　
1061
 AR5K_USEC_32AR5K_USEC_32 0x00003f80 reg.h clock cycles for 1us while on 32Mhz clock
1062
 AR5K_USEC_32_SAR5K_USEC_32_S 7 reg.h 　
1063
 AR5K_USEC_TX_LATENCY_5211AR5K_USEC_TX_LATENCY_5211 0x007fc000 reg.h 　
1064
 AR5K_USEC_TX_LATENCY_5211_SAR5K_USEC_TX_LATENCY_5211_S 14 reg.h 　
1065
 AR5K_USEC_RX_LATENCY_5211AR5K_USEC_RX_LATENCY_5211 0x1f800000 reg.h 　
1066
 AR5K_USEC_RX_LATENCY_5211_SAR5K_USEC_RX_LATENCY_5211_S 23 reg.h 　
1067
 AR5K_USEC_TX_LATENCY_5210AR5K_USEC_TX_LATENCY_5210 0x000fc000 reg.h also for 5311
1068
 AR5K_USEC_TX_LATENCY_5210_SAR5K_USEC_TX_LATENCY_5210_S 14 reg.h 　
1069
 AR5K_USEC_RX_LATENCY_5210AR5K_USEC_RX_LATENCY_5210 0x03f00000 reg.h also for 5311
1070
 AR5K_USEC_RX_LATENCY_5210_SAR5K_USEC_RX_LATENCY_5210_S 20 reg.h 　
1071
 AR5K_BEACON_5210AR5K_BEACON_5210 0x8024 reg.h Register Address [5210]
1072
 AR5K_BEACON_5211AR5K_BEACON_5211 0x8020 reg.h Register Address [5211+]
1073
 AR5K_BEACONAR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ AR5K_BEACON_5210 : AR5K_BEACON_5211) reg.h 　
1074
 AR5K_BEACON_PERIODAR5K_BEACON_PERIOD 0x0000ffff reg.h Mask for beacon period
1075
 AR5K_BEACON_PERIOD_SAR5K_BEACON_PERIOD_S 0 reg.h 　
1076
 AR5K_BEACON_TIMAR5K_BEACON_TIM 0x007f0000 reg.h Mask for TIM offset
1077
 AR5K_BEACON_TIM_SAR5K_BEACON_TIM_S 16 reg.h 　
1078
 AR5K_BEACON_ENABLEAR5K_BEACON_ENABLE 0x00800000 reg.h Enable beacons
1079
 AR5K_BEACON_RESET_TSFAR5K_BEACON_RESET_TSF 0x01000000 reg.h Force TSF reset
1080
 AR5K_CFP_PERIOD_5210AR5K_CFP_PERIOD_5210 0x8028 reg.h 　
1081
 AR5K_CFP_PERIOD_5211AR5K_CFP_PERIOD_5211 0x8024 reg.h 　
1082
 AR5K_CFP_PERIODAR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \ AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) reg.h 　
1083
 AR5K_TIMER0_5210AR5K_TIMER0_5210 0x802c reg.h 　
1084
 AR5K_TIMER0_5211AR5K_TIMER0_5211 0x8028 reg.h 　
1085
 AR5K_TIMER0AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER0_5210 : AR5K_TIMER0_5211) reg.h 　
1086
 AR5K_TIMER1_5210AR5K_TIMER1_5210 0x8030 reg.h 　
1087
 AR5K_TIMER1_5211AR5K_TIMER1_5211 0x802c reg.h 　
1088
 AR5K_TIMER1AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER1_5210 : AR5K_TIMER1_5211) reg.h 　
1089
 AR5K_TIMER2_5210AR5K_TIMER2_5210 0x8034 reg.h 　
1090
 AR5K_TIMER2_5211AR5K_TIMER2_5211 0x8030 reg.h 　
1091
 AR5K_TIMER2AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER2_5210 : AR5K_TIMER2_5211) reg.h 　
1092
 AR5K_TIMER3_5210AR5K_TIMER3_5210 0x8038 reg.h 　
1093
 AR5K_TIMER3_5211AR5K_TIMER3_5211 0x8034 reg.h 　
1094
 AR5K_TIMER3AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER3_5210 : AR5K_TIMER3_5211) reg.h 　
1095
 AR5K_IFS0AR5K_IFS0 0x8040 reg.h 　
1096
 AR5K_IFS0_SIFSAR5K_IFS0_SIFS 0x000007ff reg.h 　
1097
 AR5K_IFS0_SIFS_SAR5K_IFS0_SIFS_S 0 reg.h 　
1098
 AR5K_IFS0_DIFSAR5K_IFS0_DIFS 0x007ff800 reg.h 　
1099
 AR5K_IFS0_DIFS_SAR5K_IFS0_DIFS_S 11 reg.h 　
1100
 AR5K_IFS1AR5K_IFS1 0x8044 reg.h 　
1101
 AR5K_IFS1_PIFSAR5K_IFS1_PIFS 0x00000fff reg.h 　
1102
 AR5K_IFS1_PIFS_SAR5K_IFS1_PIFS_S 0 reg.h 　
1103
 AR5K_IFS1_EIFSAR5K_IFS1_EIFS 0x03fff000 reg.h 　
1104
 AR5K_IFS1_EIFS_SAR5K_IFS1_EIFS_S 12 reg.h 　
1105
 AR5K_IFS1_CS_ENAR5K_IFS1_CS_EN 0x04000000 reg.h 　
1106
 AR5K_CFP_DUR_5210AR5K_CFP_DUR_5210 0x8048 reg.h 　
1107
 AR5K_CFP_DUR_5211AR5K_CFP_DUR_5211 0x8038 reg.h 　
1108
 AR5K_CFP_DURAR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \ AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) reg.h 　
1109
 AR5K_RX_FILTER_5210AR5K_RX_FILTER_5210 0x804c reg.h Register Address [5210]
1110
 AR5K_RX_FILTER_5211AR5K_RX_FILTER_5211 0x803c reg.h Register Address [5211+]
1111
 AR5K_RX_FILTERAR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) reg.h 　
1112
 AR5K_RX_FILTER_UCASTAR5K_RX_FILTER_UCAST 0x00000001 reg.h Don't filter unicast frames
1113
 AR5K_RX_FILTER_MCASTAR5K_RX_FILTER_MCAST 0x00000002 reg.h Don't filter multicast frames
1114
 AR5K_RX_FILTER_BCASTAR5K_RX_FILTER_BCAST 0x00000004 reg.h Don't filter broadcast frames
1115
 AR5K_RX_FILTER_CONTROLAR5K_RX_FILTER_CONTROL 0x00000008 reg.h Don't filter control frames
1116
 AR5K_RX_FILTER_BEACONAR5K_RX_FILTER_BEACON 0x00000010 reg.h Don't filter beacon frames
1117
 AR5K_RX_FILTER_PROMAR5K_RX_FILTER_PROM 0x00000020 reg.h Set promiscuous mode
1118
 AR5K_RX_FILTER_XRPOLLAR5K_RX_FILTER_XRPOLL 0x00000040 reg.h Don't filter XR poll frame [5212+]
1119
 AR5K_RX_FILTER_PROBEREQAR5K_RX_FILTER_PROBEREQ 0x00000080 reg.h Don't filter probe requests [5212+]
1120
 AR5K_RX_FILTER_PHYERR_5212AR5K_RX_FILTER_PHYERR_5212 0x00000100 reg.h Don't filter phy errors [5212+]
1121
 AR5K_RX_FILTER_RADARERR_5212AR5K_RX_FILTER_RADARERR_5212 0x00000200 reg.h Don't filter phy radar errors [5212+]
1122
 AR5K_RX_FILTER_PHYERR_5211AR5K_RX_FILTER_PHYERR_5211 0x00000040 reg.h [5211]
1123
 AR5K_RX_FILTER_RADARERR_5211AR5K_RX_FILTER_RADARERR_5211 0x00000080 reg.h [5211]
1124
 AR5K_RX_FILTER_PHYERRAR5K_RX_FILTER_PHYERR ((ah->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212)) reg.h 　
1125
 AR5K_RX_FILTER_RADARERRAR5K_RX_FILTER_RADARERR ((ah->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212)) reg.h 　
1126
 AR5K_MCAST_FILTER0_5210AR5K_MCAST_FILTER0_5210 0x8050 reg.h 　
1127
 AR5K_MCAST_FILTER0_5211AR5K_MCAST_FILTER0_5211 0x8040 reg.h 　
1128
 AR5K_MCAST_FILTER0AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) reg.h 　
1129
 AR5K_MCAST_FILTER1_5210AR5K_MCAST_FILTER1_5210 0x8054 reg.h 　
1130
 AR5K_MCAST_FILTER1_5211AR5K_MCAST_FILTER1_5211 0x8044 reg.h 　
1131
 AR5K_MCAST_FILTER1AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \ AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) reg.h 　
1132
 AR5K_TX_MASK0AR5K_TX_MASK0 0x8058 reg.h 　
1133
 AR5K_TX_MASK1AR5K_TX_MASK1 0x805c reg.h 　
1134
 AR5K_CLR_TMASKAR5K_CLR_TMASK 0x8060 reg.h 　
1135
 AR5K_TRIG_LVLAR5K_TRIG_LVL 0x8064 reg.h 　
1136
 AR5K_DIAG_SW_5210AR5K_DIAG_SW_5210 0x8068 reg.h Register Address [5210]
1137
 AR5K_DIAG_SW_5211AR5K_DIAG_SW_5211 0x8048 reg.h Register Address [5211+]
1138
 AR5K_DIAG_SWAR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) reg.h 　
1139
 AR5K_DIAG_SW_DIS_WEP_ACKAR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 reg.h Disable ACKs if WEP key is invalid
1140
 AR5K_DIAG_SW_DIS_ACKAR5K_DIAG_SW_DIS_ACK 0x00000002 reg.h Disable ACKs
1141
 AR5K_DIAG_SW_DIS_CTSAR5K_DIAG_SW_DIS_CTS 0x00000004 reg.h Disable CTSs
1142
 AR5K_DIAG_SW_DIS_ENCAR5K_DIAG_SW_DIS_ENC 0x00000008 reg.h Disable encryption
1143
 AR5K_DIAG_SW_DIS_DECAR5K_DIAG_SW_DIS_DEC 0x00000010 reg.h Disable decryption
1144
 AR5K_DIAG_SW_DIS_TXAR5K_DIAG_SW_DIS_TX 0x00000020 reg.h Disable transmit [5210]
1145
 AR5K_DIAG_SW_DIS_RX_5210AR5K_DIAG_SW_DIS_RX_5210 0x00000040 reg.h Disable recieve
1146
 AR5K_DIAG_SW_DIS_RX_5211AR5K_DIAG_SW_DIS_RX_5211 0x00000020 reg.h 　
1147
 AR5K_DIAG_SW_DIS_RXAR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) reg.h 　
1148
 AR5K_DIAG_SW_LOOP_BACK_5210AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 reg.h Loopback (i guess it goes with DIS_TX) [5210]
1149
 AR5K_DIAG_SW_LOOP_BACK_5211AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 reg.h 　
1150
 AR5K_DIAG_SW_LOOP_BACKAR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) reg.h 　
1151
 AR5K_DIAG_SW_CORR_FCS_5210AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 reg.h Corrupted FCS
1152
 AR5K_DIAG_SW_CORR_FCS_5211AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 reg.h 　
1153
 AR5K_DIAG_SW_CORR_FCSAR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) reg.h 　
1154
 AR5K_DIAG_SW_CHAN_INFO_5210AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 reg.h Dump channel info
1155
 AR5K_DIAG_SW_CHAN_INFO_5211AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 reg.h 　
1156
 AR5K_DIAG_SW_CHAN_INFOAR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) reg.h 　
1157
 AR5K_DIAG_SW_EN_SCRAM_SEED_5210AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 reg.h Enable fixed scrambler seed
1158
 AR5K_DIAG_SW_EN_SCRAM_SEED_5211AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 reg.h 　
1159
 AR5K_DIAG_SW_EN_SCRAM_SEEDAR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) reg.h 　
1160
 AR5K_DIAG_SW_ECO_ENABLEAR5K_DIAG_SW_ECO_ENABLE 0x00000400 reg.h [5211+]
1161
 AR5K_DIAG_SW_SCVRAM_SEEDAR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 reg.h [5210]
1162
 AR5K_DIAG_SW_SCRAM_SEED_MAR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 reg.h Scrambler seed mask
1163
 AR5K_DIAG_SW_SCRAM_SEED_SAR5K_DIAG_SW_SCRAM_SEED_S 10 reg.h 　
1164
 AR5K_DIAG_SW_DIS_SEQ_INCAR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 reg.h Disable seqnum increment (?)[5210]
1165
 AR5K_DIAG_SW_FRAME_NV0_5210AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 reg.h 　
1166
 AR5K_DIAG_SW_FRAME_NV0_5211AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 reg.h Accept frames of non-zero protocol number
1167
 AR5K_DIAG_SW_FRAME_NV0AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) reg.h 　
1168
 AR5K_DIAG_SW_OBSPT_MAR5K_DIAG_SW_OBSPT_M 0x000c0000 reg.h Observation point select (?)
1169
 AR5K_DIAG_SW_OBSPT_SAR5K_DIAG_SW_OBSPT_S 18 reg.h 　
1170
 AR5K_DIAG_SW_RX_CLEAR_HIGHAR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 reg.h Force RX Clear high
1171
 AR5K_DIAG_SW_IGNORE_CARR_SENSEAR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 reg.h Ignore virtual carrier sense
1172
 AR5K_DIAG_SW_CHANEL_IDLE_HIGHAR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 reg.h Force channel idle high
1173
 AR5K_DIAG_SW_PHEAR_MEAR5K_DIAG_SW_PHEAR_ME 0x0080000 reg.h ???
1174
 AR5K_TSF_L32_5210AR5K_TSF_L32_5210 0x806c reg.h 　
1175
 AR5K_TSF_L32_5211AR5K_TSF_L32_5211 0x804c reg.h 　
1176
 AR5K_TSF_L32AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) reg.h 　
1177
 AR5K_TSF_U32_5210AR5K_TSF_U32_5210 0x8070 reg.h 　
1178
 AR5K_TSF_U32_5211AR5K_TSF_U32_5211 0x8050 reg.h 　
1179
 AR5K_TSF_U32AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) reg.h 　
1180
 AR5K_LAST_TSTPAR5K_LAST_TSTP 0x8080 reg.h 　
1181
 AR5K_ADDAC_TESTAR5K_ADDAC_TEST 0x8054 reg.h Register Address
1182
 AR5K_ADDAC_TEST_TXCONTAR5K_ADDAC_TEST_TXCONT 0x00000001 reg.h Test continuous tx
1183
 AR5K_ADDAC_TEST_TST_MODEAR5K_ADDAC_TEST_TST_MODE 0x00000002 reg.h Test mode
1184
 AR5K_ADDAC_TEST_LOOP_ENAR5K_ADDAC_TEST_LOOP_EN 0x00000004 reg.h Enable loop
1185
 AR5K_ADDAC_TEST_LOOP_LENAR5K_ADDAC_TEST_LOOP_LEN 0x00000008 reg.h Loop length (field)
1186
 AR5K_ADDAC_TEST_USE_U8AR5K_ADDAC_TEST_USE_U8 0x00004000 reg.h Use upper 8 bits
1187
 AR5K_ADDAC_TEST_MSBAR5K_ADDAC_TEST_MSB 0x00008000 reg.h State of MSB
1188
 AR5K_ADDAC_TEST_TRIG_SELAR5K_ADDAC_TEST_TRIG_SEL 0x00010000 reg.h Trigger select
1189
 AR5K_ADDAC_TEST_TRIG_PTYAR5K_ADDAC_TEST_TRIG_PTY 0x00020000 reg.h Trigger polarity
1190
 AR5K_ADDAC_TEST_RXCONTAR5K_ADDAC_TEST_RXCONT 0x00040000 reg.h Continuous capture
1191
 AR5K_ADDAC_TEST_CAPTUREAR5K_ADDAC_TEST_CAPTURE 0x00080000 reg.h Begin capture
1192
 AR5K_ADDAC_TEST_TST_ARMAR5K_ADDAC_TEST_TST_ARM 0x00100000 reg.h ARM rx buffer for capture
1193
 AR5K_DEFAULT_ANTENNAAR5K_DEFAULT_ANTENNA 0x8058 reg.h 　
1194
 AR5K_FRAME_CTL_QOSMAR5K_FRAME_CTL_QOSM 0x805c reg.h 　
1195
 AR5K_SEQ_MASKAR5K_SEQ_MASK 0x8060 reg.h 　
1196
 AR5K_RETRY_CNTAR5K_RETRY_CNT 0x8084 reg.h Register Address [5210]
1197
 AR5K_RETRY_CNT_SSHAR5K_RETRY_CNT_SSH 0x0000003f reg.h Station short retry count (?)
1198
 AR5K_RETRY_CNT_SLGAR5K_RETRY_CNT_SLG 0x00000fc0 reg.h Station long retry count (?)
1199
 AR5K_BACKOFFAR5K_BACKOFF 0x8088 reg.h Register Address [5210]
1200
 AR5K_BACKOFF_CWAR5K_BACKOFF_CW 0x000003ff reg.h Backoff Contention Window (?)
1201
 AR5K_BACKOFF_CNTAR5K_BACKOFF_CNT 0x03ff0000 reg.h Backoff count (?)
1202
 AR5K_NAV_5210AR5K_NAV_5210 0x808c reg.h 　
1203
 AR5K_NAV_5211AR5K_NAV_5211 0x8084 reg.h 　
1204
 AR5K_NAVAR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ AR5K_NAV_5210 : AR5K_NAV_5211) reg.h 　
1205
 AR5K_RTS_OK_5210AR5K_RTS_OK_5210 0x8090 reg.h 　
1206
 AR5K_RTS_OK_5211AR5K_RTS_OK_5211 0x8088 reg.h 　
1207
 AR5K_RTS_OKAR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) reg.h 　
1208
 AR5K_RTS_FAIL_5210AR5K_RTS_FAIL_5210 0x8094 reg.h 　
1209
 AR5K_RTS_FAIL_5211AR5K_RTS_FAIL_5211 0x808c reg.h 　
1210
 AR5K_RTS_FAILAR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) reg.h 　
1211
 AR5K_ACK_FAIL_5210AR5K_ACK_FAIL_5210 0x8098 reg.h 　
1212
 AR5K_ACK_FAIL_5211AR5K_ACK_FAIL_5211 0x8090 reg.h 　
1213
 AR5K_ACK_FAILAR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) reg.h 　
1214
 AR5K_FCS_FAIL_5210AR5K_FCS_FAIL_5210 0x809c reg.h 　
1215
 AR5K_FCS_FAIL_5211AR5K_FCS_FAIL_5211 0x8094 reg.h 　
1216
 AR5K_FCS_FAILAR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) reg.h 　
1217
 AR5K_BEACON_CNT_5210AR5K_BEACON_CNT_5210 0x80a0 reg.h 　
1218
 AR5K_BEACON_CNT_5211AR5K_BEACON_CNT_5211 0x8098 reg.h 　
1219
 AR5K_BEACON_CNTAR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \ AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) reg.h 　
1220
 AR5K_TPCAR5K_TPC 0x80e8 reg.h 　
1221
 AR5K_TPC_ACKAR5K_TPC_ACK 0x0000003f reg.h ack frames
1222
 AR5K_TPC_ACK_SAR5K_TPC_ACK_S 0 reg.h 　
1223
 AR5K_TPC_CTSAR5K_TPC_CTS 0x00003f00 reg.h cts frames
1224
 AR5K_TPC_CTS_SAR5K_TPC_CTS_S 8 reg.h 　
1225
 AR5K_TPC_CHIRPAR5K_TPC_CHIRP 0x003f0000 reg.h chirp frames
1226
 AR5K_TPC_CHIRP_SAR5K_TPC_CHIRP_S 16 reg.h 　
1227
 AR5K_TPC_DOPPLERAR5K_TPC_DOPPLER 0x0f000000 reg.h doppler chirp span
1228
 AR5K_TPC_DOPPLER_SAR5K_TPC_DOPPLER_S 24 reg.h 　
1229
 AR5K_XRMODEAR5K_XRMODE 0x80c0 reg.h Register Address
1230
 AR5K_XRMODE_POLL_TYPE_MAR5K_XRMODE_POLL_TYPE_M 0x0000003f reg.h Mask for Poll type (?)
1231
 AR5K_XRMODE_POLL_TYPE_SAR5K_XRMODE_POLL_TYPE_S 0 reg.h 　
1232
 AR5K_XRMODE_POLL_SUBTYPE_MAR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c reg.h Mask for Poll subtype (?)
1233
 AR5K_XRMODE_POLL_SUBTYPE_SAR5K_XRMODE_POLL_SUBTYPE_S 2 reg.h 　
1234
 AR5K_XRMODE_POLL_WAIT_ALLAR5K_XRMODE_POLL_WAIT_ALL 0x00000080 reg.h Wait for poll
1235
 AR5K_XRMODE_SIFS_DELAYAR5K_XRMODE_SIFS_DELAY 0x000fff00 reg.h Mask for SIFS delay
1236
 AR5K_XRMODE_FRAME_HOLD_MAR5K_XRMODE_FRAME_HOLD_M 0xfff00000 reg.h Mask for frame hold (?)
1237
 AR5K_XRMODE_FRAME_HOLD_SAR5K_XRMODE_FRAME_HOLD_S 20 reg.h 　
1238
 AR5K_XRDELAYAR5K_XRDELAY 0x80c4 reg.h Register Address
1239
 AR5K_XRDELAY_SLOT_DELAY_MAR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff reg.h Mask for slot delay
1240
 AR5K_XRDELAY_SLOT_DELAY_SAR5K_XRDELAY_SLOT_DELAY_S 0 reg.h 　
1241
 AR5K_XRDELAY_CHIRP_DELAY_MAR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 reg.h Mask for CHIRP data delay
1242
 AR5K_XRDELAY_CHIRP_DELAY_SAR5K_XRDELAY_CHIRP_DELAY_S 16 reg.h 　
1243
 AR5K_XRTIMEOUTAR5K_XRTIMEOUT 0x80c8 reg.h Register Address
1244
 AR5K_XRTIMEOUT_CHIRP_MAR5K_XRTIMEOUT_CHIRP_M 0x0000ffff reg.h Mask for CHIRP timeout
1245
 AR5K_XRTIMEOUT_CHIRP_SAR5K_XRTIMEOUT_CHIRP_S 0 reg.h 　
1246
 AR5K_XRTIMEOUT_POLL_MAR5K_XRTIMEOUT_POLL_M 0xffff0000 reg.h Mask for Poll timeout
1247
 AR5K_XRTIMEOUT_POLL_SAR5K_XRTIMEOUT_POLL_S 16 reg.h 　
1248
 AR5K_XRCHIRPAR5K_XRCHIRP 0x80cc reg.h Register Address
1249
 AR5K_XRCHIRP_SENDAR5K_XRCHIRP_SEND 0x00000001 reg.h Send CHIRP
1250
 AR5K_XRCHIRP_GAPAR5K_XRCHIRP_GAP 0xffff0000 reg.h Mask for CHIRP gap (?)
1251
 AR5K_XRSTOMPAR5K_XRSTOMP 0x80d0 reg.h Register Address
1252
 AR5K_XRSTOMP_TXAR5K_XRSTOMP_TX 0x00000001 reg.h Stomp Tx (?)
1253
 AR5K_XRSTOMP_RXAR5K_XRSTOMP_RX 0x00000002 reg.h Stomp Rx (?)
1254
 AR5K_XRSTOMP_TX_RSSIAR5K_XRSTOMP_TX_RSSI 0x00000004 reg.h Stomp Tx RSSI (?)
1255
 AR5K_XRSTOMP_TX_BSSIDAR5K_XRSTOMP_TX_BSSID 0x00000008 reg.h Stomp Tx BSSID (?)
1256
 AR5K_XRSTOMP_DATAAR5K_XRSTOMP_DATA 0x00000010 reg.h Stomp data (?)
1257
 AR5K_XRSTOMP_RSSI_THRESAR5K_XRSTOMP_RSSI_THRES 0x0000ff00 reg.h Mask for XR RSSI threshold
1258
 AR5K_SLEEP0AR5K_SLEEP0 0x80d4 reg.h Register Address
1259
 AR5K_SLEEP0_NEXT_DTIMAR5K_SLEEP0_NEXT_DTIM 0x0007ffff reg.h Mask for next DTIM (?)
1260
 AR5K_SLEEP0_NEXT_DTIM_SAR5K_SLEEP0_NEXT_DTIM_S 0 reg.h 　
1261
 AR5K_SLEEP0_ASSUME_DTIMAR5K_SLEEP0_ASSUME_DTIM 0x00080000 reg.h Assume DTIM
1262
 AR5K_SLEEP0_ENH_SLEEP_ENAR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 reg.h Enable enchanced sleep control
1263
 AR5K_SLEEP0_CABTOAR5K_SLEEP0_CABTO 0xff000000 reg.h Mask for CAB Time Out
1264
 AR5K_SLEEP0_CABTO_SAR5K_SLEEP0_CABTO_S 24 reg.h 　
1265
 AR5K_SLEEP1AR5K_SLEEP1 0x80d8 reg.h Register Address
1266
 AR5K_SLEEP1_NEXT_TIMAR5K_SLEEP1_NEXT_TIM 0x0007ffff reg.h Mask for next TIM (?)
1267
 AR5K_SLEEP1_NEXT_TIM_SAR5K_SLEEP1_NEXT_TIM_S 0 reg.h 　
1268
 AR5K_SLEEP1_BEACON_TOAR5K_SLEEP1_BEACON_TO 0xff000000 reg.h Mask for Beacon Time Out
1269
 AR5K_SLEEP1_BEACON_TO_SAR5K_SLEEP1_BEACON_TO_S 24 reg.h 　
1270
 AR5K_SLEEP2AR5K_SLEEP2 0x80dc reg.h Register Address
1271
 AR5K_SLEEP2_TIM_PERAR5K_SLEEP2_TIM_PER 0x0000ffff reg.h Mask for TIM period (?)
1272
 AR5K_SLEEP2_TIM_PER_SAR5K_SLEEP2_TIM_PER_S 0 reg.h 　
1273
 AR5K_SLEEP2_DTIM_PERAR5K_SLEEP2_DTIM_PER 0xffff0000 reg.h Mask for DTIM period (?)
1274
 AR5K_SLEEP2_DTIM_PER_SAR5K_SLEEP2_DTIM_PER_S 16 reg.h 　
1275
 AR5K_BSS_IDM0AR5K_BSS_IDM0 0x80e0 reg.h Upper bits
1276
 AR5K_BSS_IDM1AR5K_BSS_IDM1 0x80e4 reg.h Lower bits
1277
 AR5K_TXPCAR5K_TXPC 0x80e8 reg.h Register Address
1278
 AR5K_TXPC_ACK_MAR5K_TXPC_ACK_M 0x0000003f reg.h ACK tx power
1279
 AR5K_TXPC_ACK_SAR5K_TXPC_ACK_S 0 reg.h 　
1280
 AR5K_TXPC_CTS_MAR5K_TXPC_CTS_M 0x00003f00 reg.h CTS tx power
1281
 AR5K_TXPC_CTS_SAR5K_TXPC_CTS_S 8 reg.h 　
1282
 AR5K_TXPC_CHIRP_MAR5K_TXPC_CHIRP_M 0x003f0000 reg.h CHIRP tx power
1283
 AR5K_TXPC_CHIRP_SAR5K_TXPC_CHIRP_S 16 reg.h 　
1284
 AR5K_TXPC_DOPPLERAR5K_TXPC_DOPPLER 0x0f000000 reg.h Doppler chirp span (?)
1285
 AR5K_TXPC_DOPPLER_SAR5K_TXPC_DOPPLER_S 24 reg.h 　
1286
 AR5K_PROFCNT_TXAR5K_PROFCNT_TX 0x80ec reg.h Tx count
1287
 AR5K_PROFCNT_RXAR5K_PROFCNT_RX 0x80f0 reg.h Rx count
1288
 AR5K_PROFCNT_RXCLRAR5K_PROFCNT_RXCLR 0x80f4 reg.h Clear Rx count
1289
 AR5K_PROFCNT_CYCLEAR5K_PROFCNT_CYCLE 0x80f8 reg.h Cycle count (?)
1290
 AR5K_QUIET_CTL1AR5K_QUIET_CTL1 0x80fc reg.h Register Address
1291
 AR5K_QUIET_CTL1_NEXT_QT_TSFAR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff reg.h Next quiet period TSF (TU)
1292
 AR5K_QUIET_CTL1_NEXT_QT_TSF_SAR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 reg.h 　
1293
 AR5K_QUIET_CTL1_QT_ENAR5K_QUIET_CTL1_QT_EN 0x00010000 reg.h Enable quiet period
1294
 AR5K_QUIET_CTL1_ACK_CTS_ENAR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 reg.h Send ACK/CTS during quiet period
1295
 AR5K_QUIET_CTL2AR5K_QUIET_CTL2 0x8100 reg.h Register Address
1296
 AR5K_QUIET_CTL2_QT_PERAR5K_QUIET_CTL2_QT_PER 0x0000ffff reg.h Mask for quiet period periodicity
1297
 AR5K_QUIET_CTL2_QT_PER_SAR5K_QUIET_CTL2_QT_PER_S 0 reg.h 　
1298
 AR5K_QUIET_CTL2_QT_DURAR5K_QUIET_CTL2_QT_DUR 0xffff0000 reg.h Mask for quiet period duration
1299
 AR5K_QUIET_CTL2_QT_DUR_SAR5K_QUIET_CTL2_QT_DUR_S 16 reg.h 　
1300
 AR5K_TSF_PARMAR5K_TSF_PARM 0x8104 reg.h Register Address
1301
 AR5K_TSF_PARM_INCAR5K_TSF_PARM_INC 0x000000ff reg.h Mask for TSF increment
1302
 AR5K_TSF_PARM_INC_SAR5K_TSF_PARM_INC_S 0 reg.h 　
1303
 AR5K_QOS_NOACKAR5K_QOS_NOACK 0x8108 reg.h Register Address
1304
 AR5K_QOS_NOACK_2BIT_VALUESAR5K_QOS_NOACK_2BIT_VALUES 0x0000000f reg.h ???
1305
 AR5K_QOS_NOACK_2BIT_VALUES_SAR5K_QOS_NOACK_2BIT_VALUES_S 0 reg.h 　
1306
 AR5K_QOS_NOACK_BIT_OFFSETAR5K_QOS_NOACK_BIT_OFFSET 0x00000070 reg.h ???
1307
 AR5K_QOS_NOACK_BIT_OFFSET_SAR5K_QOS_NOACK_BIT_OFFSET_S 4 reg.h 　
1308
 AR5K_QOS_NOACK_BYTE_OFFSETAR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 reg.h ???
1309
 AR5K_QOS_NOACK_BYTE_OFFSET_SAR5K_QOS_NOACK_BYTE_OFFSET_S 7 reg.h 　
1310
 AR5K_PHY_ERR_FILAR5K_PHY_ERR_FIL 0x810c reg.h 　
1311
 AR5K_PHY_ERR_FIL_RADARAR5K_PHY_ERR_FIL_RADAR 0x00000020 reg.h Radar signal
1312
 AR5K_PHY_ERR_FIL_OFDMAR5K_PHY_ERR_FIL_OFDM 0x00020000 reg.h OFDM false detect (ANI)
1313
 AR5K_PHY_ERR_FIL_CCKAR5K_PHY_ERR_FIL_CCK 0x02000000 reg.h CCK false detect (ANI)
1314
 AR5K_XRLAT_TXAR5K_XRLAT_TX 0x8110 reg.h 　
1315
 AR5K_ACKSIFSAR5K_ACKSIFS 0x8114 reg.h Register Address
1316
 AR5K_ACKSIFS_INCAR5K_ACKSIFS_INC 0x00000000 reg.h ACK SIFS Increment (field)
1317
 AR5K_MIC_QOS_CTLAR5K_MIC_QOS_CTL 0x8118 reg.h Register Address
1318
 AR5K_MIC_QOS_CTL_MQ_ENAR5K_MIC_QOS_CTL_MQ_EN 0x00010000 reg.h Enable MIC QoS
1319
 AR5K_MIC_QOS_SELAR5K_MIC_QOS_SEL 0x811c reg.h 　
1320
 AR5K_MISC_MODEAR5K_MISC_MODE 0x8120 reg.h Register Address
1321
 AR5K_MISC_MODE_FBSSID_MATCHAR5K_MISC_MODE_FBSSID_MATCH 0x00000001 reg.h Force BSSID match
1322
 AR5K_MISC_MODE_ACKSIFS_MEMAR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 reg.h ACK SIFS memory (?)
1323
 AR5K_MISC_MODE_COMBINED_MICAR5K_MISC_MODE_COMBINED_MIC 0x00000004 reg.h use rx/tx MIC key
1324
 AR5K_OFDM_FIL_CNTAR5K_OFDM_FIL_CNT 0x8124 reg.h 　
1325
 AR5K_CCK_FIL_CNTAR5K_CCK_FIL_CNT 0x8128 reg.h 　
1326
 AR5K_PHYERR_CNT1AR5K_PHYERR_CNT1 0x812c reg.h 　
1327
 AR5K_PHYERR_CNT1_MASKAR5K_PHYERR_CNT1_MASK 0x8130 reg.h 　
1328
 AR5K_PHYERR_CNT2AR5K_PHYERR_CNT2 0x8134 reg.h 　
1329
 AR5K_PHYERR_CNT2_MASKAR5K_PHYERR_CNT2_MASK 0x8138 reg.h 　
1330
 AR5K_TSF_THRESAR5K_TSF_THRES 0x813c reg.h 　
1331
 AR5K_RATE_ACKSIFS_BASEAR5K_RATE_ACKSIFS_BASE 0x8680 reg.h Register Address
1332
 AR5K_RATE_ACKSIFS_NORMALAR5K_RATE_ACKSIFS_NORMAL 0x00000001 reg.h Normal SIFS (field)
1333
 AR5K_RATE_ACKSIFS_TURBOAR5K_RATE_ACKSIFS_TURBO 0x00000400 reg.h Turbo SIFS (field)
1334
 AR5K_RATE_DUR_BASEAR5K_RATE_DUR_BASE 0x8700 reg.h 　
1335
 AR5K_RATE2DB_BASEAR5K_RATE2DB_BASE 0x87c0 reg.h 　
1336
 AR5K_DB2RATE_BASEAR5K_DB2RATE_BASE 0x87e0 reg.h 　
1337
 AR5K_KEYTABLE_0_5210AR5K_KEYTABLE_0_5210 0x9000 reg.h 　
1338
 AR5K_KEYTABLE_0_5211AR5K_KEYTABLE_0_5211 0x8800 reg.h 　
1339
 AR5K_KEYTABLE_TYPE_40AR5K_KEYTABLE_TYPE_40 0x00000000 reg.h 　
1340
 AR5K_KEYTABLE_TYPE_104AR5K_KEYTABLE_TYPE_104 0x00000001 reg.h 　
1341
 AR5K_KEYTABLE_TYPE_128AR5K_KEYTABLE_TYPE_128 0x00000003 reg.h 　
1342
 AR5K_KEYTABLE_TYPE_TKIPAR5K_KEYTABLE_TYPE_TKIP 0x00000004 reg.h [5212+]
1343
 AR5K_KEYTABLE_TYPE_AESAR5K_KEYTABLE_TYPE_AES 0x00000005 reg.h [5211+]
1344
 AR5K_KEYTABLE_TYPE_CCMAR5K_KEYTABLE_TYPE_CCM 0x00000006 reg.h [5212+]
1345
 AR5K_KEYTABLE_TYPE_NULLAR5K_KEYTABLE_TYPE_NULL 0x00000007 reg.h [5211+]
1346
 AR5K_KEYTABLE_ANTENNAAR5K_KEYTABLE_ANTENNA 0x00000008 reg.h [5212+]
1347
 AR5K_KEYTABLE_VALIDAR5K_KEYTABLE_VALID 0x00008000 reg.h 　
1348
 AR5K_KEYTABLE_MIC_OFFSETAR5K_KEYTABLE_MIC_OFFSET 64 reg.h 　
1349
 AR5K_KEYTABLE_SIZE_5210AR5K_KEYTABLE_SIZE_5210 64 reg.h 　
1350
 AR5K_KEYTABLE_SIZE_5211AR5K_KEYTABLE_SIZE_5211 128 reg.h 　
1351
 AR5K_KEYTABLE_SIZEAR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \ AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) reg.h 　
1352
 AR5K_PHY_BASEAR5K_PHY_BASE 0x9800 reg.h 　
1353
 AR5K_PHY_TST2AR5K_PHY_TST2 0x9800 reg.h Register Address
1354
 AR5K_PHY_TST2_TRIG_SELAR5K_PHY_TST2_TRIG_SEL 0x00000007 reg.h Trigger select (?)
1355
 AR5K_PHY_TST2_TRIGAR5K_PHY_TST2_TRIG 0x00000010 reg.h Trigger (?)
1356
 AR5K_PHY_TST2_CBUS_MODEAR5K_PHY_TST2_CBUS_MODE 0x00000060 reg.h Cardbus mode (?)
1357
 AR5K_PHY_TST2_CLK32AR5K_PHY_TST2_CLK32 0x00000400 reg.h CLK_OUT is CLK32 (32Khz external)
1358
 AR5K_PHY_TST2_CHANCOR_DUMP_ENAR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 reg.h Enable Chancor dump (?)
1359
 AR5K_PHY_TST2_EVEN_CHANCOR_DUMPAR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 reg.h Even Chancor dump (?)
1360
 AR5K_PHY_TST2_RFSILENT_ENAR5K_PHY_TST2_RFSILENT_EN 0x00002000 reg.h Enable RFSILENT
1361
 AR5K_PHY_TST2_ALT_RFDATAAR5K_PHY_TST2_ALT_RFDATA 0x00004000 reg.h Alternate RFDATA (5-2GHz switch ?)
1362
 AR5K_PHY_TST2_MINI_OBS_ENAR5K_PHY_TST2_MINI_OBS_EN 0x00008000 reg.h Enable mini OBS (?)
1363
 AR5K_PHY_TST2_RX2_IS_RX5_INVAR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 reg.h 2GHz rx path is the 5GHz path inverted (?)
1364
 AR5K_PHY_TST2_SLOW_CLK160AR5K_PHY_TST2_SLOW_CLK160 0x00020000 reg.h Slow CLK160 (?)
1365
 AR5K_PHY_TST2_AGC_OBS_SEL_3AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 reg.h AGC OBS Select 3 (?)
1366
 AR5K_PHY_TST2_BBB_OBS_SELAR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 reg.h BB OBS Select (field ?)
1367
 AR5K_PHY_TST2_ADC_OBS_SELAR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 reg.h ADC OBS Select (field ?)
1368
 AR5K_PHY_TST2_RX_CLR_SELAR5K_PHY_TST2_RX_CLR_SEL 0x08000000 reg.h RX Clear Select (?)
1369
 AR5K_PHY_TST2_FORCE_AGC_CLRAR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 reg.h Force AGC clear (?)
1370
 AR5K_PHY_SHIFT_2GHZAR5K_PHY_SHIFT_2GHZ 0x00004007 reg.h Used to access 2GHz radios
1371
 AR5K_PHY_SHIFT_5GHZAR5K_PHY_SHIFT_5GHZ 0x00000007 reg.h Used to access 5GHz radios (default)
1372
 AR5K_PHY_TURBOAR5K_PHY_TURBO 0x9804 reg.h Register Address
1373
 AR5K_PHY_TURBO_MODEAR5K_PHY_TURBO_MODE 0x00000001 reg.h Enable turbo mode
1374
 AR5K_PHY_TURBO_SHORTAR5K_PHY_TURBO_SHORT 0x00000002 reg.h Set short symbols to turbo mode
1375
 AR5K_PHY_TURBO_MIMOAR5K_PHY_TURBO_MIMO 0x00000004 reg.h Set turbo for mimo mimo
1376
 AR5K_PHY_AGCAR5K_PHY_AGC 0x9808 reg.h Register Address
1377
 AR5K_PHY_TST1AR5K_PHY_TST1 0x9808 reg.h 　
1378
 AR5K_PHY_AGC_DISABLEAR5K_PHY_AGC_DISABLE 0x08000000 reg.h Disable AGC to A2 (?)
1379
 AR5K_PHY_TST1_TXHOLDAR5K_PHY_TST1_TXHOLD 0x00003800 reg.h Set tx hold (?)
1380
 AR5K_PHY_TST1_TXSRC_SRCAR5K_PHY_TST1_TXSRC_SRC 0x00000002 reg.h Used with bit 7 (?)
1381
 AR5K_PHY_TST1_TXSRC_SRC_SAR5K_PHY_TST1_TXSRC_SRC_S 1 reg.h 　
1382
 AR5K_PHY_TST1_TXSRC_ALTAR5K_PHY_TST1_TXSRC_ALT 0x00000080 reg.h Set input to tsdac (?)
1383
 AR5K_PHY_TST1_TXSRC_ALT_SAR5K_PHY_TST1_TXSRC_ALT_S 7 reg.h 　
1384
 AR5K_PHY_TIMING_3AR5K_PHY_TIMING_3 0x9814 reg.h 　
1385
 AR5K_PHY_TIMING_3_DSC_MANAR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 reg.h 　
1386
 AR5K_PHY_TIMING_3_DSC_MAN_SAR5K_PHY_TIMING_3_DSC_MAN_S 17 reg.h 　
1387
 AR5K_PHY_TIMING_3_DSC_EXPAR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 reg.h 　
1388
 AR5K_PHY_TIMING_3_DSC_EXP_SAR5K_PHY_TIMING_3_DSC_EXP_S 13 reg.h 　
1389
 AR5K_PHY_CHIP_IDAR5K_PHY_CHIP_ID 0x9818 reg.h 　
1390
 AR5K_PHY_ACTAR5K_PHY_ACT 0x981c reg.h Register Address
1391
 AR5K_PHY_ACT_ENABLEAR5K_PHY_ACT_ENABLE 0x00000001 reg.h Activate PHY
1392
 AR5K_PHY_ACT_DISABLEAR5K_PHY_ACT_DISABLE 0x00000002 reg.h Deactivate PHY
1393
 AR5K_PHY_RF_CTL2AR5K_PHY_RF_CTL2 0x9824 reg.h Register Address
1394
 AR5K_PHY_RF_CTL2_TXF2TXD_STARTAR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f reg.h TX frame to TX data start
1395
 AR5K_PHY_RF_CTL2_TXF2TXD_START_AR5K_PHY_RF_CTL2_TXF2TXD_START_ 0 reg.h 　
1396
 AR5K_PHY_RF_CTL3AR5K_PHY_RF_CTL3 0x9828 reg.h Register Address
1397
 AR5K_PHY_RF_CTL3_TXE2XLNA_ONAR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 reg.h TX end to XLNA on
1398
 AR5K_PHY_RF_CTL3_TXE2XLNA_ON_SAR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8 reg.h 　
1399
 AR5K_PHY_ADC_CTLAR5K_PHY_ADC_CTL 0x982c reg.h 　
1400
 AR5K_PHY_ADC_CTL_INBUFGAIN_OFFAR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003 reg.h 　
1401
 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_ 0 reg.h 　
1402
 AR5K_PHY_ADC_CTL_PWD_DAC_OFFAR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000 reg.h 　
1403
 AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OAR5K_PHY_ADC_CTL_PWD_BAND_GAP_O 0x00004000 reg.h 　
1404
 AR5K_PHY_ADC_CTL_PWD_ADC_OFFAR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000 reg.h 　
1405
 AR5K_PHY_ADC_CTL_INBUFGAIN_ONAR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000 reg.h 　
1406
 AR5K_PHY_ADC_CTL_INBUFGAIN_ON_SAR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16 reg.h 　
1407
 AR5K_PHY_RF_CTL4AR5K_PHY_RF_CTL4 0x9834 reg.h Register Address
1408
 AR5K_PHY_RF_CTL4_TXF2XPA_A_ONAR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 reg.h TX frame to XPA A on (field)
1409
 AR5K_PHY_RF_CTL4_TXF2XPA_B_ONAR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 reg.h TX frame to XPA B on (field)
1410
 AR5K_PHY_RF_CTL4_TXE2XPA_A_OFFAR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 reg.h TX end to XPA A off (field)
1411
 AR5K_PHY_RF_CTL4_TXE2XPA_B_OFFAR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 reg.h TX end to XPA B off (field)
1412
 AR5K_PHY_PA_CTLAR5K_PHY_PA_CTL 0x9838 reg.h Register Address
1413
 AR5K_PHY_PA_CTL_XPA_A_HIAR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 reg.h XPA A high (?)
1414
 AR5K_PHY_PA_CTL_XPA_B_HIAR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 reg.h XPA B high (?)
1415
 AR5K_PHY_PA_CTL_XPA_A_ENAR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 reg.h Enable XPA A
1416
 AR5K_PHY_PA_CTL_XPA_B_ENAR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 reg.h Enable XPA B
1417
 AR5K_PHY_SETTLINGAR5K_PHY_SETTLING 0x9844 reg.h Register Address
1418
 AR5K_PHY_SETTLING_AGCAR5K_PHY_SETTLING_AGC 0x0000007f reg.h AGC settling time
1419
 AR5K_PHY_SETTLING_AGC_SAR5K_PHY_SETTLING_AGC_S 0 reg.h 　
1420
 AR5K_PHY_SETTLING_SWITCHAR5K_PHY_SETTLING_SWITCH 0x00003f80 reg.h Switch settlig time
1421
 AR5K_PHY_SETTLING_SWITCH_SAR5K_PHY_SETTLING_SWITCH_S 7 reg.h 　
1422
 AR5K_PHY_GAINAR5K_PHY_GAIN 0x9848 reg.h Register Address
1423
 AR5K_PHY_GAIN_TXRX_ATTENAR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 reg.h TX-RX Attenuation
1424
 AR5K_PHY_GAIN_TXRX_ATTEN_SAR5K_PHY_GAIN_TXRX_ATTEN_S 12 reg.h 　
1425
 AR5K_PHY_GAIN_TXRX_RF_MAXAR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000 reg.h 　
1426
 AR5K_PHY_GAIN_TXRX_RF_MAX_SAR5K_PHY_GAIN_TXRX_RF_MAX_S 18 reg.h 　
1427
 AR5K_PHY_GAIN_OFFSETAR5K_PHY_GAIN_OFFSET 0x984c reg.h Register Address
1428
 AR5K_PHY_GAIN_OFFSET_RXTX_FLAGAR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 reg.h RX-TX flag (?)
1429
 AR5K_PHY_DESIRED_SIZEAR5K_PHY_DESIRED_SIZE 0x9850 reg.h Register Address
1430
 AR5K_PHY_DESIRED_SIZE_ADCAR5K_PHY_DESIRED_SIZE_ADC 0x000000ff reg.h ADC desired size
1431
 AR5K_PHY_DESIRED_SIZE_ADC_SAR5K_PHY_DESIRED_SIZE_ADC_S 0 reg.h 　
1432
 AR5K_PHY_DESIRED_SIZE_PGAAR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 reg.h PGA desired size
1433
 AR5K_PHY_DESIRED_SIZE_PGA_SAR5K_PHY_DESIRED_SIZE_PGA_S 8 reg.h 　
1434
 AR5K_PHY_DESIRED_SIZE_TOTAR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 reg.h Total desired size
1435
 AR5K_PHY_DESIRED_SIZE_TOT_SAR5K_PHY_DESIRED_SIZE_TOT_S 20 reg.h 　
1436
 AR5K_PHY_SIGAR5K_PHY_SIG 0x9858 reg.h Register Address
1437
 AR5K_PHY_SIG_FIRSTEPAR5K_PHY_SIG_FIRSTEP 0x0003f000 reg.h FIRSTEP
1438
 AR5K_PHY_SIG_FIRSTEP_SAR5K_PHY_SIG_FIRSTEP_S 12 reg.h 　
1439
 AR5K_PHY_SIG_FIRPWRAR5K_PHY_SIG_FIRPWR 0x03fc0000 reg.h FIPWR
1440
 AR5K_PHY_SIG_FIRPWR_SAR5K_PHY_SIG_FIRPWR_S 18 reg.h 　
1441
 AR5K_PHY_AGCCOARSEAR5K_PHY_AGCCOARSE 0x985c reg.h Register Address
1442
 AR5K_PHY_AGCCOARSE_LOAR5K_PHY_AGCCOARSE_LO 0x00007f80 reg.h AGC Coarse low
1443
 AR5K_PHY_AGCCOARSE_LO_SAR5K_PHY_AGCCOARSE_LO_S 7 reg.h 　
1444
 AR5K_PHY_AGCCOARSE_HIAR5K_PHY_AGCCOARSE_HI 0x003f8000 reg.h AGC Coarse high
1445
 AR5K_PHY_AGCCOARSE_HI_SAR5K_PHY_AGCCOARSE_HI_S 15 reg.h 　
1446
 AR5K_PHY_AGCCTLAR5K_PHY_AGCCTL 0x9860 reg.h Register address
1447
 AR5K_PHY_AGCCTL_CALAR5K_PHY_AGCCTL_CAL 0x00000001 reg.h Enable PHY calibration
1448
 AR5K_PHY_AGCCTL_NFAR5K_PHY_AGCCTL_NF 0x00000002 reg.h Enable Noise Floor calibration
1449
 AR5K_PHY_AGCCTL_NF_ENAR5K_PHY_AGCCTL_NF_EN 0x00008000 reg.h Enable nf calibration to happen (?)
1450
 AR5K_PHY_AGCCTL_NF_NOUPDATEAR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 reg.h Don't update nf automaticaly
1451
 AR5K_PHY_NFAR5K_PHY_NF 0x9864 reg.h Register address
1452
 AR5K_PHY_NF_MAR5K_PHY_NF_M 0x000001ff reg.h Noise floor mask
1453
 AR5K_PHY_NF_ACTIVEAR5K_PHY_NF_ACTIVE 0x00000100 reg.h Noise floor calibration still active
1454
 AR5K_PHY_NF_THRESH62AR5K_PHY_NF_THRESH62 0x0007f000 reg.h Thresh62 -check ANI patent- (field)
1455
 AR5K_PHY_NF_THRESH62_SAR5K_PHY_NF_THRESH62_S 12 reg.h 　
1456
 AR5K_PHY_NF_MINCCA_PWRAR5K_PHY_NF_MINCCA_PWR 0x0ff80000 reg.h ???
1457
 AR5K_PHY_NF_MINCCA_PWR_SAR5K_PHY_NF_MINCCA_PWR_S 19 reg.h 　
1458
 AR5K_PHY_ADCSATAR5K_PHY_ADCSAT 0x9868 reg.h 　
1459
 AR5K_PHY_ADCSAT_ICNTAR5K_PHY_ADCSAT_ICNT 0x0001f800 reg.h 　
1460
 AR5K_PHY_ADCSAT_ICNT_SAR5K_PHY_ADCSAT_ICNT_S 11 reg.h 　
1461
 AR5K_PHY_ADCSAT_THRAR5K_PHY_ADCSAT_THR 0x000007e0 reg.h 　
1462
 AR5K_PHY_ADCSAT_THR_SAR5K_PHY_ADCSAT_THR_S 5 reg.h 　
1463
 AR5K_PHY_WEAK_OFDM_HIGH_THRAR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868 reg.h 　
1464
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 0x0000001f reg.h 　
1465
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 0 reg.h 　
1466
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M1AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000 reg.h 　
1467
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_ 17 reg.h 　
1468
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000 reg.h 　
1469
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 24 reg.h 　
1470
 AR5K_PHY_WEAK_OFDM_LOW_THRAR5K_PHY_WEAK_OFDM_LOW_THR 0x986c reg.h 　
1471
 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFAR5K_PHY_WEAK_OFDM_LOW_THR_SELF 0x00000001 reg.h 　
1472
 AR5K_PHY_WEAK_OFDM_LOW_THR_M2_CAR5K_PHY_WEAK_OFDM_LOW_THR_M2_C 0x00003f00 reg.h 　
1473
 AR5K_PHY_WEAK_OFDM_LOW_THR_M2_CAR5K_PHY_WEAK_OFDM_LOW_THR_M2_C 8 reg.h 　
1474
 AR5K_PHY_WEAK_OFDM_LOW_THR_M1AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000 reg.h 　
1475
 AR5K_PHY_WEAK_OFDM_LOW_THR_M1_SAR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14 reg.h 　
1476
 AR5K_PHY_WEAK_OFDM_LOW_THR_M2AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000 reg.h 　
1477
 AR5K_PHY_WEAK_OFDM_LOW_THR_M2_SAR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21 reg.h 　
1478
 AR5K_PHY_SCRAR5K_PHY_SCR 0x9870 reg.h 　
1479
 AR5K_PHY_SLMTAR5K_PHY_SLMT 0x9874 reg.h 　
1480
 AR5K_PHY_SLMT_32MHZAR5K_PHY_SLMT_32MHZ 0x0000007f reg.h 　
1481
 AR5K_PHY_SCALAR5K_PHY_SCAL 0x9878 reg.h 　
1482
 AR5K_PHY_SCAL_32MHZAR5K_PHY_SCAL_32MHZ 0x0000000e reg.h 　
1483
 AR5K_PHY_SCAL_32MHZ_2417AR5K_PHY_SCAL_32MHZ_2417 0x0000000a reg.h 　
1484
 AR5K_PHY_SCAL_32MHZ_HB63AR5K_PHY_SCAL_32MHZ_HB63 0x00000032 reg.h 　
1485
 AR5K_PHY_PLLAR5K_PHY_PLL 0x987c reg.h 　
1486
 AR5K_PHY_PLL_20MHZAR5K_PHY_PLL_20MHZ 0x00000013 reg.h For half rate (?)
1487
 AR5K_PHY_PLL_40MHZ_5211AR5K_PHY_PLL_40MHZ_5211 0x00000018 reg.h 　
1488
 AR5K_PHY_PLL_40MHZ_5212AR5K_PHY_PLL_40MHZ_5212 0x000000aa reg.h 　
1489
 AR5K_PHY_PLL_40MHZ_5413AR5K_PHY_PLL_40MHZ_5413 0x00000004 reg.h 　
1490
 AR5K_PHY_PLL_40MHZAR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) reg.h 　
1491
 AR5K_PHY_PLL_44MHZ_5211AR5K_PHY_PLL_44MHZ_5211 0x00000019 reg.h 　
1492
 AR5K_PHY_PLL_44MHZ_5212AR5K_PHY_PLL_44MHZ_5212 0x000000ab reg.h 　
1493
 AR5K_PHY_PLL_44MHZAR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) reg.h 　
1494
 AR5K_PHY_PLL_RF5111AR5K_PHY_PLL_RF5111 0x00000000 reg.h 　
1495
 AR5K_PHY_PLL_RF5112AR5K_PHY_PLL_RF5112 0x00000040 reg.h 　
1496
 AR5K_PHY_PLL_HALF_RATEAR5K_PHY_PLL_HALF_RATE 0x00000100 reg.h 　
1497
 AR5K_PHY_PLL_QUARTER_RATEAR5K_PHY_PLL_QUARTER_RATE 0x00000200 reg.h 　
1498
 AR5K_RF_BUFFERAR5K_RF_BUFFER 0x989c reg.h 　
1499
 AR5K_RF_BUFFER_CONTROL_0AR5K_RF_BUFFER_CONTROL_0 0x98c0 reg.h Channel on 5110
1500
 AR5K_RF_BUFFER_CONTROL_1AR5K_RF_BUFFER_CONTROL_1 0x98c4 reg.h Bank 7 on 5112
1501
 AR5K_RF_BUFFER_CONTROL_2AR5K_RF_BUFFER_CONTROL_2 0x98cc reg.h Bank 7 on 5111
1502
 AR5K_RF_BUFFER_CONTROL_3AR5K_RF_BUFFER_CONTROL_3 0x98d0 reg.h Bank 2 on 5112
1503
 AR5K_RF_BUFFER_CONTROL_4AR5K_RF_BUFFER_CONTROL_4 0x98d4 reg.h RF Stage register on 5110
1504
 AR5K_RF_BUFFER_CONTROL_5AR5K_RF_BUFFER_CONTROL_5 0x98d8 reg.h Bank 3 on 5111
1505
 AR5K_RF_BUFFER_CONTROL_6AR5K_RF_BUFFER_CONTROL_6 0x98dc reg.h Bank 3 on 5112
1506
 AR5K_PHY_RFSTGAR5K_PHY_RFSTG 0x98d4 reg.h 　
1507
 AR5K_PHY_RFSTG_DISABLEAR5K_PHY_RFSTG_DISABLE 0x00000021 reg.h 　
1508
 AR5K_PHY_BIN_MASK_1AR5K_PHY_BIN_MASK_1 0x9900 reg.h 　
1509
 AR5K_PHY_BIN_MASK_2AR5K_PHY_BIN_MASK_2 0x9904 reg.h 　
1510
 AR5K_PHY_BIN_MASK_3AR5K_PHY_BIN_MASK_3 0x9908 reg.h 　
1511
 AR5K_PHY_BIN_MASK_CTLAR5K_PHY_BIN_MASK_CTL 0x990c reg.h 　
1512
 AR5K_PHY_BIN_MASK_CTL_MASK_4AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff reg.h 　
1513
 AR5K_PHY_BIN_MASK_CTL_MASK_4_SAR5K_PHY_BIN_MASK_CTL_MASK_4_S 0 reg.h 　
1514
 AR5K_PHY_BIN_MASK_CTL_RATEAR5K_PHY_BIN_MASK_CTL_RATE 0xff000000 reg.h 　
1515
 AR5K_PHY_BIN_MASK_CTL_RATE_SAR5K_PHY_BIN_MASK_CTL_RATE_S 24 reg.h 　
1516
 AR5K_PHY_ANT_CTLAR5K_PHY_ANT_CTL 0x9910 reg.h Register Address
1517
 AR5K_PHY_ANT_CTL_TXRX_ENAR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 reg.h Enable TX/RX (?)
1518
 AR5K_PHY_ANT_CTL_SECTORED_ANTAR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 reg.h Sectored Antenna
1519
 AR5K_PHY_ANT_CTL_HITUNE5AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 reg.h Hitune5 (?)
1520
 AR5K_PHY_ANT_CTL_SWTABLE_IDLEAR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 reg.h Switch table idle (?)
1521
 AR5K_PHY_ANT_CTL_SWTABLE_IDLE_SAR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4 reg.h 　
1522
 AR5K_PHY_RX_DELAYAR5K_PHY_RX_DELAY 0x9914 reg.h Register Address
1523
 AR5K_PHY_RX_DELAY_MAR5K_PHY_RX_DELAY_M 0x00003fff reg.h Mask for RX activate to receive delay (/100ns)
1524
 AR5K_PHY_MAX_RX_LENAR5K_PHY_MAX_RX_LEN 0x991c reg.h 　
1525
 AR5K_PHY_IQAR5K_PHY_IQ 0x9920 reg.h Register Address
1526
 AR5K_PHY_IQ_CORR_Q_Q_COFFAR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f reg.h Mask for q correction info
1527
 AR5K_PHY_IQ_CORR_Q_I_COFFAR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 reg.h Mask for i correction info
1528
 AR5K_PHY_IQ_CORR_Q_I_COFF_SAR5K_PHY_IQ_CORR_Q_I_COFF_S 5 reg.h 　
1529
 AR5K_PHY_IQ_CORR_ENABLEAR5K_PHY_IQ_CORR_ENABLE 0x00000800 reg.h Enable i/q correction
1530
 AR5K_PHY_IQ_CAL_NUM_LOG_MAXAR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 reg.h Mask for max number of samples in log scale
1531
 AR5K_PHY_IQ_CAL_NUM_LOG_MAX_SAR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 reg.h 　
1532
 AR5K_PHY_IQ_RUNAR5K_PHY_IQ_RUN 0x00010000 reg.h Run i/q calibration
1533
 AR5K_PHY_IQ_USE_PT_DFAR5K_PHY_IQ_USE_PT_DF 0x00020000 reg.h Use pilot track df (?)
1534
 AR5K_PHY_IQ_EARLY_TRIG_THRAR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 reg.h Early trigger threshold (?) (field)
1535
 AR5K_PHY_IQ_PILOT_MASK_ENAR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 reg.h Enable pilot mask (?)
1536
 AR5K_PHY_IQ_CHAN_MASK_ENAR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 reg.h Enable channel mask (?)
1537
 AR5K_PHY_IQ_SPUR_FILT_ENAR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 reg.h Enable spur filter
1538
 AR5K_PHY_IQ_SPUR_RSSI_ENAR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 reg.h Enable spur rssi
1539
 AR5K_PHY_OFDM_SELFCORRAR5K_PHY_OFDM_SELFCORR 0x9924 reg.h Register Address
1540
 AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x00000001 reg.h Enable cyclic RSSI thr 1
1541
 AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x000000fe reg.h Mask for Cyclic RSSI threshold 1
1542
 AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 1 reg.h 　
1543
 AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x00000100 reg.h Cyclic RSSI threshold 3 (field) (?)
1544
 AR5K_PHY_OFDM_SELFCORR_RSSI_1ATAR5K_PHY_OFDM_SELFCORR_RSSI_1AT 0x00008000 reg.h Enable 1A RSSI threshold (?)
1545
 AR5K_PHY_OFDM_SELFCORR_RSSI_1ATAR5K_PHY_OFDM_SELFCORR_RSSI_1AT 0x00010000 reg.h 1A RSSI threshold (field) (?)
1546
 AR5K_PHY_OFDM_SELFCORR_LSCTHR_HAR5K_PHY_OFDM_SELFCORR_LSCTHR_H 0x00800000 reg.h Long sc threshold hi rssi (?)
1547
 AR5K_PHY_WARM_RESETAR5K_PHY_WARM_RESET 0x9928 reg.h 　
1548
 AR5K_PHY_CTLAR5K_PHY_CTL 0x992c reg.h Register Address
1549
 AR5K_PHY_CTL_RX_DRAIN_RATEAR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 reg.h RX drain rate (?)
1550
 AR5K_PHY_CTL_LATE_TX_SIG_SYMAR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 reg.h Late tx signal symbol (?)
1551
 AR5K_PHY_CTL_GEN_SCRAMBLERAR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 reg.h Generate scrambler
1552
 AR5K_PHY_CTL_TX_ANT_SELAR5K_PHY_CTL_TX_ANT_SEL 0x00000008 reg.h TX antenna select
1553
 AR5K_PHY_CTL_TX_ANT_STATICAR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 reg.h Static TX antenna
1554
 AR5K_PHY_CTL_RX_ANT_SELAR5K_PHY_CTL_RX_ANT_SEL 0x00000020 reg.h RX antenna select
1555
 AR5K_PHY_CTL_RX_ANT_STATICAR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 reg.h Static RX antenna
1556
 AR5K_PHY_CTL_LOW_FREQ_SLE_ENAR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 reg.h Enable low freq sleep
1557
 AR5K_PHY_PAPD_PROBEAR5K_PHY_PAPD_PROBE 0x9930 reg.h 　
1558
 AR5K_PHY_PAPD_PROBE_SH_HI_PARAR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 reg.h 　
1559
 AR5K_PHY_PAPD_PROBE_PCDAC_BIASAR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002 reg.h 　
1560
 AR5K_PHY_PAPD_PROBE_COMP_GAINAR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040 reg.h 　
1561
 AR5K_PHY_PAPD_PROBE_TXPOWERAR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 reg.h 　
1562
 AR5K_PHY_PAPD_PROBE_TXPOWER_SAR5K_PHY_PAPD_PROBE_TXPOWER_S 9 reg.h 　
1563
 AR5K_PHY_PAPD_PROBE_TX_NEXTAR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 reg.h 　
1564
 AR5K_PHY_PAPD_PROBE_PREDIST_ENAR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000 reg.h 　
1565
 AR5K_PHY_PAPD_PROBE_TYPEAR5K_PHY_PAPD_PROBE_TYPE 0x01800000 reg.h [5112+]
1566
 AR5K_PHY_PAPD_PROBE_TYPE_SAR5K_PHY_PAPD_PROBE_TYPE_S 23 reg.h 　
1567
 AR5K_PHY_PAPD_PROBE_TYPE_OFDMAR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 reg.h 　
1568
 AR5K_PHY_PAPD_PROBE_TYPE_XRAR5K_PHY_PAPD_PROBE_TYPE_XR 1 reg.h 　
1569
 AR5K_PHY_PAPD_PROBE_TYPE_CCKAR5K_PHY_PAPD_PROBE_TYPE_CCK 2 reg.h 　
1570
 AR5K_PHY_PAPD_PROBE_GAINFAR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 reg.h 　
1571
 AR5K_PHY_PAPD_PROBE_GAINF_SAR5K_PHY_PAPD_PROBE_GAINF_S 25 reg.h 　
1572
 AR5K_PHY_PAPD_PROBE_INI_5111AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 reg.h [5212+]
1573
 AR5K_PHY_PAPD_PROBE_INI_5112AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 reg.h [5212+]
1574
 AR5K_PHY_TXPOWER_RATE1AR5K_PHY_TXPOWER_RATE1 0x9934 reg.h 　
1575
 AR5K_PHY_TXPOWER_RATE2AR5K_PHY_TXPOWER_RATE2 0x9938 reg.h 　
1576
 AR5K_PHY_TXPOWER_RATE_MAXAR5K_PHY_TXPOWER_RATE_MAX 0x993c reg.h 　
1577
 AR5K_PHY_TXPOWER_RATE_MAX_TPC_EAR5K_PHY_TXPOWER_RATE_MAX_TPC_E 0x00000040 reg.h 　
1578
 AR5K_PHY_TXPOWER_RATE3AR5K_PHY_TXPOWER_RATE3 0xa234 reg.h 　
1579
 AR5K_PHY_TXPOWER_RATE4AR5K_PHY_TXPOWER_RATE4 0xa238 reg.h 　
1580
 AR5K_PHY_FRAME_CTL_5210AR5K_PHY_FRAME_CTL_5210 0x9804 reg.h 　
1581
 AR5K_PHY_FRAME_CTL_5211AR5K_PHY_FRAME_CTL_5211 0x9944 reg.h 　
1582
 AR5K_PHY_FRAME_CTLAR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) reg.h 　
1583
 AR5K_PHY_FRAME_CTL_TX_CLIPAR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 reg.h Mask for tx clip (?)
1584
 AR5K_PHY_FRAME_CTL_TX_CLIP_SAR5K_PHY_FRAME_CTL_TX_CLIP_S 3 reg.h 　
1585
 AR5K_PHY_FRAME_CTL_PREP_CHINFOAR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 reg.h Prepend chan info
1586
 AR5K_PHY_FRAME_CTL_EMUAR5K_PHY_FRAME_CTL_EMU 0x80000000 reg.h 　
1587
 AR5K_PHY_FRAME_CTL_EMU_SAR5K_PHY_FRAME_CTL_EMU_S 31 reg.h 　
1588
 AR5K_PHY_FRAME_CTL_TIMING_ERRAR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 reg.h PHY timing error
1589
 AR5K_PHY_FRAME_CTL_PARITY_ERRAR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 reg.h Parity error
1590
 AR5K_PHY_FRAME_CTL_ILLRATE_ERRAR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 reg.h Illegal rate
1591
 AR5K_PHY_FRAME_CTL_ILLLEN_ERRAR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 reg.h Illegal length
1592
 AR5K_PHY_FRAME_CTL_SERVICE_ERRAR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 reg.h 　
1593
 AR5K_PHY_FRAME_CTL_TXURN_ERRAR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 reg.h TX underrun
1594
 AR5K_PHY_FRAME_CTL_INIAR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ AR5K_PHY_FRAME_CTL_TXURN_ERR | \ AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ AR5K_PHY_FRAME_CTL_ILLRAT reg.h 　
1595
 AR5K_PHY_TX_PWR_ADJAR5K_PHY_TX_PWR_ADJ 0x994c reg.h 　
1596
 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DEAR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE 0x00000fc0 reg.h 　
1597
 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DEAR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE 6 reg.h 　
1598
 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_IAR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I 0x00fc0000 reg.h 　
1599
 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_IAR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I 18 reg.h 　
1600
 AR5K_PHY_RADARAR5K_PHY_RADAR 0x9954 reg.h 　
1601
 AR5K_PHY_RADAR_ENABLEAR5K_PHY_RADAR_ENABLE 0x00000001 reg.h 　
1602
 AR5K_PHY_RADAR_DISABLEAR5K_PHY_RADAR_DISABLE 0x00000000 reg.h 　
1603
 AR5K_PHY_RADAR_INBANDTHRAR5K_PHY_RADAR_INBANDTHR 0x0000003e reg.h Inband threshold
1604
 AR5K_PHY_RADAR_INBANDTHR_SAR5K_PHY_RADAR_INBANDTHR_S 1 reg.h 　
1605
 AR5K_PHY_RADAR_PRSSI_THRAR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 reg.h Pulse RSSI/SNR threshold
1606
 AR5K_PHY_RADAR_PRSSI_THR_SAR5K_PHY_RADAR_PRSSI_THR_S 6 reg.h 　
1607
 AR5K_PHY_RADAR_PHEIGHT_THRAR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 reg.h Pulse height threshold
1608
 AR5K_PHY_RADAR_PHEIGHT_THR_SAR5K_PHY_RADAR_PHEIGHT_THR_S 12 reg.h 　
1609
 AR5K_PHY_RADAR_RSSI_THRAR5K_PHY_RADAR_RSSI_THR 0x00fc0000 reg.h Radar RSSI/SNR threshold.
1610
 AR5K_PHY_RADAR_RSSI_THR_SAR5K_PHY_RADAR_RSSI_THR_S 18 reg.h 　
1611
 AR5K_PHY_RADAR_FIRPWR_THRAR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 reg.h Finite Impulse Response
1612
 AR5K_PHY_RADAR_FIRPWR_THRSAR5K_PHY_RADAR_FIRPWR_THRS 24 reg.h 　
1613
 AR5K_PHY_ANT_SWITCH_TABLE_0AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 reg.h 　
1614
 AR5K_PHY_ANT_SWITCH_TABLE_1AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 reg.h 　
1615
 AR5K_PHY_NFTHRESAR5K_PHY_NFTHRES 0x9968 reg.h 　
1616
 AR5K_PHY_SIGMA_DELTAAR5K_PHY_SIGMA_DELTA 0x996C reg.h 　
1617
 AR5K_PHY_SIGMA_DELTA_ADC_SELAR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 reg.h 　
1618
 AR5K_PHY_SIGMA_DELTA_ADC_SEL_SAR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0 reg.h 　
1619
 AR5K_PHY_SIGMA_DELTA_FILT2AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8 reg.h 　
1620
 AR5K_PHY_SIGMA_DELTA_FILT2_SAR5K_PHY_SIGMA_DELTA_FILT2_S 3 reg.h 　
1621
 AR5K_PHY_SIGMA_DELTA_FILT1AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00 reg.h 　
1622
 AR5K_PHY_SIGMA_DELTA_FILT1_SAR5K_PHY_SIGMA_DELTA_FILT1_S 8 reg.h 　
1623
 AR5K_PHY_SIGMA_DELTA_ADC_CLIPAR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 reg.h 　
1624
 AR5K_PHY_SIGMA_DELTA_ADC_CLIP_SAR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13 reg.h 　
1625
 AR5K_PHY_RESTARTAR5K_PHY_RESTART 0x9970 reg.h restart
1626
 AR5K_PHY_RESTART_DIV_GCAR5K_PHY_RESTART_DIV_GC 0x001c0000 reg.h Fast diversity gc_limit (?)
1627
 AR5K_PHY_RESTART_DIV_GC_SAR5K_PHY_RESTART_DIV_GC_S 18 reg.h 　
1628
 AR5K_PHY_RFBUS_REQAR5K_PHY_RFBUS_REQ 0x997C reg.h 　
1629
 AR5K_PHY_RFBUS_REQ_REQUESTAR5K_PHY_RFBUS_REQ_REQUEST 0x00000001 reg.h 　
1630
 AR5K_PHY_TIMING_7AR5K_PHY_TIMING_7 0x9980 reg.h 　
1631
 AR5K_PHY_TIMING_8AR5K_PHY_TIMING_8 0x9984 reg.h 　
1632
 AR5K_PHY_TIMING_8_PILOT_MASK_2AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff reg.h 　
1633
 AR5K_PHY_TIMING_8_PILOT_MASK_2_AR5K_PHY_TIMING_8_PILOT_MASK_2_ 0 reg.h 　
1634
 AR5K_PHY_BIN_MASK2_1AR5K_PHY_BIN_MASK2_1 0x9988 reg.h 　
1635
 AR5K_PHY_BIN_MASK2_2AR5K_PHY_BIN_MASK2_2 0x998c reg.h 　
1636
 AR5K_PHY_BIN_MASK2_3AR5K_PHY_BIN_MASK2_3 0x9990 reg.h 　
1637
 AR5K_PHY_BIN_MASK2_4AR5K_PHY_BIN_MASK2_4 0x9994 reg.h 　
1638
 AR5K_PHY_BIN_MASK2_4_MASK_4AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff reg.h 　
1639
 AR5K_PHY_BIN_MASK2_4_MASK_4_SAR5K_PHY_BIN_MASK2_4_MASK_4_S 0 reg.h 　
1640
 AR5K_PHY_TIMING_9AR5K_PHY_TIMING_9 0x9998 reg.h 　
1641
 AR5K_PHY_TIMING_10AR5K_PHY_TIMING_10 0x999c reg.h 　
1642
 AR5K_PHY_TIMING_10_PILOT_MASK_2AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff reg.h 　
1643
 AR5K_PHY_TIMING_10_PILOT_MASK_2AR5K_PHY_TIMING_10_PILOT_MASK_2 0 reg.h 　
1644
 AR5K_PHY_TIMING_11AR5K_PHY_TIMING_11 0x99a0 reg.h Register address
1645
 AR5K_PHY_TIMING_11_SPUR_DELTA_PAR5K_PHY_TIMING_11_SPUR_DELTA_P 0x000fffff reg.h Spur delta phase
1646
 AR5K_PHY_TIMING_11_SPUR_DELTA_PAR5K_PHY_TIMING_11_SPUR_DELTA_P 0 reg.h 　
1647
 AR5K_PHY_TIMING_11_SPUR_FREQ_SDAR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 reg.h Freq sigma delta
1648
 AR5K_PHY_TIMING_11_SPUR_FREQ_SDAR5K_PHY_TIMING_11_SPUR_FREQ_SD 20 reg.h 　
1649
 AR5K_PHY_TIMING_11_USE_SPUR_IN_AR5K_PHY_TIMING_11_USE_SPUR_IN_ 0x40000000 reg.h Spur filter in AGC detector
1650
 AR5K_PHY_TIMING_11_USE_SPUR_IN_AR5K_PHY_TIMING_11_USE_SPUR_IN_ 0x80000000 reg.h Spur filter in OFDM self correlator
1651
 AR5K_BB_GAIN_BASEAR5K_BB_GAIN_BASE 0x9b00 reg.h BaseBand Amplifier Gain table base address
1652
 AR5K_RF_GAIN_BASEAR5K_RF_GAIN_BASE 0x9a00 reg.h RF Amplrifier Gain table base address
1653
 AR5K_PHY_IQRES_CAL_PWR_IAR5K_PHY_IQRES_CAL_PWR_I 0x9c10 reg.h I (Inphase) power value
1654
 AR5K_PHY_IQRES_CAL_PWR_QAR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 reg.h Q (Quadrature) power value
1655
 AR5K_PHY_IQRES_CAL_CORRAR5K_PHY_IQRES_CAL_CORR 0x9c18 reg.h I/Q Correlation
1656
 AR5K_PHY_CURRENT_RSSIAR5K_PHY_CURRENT_RSSI 0x9c1c reg.h 　
1657
 AR5K_PHY_RFBUS_GRANTAR5K_PHY_RFBUS_GRANT 0x9c20 reg.h 　
1658
 AR5K_PHY_RFBUS_GRANT_OKAR5K_PHY_RFBUS_GRANT_OK 0x00000001 reg.h 　
1659
 AR5K_PHY_ADC_TESTAR5K_PHY_ADC_TEST 0x9c24 reg.h 　
1660
 AR5K_PHY_ADC_TEST_IAR5K_PHY_ADC_TEST_I 0x00000001 reg.h 　
1661
 AR5K_PHY_ADC_TEST_QAR5K_PHY_ADC_TEST_Q 0x00000200 reg.h 　
1662
 AR5K_PHY_DAC_TESTAR5K_PHY_DAC_TEST 0x9c28 reg.h 　
1663
 AR5K_PHY_DAC_TEST_IAR5K_PHY_DAC_TEST_I 0x00000001 reg.h 　
1664
 AR5K_PHY_DAC_TEST_QAR5K_PHY_DAC_TEST_Q 0x00000200 reg.h 　
1665
 AR5K_PHY_PTATAR5K_PHY_PTAT 0x9c2c reg.h 　
1666
 AR5K_PHY_BAD_TX_RATEAR5K_PHY_BAD_TX_RATE 0x9c30 reg.h 　
1667
 AR5K_PHY_SPUR_PWRAR5K_PHY_SPUR_PWR 0x9c34 reg.h Register Address
1668
 AR5K_PHY_SPUR_PWR_IAR5K_PHY_SPUR_PWR_I 0x00000001 reg.h SPUR Power estimate for I (field)
1669
 AR5K_PHY_SPUR_PWR_QAR5K_PHY_SPUR_PWR_Q 0x00000100 reg.h SPUR Power estimate for Q (field)
1670
 AR5K_PHY_SPUR_PWR_FILTAR5K_PHY_SPUR_PWR_FILT 0x00010000 reg.h Power with SPUR removed (field)
1671
 AR5K_PHY_CHAN_STATUSAR5K_PHY_CHAN_STATUS 0x9c38 reg.h 　
1672
 AR5K_PHY_CHAN_STATUS_BT_ACTAR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001 reg.h 　
1673
 AR5K_PHY_CHAN_STATUS_RX_CLR_RAWAR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002 reg.h 　
1674
 AR5K_PHY_CHAN_STATUS_RX_CLR_MACAR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004 reg.h 　
1675
 AR5K_PHY_CHAN_STATUS_RX_CLR_PAPAR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 reg.h 　
1676
 AR5K_PHY_HEAVY_CLIP_ENABLEAR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0 reg.h 　
1677
 AR5K_PHY_SCLOCKAR5K_PHY_SCLOCK 0x99f0 reg.h 　
1678
 AR5K_PHY_SCLOCK_32MHZAR5K_PHY_SCLOCK_32MHZ 0x0000000c reg.h 　
1679
 AR5K_PHY_SDELAYAR5K_PHY_SDELAY 0x99f4 reg.h 　
1680
 AR5K_PHY_SDELAY_32MHZAR5K_PHY_SDELAY_32MHZ 0x000000ff reg.h 　
1681
 AR5K_PHY_SPENDINGAR5K_PHY_SPENDING 0x99f8 reg.h 　
1682
 AR5K_PHY_PAPD_I_BASEAR5K_PHY_PAPD_I_BASE 0xa000 reg.h 　
1683
 AR5K_PHY_PCDAC_TXPOWER_BASEAR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 reg.h 　
1684
 AR5K_PHY_MODEAR5K_PHY_MODE 0x0a200 reg.h Register Address
1685
 AR5K_PHY_MODE_MODAR5K_PHY_MODE_MOD 0x00000001 reg.h PHY Modulation bit
1686
 AR5K_PHY_MODE_MOD_OFDMAR5K_PHY_MODE_MOD_OFDM 0 reg.h 　
1687
 AR5K_PHY_MODE_MOD_CCKAR5K_PHY_MODE_MOD_CCK 1 reg.h 　
1688
 AR5K_PHY_MODE_FREQAR5K_PHY_MODE_FREQ 0x00000002 reg.h Freq mode bit
1689
 AR5K_PHY_MODE_FREQ_5GHZAR5K_PHY_MODE_FREQ_5GHZ 0 reg.h 　
1690
 AR5K_PHY_MODE_FREQ_2GHZAR5K_PHY_MODE_FREQ_2GHZ 2 reg.h 　
1691
 AR5K_PHY_MODE_MOD_DYNAR5K_PHY_MODE_MOD_DYN 0x00000004 reg.h Enable Dynamic OFDM/CCK mode [5112+]
1692
 AR5K_PHY_MODE_RADAR5K_PHY_MODE_RAD 0x00000008 reg.h [5212+]
1693
 AR5K_PHY_MODE_RAD_RF5111AR5K_PHY_MODE_RAD_RF5111 0 reg.h 　
1694
 AR5K_PHY_MODE_RAD_RF5112AR5K_PHY_MODE_RAD_RF5112 8 reg.h 　
1695
 AR5K_PHY_MODE_XRAR5K_PHY_MODE_XR 0x00000010 reg.h Enable XR mode [5112+]
1696
 AR5K_PHY_MODE_HALF_RATEAR5K_PHY_MODE_HALF_RATE 0x00000020 reg.h Enable Half rate (test)
1697
 AR5K_PHY_MODE_QUARTER_RATEAR5K_PHY_MODE_QUARTER_RATE 0x00000040 reg.h Enable Quarter rat (test)
1698
 AR5K_PHY_CCKTXCTLAR5K_PHY_CCKTXCTL 0xa204 reg.h 　
1699
 AR5K_PHY_CCKTXCTL_WORLDAR5K_PHY_CCKTXCTL_WORLD 0x00000000 reg.h 　
1700
 AR5K_PHY_CCKTXCTL_JAPANAR5K_PHY_CCKTXCTL_JAPAN 0x00000010 reg.h 　
1701
 AR5K_PHY_CCKTXCTL_SCRAMBLER_DISAR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001 reg.h 　
1702
 AR5K_PHY_CCKTXCTK_DAC_SCALEAR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004 reg.h 　
1703
 AR5K_PHY_CCK_CROSSCORRAR5K_PHY_CCK_CROSSCORR 0xa208 reg.h 　
1704
 AR5K_PHY_CCK_CROSSCORR_WEAK_SIGAR5K_PHY_CCK_CROSSCORR_WEAK_SIG 0x0000000f reg.h 　
1705
 AR5K_PHY_CCK_CROSSCORR_WEAK_SIGAR5K_PHY_CCK_CROSSCORR_WEAK_SIG 0 reg.h 　
1706
 AR5K_PHY_FAST_ANT_DIVAR5K_PHY_FAST_ANT_DIV 0xa208 reg.h 　
1707
 AR5K_PHY_FAST_ANT_DIV_ENAR5K_PHY_FAST_ANT_DIV_EN 0x00002000 reg.h 　
1708
 AR5K_PHY_GAIN_2GHZAR5K_PHY_GAIN_2GHZ 0xa20c reg.h 　
1709
 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRXAR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 reg.h 　
1710
 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_ 18 reg.h 　
1711
 AR5K_PHY_GAIN_2GHZ_INI_5111AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c reg.h 　
1712
 AR5K_PHY_CCK_RX_CTL_4AR5K_PHY_CCK_RX_CTL_4 0xa21c reg.h 　
1713
 AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ 0x01f80000 reg.h 　
1714
 AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ 19 reg.h 　
1715
 AR5K_PHY_DAG_CCK_CTLAR5K_PHY_DAG_CCK_CTL 0xa228 reg.h 　
1716
 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THAR5K_PHY_DAG_CCK_CTL_EN_RSSI_TH 0x00000200 reg.h 　
1717
 AR5K_PHY_DAG_CCK_CTL_RSSI_THRAR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00 reg.h 　
1718
 AR5K_PHY_DAG_CCK_CTL_RSSI_THR_SAR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10 reg.h 　
1719
 AR5K_PHY_FAST_ADCAR5K_PHY_FAST_ADC 0xa24c reg.h 　
1720
 AR5K_PHY_BLUETOOTHAR5K_PHY_BLUETOOTH 0xa254 reg.h 　
1721
 AR5K_PHY_TPC_RG1AR5K_PHY_TPC_RG1 0xa258 reg.h 　
1722
 AR5K_PHY_TPC_RG1_NUM_PD_GAINAR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000 reg.h 　
1723
 AR5K_PHY_TPC_RG1_NUM_PD_GAIN_SAR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14 reg.h 　
1724
 AR5K_PHY_TPC_RG1_PDGAIN_1AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000 reg.h 　
1725
 AR5K_PHY_TPC_RG1_PDGAIN_1_SAR5K_PHY_TPC_RG1_PDGAIN_1_S 16 reg.h 　
1726
 AR5K_PHY_TPC_RG1_PDGAIN_2AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000 reg.h 　
1727
 AR5K_PHY_TPC_RG1_PDGAIN_2_SAR5K_PHY_TPC_RG1_PDGAIN_2_S 18 reg.h 　
1728
 AR5K_PHY_TPC_RG1_PDGAIN_3AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000 reg.h 　
1729
 AR5K_PHY_TPC_RG1_PDGAIN_3_SAR5K_PHY_TPC_RG1_PDGAIN_3_S 20 reg.h 　
1730
 AR5K_PHY_TPC_RG5AR5K_PHY_TPC_RG5 0xa26C reg.h 　
1731
 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAAR5K_PHY_TPC_RG5_PD_GAIN_OVERLA 0x0000000F reg.h 　
1732
 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAAR5K_PHY_TPC_RG5_PD_GAIN_OVERLA 0 reg.h 　
1733
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x000003F0 reg.h 　
1734
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 4 reg.h 　
1735
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x0000FC00 reg.h 　
1736
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 10 reg.h 　
1737
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x003F0000 reg.h 　
1738
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 16 reg.h 　
1739
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x0FC00000 reg.h 　
1740
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 22 reg.h 　
1741
 AR5K_PHY_PDADC_TXPOWER_BASEAR5K_PHY_PDADC_TXPOWER_BASE 0xa280 reg.h 　
1742
 AR5K_RF5111_OB_2GHZAR5K_RF5111_OB_2GHZ { 3, 119, 0 } rfbuffer.h 　
1743
 AR5K_RF5111_DB_2GHZAR5K_RF5111_DB_2GHZ { 3, 122, 0 } rfbuffer.h 　
1744
 AR5K_RF5111_OB_5GHZAR5K_RF5111_OB_5GHZ { 3, 104, 0 } rfbuffer.h 　
1745
 AR5K_RF5111_DB_5GHZAR5K_RF5111_DB_5GHZ { 3, 107, 0 } rfbuffer.h 　
1746
 AR5K_RF5111_PWD_XPDAR5K_RF5111_PWD_XPD { 1, 95, 0 } rfbuffer.h 　
1747
 AR5K_RF5111_XPD_GAINAR5K_RF5111_XPD_GAIN { 4, 96, 0 } rfbuffer.h 　
1748
 AR5K_RF5111_GAIN_IAR5K_RF5111_GAIN_I { 6, 29, 0 } rfbuffer.h 　
1749
 AR5K_RF5111_PLO_SELAR5K_RF5111_PLO_SEL { 1, 4, 0 } rfbuffer.h 　
1750
 AR5K_RF5111_RFGAIN_SELAR5K_RF5111_RFGAIN_SEL { 1, 36, 0 } rfbuffer.h 　
1751
 AR5K_RF5111_RFGAIN_STEPAR5K_RF5111_RFGAIN_STEP { 6, 37, 0 } rfbuffer.h 　
1752
 AR5K_RF5111_WAIT_SAR5K_RF5111_WAIT_S { 5, 19, 0 } rfbuffer.h 　
1753
 AR5K_RF5111_WAIT_IAR5K_RF5111_WAIT_I { 5, 24, 0 } rfbuffer.h 　
1754
 AR5K_RF5111_MAX_TIMEAR5K_RF5111_MAX_TIME { 2, 49, 0 } rfbuffer.h 　
1755
 AR5K_RF5112X_GAIN_IAR5K_RF5112X_GAIN_I { 6, 14, 0 } rfbuffer.h 　
1756
 AR5K_RF5112X_MIXVGA_OVRAR5K_RF5112X_MIXVGA_OVR { 1, 36, 0 } rfbuffer.h 　
1757
 AR5K_RF5112X_MIXGAIN_OVRAR5K_RF5112X_MIXGAIN_OVR { 2, 37, 0 } rfbuffer.h 　
1758
 AR5K_RF5112X_MIXGAIN_STEPAR5K_RF5112X_MIXGAIN_STEP { 4, 32, 0 } rfbuffer.h 　
1759
 AR5K_RF5112X_PD_DELAY_AAR5K_RF5112X_PD_DELAY_A { 4, 58, 0 } rfbuffer.h 　
1760
 AR5K_RF5112X_PD_DELAY_BAR5K_RF5112X_PD_DELAY_B { 4, 62, 0 } rfbuffer.h 　
1761
 AR5K_RF5112X_PD_DELAY_XRAR5K_RF5112X_PD_DELAY_XR { 4, 66, 0 } rfbuffer.h 　
1762
 AR5K_RF5112X_PD_PERIOD_AAR5K_RF5112X_PD_PERIOD_A { 4, 70, 0 } rfbuffer.h 　
1763
 AR5K_RF5112X_PD_PERIOD_BAR5K_RF5112X_PD_PERIOD_B { 4, 74, 0 } rfbuffer.h 　
1764
 AR5K_RF5112X_PD_PERIOD_XRAR5K_RF5112X_PD_PERIOD_XR { 4, 78, 0 } rfbuffer.h 　
1765
 AR5K_RF5112_OB_2GHZAR5K_RF5112_OB_2GHZ { 3, 269, 0 } rfbuffer.h 　
1766
 AR5K_RF5112_DB_2GHZAR5K_RF5112_DB_2GHZ { 3, 272, 0 } rfbuffer.h 　
1767
 AR5K_RF5112_OB_5GHZAR5K_RF5112_OB_5GHZ { 3, 261, 0 } rfbuffer.h 　
1768
 AR5K_RF5112_DB_5GHZAR5K_RF5112_DB_5GHZ { 3, 264, 0 } rfbuffer.h 　
1769
 AR5K_RF5112_FIXED_BIAS_AAR5K_RF5112_FIXED_BIAS_A { 1, 260, 0 } rfbuffer.h 　
1770
 AR5K_RF5112_FIXED_BIAS_BAR5K_RF5112_FIXED_BIAS_B { 1, 259, 0 } rfbuffer.h 　
1771
 AR5K_RF5112_XPD_SELAR5K_RF5112_XPD_SEL { 1, 284, 0 } rfbuffer.h 　
1772
 AR5K_RF5112_XPD_GAINAR5K_RF5112_XPD_GAIN { 2, 252, 0 } rfbuffer.h 　
1773
 AR5K_RF5112A_OB_2GHZAR5K_RF5112A_OB_2GHZ { 3, 287, 0 } rfbuffer.h 　
1774
 AR5K_RF5112A_DB_2GHZAR5K_RF5112A_DB_2GHZ { 3, 290, 0 } rfbuffer.h 　
1775
 AR5K_RF5112A_OB_5GHZAR5K_RF5112A_OB_5GHZ { 3, 279, 0 } rfbuffer.h 　
1776
 AR5K_RF5112A_DB_5GHZAR5K_RF5112A_DB_5GHZ { 3, 282, 0 } rfbuffer.h 　
1777
 AR5K_RF5112A_FIXED_BIAS_AAR5K_RF5112A_FIXED_BIAS_A { 1, 278, 0 } rfbuffer.h 　
1778
 AR5K_RF5112A_FIXED_BIAS_BAR5K_RF5112A_FIXED_BIAS_B { 1, 277, 0 } rfbuffer.h 　
1779
 AR5K_RF5112A_XPD_SELAR5K_RF5112A_XPD_SEL { 1, 302, 0 } rfbuffer.h 　
1780
 AR5K_RF5112A_PDGAINLOAR5K_RF5112A_PDGAINLO { 2, 270, 0 } rfbuffer.h 　
1781
 AR5K_RF5112A_PDGAINHIAR5K_RF5112A_PDGAINHI { 2, 257, 0 } rfbuffer.h 　
1782
 AR5K_RF5112A_HIGH_VC_CPAR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 } rfbuffer.h 　
1783
 AR5K_RF5112A_MID_VC_CPAR5K_RF5112A_MID_VC_CP { 2, 92, 2 } rfbuffer.h 　
1784
 AR5K_RF5112A_LOW_VC_CPAR5K_RF5112A_LOW_VC_CP { 2, 94, 2 } rfbuffer.h 　
1785
 AR5K_RF5112A_PUSH_UPAR5K_RF5112A_PUSH_UP { 1, 254, 2 } rfbuffer.h 　
1786
 AR5K_RF5112A_PAD2GNDAR5K_RF5112A_PAD2GND { 1, 281, 1 } rfbuffer.h 　
1787
 AR5K_RF5112A_XB2_LVLAR5K_RF5112A_XB2_LVL { 2, 1, 3 } rfbuffer.h 　
1788
 AR5K_RF5112A_XB5_LVLAR5K_RF5112A_XB5_LVL { 2, 3, 3 } rfbuffer.h 　
1789
 AR5K_RF2413_OB_2GHZAR5K_RF2413_OB_2GHZ { 3, 168, 0 } rfbuffer.h 　
1790
 AR5K_RF2413_DB_2GHZAR5K_RF2413_DB_2GHZ { 3, 165, 0 } rfbuffer.h 　
1791
 AR5K_RF2316_OB_2GHZAR5K_RF2316_OB_2GHZ { 3, 178, 0 } rfbuffer.h 　
1792
 AR5K_RF2316_DB_2GHZAR5K_RF2316_DB_2GHZ { 3, 175, 0 } rfbuffer.h 　
1793
 AR5K_RF5413_OB_2GHZAR5K_RF5413_OB_2GHZ { 3, 241, 0 } rfbuffer.h 　
1794
 AR5K_RF5413_DB_2GHZAR5K_RF5413_DB_2GHZ { 3, 238, 0 } rfbuffer.h 　
1795
 AR5K_RF5413_OB_5GHZAR5K_RF5413_OB_5GHZ { 3, 247, 0 } rfbuffer.h 　
1796
 AR5K_RF5413_DB_5GHZAR5K_RF5413_DB_5GHZ { 3, 244, 0 } rfbuffer.h 　
1797
 AR5K_RF5413_PWD_ICLOBUF2GAR5K_RF5413_PWD_ICLOBUF2G { 3, 131, 3 } rfbuffer.h 　
1798
 AR5K_RF5413_DERBY_CHAN_SEL_MODEAR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 } rfbuffer.h 　
1799
 AR5K_RF2425_OB_2GHZAR5K_RF2425_OB_2GHZ { 3, 193, 0 } rfbuffer.h 　
1800
 AR5K_RF2425_DB_2GHZAR5K_RF2425_DB_2GHZ { 3, 190, 0 } rfbuffer.h 　
1801
 AR5K_GAIN_CRN_FIX_BITS_5111AR5K_GAIN_CRN_FIX_BITS_5111 4 rfgain.h 　
1802
 AR5K_GAIN_CRN_FIX_BITS_5112AR5K_GAIN_CRN_FIX_BITS_5112 7 rfgain.h 　
1803
 AR5K_GAIN_CRN_MAX_FIX_BITSAR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 rfgain.h 　
1804
 AR5K_GAIN_DYN_ADJUST_HI_MARGINAR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 rfgain.h 　
1805
 AR5K_GAIN_DYN_ADJUST_LO_MARGINAR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 rfgain.h 　
1806
 AR5K_GAIN_CCK_PROBE_CORRAR5K_GAIN_CCK_PROBE_CORR 5 rfgain.h 　
1807
 AR5K_GAIN_CCK_OFDM_GAIN_DELTAAR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 rfgain.h 　
1808
 AR5K_GAIN_STEP_COUNTAR5K_GAIN_STEP_COUNT 10 rfgain.h 　
1809
 IGP01E1000_AGC_LENGTH_TABLE_SIZIGP01E1000_AGC_LENGTH_TABLE_SIZ (sizeof(e1000_igp_cable_length_table) / \ sizeof(e1000_igp_cable_length_table[0])) e1000_82541.c 　
1810
 M88E1000_CABLE_LENGTH_TABLE_SIZM88E1000_CABLE_LENGTH_TABLE_SIZ (sizeof(e1000_m88_cable_length_table) / \ sizeof(e1000_m88_cable_length_table[0])) e1000_phy.c 　
1811
 IGP02E1000_CABLE_LENGTH_TABLE_SIGP02E1000_CABLE_LENGTH_TABLE_S (sizeof(e1000_igp_2_cable_length_table) / \ sizeof(e1000_igp_2_cable_length_table[0])) e1000_phy.c 　
1812
 BAR_0BAR_0 0 e1000.h 　
1813
 BAR_1BAR_1 1 e1000.h 　
1814
 BAR_5BAR_5 5 e1000.h 　
1815
 E1000_DEFAULT_TXDE1000_DEFAULT_TXD 256 e1000.h 　
1816
 E1000_MAX_TXDE1000_MAX_TXD 256 e1000.h 　
1817
 E1000_MIN_TXDE1000_MIN_TXD 80 e1000.h 　
1818
 E1000_MAX_82544_TXDE1000_MAX_82544_TXD 4096 e1000.h 　
1819
 E1000_DEFAULT_TXD_PWRE1000_DEFAULT_TXD_PWR 12 e1000.h 　
1820
 E1000_MAX_TXD_PWRE1000_MAX_TXD_PWR 12 e1000.h 　
1821
 E1000_MIN_TXD_PWRE1000_MIN_TXD_PWR 7 e1000.h 　
1822
 E1000_DEFAULT_RXDE1000_DEFAULT_RXD 256 e1000.h 　
1823
 E1000_MAX_RXDE1000_MAX_RXD 256 e1000.h 　
1824
 E1000_MIN_RXDE1000_MIN_RXD 80 e1000.h 　
1825
 E1000_MAX_82544_RXDE1000_MAX_82544_RXD 4096 e1000.h 　
1826
 E1000_MIN_ITR_USECSE1000_MIN_ITR_USECS 10 e1000.h 100000 irq/sec
1827
 E1000_MAX_ITR_USECSE1000_MAX_ITR_USECS 10000 e1000.h 100 irq/sec
1828
 MAXIMUM_ETHERNET_VLAN_SIZEMAXIMUM_ETHERNET_VLAN_SIZE 1522 e1000.h 　
1829
 E1000_RXBUFFER_128E1000_RXBUFFER_128 128 e1000.h 　
1830
 E1000_RXBUFFER_256E1000_RXBUFFER_256 256 e1000.h 　
1831
 E1000_RXBUFFER_512E1000_RXBUFFER_512 512 e1000.h 　
1832
 E1000_RXBUFFER_1024E1000_RXBUFFER_1024 1024 e1000.h 　
1833
 E1000_RXBUFFER_2048E1000_RXBUFFER_2048 2048 e1000.h 　
1834
 E1000_RXBUFFER_4096E1000_RXBUFFER_4096 4096 e1000.h 　
1835
 E1000_RXBUFFER_8192E1000_RXBUFFER_8192 8192 e1000.h 　
1836
 E1000_RXBUFFER_16384E1000_RXBUFFER_16384 16384 e1000.h 　
1837
 E1000_SMARTSPEED_DOWNSHIFTE1000_SMARTSPEED_DOWNSHIFT 3 e1000.h 　
1838
 E1000_SMARTSPEED_MAXE1000_SMARTSPEED_MAX 15 e1000.h 　
1839
 E1000_PBA_BYTES_SHIFTE1000_PBA_BYTES_SHIFT 0xA e1000.h 　
1840
 E1000_TX_HEAD_ADDR_SHIFTE1000_TX_HEAD_ADDR_SHIFT 7 e1000.h 　
1841
 E1000_PBA_TX_MASKE1000_PBA_TX_MASK 0xFFFF0000 e1000.h 　
1842
 E1000_ERT_2048E1000_ERT_2048 0x100 e1000.h 　
1843
 E1000_FC_PAUSE_TIMEE1000_FC_PAUSE_TIME 0x0680 e1000.h 858 usec
1844
 E1000_TX_QUEUE_WAKEE1000_TX_QUEUE_WAKE 16 e1000.h 　
1845
 E1000_RX_BUFFER_WRITEE1000_RX_BUFFER_WRITE 16 e1000.h Must be power of 2
1846
 AUTO_ALL_MODESAUTO_ALL_MODES 0 e1000.h 　
1847
 E1000_EEPROM_82544_APME1000_EEPROM_82544_APM 0x0004 e1000.h 　
1848
 E1000_EEPROM_APMEE1000_EEPROM_APME 0x0400 e1000.h 　
1849
 E1000_FLAG_HAS_SMBUSE1000_FLAG_HAS_SMBUS (1 << 0) e1000.h 　
1850
 E1000_FLAG_HAS_INTR_MODERATIONE1000_FLAG_HAS_INTR_MODERATION (1 << 4) e1000.h 　
1851
 E1000_FLAG_BAD_TX_CARRIER_STATSE1000_FLAG_BAD_TX_CARRIER_STATS (1 << 6) e1000.h 　
1852
 E1000_FLAG_QUAD_PORT_AE1000_FLAG_QUAD_PORT_A (1 << 8) e1000.h 　
1853
 E1000_FLAG_SMART_POWER_DOWNE1000_FLAG_SMART_POWER_DOWN (1 << 9) e1000.h 　
1854
 NVM_WORD_SIZE_BASE_SHIFT_82541NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1) e1000_82541.h 　
1855
 IGP01E1000_PHY_CHANNEL_NUMIGP01E1000_PHY_CHANNEL_NUM 4 e1000_82541.h 　
1856
 IGP01E1000_PHY_AGC_AIGP01E1000_PHY_AGC_A 0x1172 e1000_82541.h 　
1857
 IGP01E1000_PHY_AGC_BIGP01E1000_PHY_AGC_B 0x1272 e1000_82541.h 　
1858
 IGP01E1000_PHY_AGC_CIGP01E1000_PHY_AGC_C 0x1472 e1000_82541.h 　
1859
 IGP01E1000_PHY_AGC_DIGP01E1000_PHY_AGC_D 0x1872 e1000_82541.h 　
1860
 IGP01E1000_PHY_AGC_PARAM_AIGP01E1000_PHY_AGC_PARAM_A 0x1171 e1000_82541.h 　
1861
 IGP01E1000_PHY_AGC_PARAM_BIGP01E1000_PHY_AGC_PARAM_B 0x1271 e1000_82541.h 　
1862
 IGP01E1000_PHY_AGC_PARAM_CIGP01E1000_PHY_AGC_PARAM_C 0x1471 e1000_82541.h 　
1863
 IGP01E1000_PHY_AGC_PARAM_DIGP01E1000_PHY_AGC_PARAM_D 0x1871 e1000_82541.h 　
1864
 IGP01E1000_PHY_EDAC_MU_INDEXIGP01E1000_PHY_EDAC_MU_INDEX 0xC000 e1000_82541.h 　
1865
 IGP01E1000_PHY_EDAC_SIGN_EXT_9_IGP01E1000_PHY_EDAC_SIGN_EXT_9_ 0x8000 e1000_82541.h 　
1866
 IGP01E1000_PHY_DSP_RESETIGP01E1000_PHY_DSP_RESET 0x1F33 e1000_82541.h 　
1867
 IGP01E1000_PHY_DSP_FFEIGP01E1000_PHY_DSP_FFE 0x1F35 e1000_82541.h 　
1868
 IGP01E1000_PHY_DSP_FFE_CM_CPIGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 e1000_82541.h 　
1869
 IGP01E1000_PHY_DSP_FFE_DEFAULTIGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A e1000_82541.h 　
1870
 IGP01E1000_IEEE_FORCE_GIGIGP01E1000_IEEE_FORCE_GIG 0x0140 e1000_82541.h 　
1871
 IGP01E1000_IEEE_RESTART_AUTONEGIGP01E1000_IEEE_RESTART_AUTONEG 0x3300 e1000_82541.h 　
1872
 IGP01E1000_AGC_LENGTH_SHIFTIGP01E1000_AGC_LENGTH_SHIFT 7 e1000_82541.h 　
1873
 IGP01E1000_AGC_RANGEIGP01E1000_AGC_RANGE 10 e1000_82541.h 　
1874
 FFE_IDLE_ERR_COUNT_TIMEOUT_20FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 e1000_82541.h 　
1875
 FFE_IDLE_ERR_COUNT_TIMEOUT_100FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 e1000_82541.h 　
1876
 IGP01E1000_ANALOG_FUSE_STATUSIGP01E1000_ANALOG_FUSE_STATUS 0x20D0 e1000_82541.h 　
1877
 IGP01E1000_ANALOG_SPARE_FUSE_STIGP01E1000_ANALOG_SPARE_FUSE_ST 0x20D1 e1000_82541.h 　
1878
 IGP01E1000_ANALOG_FUSE_CONTROLIGP01E1000_ANALOG_FUSE_CONTROL 0x20DC e1000_82541.h 　
1879
 IGP01E1000_ANALOG_FUSE_BYPASSIGP01E1000_ANALOG_FUSE_BYPASS 0x20DE e1000_82541.h 　
1880
 IGP01E1000_ANALOG_SPARE_FUSE_ENIGP01E1000_ANALOG_SPARE_FUSE_EN 0x0100 e1000_82541.h 　
1881
 IGP01E1000_ANALOG_FUSE_FINE_MASIGP01E1000_ANALOG_FUSE_FINE_MAS 0x0F80 e1000_82541.h 　
1882
 IGP01E1000_ANALOG_FUSE_COARSE_MIGP01E1000_ANALOG_FUSE_COARSE_M 0x0070 e1000_82541.h 　
1883
 IGP01E1000_ANALOG_FUSE_COARSE_TIGP01E1000_ANALOG_FUSE_COARSE_T 0x0040 e1000_82541.h 　
1884
 IGP01E1000_ANALOG_FUSE_COARSE_1IGP01E1000_ANALOG_FUSE_COARSE_1 0x0010 e1000_82541.h 　
1885
 IGP01E1000_ANALOG_FUSE_FINE_1IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 e1000_82541.h 　
1886
 IGP01E1000_ANALOG_FUSE_FINE_10IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 e1000_82541.h 　
1887
 IGP01E1000_ANALOG_FUSE_POLY_MASIGP01E1000_ANALOG_FUSE_POLY_MAS 0xF000 e1000_82541.h 　
1888
 IGP01E1000_ANALOG_FUSE_ENABLE_SIGP01E1000_ANALOG_FUSE_ENABLE_S 0x0002 e1000_82541.h 　
1889
 IGP01E1000_MSE_CHANNEL_DIGP01E1000_MSE_CHANNEL_D 0x000F e1000_82541.h 　
1890
 IGP01E1000_MSE_CHANNEL_CIGP01E1000_MSE_CHANNEL_C 0x00F0 e1000_82541.h 　
1891
 IGP01E1000_MSE_CHANNEL_BIGP01E1000_MSE_CHANNEL_B 0x0F00 e1000_82541.h 　
1892
 IGP01E1000_MSE_CHANNEL_AIGP01E1000_MSE_CHANNEL_A 0xF000 e1000_82541.h 　
1893
 PHY_PREAMBLEPHY_PREAMBLE 0xFFFFFFFF e1000_82543.h 　
1894
 PHY_PREAMBLE_SIZEPHY_PREAMBLE_SIZE 32 e1000_82543.h 　
1895
 PHY_SOFPHY_SOF 0x1 e1000_82543.h 　
1896
 PHY_OP_READPHY_OP_READ 0x2 e1000_82543.h 　
1897
 PHY_OP_WRITEPHY_OP_WRITE 0x1 e1000_82543.h 　
1898
 PHY_TURNAROUNDPHY_TURNAROUND 0x2 e1000_82543.h 　
1899
 TBI_COMPAT_ENABLEDTBI_COMPAT_ENABLED 0x1 e1000_82543.h Global "knob" for the workaround
1900
 TBI_SBP_ENABLEDTBI_SBP_ENABLED 0x2 e1000_82543.h 　
1901
 REQ_TX_DESCRIPTOR_MULTIPLEREQ_TX_DESCRIPTOR_MULTIPLE 8 e1000_defines.h 　
1902
 REQ_RX_DESCRIPTOR_MULTIPLEREQ_RX_DESCRIPTOR_MULTIPLE 8 e1000_defines.h 　
1903
 E1000_WUC_APMEE1000_WUC_APME 0x00000001 e1000_defines.h APM Enable
1904
 E1000_WUC_PME_ENE1000_WUC_PME_EN 0x00000002 e1000_defines.h PME Enable
1905
 E1000_WUC_PME_STATUSE1000_WUC_PME_STATUS 0x00000004 e1000_defines.h PME Status
1906
 E1000_WUC_APMPMEE1000_WUC_APMPME 0x00000008 e1000_defines.h Assert PME on APM Wakeup
1907
 E1000_WUC_LSCWEE1000_WUC_LSCWE 0x00000010 e1000_defines.h Link Status wake up enable
1908
 E1000_WUC_LSCWOE1000_WUC_LSCWO 0x00000020 e1000_defines.h Link Status wake up override
1909
 E1000_WUC_SPME1000_WUC_SPM 0x80000000 e1000_defines.h Enable SPM
1910
 E1000_WUC_PHY_WAKEE1000_WUC_PHY_WAKE 0x00000100 e1000_defines.h if PHY supports wakeup
1911
 E1000_WUFC_LNKCE1000_WUFC_LNKC 0x00000001 e1000_defines.h Link Status Change Wakeup Enable
1912
 E1000_WUFC_MAGE1000_WUFC_MAG 0x00000002 e1000_defines.h Magic Packet Wakeup Enable
1913
 E1000_WUFC_EXE1000_WUFC_EX 0x00000004 e1000_defines.h Directed Exact Wakeup Enable
1914
 E1000_WUFC_MCE1000_WUFC_MC 0x00000008 e1000_defines.h Directed Multicast Wakeup Enable
1915
 E1000_WUFC_BCE1000_WUFC_BC 0x00000010 e1000_defines.h Broadcast Wakeup Enable
1916
 E1000_WUFC_ARPE1000_WUFC_ARP 0x00000020 e1000_defines.h ARP Request Packet Wakeup Enable
1917
 E1000_WUFC_IPV4E1000_WUFC_IPV4 0x00000040 e1000_defines.h Directed IPv4 Packet Wakeup Enable
1918
 E1000_WUFC_IPV6E1000_WUFC_IPV6 0x00000080 e1000_defines.h Directed IPv6 Packet Wakeup Enable
1919
 E1000_WUFC_IGNORE_TCOE1000_WUFC_IGNORE_TCO 0x00008000 e1000_defines.h Ignore WakeOn TCO packets
1920
 E1000_WUFC_FLX0E1000_WUFC_FLX0 0x00010000 e1000_defines.h Flexible Filter 0 Enable
1921
 E1000_WUFC_FLX1E1000_WUFC_FLX1 0x00020000 e1000_defines.h Flexible Filter 1 Enable
1922
 E1000_WUFC_FLX2E1000_WUFC_FLX2 0x00040000 e1000_defines.h Flexible Filter 2 Enable
1923
 E1000_WUFC_FLX3E1000_WUFC_FLX3 0x00080000 e1000_defines.h Flexible Filter 3 Enable
1924
 E1000_WUFC_ALL_FILTERSE1000_WUFC_ALL_FILTERS 0x000F00FF e1000_defines.h Mask for all wakeup filters
1925
 E1000_WUFC_FLX_OFFSETE1000_WUFC_FLX_OFFSET 16 e1000_defines.h Offset to the Flexible Filters bits
1926
 E1000_WUFC_FLX_FILTERSE1000_WUFC_FLX_FILTERS 0x000F0000 e1000_defines.h Mask for the 4 flexible filters
1927
 E1000_WUS_LNKCE1000_WUS_LNKC E1000_WUFC_LNKC e1000_defines.h 　
1928
 E1000_WUS_MAGE1000_WUS_MAG E1000_WUFC_MAG e1000_defines.h 　
1929
 E1000_WUS_EXE1000_WUS_EX E1000_WUFC_EX e1000_defines.h 　
1930
 E1000_WUS_MCE1000_WUS_MC E1000_WUFC_MC e1000_defines.h 　
1931
 E1000_WUS_BCE1000_WUS_BC E1000_WUFC_BC e1000_defines.h 　
1932
 E1000_WUS_ARPE1000_WUS_ARP E1000_WUFC_ARP e1000_defines.h 　
1933
 E1000_WUS_IPV4E1000_WUS_IPV4 E1000_WUFC_IPV4 e1000_defines.h 　
1934
 E1000_WUS_IPV6E1000_WUS_IPV6 E1000_WUFC_IPV6 e1000_defines.h 　
1935
 E1000_WUS_FLX0E1000_WUS_FLX0 E1000_WUFC_FLX0 e1000_defines.h 　
1936
 E1000_WUS_FLX1E1000_WUS_FLX1 E1000_WUFC_FLX1 e1000_defines.h 　
1937
 E1000_WUS_FLX2E1000_WUS_FLX2 E1000_WUFC_FLX2 e1000_defines.h 　
1938
 E1000_WUS_FLX3E1000_WUS_FLX3 E1000_WUFC_FLX3 e1000_defines.h 　
1939
 E1000_WUS_FLX_FILTERSE1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS e1000_defines.h 　
1940
 E1000_WUPL_LENGTH_MASKE1000_WUPL_LENGTH_MASK 0x0FFF e1000_defines.h Only the lower 12 bits are valid
1941
 E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 4 e1000_defines.h 　
1942
 E1000_FLEXIBLE_FILTER_SIZE_MAXE1000_FLEXIBLE_FILTER_SIZE_MAX 128 e1000_defines.h 　
1943
 E1000_FFLT_SIZEE1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX e1000_defines.h 　
1944
 E1000_FFMT_SIZEE1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000_defines.h 　
1945
 E1000_FFVT_SIZEE1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000_defines.h 　
1946
 E1000_CTRL_EXT_GPI0_ENE1000_CTRL_EXT_GPI0_EN 0x00000001 e1000_defines.h Maps SDP4 to GPI0
1947
 E1000_CTRL_EXT_GPI1_ENE1000_CTRL_EXT_GPI1_EN 0x00000002 e1000_defines.h Maps SDP5 to GPI1
1948
 E1000_CTRL_EXT_PHYINT_ENE1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN e1000_defines.h 　
1949
 E1000_CTRL_EXT_GPI2_ENE1000_CTRL_EXT_GPI2_EN 0x00000004 e1000_defines.h Maps SDP6 to GPI2
1950
 E1000_CTRL_EXT_GPI3_ENE1000_CTRL_EXT_GPI3_EN 0x00000008 e1000_defines.h Maps SDP7 to GPI3
1951
 E1000_CTRL_EXT_SDP4_DATAE1000_CTRL_EXT_SDP4_DATA 0x00000010 e1000_defines.h Value of SW Definable Pin 4
1952
 E1000_CTRL_EXT_SDP5_DATAE1000_CTRL_EXT_SDP5_DATA 0x00000020 e1000_defines.h Value of SW Definable Pin 5
1953
 E1000_CTRL_EXT_PHY_INTE1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA e1000_defines.h 　
1954
 E1000_CTRL_EXT_SDP6_DATAE1000_CTRL_EXT_SDP6_DATA 0x00000040 e1000_defines.h Value of SW Definable Pin 6
1955
 E1000_CTRL_EXT_SDP7_DATAE1000_CTRL_EXT_SDP7_DATA 0x00000080 e1000_defines.h Value of SW Definable Pin 7
1956
 E1000_CTRL_EXT_SDP4_DIRE1000_CTRL_EXT_SDP4_DIR 0x00000100 e1000_defines.h Direction of SDP4 0=in 1=out
1957
 E1000_CTRL_EXT_SDP5_DIRE1000_CTRL_EXT_SDP5_DIR 0x00000200 e1000_defines.h Direction of SDP5 0=in 1=out
1958
 E1000_CTRL_EXT_SDP6_DIRE1000_CTRL_EXT_SDP6_DIR 0x00000400 e1000_defines.h Direction of SDP6 0=in 1=out
1959
 E1000_CTRL_EXT_SDP7_DIRE1000_CTRL_EXT_SDP7_DIR 0x00000800 e1000_defines.h Direction of SDP7 0=in 1=out
1960
 E1000_CTRL_EXT_ASDCHKE1000_CTRL_EXT_ASDCHK 0x00001000 e1000_defines.h Initiate an ASD sequence
1961
 E1000_CTRL_EXT_EE_RSTE1000_CTRL_EXT_EE_RST 0x00002000 e1000_defines.h Reinitialize from EEPROM
1962
 E1000_CTRL_EXT_IPSE1000_CTRL_EXT_IPS 0x00004000 e1000_defines.h Invert Power State
1963
 E1000_CTRL_EXT_SPD_BYPSE1000_CTRL_EXT_SPD_BYPS 0x00008000 e1000_defines.h Speed Select Bypass
1964
 E1000_CTRL_EXT_RO_DISE1000_CTRL_EXT_RO_DIS 0x00020000 e1000_defines.h Relaxed Ordering disable
1965
 E1000_CTRL_EXT_DMA_DYN_CLK_ENE1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 e1000_defines.h DMA Dynamic Clock Gating
1966
 E1000_CTRL_EXT_LINK_MODE_MASKE1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 e1000_defines.h 　
1967
 E1000_CTRL_EXT_LINK_MODE_GMIIE1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 e1000_defines.h 　
1968
 E1000_CTRL_EXT_LINK_MODE_TBIE1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 e1000_defines.h 　
1969
 E1000_CTRL_EXT_LINK_MODE_KMRNE1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 e1000_defines.h 　
1970
 E1000_CTRL_EXT_LINK_MODE_PCIE_SE1000_CTRL_EXT_LINK_MODE_PCIE_S 0x00C00000 e1000_defines.h 　
1971
 E1000_CTRL_EXT_LINK_MODE_PCIX_SE1000_CTRL_EXT_LINK_MODE_PCIX_S 0x00800000 e1000_defines.h 　
1972
 E1000_CTRL_EXT_LINK_MODE_SGMIIE1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 e1000_defines.h 　
1973
 E1000_CTRL_EXT_EIAMEE1000_CTRL_EXT_EIAME 0x01000000 e1000_defines.h 　
1974
 E1000_CTRL_EXT_IRCAE1000_CTRL_EXT_IRCA 0x00000001 e1000_defines.h 　
1975
 E1000_CTRL_EXT_WR_WMARK_MASKE1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 e1000_defines.h 　
1976
 E1000_CTRL_EXT_WR_WMARK_256E1000_CTRL_EXT_WR_WMARK_256 0x00000000 e1000_defines.h 　
1977
 E1000_CTRL_EXT_WR_WMARK_320E1000_CTRL_EXT_WR_WMARK_320 0x01000000 e1000_defines.h 　
1978
 E1000_CTRL_EXT_WR_WMARK_384E1000_CTRL_EXT_WR_WMARK_384 0x02000000 e1000_defines.h 　
1979
 E1000_CTRL_EXT_WR_WMARK_448E1000_CTRL_EXT_WR_WMARK_448 0x03000000 e1000_defines.h 　
1980
 E1000_CTRL_EXT_CANCE1000_CTRL_EXT_CANC 0x04000000 e1000_defines.h Int delay cancellation
1981
 E1000_CTRL_EXT_DRV_LOADE1000_CTRL_EXT_DRV_LOAD 0x10000000 e1000_defines.h Driver loaded bit for FW
1982
 E1000_CTRL_EXT_IAMEE1000_CTRL_EXT_IAME 0x08000000 e1000_defines.h Int acknowledge Auto-mask
1983
 E1000_CRTL_EXT_PB_PARENE1000_CRTL_EXT_PB_PAREN 0x01000000 e1000_defines.h packet buffer parity error
1984
 E1000_CTRL_EXT_DF_PARENE1000_CTRL_EXT_DF_PAREN 0x02000000 e1000_defines.h descriptor FIFO parity
1985
 E1000_CTRL_EXT_GHOST_PARENE1000_CTRL_EXT_GHOST_PAREN 0x40000000 e1000_defines.h 　
1986
 E1000_CTRL_EXT_PBA_CLRE1000_CTRL_EXT_PBA_CLR 0x80000000 e1000_defines.h PBA Clear
1987
 E1000_I2CCMD_REG_ADDR_SHIFTE1000_I2CCMD_REG_ADDR_SHIFT 16 e1000_defines.h 　
1988
 E1000_I2CCMD_REG_ADDRE1000_I2CCMD_REG_ADDR 0x00FF0000 e1000_defines.h 　
1989
 E1000_I2CCMD_PHY_ADDR_SHIFTE1000_I2CCMD_PHY_ADDR_SHIFT 24 e1000_defines.h 　
1990
 E1000_I2CCMD_PHY_ADDRE1000_I2CCMD_PHY_ADDR 0x07000000 e1000_defines.h 　
1991
 E1000_I2CCMD_OPCODE_READE1000_I2CCMD_OPCODE_READ 0x08000000 e1000_defines.h 　
1992
 E1000_I2CCMD_OPCODE_WRITEE1000_I2CCMD_OPCODE_WRITE 0x00000000 e1000_defines.h 　
1993
 E1000_I2CCMD_RESETE1000_I2CCMD_RESET 0x10000000 e1000_defines.h 　
1994
 E1000_I2CCMD_READYE1000_I2CCMD_READY 0x20000000 e1000_defines.h 　
1995
 E1000_I2CCMD_INTERRUPT_ENAE1000_I2CCMD_INTERRUPT_ENA 0x40000000 e1000_defines.h 　
1996
 E1000_I2CCMD_ERRORE1000_I2CCMD_ERROR 0x80000000 e1000_defines.h 　
1997
 E1000_MAX_SGMII_PHY_REG_ADDRE1000_MAX_SGMII_PHY_REG_ADDR 255 e1000_defines.h 　
1998
 E1000_I2CCMD_PHY_TIMEOUTE1000_I2CCMD_PHY_TIMEOUT 200 e1000_defines.h 　
1999
 E1000_RXD_STAT_DDE1000_RXD_STAT_DD 0x01 e1000_defines.h Descriptor Done
2000
 E1000_RXD_STAT_EOPE1000_RXD_STAT_EOP 0x02 e1000_defines.h End of Packet
2001
 E1000_RXD_STAT_IXSME1000_RXD_STAT_IXSM 0x04 e1000_defines.h Ignore checksum
2002
 E1000_RXD_STAT_VPE1000_RXD_STAT_VP 0x08 e1000_defines.h IEEE VLAN Packet
2003
 E1000_RXD_STAT_UDPCSE1000_RXD_STAT_UDPCS 0x10 e1000_defines.h UDP xsum calculated
2004
 E1000_RXD_STAT_TCPCSE1000_RXD_STAT_TCPCS 0x20 e1000_defines.h TCP xsum calculated
2005
 E1000_RXD_STAT_IPCSE1000_RXD_STAT_IPCS 0x40 e1000_defines.h IP xsum calculated
2006
 E1000_RXD_STAT_PIFE1000_RXD_STAT_PIF 0x80 e1000_defines.h passed in-exact filter
2007
 E1000_RXD_STAT_CRCVE1000_RXD_STAT_CRCV 0x100 e1000_defines.h Speculative CRC Valid
2008
 E1000_RXD_STAT_IPIDVE1000_RXD_STAT_IPIDV 0x200 e1000_defines.h IP identification valid
2009
 E1000_RXD_STAT_UDPVE1000_RXD_STAT_UDPV 0x400 e1000_defines.h Valid UDP checksum
2010
 E1000_RXD_STAT_DYNINTE1000_RXD_STAT_DYNINT 0x800 e1000_defines.h Pkt caused INT via DYNINT
2011
 E1000_RXD_STAT_ACKE1000_RXD_STAT_ACK 0x8000 e1000_defines.h ACK Packet indication
2012
 E1000_RXD_ERR_CEE1000_RXD_ERR_CE 0x01 e1000_defines.h CRC Error
2013
 E1000_RXD_ERR_SEE1000_RXD_ERR_SE 0x02 e1000_defines.h Symbol Error
2014
 E1000_RXD_ERR_SEQE1000_RXD_ERR_SEQ 0x04 e1000_defines.h Sequence Error
2015
 E1000_RXD_ERR_CXEE1000_RXD_ERR_CXE 0x10 e1000_defines.h Carrier Extension Error
2016
 E1000_RXD_ERR_TCPEE1000_RXD_ERR_TCPE 0x20 e1000_defines.h TCP/UDP Checksum Error
2017
 E1000_RXD_ERR_IPEE1000_RXD_ERR_IPE 0x40 e1000_defines.h IP Checksum Error
2018
 E1000_RXD_ERR_RXEE1000_RXD_ERR_RXE 0x80 e1000_defines.h Rx Data Error
2019
 E1000_RXD_SPC_VLAN_MASKE1000_RXD_SPC_VLAN_MASK 0x0FFF e1000_defines.h VLAN ID is in lower 12 bits
2020
 E1000_RXD_SPC_PRI_MASKE1000_RXD_SPC_PRI_MASK 0xE000 e1000_defines.h Priority is in upper 3 bits
2021
 E1000_RXD_SPC_PRI_SHIFTE1000_RXD_SPC_PRI_SHIFT 13 e1000_defines.h 　
2022
 E1000_RXD_SPC_CFI_MASKE1000_RXD_SPC_CFI_MASK 0x1000 e1000_defines.h CFI is bit 12
2023
 E1000_RXD_SPC_CFI_SHIFTE1000_RXD_SPC_CFI_SHIFT 12 e1000_defines.h 　
2024
 E1000_RXDEXT_STATERR_CEE1000_RXDEXT_STATERR_CE 0x01000000 e1000_defines.h 　
2025
 E1000_RXDEXT_STATERR_SEE1000_RXDEXT_STATERR_SE 0x02000000 e1000_defines.h 　
2026
 E1000_RXDEXT_STATERR_SEQE1000_RXDEXT_STATERR_SEQ 0x04000000 e1000_defines.h 　
2027
 E1000_RXDEXT_STATERR_CXEE1000_RXDEXT_STATERR_CXE 0x10000000 e1000_defines.h 　
2028
 E1000_RXDEXT_STATERR_TCPEE1000_RXDEXT_STATERR_TCPE 0x20000000 e1000_defines.h 　
2029
 E1000_RXDEXT_STATERR_IPEE1000_RXDEXT_STATERR_IPE 0x40000000 e1000_defines.h 　
2030
 E1000_RXDEXT_STATERR_RXEE1000_RXDEXT_STATERR_RXE 0x80000000 e1000_defines.h 　
2031
 E1000_RXD_ERR_FRAME_ERR_MASKE1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ E1000_RXD_ERR_SE | \ E1000_RXD_ERR_SEQ | \ E1000_RXD_ER e1000_defines.h 　
2032
 E1000_RXDEXT_ERR_FRAME_ERR_MASKE1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_SE | \ E1000_RXDEXT_STATERR_SEQ | \ E10 e1000_defines.h 　
2033
 E1000_MRQC_ENABLE_MASKE1000_MRQC_ENABLE_MASK 0x00000007 e1000_defines.h 　
2034
 E1000_MRQC_ENABLE_RSS_2QE1000_MRQC_ENABLE_RSS_2Q 0x00000001 e1000_defines.h 　
2035
 E1000_MRQC_ENABLE_RSS_INTE1000_MRQC_ENABLE_RSS_INT 0x00000004 e1000_defines.h 　
2036
 E1000_MRQC_RSS_FIELD_MASKE1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 e1000_defines.h 　
2037
 E1000_MRQC_RSS_FIELD_IPV4_TCPE1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 e1000_defines.h 　
2038
 E1000_MRQC_RSS_FIELD_IPV4E1000_MRQC_RSS_FIELD_IPV4 0x00020000 e1000_defines.h 　
2039
 E1000_MRQC_RSS_FIELD_IPV6_TCP_EE1000_MRQC_RSS_FIELD_IPV6_TCP_E 0x00040000 e1000_defines.h 　
2040
 E1000_MRQC_RSS_FIELD_IPV6_EXE1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 e1000_defines.h 　
2041
 E1000_MRQC_RSS_FIELD_IPV6E1000_MRQC_RSS_FIELD_IPV6 0x00100000 e1000_defines.h 　
2042
 E1000_MRQC_RSS_FIELD_IPV6_TCPE1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 e1000_defines.h 　
2043
 E1000_RXDPS_HDRSTAT_HDRSPE1000_RXDPS_HDRSTAT_HDRSP 0x00008000 e1000_defines.h 　
2044
 E1000_RXDPS_HDRSTAT_HDRLEN_MASKE1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF e1000_defines.h 　
2045
 E1000_MANC_SMBUS_ENE1000_MANC_SMBUS_EN 0x00000001 e1000_defines.h SMBus Enabled - RO
2046
 E1000_MANC_ASF_ENE1000_MANC_ASF_EN 0x00000002 e1000_defines.h ASF Enabled - RO
2047
 E1000_MANC_R_ON_FORCEE1000_MANC_R_ON_FORCE 0x00000004 e1000_defines.h Reset on Force TCO - RO
2048
 E1000_MANC_RMCP_ENE1000_MANC_RMCP_EN 0x00000100 e1000_defines.h Enable RCMP 026Fh Filtering
2049
 E1000_MANC_0298_ENE1000_MANC_0298_EN 0x00000200 e1000_defines.h Enable RCMP 0298h Filtering
2050
 E1000_MANC_IPV4_ENE1000_MANC_IPV4_EN 0x00000400 e1000_defines.h Enable IPv4
2051
 E1000_MANC_IPV6_ENE1000_MANC_IPV6_EN 0x00000800 e1000_defines.h Enable IPv6
2052
 E1000_MANC_SNAP_ENE1000_MANC_SNAP_EN 0x00001000 e1000_defines.h Accept LLC/SNAP
2053
 E1000_MANC_ARP_ENE1000_MANC_ARP_EN 0x00002000 e1000_defines.h Enable ARP Request Filtering
2054
 E1000_MANC_NEIGHBOR_ENE1000_MANC_NEIGHBOR_EN 0x00004000 e1000_defines.h 　
2055
 E1000_MANC_ARP_RES_ENE1000_MANC_ARP_RES_EN 0x00008000 e1000_defines.h Enable ARP response Filtering
2056
 E1000_MANC_TCO_RESETE1000_MANC_TCO_RESET 0x00010000 e1000_defines.h TCO Reset Occurred
2057
 E1000_MANC_RCV_TCO_ENE1000_MANC_RCV_TCO_EN 0x00020000 e1000_defines.h Receive TCO Packets Enabled
2058
 E1000_MANC_REPORT_STATUSE1000_MANC_REPORT_STATUS 0x00040000 e1000_defines.h Status Reporting Enabled
2059
 E1000_MANC_RCV_ALLE1000_MANC_RCV_ALL 0x00080000 e1000_defines.h Receive All Enabled
2060
 E1000_MANC_BLK_PHY_RST_ON_IDEE1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 e1000_defines.h Block phy resets
2061
 E1000_MANC_EN_MAC_ADDR_FILTERE1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 e1000_defines.h 　
2062
 E1000_MANC_EN_MNG2HOSTE1000_MANC_EN_MNG2HOST 0x00200000 e1000_defines.h 　
2063
 E1000_MANC_EN_IP_ADDR_FILTERE1000_MANC_EN_IP_ADDR_FILTER 0x00400000 e1000_defines.h 　
2064
 E1000_MANC_EN_XSUM_FILTERE1000_MANC_EN_XSUM_FILTER 0x00800000 e1000_defines.h Enable checksum filtering
2065
 E1000_MANC_BR_ENE1000_MANC_BR_EN 0x01000000 e1000_defines.h Enable broadcast filtering
2066
 E1000_MANC_SMB_REQE1000_MANC_SMB_REQ 0x01000000 e1000_defines.h SMBus Request
2067
 E1000_MANC_SMB_GNTE1000_MANC_SMB_GNT 0x02000000 e1000_defines.h SMBus Grant
2068
 E1000_MANC_SMB_CLK_INE1000_MANC_SMB_CLK_IN 0x04000000 e1000_defines.h SMBus Clock In
2069
 E1000_MANC_SMB_DATA_INE1000_MANC_SMB_DATA_IN 0x08000000 e1000_defines.h SMBus Data In
2070
 E1000_MANC_SMB_DATA_OUTE1000_MANC_SMB_DATA_OUT 0x10000000 e1000_defines.h SMBus Data Out
2071
 E1000_MANC_SMB_CLK_OUTE1000_MANC_SMB_CLK_OUT 0x20000000 e1000_defines.h SMBus Clock Out
2072
 E1000_MANC_SMB_DATA_OUT_SHIFTE1000_MANC_SMB_DATA_OUT_SHIFT 28 e1000_defines.h SMBus Data Out Shift
2073
 E1000_MANC_SMB_CLK_OUT_SHIFTE1000_MANC_SMB_CLK_OUT_SHIFT 29 e1000_defines.h SMBus Clock Out Shift
2074
 E1000_RCTL_RSTE1000_RCTL_RST 0x00000001 e1000_defines.h Software reset
2075
 E1000_RCTL_ENE1000_RCTL_EN 0x00000002 e1000_defines.h enable
2076
 E1000_RCTL_SBPE1000_RCTL_SBP 0x00000004 e1000_defines.h store bad packet
2077
 E1000_RCTL_UPEE1000_RCTL_UPE 0x00000008 e1000_defines.h unicast promisc enable
2078
 E1000_RCTL_MPEE1000_RCTL_MPE 0x00000010 e1000_defines.h multicast promisc enable
2079
 E1000_RCTL_LPEE1000_RCTL_LPE 0x00000020 e1000_defines.h long packet enable
2080
 E1000_RCTL_LBM_NOE1000_RCTL_LBM_NO 0x00000000 e1000_defines.h no loopback mode
2081
 E1000_RCTL_LBM_MACE1000_RCTL_LBM_MAC 0x00000040 e1000_defines.h MAC loopback mode
2082
 E1000_RCTL_LBM_SLPE1000_RCTL_LBM_SLP 0x00000080 e1000_defines.h serial link loopback mode
2083
 E1000_RCTL_LBM_TCVRE1000_RCTL_LBM_TCVR 0x000000C0 e1000_defines.h tcvr loopback mode
2084
 E1000_RCTL_DTYP_MASKE1000_RCTL_DTYP_MASK 0x00000C00 e1000_defines.h Descriptor type mask
2085
 E1000_RCTL_DTYP_PSE1000_RCTL_DTYP_PS 0x00000400 e1000_defines.h Packet Split descriptor
2086
 E1000_RCTL_RDMTS_HALFE1000_RCTL_RDMTS_HALF 0x00000000 e1000_defines.h rx desc min thresh size
2087
 E1000_RCTL_RDMTS_QUATE1000_RCTL_RDMTS_QUAT 0x00000100 e1000_defines.h rx desc min thresh size
2088
 E1000_RCTL_RDMTS_EIGTHE1000_RCTL_RDMTS_EIGTH 0x00000200 e1000_defines.h rx desc min thresh size
2089
 E1000_RCTL_MO_SHIFTE1000_RCTL_MO_SHIFT 12 e1000_defines.h multicast offset shift
2090
 E1000_RCTL_MO_0E1000_RCTL_MO_0 0x00000000 e1000_defines.h multicast offset 11:0
2091
 E1000_RCTL_MO_1E1000_RCTL_MO_1 0x00001000 e1000_defines.h multicast offset 12:1
2092
 E1000_RCTL_MO_2E1000_RCTL_MO_2 0x00002000 e1000_defines.h multicast offset 13:2
2093
 E1000_RCTL_MO_3E1000_RCTL_MO_3 0x00003000 e1000_defines.h multicast offset 15:4
2094
 E1000_RCTL_MDRE1000_RCTL_MDR 0x00004000 e1000_defines.h multicast desc ring 0
2095
 E1000_RCTL_BAME1000_RCTL_BAM 0x00008000 e1000_defines.h broadcast enable
2096
 E1000_RCTL_SZ_2048E1000_RCTL_SZ_2048 0x00000000 e1000_defines.h rx buffer size 2048
2097
 E1000_RCTL_SZ_1024E1000_RCTL_SZ_1024 0x00010000 e1000_defines.h rx buffer size 1024
2098
 E1000_RCTL_SZ_512E1000_RCTL_SZ_512 0x00020000 e1000_defines.h rx buffer size 512
2099
 E1000_RCTL_SZ_256E1000_RCTL_SZ_256 0x00030000 e1000_defines.h rx buffer size 256
2100
 E1000_RCTL_SZ_16384E1000_RCTL_SZ_16384 0x00010000 e1000_defines.h rx buffer size 16384
2101
 E1000_RCTL_SZ_8192E1000_RCTL_SZ_8192 0x00020000 e1000_defines.h rx buffer size 8192
2102
 E1000_RCTL_SZ_4096E1000_RCTL_SZ_4096 0x00030000 e1000_defines.h rx buffer size 4096
2103
 E1000_RCTL_VFEE1000_RCTL_VFE 0x00040000 e1000_defines.h vlan filter enable
2104
 E1000_RCTL_CFIENE1000_RCTL_CFIEN 0x00080000 e1000_defines.h canonical form enable
2105
 E1000_RCTL_CFIE1000_RCTL_CFI 0x00100000 e1000_defines.h canonical form indicator
2106
 E1000_RCTL_DPFE1000_RCTL_DPF 0x00400000 e1000_defines.h discard pause frames
2107
 E1000_RCTL_PMCFE1000_RCTL_PMCF 0x00800000 e1000_defines.h pass MAC control frames
2108
 E1000_RCTL_BSEXE1000_RCTL_BSEX 0x02000000 e1000_defines.h Buffer size extension
2109
 E1000_RCTL_SECRCE1000_RCTL_SECRC 0x04000000 e1000_defines.h Strip Ethernet CRC
2110
 E1000_RCTL_FLXBUF_MASKE1000_RCTL_FLXBUF_MASK 0x78000000 e1000_defines.h Flexible buffer size
2111
 E1000_RCTL_FLXBUF_SHIFTE1000_RCTL_FLXBUF_SHIFT 27 e1000_defines.h Flexible buffer shift
2112
 E1000_PSRCTL_BSIZE0_MASKE1000_PSRCTL_BSIZE0_MASK 0x0000007F e1000_defines.h 　
2113
 E1000_PSRCTL_BSIZE1_MASKE1000_PSRCTL_BSIZE1_MASK 0x00003F00 e1000_defines.h 　
2114
 E1000_PSRCTL_BSIZE2_MASKE1000_PSRCTL_BSIZE2_MASK 0x003F0000 e1000_defines.h 　
2115
 E1000_PSRCTL_BSIZE3_MASKE1000_PSRCTL_BSIZE3_MASK 0x3F000000 e1000_defines.h 　
2116
 E1000_PSRCTL_BSIZE0_SHIFTE1000_PSRCTL_BSIZE0_SHIFT 7 e1000_defines.h Shift _right_ 7
2117
 E1000_PSRCTL_BSIZE1_SHIFTE1000_PSRCTL_BSIZE1_SHIFT 2 e1000_defines.h Shift _right_ 2
2118
 E1000_PSRCTL_BSIZE2_SHIFTE1000_PSRCTL_BSIZE2_SHIFT 6 e1000_defines.h Shift _left_ 6
2119
 E1000_PSRCTL_BSIZE3_SHIFTE1000_PSRCTL_BSIZE3_SHIFT 14 e1000_defines.h Shift _left_ 14
2120
 E1000_SWFW_EEP_SME1000_SWFW_EEP_SM 0x01 e1000_defines.h 　
2121
 E1000_SWFW_PHY0_SME1000_SWFW_PHY0_SM 0x02 e1000_defines.h 　
2122
 E1000_SWFW_PHY1_SME1000_SWFW_PHY1_SM 0x04 e1000_defines.h 　
2123
 E1000_SWFW_CSR_SME1000_SWFW_CSR_SM 0x08 e1000_defines.h 　
2124
 E1000_FACTPS_LFSE1000_FACTPS_LFS 0x40000000 e1000_defines.h LAN Function Select
2125
 E1000_CTRL_FDE1000_CTRL_FD 0x00000001 e1000_defines.h Full duplex.0=half; 1=full
2126
 E1000_CTRL_BEME1000_CTRL_BEM 0x00000002 e1000_defines.h Endian Mode.0=little,1=big
2127
 E1000_CTRL_PRIORE1000_CTRL_PRIOR 0x00000004 e1000_defines.h Priority on PCI. 0=rx,1=fair
2128
 E1000_CTRL_GIO_MASTER_DISABLEE1000_CTRL_GIO_MASTER_DISABLE 0x00000004 e1000_defines.h Blocks new Master reqs
2129
 E1000_CTRL_LRSTE1000_CTRL_LRST 0x00000008 e1000_defines.h Link reset. 0=normal,1=reset
2130
 E1000_CTRL_TMEE1000_CTRL_TME 0x00000010 e1000_defines.h Test mode. 0=normal,1=test
2131
 E1000_CTRL_SLEE1000_CTRL_SLE 0x00000020 e1000_defines.h Serial Link on 0=dis,1=en
2132
 E1000_CTRL_ASDEE1000_CTRL_ASDE 0x00000020 e1000_defines.h Auto-speed detect enable
2133
 E1000_CTRL_SLUE1000_CTRL_SLU 0x00000040 e1000_defines.h Set link up (Force Link)
2134
 E1000_CTRL_ILOSE1000_CTRL_ILOS 0x00000080 e1000_defines.h Invert Loss-Of Signal
2135
 E1000_CTRL_SPD_SELE1000_CTRL_SPD_SEL 0x00000300 e1000_defines.h Speed Select Mask
2136
 E1000_CTRL_SPD_10E1000_CTRL_SPD_10 0x00000000 e1000_defines.h Force 10Mb
2137
 E1000_CTRL_SPD_100E1000_CTRL_SPD_100 0x00000100 e1000_defines.h Force 100Mb
2138
 E1000_CTRL_SPD_1000E1000_CTRL_SPD_1000 0x00000200 e1000_defines.h Force 1Gb
2139
 E1000_CTRL_BEM32E1000_CTRL_BEM32 0x00000400 e1000_defines.h Big Endian 32 mode
2140
 E1000_CTRL_FRCSPDE1000_CTRL_FRCSPD 0x00000800 e1000_defines.h Force Speed
2141
 E1000_CTRL_FRCDPXE1000_CTRL_FRCDPX 0x00001000 e1000_defines.h Force Duplex
2142
 E1000_CTRL_D_UD_ENE1000_CTRL_D_UD_EN 0x00002000 e1000_defines.h Dock/Undock enable
2143
 E1000_CTRL_D_UD_POLARITYE1000_CTRL_D_UD_POLARITY 0x00004000 e1000_defines.h Defined polarity of Dock/Undock
2144
 E1000_CTRL_FORCE_PHY_RESETE1000_CTRL_FORCE_PHY_RESET 0x00008000 e1000_defines.h Reset both PHY ports, through
2145
 E1000_CTRL_EXT_LINK_ENE1000_CTRL_EXT_LINK_EN 0x00010000 e1000_defines.h enable link status from external
2146
 E1000_CTRL_SWDPIN0E1000_CTRL_SWDPIN0 0x00040000 e1000_defines.h SWDPIN 0 value
2147
 E1000_CTRL_SWDPIN1E1000_CTRL_SWDPIN1 0x00080000 e1000_defines.h SWDPIN 1 value
2148
 E1000_CTRL_SWDPIN2E1000_CTRL_SWDPIN2 0x00100000 e1000_defines.h SWDPIN 2 value
2149
 E1000_CTRL_SWDPIN3E1000_CTRL_SWDPIN3 0x00200000 e1000_defines.h SWDPIN 3 value
2150
 E1000_CTRL_SWDPIO0E1000_CTRL_SWDPIO0 0x00400000 e1000_defines.h SWDPIN 0 Input or output
2151
 E1000_CTRL_SWDPIO1E1000_CTRL_SWDPIO1 0x00800000 e1000_defines.h SWDPIN 1 input or output
2152
 E1000_CTRL_SWDPIO2E1000_CTRL_SWDPIO2 0x01000000 e1000_defines.h SWDPIN 2 input or output
2153
 E1000_CTRL_SWDPIO3E1000_CTRL_SWDPIO3 0x02000000 e1000_defines.h SWDPIN 3 input or output
2154
 E1000_CTRL_RSTE1000_CTRL_RST 0x04000000 e1000_defines.h Global reset
2155
 E1000_CTRL_RFCEE1000_CTRL_RFCE 0x08000000 e1000_defines.h Receive Flow Control enable
2156
 E1000_CTRL_TFCEE1000_CTRL_TFCE 0x10000000 e1000_defines.h Transmit flow control enable
2157
 E1000_CTRL_RTEE1000_CTRL_RTE 0x20000000 e1000_defines.h Routing tag enable
2158
 E1000_CTRL_VMEE1000_CTRL_VME 0x40000000 e1000_defines.h IEEE VLAN mode enable
2159
 E1000_CTRL_PHY_RSTE1000_CTRL_PHY_RST 0x80000000 e1000_defines.h PHY Reset
2160
 E1000_CTRL_SW2FW_INTE1000_CTRL_SW2FW_INT 0x02000000 e1000_defines.h Initiate an interrupt to ME
2161
 E1000_CTRL_I2C_ENAE1000_CTRL_I2C_ENA 0x02000000 e1000_defines.h I2C enable
2162
 E1000_CTRL_PHY_RESET_DIRE1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 e1000_defines.h 　
2163
 E1000_CTRL_PHY_RESETE1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 e1000_defines.h 　
2164
 E1000_CTRL_MDIO_DIRE1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 e1000_defines.h 　
2165
 E1000_CTRL_MDIOE1000_CTRL_MDIO E1000_CTRL_SWDPIN2 e1000_defines.h 　
2166
 E1000_CTRL_MDC_DIRE1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 e1000_defines.h 　
2167
 E1000_CTRL_MDCE1000_CTRL_MDC E1000_CTRL_SWDPIN3 e1000_defines.h 　
2168
 E1000_CTRL_PHY_RESET_DIR4E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR e1000_defines.h 　
2169
 E1000_CTRL_PHY_RESET4E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA e1000_defines.h 　
2170
 E1000_CONNSW_ENRGSRCE1000_CONNSW_ENRGSRC 0x4 e1000_defines.h 　
2171
 E1000_PCS_CFG_PCS_ENE1000_PCS_CFG_PCS_EN 8 e1000_defines.h 　
2172
 E1000_PCS_LCTL_FLV_LINK_UPE1000_PCS_LCTL_FLV_LINK_UP 1 e1000_defines.h 　
2173
 E1000_PCS_LCTL_FSV_10E1000_PCS_LCTL_FSV_10 0 e1000_defines.h 　
2174
 E1000_PCS_LCTL_FSV_100E1000_PCS_LCTL_FSV_100 2 e1000_defines.h 　
2175
 E1000_PCS_LCTL_FSV_1000E1000_PCS_LCTL_FSV_1000 4 e1000_defines.h 　
2176
 E1000_PCS_LCTL_FDV_FULLE1000_PCS_LCTL_FDV_FULL 8 e1000_defines.h 　
2177
 E1000_PCS_LCTL_FSDE1000_PCS_LCTL_FSD 0x10 e1000_defines.h 　
2178
 E1000_PCS_LCTL_FORCE_LINKE1000_PCS_LCTL_FORCE_LINK 0x20 e1000_defines.h 　
2179
 E1000_PCS_LCTL_LOW_LINK_LATCHE1000_PCS_LCTL_LOW_LINK_LATCH 0x40 e1000_defines.h 　
2180
 E1000_PCS_LCTL_FORCE_FCTRLE1000_PCS_LCTL_FORCE_FCTRL 0x80 e1000_defines.h 　
2181
 E1000_PCS_LCTL_AN_ENABLEE1000_PCS_LCTL_AN_ENABLE 0x10000 e1000_defines.h 　
2182
 E1000_PCS_LCTL_AN_RESTARTE1000_PCS_LCTL_AN_RESTART 0x20000 e1000_defines.h 　
2183
 E1000_PCS_LCTL_AN_TIMEOUTE1000_PCS_LCTL_AN_TIMEOUT 0x40000 e1000_defines.h 　
2184
 E1000_PCS_LCTL_AN_SGMII_BYPASSE1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 e1000_defines.h 　
2185
 E1000_PCS_LCTL_AN_SGMII_TRIGGERE1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 e1000_defines.h 　
2186
 E1000_PCS_LCTL_FAST_LINK_TIMERE1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 e1000_defines.h 　
2187
 E1000_PCS_LCTL_LINK_OK_FIXE1000_PCS_LCTL_LINK_OK_FIX 0x2000000 e1000_defines.h 　
2188
 E1000_PCS_LCTL_CRS_ON_NIE1000_PCS_LCTL_CRS_ON_NI 0x4000000 e1000_defines.h 　
2189
 E1000_ENABLE_SERDES_LOOPBACKE1000_ENABLE_SERDES_LOOPBACK 0x0410 e1000_defines.h 　
2190
 E1000_PCS_LSTS_LINK_OKE1000_PCS_LSTS_LINK_OK 1 e1000_defines.h 　
2191
 E1000_PCS_LSTS_SPEED_10E1000_PCS_LSTS_SPEED_10 0 e1000_defines.h 　
2192
 E1000_PCS_LSTS_SPEED_100E1000_PCS_LSTS_SPEED_100 2 e1000_defines.h 　
2193
 E1000_PCS_LSTS_SPEED_1000E1000_PCS_LSTS_SPEED_1000 4 e1000_defines.h 　
2194
 E1000_PCS_LSTS_DUPLEX_FULLE1000_PCS_LSTS_DUPLEX_FULL 8 e1000_defines.h 　
2195
 E1000_PCS_LSTS_SYNK_OKE1000_PCS_LSTS_SYNK_OK 0x10 e1000_defines.h 　
2196
 E1000_PCS_LSTS_AN_COMPLETEE1000_PCS_LSTS_AN_COMPLETE 0x10000 e1000_defines.h 　
2197
 E1000_PCS_LSTS_AN_PAGE_RXE1000_PCS_LSTS_AN_PAGE_RX 0x20000 e1000_defines.h 　
2198
 E1000_PCS_LSTS_AN_TIMED_OUTE1000_PCS_LSTS_AN_TIMED_OUT 0x40000 e1000_defines.h 　
2199
 E1000_PCS_LSTS_AN_REMOTE_FAULTE1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 e1000_defines.h 　
2200
 E1000_PCS_LSTS_AN_ERROR_RWSE1000_PCS_LSTS_AN_ERROR_RWS 0x100000 e1000_defines.h 　
2201
 E1000_STATUS_FDE1000_STATUS_FD 0x00000001 e1000_defines.h Full duplex.0=half,1=full
2202
 E1000_STATUS_LUE1000_STATUS_LU 0x00000002 e1000_defines.h Link up.0=no,1=link
2203
 E1000_STATUS_FUNC_MASKE1000_STATUS_FUNC_MASK 0x0000000C e1000_defines.h PCI Function Mask
2204
 E1000_STATUS_FUNC_SHIFTE1000_STATUS_FUNC_SHIFT 2 e1000_defines.h 　
2205
 E1000_STATUS_FUNC_0E1000_STATUS_FUNC_0 0x00000000 e1000_defines.h Function 0
2206
 E1000_STATUS_FUNC_1E1000_STATUS_FUNC_1 0x00000004 e1000_defines.h Function 1
2207
 E1000_STATUS_TXOFFE1000_STATUS_TXOFF 0x00000010 e1000_defines.h transmission paused
2208
 E1000_STATUS_TBIMODEE1000_STATUS_TBIMODE 0x00000020 e1000_defines.h TBI mode
2209
 E1000_STATUS_SPEED_MASKE1000_STATUS_SPEED_MASK 0x000000C0 e1000_defines.h 　
2210
 E1000_STATUS_SPEED_10E1000_STATUS_SPEED_10 0x00000000 e1000_defines.h Speed 10Mb/s
2211
 E1000_STATUS_SPEED_100E1000_STATUS_SPEED_100 0x00000040 e1000_defines.h Speed 100Mb/s
2212
 E1000_STATUS_SPEED_1000E1000_STATUS_SPEED_1000 0x00000080 e1000_defines.h Speed 1000Mb/s
2213
 E1000_STATUS_LAN_INIT_DONEE1000_STATUS_LAN_INIT_DONE 0x00000200 e1000_defines.h Lan Init Completion by NVM
2214
 E1000_STATUS_ASDVE1000_STATUS_ASDV 0x00000300 e1000_defines.h Auto speed detect value
2215
 E1000_STATUS_PHYRAE1000_STATUS_PHYRA 0x00000400 e1000_defines.h PHY Reset Asserted
2216
 E1000_STATUS_DOCK_CIE1000_STATUS_DOCK_CI 0x00000800 e1000_defines.h Change in Dock/Undock state.
2217
 E1000_STATUS_GIO_MASTER_ENABLEE1000_STATUS_GIO_MASTER_ENABLE 0x00080000 e1000_defines.h Master request status
2218
 E1000_STATUS_MTXCKOKE1000_STATUS_MTXCKOK 0x00000400 e1000_defines.h MTX clock running OK
2219
 E1000_STATUS_PCI66E1000_STATUS_PCI66 0x00000800 e1000_defines.h In 66Mhz slot
2220
 E1000_STATUS_BUS64E1000_STATUS_BUS64 0x00001000 e1000_defines.h In 64 bit slot
2221
 E1000_STATUS_PCIX_MODEE1000_STATUS_PCIX_MODE 0x00002000 e1000_defines.h PCI-X mode
2222
 E1000_STATUS_PCIX_SPEEDE1000_STATUS_PCIX_SPEED 0x0000C000 e1000_defines.h PCI-X bus speed
2223
 E1000_STATUS_BMC_SKU_0E1000_STATUS_BMC_SKU_0 0x00100000 e1000_defines.h BMC USB redirect disabled
2224
 E1000_STATUS_BMC_SKU_1E1000_STATUS_BMC_SKU_1 0x00200000 e1000_defines.h BMC SRAM disabled
2225
 E1000_STATUS_BMC_SKU_2E1000_STATUS_BMC_SKU_2 0x00400000 e1000_defines.h BMC SDRAM disabled
2226
 E1000_STATUS_BMC_CRYPTOE1000_STATUS_BMC_CRYPTO 0x00800000 e1000_defines.h BMC crypto disabled
2227
 E1000_STATUS_BMC_LITEE1000_STATUS_BMC_LITE 0x01000000 e1000_defines.h BMC external code execution
2228
 E1000_STATUS_RGMII_ENABLEE1000_STATUS_RGMII_ENABLE 0x02000000 e1000_defines.h RGMII disabled
2229
 E1000_STATUS_FUSE_8E1000_STATUS_FUSE_8 0x04000000 e1000_defines.h 　
2230
 E1000_STATUS_FUSE_9E1000_STATUS_FUSE_9 0x08000000 e1000_defines.h 　
2231
 E1000_STATUS_SERDES0_DISE1000_STATUS_SERDES0_DIS 0x10000000 e1000_defines.h SERDES disabled on port 0
2232
 E1000_STATUS_SERDES1_DISE1000_STATUS_SERDES1_DIS 0x20000000 e1000_defines.h SERDES disabled on port 1
2233
 E1000_STATUS_PCIX_SPEED_66E1000_STATUS_PCIX_SPEED_66 0x00000000 e1000_defines.h PCI-X bus speed 50-66 MHz
2234
 E1000_STATUS_PCIX_SPEED_100E1000_STATUS_PCIX_SPEED_100 0x00004000 e1000_defines.h PCI-X bus speed 66-100 MHz
2235
 E1000_STATUS_PCIX_SPEED_133E1000_STATUS_PCIX_SPEED_133 0x00008000 e1000_defines.h PCI-X bus speed 100-133 MHz
2236
 SPEED_10SPEED_10 10 e1000_defines.h 　
2237
 SPEED_100SPEED_100 100 e1000_defines.h 　
2238
 SPEED_1000SPEED_1000 1000 e1000_defines.h 　
2239
 HALF_DUPLEXHALF_DUPLEX 1 e1000_defines.h 　
2240
 FULL_DUPLEXFULL_DUPLEX 2 e1000_defines.h 　
2241
 PHY_FORCE_TIMEPHY_FORCE_TIME 20 e1000_defines.h 　
2242
 ADVERTISE_10_HALFADVERTISE_10_HALF 0x0001 e1000_defines.h 　
2243
 ADVERTISE_10_FULLADVERTISE_10_FULL 0x0002 e1000_defines.h 　
2244
 ADVERTISE_100_HALFADVERTISE_100_HALF 0x0004 e1000_defines.h 　
2245
 ADVERTISE_100_FULLADVERTISE_100_FULL 0x0008 e1000_defines.h 　
2246
 ADVERTISE_1000_HALFADVERTISE_1000_HALF 0x0010 e1000_defines.h Not used, just FYI
2247
 ADVERTISE_1000_FULLADVERTISE_1000_FULL 0x0020 e1000_defines.h 　
2248
 E1000_ALL_SPEED_DUPLEXE1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) e1000_defines.h 　
2249
 E1000_ALL_NOT_GIGE1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL) e1000_defines.h 　
2250
 E1000_ALL_100_SPEEDE1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) e1000_defines.h 　
2251
 E1000_ALL_10_SPEEDE1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) e1000_defines.h 　
2252
 E1000_ALL_FULL_DUPLEXE1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) e1000_defines.h 　
2253
 E1000_ALL_HALF_DUPLEXE1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) e1000_defines.h 　
2254
 AUTONEG_ADVERTISE_SPEED_DEFAULTAUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX e1000_defines.h 　
2255
 E1000_LEDCTL_LED0_MODE_MASKE1000_LEDCTL_LED0_MODE_MASK 0x0000000F e1000_defines.h 　
2256
 E1000_LEDCTL_LED0_MODE_SHIFTE1000_LEDCTL_LED0_MODE_SHIFT 0 e1000_defines.h 　
2257
 E1000_LEDCTL_LED0_BLINK_RATEE1000_LEDCTL_LED0_BLINK_RATE 0x00000020 e1000_defines.h 　
2258
 E1000_LEDCTL_LED0_IVRTE1000_LEDCTL_LED0_IVRT 0x00000040 e1000_defines.h 　
2259
 E1000_LEDCTL_LED0_BLINKE1000_LEDCTL_LED0_BLINK 0x00000080 e1000_defines.h 　
2260
 E1000_LEDCTL_LED1_MODE_MASKE1000_LEDCTL_LED1_MODE_MASK 0x00000F00 e1000_defines.h 　
2261
 E1000_LEDCTL_LED1_MODE_SHIFTE1000_LEDCTL_LED1_MODE_SHIFT 8 e1000_defines.h 　
2262
 E1000_LEDCTL_LED1_BLINK_RATEE1000_LEDCTL_LED1_BLINK_RATE 0x00002000 e1000_defines.h 　
2263
 E1000_LEDCTL_LED1_IVRTE1000_LEDCTL_LED1_IVRT 0x00004000 e1000_defines.h 　
2264
 E1000_LEDCTL_LED1_BLINKE1000_LEDCTL_LED1_BLINK 0x00008000 e1000_defines.h 　
2265
 E1000_LEDCTL_LED2_MODE_MASKE1000_LEDCTL_LED2_MODE_MASK 0x000F0000 e1000_defines.h 　
2266
 E1000_LEDCTL_LED2_MODE_SHIFTE1000_LEDCTL_LED2_MODE_SHIFT 16 e1000_defines.h 　
2267
 E1000_LEDCTL_LED2_BLINK_RATEE1000_LEDCTL_LED2_BLINK_RATE 0x00200000 e1000_defines.h 　
2268
 E1000_LEDCTL_LED2_IVRTE1000_LEDCTL_LED2_IVRT 0x00400000 e1000_defines.h 　
2269
 E1000_LEDCTL_LED2_BLINKE1000_LEDCTL_LED2_BLINK 0x00800000 e1000_defines.h 　
2270
 E1000_LEDCTL_LED3_MODE_MASKE1000_LEDCTL_LED3_MODE_MASK 0x0F000000 e1000_defines.h 　
2271
 E1000_LEDCTL_LED3_MODE_SHIFTE1000_LEDCTL_LED3_MODE_SHIFT 24 e1000_defines.h 　
2272
 E1000_LEDCTL_LED3_BLINK_RATEE1000_LEDCTL_LED3_BLINK_RATE 0x20000000 e1000_defines.h 　
2273
 E1000_LEDCTL_LED3_IVRTE1000_LEDCTL_LED3_IVRT 0x40000000 e1000_defines.h 　
2274
 E1000_LEDCTL_LED3_BLINKE1000_LEDCTL_LED3_BLINK 0x80000000 e1000_defines.h 　
2275
 E1000_LEDCTL_MODE_LINK_10_1000E1000_LEDCTL_MODE_LINK_10_1000 0x0 e1000_defines.h 　
2276
 E1000_LEDCTL_MODE_LINK_100_1000E1000_LEDCTL_MODE_LINK_100_1000 0x1 e1000_defines.h 　
2277
 E1000_LEDCTL_MODE_LINK_UPE1000_LEDCTL_MODE_LINK_UP 0x2 e1000_defines.h 　
2278
 E1000_LEDCTL_MODE_ACTIVITYE1000_LEDCTL_MODE_ACTIVITY 0x3 e1000_defines.h 　
2279
 E1000_LEDCTL_MODE_LINK_ACTIVITYE1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 e1000_defines.h 　
2280
 E1000_LEDCTL_MODE_LINK_10E1000_LEDCTL_MODE_LINK_10 0x5 e1000_defines.h 　
2281
 E1000_LEDCTL_MODE_LINK_100E1000_LEDCTL_MODE_LINK_100 0x6 e1000_defines.h 　
2282
 E1000_LEDCTL_MODE_LINK_1000E1000_LEDCTL_MODE_LINK_1000 0x7 e1000_defines.h 　
2283
 E1000_LEDCTL_MODE_PCIX_MODEE1000_LEDCTL_MODE_PCIX_MODE 0x8 e1000_defines.h 　
2284
 E1000_LEDCTL_MODE_FULL_DUPLEXE1000_LEDCTL_MODE_FULL_DUPLEX 0x9 e1000_defines.h 　
2285
 E1000_LEDCTL_MODE_COLLISIONE1000_LEDCTL_MODE_COLLISION 0xA e1000_defines.h 　
2286
 E1000_LEDCTL_MODE_BUS_SPEEDE1000_LEDCTL_MODE_BUS_SPEED 0xB e1000_defines.h 　
2287
 E1000_LEDCTL_MODE_BUS_SIZEE1000_LEDCTL_MODE_BUS_SIZE 0xC e1000_defines.h 　
2288
 E1000_LEDCTL_MODE_PAUSEDE1000_LEDCTL_MODE_PAUSED 0xD e1000_defines.h 　
2289
 E1000_LEDCTL_MODE_LED_ONE1000_LEDCTL_MODE_LED_ON 0xE e1000_defines.h 　
2290
 E1000_LEDCTL_MODE_LED_OFFE1000_LEDCTL_MODE_LED_OFF 0xF e1000_defines.h 　
2291
 E1000_TXD_DTYP_DE1000_TXD_DTYP_D 0x00100000 e1000_defines.h Data Descriptor
2292
 E1000_TXD_DTYP_CE1000_TXD_DTYP_C 0x00000000 e1000_defines.h Context Descriptor
2293
 E1000_TXD_POPTS_SHIFTE1000_TXD_POPTS_SHIFT 8 e1000_defines.h POPTS shift
2294
 E1000_TXD_POPTS_IXSME1000_TXD_POPTS_IXSM 0x01 e1000_defines.h Insert IP checksum
2295
 E1000_TXD_POPTS_TXSME1000_TXD_POPTS_TXSM 0x02 e1000_defines.h Insert TCP/UDP checksum
2296
 E1000_TXD_CMD_EOPE1000_TXD_CMD_EOP 0x01000000 e1000_defines.h End of Packet
2297
 E1000_TXD_CMD_IFCSE1000_TXD_CMD_IFCS 0x02000000 e1000_defines.h Insert FCS (Ethernet CRC)
2298
 E1000_TXD_CMD_ICE1000_TXD_CMD_IC 0x04000000 e1000_defines.h Insert Checksum
2299
 E1000_TXD_CMD_RSE1000_TXD_CMD_RS 0x08000000 e1000_defines.h Report Status
2300
 E1000_TXD_CMD_RPSE1000_TXD_CMD_RPS 0x10000000 e1000_defines.h Report Packet Sent
2301
 E1000_TXD_CMD_DEXTE1000_TXD_CMD_DEXT 0x20000000 e1000_defines.h Descriptor extension (0 = legacy)
2302
 E1000_TXD_CMD_VLEE1000_TXD_CMD_VLE 0x40000000 e1000_defines.h Add VLAN tag
2303
 E1000_TXD_CMD_IDEE1000_TXD_CMD_IDE 0x80000000 e1000_defines.h Enable Tidv register
2304
 E1000_TXD_STAT_DDE1000_TXD_STAT_DD 0x00000001 e1000_defines.h Descriptor Done
2305
 E1000_TXD_STAT_ECE1000_TXD_STAT_EC 0x00000002 e1000_defines.h Excess Collisions
2306
 E1000_TXD_STAT_LCE1000_TXD_STAT_LC 0x00000004 e1000_defines.h Late Collisions
2307
 E1000_TXD_STAT_TUE1000_TXD_STAT_TU 0x00000008 e1000_defines.h Transmit underrun
2308
 E1000_TXD_CMD_TCPE1000_TXD_CMD_TCP 0x01000000 e1000_defines.h TCP packet
2309
 E1000_TXD_CMD_IPE1000_TXD_CMD_IP 0x02000000 e1000_defines.h IP packet
2310
 E1000_TXD_CMD_TSEE1000_TXD_CMD_TSE 0x04000000 e1000_defines.h TCP Seg enable
2311
 E1000_TXD_STAT_TCE1000_TXD_STAT_TC 0x00000004 e1000_defines.h Tx Underrun
2312
 E1000_TCTL_RSTE1000_TCTL_RST 0x00000001 e1000_defines.h software reset
2313
 E1000_TCTL_ENE1000_TCTL_EN 0x00000002 e1000_defines.h enable tx
2314
 E1000_TCTL_BCEE1000_TCTL_BCE 0x00000004 e1000_defines.h busy check enable
2315
 E1000_TCTL_PSPE1000_TCTL_PSP 0x00000008 e1000_defines.h pad short packets
2316
 E1000_TCTL_CTE1000_TCTL_CT 0x00000ff0 e1000_defines.h collision threshold
2317
 E1000_TCTL_COLDE1000_TCTL_COLD 0x003ff000 e1000_defines.h collision distance
2318
 E1000_TCTL_SWXOFFE1000_TCTL_SWXOFF 0x00400000 e1000_defines.h SW Xoff transmission
2319
 E1000_TCTL_PBEE1000_TCTL_PBE 0x00800000 e1000_defines.h Packet Burst Enable
2320
 E1000_TCTL_RTLCE1000_TCTL_RTLC 0x01000000 e1000_defines.h Re-transmit on late collision
2321
 E1000_TCTL_NRTUE1000_TCTL_NRTU 0x02000000 e1000_defines.h No Re-transmit on underrun
2322
 E1000_TCTL_MULRE1000_TCTL_MULR 0x10000000 e1000_defines.h Multiple request support
2323
 E1000_TARC0_ENABLEE1000_TARC0_ENABLE 0x00000400 e1000_defines.h Enable Tx Queue 0
2324
 E1000_SCTL_DISABLE_SERDES_LOOPBE1000_SCTL_DISABLE_SERDES_LOOPB 0x0400 e1000_defines.h 　
2325
 E1000_RXCSUM_PCSS_MASKE1000_RXCSUM_PCSS_MASK 0x000000FF e1000_defines.h Packet Checksum Start
2326
 E1000_RXCSUM_IPOFLE1000_RXCSUM_IPOFL 0x00000100 e1000_defines.h IPv4 checksum offload
2327
 E1000_RXCSUM_TUOFLE1000_RXCSUM_TUOFL 0x00000200 e1000_defines.h TCP / UDP checksum offload
2328
 E1000_RXCSUM_IPV6OFLE1000_RXCSUM_IPV6OFL 0x00000400 e1000_defines.h IPv6 checksum offload
2329
 E1000_RXCSUM_CRCOFLE1000_RXCSUM_CRCOFL 0x00000800 e1000_defines.h CRC32 offload enable
2330
 E1000_RXCSUM_IPPCSEE1000_RXCSUM_IPPCSE 0x00001000 e1000_defines.h IP payload checksum enable
2331
 E1000_RXCSUM_PCSDE1000_RXCSUM_PCSD 0x00002000 e1000_defines.h packet checksum disabled
2332
 E1000_RFCTL_ISCSI_DISE1000_RFCTL_ISCSI_DIS 0x00000001 e1000_defines.h 　
2333
 E1000_RFCTL_ISCSI_DWC_MASKE1000_RFCTL_ISCSI_DWC_MASK 0x0000003E e1000_defines.h 　
2334
 E1000_RFCTL_ISCSI_DWC_SHIFTE1000_RFCTL_ISCSI_DWC_SHIFT 1 e1000_defines.h 　
2335
 E1000_RFCTL_NFSW_DISE1000_RFCTL_NFSW_DIS 0x00000040 e1000_defines.h 　
2336
 E1000_RFCTL_NFSR_DISE1000_RFCTL_NFSR_DIS 0x00000080 e1000_defines.h 　
2337
 E1000_RFCTL_NFS_VER_MASKE1000_RFCTL_NFS_VER_MASK 0x00000300 e1000_defines.h 　
2338
 E1000_RFCTL_NFS_VER_SHIFTE1000_RFCTL_NFS_VER_SHIFT 8 e1000_defines.h 　
2339
 E1000_RFCTL_IPV6_DISE1000_RFCTL_IPV6_DIS 0x00000400 e1000_defines.h 　
2340
 E1000_RFCTL_IPV6_XSUM_DISE1000_RFCTL_IPV6_XSUM_DIS 0x00000800 e1000_defines.h 　
2341
 E1000_RFCTL_ACK_DISE1000_RFCTL_ACK_DIS 0x00001000 e1000_defines.h 　
2342
 E1000_RFCTL_ACKD_DISE1000_RFCTL_ACKD_DIS 0x00002000 e1000_defines.h 　
2343
 E1000_RFCTL_IPFRSP_DISE1000_RFCTL_IPFRSP_DIS 0x00004000 e1000_defines.h 　
2344
 E1000_RFCTL_EXTENE1000_RFCTL_EXTEN 0x00008000 e1000_defines.h 　
2345
 E1000_RFCTL_IPV6_EX_DISE1000_RFCTL_IPV6_EX_DIS 0x00010000 e1000_defines.h 　
2346
 E1000_RFCTL_NEW_IPV6_EXT_DISE1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 e1000_defines.h 　
2347
 E1000_RFCTL_LEFE1000_RFCTL_LEF 0x00040000 e1000_defines.h 　
2348
 E1000_COLLISION_THRESHOLDE1000_COLLISION_THRESHOLD 15 e1000_defines.h 　
2349
 E1000_CT_SHIFTE1000_CT_SHIFT 4 e1000_defines.h 　
2350
 E1000_COLLISION_DISTANCEE1000_COLLISION_DISTANCE 63 e1000_defines.h 　
2351
 E1000_COLD_SHIFTE1000_COLD_SHIFT 12 e1000_defines.h 　
2352
 DEFAULT_82542_TIPG_IPGTDEFAULT_82542_TIPG_IPGT 10 e1000_defines.h 　
2353
 DEFAULT_82543_TIPG_IPGT_FIBERDEFAULT_82543_TIPG_IPGT_FIBER 9 e1000_defines.h 　
2354
 DEFAULT_82543_TIPG_IPGT_COPPERDEFAULT_82543_TIPG_IPGT_COPPER 8 e1000_defines.h 　
2355
 E1000_TIPG_IPGT_MASKE1000_TIPG_IPGT_MASK 0x000003FF e1000_defines.h 　
2356
 E1000_TIPG_IPGR1_MASKE1000_TIPG_IPGR1_MASK 0x000FFC00 e1000_defines.h 　
2357
 E1000_TIPG_IPGR2_MASKE1000_TIPG_IPGR2_MASK 0x3FF00000 e1000_defines.h 　
2358
 DEFAULT_82542_TIPG_IPGR1DEFAULT_82542_TIPG_IPGR1 2 e1000_defines.h 　
2359
 DEFAULT_82543_TIPG_IPGR1DEFAULT_82543_TIPG_IPGR1 8 e1000_defines.h 　
2360
 E1000_TIPG_IPGR1_SHIFTE1000_TIPG_IPGR1_SHIFT 10 e1000_defines.h 　
2361
 DEFAULT_82542_TIPG_IPGR2DEFAULT_82542_TIPG_IPGR2 10 e1000_defines.h 　
2362
 DEFAULT_82543_TIPG_IPGR2DEFAULT_82543_TIPG_IPGR2 6 e1000_defines.h 　
2363
 DEFAULT_80003ES2LAN_TIPG_IPGR2DEFAULT_80003ES2LAN_TIPG_IPGR2 7 e1000_defines.h 　
2364
 E1000_TIPG_IPGR2_SHIFTE1000_TIPG_IPGR2_SHIFT 20 e1000_defines.h 　
2365
 ETHERNET_IEEE_VLAN_TYPEETHERNET_IEEE_VLAN_TYPE 0x8100 e1000_defines.h 802.3ac packet
2366
 ETHERNET_FCS_SIZEETHERNET_FCS_SIZE 4 e1000_defines.h 　
2367
 MAX_JUMBO_FRAME_SIZEMAX_JUMBO_FRAME_SIZE 0x3F00 e1000_defines.h 　
2368
 E1000_EXTCNF_CTRL_MDIO_SW_OWNERE1000_EXTCNF_CTRL_MDIO_SW_OWNER 0x00000020 e1000_defines.h 　
2369
 E1000_EXTCNF_CTRL_LCD_WRITE_ENAE1000_EXTCNF_CTRL_LCD_WRITE_ENA 0x00000001 e1000_defines.h 　
2370
 E1000_EXTCNF_CTRL_SWFLAGE1000_EXTCNF_CTRL_SWFLAG 0x00000020 e1000_defines.h 　
2371
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 0x00FF0000 e1000_defines.h 　
2372
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 16 e1000_defines.h 　
2373
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 0x0FFF0000 e1000_defines.h 　
2374
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 16 e1000_defines.h 　
2375
 E1000_PHY_CTRL_SPD_ENE1000_PHY_CTRL_SPD_EN 0x00000001 e1000_defines.h 　
2376
 E1000_PHY_CTRL_D0A_LPLUE1000_PHY_CTRL_D0A_LPLU 0x00000002 e1000_defines.h 　
2377
 E1000_PHY_CTRL_NOND0A_LPLUE1000_PHY_CTRL_NOND0A_LPLU 0x00000004 e1000_defines.h 　
2378
 E1000_PHY_CTRL_NOND0A_GBE_DISABE1000_PHY_CTRL_NOND0A_GBE_DISAB 0x00000008 e1000_defines.h 　
2379
 E1000_PHY_CTRL_GBE_DISABLEE1000_PHY_CTRL_GBE_DISABLE 0x00000040 e1000_defines.h 　
2380
 E1000_KABGTXD_BGSQLBIASE1000_KABGTXD_BGSQLBIAS 0x00050000 e1000_defines.h 　
2381
 E1000_PBA_6KE1000_PBA_6K 0x0006 e1000_defines.h 6KB
2382
 E1000_PBA_8KE1000_PBA_8K 0x0008 e1000_defines.h 8KB
2383
 E1000_PBA_10KE1000_PBA_10K 0x000A e1000_defines.h 10KB
2384
 E1000_PBA_12KE1000_PBA_12K 0x000C e1000_defines.h 12KB
2385
 E1000_PBA_14KE1000_PBA_14K 0x000E e1000_defines.h 14KB
2386
 E1000_PBA_16KE1000_PBA_16K 0x0010 e1000_defines.h 16KB
2387
 E1000_PBA_18KE1000_PBA_18K 0x0012 e1000_defines.h 　
2388
 E1000_PBA_20KE1000_PBA_20K 0x0014 e1000_defines.h 　
2389
 E1000_PBA_22KE1000_PBA_22K 0x0016 e1000_defines.h 　
2390
 E1000_PBA_24KE1000_PBA_24K 0x0018 e1000_defines.h 　
2391
 E1000_PBA_26KE1000_PBA_26K 0x001A e1000_defines.h 　
2392
 E1000_PBA_30KE1000_PBA_30K 0x001E e1000_defines.h 　
2393
 E1000_PBA_32KE1000_PBA_32K 0x0020 e1000_defines.h 　
2394
 E1000_PBA_34KE1000_PBA_34K 0x0022 e1000_defines.h 　
2395
 E1000_PBA_35KE1000_PBA_35K 0x0023 e1000_defines.h 　
2396
 E1000_PBA_38KE1000_PBA_38K 0x0026 e1000_defines.h 　
2397
 E1000_PBA_40KE1000_PBA_40K 0x0028 e1000_defines.h 　
2398
 E1000_PBA_48KE1000_PBA_48K 0x0030 e1000_defines.h 48KB
2399
 E1000_PBA_64KE1000_PBA_64K 0x0040 e1000_defines.h 64KB
2400
 E1000_PBS_16KE1000_PBS_16K E1000_PBA_16K e1000_defines.h 　
2401
 E1000_PBS_24KE1000_PBS_24K E1000_PBA_24K e1000_defines.h 　
2402
 IFS_MAXIFS_MAX 80 e1000_defines.h 　
2403
 IFS_MINIFS_MIN 40 e1000_defines.h 　
2404
 IFS_RATIOIFS_RATIO 4 e1000_defines.h 　
2405
 IFS_STEPIFS_STEP 10 e1000_defines.h 　
2406
 MIN_NUM_XMITSMIN_NUM_XMITS 1000 e1000_defines.h 　
2407
 E1000_SWSM_SMBIE1000_SWSM_SMBI 0x00000001 e1000_defines.h Driver Semaphore bit
2408
 E1000_SWSM_SWESMBIE1000_SWSM_SWESMBI 0x00000002 e1000_defines.h FW Semaphore bit
2409
 E1000_SWSM_WMNGE1000_SWSM_WMNG 0x00000004 e1000_defines.h Wake MNG Clock
2410
 E1000_SWSM_DRV_LOADE1000_SWSM_DRV_LOAD 0x00000008 e1000_defines.h Driver Loaded Bit
2411
 E1000_SWSM2_LOCKE1000_SWSM2_LOCK 0x00000002 e1000_defines.h Secondary driver semaphore bit
2412
 E1000_ICR_TXDWE1000_ICR_TXDW 0x00000001 e1000_defines.h Transmit desc written back
2413
 E1000_ICR_TXQEE1000_ICR_TXQE 0x00000002 e1000_defines.h Transmit Queue empty
2414
 E1000_ICR_LSCE1000_ICR_LSC 0x00000004 e1000_defines.h Link Status Change
2415
 E1000_ICR_RXSEQE1000_ICR_RXSEQ 0x00000008 e1000_defines.h rx sequence error
2416
 E1000_ICR_RXDMT0E1000_ICR_RXDMT0 0x00000010 e1000_defines.h rx desc min. threshold (0)
2417
 E1000_ICR_RXOE1000_ICR_RXO 0x00000040 e1000_defines.h rx overrun
2418
 E1000_ICR_RXT0E1000_ICR_RXT0 0x00000080 e1000_defines.h rx timer intr (ring 0)
2419
 E1000_ICR_VMMBE1000_ICR_VMMB 0x00000100 e1000_defines.h VM MB event
2420
 E1000_ICR_MDACE1000_ICR_MDAC 0x00000200 e1000_defines.h MDIO access complete
2421
 E1000_ICR_RXCFGE1000_ICR_RXCFG 0x00000400 e1000_defines.h Rx /c/ ordered set
2422
 E1000_ICR_GPI_EN0E1000_ICR_GPI_EN0 0x00000800 e1000_defines.h GP Int 0
2423
 E1000_ICR_GPI_EN1E1000_ICR_GPI_EN1 0x00001000 e1000_defines.h GP Int 1
2424
 E1000_ICR_GPI_EN2E1000_ICR_GPI_EN2 0x00002000 e1000_defines.h GP Int 2
2425
 E1000_ICR_GPI_EN3E1000_ICR_GPI_EN3 0x00004000 e1000_defines.h GP Int 3
2426
 E1000_ICR_TXD_LOWE1000_ICR_TXD_LOW 0x00008000 e1000_defines.h 　
2427
 E1000_ICR_SRPDE1000_ICR_SRPD 0x00010000 e1000_defines.h 　
2428
 E1000_ICR_ACKE1000_ICR_ACK 0x00020000 e1000_defines.h Receive Ack frame
2429
 E1000_ICR_MNGE1000_ICR_MNG 0x00040000 e1000_defines.h Manageability event
2430
 E1000_ICR_DOCKE1000_ICR_DOCK 0x00080000 e1000_defines.h Dock/Undock
2431
 E1000_ICR_INT_ASSERTEDE1000_ICR_INT_ASSERTED 0x80000000 e1000_defines.h If this bit asserted, the driver
2432
 E1000_ICR_RXD_FIFO_PAR0E1000_ICR_RXD_FIFO_PAR0 0x00100000 e1000_defines.h Q0 Rx desc FIFO parity error
2433
 E1000_ICR_TXD_FIFO_PAR0E1000_ICR_TXD_FIFO_PAR0 0x00200000 e1000_defines.h Q0 Tx desc FIFO parity error
2434
 E1000_ICR_HOST_ARB_PARE1000_ICR_HOST_ARB_PAR 0x00400000 e1000_defines.h host arb read buffer parity err
2435
 E1000_ICR_PB_PARE1000_ICR_PB_PAR 0x00800000 e1000_defines.h packet buffer parity error
2436
 E1000_ICR_RXD_FIFO_PAR1E1000_ICR_RXD_FIFO_PAR1 0x01000000 e1000_defines.h Q1 Rx desc FIFO parity error
2437
 E1000_ICR_TXD_FIFO_PAR1E1000_ICR_TXD_FIFO_PAR1 0x02000000 e1000_defines.h Q1 Tx desc FIFO parity error
2438
 E1000_ICR_ALL_PARITYE1000_ICR_ALL_PARITY 0x03F00000 e1000_defines.h all parity error bits
2439
 E1000_ICR_DSWE1000_ICR_DSW 0x00000020 e1000_defines.h FW changed the status of DISSW
2440
 E1000_ICR_PHYINTE1000_ICR_PHYINT 0x00001000 e1000_defines.h LAN connected device generates
2441
 E1000_ICR_DOUTSYNCE1000_ICR_DOUTSYNC 0x10000000 e1000_defines.h NIC DMA out of sync
2442
 E1000_ICR_EPRSTE1000_ICR_EPRST 0x00100000 e1000_defines.h ME hardware reset occurs
2443
 POLL_IMS_ENABLE_MASKPOLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) e1000_defines.h 　
2444
 IMS_ENABLE_MASKIMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_LSC) e1000_defines.h 　
2445
 E1000_IMS_TXDWE1000_IMS_TXDW E1000_ICR_TXDW e1000_defines.h Tx desc written back
2446
 E1000_IMS_TXQEE1000_IMS_TXQE E1000_ICR_TXQE e1000_defines.h Transmit Queue empty
2447
 E1000_IMS_LSCE1000_IMS_LSC E1000_ICR_LSC e1000_defines.h Link Status Change
2448
 E1000_IMS_VMMBE1000_IMS_VMMB E1000_ICR_VMMB e1000_defines.h Mail box activity
2449
 E1000_IMS_RXSEQE1000_IMS_RXSEQ E1000_ICR_RXSEQ e1000_defines.h rx sequence error
2450
 E1000_IMS_RXDMT0E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 e1000_defines.h rx desc min. threshold
2451
 E1000_IMS_RXOE1000_IMS_RXO E1000_ICR_RXO e1000_defines.h rx overrun
2452
 E1000_IMS_RXT0E1000_IMS_RXT0 E1000_ICR_RXT0 e1000_defines.h rx timer intr
2453
 E1000_IMS_MDACE1000_IMS_MDAC E1000_ICR_MDAC e1000_defines.h MDIO access complete
2454
 E1000_IMS_RXCFGE1000_IMS_RXCFG E1000_ICR_RXCFG e1000_defines.h Rx /c/ ordered set
2455
 E1000_IMS_GPI_EN0E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 e1000_defines.h GP Int 0
2456
 E1000_IMS_GPI_EN1E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 e1000_defines.h GP Int 1
2457
 E1000_IMS_GPI_EN2E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 e1000_defines.h GP Int 2
2458
 E1000_IMS_GPI_EN3E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 e1000_defines.h GP Int 3
2459
 E1000_IMS_TXD_LOWE1000_IMS_TXD_LOW E1000_ICR_TXD_LOW e1000_defines.h 　
2460
 E1000_IMS_SRPDE1000_IMS_SRPD E1000_ICR_SRPD e1000_defines.h 　
2461
 E1000_IMS_ACKE1000_IMS_ACK E1000_ICR_ACK e1000_defines.h Receive Ack frame
2462
 E1000_IMS_MNGE1000_IMS_MNG E1000_ICR_MNG e1000_defines.h Manageability event
2463
 E1000_IMS_DOCKE1000_IMS_DOCK E1000_ICR_DOCK e1000_defines.h Dock/Undock
2464
 E1000_IMS_RXD_FIFO_PAR0E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000_defines.h Q0 Rx desc FIFO
2465
 E1000_IMS_TXD_FIFO_PAR0E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000_defines.h Q0 Tx desc FIFO
2466
 E1000_IMS_HOST_ARB_PARE1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000_defines.h host arb read buffer
2467
 E1000_IMS_PB_PARE1000_IMS_PB_PAR E1000_ICR_PB_PAR e1000_defines.h packet buffer parity
2468
 E1000_IMS_RXD_FIFO_PAR1E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000_defines.h Q1 Rx desc FIFO
2469
 E1000_IMS_TXD_FIFO_PAR1E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000_defines.h Q1 Tx desc FIFO
2470
 E1000_IMS_DSWE1000_IMS_DSW E1000_ICR_DSW e1000_defines.h 　
2471
 E1000_IMS_PHYINTE1000_IMS_PHYINT E1000_ICR_PHYINT e1000_defines.h 　
2472
 E1000_IMS_DOUTSYNCE1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC e1000_defines.h NIC DMA out of sync
2473
 E1000_IMS_EPRSTE1000_IMS_EPRST E1000_ICR_EPRST e1000_defines.h 　
2474
 E1000_ICS_TXDWE1000_ICS_TXDW E1000_ICR_TXDW e1000_defines.h Tx desc written back
2475
 E1000_ICS_TXQEE1000_ICS_TXQE E1000_ICR_TXQE e1000_defines.h Transmit Queue empty
2476
 E1000_ICS_LSCE1000_ICS_LSC E1000_ICR_LSC e1000_defines.h Link Status Change
2477
 E1000_ICS_RXSEQE1000_ICS_RXSEQ E1000_ICR_RXSEQ e1000_defines.h rx sequence error
2478
 E1000_ICS_RXDMT0E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 e1000_defines.h rx desc min. threshold
2479
 E1000_ICS_RXOE1000_ICS_RXO E1000_ICR_RXO e1000_defines.h rx overrun
2480
 E1000_ICS_RXT0E1000_ICS_RXT0 E1000_ICR_RXT0 e1000_defines.h rx timer intr
2481
 E1000_ICS_MDACE1000_ICS_MDAC E1000_ICR_MDAC e1000_defines.h MDIO access complete
2482
 E1000_ICS_RXCFGE1000_ICS_RXCFG E1000_ICR_RXCFG e1000_defines.h Rx /c/ ordered set
2483
 E1000_ICS_GPI_EN0E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 e1000_defines.h GP Int 0
2484
 E1000_ICS_GPI_EN1E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 e1000_defines.h GP Int 1
2485
 E1000_ICS_GPI_EN2E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 e1000_defines.h GP Int 2
2486
 E1000_ICS_GPI_EN3E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 e1000_defines.h GP Int 3
2487
 E1000_ICS_TXD_LOWE1000_ICS_TXD_LOW E1000_ICR_TXD_LOW e1000_defines.h 　
2488
 E1000_ICS_SRPDE1000_ICS_SRPD E1000_ICR_SRPD e1000_defines.h 　
2489
 E1000_ICS_ACKE1000_ICS_ACK E1000_ICR_ACK e1000_defines.h Receive Ack frame
2490
 E1000_ICS_MNGE1000_ICS_MNG E1000_ICR_MNG e1000_defines.h Manageability event
2491
 E1000_ICS_DOCKE1000_ICS_DOCK E1000_ICR_DOCK e1000_defines.h Dock/Undock
2492
 E1000_ICS_RXD_FIFO_PAR0E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000_defines.h Q0 Rx desc FIFO
2493
 E1000_ICS_TXD_FIFO_PAR0E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000_defines.h Q0 Tx desc FIFO
2494
 E1000_ICS_HOST_ARB_PARE1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000_defines.h host arb read buffer
2495
 E1000_ICS_PB_PARE1000_ICS_PB_PAR E1000_ICR_PB_PAR e1000_defines.h packet buffer parity
2496
 E1000_ICS_RXD_FIFO_PAR1E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000_defines.h Q1 Rx desc FIFO
2497
 E1000_ICS_TXD_FIFO_PAR1E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000_defines.h Q1 Tx desc FIFO
2498
 E1000_ICS_DSWE1000_ICS_DSW E1000_ICR_DSW e1000_defines.h 　
2499
 E1000_ICS_DOUTSYNCE1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC e1000_defines.h NIC DMA out of sync
2500
 E1000_ICS_PHYINTE1000_ICS_PHYINT E1000_ICR_PHYINT e1000_defines.h 　
2501
 E1000_ICS_EPRSTE1000_ICS_EPRST E1000_ICR_EPRST e1000_defines.h 　
2502
 E1000_TXDCTL_PTHRESHE1000_TXDCTL_PTHRESH 0x0000003F e1000_defines.h TXDCTL Prefetch Threshold
2503
 E1000_TXDCTL_HTHRESHE1000_TXDCTL_HTHRESH 0x00003F00 e1000_defines.h TXDCTL Host Threshold
2504
 E1000_TXDCTL_WTHRESHE1000_TXDCTL_WTHRESH 0x003F0000 e1000_defines.h TXDCTL Writeback Threshold
2505
 E1000_TXDCTL_GRANE1000_TXDCTL_GRAN 0x01000000 e1000_defines.h TXDCTL Granularity
2506
 E1000_TXDCTL_LWTHRESHE1000_TXDCTL_LWTHRESH 0xFE000000 e1000_defines.h TXDCTL Low Threshold
2507
 E1000_TXDCTL_FULL_TX_DESC_WBE1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 e1000_defines.h GRAN=1, WTHRESH=1
2508
 E1000_TXDCTL_MAX_TX_DESC_PREFETE1000_TXDCTL_MAX_TX_DESC_PREFET 0x0100001F e1000_defines.h GRAN=1, PTHRESH=31
2509
 E1000_TXDCTL_COUNT_DESCE1000_TXDCTL_COUNT_DESC 0x00400000 e1000_defines.h 　
2510
 FLOW_CONTROL_ADDRESS_LOWFLOW_CONTROL_ADDRESS_LOW 0x00C28001 e1000_defines.h 　
2511
 FLOW_CONTROL_ADDRESS_HIGHFLOW_CONTROL_ADDRESS_HIGH 0x00000100 e1000_defines.h 　
2512
 FLOW_CONTROL_TYPEFLOW_CONTROL_TYPE 0x8808 e1000_defines.h 　
2513
 VLAN_TAG_SIZEVLAN_TAG_SIZE 4 e1000_defines.h 802.3ac tag (not DMA'd)
2514
 E1000_VLAN_FILTER_TBL_SIZEE1000_VLAN_FILTER_TBL_SIZE 128 e1000_defines.h VLAN Filter Table (4096 bits)
2515
 E1000_RAR_ENTRIESE1000_RAR_ENTRIES 15 e1000_defines.h 　
2516
 E1000_RAH_AVE1000_RAH_AV 0x80000000 e1000_defines.h Receive descriptor valid
2517
 E1000_RAL_MAC_ADDR_LENE1000_RAL_MAC_ADDR_LEN 4 e1000_defines.h 　
2518
 E1000_RAH_MAC_ADDR_LENE1000_RAH_MAC_ADDR_LEN 2 e1000_defines.h 　
2519
 E1000_RAH_POOL_MASKE1000_RAH_POOL_MASK 0x03FC0000 e1000_defines.h 　
2520
 E1000_RAH_POOL_1E1000_RAH_POOL_1 0x00040000 e1000_defines.h 　
2521
 E1000_SUCCESSE1000_SUCCESS 0 e1000_defines.h 　
2522
 E1000_ERR_NVME1000_ERR_NVM 1 e1000_defines.h 　
2523
 E1000_ERR_PHYE1000_ERR_PHY 2 e1000_defines.h 　
2524
 E1000_ERR_CONFIGE1000_ERR_CONFIG 3 e1000_defines.h 　
2525
 E1000_ERR_PARAME1000_ERR_PARAM 4 e1000_defines.h 　
2526
 E1000_ERR_MAC_INITE1000_ERR_MAC_INIT 5 e1000_defines.h 　
2527
 E1000_ERR_PHY_TYPEE1000_ERR_PHY_TYPE 6 e1000_defines.h 　
2528
 E1000_ERR_RESETE1000_ERR_RESET 9 e1000_defines.h 　
2529
 E1000_ERR_MASTER_REQUESTS_PENDIE1000_ERR_MASTER_REQUESTS_PENDI 10 e1000_defines.h 　
2530
 E1000_ERR_HOST_INTERFACE_COMMANE1000_ERR_HOST_INTERFACE_COMMAN 11 e1000_defines.h 　
2531
 E1000_BLK_PHY_RESETE1000_BLK_PHY_RESET 12 e1000_defines.h 　
2532
 E1000_ERR_SWFW_SYNCE1000_ERR_SWFW_SYNC 13 e1000_defines.h 　
2533
 E1000_NOT_IMPLEMENTEDE1000_NOT_IMPLEMENTED 14 e1000_defines.h 　
2534
 E1000_ERR_MBXE1000_ERR_MBX 15 e1000_defines.h 　
2535
 FIBER_LINK_UP_LIMITFIBER_LINK_UP_LIMIT 50 e1000_defines.h 　
2536
 COPPER_LINK_UP_LIMITCOPPER_LINK_UP_LIMIT 10 e1000_defines.h 　
2537
 PHY_AUTO_NEG_LIMITPHY_AUTO_NEG_LIMIT 45 e1000_defines.h 　
2538
 PHY_FORCE_LIMITPHY_FORCE_LIMIT 20 e1000_defines.h 　
2539
 MASTER_DISABLE_TIMEOUTMASTER_DISABLE_TIMEOUT 800 e1000_defines.h 　
2540
 PHY_CFG_TIMEOUTPHY_CFG_TIMEOUT 100 e1000_defines.h 　
2541
 MDIO_OWNERSHIP_TIMEOUTMDIO_OWNERSHIP_TIMEOUT 10 e1000_defines.h 　
2542
 AUTO_READ_DONE_TIMEOUTAUTO_READ_DONE_TIMEOUT 10 e1000_defines.h 　
2543
 E1000_FCRTH_RTHE1000_FCRTH_RTH 0x0000FFF8 e1000_defines.h Mask Bits[15:3] for RTH
2544
 E1000_FCRTH_XFCEE1000_FCRTH_XFCE 0x80000000 e1000_defines.h External Flow Control Enable
2545
 E1000_FCRTL_RTLE1000_FCRTL_RTL 0x0000FFF8 e1000_defines.h Mask Bits[15:3] for RTL
2546
 E1000_FCRTL_XONEE1000_FCRTL_XONE 0x80000000 e1000_defines.h Enable XON frame transmission
2547
 E1000_TXCW_FDE1000_TXCW_FD 0x00000020 e1000_defines.h TXCW full duplex
2548
 E1000_TXCW_HDE1000_TXCW_HD 0x00000040 e1000_defines.h TXCW half duplex
2549
 E1000_TXCW_PAUSEE1000_TXCW_PAUSE 0x00000080 e1000_defines.h TXCW sym pause request
2550
 E1000_TXCW_ASM_DIRE1000_TXCW_ASM_DIR 0x00000100 e1000_defines.h TXCW astm pause direction
2551
 E1000_TXCW_PAUSE_MASKE1000_TXCW_PAUSE_MASK 0x00000180 e1000_defines.h TXCW pause request mask
2552
 E1000_TXCW_RFE1000_TXCW_RF 0x00003000 e1000_defines.h TXCW remote fault
2553
 E1000_TXCW_NPE1000_TXCW_NP 0x00008000 e1000_defines.h TXCW next page
2554
 E1000_TXCW_CWE1000_TXCW_CW 0x0000ffff e1000_defines.h TxConfigWord mask
2555
 E1000_TXCW_TXCE1000_TXCW_TXC 0x40000000 e1000_defines.h Transmit Config control
2556
 E1000_TXCW_ANEE1000_TXCW_ANE 0x80000000 e1000_defines.h Auto-neg enable
2557
 E1000_RXCW_CWE1000_RXCW_CW 0x0000ffff e1000_defines.h RxConfigWord mask
2558
 E1000_RXCW_NCE1000_RXCW_NC 0x04000000 e1000_defines.h Receive config no carrier
2559
 E1000_RXCW_IVE1000_RXCW_IV 0x08000000 e1000_defines.h Receive config invalid
2560
 E1000_RXCW_CCE1000_RXCW_CC 0x10000000 e1000_defines.h Receive config change
2561
 E1000_RXCW_CE1000_RXCW_C 0x20000000 e1000_defines.h Receive config
2562
 E1000_RXCW_SYNCHE1000_RXCW_SYNCH 0x40000000 e1000_defines.h Receive config synch
2563
 E1000_RXCW_ANCE1000_RXCW_ANC 0x80000000 e1000_defines.h Auto-neg complete
2564
 E1000_GCR_RXD_NO_SNOOPE1000_GCR_RXD_NO_SNOOP 0x00000001 e1000_defines.h 　
2565
 E1000_GCR_RXDSCW_NO_SNOOPE1000_GCR_RXDSCW_NO_SNOOP 0x00000002 e1000_defines.h 　
2566
 E1000_GCR_RXDSCR_NO_SNOOPE1000_GCR_RXDSCR_NO_SNOOP 0x00000004 e1000_defines.h 　
2567
 E1000_GCR_TXD_NO_SNOOPE1000_GCR_TXD_NO_SNOOP 0x00000008 e1000_defines.h 　
2568
 E1000_GCR_TXDSCW_NO_SNOOPE1000_GCR_TXDSCW_NO_SNOOP 0x00000010 e1000_defines.h 　
2569
 E1000_GCR_TXDSCR_NO_SNOOPE1000_GCR_TXDSCR_NO_SNOOP 0x00000020 e1000_defines.h 　
2570
 E1000_GCR_CMPL_TMOUT_MASKE1000_GCR_CMPL_TMOUT_MASK 0x0000F000 e1000_defines.h 　
2571
 E1000_GCR_CMPL_TMOUT_10msE1000_GCR_CMPL_TMOUT_10ms 0x00001000 e1000_defines.h 　
2572
 E1000_GCR_CMPL_TMOUT_RESENDE1000_GCR_CMPL_TMOUT_RESEND 0x00010000 e1000_defines.h 　
2573
 E1000_GCR_CAP_VER2E1000_GCR_CAP_VER2 0x00040000 e1000_defines.h 　
2574
 PCIE_NO_SNOOP_ALLPCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ E1000_GCR_RXDSCW_NO_SNOOP | \ E1000_GCR_RXDSCR_NO_SNOOP | \ E1000_GCR_TXD_NO_SNOO e1000_defines.h 　
2575
 MII_CR_SPEED_SELECT_MSBMII_CR_SPEED_SELECT_MSB 0x0040 e1000_defines.h bits 6,13: 10=1000, 01=100, 00=10
2576
 MII_CR_COLL_TEST_ENABLEMII_CR_COLL_TEST_ENABLE 0x0080 e1000_defines.h Collision test enable
2577
 MII_CR_FULL_DUPLEXMII_CR_FULL_DUPLEX 0x0100 e1000_defines.h FDX =1, half duplex =0
2578
 MII_CR_RESTART_AUTO_NEGMII_CR_RESTART_AUTO_NEG 0x0200 e1000_defines.h Restart auto negotiation
2579
 MII_CR_ISOLATEMII_CR_ISOLATE 0x0400 e1000_defines.h Isolate PHY from MII
2580
 MII_CR_POWER_DOWNMII_CR_POWER_DOWN 0x0800 e1000_defines.h Power down
2581
 MII_CR_AUTO_NEG_ENMII_CR_AUTO_NEG_EN 0x1000 e1000_defines.h Auto Neg Enable
2582
 MII_CR_SPEED_SELECT_LSBMII_CR_SPEED_SELECT_LSB 0x2000 e1000_defines.h bits 6,13: 10=1000, 01=100, 00=10
2583
 MII_CR_LOOPBACKMII_CR_LOOPBACK 0x4000 e1000_defines.h 0 = normal, 1 = loopback
2584
 MII_CR_RESETMII_CR_RESET 0x8000 e1000_defines.h 0 = normal, 1 = PHY reset
2585
 MII_CR_SPEED_1000MII_CR_SPEED_1000 0x0040 e1000_defines.h 　
2586
 MII_CR_SPEED_100MII_CR_SPEED_100 0x2000 e1000_defines.h 　
2587
 MII_CR_SPEED_10MII_CR_SPEED_10 0x0000 e1000_defines.h 　
2588
 MII_SR_EXTENDED_CAPSMII_SR_EXTENDED_CAPS 0x0001 e1000_defines.h Extended register capabilities
2589
 MII_SR_JABBER_DETECTMII_SR_JABBER_DETECT 0x0002 e1000_defines.h Jabber Detected
2590
 MII_SR_LINK_STATUSMII_SR_LINK_STATUS 0x0004 e1000_defines.h Link Status 1 = link
2591
 MII_SR_AUTONEG_CAPSMII_SR_AUTONEG_CAPS 0x0008 e1000_defines.h Auto Neg Capable
2592
 MII_SR_REMOTE_FAULTMII_SR_REMOTE_FAULT 0x0010 e1000_defines.h Remote Fault Detect
2593
 MII_SR_AUTONEG_COMPLETEMII_SR_AUTONEG_COMPLETE 0x0020 e1000_defines.h Auto Neg Complete
2594
 MII_SR_PREAMBLE_SUPPRESSMII_SR_PREAMBLE_SUPPRESS 0x0040 e1000_defines.h Preamble may be suppressed
2595
 MII_SR_EXTENDED_STATUSMII_SR_EXTENDED_STATUS 0x0100 e1000_defines.h Ext. status info in Reg 0x0F
2596
 MII_SR_100T2_HD_CAPSMII_SR_100T2_HD_CAPS 0x0200 e1000_defines.h 100T2 Half Duplex Capable
2597
 MII_SR_100T2_FD_CAPSMII_SR_100T2_FD_CAPS 0x0400 e1000_defines.h 100T2 Full Duplex Capable
2598
 MII_SR_10T_HD_CAPSMII_SR_10T_HD_CAPS 0x0800 e1000_defines.h 10T Half Duplex Capable
2599
 MII_SR_10T_FD_CAPSMII_SR_10T_FD_CAPS 0x1000 e1000_defines.h 10T Full Duplex Capable
2600
 MII_SR_100X_HD_CAPSMII_SR_100X_HD_CAPS 0x2000 e1000_defines.h 100X Half Duplex Capable
2601
 MII_SR_100X_FD_CAPSMII_SR_100X_FD_CAPS 0x4000 e1000_defines.h 100X Full Duplex Capable
2602
 MII_SR_100T4_CAPSMII_SR_100T4_CAPS 0x8000 e1000_defines.h 100T4 Capable
2603
 NWAY_AR_SELECTOR_FIELDNWAY_AR_SELECTOR_FIELD 0x0001 e1000_defines.h indicates IEEE 802.3 CSMA/CD
2604
 NWAY_AR_10T_HD_CAPSNWAY_AR_10T_HD_CAPS 0x0020 e1000_defines.h 10T Half Duplex Capable
2605
 NWAY_AR_10T_FD_CAPSNWAY_AR_10T_FD_CAPS 0x0040 e1000_defines.h 10T Full Duplex Capable
2606
 NWAY_AR_100TX_HD_CAPSNWAY_AR_100TX_HD_CAPS 0x0080 e1000_defines.h 100TX Half Duplex Capable
2607
 NWAY_AR_100TX_FD_CAPSNWAY_AR_100TX_FD_CAPS 0x0100 e1000_defines.h 100TX Full Duplex Capable
2608
 NWAY_AR_100T4_CAPSNWAY_AR_100T4_CAPS 0x0200 e1000_defines.h 100T4 Capable
2609
 NWAY_AR_PAUSENWAY_AR_PAUSE 0x0400 e1000_defines.h Pause operation desired
2610
 NWAY_AR_ASM_DIRNWAY_AR_ASM_DIR 0x0800 e1000_defines.h Asymmetric Pause Direction bit
2611
 NWAY_AR_REMOTE_FAULTNWAY_AR_REMOTE_FAULT 0x2000 e1000_defines.h Remote Fault detected
2612
 NWAY_AR_NEXT_PAGENWAY_AR_NEXT_PAGE 0x8000 e1000_defines.h Next Page ability supported
2613
 NWAY_LPAR_SELECTOR_FIELDNWAY_LPAR_SELECTOR_FIELD 0x0000 e1000_defines.h LP protocol selector field
2614
 NWAY_LPAR_10T_HD_CAPSNWAY_LPAR_10T_HD_CAPS 0x0020 e1000_defines.h LP is 10T Half Duplex Capable
2615
 NWAY_LPAR_10T_FD_CAPSNWAY_LPAR_10T_FD_CAPS 0x0040 e1000_defines.h LP is 10T Full Duplex Capable
2616
 NWAY_LPAR_100TX_HD_CAPSNWAY_LPAR_100TX_HD_CAPS 0x0080 e1000_defines.h LP is 100TX Half Duplex Capable
2617
 NWAY_LPAR_100TX_FD_CAPSNWAY_LPAR_100TX_FD_CAPS 0x0100 e1000_defines.h LP is 100TX Full Duplex Capable
2618
 NWAY_LPAR_100T4_CAPSNWAY_LPAR_100T4_CAPS 0x0200 e1000_defines.h LP is 100T4 Capable
2619
 NWAY_LPAR_PAUSENWAY_LPAR_PAUSE 0x0400 e1000_defines.h LP Pause operation desired
2620
 NWAY_LPAR_ASM_DIRNWAY_LPAR_ASM_DIR 0x0800 e1000_defines.h LP Asymmetric Pause Direction bit
2621
 NWAY_LPAR_REMOTE_FAULTNWAY_LPAR_REMOTE_FAULT 0x2000 e1000_defines.h LP has detected Remote Fault
2622
 NWAY_LPAR_ACKNOWLEDGENWAY_LPAR_ACKNOWLEDGE 0x4000 e1000_defines.h LP has rx'd link code word
2623
 NWAY_LPAR_NEXT_PAGENWAY_LPAR_NEXT_PAGE 0x8000 e1000_defines.h Next Page ability supported
2624
 NWAY_ER_LP_NWAY_CAPSNWAY_ER_LP_NWAY_CAPS 0x0001 e1000_defines.h LP has Auto Neg Capability
2625
 NWAY_ER_PAGE_RXDNWAY_ER_PAGE_RXD 0x0002 e1000_defines.h LP is 10T Half Duplex Capable
2626
 NWAY_ER_NEXT_PAGE_CAPSNWAY_ER_NEXT_PAGE_CAPS 0x0004 e1000_defines.h LP is 10T Full Duplex Capable
2627
 NWAY_ER_LP_NEXT_PAGE_CAPSNWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 e1000_defines.h LP is 100TX Half Duplex Capable
2628
 NWAY_ER_PAR_DETECT_FAULTNWAY_ER_PAR_DETECT_FAULT 0x0010 e1000_defines.h LP is 100TX Full Duplex Capable
2629
 CR_1000T_ASYM_PAUSECR_1000T_ASYM_PAUSE 0x0080 e1000_defines.h Advertise asymmetric pause bit
2630
 CR_1000T_HD_CAPSCR_1000T_HD_CAPS 0x0100 e1000_defines.h Advertise 1000T HD capability
2631
 CR_1000T_FD_CAPSCR_1000T_FD_CAPS 0x0200 e1000_defines.h Advertise 1000T FD capability
2632
 CR_1000T_REPEATER_DTECR_1000T_REPEATER_DTE 0x0400 e1000_defines.h 1=Repeater/switch device port
2633
 CR_1000T_MS_VALUECR_1000T_MS_VALUE 0x0800 e1000_defines.h 1=Configure PHY as Master
2634
 CR_1000T_MS_ENABLECR_1000T_MS_ENABLE 0x1000 e1000_defines.h 1=Master/Slave manual config value
2635
 CR_1000T_TEST_MODE_NORMALCR_1000T_TEST_MODE_NORMAL 0x0000 e1000_defines.h Normal Operation
2636
 CR_1000T_TEST_MODE_1CR_1000T_TEST_MODE_1 0x2000 e1000_defines.h Transmit Waveform test
2637
 CR_1000T_TEST_MODE_2CR_1000T_TEST_MODE_2 0x4000 e1000_defines.h Master Transmit Jitter test
2638
 CR_1000T_TEST_MODE_3CR_1000T_TEST_MODE_3 0x6000 e1000_defines.h Slave Transmit Jitter test
2639
 CR_1000T_TEST_MODE_4CR_1000T_TEST_MODE_4 0x8000 e1000_defines.h Transmitter Distortion test
2640
 SR_1000T_IDLE_ERROR_CNTSR_1000T_IDLE_ERROR_CNT 0x00FF e1000_defines.h Num idle errors since last read
2641
 SR_1000T_ASYM_PAUSE_DIRSR_1000T_ASYM_PAUSE_DIR 0x0100 e1000_defines.h LP asymmetric pause direction bit
2642
 SR_1000T_LP_HD_CAPSSR_1000T_LP_HD_CAPS 0x0400 e1000_defines.h LP is 1000T HD capable
2643
 SR_1000T_LP_FD_CAPSSR_1000T_LP_FD_CAPS 0x0800 e1000_defines.h LP is 1000T FD capable
2644
 SR_1000T_REMOTE_RX_STATUSSR_1000T_REMOTE_RX_STATUS 0x1000 e1000_defines.h Remote receiver OK
2645
 SR_1000T_LOCAL_RX_STATUSSR_1000T_LOCAL_RX_STATUS 0x2000 e1000_defines.h Local receiver OK
2646
 SR_1000T_MS_CONFIG_RESSR_1000T_MS_CONFIG_RES 0x4000 e1000_defines.h 1=Local Tx is Master, 0=Slave
2647
 SR_1000T_MS_CONFIG_FAULTSR_1000T_MS_CONFIG_FAULT 0x8000 e1000_defines.h Master/Slave config fault
2648
 SR_1000T_PHY_EXCESSIVE_IDLE_ERRSR_1000T_PHY_EXCESSIVE_IDLE_ERR 5 e1000_defines.h 　
2649
 PHY_CONTROLPHY_CONTROL 0x00 e1000_defines.h Control Register
2650
 PHY_STATUSPHY_STATUS 0x01 e1000_defines.h Status Register
2651
 PHY_ID1PHY_ID1 0x02 e1000_defines.h Phy Id Reg (word 1)
2652
 PHY_ID2PHY_ID2 0x03 e1000_defines.h Phy Id Reg (word 2)
2653
 PHY_AUTONEG_ADVPHY_AUTONEG_ADV 0x04 e1000_defines.h Autoneg Advertisement
2654
 PHY_LP_ABILITYPHY_LP_ABILITY 0x05 e1000_defines.h Link Partner Ability (Base Page)
2655
 PHY_AUTONEG_EXPPHY_AUTONEG_EXP 0x06 e1000_defines.h Autoneg Expansion Reg
2656
 PHY_NEXT_PAGE_TXPHY_NEXT_PAGE_TX 0x07 e1000_defines.h Next Page Tx
2657
 PHY_LP_NEXT_PAGEPHY_LP_NEXT_PAGE 0x08 e1000_defines.h Link Partner Next Page
2658
 PHY_1000T_CTRLPHY_1000T_CTRL 0x09 e1000_defines.h 1000Base-T Control Reg
2659
 PHY_1000T_STATUSPHY_1000T_STATUS 0x0A e1000_defines.h 1000Base-T Status Reg
2660
 PHY_EXT_STATUSPHY_EXT_STATUS 0x0F e1000_defines.h Extended Status Reg
2661
 PHY_CONTROL_LBPHY_CONTROL_LB 0x4000 e1000_defines.h PHY Loopback bit
2662
 E1000_EECD_SKE1000_EECD_SK 0x00000001 e1000_defines.h NVM Clock
2663
 E1000_EECD_CSE1000_EECD_CS 0x00000002 e1000_defines.h NVM Chip Select
2664
 E1000_EECD_DIE1000_EECD_DI 0x00000004 e1000_defines.h NVM Data In
2665
 E1000_EECD_DOE1000_EECD_DO 0x00000008 e1000_defines.h NVM Data Out
2666
 E1000_EECD_FWE_MASKE1000_EECD_FWE_MASK 0x00000030 e1000_defines.h 　
2667
 E1000_EECD_FWE_DISE1000_EECD_FWE_DIS 0x00000010 e1000_defines.h Disable FLASH writes
2668
 E1000_EECD_FWE_ENE1000_EECD_FWE_EN 0x00000020 e1000_defines.h Enable FLASH writes
2669
 E1000_EECD_FWE_SHIFTE1000_EECD_FWE_SHIFT 4 e1000_defines.h 　
2670
 E1000_EECD_REQE1000_EECD_REQ 0x00000040 e1000_defines.h NVM Access Request
2671
 E1000_EECD_GNTE1000_EECD_GNT 0x00000080 e1000_defines.h NVM Access Grant
2672
 E1000_EECD_PRESE1000_EECD_PRES 0x00000100 e1000_defines.h NVM Present
2673
 E1000_EECD_SIZEE1000_EECD_SIZE 0x00000200 e1000_defines.h NVM Size (0=64 word 1=256 word)
2674
 E1000_EECD_ADDR_BITSE1000_EECD_ADDR_BITS 0x00000400 e1000_defines.h 　
2675
 E1000_EECD_TYPEE1000_EECD_TYPE 0x00002000 e1000_defines.h NVM Type (1-SPI, 0-Microwire)
2676
 E1000_NVM_GRANT_ATTEMPTSE1000_NVM_GRANT_ATTEMPTS 1000 e1000_defines.h NVM # attempts to gain grant
2677
 E1000_EECD_AUTO_RDE1000_EECD_AUTO_RD 0x00000200 e1000_defines.h NVM Auto Read done
2678
 E1000_EECD_SIZE_EX_MASKE1000_EECD_SIZE_EX_MASK 0x00007800 e1000_defines.h NVM Size
2679
 E1000_EECD_SIZE_EX_SHIFTE1000_EECD_SIZE_EX_SHIFT 11 e1000_defines.h 　
2680
 E1000_EECD_NVADDSE1000_EECD_NVADDS 0x00018000 e1000_defines.h NVM Address Size
2681
 E1000_EECD_SELSHADE1000_EECD_SELSHAD 0x00020000 e1000_defines.h Select Shadow RAM
2682
 E1000_EECD_INITSRAME1000_EECD_INITSRAM 0x00040000 e1000_defines.h Initialize Shadow RAM
2683
 E1000_EECD_FLUPDE1000_EECD_FLUPD 0x00080000 e1000_defines.h Update FLASH
2684
 E1000_EECD_AUPDENE1000_EECD_AUPDEN 0x00100000 e1000_defines.h Enable Autonomous FLASH update
2685
 E1000_EECD_SHADVE1000_EECD_SHADV 0x00200000 e1000_defines.h Shadow RAM Data Valid
2686
 E1000_EECD_SEC1VALE1000_EECD_SEC1VAL 0x00400000 e1000_defines.h Sector One Valid
2687
 E1000_EECD_SECVAL_SHIFTE1000_EECD_SECVAL_SHIFT 22 e1000_defines.h 　
2688
 E1000_EECD_SEC1VAL_VALID_MASKE1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) e1000_defines.h 　
2689
 E1000_NVM_SWDPIN0E1000_NVM_SWDPIN0 0x0001 e1000_defines.h SWDPIN 0 NVM Value
2690
 E1000_NVM_LED_LOGICE1000_NVM_LED_LOGIC 0x0020 e1000_defines.h Led Logic Word
2691
 E1000_NVM_RW_REG_DATAE1000_NVM_RW_REG_DATA 16 e1000_defines.h Offset to data in NVM read/write regs
2692
 E1000_NVM_RW_REG_DONEE1000_NVM_RW_REG_DONE 2 e1000_defines.h Offset to READ/WRITE done bit
2693
 E1000_NVM_RW_REG_STARTE1000_NVM_RW_REG_START 1 e1000_defines.h Start operation
2694
 E1000_NVM_RW_ADDR_SHIFTE1000_NVM_RW_ADDR_SHIFT 2 e1000_defines.h Shift to the address bits
2695
 E1000_NVM_POLL_WRITEE1000_NVM_POLL_WRITE 1 e1000_defines.h Flag for polling for write complete
2696
 E1000_NVM_POLL_READE1000_NVM_POLL_READ 0 e1000_defines.h Flag for polling for read complete
2697
 E1000_FLASH_UPDATESE1000_FLASH_UPDATES 2000 e1000_defines.h 　
2698
 NVM_COMPATNVM_COMPAT 0x0003 e1000_defines.h 　
2699
 NVM_ID_LED_SETTINGSNVM_ID_LED_SETTINGS 0x0004 e1000_defines.h 　
2700
 NVM_VERSIONNVM_VERSION 0x0005 e1000_defines.h 　
2701
 NVM_SERDES_AMPLITUDENVM_SERDES_AMPLITUDE 0x0006 e1000_defines.h SERDES output amplitude
2702
 NVM_PHY_CLASS_WORDNVM_PHY_CLASS_WORD 0x0007 e1000_defines.h 　
2703
 NVM_INIT_CONTROL1_REGNVM_INIT_CONTROL1_REG 0x000A e1000_defines.h 　
2704
 NVM_INIT_CONTROL2_REGNVM_INIT_CONTROL2_REG 0x000F e1000_defines.h 　
2705
 NVM_SWDEF_PINS_CTRL_PORT_1NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 e1000_defines.h 　
2706
 NVM_INIT_CONTROL3_PORT_BNVM_INIT_CONTROL3_PORT_B 0x0014 e1000_defines.h 　
2707
 NVM_INIT_3GIO_3NVM_INIT_3GIO_3 0x001A e1000_defines.h 　
2708
 NVM_SWDEF_PINS_CTRL_PORT_0NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 e1000_defines.h 　
2709
 NVM_INIT_CONTROL3_PORT_ANVM_INIT_CONTROL3_PORT_A 0x0024 e1000_defines.h 　
2710
 NVM_CFGNVM_CFG 0x0012 e1000_defines.h 　
2711
 NVM_FLASH_VERSIONNVM_FLASH_VERSION 0x0032 e1000_defines.h 　
2712
 NVM_ALT_MAC_ADDR_PTRNVM_ALT_MAC_ADDR_PTR 0x0037 e1000_defines.h 　
2713
 NVM_CHECKSUM_REGNVM_CHECKSUM_REG 0x003F e1000_defines.h 　
2714
 E1000_NVM_CFG_DONE_PORT_0E1000_NVM_CFG_DONE_PORT_0 0x040000 e1000_defines.h MNG config cycle done
2715
 E1000_NVM_CFG_DONE_PORT_1E1000_NVM_CFG_DONE_PORT_1 0x080000 e1000_defines.h ...for second port
2716
 NVM_WORD0F_PAUSE_MASKNVM_WORD0F_PAUSE_MASK 0x3000 e1000_defines.h 　
2717
 NVM_WORD0F_PAUSENVM_WORD0F_PAUSE 0x1000 e1000_defines.h 　
2718
 NVM_WORD0F_ASM_DIRNVM_WORD0F_ASM_DIR 0x2000 e1000_defines.h 　
2719
 NVM_WORD0F_ANENVM_WORD0F_ANE 0x0800 e1000_defines.h 　
2720
 NVM_WORD0F_SWPDIO_EXT_MASKNVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 e1000_defines.h 　
2721
 NVM_WORD0F_LPLUNVM_WORD0F_LPLU 0x0001 e1000_defines.h 　
2722
 NVM_WORD1A_ASPM_MASKNVM_WORD1A_ASPM_MASK 0x000C e1000_defines.h 　
2723
 NVM_SUMNVM_SUM 0xBABA e1000_defines.h 　
2724
 NVM_MAC_ADDR_OFFSETNVM_MAC_ADDR_OFFSET 0 e1000_defines.h 　
2725
 NVM_PBA_OFFSET_0NVM_PBA_OFFSET_0 8 e1000_defines.h 　
2726
 NVM_PBA_OFFSET_1NVM_PBA_OFFSET_1 9 e1000_defines.h 　
2727
 NVM_RESERVED_WORDNVM_RESERVED_WORD 0xFFFF e1000_defines.h 　
2728
 NVM_PHY_CLASS_ANVM_PHY_CLASS_A 0x8000 e1000_defines.h 　
2729
 NVM_SERDES_AMPLITUDE_MASKNVM_SERDES_AMPLITUDE_MASK 0x000F e1000_defines.h 　
2730
 NVM_SIZE_MASKNVM_SIZE_MASK 0x1C00 e1000_defines.h 　
2731
 NVM_SIZE_SHIFTNVM_SIZE_SHIFT 10 e1000_defines.h 　
2732
 NVM_WORD_SIZE_BASE_SHIFTNVM_WORD_SIZE_BASE_SHIFT 6 e1000_defines.h 　
2733
 NVM_SWDPIO_EXT_SHIFTNVM_SWDPIO_EXT_SHIFT 4 e1000_defines.h 　
2734
 NVM_READ_OPCODE_MICROWIRENVM_READ_OPCODE_MICROWIRE 0x6 e1000_defines.h NVM read opcode
2735
 NVM_WRITE_OPCODE_MICROWIRENVM_WRITE_OPCODE_MICROWIRE 0x5 e1000_defines.h NVM write opcode
2736
 NVM_ERASE_OPCODE_MICROWIRENVM_ERASE_OPCODE_MICROWIRE 0x7 e1000_defines.h NVM erase opcode
2737
 NVM_EWEN_OPCODE_MICROWIRENVM_EWEN_OPCODE_MICROWIRE 0x13 e1000_defines.h NVM erase/write enable
2738
 NVM_EWDS_OPCODE_MICROWIRENVM_EWDS_OPCODE_MICROWIRE 0x10 e1000_defines.h NVM erase/write disable
2739
 NVM_MAX_RETRY_SPINVM_MAX_RETRY_SPI 5000 e1000_defines.h Max wait of 5ms, for RDY signal
2740
 NVM_READ_OPCODE_SPINVM_READ_OPCODE_SPI 0x03 e1000_defines.h NVM read opcode
2741
 NVM_WRITE_OPCODE_SPINVM_WRITE_OPCODE_SPI 0x02 e1000_defines.h NVM write opcode
2742
 NVM_A8_OPCODE_SPINVM_A8_OPCODE_SPI 0x08 e1000_defines.h opcode bit-3 = address bit-8
2743
 NVM_WREN_OPCODE_SPINVM_WREN_OPCODE_SPI 0x06 e1000_defines.h NVM set Write Enable latch
2744
 NVM_WRDI_OPCODE_SPINVM_WRDI_OPCODE_SPI 0x04 e1000_defines.h NVM reset Write Enable latch
2745
 NVM_RDSR_OPCODE_SPINVM_RDSR_OPCODE_SPI 0x05 e1000_defines.h NVM read Status register
2746
 NVM_WRSR_OPCODE_SPINVM_WRSR_OPCODE_SPI 0x01 e1000_defines.h NVM write Status register
2747
 NVM_STATUS_RDY_SPINVM_STATUS_RDY_SPI 0x01 e1000_defines.h 　
2748
 NVM_STATUS_WEN_SPINVM_STATUS_WEN_SPI 0x02 e1000_defines.h 　
2749
 NVM_STATUS_BP0_SPINVM_STATUS_BP0_SPI 0x04 e1000_defines.h 　
2750
 NVM_STATUS_BP1_SPINVM_STATUS_BP1_SPI 0x08 e1000_defines.h 　
2751
 NVM_STATUS_WPEN_SPINVM_STATUS_WPEN_SPI 0x80 e1000_defines.h 　
2752
 ID_LED_RESERVED_0000ID_LED_RESERVED_0000 0x0000 e1000_defines.h 　
2753
 ID_LED_RESERVED_FFFFID_LED_RESERVED_FFFF 0xFFFF e1000_defines.h 　
2754
 ID_LED_DEFAULTID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) e1000_defines.h 　
2755
 ID_LED_DEF1_DEF2ID_LED_DEF1_DEF2 0x1 e1000_defines.h 　
2756
 ID_LED_DEF1_ON2ID_LED_DEF1_ON2 0x2 e1000_defines.h 　
2757
 ID_LED_DEF1_OFF2ID_LED_DEF1_OFF2 0x3 e1000_defines.h 　
2758
 ID_LED_ON1_DEF2ID_LED_ON1_DEF2 0x4 e1000_defines.h 　
2759
 ID_LED_ON1_ON2ID_LED_ON1_ON2 0x5 e1000_defines.h 　
2760
 ID_LED_ON1_OFF2ID_LED_ON1_OFF2 0x6 e1000_defines.h 　
2761
 ID_LED_OFF1_DEF2ID_LED_OFF1_DEF2 0x7 e1000_defines.h 　
2762
 ID_LED_OFF1_ON2ID_LED_OFF1_ON2 0x8 e1000_defines.h 　
2763
 ID_LED_OFF1_OFF2ID_LED_OFF1_OFF2 0x9 e1000_defines.h 　
2764
 IGP_ACTIVITY_LED_MASKIGP_ACTIVITY_LED_MASK 0xFFFFF0FF e1000_defines.h 　
2765
 IGP_ACTIVITY_LED_ENABLEIGP_ACTIVITY_LED_ENABLE 0x0300 e1000_defines.h 　
2766
 IGP_LED3_MODEIGP_LED3_MODE 0x07000000 e1000_defines.h 　
2767
 PCIX_COMMAND_REGISTERPCIX_COMMAND_REGISTER 0xE6 e1000_defines.h 　
2768
 PCIX_STATUS_REGISTER_LOPCIX_STATUS_REGISTER_LO 0xE8 e1000_defines.h 　
2769
 PCIX_STATUS_REGISTER_HIPCIX_STATUS_REGISTER_HI 0xEA e1000_defines.h 　
2770
 PCI_HEADER_TYPE_REGISTERPCI_HEADER_TYPE_REGISTER 0x0E e1000_defines.h 　
2771
 PCIE_LINK_STATUSPCIE_LINK_STATUS 0x12 e1000_defines.h 　
2772
 PCIE_DEVICE_CONTROL2PCIE_DEVICE_CONTROL2 0x28 e1000_defines.h 　
2773
 PCIX_COMMAND_MMRBC_MASKPCIX_COMMAND_MMRBC_MASK 0x000C e1000_defines.h 　
2774
 PCIX_COMMAND_MMRBC_SHIFTPCIX_COMMAND_MMRBC_SHIFT 0x2 e1000_defines.h 　
2775
 PCIX_STATUS_HI_MMRBC_MASKPCIX_STATUS_HI_MMRBC_MASK 0x0060 e1000_defines.h 　
2776
 PCIX_STATUS_HI_MMRBC_SHIFTPCIX_STATUS_HI_MMRBC_SHIFT 0x5 e1000_defines.h 　
2777
 PCIX_STATUS_HI_MMRBC_4KPCIX_STATUS_HI_MMRBC_4K 0x3 e1000_defines.h 　
2778
 PCIX_STATUS_HI_MMRBC_2KPCIX_STATUS_HI_MMRBC_2K 0x2 e1000_defines.h 　
2779
 PCIX_STATUS_LO_FUNC_MASKPCIX_STATUS_LO_FUNC_MASK 0x7 e1000_defines.h 　
2780
 PCI_HEADER_TYPE_MULTIFUNCPCI_HEADER_TYPE_MULTIFUNC 0x80 e1000_defines.h 　
2781
 PCIE_LINK_WIDTH_MASKPCIE_LINK_WIDTH_MASK 0x3F0 e1000_defines.h 　
2782
 PCIE_LINK_WIDTH_SHIFTPCIE_LINK_WIDTH_SHIFT 4 e1000_defines.h 　
2783
 PCIE_DEVICE_CONTROL2_16msPCIE_DEVICE_CONTROL2_16ms 0x0005 e1000_defines.h 　
2784
 ETH_ADDR_LENETH_ADDR_LEN 6 e1000_defines.h 　
2785
 PHY_REVISION_MASKPHY_REVISION_MASK 0xFFFFFFF0 e1000_defines.h 　
2786
 MAX_PHY_REG_ADDRESSMAX_PHY_REG_ADDRESS 0x1F e1000_defines.h 5 bit address bus (0-0x1F)
2787
 MAX_PHY_MULTI_PAGE_REGMAX_PHY_MULTI_PAGE_REG 0xF e1000_defines.h 　
2788
 M88E1000_E_PHY_IDM88E1000_E_PHY_ID 0x01410C50 e1000_defines.h 　
2789
 M88E1000_I_PHY_IDM88E1000_I_PHY_ID 0x01410C30 e1000_defines.h 　
2790
 M88E1011_I_PHY_IDM88E1011_I_PHY_ID 0x01410C20 e1000_defines.h 　
2791
 IGP01E1000_I_PHY_IDIGP01E1000_I_PHY_ID 0x02A80380 e1000_defines.h 　
2792
 M88E1011_I_REV_4M88E1011_I_REV_4 0x04 e1000_defines.h 　
2793
 M88E1111_I_PHY_IDM88E1111_I_PHY_ID 0x01410CC0 e1000_defines.h 　
2794
 GG82563_E_PHY_IDGG82563_E_PHY_ID 0x01410CA0 e1000_defines.h 　
2795
 IGP03E1000_E_PHY_IDIGP03E1000_E_PHY_ID 0x02A80390 e1000_defines.h 　
2796
 IFE_E_PHY_IDIFE_E_PHY_ID 0x02A80330 e1000_defines.h 　
2797
 IFE_PLUS_E_PHY_IDIFE_PLUS_E_PHY_ID 0x02A80320 e1000_defines.h 　
2798
 IFE_C_E_PHY_IDIFE_C_E_PHY_ID 0x02A80310 e1000_defines.h 　
2799
 M88_VENDORM88_VENDOR 0x0141 e1000_defines.h 　
2800
 M88E1000_PHY_SPEC_CTRLM88E1000_PHY_SPEC_CTRL 0x10 e1000_defines.h PHY Specific Control Register
2801
 M88E1000_PHY_SPEC_STATUSM88E1000_PHY_SPEC_STATUS 0x11 e1000_defines.h PHY Specific Status Register
2802
 M88E1000_INT_ENABLEM88E1000_INT_ENABLE 0x12 e1000_defines.h Interrupt Enable Register
2803
 M88E1000_INT_STATUSM88E1000_INT_STATUS 0x13 e1000_defines.h Interrupt Status Register
2804
 M88E1000_EXT_PHY_SPEC_CTRLM88E1000_EXT_PHY_SPEC_CTRL 0x14 e1000_defines.h Extended PHY Specific Control
2805
 M88E1000_RX_ERR_CNTRM88E1000_RX_ERR_CNTR 0x15 e1000_defines.h Receive Error Counter
2806
 M88E1000_PHY_EXT_CTRLM88E1000_PHY_EXT_CTRL 0x1A e1000_defines.h PHY extend control register
2807
 M88E1000_PHY_PAGE_SELECTM88E1000_PHY_PAGE_SELECT 0x1D e1000_defines.h Reg 29 for page number setting
2808
 M88E1000_PHY_GEN_CONTROLM88E1000_PHY_GEN_CONTROL 0x1E e1000_defines.h Its meaning depends on reg 29
2809
 M88E1000_PHY_VCO_REG_BIT8M88E1000_PHY_VCO_REG_BIT8 0x100 e1000_defines.h Bits 8 & 11 are adjusted for
2810
 M88E1000_PHY_VCO_REG_BIT11M88E1000_PHY_VCO_REG_BIT11 0x800 e1000_defines.h improved BER performance
2811
 M88E1000_PSCR_JABBER_DISABLEM88E1000_PSCR_JABBER_DISABLE 0x0001 e1000_defines.h 1=Jabber Function disabled
2812
 M88E1000_PSCR_POLARITY_REVERSALM88E1000_PSCR_POLARITY_REVERSAL 0x0002 e1000_defines.h 1=Polarity Reverse enabled
2813
 M88E1000_PSCR_SQE_TESTM88E1000_PSCR_SQE_TEST 0x0004 e1000_defines.h 1=SQE Test enabled
2814
 M88E1000_PSCR_CLK125_DISABLEM88E1000_PSCR_CLK125_DISABLE 0x0010 e1000_defines.h 　
2815
 M88E1000_PSCR_MDI_MANUAL_MODEM88E1000_PSCR_MDI_MANUAL_MODE 0x0000 e1000_defines.h MDI Crossover Mode bits 6:5
2816
 M88E1000_PSCR_MDIX_MANUAL_MODEM88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 e1000_defines.h Manual MDIX configuration
2817
 M88E1000_PSCR_AUTO_X_1000TM88E1000_PSCR_AUTO_X_1000T 0x0040 e1000_defines.h 　
2818
 M88E1000_PSCR_AUTO_X_MODEM88E1000_PSCR_AUTO_X_MODE 0x0060 e1000_defines.h 　
2819
 M88E1000_PSCR_EN_10BT_EXT_DISTM88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 e1000_defines.h 　
2820
 M88E1000_PSCR_MII_5BIT_ENABLEM88E1000_PSCR_MII_5BIT_ENABLE 0x0100 e1000_defines.h 　
2821
 M88E1000_PSCR_SCRAMBLER_DISABLEM88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 e1000_defines.h 1=Scrambler disable
2822
 M88E1000_PSCR_FORCE_LINK_GOODM88E1000_PSCR_FORCE_LINK_GOOD 0x0400 e1000_defines.h 1=Force link good
2823
 M88E1000_PSCR_ASSERT_CRS_ON_TXM88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 e1000_defines.h 1=Assert CRS on Tx
2824
 M88E1000_PSSR_JABBERM88E1000_PSSR_JABBER 0x0001 e1000_defines.h 1=Jabber
2825
 M88E1000_PSSR_REV_POLARITYM88E1000_PSSR_REV_POLARITY 0x0002 e1000_defines.h 1=Polarity reversed
2826
 M88E1000_PSSR_DOWNSHIFTM88E1000_PSSR_DOWNSHIFT 0x0020 e1000_defines.h 1=Downshifted
2827
 M88E1000_PSSR_MDIXM88E1000_PSSR_MDIX 0x0040 e1000_defines.h 1=MDIX; 0=MDI
2828
 M88E1000_PSSR_CABLE_LENGTHM88E1000_PSSR_CABLE_LENGTH 0x0380 e1000_defines.h 　
2829
 M88E1000_PSSR_LINKM88E1000_PSSR_LINK 0x0400 e1000_defines.h 1=Link up, 0=Link down
2830
 M88E1000_PSSR_SPD_DPLX_RESOLVEDM88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 e1000_defines.h 1=Speed & Duplex resolved
2831
 M88E1000_PSSR_PAGE_RCVDM88E1000_PSSR_PAGE_RCVD 0x1000 e1000_defines.h 1=Page received
2832
 M88E1000_PSSR_DPLXM88E1000_PSSR_DPLX 0x2000 e1000_defines.h 1=Duplex 0=Half Duplex
2833
 M88E1000_PSSR_SPEEDM88E1000_PSSR_SPEED 0xC000 e1000_defines.h Speed, bits 14:15
2834
 M88E1000_PSSR_10MBSM88E1000_PSSR_10MBS 0x0000 e1000_defines.h 00=10Mbs
2835
 M88E1000_PSSR_100MBSM88E1000_PSSR_100MBS 0x4000 e1000_defines.h 01=100Mbs
2836
 M88E1000_PSSR_1000MBSM88E1000_PSSR_1000MBS 0x8000 e1000_defines.h 10=1000Mbs
2837
 M88E1000_PSSR_CABLE_LENGTH_SHIFM88E1000_PSSR_CABLE_LENGTH_SHIF 7 e1000_defines.h 　
2838
 M88E1000_EPSCR_FIBER_LOOPBACKM88E1000_EPSCR_FIBER_LOOPBACK 0x4000 e1000_defines.h 1=Fiber loopback
2839
 M88E1000_EPSCR_DOWN_NO_IDLEM88E1000_EPSCR_DOWN_NO_IDLE 0x8000 e1000_defines.h 　
2840
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 e1000_defines.h 　
2841
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0000 e1000_defines.h 　
2842
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0400 e1000_defines.h 　
2843
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0800 e1000_defines.h 　
2844
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 e1000_defines.h 　
2845
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 e1000_defines.h 　
2846
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0000 e1000_defines.h 　
2847
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0100 e1000_defines.h 　
2848
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0200 e1000_defines.h 　
2849
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 e1000_defines.h 　
2850
 M88E1000_EPSCR_TX_CLK_2_5M88E1000_EPSCR_TX_CLK_2_5 0x0060 e1000_defines.h 2.5 MHz TX_CLK
2851
 M88E1000_EPSCR_TX_CLK_25M88E1000_EPSCR_TX_CLK_25 0x0070 e1000_defines.h 25 MHz TX_CLK
2852
 M88E1000_EPSCR_TX_CLK_0M88E1000_EPSCR_TX_CLK_0 0x0000 e1000_defines.h NO TX_CLK
2853
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 e1000_defines.h 　
2854
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0000 e1000_defines.h 　
2855
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0200 e1000_defines.h 　
2856
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0400 e1000_defines.h 　
2857
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0600 e1000_defines.h 　
2858
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0800 e1000_defines.h 　
2859
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0A00 e1000_defines.h 　
2860
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0C00 e1000_defines.h 　
2861
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 e1000_defines.h 　
2862
 GG82563_PAGE_SHIFTGG82563_PAGE_SHIFT 5 e1000_defines.h 　
2863
 GG82563_MIN_ALT_REGGG82563_MIN_ALT_REG 30 e1000_defines.h 　
2864
 GG82563_PHY_SPEC_CTRLGG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) e1000_defines.h PHY Specific Control
2865
 GG82563_PHY_SPEC_STATUSGG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) e1000_defines.h PHY Specific Status
2866
 GG82563_PHY_INT_ENABLEGG82563_PHY_INT_ENABLE GG82563_REG(0, 18) e1000_defines.h Interrupt Enable
2867
 GG82563_PHY_SPEC_STATUS_2GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) e1000_defines.h PHY Specific Status 2
2868
 GG82563_PHY_RX_ERR_CNTRGG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) e1000_defines.h Receive Error Counter
2869
 GG82563_PHY_PAGE_SELECTGG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) e1000_defines.h Page Select
2870
 GG82563_PHY_SPEC_CTRL_2GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) e1000_defines.h PHY Specific Control 2
2871
 GG82563_PHY_PAGE_SELECT_ALTGG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) e1000_defines.h Alternate Page Select
2872
 GG82563_PHY_TEST_CLK_CTRLGG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) e1000_defines.h Test Clock Control (use reg. 29 to select)
2873
 GG82563_PHY_MAC_SPEC_CTRLGG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) e1000_defines.h MAC Specific Control Register
2874
 GG82563_PHY_MAC_SPEC_CTRL_2GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) e1000_defines.h MAC Specific Control 2
2875
 GG82563_PHY_DSP_DISTANCEGG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) e1000_defines.h DSP Distance
2876
 GG82563_PHY_KMRN_MODE_CTRLGG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) e1000_defines.h Kumeran Mode Control
2877
 GG82563_PHY_PORT_RESETGG82563_PHY_PORT_RESET GG82563_REG(193, 17) e1000_defines.h Port Reset
2878
 GG82563_PHY_REVISION_IDGG82563_PHY_REVISION_ID GG82563_REG(193, 18) e1000_defines.h Revision ID
2879
 GG82563_PHY_DEVICE_IDGG82563_PHY_DEVICE_ID GG82563_REG(193, 19) e1000_defines.h Device ID
2880
 GG82563_PHY_PWR_MGMT_CTRLGG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) e1000_defines.h Power Management Control
2881
 GG82563_PHY_RATE_ADAPT_CTRLGG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) e1000_defines.h Rate Adaptation Control
2882
 GG82563_PHY_KMRN_FIFO_CTRL_STATGG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) e1000_defines.h FIFO's Control/Status
2883
 GG82563_PHY_KMRN_CTRLGG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) e1000_defines.h Control
2884
 GG82563_PHY_INBAND_CTRLGG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) e1000_defines.h Inband Control
2885
 GG82563_PHY_KMRN_DIAGNOSTICGG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) e1000_defines.h Diagnostic
2886
 GG82563_PHY_ACK_TIMEOUTSGG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) e1000_defines.h Acknowledge Timeouts
2887
 GG82563_PHY_ADV_ABILITYGG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) e1000_defines.h Advertised Ability
2888
 GG82563_PHY_LINK_PARTNER_ADV_ABGG82563_PHY_LINK_PARTNER_ADV_AB GG82563_REG(194, 23) e1000_defines.h Link Partner Advertised Ability
2889
 GG82563_PHY_ADV_NEXT_PAGEGG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) e1000_defines.h Advertised Next Page
2890
 GG82563_PHY_LINK_PARTNER_ADV_NEGG82563_PHY_LINK_PARTNER_ADV_NE GG82563_REG(194, 25) e1000_defines.h Link Partner Advertised Next page
2891
 GG82563_PHY_KMRN_MISCGG82563_PHY_KMRN_MISC GG82563_REG(194, 26) e1000_defines.h Misc.
2892
 E1000_MDIC_DATA_MASKE1000_MDIC_DATA_MASK 0x0000FFFF e1000_defines.h 　
2893
 E1000_MDIC_REG_MASKE1000_MDIC_REG_MASK 0x001F0000 e1000_defines.h 　
2894
 E1000_MDIC_REG_SHIFTE1000_MDIC_REG_SHIFT 16 e1000_defines.h 　
2895
 E1000_MDIC_PHY_MASKE1000_MDIC_PHY_MASK 0x03E00000 e1000_defines.h 　
2896
 E1000_MDIC_PHY_SHIFTE1000_MDIC_PHY_SHIFT 21 e1000_defines.h 　
2897
 E1000_MDIC_OP_WRITEE1000_MDIC_OP_WRITE 0x04000000 e1000_defines.h 　
2898
 E1000_MDIC_OP_READE1000_MDIC_OP_READ 0x08000000 e1000_defines.h 　
2899
 E1000_MDIC_READYE1000_MDIC_READY 0x10000000 e1000_defines.h 　
2900
 E1000_MDIC_INT_ENE1000_MDIC_INT_EN 0x20000000 e1000_defines.h 　
2901
 E1000_MDIC_ERRORE1000_MDIC_ERROR 0x40000000 e1000_defines.h 　
2902
 E1000_GEN_CTL_READYE1000_GEN_CTL_READY 0x80000000 e1000_defines.h 　
2903
 E1000_GEN_CTL_ADDRESS_SHIFTE1000_GEN_CTL_ADDRESS_SHIFT 8 e1000_defines.h 　
2904
 E1000_GEN_POLL_TIMEOUTE1000_GEN_POLL_TIMEOUT 640 e1000_defines.h 　
2905
 E1000_DEV_ID_82542E1000_DEV_ID_82542 0x1000 e1000_hw.h 　
2906
 E1000_DEV_ID_82543GC_FIBERE1000_DEV_ID_82543GC_FIBER 0x1001 e1000_hw.h 　
2907
 E1000_DEV_ID_82543GC_COPPERE1000_DEV_ID_82543GC_COPPER 0x1004 e1000_hw.h 　
2908
 E1000_DEV_ID_82544EI_COPPERE1000_DEV_ID_82544EI_COPPER 0x1008 e1000_hw.h 　
2909
 E1000_DEV_ID_82544EI_FIBERE1000_DEV_ID_82544EI_FIBER 0x1009 e1000_hw.h 　
2910
 E1000_DEV_ID_82544GC_COPPERE1000_DEV_ID_82544GC_COPPER 0x100C e1000_hw.h 　
2911
 E1000_DEV_ID_82544GC_LOME1000_DEV_ID_82544GC_LOM 0x100D e1000_hw.h 　
2912
 E1000_DEV_ID_82540EME1000_DEV_ID_82540EM 0x100E e1000_hw.h 　
2913
 E1000_DEV_ID_82540EM_LOME1000_DEV_ID_82540EM_LOM 0x1015 e1000_hw.h 　
2914
 E1000_DEV_ID_82540EP_LOME1000_DEV_ID_82540EP_LOM 0x1016 e1000_hw.h 　
2915
 E1000_DEV_ID_82540EPE1000_DEV_ID_82540EP 0x1017 e1000_hw.h 　
2916
 E1000_DEV_ID_82540EP_LPE1000_DEV_ID_82540EP_LP 0x101E e1000_hw.h 　
2917
 E1000_DEV_ID_82545EM_COPPERE1000_DEV_ID_82545EM_COPPER 0x100F e1000_hw.h 　
2918
 E1000_DEV_ID_82545EM_FIBERE1000_DEV_ID_82545EM_FIBER 0x1011 e1000_hw.h 　
2919
 E1000_DEV_ID_82545GM_COPPERE1000_DEV_ID_82545GM_COPPER 0x1026 e1000_hw.h 　
2920
 E1000_DEV_ID_82545GM_FIBERE1000_DEV_ID_82545GM_FIBER 0x1027 e1000_hw.h 　
2921
 E1000_DEV_ID_82545GM_SERDESE1000_DEV_ID_82545GM_SERDES 0x1028 e1000_hw.h 　
2922
 E1000_DEV_ID_82546EB_COPPERE1000_DEV_ID_82546EB_COPPER 0x1010 e1000_hw.h 　
2923
 E1000_DEV_ID_82546EB_FIBERE1000_DEV_ID_82546EB_FIBER 0x1012 e1000_hw.h 　
2924
 E1000_DEV_ID_82546EB_QUAD_COPPEE1000_DEV_ID_82546EB_QUAD_COPPE 0x101D e1000_hw.h 　
2925
 E1000_DEV_ID_82546GB_COPPERE1000_DEV_ID_82546GB_COPPER 0x1079 e1000_hw.h 　
2926
 E1000_DEV_ID_82546GB_FIBERE1000_DEV_ID_82546GB_FIBER 0x107A e1000_hw.h 　
2927
 E1000_DEV_ID_82546GB_SERDESE1000_DEV_ID_82546GB_SERDES 0x107B e1000_hw.h 　
2928
 E1000_DEV_ID_82546GB_PCIEE1000_DEV_ID_82546GB_PCIE 0x108A e1000_hw.h 　
2929
 E1000_DEV_ID_82546GB_QUAD_COPPEE1000_DEV_ID_82546GB_QUAD_COPPE 0x1099 e1000_hw.h 　
2930
 E1000_DEV_ID_82546GB_QUAD_COPPEE1000_DEV_ID_82546GB_QUAD_COPPE 0x10B5 e1000_hw.h 　
2931
 E1000_DEV_ID_82541EIE1000_DEV_ID_82541EI 0x1013 e1000_hw.h 　
2932
 E1000_DEV_ID_82541EI_MOBILEE1000_DEV_ID_82541EI_MOBILE 0x1018 e1000_hw.h 　
2933
 E1000_DEV_ID_82541ER_LOME1000_DEV_ID_82541ER_LOM 0x1014 e1000_hw.h 　
2934
 E1000_DEV_ID_82541ERE1000_DEV_ID_82541ER 0x1078 e1000_hw.h 　
2935
 E1000_DEV_ID_82541GIE1000_DEV_ID_82541GI 0x1076 e1000_hw.h 　
2936
 E1000_DEV_ID_82541GI_LFE1000_DEV_ID_82541GI_LF 0x107C e1000_hw.h 　
2937
 E1000_DEV_ID_82541GI_MOBILEE1000_DEV_ID_82541GI_MOBILE 0x1077 e1000_hw.h 　
2938
 E1000_DEV_ID_82547EIE1000_DEV_ID_82547EI 0x1019 e1000_hw.h 　
2939
 E1000_DEV_ID_82547EI_MOBILEE1000_DEV_ID_82547EI_MOBILE 0x101A e1000_hw.h 　
2940
 E1000_DEV_ID_82547GIE1000_DEV_ID_82547GI 0x1075 e1000_hw.h 　
2941
 E1000_REVISION_0E1000_REVISION_0 0 e1000_hw.h 　
2942
 E1000_REVISION_1E1000_REVISION_1 1 e1000_hw.h 　
2943
 E1000_REVISION_2E1000_REVISION_2 2 e1000_hw.h 　
2944
 E1000_REVISION_3E1000_REVISION_3 3 e1000_hw.h 　
2945
 E1000_REVISION_4E1000_REVISION_4 4 e1000_hw.h 　
2946
 E1000_FUNC_0E1000_FUNC_0 0 e1000_hw.h 　
2947
 E1000_FUNC_1E1000_FUNC_1 1 e1000_hw.h 　
2948
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 0 e1000_hw.h 　
2949
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 3 e1000_hw.h 　
2950
 MAX_PS_BUFFERSMAX_PS_BUFFERS 4 e1000_hw.h 　
2951
 E1000_HI_MAX_DATA_LENGTHE1000_HI_MAX_DATA_LENGTH 252 e1000_hw.h 　
2952
 E1000_HI_MAX_MNG_DATA_LENGTHE1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 e1000_hw.h 　
2953
 E1000_FACTPS_MNGCGE1000_FACTPS_MNGCG 0x20000000 e1000_manage.h 　
2954
 E1000_FWSM_MODE_MASKE1000_FWSM_MODE_MASK 0xE e1000_manage.h 　
2955
 E1000_FWSM_MODE_SHIFTE1000_FWSM_MODE_SHIFT 1 e1000_manage.h 　
2956
 E1000_MNG_IAMT_MODEE1000_MNG_IAMT_MODE 0x3 e1000_manage.h 　
2957
 E1000_MNG_DHCP_COOKIE_LENGTHE1000_MNG_DHCP_COOKIE_LENGTH 0x10 e1000_manage.h 　
2958
 E1000_MNG_DHCP_COOKIE_OFFSETE1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 e1000_manage.h 　
2959
 E1000_MNG_DHCP_COMMAND_TIMEOUTE1000_MNG_DHCP_COMMAND_TIMEOUT 10 e1000_manage.h 　
2960
 E1000_MNG_DHCP_TX_PAYLOAD_CMDE1000_MNG_DHCP_TX_PAYLOAD_CMD 64 e1000_manage.h 　
2961
 E1000_MNG_DHCP_COOKIE_STATUS_PAE1000_MNG_DHCP_COOKIE_STATUS_PA 0x1 e1000_manage.h 　
2962
 E1000_MNG_DHCP_COOKIE_STATUS_VLE1000_MNG_DHCP_COOKIE_STATUS_VL 0x2 e1000_manage.h 　
2963
 E1000_VFTA_ENTRY_SHIFTE1000_VFTA_ENTRY_SHIFT 5 e1000_manage.h 　
2964
 E1000_VFTA_ENTRY_MASKE1000_VFTA_ENTRY_MASK 0x7F e1000_manage.h 　
2965
 E1000_VFTA_ENTRY_BIT_SHIFT_MASKE1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F e1000_manage.h 　
2966
 E1000_HI_MAX_BLOCK_BYTE_LENGTHE1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 e1000_manage.h Num of bytes in range
2967
 E1000_HI_MAX_BLOCK_DWORD_LENGTHE1000_HI_MAX_BLOCK_DWORD_LENGTH 448 e1000_manage.h Num of dwords in range
2968
 E1000_HI_COMMAND_TIMEOUTE1000_HI_COMMAND_TIMEOUT 500 e1000_manage.h Process HI command limit
2969
 E1000_HICR_ENE1000_HICR_EN 0x01 e1000_manage.h Enable bit - RO
2970
 E1000_HICR_CE1000_HICR_C 0x02 e1000_manage.h 　
2971
 E1000_HICR_SVE1000_HICR_SV 0x04 e1000_manage.h Status Validity
2972
 E1000_HICR_FW_RESET_ENABLEE1000_HICR_FW_RESET_ENABLE 0x40 e1000_manage.h 　
2973
 E1000_HICR_FW_RESETE1000_HICR_FW_RESET 0x80 e1000_manage.h 　
2974
 E1000_IAMT_SIGNATUREE1000_IAMT_SIGNATURE 0x544D4149 e1000_manage.h 　
2975
 E1000_STM_OPCODEE1000_STM_OPCODE 0xDB00 e1000_nvm.h 　
2976
 u8u8 unsigned char e1000_osdep.h 　
2977
 boolbool boolean_t e1000_osdep.h 　
2978
 dma_addr_tdma_addr_t unsigned long e1000_osdep.h 　
2979
 __le16__le16 uint16_t e1000_osdep.h 　
2980
 __le32__le32 uint32_t e1000_osdep.h 　
2981
 __le64__le64 uint64_t e1000_osdep.h 　
2982
 ETH_FCS_LENETH_FCS_LEN 4 e1000_osdep.h 　
2983
 PCI_COMMAND_REGISTERPCI_COMMAND_REGISTER PCI_COMMAND e1000_osdep.h 　
2984
 CMD_MEM_WRT_INVALIDATECMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE e1000_osdep.h 　
2985
 ETH_ADDR_LENETH_ADDR_LEN ETH_ALEN e1000_osdep.h 　
2986
 DEBUGOUT2DEBUGOUT2 DEBUGOUT1 e1000_osdep.h 　
2987
 DEBUGOUT3DEBUGOUT3 DEBUGOUT2 e1000_osdep.h 　
2988
 DEBUGOUT7DEBUGOUT7 DEBUGOUT3 e1000_osdep.h 　
2989
 E1000_READ_REG_ARRAY_DWORDE1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY e1000_osdep.h 　
2990
 E1000_WRITE_REG_ARRAY_DWORDE1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY e1000_osdep.h 　
2991
 E1000_MAX_PHY_ADDRE1000_MAX_PHY_ADDR 4 e1000_phy.h 　
2992
 IGP01E1000_PHY_PORT_CONFIGIGP01E1000_PHY_PORT_CONFIG 0x10 e1000_phy.h Port Config
2993
 IGP01E1000_PHY_PORT_STATUSIGP01E1000_PHY_PORT_STATUS 0x11 e1000_phy.h Status
2994
 IGP01E1000_PHY_PORT_CTRLIGP01E1000_PHY_PORT_CTRL 0x12 e1000_phy.h Control
2995
 IGP01E1000_PHY_LINK_HEALTHIGP01E1000_PHY_LINK_HEALTH 0x13 e1000_phy.h PHY Link Health
2996
 IGP01E1000_GMII_FIFOIGP01E1000_GMII_FIFO 0x14 e1000_phy.h GMII FIFO
2997
 IGP01E1000_PHY_CHANNEL_QUALITYIGP01E1000_PHY_CHANNEL_QUALITY 0x15 e1000_phy.h PHY Channel Quality
2998
 IGP02E1000_PHY_POWER_MGMTIGP02E1000_PHY_POWER_MGMT 0x19 e1000_phy.h Power Management
2999
 IGP01E1000_PHY_PAGE_SELECTIGP01E1000_PHY_PAGE_SELECT 0x1F e1000_phy.h Page Select
3000
 BM_PHY_PAGE_SELECTBM_PHY_PAGE_SELECT 22 e1000_phy.h Page Select for BM
3001
 IGP_PAGE_SHIFTIGP_PAGE_SHIFT 5 e1000_phy.h 　
3002
 PHY_REG_MASKPHY_REG_MASK 0x1F e1000_phy.h 　
3003
 IGP01E1000_PHY_PCS_INIT_REGIGP01E1000_PHY_PCS_INIT_REG 0x00B4 e1000_phy.h 　
3004
 IGP01E1000_PHY_POLARITY_MASKIGP01E1000_PHY_POLARITY_MASK 0x0078 e1000_phy.h 　
3005
 IGP01E1000_PSCR_AUTO_MDIXIGP01E1000_PSCR_AUTO_MDIX 0x1000 e1000_phy.h 　
3006
 IGP01E1000_PSCR_FORCE_MDI_MDIXIGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 e1000_phy.h 0=MDI, 1=MDIX
3007
 IGP01E1000_PSCFR_SMART_SPEEDIGP01E1000_PSCFR_SMART_SPEED 0x0080 e1000_phy.h 　
3008
 IGP01E1000_GMII_FLEX_SPDIGP01E1000_GMII_FLEX_SPD 0x0010 e1000_phy.h 　
3009
 IGP01E1000_GMII_SPDIGP01E1000_GMII_SPD 0x0020 e1000_phy.h Enable SPD
3010
 IGP02E1000_PM_SPDIGP02E1000_PM_SPD 0x0001 e1000_phy.h Smart Power Down
3011
 IGP02E1000_PM_D0_LPLUIGP02E1000_PM_D0_LPLU 0x0002 e1000_phy.h For D0a states
3012
 IGP02E1000_PM_D3_LPLUIGP02E1000_PM_D3_LPLU 0x0004 e1000_phy.h For all other states
3013
 IGP01E1000_PLHR_SS_DOWNGRADEIGP01E1000_PLHR_SS_DOWNGRADE 0x8000 e1000_phy.h 　
3014
 IGP01E1000_PSSR_POLARITY_REVERSIGP01E1000_PSSR_POLARITY_REVERS 0x0002 e1000_phy.h 　
3015
 IGP01E1000_PSSR_MDIXIGP01E1000_PSSR_MDIX 0x0800 e1000_phy.h 　
3016
 IGP01E1000_PSSR_SPEED_MASKIGP01E1000_PSSR_SPEED_MASK 0xC000 e1000_phy.h 　
3017
 IGP01E1000_PSSR_SPEED_1000MBPSIGP01E1000_PSSR_SPEED_1000MBPS 0xC000 e1000_phy.h 　
3018
 IGP02E1000_PHY_CHANNEL_NUMIGP02E1000_PHY_CHANNEL_NUM 4 e1000_phy.h 　
3019
 IGP02E1000_PHY_AGC_AIGP02E1000_PHY_AGC_A 0x11B1 e1000_phy.h 　
3020
 IGP02E1000_PHY_AGC_BIGP02E1000_PHY_AGC_B 0x12B1 e1000_phy.h 　
3021
 IGP02E1000_PHY_AGC_CIGP02E1000_PHY_AGC_C 0x14B1 e1000_phy.h 　
3022
 IGP02E1000_PHY_AGC_DIGP02E1000_PHY_AGC_D 0x18B1 e1000_phy.h 　
3023
 IGP02E1000_AGC_LENGTH_SHIFTIGP02E1000_AGC_LENGTH_SHIFT 9 e1000_phy.h Course - 15:13, Fine - 12:9
3024
 IGP02E1000_AGC_LENGTH_MASKIGP02E1000_AGC_LENGTH_MASK 0x7F e1000_phy.h 　
3025
 IGP02E1000_AGC_RANGEIGP02E1000_AGC_RANGE 15 e1000_phy.h 　
3026
 IGP03E1000_PHY_MISC_CTRLIGP03E1000_PHY_MISC_CTRL 0x1B e1000_phy.h 　
3027
 IGP03E1000_PHY_MISC_DUPLEX_MANUIGP03E1000_PHY_MISC_DUPLEX_MANU 0x1000 e1000_phy.h Manually Set Duplex
3028
 E1000_CABLE_LENGTH_UNDEFINEDE1000_CABLE_LENGTH_UNDEFINED 0xFF e1000_phy.h 　
3029
 E1000_KMRNCTRLSTA_OFFSETE1000_KMRNCTRLSTA_OFFSET 0x001F0000 e1000_phy.h 　
3030
 E1000_KMRNCTRLSTA_OFFSET_SHIFTE1000_KMRNCTRLSTA_OFFSET_SHIFT 16 e1000_phy.h 　
3031
 E1000_KMRNCTRLSTA_RENE1000_KMRNCTRLSTA_REN 0x00200000 e1000_phy.h 　
3032
 E1000_KMRNCTRLSTA_DIAG_OFFSETE1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 e1000_phy.h Kumeran Diagnostic
3033
 E1000_KMRNCTRLSTA_TIMEOUTSE1000_KMRNCTRLSTA_TIMEOUTS 0x4 e1000_phy.h Kumeran Timeouts
3034
 E1000_KMRNCTRLSTA_INBAND_PARAME1000_KMRNCTRLSTA_INBAND_PARAM 0x9 e1000_phy.h Kumeran InBand Parameters
3035
 E1000_KMRNCTRLSTA_DIAG_NELPBKE1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 e1000_phy.h Nearend Loopback mode
3036
 IFE_PHY_EXTENDED_STATUS_CONTROLIFE_PHY_EXTENDED_STATUS_CONTROL 0x10 e1000_phy.h 　
3037
 IFE_PHY_SPECIAL_CONTROLIFE_PHY_SPECIAL_CONTROL 0x11 e1000_phy.h 100BaseTx PHY Special Control
3038
 IFE_PHY_SPECIAL_CONTROL_LEDIFE_PHY_SPECIAL_CONTROL_LED 0x1B e1000_phy.h PHY Special and LED Control
3039
 IFE_PHY_MDIX_CONTROLIFE_PHY_MDIX_CONTROL 0x1C e1000_phy.h MDI/MDI-X Control
3040
 IFE_PESC_POLARITY_REVERSEDIFE_PESC_POLARITY_REVERSED 0x0100 e1000_phy.h 　
3041
 IFE_PSC_AUTO_POLARITY_DISABLEIFE_PSC_AUTO_POLARITY_DISABLE 0x0010 e1000_phy.h 　
3042
 IFE_PSC_FORCE_POLARITYIFE_PSC_FORCE_POLARITY 0x0020 e1000_phy.h 　
3043
 IFE_PSC_DISABLE_DYNAMIC_POWER_DIFE_PSC_DISABLE_DYNAMIC_POWER_D 0x0100 e1000_phy.h 　
3044
 IFE_PSCL_PROBE_MODEIFE_PSCL_PROBE_MODE 0x0020 e1000_phy.h 　
3045
 IFE_PSCL_PROBE_LEDS_OFFIFE_PSCL_PROBE_LEDS_OFF 0x0006 e1000_phy.h Force LEDs 0 and 2 off
3046
 IFE_PSCL_PROBE_LEDS_ONIFE_PSCL_PROBE_LEDS_ON 0x0007 e1000_phy.h Force LEDs 0 and 2 on
3047
 IFE_PMC_MDIX_STATUSIFE_PMC_MDIX_STATUS 0x0020 e1000_phy.h 1=MDI-X, 0=MDI
3048
 IFE_PMC_FORCE_MDIXIFE_PMC_FORCE_MDIX 0x0040 e1000_phy.h 1=force MDI-X, 0=force MDI
3049
 IFE_PMC_AUTO_MDIXIFE_PMC_AUTO_MDIX 0x0080 e1000_phy.h 1=enable auto MDI/MDI-X, 0=disable
3050
 E1000_CTRLE1000_CTRL 0x00000 e1000_regs.h Device Control - RW
3051
 E1000_CTRL_DUPE1000_CTRL_DUP 0x00004 e1000_regs.h Device Control Duplicate (Shadow) - RW
3052
 E1000_STATUSE1000_STATUS 0x00008 e1000_regs.h Device Status - RO
3053
 E1000_EECDE1000_EECD 0x00010 e1000_regs.h EEPROM/Flash Control - RW
3054
 E1000_EERDE1000_EERD 0x00014 e1000_regs.h EEPROM Read - RW
3055
 E1000_CTRL_EXTE1000_CTRL_EXT 0x00018 e1000_regs.h Extended Device Control - RW
3056
 E1000_FLAE1000_FLA 0x0001C e1000_regs.h Flash Access - RW
3057
 E1000_MDICE1000_MDIC 0x00020 e1000_regs.h MDI Control - RW
3058
 E1000_SCTLE1000_SCTL 0x00024 e1000_regs.h SerDes Control - RW
3059
 E1000_FCALE1000_FCAL 0x00028 e1000_regs.h Flow Control Address Low - RW
3060
 E1000_FCAHE1000_FCAH 0x0002C e1000_regs.h Flow Control Address High -RW
3061
 E1000_FEXTE1000_FEXT 0x0002C e1000_regs.h Future Extended - RW
3062
 E1000_FEXTNVME1000_FEXTNVM 0x00028 e1000_regs.h Future Extended NVM - RW
3063
 E1000_FCTE1000_FCT 0x00030 e1000_regs.h Flow Control Type - RW
3064
 E1000_CONNSWE1000_CONNSW 0x00034 e1000_regs.h Copper/Fiber switch control - RW
3065
 E1000_VETE1000_VET 0x00038 e1000_regs.h VLAN Ether Type - RW
3066
 E1000_ICRE1000_ICR 0x000C0 e1000_regs.h Interrupt Cause Read - R/clr
3067
 E1000_ITRE1000_ITR 0x000C4 e1000_regs.h Interrupt Throttling Rate - RW
3068
 E1000_ICSE1000_ICS 0x000C8 e1000_regs.h Interrupt Cause Set - WO
3069
 E1000_IMSE1000_IMS 0x000D0 e1000_regs.h Interrupt Mask Set - RW
3070
 E1000_IMCE1000_IMC 0x000D8 e1000_regs.h Interrupt Mask Clear - WO
3071
 E1000_IAME1000_IAM 0x000E0 e1000_regs.h Interrupt Acknowledge Auto Mask
3072
 E1000_RCTLE1000_RCTL 0x00100 e1000_regs.h Rx Control - RW
3073
 E1000_FCTTVE1000_FCTTV 0x00170 e1000_regs.h Flow Control Transmit Timer Value - RW
3074
 E1000_TXCWE1000_TXCW 0x00178 e1000_regs.h Tx Configuration Word - RW
3075
 E1000_RXCWE1000_RXCW 0x00180 e1000_regs.h Rx Configuration Word - RO
3076
 E1000_TCTLE1000_TCTL 0x00400 e1000_regs.h Tx Control - RW
3077
 E1000_TCTL_EXTE1000_TCTL_EXT 0x00404 e1000_regs.h Extended Tx Control - RW
3078
 E1000_TIPGE1000_TIPG 0x00410 e1000_regs.h Tx Inter-packet gap -RW
3079
 E1000_TBTE1000_TBT 0x00448 e1000_regs.h Tx Burst Timer - RW
3080
 E1000_AITE1000_AIT 0x00458 e1000_regs.h Adaptive Interframe Spacing Throttle - RW
3081
 E1000_LEDCTLE1000_LEDCTL 0x00E00 e1000_regs.h LED Control - RW
3082
 E1000_EXTCNF_CTRLE1000_EXTCNF_CTRL 0x00F00 e1000_regs.h Extended Configuration Control
3083
 E1000_EXTCNF_SIZEE1000_EXTCNF_SIZE 0x00F08 e1000_regs.h Extended Configuration Size
3084
 E1000_PHY_CTRLE1000_PHY_CTRL 0x00F10 e1000_regs.h PHY Control Register in CSR
3085
 E1000_PBAE1000_PBA 0x01000 e1000_regs.h Packet Buffer Allocation - RW
3086
 E1000_PBSE1000_PBS 0x01008 e1000_regs.h Packet Buffer Size
3087
 E1000_EEMNGCTLE1000_EEMNGCTL 0x01010 e1000_regs.h MNG EEprom Control
3088
 E1000_EEARBCE1000_EEARBC 0x01024 e1000_regs.h EEPROM Auto Read Bus Control
3089
 E1000_FLASHTE1000_FLASHT 0x01028 e1000_regs.h FLASH Timer Register
3090
 E1000_EEWRE1000_EEWR 0x0102C e1000_regs.h EEPROM Write Register - RW
3091
 E1000_FLSWCTLE1000_FLSWCTL 0x01030 e1000_regs.h FLASH control register
3092
 E1000_FLSWDATAE1000_FLSWDATA 0x01034 e1000_regs.h FLASH data register
3093
 E1000_FLSWCNTE1000_FLSWCNT 0x01038 e1000_regs.h FLASH Access Counter
3094
 E1000_FLOPE1000_FLOP 0x0103C e1000_regs.h FLASH Opcode Register
3095
 E1000_I2CCMDE1000_I2CCMD 0x01028 e1000_regs.h SFPI2C Command Register - RW
3096
 E1000_I2CPARAMSE1000_I2CPARAMS 0x0102C e1000_regs.h SFPI2C Parameters Register - RW
3097
 E1000_WDSTPE1000_WDSTP 0x01040 e1000_regs.h Watchdog Setup - RW
3098
 E1000_SWDSTSE1000_SWDSTS 0x01044 e1000_regs.h SW Device Status - RW
3099
 E1000_FRTIMERE1000_FRTIMER 0x01048 e1000_regs.h Free Running Timer - RW
3100
 E1000_ERTE1000_ERT 0x02008 e1000_regs.h Early Rx Threshold - RW
3101
 E1000_FCRTLE1000_FCRTL 0x02160 e1000_regs.h Flow Control Receive Threshold Low - RW
3102
 E1000_FCRTHE1000_FCRTH 0x02168 e1000_regs.h Flow Control Receive Threshold High - RW
3103
 E1000_PSRCTLE1000_PSRCTL 0x02170 e1000_regs.h Packet Split Receive Control - RW
3104
 E1000_PBRTHE1000_PBRTH 0x02458 e1000_regs.h PB Rx Arbitration Threshold - RW
3105
 E1000_FCRTVE1000_FCRTV 0x02460 e1000_regs.h Flow Control Refresh Timer Value - RW
3106
 E1000_RDPUMBE1000_RDPUMB 0x025CC e1000_regs.h DMA Rx Descriptor uC Mailbox - RW
3107
 E1000_RDPUADE1000_RDPUAD 0x025D0 e1000_regs.h DMA Rx Descriptor uC Addr Command - RW
3108
 E1000_RDPUWDE1000_RDPUWD 0x025D4 e1000_regs.h DMA Rx Descriptor uC Data Write - RW
3109
 E1000_RDPURDE1000_RDPURD 0x025D8 e1000_regs.h DMA Rx Descriptor uC Data Read - RW
3110
 E1000_RDPUCTLE1000_RDPUCTL 0x025DC e1000_regs.h DMA Rx Descriptor uC Control - RW
3111
 E1000_RDTRE1000_RDTR 0x02820 e1000_regs.h Rx Delay Timer - RW
3112
 E1000_RADVE1000_RADV 0x0282C e1000_regs.h Rx Interrupt Absolute Delay Timer - RW
3113
 E1000_RSRPDE1000_RSRPD 0x02C00 e1000_regs.h Rx Small Packet Detect - RW
3114
 E1000_RAIDE1000_RAID 0x02C08 e1000_regs.h Receive Ack Interrupt Delay - RW
3115
 E1000_TXDMACE1000_TXDMAC 0x03000 e1000_regs.h Tx DMA Control - RW
3116
 E1000_KABGTXDE1000_KABGTXD 0x03004 e1000_regs.h AFE Band Gap Transmit Ref Data
3117
 E1000_TDFHE1000_TDFH 0x03410 e1000_regs.h Tx Data FIFO Head - RW
3118
 E1000_TDFTE1000_TDFT 0x03418 e1000_regs.h Tx Data FIFO Tail - RW
3119
 E1000_TDFHSE1000_TDFHS 0x03420 e1000_regs.h Tx Data FIFO Head Saved - RW
3120
 E1000_TDFTSE1000_TDFTS 0x03428 e1000_regs.h Tx Data FIFO Tail Saved - RW
3121
 E1000_TDFPCE1000_TDFPC 0x03430 e1000_regs.h Tx Data FIFO Packet Count - RW
3122
 E1000_TDPUMBE1000_TDPUMB 0x0357C e1000_regs.h DMA Tx Descriptor uC Mail Box - RW
3123
 E1000_TDPUADE1000_TDPUAD 0x03580 e1000_regs.h DMA Tx Descriptor uC Addr Command - RW
3124
 E1000_TDPUWDE1000_TDPUWD 0x03584 e1000_regs.h DMA Tx Descriptor uC Data Write - RW
3125
 E1000_TDPURDE1000_TDPURD 0x03588 e1000_regs.h DMA Tx Descriptor uC Data Read - RW
3126
 E1000_TDPUCTLE1000_TDPUCTL 0x0358C e1000_regs.h DMA Tx Descriptor uC Control - RW
3127
 E1000_DTXCTLE1000_DTXCTL 0x03590 e1000_regs.h DMA Tx Control - RW
3128
 E1000_TIDVE1000_TIDV 0x03820 e1000_regs.h Tx Interrupt Delay Value - RW
3129
 E1000_TADVE1000_TADV 0x0382C e1000_regs.h Tx Interrupt Absolute Delay Val - RW
3130
 E1000_TSPMTE1000_TSPMT 0x03830 e1000_regs.h TCP Segmentation PAD & Min Threshold - RW
3131
 E1000_CRCERRSE1000_CRCERRS 0x04000 e1000_regs.h CRC Error Count - R/clr
3132
 E1000_ALGNERRCE1000_ALGNERRC 0x04004 e1000_regs.h Alignment Error Count - R/clr
3133
 E1000_SYMERRSE1000_SYMERRS 0x04008 e1000_regs.h Symbol Error Count - R/clr
3134
 E1000_RXERRCE1000_RXERRC 0x0400C e1000_regs.h Receive Error Count - R/clr
3135
 E1000_MPCE1000_MPC 0x04010 e1000_regs.h Missed Packet Count - R/clr
3136
 E1000_SCCE1000_SCC 0x04014 e1000_regs.h Single Collision Count - R/clr
3137
 E1000_ECOLE1000_ECOL 0x04018 e1000_regs.h Excessive Collision Count - R/clr
3138
 E1000_MCCE1000_MCC 0x0401C e1000_regs.h Multiple Collision Count - R/clr
3139
 E1000_LATECOLE1000_LATECOL 0x04020 e1000_regs.h Late Collision Count - R/clr
3140
 E1000_COLCE1000_COLC 0x04028 e1000_regs.h Collision Count - R/clr
3141
 E1000_DCE1000_DC 0x04030 e1000_regs.h Defer Count - R/clr
3142
 E1000_TNCRSE1000_TNCRS 0x04034 e1000_regs.h Tx-No CRS - R/clr
3143
 E1000_SECE1000_SEC 0x04038 e1000_regs.h Sequence Error Count - R/clr
3144
 E1000_CEXTERRE1000_CEXTERR 0x0403C e1000_regs.h Carrier Extension Error Count - R/clr
3145
 E1000_RLECE1000_RLEC 0x04040 e1000_regs.h Receive Length Error Count - R/clr
3146
 E1000_XONRXCE1000_XONRXC 0x04048 e1000_regs.h XON Rx Count - R/clr
3147
 E1000_XONTXCE1000_XONTXC 0x0404C e1000_regs.h XON Tx Count - R/clr
3148
 E1000_XOFFRXCE1000_XOFFRXC 0x04050 e1000_regs.h XOFF Rx Count - R/clr
3149
 E1000_XOFFTXCE1000_XOFFTXC 0x04054 e1000_regs.h XOFF Tx Count - R/clr
3150
 E1000_FCRUCE1000_FCRUC 0x04058 e1000_regs.h Flow Control Rx Unsupported Count- R/clr
3151
 E1000_PRC64E1000_PRC64 0x0405C e1000_regs.h Packets Rx (64 bytes) - R/clr
3152
 E1000_PRC127E1000_PRC127 0x04060 e1000_regs.h Packets Rx (65-127 bytes) - R/clr
3153
 E1000_PRC255E1000_PRC255 0x04064 e1000_regs.h Packets Rx (128-255 bytes) - R/clr
3154
 E1000_PRC511E1000_PRC511 0x04068 e1000_regs.h Packets Rx (255-511 bytes) - R/clr
3155
 E1000_PRC1023E1000_PRC1023 0x0406C e1000_regs.h Packets Rx (512-1023 bytes) - R/clr
3156
 E1000_PRC1522E1000_PRC1522 0x04070 e1000_regs.h Packets Rx (1024-1522 bytes) - R/clr
3157
 E1000_GPRCE1000_GPRC 0x04074 e1000_regs.h Good Packets Rx Count - R/clr
3158
 E1000_BPRCE1000_BPRC 0x04078 e1000_regs.h Broadcast Packets Rx Count - R/clr
3159
 E1000_MPRCE1000_MPRC 0x0407C e1000_regs.h Multicast Packets Rx Count - R/clr
3160
 E1000_GPTCE1000_GPTC 0x04080 e1000_regs.h Good Packets Tx Count - R/clr
3161
 E1000_GORCLE1000_GORCL 0x04088 e1000_regs.h Good Octets Rx Count Low - R/clr
3162
 E1000_GORCHE1000_GORCH 0x0408C e1000_regs.h Good Octets Rx Count High - R/clr
3163
 E1000_GOTCLE1000_GOTCL 0x04090 e1000_regs.h Good Octets Tx Count Low - R/clr
3164
 E1000_GOTCHE1000_GOTCH 0x04094 e1000_regs.h Good Octets Tx Count High - R/clr
3165
 E1000_RNBCE1000_RNBC 0x040A0 e1000_regs.h Rx No Buffers Count - R/clr
3166
 E1000_RUCE1000_RUC 0x040A4 e1000_regs.h Rx Undersize Count - R/clr
3167
 E1000_RFCE1000_RFC 0x040A8 e1000_regs.h Rx Fragment Count - R/clr
3168
 E1000_ROCE1000_ROC 0x040AC e1000_regs.h Rx Oversize Count - R/clr
3169
 E1000_RJCE1000_RJC 0x040B0 e1000_regs.h Rx Jabber Count - R/clr
3170
 E1000_MGTPRCE1000_MGTPRC 0x040B4 e1000_regs.h Management Packets Rx Count - R/clr
3171
 E1000_MGTPDCE1000_MGTPDC 0x040B8 e1000_regs.h Management Packets Dropped Count - R/clr
3172
 E1000_MGTPTCE1000_MGTPTC 0x040BC e1000_regs.h Management Packets Tx Count - R/clr
3173
 E1000_TORLE1000_TORL 0x040C0 e1000_regs.h Total Octets Rx Low - R/clr
3174
 E1000_TORHE1000_TORH 0x040C4 e1000_regs.h Total Octets Rx High - R/clr
3175
 E1000_TOTLE1000_TOTL 0x040C8 e1000_regs.h Total Octets Tx Low - R/clr
3176
 E1000_TOTHE1000_TOTH 0x040CC e1000_regs.h Total Octets Tx High - R/clr
3177
 E1000_TPRE1000_TPR 0x040D0 e1000_regs.h Total Packets Rx - R/clr
3178
 E1000_TPTE1000_TPT 0x040D4 e1000_regs.h Total Packets Tx - R/clr
3179
 E1000_PTC64E1000_PTC64 0x040D8 e1000_regs.h Packets Tx (64 bytes) - R/clr
3180
 E1000_PTC127E1000_PTC127 0x040DC e1000_regs.h Packets Tx (65-127 bytes) - R/clr
3181
 E1000_PTC255E1000_PTC255 0x040E0 e1000_regs.h Packets Tx (128-255 bytes) - R/clr
3182
 E1000_PTC511E1000_PTC511 0x040E4 e1000_regs.h Packets Tx (256-511 bytes) - R/clr
3183
 E1000_PTC1023E1000_PTC1023 0x040E8 e1000_regs.h Packets Tx (512-1023 bytes) - R/clr
3184
 E1000_PTC1522E1000_PTC1522 0x040EC e1000_regs.h Packets Tx (1024-1522 Bytes) - R/clr
3185
 E1000_MPTCE1000_MPTC 0x040F0 e1000_regs.h Multicast Packets Tx Count - R/clr
3186
 E1000_BPTCE1000_BPTC 0x040F4 e1000_regs.h Broadcast Packets Tx Count - R/clr
3187
 E1000_TSCTCE1000_TSCTC 0x040F8 e1000_regs.h TCP Segmentation Context Tx - R/clr
3188
 E1000_TSCTFCE1000_TSCTFC 0x040FC e1000_regs.h TCP Segmentation Context Tx Fail - R/clr
3189
 E1000_IACE1000_IAC 0x04100 e1000_regs.h Interrupt Assertion Count
3190
 E1000_ICRXPTCE1000_ICRXPTC 0x04104 e1000_regs.h Interrupt Cause Rx Pkt Timer Expire Count
3191
 E1000_ICRXATCE1000_ICRXATC 0x04108 e1000_regs.h Interrupt Cause Rx Abs Timer Expire Count
3192
 E1000_ICTXPTCE1000_ICTXPTC 0x0410C e1000_regs.h Interrupt Cause Tx Pkt Timer Expire Count
3193
 E1000_ICTXATCE1000_ICTXATC 0x04110 e1000_regs.h Interrupt Cause Tx Abs Timer Expire Count
3194
 E1000_ICTXQECE1000_ICTXQEC 0x04118 e1000_regs.h Interrupt Cause Tx Queue Empty Count
3195
 E1000_ICTXQMTCE1000_ICTXQMTC 0x0411C e1000_regs.h Interrupt Cause Tx Queue Min Thresh Count
3196
 E1000_ICRXDMTCE1000_ICRXDMTC 0x04120 e1000_regs.h Interrupt Cause Rx Desc Min Thresh Count
3197
 E1000_ICRXOCE1000_ICRXOC 0x04124 e1000_regs.h Interrupt Cause Receiver Overrun Count
3198
 E1000_PCS_CFG0E1000_PCS_CFG0 0x04200 e1000_regs.h PCS Configuration 0 - RW
3199
 E1000_PCS_LCTLE1000_PCS_LCTL 0x04208 e1000_regs.h PCS Link Control - RW
3200
 E1000_PCS_LSTATE1000_PCS_LSTAT 0x0420C e1000_regs.h PCS Link Status - RO
3201
 E1000_CBTMPCE1000_CBTMPC 0x0402C e1000_regs.h Circuit Breaker Tx Packet Count
3202
 E1000_HTDPMCE1000_HTDPMC 0x0403C e1000_regs.h Host Transmit Discarded Packets
3203
 E1000_CBRDPCE1000_CBRDPC 0x04044 e1000_regs.h Circuit Breaker Rx Dropped Count
3204
 E1000_CBRMPCE1000_CBRMPC 0x040FC e1000_regs.h Circuit Breaker Rx Packet Count
3205
 E1000_RPTHCE1000_RPTHC 0x04104 e1000_regs.h Rx Packets To Host
3206
 E1000_HGPTCE1000_HGPTC 0x04118 e1000_regs.h Host Good Packets Tx Count
3207
 E1000_HTCBDPCE1000_HTCBDPC 0x04124 e1000_regs.h Host Tx Circuit Breaker Dropped Count
3208
 E1000_HGORCLE1000_HGORCL 0x04128 e1000_regs.h Host Good Octets Received Count Low
3209
 E1000_HGORCHE1000_HGORCH 0x0412C e1000_regs.h Host Good Octets Received Count High
3210
 E1000_HGOTCLE1000_HGOTCL 0x04130 e1000_regs.h Host Good Octets Transmit Count Low
3211
 E1000_HGOTCHE1000_HGOTCH 0x04134 e1000_regs.h Host Good Octets Transmit Count High
3212
 E1000_LENERRSE1000_LENERRS 0x04138 e1000_regs.h Length Errors Count
3213
 E1000_SCVPCE1000_SCVPC 0x04228 e1000_regs.h SerDes/SGMII Code Violation Pkt Count
3214
 E1000_HRMPCE1000_HRMPC 0x0A018 e1000_regs.h Header Redirection Missed Packet Count
3215
 E1000_PCS_ANADVE1000_PCS_ANADV 0x04218 e1000_regs.h AN advertisement - RW
3216
 E1000_PCS_LPABE1000_PCS_LPAB 0x0421C e1000_regs.h Link Partner Ability - RW
3217
 E1000_PCS_NPTXE1000_PCS_NPTX 0x04220 e1000_regs.h AN Next Page Transmit - RW
3218
 E1000_PCS_LPABNPE1000_PCS_LPABNP 0x04224 e1000_regs.h Link Partner Ability Next Page - RW
3219
 E1000_1GSTAT_RCVE1000_1GSTAT_RCV 0x04228 e1000_regs.h 1GSTAT Code Violation Packet Count - RW
3220
 E1000_RXCSUME1000_RXCSUM 0x05000 e1000_regs.h Rx Checksum Control - RW
3221
 E1000_RLPMLE1000_RLPML 0x05004 e1000_regs.h Rx Long Packet Max Length
3222
 E1000_RFCTLE1000_RFCTL 0x05008 e1000_regs.h Receive Filter Control
3223
 E1000_MTAE1000_MTA 0x05200 e1000_regs.h Multicast Table Array - RW Array
3224
 E1000_RAE1000_RA 0x05400 e1000_regs.h Receive Address - RW Array
3225
 E1000_VFTAE1000_VFTA 0x05600 e1000_regs.h VLAN Filter Table Array - RW Array
3226
 E1000_VT_CTLE1000_VT_CTL 0x0581C e1000_regs.h VMDq Control - RW
3227
 E1000_VFQA0E1000_VFQA0 0x0B000 e1000_regs.h VLAN Filter Queue Array 0 - RW Array
3228
 E1000_VFQA1E1000_VFQA1 0x0B200 e1000_regs.h VLAN Filter Queue Array 1 - RW Array
3229
 E1000_WUCE1000_WUC 0x05800 e1000_regs.h Wakeup Control - RW
3230
 E1000_WUFCE1000_WUFC 0x05808 e1000_regs.h Wakeup Filter Control - RW
3231
 E1000_WUSE1000_WUS 0x05810 e1000_regs.h Wakeup Status - RO
3232
 E1000_MANCE1000_MANC 0x05820 e1000_regs.h Management Control - RW
3233
 E1000_IPAVE1000_IPAV 0x05838 e1000_regs.h IP Address Valid - RW
3234
 E1000_IP4ATE1000_IP4AT 0x05840 e1000_regs.h IPv4 Address Table - RW Array
3235
 E1000_IP6ATE1000_IP6AT 0x05880 e1000_regs.h IPv6 Address Table - RW Array
3236
 E1000_WUPLE1000_WUPL 0x05900 e1000_regs.h Wakeup Packet Length - RW
3237
 E1000_WUPME1000_WUPM 0x05A00 e1000_regs.h Wakeup Packet Memory - RO A
3238
 E1000_PBACLE1000_PBACL 0x05B68 e1000_regs.h MSIx PBA Clear - Read/Write 1's to clear
3239
 E1000_FFLTE1000_FFLT 0x05F00 e1000_regs.h Flexible Filter Length Table - RW Array
3240
 E1000_HOST_IFE1000_HOST_IF 0x08800 e1000_regs.h Host Interface
3241
 E1000_FFMTE1000_FFMT 0x09000 e1000_regs.h Flexible Filter Mask Table - RW Array
3242
 E1000_FFVTE1000_FFVT 0x09800 e1000_regs.h Flexible Filter Value Table - RW Array
3243
 E1000_KMRNCTRLSTAE1000_KMRNCTRLSTA 0x00034 e1000_regs.h MAC-PHY interface - RW
3244
 E1000_MDPHYAE1000_MDPHYA 0x0003C e1000_regs.h PHY address - RW
3245
 E1000_MANC2HE1000_MANC2H 0x05860 e1000_regs.h Management Control To Host - RW
3246
 E1000_SW_FW_SYNCE1000_SW_FW_SYNC 0x05B5C e1000_regs.h Software-Firmware Synchronization - RW
3247
 E1000_CCMCTLE1000_CCMCTL 0x05B48 e1000_regs.h CCM Control Register
3248
 E1000_GIOCTLE1000_GIOCTL 0x05B44 e1000_regs.h GIO Analog Control Register
3249
 E1000_SCCTLE1000_SCCTL 0x05B4C e1000_regs.h PCIc PLL Configuration Register
3250
 E1000_GCRE1000_GCR 0x05B00 e1000_regs.h PCI-Ex Control
3251
 E1000_GCR2E1000_GCR2 0x05B64 e1000_regs.h PCI-Ex Control #2
3252
 E1000_GSCL_1E1000_GSCL_1 0x05B10 e1000_regs.h PCI-Ex Statistic Control #1
3253
 E1000_GSCL_2E1000_GSCL_2 0x05B14 e1000_regs.h PCI-Ex Statistic Control #2
3254
 E1000_GSCL_3E1000_GSCL_3 0x05B18 e1000_regs.h PCI-Ex Statistic Control #3
3255
 E1000_GSCL_4E1000_GSCL_4 0x05B1C e1000_regs.h PCI-Ex Statistic Control #4
3256
 E1000_FACTPSE1000_FACTPS 0x05B30 e1000_regs.h Function Active and Power State to MNG
3257
 E1000_SWSME1000_SWSM 0x05B50 e1000_regs.h SW Semaphore
3258
 E1000_FWSME1000_FWSM 0x05B54 e1000_regs.h FW Semaphore
3259
 E1000_SWSM2E1000_SWSM2 0x05B58 e1000_regs.h Driver-only SW semaphore (not used by BOOT agents)
3260
 E1000_DCA_IDE1000_DCA_ID 0x05B70 e1000_regs.h DCA Requester ID Information - RO
3261
 E1000_DCA_CTRLE1000_DCA_CTRL 0x05B74 e1000_regs.h DCA Control - RW
3262
 E1000_FFLT_DBGE1000_FFLT_DBG 0x05F04 e1000_regs.h Debug Register
3263
 E1000_HICRE1000_HICR 0x08F00 e1000_regs.h Host Interface Control
3264
 E1000_CPUVECE1000_CPUVEC 0x02C10 e1000_regs.h CPU Vector Register - RW
3265
 E1000_MRQCE1000_MRQC 0x05818 e1000_regs.h Multiple Receive Control - RW
3266
 E1000_IMIRVPE1000_IMIRVP 0x05AC0 e1000_regs.h Immediate Interrupt Rx VLAN Priority - RW
3267
 E1000_MSIXPBAE1000_MSIXPBA 0x0E000 e1000_regs.h MSI-X Pending bit array
3268
 E1000_RSSIME1000_RSSIM 0x05864 e1000_regs.h RSS Interrupt Mask
3269
 E1000_RSSIRE1000_RSSIR 0x05868 e1000_regs.h RSS Interrupt Request
3270
 GG82563_CABLE_LENGTH_TABLE_SIZEGG82563_CABLE_LENGTH_TABLE_SIZE (sizeof(e1000_gg82563_cable_length_table) / \ sizeof(e1000_gg82563_cable_length_table[0])) e1000e_80003es2lan.c 　
3271
 M88E1000_CABLE_LENGTH_TABLE_SIZM88E1000_CABLE_LENGTH_TABLE_SIZ (sizeof(e1000_m88_cable_length_table) / \ sizeof(e1000_m88_cable_length_table[0])) e1000e_phy.c 　
3272
 IGP02E1000_CABLE_LENGTH_TABLE_SIGP02E1000_CABLE_LENGTH_TABLE_S (sizeof(e1000_igp_2_cable_length_table) / \ sizeof(e1000_igp_2_cable_length_table[0])) e1000e_phy.c 　
3273
 u8u8 unsigned char e1000e.h 　
3274
 boolbool boolean_t e1000e.h 　
3275
 dma_addr_tdma_addr_t unsigned long e1000e.h 　
3276
 __le16__le16 uint16_t e1000e.h 　
3277
 __le32__le32 uint32_t e1000e.h 　
3278
 __le64__le64 uint64_t e1000e.h 　
3279
 ETH_FCS_LENETH_FCS_LEN 4 e1000e.h 　
3280
 E1000_TX_FLAGS_CSUME1000_TX_FLAGS_CSUM 0x00000001 e1000e.h 　
3281
 E1000_TX_FLAGS_VLANE1000_TX_FLAGS_VLAN 0x00000002 e1000e.h 　
3282
 E1000_TX_FLAGS_TSOE1000_TX_FLAGS_TSO 0x00000004 e1000e.h 　
3283
 E1000_TX_FLAGS_IPV4E1000_TX_FLAGS_IPV4 0x00000008 e1000e.h 　
3284
 E1000_TX_FLAGS_VLAN_MASKE1000_TX_FLAGS_VLAN_MASK 0xffff0000 e1000e.h 　
3285
 E1000_TX_FLAGS_VLAN_SHIFTE1000_TX_FLAGS_VLAN_SHIFT 16 e1000e.h 　
3286
 E1000_MAX_PER_TXDE1000_MAX_PER_TXD 8192 e1000e.h 　
3287
 E1000_MAX_TXD_PWRE1000_MAX_TXD_PWR 12 e1000e.h 　
3288
 MINIMUM_DHCP_PACKET_SIZEMINIMUM_DHCP_PACKET_SIZE 282 e1000e.h 　
3289
 E1000E_INT_MODE_LEGACYE1000E_INT_MODE_LEGACY 0 e1000e.h 　
3290
 E1000E_INT_MODE_MSIE1000E_INT_MODE_MSI 1 e1000e.h 　
3291
 E1000E_INT_MODE_MSIXE1000E_INT_MODE_MSIX 2 e1000e.h 　
3292
 E1000_MAX_INTRE1000_MAX_INTR 10 e1000e.h 　
3293
 E1000_DEFAULT_TXDE1000_DEFAULT_TXD 256 e1000e.h 　
3294
 E1000_MAX_TXDE1000_MAX_TXD 4096 e1000e.h 　
3295
 E1000_MIN_TXDE1000_MIN_TXD 64 e1000e.h 　
3296
 E1000_DEFAULT_RXDE1000_DEFAULT_RXD 256 e1000e.h 　
3297
 E1000_MAX_RXDE1000_MAX_RXD 4096 e1000e.h 　
3298
 E1000_MIN_RXDE1000_MIN_RXD 64 e1000e.h 　
3299
 E1000_MIN_ITR_USECSE1000_MIN_ITR_USECS 10 e1000e.h 100000 irq/sec
3300
 E1000_MAX_ITR_USECSE1000_MAX_ITR_USECS 10000 e1000e.h 100 irq/sec
3301
 E1000_ERT_2048E1000_ERT_2048 0x100 e1000e.h 　
3302
 E1000_FC_PAUSE_TIMEE1000_FC_PAUSE_TIME 0x0680 e1000e.h 858 usec
3303
 E1000_RX_BUFFER_WRITEE1000_RX_BUFFER_WRITE 16 e1000e.h Must be power of 2
3304
 AUTO_ALL_MODESAUTO_ALL_MODES 0 e1000e.h 　
3305
 E1000_EEPROM_APMEE1000_EEPROM_APME 0x0400 e1000e.h 　
3306
 E1000_MNG_VLAN_NONEE1000_MNG_VLAN_NONE (-1) e1000e.h 　
3307
 PS_PAGE_BUFFERSPS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) e1000e.h 　
3308
 MAXIMUM_ETHERNET_VLAN_SIZEMAXIMUM_ETHERNET_VLAN_SIZE 1522 e1000e.h 　
3309
 DEFAULT_JUMBODEFAULT_JUMBO 9234 e1000e.h 　
3310
 FLAG_HAS_AMTFLAG_HAS_AMT (1 << 0) e1000e.h 　
3311
 FLAG_HAS_FLASHFLAG_HAS_FLASH (1 << 1) e1000e.h 　
3312
 FLAG_HAS_HW_VLAN_FILTERFLAG_HAS_HW_VLAN_FILTER (1 << 2) e1000e.h 　
3313
 FLAG_HAS_WOLFLAG_HAS_WOL (1 << 3) e1000e.h 　
3314
 FLAG_HAS_ERTFLAG_HAS_ERT (1 << 4) e1000e.h 　
3315
 FLAG_HAS_CTRLEXT_ON_LOADFLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) e1000e.h 　
3316
 FLAG_HAS_SWSM_ON_LOADFLAG_HAS_SWSM_ON_LOAD (1 << 6) e1000e.h 　
3317
 FLAG_HAS_JUMBO_FRAMESFLAG_HAS_JUMBO_FRAMES (1 << 7) e1000e.h 　
3318
 FLAG_IS_ICHFLAG_IS_ICH (1 << 9) e1000e.h 　
3319
 FLAG_HAS_MSIXFLAG_HAS_MSIX (1 << 10) e1000e.h 　
3320
 FLAG_HAS_SMART_POWER_DOWNFLAG_HAS_SMART_POWER_DOWN (1 << 11) e1000e.h 　
3321
 FLAG_IS_QUAD_PORT_AFLAG_IS_QUAD_PORT_A (1 << 12) e1000e.h 　
3322
 FLAG_IS_QUAD_PORTFLAG_IS_QUAD_PORT (1 << 13) e1000e.h 　
3323
 FLAG_TIPG_MEDIUM_FOR_80003ESLANFLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14) e1000e.h 　
3324
 FLAG_APME_IN_WUCFLAG_APME_IN_WUC (1 << 15) e1000e.h 　
3325
 FLAG_APME_IN_CTRL3FLAG_APME_IN_CTRL3 (1 << 16) e1000e.h 　
3326
 FLAG_APME_CHECK_PORT_BFLAG_APME_CHECK_PORT_B (1 << 17) e1000e.h 　
3327
 FLAG_DISABLE_FC_PAUSE_TIMEFLAG_DISABLE_FC_PAUSE_TIME (1 << 18) e1000e.h 　
3328
 FLAG_NO_WAKE_UCASTFLAG_NO_WAKE_UCAST (1 << 19) e1000e.h 　
3329
 FLAG_MNG_PT_ENABLEDFLAG_MNG_PT_ENABLED (1 << 20) e1000e.h 　
3330
 FLAG_RESET_OVERWRITES_LAAFLAG_RESET_OVERWRITES_LAA (1 << 21) e1000e.h 　
3331
 FLAG_TARC_SPEED_MODE_BITFLAG_TARC_SPEED_MODE_BIT (1 << 22) e1000e.h 　
3332
 FLAG_TARC_SET_BIT_ZEROFLAG_TARC_SET_BIT_ZERO (1 << 23) e1000e.h 　
3333
 FLAG_RX_NEEDS_RESTARTFLAG_RX_NEEDS_RESTART (1 << 24) e1000e.h 　
3334
 FLAG_LSC_GIG_SPEED_DROPFLAG_LSC_GIG_SPEED_DROP (1 << 25) e1000e.h 　
3335
 FLAG_SMART_POWER_DOWNFLAG_SMART_POWER_DOWN (1 << 26) e1000e.h 　
3336
 FLAG_MSI_ENABLEDFLAG_MSI_ENABLED (1 << 27) e1000e.h 　
3337
 FLAG_RX_CSUM_ENABLEDFLAG_RX_CSUM_ENABLED (1 << 28) e1000e.h 　
3338
 FLAG_TSO_FORCEFLAG_TSO_FORCE (1 << 29) e1000e.h 　
3339
 FLAG_RX_RESTART_NOWFLAG_RX_RESTART_NOW (1 << 30) e1000e.h 　
3340
 FLAG_MSI_TEST_FAILEDFLAG_MSI_TEST_FAILED (1 << 31) e1000e.h 　
3341
 FLAG2_CRC_STRIPPINGFLAG2_CRC_STRIPPING (1 << 0) e1000e.h 　
3342
 FLAG2_HAS_PHY_WAKEUPFLAG2_HAS_PHY_WAKEUP (1 << 1) e1000e.h 　
3343
 E1000_READ_REG_ARRAY_DWORDE1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY e1000e.h 　
3344
 E1000_WRITE_REG_ARRAY_DWORDE1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY e1000e.h 　
3345
 E1000_KMRNCTRLSTA_OFFSET_FIFO_CE1000_KMRNCTRLSTA_OFFSET_FIFO_C 0x00 e1000e_80003es2lan.h 　
3346
 E1000_KMRNCTRLSTA_OFFSET_INB_CTE1000_KMRNCTRLSTA_OFFSET_INB_CT 0x02 e1000e_80003es2lan.h 　
3347
 E1000_KMRNCTRLSTA_OFFSET_HD_CTRE1000_KMRNCTRLSTA_OFFSET_HD_CTR 0x10 e1000e_80003es2lan.h 　
3348
 E1000_KMRNCTRLSTA_OFFSET_MAC2PHE1000_KMRNCTRLSTA_OFFSET_MAC2PH 0x1F e1000e_80003es2lan.h 　
3349
 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_E1000_KMRNCTRLSTA_FIFO_CTRL_RX_ 0x0008 e1000e_80003es2lan.h 　
3350
 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_E1000_KMRNCTRLSTA_FIFO_CTRL_TX_ 0x0800 e1000e_80003es2lan.h 　
3351
 E1000_KMRNCTRLSTA_INB_CTRL_DIS_E1000_KMRNCTRLSTA_INB_CTRL_DIS_ 0x0010 e1000e_80003es2lan.h 　
3352
 E1000_KMRNCTRLSTA_HD_CTRL_10_10E1000_KMRNCTRLSTA_HD_CTRL_10_10 0x0004 e1000e_80003es2lan.h 　
3353
 E1000_KMRNCTRLSTA_HD_CTRL_1000_E1000_KMRNCTRLSTA_HD_CTRL_1000_ 0x0000 e1000e_80003es2lan.h 　
3354
 E1000_KMRNCTRLSTA_OPMODE_E_IDLEE1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 e1000e_80003es2lan.h 　
3355
 E1000_KMRNCTRLSTA_OPMODE_MASKE1000_KMRNCTRLSTA_OPMODE_MASK 0x000C e1000e_80003es2lan.h 　
3356
 E1000_KMRNCTRLSTA_OPMODE_INBANDE1000_KMRNCTRLSTA_OPMODE_INBAND 0x0004 e1000e_80003es2lan.h 　
3357
 E1000_TCTL_EXT_GCEX_MASKE1000_TCTL_EXT_GCEX_MASK 0x000FFC00 e1000e_80003es2lan.h Gigabit Carry Extend Padding
3358
 DEFAULT_TCTL_EXT_GCEX_80003ES2LDEFAULT_TCTL_EXT_GCEX_80003ES2L 0x00010000 e1000e_80003es2lan.h 　
3359
 DEFAULT_TIPG_IPGT_1000_80003ES2DEFAULT_TIPG_IPGT_1000_80003ES2 0x8 e1000e_80003es2lan.h 　
3360
 DEFAULT_TIPG_IPGT_10_100_80003EDEFAULT_TIPG_IPGT_10_100_80003E 0x9 e1000e_80003es2lan.h 　
3361
 GG82563_PSCR_POLARITY_REVERSAL_GG82563_PSCR_POLARITY_REVERSAL_ 0x0002 e1000e_80003es2lan.h 1=Reversal Disabled
3362
 GG82563_PSCR_CROSSOVER_MODE_MASGG82563_PSCR_CROSSOVER_MODE_MAS 0x0060 e1000e_80003es2lan.h 　
3363
 GG82563_PSCR_CROSSOVER_MODE_MDIGG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 e1000e_80003es2lan.h 00=Manual MDI
3364
 GG82563_PSCR_CROSSOVER_MODE_MDIGG82563_PSCR_CROSSOVER_MODE_MDI 0x0020 e1000e_80003es2lan.h 01=Manual MDIX
3365
 GG82563_PSCR_CROSSOVER_MODE_AUTGG82563_PSCR_CROSSOVER_MODE_AUT 0x0060 e1000e_80003es2lan.h 11=Auto crossover
3366
 GG82563_PSCR2_REVERSE_AUTO_NEGGG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 e1000e_80003es2lan.h 　
3367
 GG82563_MSCR_TX_CLK_MASKGG82563_MSCR_TX_CLK_MASK 0x0007 e1000e_80003es2lan.h 　
3368
 GG82563_MSCR_TX_CLK_10MBPS_2_5GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 e1000e_80003es2lan.h 　
3369
 GG82563_MSCR_TX_CLK_100MBPS_25GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 e1000e_80003es2lan.h 　
3370
 GG82563_MSCR_TX_CLK_1000MBPS_2_GG82563_MSCR_TX_CLK_1000MBPS_2_ 0x0006 e1000e_80003es2lan.h 　
3371
 GG82563_MSCR_TX_CLK_1000MBPS_25GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 e1000e_80003es2lan.h 　
3372
 GG82563_MSCR_ASSERT_CRS_ON_TXGG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 e1000e_80003es2lan.h 1=Assert
3373
 GG82563_DSPD_CABLE_LENGTHGG82563_DSPD_CABLE_LENGTH 0x0007 e1000e_80003es2lan.h 　
3374
 GG82563_KMCR_PASS_FALSE_CARRIERGG82563_KMCR_PASS_FALSE_CARRIER 0x0800 e1000e_80003es2lan.h 　
3375
 GG82563_MAX_KMRN_RETRYGG82563_MAX_KMRN_RETRY 0x5 e1000e_80003es2lan.h 　
3376
 GG82563_PMCR_ENABLE_ELECTRICAL_GG82563_PMCR_ENABLE_ELECTRICAL_ 0x0001 e1000e_80003es2lan.h 　
3377
 GG82563_ICR_DIS_PADDINGGG82563_ICR_DIS_PADDING 0x0010 e1000e_80003es2lan.h Disable Padding
3378
 ID_LED_RESERVED_F746ID_LED_RESERVED_F746 0xF746 e1000e_82571.h 　
3379
 ID_LED_DEFAULT_82573ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_OFF1_ON2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) e1000e_82571.h 　
3380
 E1000_GCR_L1_ACT_WITHOUT_L0S_RXE1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 e1000e_82571.h 　
3381
 E1000_EIAC_82574E1000_EIAC_82574 0x000DC e1000e_82571.h Ext. Interrupt Auto Clear - RW
3382
 E1000_EIAC_MASK_82574E1000_EIAC_MASK_82574 0x01F00000 e1000e_82571.h 　
3383
 E1000_NVM_INIT_CTRL2_MNGME1000_NVM_INIT_CTRL2_MNGM 0x6000 e1000e_82571.h Manageability Operation Mode mask
3384
 E1000_RXCFGLE1000_RXCFGL 0x0B634 e1000e_82571.h TimeSync Rx EtherType & Msg Type Reg - RW
3385
 REQ_TX_DESCRIPTOR_MULTIPLEREQ_TX_DESCRIPTOR_MULTIPLE 8 e1000e_defines.h 　
3386
 REQ_RX_DESCRIPTOR_MULTIPLEREQ_RX_DESCRIPTOR_MULTIPLE 8 e1000e_defines.h 　
3387
 E1000_WUC_APMEE1000_WUC_APME 0x00000001 e1000e_defines.h APM Enable
3388
 E1000_WUC_PME_ENE1000_WUC_PME_EN 0x00000002 e1000e_defines.h PME Enable
3389
 E1000_WUC_PME_STATUSE1000_WUC_PME_STATUS 0x00000004 e1000e_defines.h PME Status
3390
 E1000_WUC_APMPMEE1000_WUC_APMPME 0x00000008 e1000e_defines.h Assert PME on APM Wakeup
3391
 E1000_WUC_LSCWEE1000_WUC_LSCWE 0x00000010 e1000e_defines.h Link Status wake up enable
3392
 E1000_WUC_LSCWOE1000_WUC_LSCWO 0x00000020 e1000e_defines.h Link Status wake up override
3393
 E1000_WUC_SPME1000_WUC_SPM 0x80000000 e1000e_defines.h Enable SPM
3394
 E1000_WUC_PHY_WAKEE1000_WUC_PHY_WAKE 0x00000100 e1000e_defines.h if PHY supports wakeup
3395
 E1000_WUFC_LNKCE1000_WUFC_LNKC 0x00000001 e1000e_defines.h Link Status Change Wakeup Enable
3396
 E1000_WUFC_MAGE1000_WUFC_MAG 0x00000002 e1000e_defines.h Magic Packet Wakeup Enable
3397
 E1000_WUFC_EXE1000_WUFC_EX 0x00000004 e1000e_defines.h Directed Exact Wakeup Enable
3398
 E1000_WUFC_MCE1000_WUFC_MC 0x00000008 e1000e_defines.h Directed Multicast Wakeup Enable
3399
 E1000_WUFC_BCE1000_WUFC_BC 0x00000010 e1000e_defines.h Broadcast Wakeup Enable
3400
 E1000_WUFC_ARPE1000_WUFC_ARP 0x00000020 e1000e_defines.h ARP Request Packet Wakeup Enable
3401
 E1000_WUFC_IPV4E1000_WUFC_IPV4 0x00000040 e1000e_defines.h Directed IPv4 Packet Wakeup Enable
3402
 E1000_WUFC_IPV6E1000_WUFC_IPV6 0x00000080 e1000e_defines.h Directed IPv6 Packet Wakeup Enable
3403
 E1000_WUFC_IGNORE_TCO_PHYE1000_WUFC_IGNORE_TCO_PHY 0x00000800 e1000e_defines.h Ignore WakeOn TCO packets
3404
 E1000_WUFC_FLX0_PHYE1000_WUFC_FLX0_PHY 0x00001000 e1000e_defines.h Flexible Filter 0 Enable
3405
 E1000_WUFC_FLX1_PHYE1000_WUFC_FLX1_PHY 0x00002000 e1000e_defines.h Flexible Filter 1 Enable
3406
 E1000_WUFC_FLX2_PHYE1000_WUFC_FLX2_PHY 0x00004000 e1000e_defines.h Flexible Filter 2 Enable
3407
 E1000_WUFC_FLX3_PHYE1000_WUFC_FLX3_PHY 0x00008000 e1000e_defines.h Flexible Filter 3 Enable
3408
 E1000_WUFC_FLX4_PHYE1000_WUFC_FLX4_PHY 0x00000200 e1000e_defines.h Flexible Filter 4 Enable
3409
 E1000_WUFC_FLX5_PHYE1000_WUFC_FLX5_PHY 0x00000400 e1000e_defines.h Flexible Filter 5 Enable
3410
 E1000_WUFC_IGNORE_TCOE1000_WUFC_IGNORE_TCO 0x00008000 e1000e_defines.h Ignore WakeOn TCO packets
3411
 E1000_WUFC_FLX0E1000_WUFC_FLX0 0x00010000 e1000e_defines.h Flexible Filter 0 Enable
3412
 E1000_WUFC_FLX1E1000_WUFC_FLX1 0x00020000 e1000e_defines.h Flexible Filter 1 Enable
3413
 E1000_WUFC_FLX2E1000_WUFC_FLX2 0x00040000 e1000e_defines.h Flexible Filter 2 Enable
3414
 E1000_WUFC_FLX3E1000_WUFC_FLX3 0x00080000 e1000e_defines.h Flexible Filter 3 Enable
3415
 E1000_WUFC_FLX4E1000_WUFC_FLX4 0x00100000 e1000e_defines.h Flexible Filter 4 Enable
3416
 E1000_WUFC_FLX5E1000_WUFC_FLX5 0x00200000 e1000e_defines.h Flexible Filter 5 Enable
3417
 E1000_WUFC_ALL_FILTERS_PHY_4E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF e1000e_defines.h Mask for all wakeup filters
3418
 E1000_WUFC_FLX_OFFSET_PHYE1000_WUFC_FLX_OFFSET_PHY 12 e1000e_defines.h Offset to the Flexible Filters bits
3419
 E1000_WUFC_FLX_FILTERS_PHY_4E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 e1000e_defines.h Mask for 4 flexible filters
3420
 E1000_WUFC_ALL_FILTERS_PHY_6E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF e1000e_defines.h Mask for 6 wakeup filters
3421
 E1000_WUFC_FLX_FILTERS_PHY_6E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 e1000e_defines.h Mask for 6 flexible filters
3422
 E1000_WUFC_ALL_FILTERSE1000_WUFC_ALL_FILTERS 0x000F00FF e1000e_defines.h Mask for all wakeup filters
3423
 E1000_WUFC_ALL_FILTERS_6E1000_WUFC_ALL_FILTERS_6 0x003F00FF e1000e_defines.h Mask for all 6 wakeup filters
3424
 E1000_WUFC_FLX_OFFSETE1000_WUFC_FLX_OFFSET 16 e1000e_defines.h Offset to the Flexible Filters bits
3425
 E1000_WUFC_FLX_FILTERSE1000_WUFC_FLX_FILTERS 0x000F0000 e1000e_defines.h Mask for the 4 flexible filters
3426
 E1000_WUFC_FLX_FILTERS_6E1000_WUFC_FLX_FILTERS_6 0x003F0000 e1000e_defines.h Mask for 6 flexible filters
3427
 E1000_WUS_LNKCE1000_WUS_LNKC E1000_WUFC_LNKC e1000e_defines.h 　
3428
 E1000_WUS_MAGE1000_WUS_MAG E1000_WUFC_MAG e1000e_defines.h 　
3429
 E1000_WUS_EXE1000_WUS_EX E1000_WUFC_EX e1000e_defines.h 　
3430
 E1000_WUS_MCE1000_WUS_MC E1000_WUFC_MC e1000e_defines.h 　
3431
 E1000_WUS_BCE1000_WUS_BC E1000_WUFC_BC e1000e_defines.h 　
3432
 E1000_WUS_ARPE1000_WUS_ARP E1000_WUFC_ARP e1000e_defines.h 　
3433
 E1000_WUS_IPV4E1000_WUS_IPV4 E1000_WUFC_IPV4 e1000e_defines.h 　
3434
 E1000_WUS_IPV6E1000_WUS_IPV6 E1000_WUFC_IPV6 e1000e_defines.h 　
3435
 E1000_WUS_FLX0_PHYE1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY e1000e_defines.h 　
3436
 E1000_WUS_FLX1_PHYE1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY e1000e_defines.h 　
3437
 E1000_WUS_FLX2_PHYE1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY e1000e_defines.h 　
3438
 E1000_WUS_FLX3_PHYE1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY e1000e_defines.h 　
3439
 E1000_WUS_FLX_FILTERS_PHY_4E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4 e1000e_defines.h 　
3440
 E1000_WUS_FLX0E1000_WUS_FLX0 E1000_WUFC_FLX0 e1000e_defines.h 　
3441
 E1000_WUS_FLX1E1000_WUS_FLX1 E1000_WUFC_FLX1 e1000e_defines.h 　
3442
 E1000_WUS_FLX2E1000_WUS_FLX2 E1000_WUFC_FLX2 e1000e_defines.h 　
3443
 E1000_WUS_FLX3E1000_WUS_FLX3 E1000_WUFC_FLX3 e1000e_defines.h 　
3444
 E1000_WUS_FLX4E1000_WUS_FLX4 E1000_WUFC_FLX4 e1000e_defines.h 　
3445
 E1000_WUS_FLX5E1000_WUS_FLX5 E1000_WUFC_FLX5 e1000e_defines.h 　
3446
 E1000_WUS_FLX4_PHYE1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY e1000e_defines.h 　
3447
 E1000_WUS_FLX5_PHYE1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY e1000e_defines.h 　
3448
 E1000_WUS_FLX_FILTERSE1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS e1000e_defines.h 　
3449
 E1000_WUS_FLX_FILTERS_6E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6 e1000e_defines.h 　
3450
 E1000_WUS_FLX_FILTERS_PHY_6E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6 e1000e_defines.h 　
3451
 E1000_WUPL_LENGTH_MASKE1000_WUPL_LENGTH_MASK 0x0FFF e1000e_defines.h Only the lower 12 bits are valid
3452
 E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 4 e1000e_defines.h 　
3453
 E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 6 e1000e_defines.h 　
3454
 E1000_FLEXIBLE_FILTER_SIZE_MAXE1000_FLEXIBLE_FILTER_SIZE_MAX 128 e1000e_defines.h 　
3455
 E1000_FFLT_SIZEE1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX e1000e_defines.h 　
3456
 E1000_FFLT_SIZE_6E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6 e1000e_defines.h 　
3457
 E1000_FFMT_SIZEE1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000e_defines.h 　
3458
 E1000_FFVT_SIZEE1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000e_defines.h 　
3459
 E1000_CTRL_EXT_GPI0_ENE1000_CTRL_EXT_GPI0_EN 0x00000001 e1000e_defines.h Maps SDP4 to GPI0
3460
 E1000_CTRL_EXT_GPI1_ENE1000_CTRL_EXT_GPI1_EN 0x00000002 e1000e_defines.h Maps SDP5 to GPI1
3461
 E1000_CTRL_EXT_PHYINT_ENE1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN e1000e_defines.h 　
3462
 E1000_CTRL_EXT_GPI2_ENE1000_CTRL_EXT_GPI2_EN 0x00000004 e1000e_defines.h Maps SDP6 to GPI2
3463
 E1000_CTRL_EXT_GPI3_ENE1000_CTRL_EXT_GPI3_EN 0x00000008 e1000e_defines.h Maps SDP7 to GPI3
3464
 E1000_CTRL_EXT_SDP4_DATAE1000_CTRL_EXT_SDP4_DATA 0x00000010 e1000e_defines.h Value of SW Definable Pin 4
3465
 E1000_CTRL_EXT_SDP5_DATAE1000_CTRL_EXT_SDP5_DATA 0x00000020 e1000e_defines.h Value of SW Definable Pin 5
3466
 E1000_CTRL_EXT_PHY_INTE1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA e1000e_defines.h 　
3467
 E1000_CTRL_EXT_SDP6_DATAE1000_CTRL_EXT_SDP6_DATA 0x00000040 e1000e_defines.h Value of SW Definable Pin 6
3468
 E1000_CTRL_EXT_SDP3_DATAE1000_CTRL_EXT_SDP3_DATA 0x00000080 e1000e_defines.h Value of SW Definable Pin 3
3469
 E1000_CTRL_EXT_SDP4_DIRE1000_CTRL_EXT_SDP4_DIR 0x00000100 e1000e_defines.h Direction of SDP4 0=in 1=out
3470
 E1000_CTRL_EXT_SDP5_DIRE1000_CTRL_EXT_SDP5_DIR 0x00000200 e1000e_defines.h Direction of SDP5 0=in 1=out
3471
 E1000_CTRL_EXT_SDP6_DIRE1000_CTRL_EXT_SDP6_DIR 0x00000400 e1000e_defines.h Direction of SDP6 0=in 1=out
3472
 E1000_CTRL_EXT_SDP3_DIRE1000_CTRL_EXT_SDP3_DIR 0x00000800 e1000e_defines.h Direction of SDP3 0=in 1=out
3473
 E1000_CTRL_EXT_ASDCHKE1000_CTRL_EXT_ASDCHK 0x00001000 e1000e_defines.h Initiate an ASD sequence
3474
 E1000_CTRL_EXT_EE_RSTE1000_CTRL_EXT_EE_RST 0x00002000 e1000e_defines.h Reinitialize from EEPROM
3475
 E1000_CTRL_EXT_IPSE1000_CTRL_EXT_IPS 0x00004000 e1000e_defines.h Invert Power State
3476
 E1000_CTRL_EXT_SPD_BYPSE1000_CTRL_EXT_SPD_BYPS 0x00008000 e1000e_defines.h Speed Select Bypass
3477
 E1000_CTRL_EXT_RO_DISE1000_CTRL_EXT_RO_DIS 0x00020000 e1000e_defines.h Relaxed Ordering disable
3478
 E1000_CTRL_EXT_DMA_DYN_CLK_ENE1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 e1000e_defines.h DMA Dynamic Clock Gating
3479
 E1000_CTRL_EXT_LINK_MODE_MASKE1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 e1000e_defines.h 　
3480
 E1000_CTRL_EXT_LINK_MODE_GMIIE1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 e1000e_defines.h 　
3481
 E1000_CTRL_EXT_LINK_MODE_TBIE1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 e1000e_defines.h 　
3482
 E1000_CTRL_EXT_LINK_MODE_KMRNE1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 e1000e_defines.h 　
3483
 E1000_CTRL_EXT_LINK_MODE_PCIE_SE1000_CTRL_EXT_LINK_MODE_PCIE_S 0x00C00000 e1000e_defines.h 　
3484
 E1000_CTRL_EXT_LINK_MODE_PCIX_SE1000_CTRL_EXT_LINK_MODE_PCIX_S 0x00800000 e1000e_defines.h 　
3485
 E1000_CTRL_EXT_LINK_MODE_SGMIIE1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 e1000e_defines.h 　
3486
 E1000_CTRL_EXT_EIAMEE1000_CTRL_EXT_EIAME 0x01000000 e1000e_defines.h 　
3487
 E1000_CTRL_EXT_IRCAE1000_CTRL_EXT_IRCA 0x00000001 e1000e_defines.h 　
3488
 E1000_CTRL_EXT_WR_WMARK_MASKE1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 e1000e_defines.h 　
3489
 E1000_CTRL_EXT_WR_WMARK_256E1000_CTRL_EXT_WR_WMARK_256 0x00000000 e1000e_defines.h 　
3490
 E1000_CTRL_EXT_WR_WMARK_320E1000_CTRL_EXT_WR_WMARK_320 0x01000000 e1000e_defines.h 　
3491
 E1000_CTRL_EXT_WR_WMARK_384E1000_CTRL_EXT_WR_WMARK_384 0x02000000 e1000e_defines.h 　
3492
 E1000_CTRL_EXT_WR_WMARK_448E1000_CTRL_EXT_WR_WMARK_448 0x03000000 e1000e_defines.h 　
3493
 E1000_CTRL_EXT_CANCE1000_CTRL_EXT_CANC 0x04000000 e1000e_defines.h Int delay cancellation
3494
 E1000_CTRL_EXT_DRV_LOADE1000_CTRL_EXT_DRV_LOAD 0x10000000 e1000e_defines.h Driver loaded bit for FW
3495
 E1000_CTRL_EXT_IAMEE1000_CTRL_EXT_IAME 0x08000000 e1000e_defines.h Int acknowledge Auto-mask
3496
 E1000_CRTL_EXT_PB_PARENE1000_CRTL_EXT_PB_PAREN 0x01000000 e1000e_defines.h packet buffer parity error
3497
 E1000_CTRL_EXT_DF_PARENE1000_CTRL_EXT_DF_PAREN 0x02000000 e1000e_defines.h descriptor FIFO parity
3498
 E1000_CTRL_EXT_GHOST_PARENE1000_CTRL_EXT_GHOST_PAREN 0x40000000 e1000e_defines.h 　
3499
 E1000_CTRL_EXT_PBA_CLRE1000_CTRL_EXT_PBA_CLR 0x80000000 e1000e_defines.h PBA Clear
3500
 E1000_CTRL_EXT_LSECCKE1000_CTRL_EXT_LSECCK 0x00001000 e1000e_defines.h 　
3501
 E1000_CTRL_EXT_PHYPDENE1000_CTRL_EXT_PHYPDEN 0x00100000 e1000e_defines.h 　
3502
 E1000_I2CCMD_REG_ADDR_SHIFTE1000_I2CCMD_REG_ADDR_SHIFT 16 e1000e_defines.h 　
3503
 E1000_I2CCMD_REG_ADDRE1000_I2CCMD_REG_ADDR 0x00FF0000 e1000e_defines.h 　
3504
 E1000_I2CCMD_PHY_ADDR_SHIFTE1000_I2CCMD_PHY_ADDR_SHIFT 24 e1000e_defines.h 　
3505
 E1000_I2CCMD_PHY_ADDRE1000_I2CCMD_PHY_ADDR 0x07000000 e1000e_defines.h 　
3506
 E1000_I2CCMD_OPCODE_READE1000_I2CCMD_OPCODE_READ 0x08000000 e1000e_defines.h 　
3507
 E1000_I2CCMD_OPCODE_WRITEE1000_I2CCMD_OPCODE_WRITE 0x00000000 e1000e_defines.h 　
3508
 E1000_I2CCMD_RESETE1000_I2CCMD_RESET 0x10000000 e1000e_defines.h 　
3509
 E1000_I2CCMD_READYE1000_I2CCMD_READY 0x20000000 e1000e_defines.h 　
3510
 E1000_I2CCMD_INTERRUPT_ENAE1000_I2CCMD_INTERRUPT_ENA 0x40000000 e1000e_defines.h 　
3511
 E1000_I2CCMD_ERRORE1000_I2CCMD_ERROR 0x80000000 e1000e_defines.h 　
3512
 E1000_MAX_SGMII_PHY_REG_ADDRE1000_MAX_SGMII_PHY_REG_ADDR 255 e1000e_defines.h 　
3513
 E1000_I2CCMD_PHY_TIMEOUTE1000_I2CCMD_PHY_TIMEOUT 200 e1000e_defines.h 　
3514
 E1000_RXD_STAT_DDE1000_RXD_STAT_DD 0x01 e1000e_defines.h Descriptor Done
3515
 E1000_RXD_STAT_EOPE1000_RXD_STAT_EOP 0x02 e1000e_defines.h End of Packet
3516
 E1000_RXD_STAT_IXSME1000_RXD_STAT_IXSM 0x04 e1000e_defines.h Ignore checksum
3517
 E1000_RXD_STAT_VPE1000_RXD_STAT_VP 0x08 e1000e_defines.h IEEE VLAN Packet
3518
 E1000_RXD_STAT_UDPCSE1000_RXD_STAT_UDPCS 0x10 e1000e_defines.h UDP xsum calculated
3519
 E1000_RXD_STAT_TCPCSE1000_RXD_STAT_TCPCS 0x20 e1000e_defines.h TCP xsum calculated
3520
 E1000_RXD_STAT_IPCSE1000_RXD_STAT_IPCS 0x40 e1000e_defines.h IP xsum calculated
3521
 E1000_RXD_STAT_PIFE1000_RXD_STAT_PIF 0x80 e1000e_defines.h passed in-exact filter
3522
 E1000_RXD_STAT_CRCVE1000_RXD_STAT_CRCV 0x100 e1000e_defines.h Speculative CRC Valid
3523
 E1000_RXD_STAT_IPIDVE1000_RXD_STAT_IPIDV 0x200 e1000e_defines.h IP identification valid
3524
 E1000_RXD_STAT_UDPVE1000_RXD_STAT_UDPV 0x400 e1000e_defines.h Valid UDP checksum
3525
 E1000_RXD_STAT_DYNINTE1000_RXD_STAT_DYNINT 0x800 e1000e_defines.h Pkt caused INT via DYNINT
3526
 E1000_RXD_STAT_ACKE1000_RXD_STAT_ACK 0x8000 e1000e_defines.h ACK Packet indication
3527
 E1000_RXD_ERR_CEE1000_RXD_ERR_CE 0x01 e1000e_defines.h CRC Error
3528
 E1000_RXD_ERR_SEE1000_RXD_ERR_SE 0x02 e1000e_defines.h Symbol Error
3529
 E1000_RXD_ERR_SEQE1000_RXD_ERR_SEQ 0x04 e1000e_defines.h Sequence Error
3530
 E1000_RXD_ERR_CXEE1000_RXD_ERR_CXE 0x10 e1000e_defines.h Carrier Extension Error
3531
 E1000_RXD_ERR_TCPEE1000_RXD_ERR_TCPE 0x20 e1000e_defines.h TCP/UDP Checksum Error
3532
 E1000_RXD_ERR_IPEE1000_RXD_ERR_IPE 0x40 e1000e_defines.h IP Checksum Error
3533
 E1000_RXD_ERR_RXEE1000_RXD_ERR_RXE 0x80 e1000e_defines.h Rx Data Error
3534
 E1000_RXD_SPC_VLAN_MASKE1000_RXD_SPC_VLAN_MASK 0x0FFF e1000e_defines.h VLAN ID is in lower 12 bits
3535
 E1000_RXD_SPC_PRI_MASKE1000_RXD_SPC_PRI_MASK 0xE000 e1000e_defines.h Priority is in upper 3 bits
3536
 E1000_RXD_SPC_PRI_SHIFTE1000_RXD_SPC_PRI_SHIFT 13 e1000e_defines.h 　
3537
 E1000_RXD_SPC_CFI_MASKE1000_RXD_SPC_CFI_MASK 0x1000 e1000e_defines.h CFI is bit 12
3538
 E1000_RXD_SPC_CFI_SHIFTE1000_RXD_SPC_CFI_SHIFT 12 e1000e_defines.h 　
3539
 E1000_RXDEXT_STATERR_CEE1000_RXDEXT_STATERR_CE 0x01000000 e1000e_defines.h 　
3540
 E1000_RXDEXT_STATERR_SEE1000_RXDEXT_STATERR_SE 0x02000000 e1000e_defines.h 　
3541
 E1000_RXDEXT_STATERR_SEQE1000_RXDEXT_STATERR_SEQ 0x04000000 e1000e_defines.h 　
3542
 E1000_RXDEXT_STATERR_CXEE1000_RXDEXT_STATERR_CXE 0x10000000 e1000e_defines.h 　
3543
 E1000_RXDEXT_STATERR_TCPEE1000_RXDEXT_STATERR_TCPE 0x20000000 e1000e_defines.h 　
3544
 E1000_RXDEXT_STATERR_IPEE1000_RXDEXT_STATERR_IPE 0x40000000 e1000e_defines.h 　
3545
 E1000_RXDEXT_STATERR_RXEE1000_RXDEXT_STATERR_RXE 0x80000000 e1000e_defines.h 　
3546
 E1000_RXDEXT_LSECHE1000_RXDEXT_LSECH 0x01000000 e1000e_defines.h 　
3547
 E1000_RXDEXT_LSECE_MASKE1000_RXDEXT_LSECE_MASK 0x60000000 e1000e_defines.h 　
3548
 E1000_RXDEXT_LSECE_NO_ERRORE1000_RXDEXT_LSECE_NO_ERROR 0x00000000 e1000e_defines.h 　
3549
 E1000_RXDEXT_LSECE_NO_SA_MATCHE1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000 e1000e_defines.h 　
3550
 E1000_RXDEXT_LSECE_REPLAY_DETECE1000_RXDEXT_LSECE_REPLAY_DETEC 0x40000000 e1000e_defines.h 　
3551
 E1000_RXDEXT_LSECE_BAD_SIGE1000_RXDEXT_LSECE_BAD_SIG 0x60000000 e1000e_defines.h 　
3552
 E1000_RXD_ERR_FRAME_ERR_MASKE1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ E1000_RXD_ERR_SE | \ E1000_RXD_ERR_SEQ | \ E1000_RXD_ER e1000e_defines.h 　
3553
 E1000_RXDEXT_ERR_FRAME_ERR_MASKE1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_SE | \ E1000_RXDEXT_STATERR_SEQ | \ E10 e1000e_defines.h 　
3554
 E1000_MRQC_ENABLE_MASKE1000_MRQC_ENABLE_MASK 0x00000007 e1000e_defines.h 　
3555
 E1000_MRQC_ENABLE_RSS_2QE1000_MRQC_ENABLE_RSS_2Q 0x00000001 e1000e_defines.h 　
3556
 E1000_MRQC_ENABLE_RSS_INTE1000_MRQC_ENABLE_RSS_INT 0x00000004 e1000e_defines.h 　
3557
 E1000_MRQC_RSS_FIELD_MASKE1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 e1000e_defines.h 　
3558
 E1000_MRQC_RSS_FIELD_IPV4_TCPE1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 e1000e_defines.h 　
3559
 E1000_MRQC_RSS_FIELD_IPV4E1000_MRQC_RSS_FIELD_IPV4 0x00020000 e1000e_defines.h 　
3560
 E1000_MRQC_RSS_FIELD_IPV6_TCP_EE1000_MRQC_RSS_FIELD_IPV6_TCP_E 0x00040000 e1000e_defines.h 　
3561
 E1000_MRQC_RSS_FIELD_IPV6_EXE1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 e1000e_defines.h 　
3562
 E1000_MRQC_RSS_FIELD_IPV6E1000_MRQC_RSS_FIELD_IPV6 0x00100000 e1000e_defines.h 　
3563
 E1000_MRQC_RSS_FIELD_IPV6_TCPE1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 e1000e_defines.h 　
3564
 E1000_RXDPS_HDRSTAT_HDRSPE1000_RXDPS_HDRSTAT_HDRSP 0x00008000 e1000e_defines.h 　
3565
 E1000_RXDPS_HDRSTAT_HDRLEN_MASKE1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF e1000e_defines.h 　
3566
 E1000_MANC_SMBUS_ENE1000_MANC_SMBUS_EN 0x00000001 e1000e_defines.h SMBus Enabled - RO
3567
 E1000_MANC_ASF_ENE1000_MANC_ASF_EN 0x00000002 e1000e_defines.h ASF Enabled - RO
3568
 E1000_MANC_R_ON_FORCEE1000_MANC_R_ON_FORCE 0x00000004 e1000e_defines.h Reset on Force TCO - RO
3569
 E1000_MANC_RMCP_ENE1000_MANC_RMCP_EN 0x00000100 e1000e_defines.h Enable RCMP 026Fh Filtering
3570
 E1000_MANC_0298_ENE1000_MANC_0298_EN 0x00000200 e1000e_defines.h Enable RCMP 0298h Filtering
3571
 E1000_MANC_IPV4_ENE1000_MANC_IPV4_EN 0x00000400 e1000e_defines.h Enable IPv4
3572
 E1000_MANC_IPV6_ENE1000_MANC_IPV6_EN 0x00000800 e1000e_defines.h Enable IPv6
3573
 E1000_MANC_SNAP_ENE1000_MANC_SNAP_EN 0x00001000 e1000e_defines.h Accept LLC/SNAP
3574
 E1000_MANC_ARP_ENE1000_MANC_ARP_EN 0x00002000 e1000e_defines.h Enable ARP Request Filtering
3575
 E1000_MANC_NEIGHBOR_ENE1000_MANC_NEIGHBOR_EN 0x00004000 e1000e_defines.h 　
3576
 E1000_MANC_ARP_RES_ENE1000_MANC_ARP_RES_EN 0x00008000 e1000e_defines.h Enable ARP response Filtering
3577
 E1000_MANC_TCO_RESETE1000_MANC_TCO_RESET 0x00010000 e1000e_defines.h TCO Reset Occurred
3578
 E1000_MANC_RCV_TCO_ENE1000_MANC_RCV_TCO_EN 0x00020000 e1000e_defines.h Receive TCO Packets Enabled
3579
 E1000_MANC_REPORT_STATUSE1000_MANC_REPORT_STATUS 0x00040000 e1000e_defines.h Status Reporting Enabled
3580
 E1000_MANC_RCV_ALLE1000_MANC_RCV_ALL 0x00080000 e1000e_defines.h Receive All Enabled
3581
 E1000_MANC_BLK_PHY_RST_ON_IDEE1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 e1000e_defines.h Block phy resets
3582
 E1000_MANC_EN_MAC_ADDR_FILTERE1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 e1000e_defines.h 　
3583
 E1000_MANC_EN_MNG2HOSTE1000_MANC_EN_MNG2HOST 0x00200000 e1000e_defines.h 　
3584
 E1000_MANC_EN_IP_ADDR_FILTERE1000_MANC_EN_IP_ADDR_FILTER 0x00400000 e1000e_defines.h 　
3585
 E1000_MANC_EN_XSUM_FILTERE1000_MANC_EN_XSUM_FILTER 0x00800000 e1000e_defines.h Enable checksum filtering
3586
 E1000_MANC_BR_ENE1000_MANC_BR_EN 0x01000000 e1000e_defines.h Enable broadcast filtering
3587
 E1000_MANC_SMB_REQE1000_MANC_SMB_REQ 0x01000000 e1000e_defines.h SMBus Request
3588
 E1000_MANC_SMB_GNTE1000_MANC_SMB_GNT 0x02000000 e1000e_defines.h SMBus Grant
3589
 E1000_MANC_SMB_CLK_INE1000_MANC_SMB_CLK_IN 0x04000000 e1000e_defines.h SMBus Clock In
3590
 E1000_MANC_SMB_DATA_INE1000_MANC_SMB_DATA_IN 0x08000000 e1000e_defines.h SMBus Data In
3591
 E1000_MANC_SMB_DATA_OUTE1000_MANC_SMB_DATA_OUT 0x10000000 e1000e_defines.h SMBus Data Out
3592
 E1000_MANC_SMB_CLK_OUTE1000_MANC_SMB_CLK_OUT 0x20000000 e1000e_defines.h SMBus Clock Out
3593
 E1000_MANC_SMB_DATA_OUT_SHIFTE1000_MANC_SMB_DATA_OUT_SHIFT 28 e1000e_defines.h SMBus Data Out Shift
3594
 E1000_MANC_SMB_CLK_OUT_SHIFTE1000_MANC_SMB_CLK_OUT_SHIFT 29 e1000e_defines.h SMBus Clock Out Shift
3595
 E1000_RCTL_RSTE1000_RCTL_RST 0x00000001 e1000e_defines.h Software reset
3596
 E1000_RCTL_ENE1000_RCTL_EN 0x00000002 e1000e_defines.h enable
3597
 E1000_RCTL_SBPE1000_RCTL_SBP 0x00000004 e1000e_defines.h store bad packet
3598
 E1000_RCTL_UPEE1000_RCTL_UPE 0x00000008 e1000e_defines.h unicast promisc enable
3599
 E1000_RCTL_MPEE1000_RCTL_MPE 0x00000010 e1000e_defines.h multicast promisc enable
3600
 E1000_RCTL_LPEE1000_RCTL_LPE 0x00000020 e1000e_defines.h long packet enable
3601
 E1000_RCTL_LBM_NOE1000_RCTL_LBM_NO 0x00000000 e1000e_defines.h no loopback mode
3602
 E1000_RCTL_LBM_MACE1000_RCTL_LBM_MAC 0x00000040 e1000e_defines.h MAC loopback mode
3603
 E1000_RCTL_LBM_SLPE1000_RCTL_LBM_SLP 0x00000080 e1000e_defines.h serial link loopback mode
3604
 E1000_RCTL_LBM_TCVRE1000_RCTL_LBM_TCVR 0x000000C0 e1000e_defines.h tcvr loopback mode
3605
 E1000_RCTL_DTYP_MASKE1000_RCTL_DTYP_MASK 0x00000C00 e1000e_defines.h Descriptor type mask
3606
 E1000_RCTL_DTYP_PSE1000_RCTL_DTYP_PS 0x00000400 e1000e_defines.h Packet Split descriptor
3607
 E1000_RCTL_RDMTS_HALFE1000_RCTL_RDMTS_HALF 0x00000000 e1000e_defines.h rx desc min thresh size
3608
 E1000_RCTL_RDMTS_QUATE1000_RCTL_RDMTS_QUAT 0x00000100 e1000e_defines.h rx desc min thresh size
3609
 E1000_RCTL_RDMTS_EIGTHE1000_RCTL_RDMTS_EIGTH 0x00000200 e1000e_defines.h rx desc min thresh size
3610
 E1000_RCTL_MO_SHIFTE1000_RCTL_MO_SHIFT 12 e1000e_defines.h multicast offset shift
3611
 E1000_RCTL_MO_0E1000_RCTL_MO_0 0x00000000 e1000e_defines.h multicast offset 11:0
3612
 E1000_RCTL_MO_1E1000_RCTL_MO_1 0x00001000 e1000e_defines.h multicast offset 12:1
3613
 E1000_RCTL_MO_2E1000_RCTL_MO_2 0x00002000 e1000e_defines.h multicast offset 13:2
3614
 E1000_RCTL_MO_3E1000_RCTL_MO_3 0x00003000 e1000e_defines.h multicast offset 15:4
3615
 E1000_RCTL_MDRE1000_RCTL_MDR 0x00004000 e1000e_defines.h multicast desc ring 0
3616
 E1000_RCTL_BAME1000_RCTL_BAM 0x00008000 e1000e_defines.h broadcast enable
3617
 E1000_RCTL_SZ_2048E1000_RCTL_SZ_2048 0x00000000 e1000e_defines.h rx buffer size 2048
3618
 E1000_RCTL_SZ_1024E1000_RCTL_SZ_1024 0x00010000 e1000e_defines.h rx buffer size 1024
3619
 E1000_RCTL_SZ_512E1000_RCTL_SZ_512 0x00020000 e1000e_defines.h rx buffer size 512
3620
 E1000_RCTL_SZ_256E1000_RCTL_SZ_256 0x00030000 e1000e_defines.h rx buffer size 256
3621
 E1000_RCTL_SZ_16384E1000_RCTL_SZ_16384 0x00010000 e1000e_defines.h rx buffer size 16384
3622
 E1000_RCTL_SZ_8192E1000_RCTL_SZ_8192 0x00020000 e1000e_defines.h rx buffer size 8192
3623
 E1000_RCTL_SZ_4096E1000_RCTL_SZ_4096 0x00030000 e1000e_defines.h rx buffer size 4096
3624
 E1000_RCTL_VFEE1000_RCTL_VFE 0x00040000 e1000e_defines.h vlan filter enable
3625
 E1000_RCTL_CFIENE1000_RCTL_CFIEN 0x00080000 e1000e_defines.h canonical form enable
3626
 E1000_RCTL_CFIE1000_RCTL_CFI 0x00100000 e1000e_defines.h canonical form indicator
3627
 E1000_RCTL_DPFE1000_RCTL_DPF 0x00400000 e1000e_defines.h discard pause frames
3628
 E1000_RCTL_PMCFE1000_RCTL_PMCF 0x00800000 e1000e_defines.h pass MAC control frames
3629
 E1000_RCTL_BSEXE1000_RCTL_BSEX 0x02000000 e1000e_defines.h Buffer size extension
3630
 E1000_RCTL_SECRCE1000_RCTL_SECRC 0x04000000 e1000e_defines.h Strip Ethernet CRC
3631
 E1000_RCTL_FLXBUF_MASKE1000_RCTL_FLXBUF_MASK 0x78000000 e1000e_defines.h Flexible buffer size
3632
 E1000_RCTL_FLXBUF_SHIFTE1000_RCTL_FLXBUF_SHIFT 27 e1000e_defines.h Flexible buffer shift
3633
 E1000_PSRCTL_BSIZE0_MASKE1000_PSRCTL_BSIZE0_MASK 0x0000007F e1000e_defines.h 　
3634
 E1000_PSRCTL_BSIZE1_MASKE1000_PSRCTL_BSIZE1_MASK 0x00003F00 e1000e_defines.h 　
3635
 E1000_PSRCTL_BSIZE2_MASKE1000_PSRCTL_BSIZE2_MASK 0x003F0000 e1000e_defines.h 　
3636
 E1000_PSRCTL_BSIZE3_MASKE1000_PSRCTL_BSIZE3_MASK 0x3F000000 e1000e_defines.h 　
3637
 E1000_PSRCTL_BSIZE0_SHIFTE1000_PSRCTL_BSIZE0_SHIFT 7 e1000e_defines.h Shift _right_ 7
3638
 E1000_PSRCTL_BSIZE1_SHIFTE1000_PSRCTL_BSIZE1_SHIFT 2 e1000e_defines.h Shift _right_ 2
3639
 E1000_PSRCTL_BSIZE2_SHIFTE1000_PSRCTL_BSIZE2_SHIFT 6 e1000e_defines.h Shift _left_ 6
3640
 E1000_PSRCTL_BSIZE3_SHIFTE1000_PSRCTL_BSIZE3_SHIFT 14 e1000e_defines.h Shift _left_ 14
3641
 E1000_SWFW_EEP_SME1000_SWFW_EEP_SM 0x01 e1000e_defines.h 　
3642
 E1000_SWFW_PHY0_SME1000_SWFW_PHY0_SM 0x02 e1000e_defines.h 　
3643
 E1000_SWFW_PHY1_SME1000_SWFW_PHY1_SM 0x04 e1000e_defines.h 　
3644
 E1000_SWFW_CSR_SME1000_SWFW_CSR_SM 0x08 e1000e_defines.h 　
3645
 E1000_FACTPS_LFSE1000_FACTPS_LFS 0x40000000 e1000e_defines.h LAN Function Select
3646
 E1000_CTRL_FDE1000_CTRL_FD 0x00000001 e1000e_defines.h Full duplex.0=half; 1=full
3647
 E1000_CTRL_BEME1000_CTRL_BEM 0x00000002 e1000e_defines.h Endian Mode.0=little,1=big
3648
 E1000_CTRL_PRIORE1000_CTRL_PRIOR 0x00000004 e1000e_defines.h Priority on PCI. 0=rx,1=fair
3649
 E1000_CTRL_GIO_MASTER_DISABLEE1000_CTRL_GIO_MASTER_DISABLE 0x00000004 e1000e_defines.h Blocks new Master reqs
3650
 E1000_CTRL_LRSTE1000_CTRL_LRST 0x00000008 e1000e_defines.h Link reset. 0=normal,1=reset
3651
 E1000_CTRL_TMEE1000_CTRL_TME 0x00000010 e1000e_defines.h Test mode. 0=normal,1=test
3652
 E1000_CTRL_SLEE1000_CTRL_SLE 0x00000020 e1000e_defines.h Serial Link on 0=dis,1=en
3653
 E1000_CTRL_ASDEE1000_CTRL_ASDE 0x00000020 e1000e_defines.h Auto-speed detect enable
3654
 E1000_CTRL_SLUE1000_CTRL_SLU 0x00000040 e1000e_defines.h Set link up (Force Link)
3655
 E1000_CTRL_ILOSE1000_CTRL_ILOS 0x00000080 e1000e_defines.h Invert Loss-Of Signal
3656
 E1000_CTRL_SPD_SELE1000_CTRL_SPD_SEL 0x00000300 e1000e_defines.h Speed Select Mask
3657
 E1000_CTRL_SPD_10E1000_CTRL_SPD_10 0x00000000 e1000e_defines.h Force 10Mb
3658
 E1000_CTRL_SPD_100E1000_CTRL_SPD_100 0x00000100 e1000e_defines.h Force 100Mb
3659
 E1000_CTRL_SPD_1000E1000_CTRL_SPD_1000 0x00000200 e1000e_defines.h Force 1Gb
3660
 E1000_CTRL_BEM32E1000_CTRL_BEM32 0x00000400 e1000e_defines.h Big Endian 32 mode
3661
 E1000_CTRL_FRCSPDE1000_CTRL_FRCSPD 0x00000800 e1000e_defines.h Force Speed
3662
 E1000_CTRL_FRCDPXE1000_CTRL_FRCDPX 0x00001000 e1000e_defines.h Force Duplex
3663
 E1000_CTRL_D_UD_ENE1000_CTRL_D_UD_EN 0x00002000 e1000e_defines.h Dock/Undock enable
3664
 E1000_CTRL_D_UD_POLARITYE1000_CTRL_D_UD_POLARITY 0x00004000 e1000e_defines.h Defined polarity of Dock/Undock
3665
 E1000_CTRL_FORCE_PHY_RESETE1000_CTRL_FORCE_PHY_RESET 0x00008000 e1000e_defines.h Reset both PHY ports, through
3666
 E1000_CTRL_EXT_LINK_ENE1000_CTRL_EXT_LINK_EN 0x00010000 e1000e_defines.h enable link status from external
3667
 E1000_CTRL_SWDPIN0E1000_CTRL_SWDPIN0 0x00040000 e1000e_defines.h SWDPIN 0 value
3668
 E1000_CTRL_SWDPIN1E1000_CTRL_SWDPIN1 0x00080000 e1000e_defines.h SWDPIN 1 value
3669
 E1000_CTRL_SWDPIN2E1000_CTRL_SWDPIN2 0x00100000 e1000e_defines.h SWDPIN 2 value
3670
 E1000_CTRL_SWDPIN3E1000_CTRL_SWDPIN3 0x00200000 e1000e_defines.h SWDPIN 3 value
3671
 E1000_CTRL_SWDPIO0E1000_CTRL_SWDPIO0 0x00400000 e1000e_defines.h SWDPIN 0 Input or output
3672
 E1000_CTRL_SWDPIO1E1000_CTRL_SWDPIO1 0x00800000 e1000e_defines.h SWDPIN 1 input or output
3673
 E1000_CTRL_SWDPIO2E1000_CTRL_SWDPIO2 0x01000000 e1000e_defines.h SWDPIN 2 input or output
3674
 E1000_CTRL_SWDPIO3E1000_CTRL_SWDPIO3 0x02000000 e1000e_defines.h SWDPIN 3 input or output
3675
 E1000_CTRL_RSTE1000_CTRL_RST 0x04000000 e1000e_defines.h Global reset
3676
 E1000_CTRL_RFCEE1000_CTRL_RFCE 0x08000000 e1000e_defines.h Receive Flow Control enable
3677
 E1000_CTRL_TFCEE1000_CTRL_TFCE 0x10000000 e1000e_defines.h Transmit flow control enable
3678
 E1000_CTRL_RTEE1000_CTRL_RTE 0x20000000 e1000e_defines.h Routing tag enable
3679
 E1000_CTRL_VMEE1000_CTRL_VME 0x40000000 e1000e_defines.h IEEE VLAN mode enable
3680
 E1000_CTRL_PHY_RSTE1000_CTRL_PHY_RST 0x80000000 e1000e_defines.h PHY Reset
3681
 E1000_CTRL_SW2FW_INTE1000_CTRL_SW2FW_INT 0x02000000 e1000e_defines.h Initiate an interrupt to ME
3682
 E1000_CTRL_I2C_ENAE1000_CTRL_I2C_ENA 0x02000000 e1000e_defines.h I2C enable
3683
 E1000_CTRL_PHY_RESET_DIRE1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 e1000e_defines.h 　
3684
 E1000_CTRL_PHY_RESETE1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 e1000e_defines.h 　
3685
 E1000_CTRL_MDIO_DIRE1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 e1000e_defines.h 　
3686
 E1000_CTRL_MDIOE1000_CTRL_MDIO E1000_CTRL_SWDPIN2 e1000e_defines.h 　
3687
 E1000_CTRL_MDC_DIRE1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 e1000e_defines.h 　
3688
 E1000_CTRL_MDCE1000_CTRL_MDC E1000_CTRL_SWDPIN3 e1000e_defines.h 　
3689
 E1000_CTRL_PHY_RESET_DIR4E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR e1000e_defines.h 　
3690
 E1000_CTRL_PHY_RESET4E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA e1000e_defines.h 　
3691
 E1000_CONNSW_ENRGSRCE1000_CONNSW_ENRGSRC 0x4 e1000e_defines.h 　
3692
 E1000_PCS_CFG_PCS_ENE1000_PCS_CFG_PCS_EN 8 e1000e_defines.h 　
3693
 E1000_PCS_LCTL_FLV_LINK_UPE1000_PCS_LCTL_FLV_LINK_UP 1 e1000e_defines.h 　
3694
 E1000_PCS_LCTL_FSV_10E1000_PCS_LCTL_FSV_10 0 e1000e_defines.h 　
3695
 E1000_PCS_LCTL_FSV_100E1000_PCS_LCTL_FSV_100 2 e1000e_defines.h 　
3696
 E1000_PCS_LCTL_FSV_1000E1000_PCS_LCTL_FSV_1000 4 e1000e_defines.h 　
3697
 E1000_PCS_LCTL_FDV_FULLE1000_PCS_LCTL_FDV_FULL 8 e1000e_defines.h 　
3698
 E1000_PCS_LCTL_FSDE1000_PCS_LCTL_FSD 0x10 e1000e_defines.h 　
3699
 E1000_PCS_LCTL_FORCE_LINKE1000_PCS_LCTL_FORCE_LINK 0x20 e1000e_defines.h 　
3700
 E1000_PCS_LCTL_LOW_LINK_LATCHE1000_PCS_LCTL_LOW_LINK_LATCH 0x40 e1000e_defines.h 　
3701
 E1000_PCS_LCTL_FORCE_FCTRLE1000_PCS_LCTL_FORCE_FCTRL 0x80 e1000e_defines.h 　
3702
 E1000_PCS_LCTL_AN_ENABLEE1000_PCS_LCTL_AN_ENABLE 0x10000 e1000e_defines.h 　
3703
 E1000_PCS_LCTL_AN_RESTARTE1000_PCS_LCTL_AN_RESTART 0x20000 e1000e_defines.h 　
3704
 E1000_PCS_LCTL_AN_TIMEOUTE1000_PCS_LCTL_AN_TIMEOUT 0x40000 e1000e_defines.h 　
3705
 E1000_PCS_LCTL_AN_SGMII_BYPASSE1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 e1000e_defines.h 　
3706
 E1000_PCS_LCTL_AN_SGMII_TRIGGERE1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 e1000e_defines.h 　
3707
 E1000_PCS_LCTL_FAST_LINK_TIMERE1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 e1000e_defines.h 　
3708
 E1000_PCS_LCTL_LINK_OK_FIXE1000_PCS_LCTL_LINK_OK_FIX 0x2000000 e1000e_defines.h 　
3709
 E1000_PCS_LCTL_CRS_ON_NIE1000_PCS_LCTL_CRS_ON_NI 0x4000000 e1000e_defines.h 　
3710
 E1000_ENABLE_SERDES_LOOPBACKE1000_ENABLE_SERDES_LOOPBACK 0x0410 e1000e_defines.h 　
3711
 E1000_PCS_LSTS_LINK_OKE1000_PCS_LSTS_LINK_OK 1 e1000e_defines.h 　
3712
 E1000_PCS_LSTS_SPEED_10E1000_PCS_LSTS_SPEED_10 0 e1000e_defines.h 　
3713
 E1000_PCS_LSTS_SPEED_100E1000_PCS_LSTS_SPEED_100 2 e1000e_defines.h 　
3714
 E1000_PCS_LSTS_SPEED_1000E1000_PCS_LSTS_SPEED_1000 4 e1000e_defines.h 　
3715
 E1000_PCS_LSTS_DUPLEX_FULLE1000_PCS_LSTS_DUPLEX_FULL 8 e1000e_defines.h 　
3716
 E1000_PCS_LSTS_SYNK_OKE1000_PCS_LSTS_SYNK_OK 0x10 e1000e_defines.h 　
3717
 E1000_PCS_LSTS_AN_COMPLETEE1000_PCS_LSTS_AN_COMPLETE 0x10000 e1000e_defines.h 　
3718
 E1000_PCS_LSTS_AN_PAGE_RXE1000_PCS_LSTS_AN_PAGE_RX 0x20000 e1000e_defines.h 　
3719
 E1000_PCS_LSTS_AN_TIMED_OUTE1000_PCS_LSTS_AN_TIMED_OUT 0x40000 e1000e_defines.h 　
3720
 E1000_PCS_LSTS_AN_REMOTE_FAULTE1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 e1000e_defines.h 　
3721
 E1000_PCS_LSTS_AN_ERROR_RWSE1000_PCS_LSTS_AN_ERROR_RWS 0x100000 e1000e_defines.h 　
3722
 E1000_STATUS_FDE1000_STATUS_FD 0x00000001 e1000e_defines.h Full duplex.0=half,1=full
3723
 E1000_STATUS_LUE1000_STATUS_LU 0x00000002 e1000e_defines.h Link up.0=no,1=link
3724
 E1000_STATUS_FUNC_MASKE1000_STATUS_FUNC_MASK 0x0000000C e1000e_defines.h PCI Function Mask
3725
 E1000_STATUS_FUNC_SHIFTE1000_STATUS_FUNC_SHIFT 2 e1000e_defines.h 　
3726
 E1000_STATUS_FUNC_0E1000_STATUS_FUNC_0 0x00000000 e1000e_defines.h Function 0
3727
 E1000_STATUS_FUNC_1E1000_STATUS_FUNC_1 0x00000004 e1000e_defines.h Function 1
3728
 E1000_STATUS_TXOFFE1000_STATUS_TXOFF 0x00000010 e1000e_defines.h transmission paused
3729
 E1000_STATUS_TBIMODEE1000_STATUS_TBIMODE 0x00000020 e1000e_defines.h TBI mode
3730
 E1000_STATUS_SPEED_MASKE1000_STATUS_SPEED_MASK 0x000000C0 e1000e_defines.h 　
3731
 E1000_STATUS_SPEED_10E1000_STATUS_SPEED_10 0x00000000 e1000e_defines.h Speed 10Mb/s
3732
 E1000_STATUS_SPEED_100E1000_STATUS_SPEED_100 0x00000040 e1000e_defines.h Speed 100Mb/s
3733
 E1000_STATUS_SPEED_1000E1000_STATUS_SPEED_1000 0x00000080 e1000e_defines.h Speed 1000Mb/s
3734
 E1000_STATUS_LAN_INIT_DONEE1000_STATUS_LAN_INIT_DONE 0x00000200 e1000e_defines.h Lan Init Completion by NVM
3735
 E1000_STATUS_ASDVE1000_STATUS_ASDV 0x00000300 e1000e_defines.h Auto speed detect value
3736
 E1000_STATUS_PHYRAE1000_STATUS_PHYRA 0x00000400 e1000e_defines.h PHY Reset Asserted
3737
 E1000_STATUS_DOCK_CIE1000_STATUS_DOCK_CI 0x00000800 e1000e_defines.h Change in Dock/Undock state.
3738
 E1000_STATUS_GIO_MASTER_ENABLEE1000_STATUS_GIO_MASTER_ENABLE 0x00080000 e1000e_defines.h Master request status
3739
 E1000_STATUS_MTXCKOKE1000_STATUS_MTXCKOK 0x00000400 e1000e_defines.h MTX clock running OK
3740
 E1000_STATUS_PCI66E1000_STATUS_PCI66 0x00000800 e1000e_defines.h In 66Mhz slot
3741
 E1000_STATUS_BUS64E1000_STATUS_BUS64 0x00001000 e1000e_defines.h In 64 bit slot
3742
 E1000_STATUS_PCIX_MODEE1000_STATUS_PCIX_MODE 0x00002000 e1000e_defines.h PCI-X mode
3743
 E1000_STATUS_PCIX_SPEEDE1000_STATUS_PCIX_SPEED 0x0000C000 e1000e_defines.h PCI-X bus speed
3744
 E1000_STATUS_BMC_SKU_0E1000_STATUS_BMC_SKU_0 0x00100000 e1000e_defines.h BMC USB redirect disabled
3745
 E1000_STATUS_BMC_SKU_1E1000_STATUS_BMC_SKU_1 0x00200000 e1000e_defines.h BMC SRAM disabled
3746
 E1000_STATUS_BMC_SKU_2E1000_STATUS_BMC_SKU_2 0x00400000 e1000e_defines.h BMC SDRAM disabled
3747
 E1000_STATUS_BMC_CRYPTOE1000_STATUS_BMC_CRYPTO 0x00800000 e1000e_defines.h BMC crypto disabled
3748
 E1000_STATUS_BMC_LITEE1000_STATUS_BMC_LITE 0x01000000 e1000e_defines.h BMC external code execution
3749
 E1000_STATUS_RGMII_ENABLEE1000_STATUS_RGMII_ENABLE 0x02000000 e1000e_defines.h RGMII disabled
3750
 E1000_STATUS_FUSE_8E1000_STATUS_FUSE_8 0x04000000 e1000e_defines.h 　
3751
 E1000_STATUS_FUSE_9E1000_STATUS_FUSE_9 0x08000000 e1000e_defines.h 　
3752
 E1000_STATUS_SERDES0_DISE1000_STATUS_SERDES0_DIS 0x10000000 e1000e_defines.h SERDES disabled on port 0
3753
 E1000_STATUS_SERDES1_DISE1000_STATUS_SERDES1_DIS 0x20000000 e1000e_defines.h SERDES disabled on port 1
3754
 E1000_STATUS_PCIX_SPEED_66E1000_STATUS_PCIX_SPEED_66 0x00000000 e1000e_defines.h PCI-X bus speed 50-66 MHz
3755
 E1000_STATUS_PCIX_SPEED_100E1000_STATUS_PCIX_SPEED_100 0x00004000 e1000e_defines.h PCI-X bus speed 66-100 MHz
3756
 E1000_STATUS_PCIX_SPEED_133E1000_STATUS_PCIX_SPEED_133 0x00008000 e1000e_defines.h PCI-X bus speed 100-133 MHz
3757
 SPEED_10SPEED_10 10 e1000e_defines.h 　
3758
 SPEED_100SPEED_100 100 e1000e_defines.h 　
3759
 SPEED_1000SPEED_1000 1000 e1000e_defines.h 　
3760
 HALF_DUPLEXHALF_DUPLEX 1 e1000e_defines.h 　
3761
 FULL_DUPLEXFULL_DUPLEX 2 e1000e_defines.h 　
3762
 PHY_FORCE_TIMEPHY_FORCE_TIME 20 e1000e_defines.h 　
3763
 ADVERTISE_10_HALFADVERTISE_10_HALF 0x0001 e1000e_defines.h 　
3764
 ADVERTISE_10_FULLADVERTISE_10_FULL 0x0002 e1000e_defines.h 　
3765
 ADVERTISE_100_HALFADVERTISE_100_HALF 0x0004 e1000e_defines.h 　
3766
 ADVERTISE_100_FULLADVERTISE_100_FULL 0x0008 e1000e_defines.h 　
3767
 ADVERTISE_1000_HALFADVERTISE_1000_HALF 0x0010 e1000e_defines.h Not used, just FYI
3768
 ADVERTISE_1000_FULLADVERTISE_1000_FULL 0x0020 e1000e_defines.h 　
3769
 E1000_ALL_SPEED_DUPLEXE1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) e1000e_defines.h 　
3770
 E1000_ALL_NOT_GIGE1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL) e1000e_defines.h 　
3771
 E1000_ALL_100_SPEEDE1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) e1000e_defines.h 　
3772
 E1000_ALL_10_SPEEDE1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) e1000e_defines.h 　
3773
 E1000_ALL_FULL_DUPLEXE1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) e1000e_defines.h 　
3774
 E1000_ALL_HALF_DUPLEXE1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) e1000e_defines.h 　
3775
 AUTONEG_ADVERTISE_SPEED_DEFAULTAUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX e1000e_defines.h 　
3776
 E1000_PHY_LED0_MODE_MASKE1000_PHY_LED0_MODE_MASK 0x00000007 e1000e_defines.h 　
3777
 E1000_PHY_LED0_IVRTE1000_PHY_LED0_IVRT 0x00000008 e1000e_defines.h 　
3778
 E1000_PHY_LED0_BLINKE1000_PHY_LED0_BLINK 0x00000010 e1000e_defines.h 　
3779
 E1000_PHY_LED0_MASKE1000_PHY_LED0_MASK 0x0000001F e1000e_defines.h 　
3780
 E1000_LEDCTL_LED0_MODE_MASKE1000_LEDCTL_LED0_MODE_MASK 0x0000000F e1000e_defines.h 　
3781
 E1000_LEDCTL_LED0_MODE_SHIFTE1000_LEDCTL_LED0_MODE_SHIFT 0 e1000e_defines.h 　
3782
 E1000_LEDCTL_LED0_BLINK_RATEE1000_LEDCTL_LED0_BLINK_RATE 0x00000020 e1000e_defines.h 　
3783
 E1000_LEDCTL_LED0_IVRTE1000_LEDCTL_LED0_IVRT 0x00000040 e1000e_defines.h 　
3784
 E1000_LEDCTL_LED0_BLINKE1000_LEDCTL_LED0_BLINK 0x00000080 e1000e_defines.h 　
3785
 E1000_LEDCTL_LED1_MODE_MASKE1000_LEDCTL_LED1_MODE_MASK 0x00000F00 e1000e_defines.h 　
3786
 E1000_LEDCTL_LED1_MODE_SHIFTE1000_LEDCTL_LED1_MODE_SHIFT 8 e1000e_defines.h 　
3787
 E1000_LEDCTL_LED1_BLINK_RATEE1000_LEDCTL_LED1_BLINK_RATE 0x00002000 e1000e_defines.h 　
3788
 E1000_LEDCTL_LED1_IVRTE1000_LEDCTL_LED1_IVRT 0x00004000 e1000e_defines.h 　
3789
 E1000_LEDCTL_LED1_BLINKE1000_LEDCTL_LED1_BLINK 0x00008000 e1000e_defines.h 　
3790
 E1000_LEDCTL_LED2_MODE_MASKE1000_LEDCTL_LED2_MODE_MASK 0x000F0000 e1000e_defines.h 　
3791
 E1000_LEDCTL_LED2_MODE_SHIFTE1000_LEDCTL_LED2_MODE_SHIFT 16 e1000e_defines.h 　
3792
 E1000_LEDCTL_LED2_BLINK_RATEE1000_LEDCTL_LED2_BLINK_RATE 0x00200000 e1000e_defines.h 　
3793
 E1000_LEDCTL_LED2_IVRTE1000_LEDCTL_LED2_IVRT 0x00400000 e1000e_defines.h 　
3794
 E1000_LEDCTL_LED2_BLINKE1000_LEDCTL_LED2_BLINK 0x00800000 e1000e_defines.h 　
3795
 E1000_LEDCTL_LED3_MODE_MASKE1000_LEDCTL_LED3_MODE_MASK 0x0F000000 e1000e_defines.h 　
3796
 E1000_LEDCTL_LED3_MODE_SHIFTE1000_LEDCTL_LED3_MODE_SHIFT 24 e1000e_defines.h 　
3797
 E1000_LEDCTL_LED3_BLINK_RATEE1000_LEDCTL_LED3_BLINK_RATE 0x20000000 e1000e_defines.h 　
3798
 E1000_LEDCTL_LED3_IVRTE1000_LEDCTL_LED3_IVRT 0x40000000 e1000e_defines.h 　
3799
 E1000_LEDCTL_LED3_BLINKE1000_LEDCTL_LED3_BLINK 0x80000000 e1000e_defines.h 　
3800
 E1000_LEDCTL_MODE_LINK_10_1000E1000_LEDCTL_MODE_LINK_10_1000 0x0 e1000e_defines.h 　
3801
 E1000_LEDCTL_MODE_LINK_100_1000E1000_LEDCTL_MODE_LINK_100_1000 0x1 e1000e_defines.h 　
3802
 E1000_LEDCTL_MODE_LINK_UPE1000_LEDCTL_MODE_LINK_UP 0x2 e1000e_defines.h 　
3803
 E1000_LEDCTL_MODE_ACTIVITYE1000_LEDCTL_MODE_ACTIVITY 0x3 e1000e_defines.h 　
3804
 E1000_LEDCTL_MODE_LINK_ACTIVITYE1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 e1000e_defines.h 　
3805
 E1000_LEDCTL_MODE_LINK_10E1000_LEDCTL_MODE_LINK_10 0x5 e1000e_defines.h 　
3806
 E1000_LEDCTL_MODE_LINK_100E1000_LEDCTL_MODE_LINK_100 0x6 e1000e_defines.h 　
3807
 E1000_LEDCTL_MODE_LINK_1000E1000_LEDCTL_MODE_LINK_1000 0x7 e1000e_defines.h 　
3808
 E1000_LEDCTL_MODE_PCIX_MODEE1000_LEDCTL_MODE_PCIX_MODE 0x8 e1000e_defines.h 　
3809
 E1000_LEDCTL_MODE_FULL_DUPLEXE1000_LEDCTL_MODE_FULL_DUPLEX 0x9 e1000e_defines.h 　
3810
 E1000_LEDCTL_MODE_COLLISIONE1000_LEDCTL_MODE_COLLISION 0xA e1000e_defines.h 　
3811
 E1000_LEDCTL_MODE_BUS_SPEEDE1000_LEDCTL_MODE_BUS_SPEED 0xB e1000e_defines.h 　
3812
 E1000_LEDCTL_MODE_BUS_SIZEE1000_LEDCTL_MODE_BUS_SIZE 0xC e1000e_defines.h 　
3813
 E1000_LEDCTL_MODE_PAUSEDE1000_LEDCTL_MODE_PAUSED 0xD e1000e_defines.h 　
3814
 E1000_LEDCTL_MODE_LED_ONE1000_LEDCTL_MODE_LED_ON 0xE e1000e_defines.h 　
3815
 E1000_LEDCTL_MODE_LED_OFFE1000_LEDCTL_MODE_LED_OFF 0xF e1000e_defines.h 　
3816
 E1000_TXD_DTYP_DE1000_TXD_DTYP_D 0x00100000 e1000e_defines.h Data Descriptor
3817
 E1000_TXD_DTYP_CE1000_TXD_DTYP_C 0x00000000 e1000e_defines.h Context Descriptor
3818
 E1000_TXD_POPTS_SHIFTE1000_TXD_POPTS_SHIFT 8 e1000e_defines.h POPTS shift
3819
 E1000_TXD_POPTS_IXSME1000_TXD_POPTS_IXSM 0x01 e1000e_defines.h Insert IP checksum
3820
 E1000_TXD_POPTS_TXSME1000_TXD_POPTS_TXSM 0x02 e1000e_defines.h Insert TCP/UDP checksum
3821
 E1000_TXD_CMD_EOPE1000_TXD_CMD_EOP 0x01000000 e1000e_defines.h End of Packet
3822
 E1000_TXD_CMD_IFCSE1000_TXD_CMD_IFCS 0x02000000 e1000e_defines.h Insert FCS (Ethernet CRC)
3823
 E1000_TXD_CMD_ICE1000_TXD_CMD_IC 0x04000000 e1000e_defines.h Insert Checksum
3824
 E1000_TXD_CMD_RSE1000_TXD_CMD_RS 0x08000000 e1000e_defines.h Report Status
3825
 E1000_TXD_CMD_RPSE1000_TXD_CMD_RPS 0x10000000 e1000e_defines.h Report Packet Sent
3826
 E1000_TXD_CMD_DEXTE1000_TXD_CMD_DEXT 0x20000000 e1000e_defines.h Descriptor extension (0 = legacy)
3827
 E1000_TXD_CMD_VLEE1000_TXD_CMD_VLE 0x40000000 e1000e_defines.h Add VLAN tag
3828
 E1000_TXD_CMD_IDEE1000_TXD_CMD_IDE 0x80000000 e1000e_defines.h Enable Tidv register
3829
 E1000_TXD_STAT_DDE1000_TXD_STAT_DD 0x00000001 e1000e_defines.h Descriptor Done
3830
 E1000_TXD_STAT_ECE1000_TXD_STAT_EC 0x00000002 e1000e_defines.h Excess Collisions
3831
 E1000_TXD_STAT_LCE1000_TXD_STAT_LC 0x00000004 e1000e_defines.h Late Collisions
3832
 E1000_TXD_STAT_TUE1000_TXD_STAT_TU 0x00000008 e1000e_defines.h Transmit underrun
3833
 E1000_TXD_CMD_TCPE1000_TXD_CMD_TCP 0x01000000 e1000e_defines.h TCP packet
3834
 E1000_TXD_CMD_IPE1000_TXD_CMD_IP 0x02000000 e1000e_defines.h IP packet
3835
 E1000_TXD_CMD_TSEE1000_TXD_CMD_TSE 0x04000000 e1000e_defines.h TCP Seg enable
3836
 E1000_TXD_STAT_TCE1000_TXD_STAT_TC 0x00000004 e1000e_defines.h Tx Underrun
3837
 E1000_TXD_CMD_LINKSECE1000_TXD_CMD_LINKSEC 0x10000000 e1000e_defines.h Apply LinkSec on packet
3838
 E1000_TXD_EXTCMD_TSTAMPE1000_TXD_EXTCMD_TSTAMP 0x00000010 e1000e_defines.h IEEE1588 Timestamp packet
3839
 E1000_TCTL_RSTE1000_TCTL_RST 0x00000001 e1000e_defines.h software reset
3840
 E1000_TCTL_ENE1000_TCTL_EN 0x00000002 e1000e_defines.h enable tx
3841
 E1000_TCTL_BCEE1000_TCTL_BCE 0x00000004 e1000e_defines.h busy check enable
3842
 E1000_TCTL_PSPE1000_TCTL_PSP 0x00000008 e1000e_defines.h pad short packets
3843
 E1000_TCTL_CTE1000_TCTL_CT 0x00000ff0 e1000e_defines.h collision threshold
3844
 E1000_TCTL_COLDE1000_TCTL_COLD 0x003ff000 e1000e_defines.h collision distance
3845
 E1000_TCTL_SWXOFFE1000_TCTL_SWXOFF 0x00400000 e1000e_defines.h SW Xoff transmission
3846
 E1000_TCTL_PBEE1000_TCTL_PBE 0x00800000 e1000e_defines.h Packet Burst Enable
3847
 E1000_TCTL_RTLCE1000_TCTL_RTLC 0x01000000 e1000e_defines.h Re-transmit on late collision
3848
 E1000_TCTL_NRTUE1000_TCTL_NRTU 0x02000000 e1000e_defines.h No Re-transmit on underrun
3849
 E1000_TCTL_MULRE1000_TCTL_MULR 0x10000000 e1000e_defines.h Multiple request support
3850
 E1000_TARC0_ENABLEE1000_TARC0_ENABLE 0x00000400 e1000e_defines.h Enable Tx Queue 0
3851
 E1000_SCTL_DISABLE_SERDES_LOOPBE1000_SCTL_DISABLE_SERDES_LOOPB 0x0400 e1000e_defines.h 　
3852
 E1000_RXCSUM_PCSS_MASKE1000_RXCSUM_PCSS_MASK 0x000000FF e1000e_defines.h Packet Checksum Start
3853
 E1000_RXCSUM_IPOFLE1000_RXCSUM_IPOFL 0x00000100 e1000e_defines.h IPv4 checksum offload
3854
 E1000_RXCSUM_TUOFLE1000_RXCSUM_TUOFL 0x00000200 e1000e_defines.h TCP / UDP checksum offload
3855
 E1000_RXCSUM_IPV6OFLE1000_RXCSUM_IPV6OFL 0x00000400 e1000e_defines.h IPv6 checksum offload
3856
 E1000_RXCSUM_CRCOFLE1000_RXCSUM_CRCOFL 0x00000800 e1000e_defines.h CRC32 offload enable
3857
 E1000_RXCSUM_IPPCSEE1000_RXCSUM_IPPCSE 0x00001000 e1000e_defines.h IP payload checksum enable
3858
 E1000_RXCSUM_PCSDE1000_RXCSUM_PCSD 0x00002000 e1000e_defines.h packet checksum disabled
3859
 E1000_RFCTL_ISCSI_DISE1000_RFCTL_ISCSI_DIS 0x00000001 e1000e_defines.h 　
3860
 E1000_RFCTL_ISCSI_DWC_MASKE1000_RFCTL_ISCSI_DWC_MASK 0x0000003E e1000e_defines.h 　
3861
 E1000_RFCTL_ISCSI_DWC_SHIFTE1000_RFCTL_ISCSI_DWC_SHIFT 1 e1000e_defines.h 　
3862
 E1000_RFCTL_NFSW_DISE1000_RFCTL_NFSW_DIS 0x00000040 e1000e_defines.h 　
3863
 E1000_RFCTL_NFSR_DISE1000_RFCTL_NFSR_DIS 0x00000080 e1000e_defines.h 　
3864
 E1000_RFCTL_NFS_VER_MASKE1000_RFCTL_NFS_VER_MASK 0x00000300 e1000e_defines.h 　
3865
 E1000_RFCTL_NFS_VER_SHIFTE1000_RFCTL_NFS_VER_SHIFT 8 e1000e_defines.h 　
3866
 E1000_RFCTL_IPV6_DISE1000_RFCTL_IPV6_DIS 0x00000400 e1000e_defines.h 　
3867
 E1000_RFCTL_IPV6_XSUM_DISE1000_RFCTL_IPV6_XSUM_DIS 0x00000800 e1000e_defines.h 　
3868
 E1000_RFCTL_ACK_DISE1000_RFCTL_ACK_DIS 0x00001000 e1000e_defines.h 　
3869
 E1000_RFCTL_ACKD_DISE1000_RFCTL_ACKD_DIS 0x00002000 e1000e_defines.h 　
3870
 E1000_RFCTL_IPFRSP_DISE1000_RFCTL_IPFRSP_DIS 0x00004000 e1000e_defines.h 　
3871
 E1000_RFCTL_EXTENE1000_RFCTL_EXTEN 0x00008000 e1000e_defines.h 　
3872
 E1000_RFCTL_IPV6_EX_DISE1000_RFCTL_IPV6_EX_DIS 0x00010000 e1000e_defines.h 　
3873
 E1000_RFCTL_NEW_IPV6_EXT_DISE1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 e1000e_defines.h 　
3874
 E1000_RFCTL_LEFE1000_RFCTL_LEF 0x00040000 e1000e_defines.h 　
3875
 E1000_COLLISION_THRESHOLDE1000_COLLISION_THRESHOLD 15 e1000e_defines.h 　
3876
 E1000_CT_SHIFTE1000_CT_SHIFT 4 e1000e_defines.h 　
3877
 E1000_COLLISION_DISTANCEE1000_COLLISION_DISTANCE 63 e1000e_defines.h 　
3878
 E1000_COLD_SHIFTE1000_COLD_SHIFT 12 e1000e_defines.h 　
3879
 DEFAULT_82543_TIPG_IPGT_FIBERDEFAULT_82543_TIPG_IPGT_FIBER 9 e1000e_defines.h 　
3880
 DEFAULT_82543_TIPG_IPGT_COPPERDEFAULT_82543_TIPG_IPGT_COPPER 8 e1000e_defines.h 　
3881
 E1000_TIPG_IPGT_MASKE1000_TIPG_IPGT_MASK 0x000003FF e1000e_defines.h 　
3882
 E1000_TIPG_IPGR1_MASKE1000_TIPG_IPGR1_MASK 0x000FFC00 e1000e_defines.h 　
3883
 E1000_TIPG_IPGR2_MASKE1000_TIPG_IPGR2_MASK 0x3FF00000 e1000e_defines.h 　
3884
 DEFAULT_82543_TIPG_IPGR1DEFAULT_82543_TIPG_IPGR1 8 e1000e_defines.h 　
3885
 E1000_TIPG_IPGR1_SHIFTE1000_TIPG_IPGR1_SHIFT 10 e1000e_defines.h 　
3886
 DEFAULT_82543_TIPG_IPGR2DEFAULT_82543_TIPG_IPGR2 6 e1000e_defines.h 　
3887
 DEFAULT_80003ES2LAN_TIPG_IPGR2DEFAULT_80003ES2LAN_TIPG_IPGR2 7 e1000e_defines.h 　
3888
 E1000_TIPG_IPGR2_SHIFTE1000_TIPG_IPGR2_SHIFT 20 e1000e_defines.h 　
3889
 ETHERNET_IEEE_VLAN_TYPEETHERNET_IEEE_VLAN_TYPE 0x8100 e1000e_defines.h 802.3ac packet
3890
 ETHERNET_FCS_SIZEETHERNET_FCS_SIZE 4 e1000e_defines.h 　
3891
 MAX_JUMBO_FRAME_SIZEMAX_JUMBO_FRAME_SIZE 0x3F00 e1000e_defines.h 　
3892
 E1000_EXTCNF_CTRL_MDIO_SW_OWNERE1000_EXTCNF_CTRL_MDIO_SW_OWNER 0x00000020 e1000e_defines.h 　
3893
 E1000_EXTCNF_CTRL_LCD_WRITE_ENAE1000_EXTCNF_CTRL_LCD_WRITE_ENA 0x00000001 e1000e_defines.h 　
3894
 E1000_EXTCNF_CTRL_OEM_WRITE_ENAE1000_EXTCNF_CTRL_OEM_WRITE_ENA 0x00000008 e1000e_defines.h 　
3895
 E1000_EXTCNF_CTRL_SWFLAGE1000_EXTCNF_CTRL_SWFLAG 0x00000020 e1000e_defines.h 　
3896
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 0x00FF0000 e1000e_defines.h 　
3897
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 16 e1000e_defines.h 　
3898
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 0x0FFF0000 e1000e_defines.h 　
3899
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 16 e1000e_defines.h 　
3900
 E1000_PHY_CTRL_SPD_ENE1000_PHY_CTRL_SPD_EN 0x00000001 e1000e_defines.h 　
3901
 E1000_PHY_CTRL_D0A_LPLUE1000_PHY_CTRL_D0A_LPLU 0x00000002 e1000e_defines.h 　
3902
 E1000_PHY_CTRL_NOND0A_LPLUE1000_PHY_CTRL_NOND0A_LPLU 0x00000004 e1000e_defines.h 　
3903
 E1000_PHY_CTRL_NOND0A_GBE_DISABE1000_PHY_CTRL_NOND0A_GBE_DISAB 0x00000008 e1000e_defines.h 　
3904
 E1000_PHY_CTRL_GBE_DISABLEE1000_PHY_CTRL_GBE_DISABLE 0x00000040 e1000e_defines.h 　
3905
 E1000_KABGTXD_BGSQLBIASE1000_KABGTXD_BGSQLBIAS 0x00050000 e1000e_defines.h 　
3906
 E1000_PBA_6KE1000_PBA_6K 0x0006 e1000e_defines.h 6KB
3907
 E1000_PBA_8KE1000_PBA_8K 0x0008 e1000e_defines.h 8KB
3908
 E1000_PBA_10KE1000_PBA_10K 0x000A e1000e_defines.h 10KB
3909
 E1000_PBA_12KE1000_PBA_12K 0x000C e1000e_defines.h 12KB
3910
 E1000_PBA_14KE1000_PBA_14K 0x000E e1000e_defines.h 14KB
3911
 E1000_PBA_16KE1000_PBA_16K 0x0010 e1000e_defines.h 16KB
3912
 E1000_PBA_18KE1000_PBA_18K 0x0012 e1000e_defines.h 　
3913
 E1000_PBA_20KE1000_PBA_20K 0x0014 e1000e_defines.h 　
3914
 E1000_PBA_22KE1000_PBA_22K 0x0016 e1000e_defines.h 　
3915
 E1000_PBA_24KE1000_PBA_24K 0x0018 e1000e_defines.h 　
3916
 E1000_PBA_26KE1000_PBA_26K 0x001A e1000e_defines.h 　
3917
 E1000_PBA_30KE1000_PBA_30K 0x001E e1000e_defines.h 　
3918
 E1000_PBA_32KE1000_PBA_32K 0x0020 e1000e_defines.h 　
3919
 E1000_PBA_34KE1000_PBA_34K 0x0022 e1000e_defines.h 　
3920
 E1000_PBA_35KE1000_PBA_35K 0x0023 e1000e_defines.h 　
3921
 E1000_PBA_38KE1000_PBA_38K 0x0026 e1000e_defines.h 　
3922
 E1000_PBA_40KE1000_PBA_40K 0x0028 e1000e_defines.h 　
3923
 E1000_PBA_48KE1000_PBA_48K 0x0030 e1000e_defines.h 48KB
3924
 E1000_PBA_64KE1000_PBA_64K 0x0040 e1000e_defines.h 64KB
3925
 E1000_PBS_16KE1000_PBS_16K E1000_PBA_16K e1000e_defines.h 　
3926
 E1000_PBS_24KE1000_PBS_24K E1000_PBA_24K e1000e_defines.h 　
3927
 IFS_MAXIFS_MAX 80 e1000e_defines.h 　
3928
 IFS_MINIFS_MIN 40 e1000e_defines.h 　
3929
 IFS_RATIOIFS_RATIO 4 e1000e_defines.h 　
3930
 IFS_STEPIFS_STEP 10 e1000e_defines.h 　
3931
 MIN_NUM_XMITSMIN_NUM_XMITS 1000 e1000e_defines.h 　
3932
 E1000_SWSM_SMBIE1000_SWSM_SMBI 0x00000001 e1000e_defines.h Driver Semaphore bit
3933
 E1000_SWSM_SWESMBIE1000_SWSM_SWESMBI 0x00000002 e1000e_defines.h FW Semaphore bit
3934
 E1000_SWSM_WMNGE1000_SWSM_WMNG 0x00000004 e1000e_defines.h Wake MNG Clock
3935
 E1000_SWSM_DRV_LOADE1000_SWSM_DRV_LOAD 0x00000008 e1000e_defines.h Driver Loaded Bit
3936
 E1000_SWSM2_LOCKE1000_SWSM2_LOCK 0x00000002 e1000e_defines.h Secondary driver semaphore bit
3937
 E1000_ICR_TXDWE1000_ICR_TXDW 0x00000001 e1000e_defines.h Transmit desc written back
3938
 E1000_ICR_TXQEE1000_ICR_TXQE 0x00000002 e1000e_defines.h Transmit Queue empty
3939
 E1000_ICR_LSCE1000_ICR_LSC 0x00000004 e1000e_defines.h Link Status Change
3940
 E1000_ICR_RXSEQE1000_ICR_RXSEQ 0x00000008 e1000e_defines.h rx sequence error
3941
 E1000_ICR_RXDMT0E1000_ICR_RXDMT0 0x00000010 e1000e_defines.h rx desc min. threshold (0)
3942
 E1000_ICR_RXOE1000_ICR_RXO 0x00000040 e1000e_defines.h rx overrun
3943
 E1000_ICR_RXT0E1000_ICR_RXT0 0x00000080 e1000e_defines.h rx timer intr (ring 0)
3944
 E1000_ICR_VMMBE1000_ICR_VMMB 0x00000100 e1000e_defines.h VM MB event
3945
 E1000_ICR_MDACE1000_ICR_MDAC 0x00000200 e1000e_defines.h MDIO access complete
3946
 E1000_ICR_RXCFGE1000_ICR_RXCFG 0x00000400 e1000e_defines.h Rx /c/ ordered set
3947
 E1000_ICR_GPI_EN0E1000_ICR_GPI_EN0 0x00000800 e1000e_defines.h GP Int 0
3948
 E1000_ICR_GPI_EN1E1000_ICR_GPI_EN1 0x00001000 e1000e_defines.h GP Int 1
3949
 E1000_ICR_GPI_EN2E1000_ICR_GPI_EN2 0x00002000 e1000e_defines.h GP Int 2
3950
 E1000_ICR_GPI_EN3E1000_ICR_GPI_EN3 0x00004000 e1000e_defines.h GP Int 3
3951
 E1000_ICR_TXD_LOWE1000_ICR_TXD_LOW 0x00008000 e1000e_defines.h 　
3952
 E1000_ICR_SRPDE1000_ICR_SRPD 0x00010000 e1000e_defines.h 　
3953
 E1000_ICR_ACKE1000_ICR_ACK 0x00020000 e1000e_defines.h Receive Ack frame
3954
 E1000_ICR_MNGE1000_ICR_MNG 0x00040000 e1000e_defines.h Manageability event
3955
 E1000_ICR_DOCKE1000_ICR_DOCK 0x00080000 e1000e_defines.h Dock/Undock
3956
 E1000_ICR_INT_ASSERTEDE1000_ICR_INT_ASSERTED 0x80000000 e1000e_defines.h If this bit asserted, the driver
3957
 E1000_ICR_RXD_FIFO_PAR0E1000_ICR_RXD_FIFO_PAR0 0x00100000 e1000e_defines.h Q0 Rx desc FIFO parity error
3958
 E1000_ICR_TXD_FIFO_PAR0E1000_ICR_TXD_FIFO_PAR0 0x00200000 e1000e_defines.h Q0 Tx desc FIFO parity error
3959
 E1000_ICR_HOST_ARB_PARE1000_ICR_HOST_ARB_PAR 0x00400000 e1000e_defines.h host arb read buffer parity err
3960
 E1000_ICR_PB_PARE1000_ICR_PB_PAR 0x00800000 e1000e_defines.h packet buffer parity error
3961
 E1000_ICR_RXD_FIFO_PAR1E1000_ICR_RXD_FIFO_PAR1 0x01000000 e1000e_defines.h Q1 Rx desc FIFO parity error
3962
 E1000_ICR_TXD_FIFO_PAR1E1000_ICR_TXD_FIFO_PAR1 0x02000000 e1000e_defines.h Q1 Tx desc FIFO parity error
3963
 E1000_ICR_ALL_PARITYE1000_ICR_ALL_PARITY 0x03F00000 e1000e_defines.h all parity error bits
3964
 E1000_ICR_DSWE1000_ICR_DSW 0x00000020 e1000e_defines.h FW changed the status of DISSW
3965
 E1000_ICR_PHYINTE1000_ICR_PHYINT 0x00001000 e1000e_defines.h LAN connected device generates
3966
 E1000_ICR_DOUTSYNCE1000_ICR_DOUTSYNC 0x10000000 e1000e_defines.h NIC DMA out of sync
3967
 E1000_ICR_EPRSTE1000_ICR_EPRST 0x00100000 e1000e_defines.h ME hardware reset occurs
3968
 E1000_ICR_RXQ0E1000_ICR_RXQ0 0x00100000 e1000e_defines.h Rx Queue 0 Interrupt
3969
 E1000_ICR_RXQ1E1000_ICR_RXQ1 0x00200000 e1000e_defines.h Rx Queue 1 Interrupt
3970
 E1000_ICR_TXQ0E1000_ICR_TXQ0 0x00400000 e1000e_defines.h Tx Queue 0 Interrupt
3971
 E1000_ICR_TXQ1E1000_ICR_TXQ1 0x00800000 e1000e_defines.h Tx Queue 1 Interrupt
3972
 E1000_ICR_OTHERE1000_ICR_OTHER 0x01000000 e1000e_defines.h Other Interrupts
3973
 E1000_PBA_ECC_COUNTER_MASKE1000_PBA_ECC_COUNTER_MASK 0xFFF00000 e1000e_defines.h ECC counter mask
3974
 E1000_PBA_ECC_COUNTER_SHIFTE1000_PBA_ECC_COUNTER_SHIFT 20 e1000e_defines.h ECC counter shift value
3975
 E1000_PBA_ECC_CORR_ENE1000_PBA_ECC_CORR_EN 0x00000001 e1000e_defines.h Enable ECC error correction
3976
 E1000_PBA_ECC_STAT_CLRE1000_PBA_ECC_STAT_CLR 0x00000002 e1000e_defines.h Clear ECC error counter
3977
 E1000_PBA_ECC_INT_ENE1000_PBA_ECC_INT_EN 0x00000004 e1000e_defines.h Enable ICR bit 5 on ECC error
3978
 POLL_IMS_ENABLE_MASKPOLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) e1000e_defines.h 　
3979
 IMS_ENABLE_MASKIMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_LSC) e1000e_defines.h 　
3980
 E1000_IMS_TXDWE1000_IMS_TXDW E1000_ICR_TXDW e1000e_defines.h Tx desc written back
3981
 E1000_IMS_TXQEE1000_IMS_TXQE E1000_ICR_TXQE e1000e_defines.h Transmit Queue empty
3982
 E1000_IMS_LSCE1000_IMS_LSC E1000_ICR_LSC e1000e_defines.h Link Status Change
3983
 E1000_IMS_VMMBE1000_IMS_VMMB E1000_ICR_VMMB e1000e_defines.h Mail box activity
3984
 E1000_IMS_RXSEQE1000_IMS_RXSEQ E1000_ICR_RXSEQ e1000e_defines.h rx sequence error
3985
 E1000_IMS_RXDMT0E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 e1000e_defines.h rx desc min. threshold
3986
 E1000_IMS_RXOE1000_IMS_RXO E1000_ICR_RXO e1000e_defines.h rx overrun
3987
 E1000_IMS_RXT0E1000_IMS_RXT0 E1000_ICR_RXT0 e1000e_defines.h rx timer intr
3988
 E1000_IMS_MDACE1000_IMS_MDAC E1000_ICR_MDAC e1000e_defines.h MDIO access complete
3989
 E1000_IMS_RXCFGE1000_IMS_RXCFG E1000_ICR_RXCFG e1000e_defines.h Rx /c/ ordered set
3990
 E1000_IMS_GPI_EN0E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 e1000e_defines.h GP Int 0
3991
 E1000_IMS_GPI_EN1E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 e1000e_defines.h GP Int 1
3992
 E1000_IMS_GPI_EN2E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 e1000e_defines.h GP Int 2
3993
 E1000_IMS_GPI_EN3E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 e1000e_defines.h GP Int 3
3994
 E1000_IMS_TXD_LOWE1000_IMS_TXD_LOW E1000_ICR_TXD_LOW e1000e_defines.h 　
3995
 E1000_IMS_SRPDE1000_IMS_SRPD E1000_ICR_SRPD e1000e_defines.h 　
3996
 E1000_IMS_ACKE1000_IMS_ACK E1000_ICR_ACK e1000e_defines.h Receive Ack frame
3997
 E1000_IMS_MNGE1000_IMS_MNG E1000_ICR_MNG e1000e_defines.h Manageability event
3998
 E1000_IMS_DOCKE1000_IMS_DOCK E1000_ICR_DOCK e1000e_defines.h Dock/Undock
3999
 E1000_IMS_RXD_FIFO_PAR0E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000e_defines.h Q0 Rx desc FIFO
4000
 E1000_IMS_TXD_FIFO_PAR0E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000e_defines.h Q0 Tx desc FIFO
4001
 E1000_IMS_HOST_ARB_PARE1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000e_defines.h host arb read buffer
4002
 E1000_IMS_PB_PARE1000_IMS_PB_PAR E1000_ICR_PB_PAR e1000e_defines.h packet buffer parity
4003
 E1000_IMS_RXD_FIFO_PAR1E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000e_defines.h Q1 Rx desc FIFO
4004
 E1000_IMS_TXD_FIFO_PAR1E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000e_defines.h Q1 Tx desc FIFO
4005
 E1000_IMS_DSWE1000_IMS_DSW E1000_ICR_DSW e1000e_defines.h 　
4006
 E1000_IMS_PHYINTE1000_IMS_PHYINT E1000_ICR_PHYINT e1000e_defines.h 　
4007
 E1000_IMS_DOUTSYNCE1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC e1000e_defines.h NIC DMA out of sync
4008
 E1000_IMS_EPRSTE1000_IMS_EPRST E1000_ICR_EPRST e1000e_defines.h 　
4009
 E1000_IMS_RXQ0E1000_IMS_RXQ0 E1000_ICR_RXQ0 e1000e_defines.h Rx Queue 0 Interrupt
4010
 E1000_IMS_RXQ1E1000_IMS_RXQ1 E1000_ICR_RXQ1 e1000e_defines.h Rx Queue 1 Interrupt
4011
 E1000_IMS_TXQ0E1000_IMS_TXQ0 E1000_ICR_TXQ0 e1000e_defines.h Tx Queue 0 Interrupt
4012
 E1000_IMS_TXQ1E1000_IMS_TXQ1 E1000_ICR_TXQ1 e1000e_defines.h Tx Queue 1 Interrupt
4013
 E1000_IMS_OTHERE1000_IMS_OTHER E1000_ICR_OTHER e1000e_defines.h Other Interrupts
4014
 E1000_ICS_TXDWE1000_ICS_TXDW E1000_ICR_TXDW e1000e_defines.h Tx desc written back
4015
 E1000_ICS_TXQEE1000_ICS_TXQE E1000_ICR_TXQE e1000e_defines.h Transmit Queue empty
4016
 E1000_ICS_LSCE1000_ICS_LSC E1000_ICR_LSC e1000e_defines.h Link Status Change
4017
 E1000_ICS_RXSEQE1000_ICS_RXSEQ E1000_ICR_RXSEQ e1000e_defines.h rx sequence error
4018
 E1000_ICS_RXDMT0E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 e1000e_defines.h rx desc min. threshold
4019
 E1000_ICS_RXOE1000_ICS_RXO E1000_ICR_RXO e1000e_defines.h rx overrun
4020
 E1000_ICS_RXT0E1000_ICS_RXT0 E1000_ICR_RXT0 e1000e_defines.h rx timer intr
4021
 E1000_ICS_MDACE1000_ICS_MDAC E1000_ICR_MDAC e1000e_defines.h MDIO access complete
4022
 E1000_ICS_RXCFGE1000_ICS_RXCFG E1000_ICR_RXCFG e1000e_defines.h Rx /c/ ordered set
4023
 E1000_ICS_GPI_EN0E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 e1000e_defines.h GP Int 0
4024
 E1000_ICS_GPI_EN1E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 e1000e_defines.h GP Int 1
4025
 E1000_ICS_GPI_EN2E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 e1000e_defines.h GP Int 2
4026
 E1000_ICS_GPI_EN3E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 e1000e_defines.h GP Int 3
4027
 E1000_ICS_TXD_LOWE1000_ICS_TXD_LOW E1000_ICR_TXD_LOW e1000e_defines.h 　
4028
 E1000_ICS_SRPDE1000_ICS_SRPD E1000_ICR_SRPD e1000e_defines.h 　
4029
 E1000_ICS_ACKE1000_ICS_ACK E1000_ICR_ACK e1000e_defines.h Receive Ack frame
4030
 E1000_ICS_MNGE1000_ICS_MNG E1000_ICR_MNG e1000e_defines.h Manageability event
4031
 E1000_ICS_DOCKE1000_ICS_DOCK E1000_ICR_DOCK e1000e_defines.h Dock/Undock
4032
 E1000_ICS_RXD_FIFO_PAR0E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000e_defines.h Q0 Rx desc FIFO
4033
 E1000_ICS_TXD_FIFO_PAR0E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000e_defines.h Q0 Tx desc FIFO
4034
 E1000_ICS_HOST_ARB_PARE1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000e_defines.h host arb read buffer
4035
 E1000_ICS_PB_PARE1000_ICS_PB_PAR E1000_ICR_PB_PAR e1000e_defines.h packet buffer parity
4036
 E1000_ICS_RXD_FIFO_PAR1E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000e_defines.h Q1 Rx desc FIFO
4037
 E1000_ICS_TXD_FIFO_PAR1E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000e_defines.h Q1 Tx desc FIFO
4038
 E1000_ICS_DSWE1000_ICS_DSW E1000_ICR_DSW e1000e_defines.h 　
4039
 E1000_ICS_DOUTSYNCE1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC e1000e_defines.h NIC DMA out of sync
4040
 E1000_ICS_PHYINTE1000_ICS_PHYINT E1000_ICR_PHYINT e1000e_defines.h 　
4041
 E1000_ICS_EPRSTE1000_ICS_EPRST E1000_ICR_EPRST e1000e_defines.h 　
4042
 E1000_TXDCTL_PTHRESHE1000_TXDCTL_PTHRESH 0x0000003F e1000e_defines.h TXDCTL Prefetch Threshold
4043
 E1000_TXDCTL_HTHRESHE1000_TXDCTL_HTHRESH 0x00003F00 e1000e_defines.h TXDCTL Host Threshold
4044
 E1000_TXDCTL_WTHRESHE1000_TXDCTL_WTHRESH 0x003F0000 e1000e_defines.h TXDCTL Writeback Threshold
4045
 E1000_TXDCTL_GRANE1000_TXDCTL_GRAN 0x01000000 e1000e_defines.h TXDCTL Granularity
4046
 E1000_TXDCTL_LWTHRESHE1000_TXDCTL_LWTHRESH 0xFE000000 e1000e_defines.h TXDCTL Low Threshold
4047
 E1000_TXDCTL_FULL_TX_DESC_WBE1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 e1000e_defines.h GRAN=1, WTHRESH=1
4048
 E1000_TXDCTL_MAX_TX_DESC_PREFETE1000_TXDCTL_MAX_TX_DESC_PREFET 0x0100001F e1000e_defines.h GRAN=1, PTHRESH=31
4049
 E1000_TXDCTL_COUNT_DESCE1000_TXDCTL_COUNT_DESC 0x00400000 e1000e_defines.h 　
4050
 FLOW_CONTROL_ADDRESS_LOWFLOW_CONTROL_ADDRESS_LOW 0x00C28001 e1000e_defines.h 　
4051
 FLOW_CONTROL_ADDRESS_HIGHFLOW_CONTROL_ADDRESS_HIGH 0x00000100 e1000e_defines.h 　
4052
 FLOW_CONTROL_TYPEFLOW_CONTROL_TYPE 0x8808 e1000e_defines.h 　
4053
 VLAN_TAG_SIZEVLAN_TAG_SIZE 4 e1000e_defines.h 802.3ac tag (not DMA'd)
4054
 E1000_VLAN_FILTER_TBL_SIZEE1000_VLAN_FILTER_TBL_SIZE 128 e1000e_defines.h VLAN Filter Table (4096 bits)
4055
 E1000_RAR_ENTRIESE1000_RAR_ENTRIES 15 e1000e_defines.h 　
4056
 E1000_RAH_AVE1000_RAH_AV 0x80000000 e1000e_defines.h Receive descriptor valid
4057
 E1000_RAL_MAC_ADDR_LENE1000_RAL_MAC_ADDR_LEN 4 e1000e_defines.h 　
4058
 E1000_RAH_MAC_ADDR_LENE1000_RAH_MAC_ADDR_LEN 2 e1000e_defines.h 　
4059
 E1000_RAH_POOL_MASKE1000_RAH_POOL_MASK 0x03FC0000 e1000e_defines.h 　
4060
 E1000_RAH_POOL_1E1000_RAH_POOL_1 0x00040000 e1000e_defines.h 　
4061
 E1000_SUCCESSE1000_SUCCESS 0 e1000e_defines.h 　
4062
 E1000_ERR_NVME1000_ERR_NVM 1 e1000e_defines.h 　
4063
 E1000_ERR_PHYE1000_ERR_PHY 2 e1000e_defines.h 　
4064
 E1000_ERR_CONFIGE1000_ERR_CONFIG 3 e1000e_defines.h 　
4065
 E1000_ERR_PARAME1000_ERR_PARAM 4 e1000e_defines.h 　
4066
 E1000_ERR_MAC_INITE1000_ERR_MAC_INIT 5 e1000e_defines.h 　
4067
 E1000_ERR_PHY_TYPEE1000_ERR_PHY_TYPE 6 e1000e_defines.h 　
4068
 E1000_ERR_RESETE1000_ERR_RESET 9 e1000e_defines.h 　
4069
 E1000_ERR_MASTER_REQUESTS_PENDIE1000_ERR_MASTER_REQUESTS_PENDI 10 e1000e_defines.h 　
4070
 E1000_ERR_HOST_INTERFACE_COMMANE1000_ERR_HOST_INTERFACE_COMMAN 11 e1000e_defines.h 　
4071
 E1000_BLK_PHY_RESETE1000_BLK_PHY_RESET 12 e1000e_defines.h 　
4072
 E1000_ERR_SWFW_SYNCE1000_ERR_SWFW_SYNC 13 e1000e_defines.h 　
4073
 E1000_NOT_IMPLEMENTEDE1000_NOT_IMPLEMENTED 14 e1000e_defines.h 　
4074
 E1000_ERR_MBXE1000_ERR_MBX 15 e1000e_defines.h 　
4075
 FIBER_LINK_UP_LIMITFIBER_LINK_UP_LIMIT 50 e1000e_defines.h 　
4076
 COPPER_LINK_UP_LIMITCOPPER_LINK_UP_LIMIT 10 e1000e_defines.h 　
4077
 PHY_AUTO_NEG_LIMITPHY_AUTO_NEG_LIMIT 45 e1000e_defines.h 　
4078
 PHY_FORCE_LIMITPHY_FORCE_LIMIT 20 e1000e_defines.h 　
4079
 MASTER_DISABLE_TIMEOUTMASTER_DISABLE_TIMEOUT 800 e1000e_defines.h 　
4080
 PHY_CFG_TIMEOUTPHY_CFG_TIMEOUT 100 e1000e_defines.h 　
4081
 MDIO_OWNERSHIP_TIMEOUTMDIO_OWNERSHIP_TIMEOUT 10 e1000e_defines.h 　
4082
 AUTO_READ_DONE_TIMEOUTAUTO_READ_DONE_TIMEOUT 10 e1000e_defines.h 　
4083
 E1000_FCRTH_RTHE1000_FCRTH_RTH 0x0000FFF8 e1000e_defines.h Mask Bits[15:3] for RTH
4084
 E1000_FCRTH_XFCEE1000_FCRTH_XFCE 0x80000000 e1000e_defines.h External Flow Control Enable
4085
 E1000_FCRTL_RTLE1000_FCRTL_RTL 0x0000FFF8 e1000e_defines.h Mask Bits[15:3] for RTL
4086
 E1000_FCRTL_XONEE1000_FCRTL_XONE 0x80000000 e1000e_defines.h Enable XON frame transmission
4087
 E1000_TXCW_FDE1000_TXCW_FD 0x00000020 e1000e_defines.h TXCW full duplex
4088
 E1000_TXCW_HDE1000_TXCW_HD 0x00000040 e1000e_defines.h TXCW half duplex
4089
 E1000_TXCW_PAUSEE1000_TXCW_PAUSE 0x00000080 e1000e_defines.h TXCW sym pause request
4090
 E1000_TXCW_ASM_DIRE1000_TXCW_ASM_DIR 0x00000100 e1000e_defines.h TXCW astm pause direction
4091
 E1000_TXCW_PAUSE_MASKE1000_TXCW_PAUSE_MASK 0x00000180 e1000e_defines.h TXCW pause request mask
4092
 E1000_TXCW_RFE1000_TXCW_RF 0x00003000 e1000e_defines.h TXCW remote fault
4093
 E1000_TXCW_NPE1000_TXCW_NP 0x00008000 e1000e_defines.h TXCW next page
4094
 E1000_TXCW_CWE1000_TXCW_CW 0x0000ffff e1000e_defines.h TxConfigWord mask
4095
 E1000_TXCW_TXCE1000_TXCW_TXC 0x40000000 e1000e_defines.h Transmit Config control
4096
 E1000_TXCW_ANEE1000_TXCW_ANE 0x80000000 e1000e_defines.h Auto-neg enable
4097
 E1000_RXCW_CWE1000_RXCW_CW 0x0000ffff e1000e_defines.h RxConfigWord mask
4098
 E1000_RXCW_NCE1000_RXCW_NC 0x04000000 e1000e_defines.h Receive config no carrier
4099
 E1000_RXCW_IVE1000_RXCW_IV 0x08000000 e1000e_defines.h Receive config invalid
4100
 E1000_RXCW_CCE1000_RXCW_CC 0x10000000 e1000e_defines.h Receive config change
4101
 E1000_RXCW_CE1000_RXCW_C 0x20000000 e1000e_defines.h Receive config
4102
 E1000_RXCW_SYNCHE1000_RXCW_SYNCH 0x40000000 e1000e_defines.h Receive config synch
4103
 E1000_RXCW_ANCE1000_RXCW_ANC 0x80000000 e1000e_defines.h Auto-neg complete
4104
 E1000_GCR_RXD_NO_SNOOPE1000_GCR_RXD_NO_SNOOP 0x00000001 e1000e_defines.h 　
4105
 E1000_GCR_RXDSCW_NO_SNOOPE1000_GCR_RXDSCW_NO_SNOOP 0x00000002 e1000e_defines.h 　
4106
 E1000_GCR_RXDSCR_NO_SNOOPE1000_GCR_RXDSCR_NO_SNOOP 0x00000004 e1000e_defines.h 　
4107
 E1000_GCR_TXD_NO_SNOOPE1000_GCR_TXD_NO_SNOOP 0x00000008 e1000e_defines.h 　
4108
 E1000_GCR_TXDSCW_NO_SNOOPE1000_GCR_TXDSCW_NO_SNOOP 0x00000010 e1000e_defines.h 　
4109
 E1000_GCR_TXDSCR_NO_SNOOPE1000_GCR_TXDSCR_NO_SNOOP 0x00000020 e1000e_defines.h 　
4110
 E1000_GCR_CMPL_TMOUT_MASKE1000_GCR_CMPL_TMOUT_MASK 0x0000F000 e1000e_defines.h 　
4111
 E1000_GCR_CMPL_TMOUT_10msE1000_GCR_CMPL_TMOUT_10ms 0x00001000 e1000e_defines.h 　
4112
 E1000_GCR_CMPL_TMOUT_RESENDE1000_GCR_CMPL_TMOUT_RESEND 0x00010000 e1000e_defines.h 　
4113
 E1000_GCR_CAP_VER2E1000_GCR_CAP_VER2 0x00040000 e1000e_defines.h 　
4114
 PCIE_NO_SNOOP_ALLPCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ E1000_GCR_RXDSCW_NO_SNOOP | \ E1000_GCR_RXDSCR_NO_SNOOP | \ E1000_GCR_TXD_NO_SNOO e1000e_defines.h 　
4115
 MII_CR_SPEED_SELECT_MSBMII_CR_SPEED_SELECT_MSB 0x0040 e1000e_defines.h bits 6,13: 10=1000, 01=100, 00=10
4116
 MII_CR_COLL_TEST_ENABLEMII_CR_COLL_TEST_ENABLE 0x0080 e1000e_defines.h Collision test enable
4117
 MII_CR_FULL_DUPLEXMII_CR_FULL_DUPLEX 0x0100 e1000e_defines.h FDX =1, half duplex =0
4118
 MII_CR_RESTART_AUTO_NEGMII_CR_RESTART_AUTO_NEG 0x0200 e1000e_defines.h Restart auto negotiation
4119
 MII_CR_ISOLATEMII_CR_ISOLATE 0x0400 e1000e_defines.h Isolate PHY from MII
4120
 MII_CR_POWER_DOWNMII_CR_POWER_DOWN 0x0800 e1000e_defines.h Power down
4121
 MII_CR_AUTO_NEG_ENMII_CR_AUTO_NEG_EN 0x1000 e1000e_defines.h Auto Neg Enable
4122
 MII_CR_SPEED_SELECT_LSBMII_CR_SPEED_SELECT_LSB 0x2000 e1000e_defines.h bits 6,13: 10=1000, 01=100, 00=10
4123
 MII_CR_LOOPBACKMII_CR_LOOPBACK 0x4000 e1000e_defines.h 0 = normal, 1 = loopback
4124
 MII_CR_RESETMII_CR_RESET 0x8000 e1000e_defines.h 0 = normal, 1 = PHY reset
4125
 MII_CR_SPEED_1000MII_CR_SPEED_1000 0x0040 e1000e_defines.h 　
4126
 MII_CR_SPEED_100MII_CR_SPEED_100 0x2000 e1000e_defines.h 　
4127
 MII_CR_SPEED_10MII_CR_SPEED_10 0x0000 e1000e_defines.h 　
4128
 MII_SR_EXTENDED_CAPSMII_SR_EXTENDED_CAPS 0x0001 e1000e_defines.h Extended register capabilities
4129
 MII_SR_JABBER_DETECTMII_SR_JABBER_DETECT 0x0002 e1000e_defines.h Jabber Detected
4130
 MII_SR_LINK_STATUSMII_SR_LINK_STATUS 0x0004 e1000e_defines.h Link Status 1 = link
4131
 MII_SR_AUTONEG_CAPSMII_SR_AUTONEG_CAPS 0x0008 e1000e_defines.h Auto Neg Capable
4132
 MII_SR_REMOTE_FAULTMII_SR_REMOTE_FAULT 0x0010 e1000e_defines.h Remote Fault Detect
4133
 MII_SR_AUTONEG_COMPLETEMII_SR_AUTONEG_COMPLETE 0x0020 e1000e_defines.h Auto Neg Complete
4134
 MII_SR_PREAMBLE_SUPPRESSMII_SR_PREAMBLE_SUPPRESS 0x0040 e1000e_defines.h Preamble may be suppressed
4135
 MII_SR_EXTENDED_STATUSMII_SR_EXTENDED_STATUS 0x0100 e1000e_defines.h Ext. status info in Reg 0x0F
4136
 MII_SR_100T2_HD_CAPSMII_SR_100T2_HD_CAPS 0x0200 e1000e_defines.h 100T2 Half Duplex Capable
4137
 MII_SR_100T2_FD_CAPSMII_SR_100T2_FD_CAPS 0x0400 e1000e_defines.h 100T2 Full Duplex Capable
4138
 MII_SR_10T_HD_CAPSMII_SR_10T_HD_CAPS 0x0800 e1000e_defines.h 10T Half Duplex Capable
4139
 MII_SR_10T_FD_CAPSMII_SR_10T_FD_CAPS 0x1000 e1000e_defines.h 10T Full Duplex Capable
4140
 MII_SR_100X_HD_CAPSMII_SR_100X_HD_CAPS 0x2000 e1000e_defines.h 100X Half Duplex Capable
4141
 MII_SR_100X_FD_CAPSMII_SR_100X_FD_CAPS 0x4000 e1000e_defines.h 100X Full Duplex Capable
4142
 MII_SR_100T4_CAPSMII_SR_100T4_CAPS 0x8000 e1000e_defines.h 100T4 Capable
4143
 NWAY_AR_SELECTOR_FIELDNWAY_AR_SELECTOR_FIELD 0x0001 e1000e_defines.h indicates IEEE 802.3 CSMA/CD
4144
 NWAY_AR_10T_HD_CAPSNWAY_AR_10T_HD_CAPS 0x0020 e1000e_defines.h 10T Half Duplex Capable
4145
 NWAY_AR_10T_FD_CAPSNWAY_AR_10T_FD_CAPS 0x0040 e1000e_defines.h 10T Full Duplex Capable
4146
 NWAY_AR_100TX_HD_CAPSNWAY_AR_100TX_HD_CAPS 0x0080 e1000e_defines.h 100TX Half Duplex Capable
4147
 NWAY_AR_100TX_FD_CAPSNWAY_AR_100TX_FD_CAPS 0x0100 e1000e_defines.h 100TX Full Duplex Capable
4148
 NWAY_AR_100T4_CAPSNWAY_AR_100T4_CAPS 0x0200 e1000e_defines.h 100T4 Capable
4149
 NWAY_AR_PAUSENWAY_AR_PAUSE 0x0400 e1000e_defines.h Pause operation desired
4150
 NWAY_AR_ASM_DIRNWAY_AR_ASM_DIR 0x0800 e1000e_defines.h Asymmetric Pause Direction bit
4151
 NWAY_AR_REMOTE_FAULTNWAY_AR_REMOTE_FAULT 0x2000 e1000e_defines.h Remote Fault detected
4152
 NWAY_AR_NEXT_PAGENWAY_AR_NEXT_PAGE 0x8000 e1000e_defines.h Next Page ability supported
4153
 NWAY_LPAR_SELECTOR_FIELDNWAY_LPAR_SELECTOR_FIELD 0x0000 e1000e_defines.h LP protocol selector field
4154
 NWAY_LPAR_10T_HD_CAPSNWAY_LPAR_10T_HD_CAPS 0x0020 e1000e_defines.h LP is 10T Half Duplex Capable
4155
 NWAY_LPAR_10T_FD_CAPSNWAY_LPAR_10T_FD_CAPS 0x0040 e1000e_defines.h LP is 10T Full Duplex Capable
4156
 NWAY_LPAR_100TX_HD_CAPSNWAY_LPAR_100TX_HD_CAPS 0x0080 e1000e_defines.h LP is 100TX Half Duplex Capable
4157
 NWAY_LPAR_100TX_FD_CAPSNWAY_LPAR_100TX_FD_CAPS 0x0100 e1000e_defines.h LP is 100TX Full Duplex Capable
4158
 NWAY_LPAR_100T4_CAPSNWAY_LPAR_100T4_CAPS 0x0200 e1000e_defines.h LP is 100T4 Capable
4159
 NWAY_LPAR_PAUSENWAY_LPAR_PAUSE 0x0400 e1000e_defines.h LP Pause operation desired
4160
 NWAY_LPAR_ASM_DIRNWAY_LPAR_ASM_DIR 0x0800 e1000e_defines.h LP Asymmetric Pause Direction bit
4161
 NWAY_LPAR_REMOTE_FAULTNWAY_LPAR_REMOTE_FAULT 0x2000 e1000e_defines.h LP has detected Remote Fault
4162
 NWAY_LPAR_ACKNOWLEDGENWAY_LPAR_ACKNOWLEDGE 0x4000 e1000e_defines.h LP has rx'd link code word
4163
 NWAY_LPAR_NEXT_PAGENWAY_LPAR_NEXT_PAGE 0x8000 e1000e_defines.h Next Page ability supported
4164
 NWAY_ER_LP_NWAY_CAPSNWAY_ER_LP_NWAY_CAPS 0x0001 e1000e_defines.h LP has Auto Neg Capability
4165
 NWAY_ER_PAGE_RXDNWAY_ER_PAGE_RXD 0x0002 e1000e_defines.h LP is 10T Half Duplex Capable
4166
 NWAY_ER_NEXT_PAGE_CAPSNWAY_ER_NEXT_PAGE_CAPS 0x0004 e1000e_defines.h LP is 10T Full Duplex Capable
4167
 NWAY_ER_LP_NEXT_PAGE_CAPSNWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 e1000e_defines.h LP is 100TX Half Duplex Capable
4168
 NWAY_ER_PAR_DETECT_FAULTNWAY_ER_PAR_DETECT_FAULT 0x0010 e1000e_defines.h LP is 100TX Full Duplex Capable
4169
 CR_1000T_ASYM_PAUSECR_1000T_ASYM_PAUSE 0x0080 e1000e_defines.h Advertise asymmetric pause bit
4170
 CR_1000T_HD_CAPSCR_1000T_HD_CAPS 0x0100 e1000e_defines.h Advertise 1000T HD capability
4171
 CR_1000T_FD_CAPSCR_1000T_FD_CAPS 0x0200 e1000e_defines.h Advertise 1000T FD capability
4172
 CR_1000T_REPEATER_DTECR_1000T_REPEATER_DTE 0x0400 e1000e_defines.h 1=Repeater/switch device port
4173
 CR_1000T_MS_VALUECR_1000T_MS_VALUE 0x0800 e1000e_defines.h 1=Configure PHY as Master
4174
 CR_1000T_MS_ENABLECR_1000T_MS_ENABLE 0x1000 e1000e_defines.h 1=Master/Slave manual config value
4175
 CR_1000T_TEST_MODE_NORMALCR_1000T_TEST_MODE_NORMAL 0x0000 e1000e_defines.h Normal Operation
4176
 CR_1000T_TEST_MODE_1CR_1000T_TEST_MODE_1 0x2000 e1000e_defines.h Transmit Waveform test
4177
 CR_1000T_TEST_MODE_2CR_1000T_TEST_MODE_2 0x4000 e1000e_defines.h Master Transmit Jitter test
4178
 CR_1000T_TEST_MODE_3CR_1000T_TEST_MODE_3 0x6000 e1000e_defines.h Slave Transmit Jitter test
4179
 CR_1000T_TEST_MODE_4CR_1000T_TEST_MODE_4 0x8000 e1000e_defines.h Transmitter Distortion test
4180
 SR_1000T_IDLE_ERROR_CNTSR_1000T_IDLE_ERROR_CNT 0x00FF e1000e_defines.h Num idle errors since last read
4181
 SR_1000T_ASYM_PAUSE_DIRSR_1000T_ASYM_PAUSE_DIR 0x0100 e1000e_defines.h LP asymmetric pause direction bit
4182
 SR_1000T_LP_HD_CAPSSR_1000T_LP_HD_CAPS 0x0400 e1000e_defines.h LP is 1000T HD capable
4183
 SR_1000T_LP_FD_CAPSSR_1000T_LP_FD_CAPS 0x0800 e1000e_defines.h LP is 1000T FD capable
4184
 SR_1000T_REMOTE_RX_STATUSSR_1000T_REMOTE_RX_STATUS 0x1000 e1000e_defines.h Remote receiver OK
4185
 SR_1000T_LOCAL_RX_STATUSSR_1000T_LOCAL_RX_STATUS 0x2000 e1000e_defines.h Local receiver OK
4186
 SR_1000T_MS_CONFIG_RESSR_1000T_MS_CONFIG_RES 0x4000 e1000e_defines.h 1=Local Tx is Master, 0=Slave
4187
 SR_1000T_MS_CONFIG_FAULTSR_1000T_MS_CONFIG_FAULT 0x8000 e1000e_defines.h Master/Slave config fault
4188
 SR_1000T_PHY_EXCESSIVE_IDLE_ERRSR_1000T_PHY_EXCESSIVE_IDLE_ERR 5 e1000e_defines.h 　
4189
 PHY_CONTROLPHY_CONTROL 0x00 e1000e_defines.h Control Register
4190
 PHY_STATUSPHY_STATUS 0x01 e1000e_defines.h Status Register
4191
 PHY_ID1PHY_ID1 0x02 e1000e_defines.h Phy Id Reg (word 1)
4192
 PHY_ID2PHY_ID2 0x03 e1000e_defines.h Phy Id Reg (word 2)
4193
 PHY_AUTONEG_ADVPHY_AUTONEG_ADV 0x04 e1000e_defines.h Autoneg Advertisement
4194
 PHY_LP_ABILITYPHY_LP_ABILITY 0x05 e1000e_defines.h Link Partner Ability (Base Page)
4195
 PHY_AUTONEG_EXPPHY_AUTONEG_EXP 0x06 e1000e_defines.h Autoneg Expansion Reg
4196
 PHY_NEXT_PAGE_TXPHY_NEXT_PAGE_TX 0x07 e1000e_defines.h Next Page Tx
4197
 PHY_LP_NEXT_PAGEPHY_LP_NEXT_PAGE 0x08 e1000e_defines.h Link Partner Next Page
4198
 PHY_1000T_CTRLPHY_1000T_CTRL 0x09 e1000e_defines.h 1000Base-T Control Reg
4199
 PHY_1000T_STATUSPHY_1000T_STATUS 0x0A e1000e_defines.h 1000Base-T Status Reg
4200
 PHY_EXT_STATUSPHY_EXT_STATUS 0x0F e1000e_defines.h Extended Status Reg
4201
 PHY_CONTROL_LBPHY_CONTROL_LB 0x4000 e1000e_defines.h PHY Loopback bit
4202
 E1000_EECD_SKE1000_EECD_SK 0x00000001 e1000e_defines.h NVM Clock
4203
 E1000_EECD_CSE1000_EECD_CS 0x00000002 e1000e_defines.h NVM Chip Select
4204
 E1000_EECD_DIE1000_EECD_DI 0x00000004 e1000e_defines.h NVM Data In
4205
 E1000_EECD_DOE1000_EECD_DO 0x00000008 e1000e_defines.h NVM Data Out
4206
 E1000_EECD_FWE_MASKE1000_EECD_FWE_MASK 0x00000030 e1000e_defines.h 　
4207
 E1000_EECD_FWE_DISE1000_EECD_FWE_DIS 0x00000010 e1000e_defines.h Disable FLASH writes
4208
 E1000_EECD_FWE_ENE1000_EECD_FWE_EN 0x00000020 e1000e_defines.h Enable FLASH writes
4209
 E1000_EECD_FWE_SHIFTE1000_EECD_FWE_SHIFT 4 e1000e_defines.h 　
4210
 E1000_EECD_REQE1000_EECD_REQ 0x00000040 e1000e_defines.h NVM Access Request
4211
 E1000_EECD_GNTE1000_EECD_GNT 0x00000080 e1000e_defines.h NVM Access Grant
4212
 E1000_EECD_PRESE1000_EECD_PRES 0x00000100 e1000e_defines.h NVM Present
4213
 E1000_EECD_SIZEE1000_EECD_SIZE 0x00000200 e1000e_defines.h NVM Size (0=64 word 1=256 word)
4214
 E1000_EECD_ADDR_BITSE1000_EECD_ADDR_BITS 0x00000400 e1000e_defines.h 　
4215
 E1000_EECD_TYPEE1000_EECD_TYPE 0x00002000 e1000e_defines.h NVM Type (1-SPI, 0-Microwire)
4216
 E1000_NVM_GRANT_ATTEMPTSE1000_NVM_GRANT_ATTEMPTS 1000 e1000e_defines.h NVM # attempts to gain grant
4217
 E1000_EECD_AUTO_RDE1000_EECD_AUTO_RD 0x00000200 e1000e_defines.h NVM Auto Read done
4218
 E1000_EECD_SIZE_EX_MASKE1000_EECD_SIZE_EX_MASK 0x00007800 e1000e_defines.h NVM Size
4219
 E1000_EECD_SIZE_EX_SHIFTE1000_EECD_SIZE_EX_SHIFT 11 e1000e_defines.h 　
4220
 E1000_EECD_NVADDSE1000_EECD_NVADDS 0x00018000 e1000e_defines.h NVM Address Size
4221
 E1000_EECD_SELSHADE1000_EECD_SELSHAD 0x00020000 e1000e_defines.h Select Shadow RAM
4222
 E1000_EECD_INITSRAME1000_EECD_INITSRAM 0x00040000 e1000e_defines.h Initialize Shadow RAM
4223
 E1000_EECD_FLUPDE1000_EECD_FLUPD 0x00080000 e1000e_defines.h Update FLASH
4224
 E1000_EECD_AUPDENE1000_EECD_AUPDEN 0x00100000 e1000e_defines.h Enable Autonomous FLASH update
4225
 E1000_EECD_SHADVE1000_EECD_SHADV 0x00200000 e1000e_defines.h Shadow RAM Data Valid
4226
 E1000_EECD_SEC1VALE1000_EECD_SEC1VAL 0x00400000 e1000e_defines.h Sector One Valid
4227
 E1000_EECD_SECVAL_SHIFTE1000_EECD_SECVAL_SHIFT 22 e1000e_defines.h 　
4228
 E1000_EECD_SEC1VAL_VALID_MASKE1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) e1000e_defines.h 　
4229
 E1000_NVM_SWDPIN0E1000_NVM_SWDPIN0 0x0001 e1000e_defines.h SWDPIN 0 NVM Value
4230
 E1000_NVM_LED_LOGICE1000_NVM_LED_LOGIC 0x0020 e1000e_defines.h Led Logic Word
4231
 E1000_NVM_RW_REG_DATAE1000_NVM_RW_REG_DATA 16 e1000e_defines.h Offset to data in NVM read/write regs
4232
 E1000_NVM_RW_REG_DONEE1000_NVM_RW_REG_DONE 2 e1000e_defines.h Offset to READ/WRITE done bit
4233
 E1000_NVM_RW_REG_STARTE1000_NVM_RW_REG_START 1 e1000e_defines.h Start operation
4234
 E1000_NVM_RW_ADDR_SHIFTE1000_NVM_RW_ADDR_SHIFT 2 e1000e_defines.h Shift to the address bits
4235
 E1000_NVM_POLL_WRITEE1000_NVM_POLL_WRITE 1 e1000e_defines.h Flag for polling for write complete
4236
 E1000_NVM_POLL_READE1000_NVM_POLL_READ 0 e1000e_defines.h Flag for polling for read complete
4237
 E1000_FLASH_UPDATESE1000_FLASH_UPDATES 2000 e1000e_defines.h 　
4238
 NVM_COMPATNVM_COMPAT 0x0003 e1000e_defines.h 　
4239
 NVM_ID_LED_SETTINGSNVM_ID_LED_SETTINGS 0x0004 e1000e_defines.h 　
4240
 NVM_VERSIONNVM_VERSION 0x0005 e1000e_defines.h 　
4241
 NVM_SERDES_AMPLITUDENVM_SERDES_AMPLITUDE 0x0006 e1000e_defines.h SERDES output amplitude
4242
 NVM_PHY_CLASS_WORDNVM_PHY_CLASS_WORD 0x0007 e1000e_defines.h 　
4243
 NVM_INIT_CONTROL1_REGNVM_INIT_CONTROL1_REG 0x000A e1000e_defines.h 　
4244
 NVM_INIT_CONTROL2_REGNVM_INIT_CONTROL2_REG 0x000F e1000e_defines.h 　
4245
 NVM_SWDEF_PINS_CTRL_PORT_1NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 e1000e_defines.h 　
4246
 NVM_INIT_CONTROL3_PORT_BNVM_INIT_CONTROL3_PORT_B 0x0014 e1000e_defines.h 　
4247
 NVM_INIT_3GIO_3NVM_INIT_3GIO_3 0x001A e1000e_defines.h 　
4248
 NVM_SWDEF_PINS_CTRL_PORT_0NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 e1000e_defines.h 　
4249
 NVM_INIT_CONTROL3_PORT_ANVM_INIT_CONTROL3_PORT_A 0x0024 e1000e_defines.h 　
4250
 NVM_CFGNVM_CFG 0x0012 e1000e_defines.h 　
4251
 NVM_FLASH_VERSIONNVM_FLASH_VERSION 0x0032 e1000e_defines.h 　
4252
 NVM_ALT_MAC_ADDR_PTRNVM_ALT_MAC_ADDR_PTR 0x0037 e1000e_defines.h 　
4253
 NVM_CHECKSUM_REGNVM_CHECKSUM_REG 0x003F e1000e_defines.h 　
4254
 E1000_NVM_CFG_DONE_PORT_0E1000_NVM_CFG_DONE_PORT_0 0x040000 e1000e_defines.h MNG config cycle done
4255
 E1000_NVM_CFG_DONE_PORT_1E1000_NVM_CFG_DONE_PORT_1 0x080000 e1000e_defines.h ...for second port
4256
 NVM_WORD0F_PAUSE_MASKNVM_WORD0F_PAUSE_MASK 0x3000 e1000e_defines.h 　
4257
 NVM_WORD0F_PAUSENVM_WORD0F_PAUSE 0x1000 e1000e_defines.h 　
4258
 NVM_WORD0F_ASM_DIRNVM_WORD0F_ASM_DIR 0x2000 e1000e_defines.h 　
4259
 NVM_WORD0F_ANENVM_WORD0F_ANE 0x0800 e1000e_defines.h 　
4260
 NVM_WORD0F_SWPDIO_EXT_MASKNVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 e1000e_defines.h 　
4261
 NVM_WORD0F_LPLUNVM_WORD0F_LPLU 0x0001 e1000e_defines.h 　
4262
 NVM_WORD1A_ASPM_MASKNVM_WORD1A_ASPM_MASK 0x000C e1000e_defines.h 　
4263
 NVM_SUMNVM_SUM 0xBABA e1000e_defines.h 　
4264
 NVM_MAC_ADDR_OFFSETNVM_MAC_ADDR_OFFSET 0 e1000e_defines.h 　
4265
 NVM_PBA_OFFSET_0NVM_PBA_OFFSET_0 8 e1000e_defines.h 　
4266
 NVM_PBA_OFFSET_1NVM_PBA_OFFSET_1 9 e1000e_defines.h 　
4267
 NVM_RESERVED_WORDNVM_RESERVED_WORD 0xFFFF e1000e_defines.h 　
4268
 NVM_PHY_CLASS_ANVM_PHY_CLASS_A 0x8000 e1000e_defines.h 　
4269
 NVM_SERDES_AMPLITUDE_MASKNVM_SERDES_AMPLITUDE_MASK 0x000F e1000e_defines.h 　
4270
 NVM_SIZE_MASKNVM_SIZE_MASK 0x1C00 e1000e_defines.h 　
4271
 NVM_SIZE_SHIFTNVM_SIZE_SHIFT 10 e1000e_defines.h 　
4272
 NVM_WORD_SIZE_BASE_SHIFTNVM_WORD_SIZE_BASE_SHIFT 6 e1000e_defines.h 　
4273
 NVM_SWDPIO_EXT_SHIFTNVM_SWDPIO_EXT_SHIFT 4 e1000e_defines.h 　
4274
 NVM_MAX_RETRY_SPINVM_MAX_RETRY_SPI 5000 e1000e_defines.h Max wait of 5ms, for RDY signal
4275
 NVM_READ_OPCODE_SPINVM_READ_OPCODE_SPI 0x03 e1000e_defines.h NVM read opcode
4276
 NVM_WRITE_OPCODE_SPINVM_WRITE_OPCODE_SPI 0x02 e1000e_defines.h NVM write opcode
4277
 NVM_A8_OPCODE_SPINVM_A8_OPCODE_SPI 0x08 e1000e_defines.h opcode bit-3 = address bit-8
4278
 NVM_WREN_OPCODE_SPINVM_WREN_OPCODE_SPI 0x06 e1000e_defines.h NVM set Write Enable latch
4279
 NVM_WRDI_OPCODE_SPINVM_WRDI_OPCODE_SPI 0x04 e1000e_defines.h NVM reset Write Enable latch
4280
 NVM_RDSR_OPCODE_SPINVM_RDSR_OPCODE_SPI 0x05 e1000e_defines.h NVM read Status register
4281
 NVM_WRSR_OPCODE_SPINVM_WRSR_OPCODE_SPI 0x01 e1000e_defines.h NVM write Status register
4282
 NVM_STATUS_RDY_SPINVM_STATUS_RDY_SPI 0x01 e1000e_defines.h 　
4283
 NVM_STATUS_WEN_SPINVM_STATUS_WEN_SPI 0x02 e1000e_defines.h 　
4284
 NVM_STATUS_BP0_SPINVM_STATUS_BP0_SPI 0x04 e1000e_defines.h 　
4285
 NVM_STATUS_BP1_SPINVM_STATUS_BP1_SPI 0x08 e1000e_defines.h 　
4286
 NVM_STATUS_WPEN_SPINVM_STATUS_WPEN_SPI 0x80 e1000e_defines.h 　
4287
 ID_LED_RESERVED_0000ID_LED_RESERVED_0000 0x0000 e1000e_defines.h 　
4288
 ID_LED_RESERVED_FFFFID_LED_RESERVED_FFFF 0xFFFF e1000e_defines.h 　
4289
 ID_LED_DEFAULTID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) e1000e_defines.h 　
4290
 ID_LED_DEF1_DEF2ID_LED_DEF1_DEF2 0x1 e1000e_defines.h 　
4291
 ID_LED_DEF1_ON2ID_LED_DEF1_ON2 0x2 e1000e_defines.h 　
4292
 ID_LED_DEF1_OFF2ID_LED_DEF1_OFF2 0x3 e1000e_defines.h 　
4293
 ID_LED_ON1_DEF2ID_LED_ON1_DEF2 0x4 e1000e_defines.h 　
4294
 ID_LED_ON1_ON2ID_LED_ON1_ON2 0x5 e1000e_defines.h 　
4295
 ID_LED_ON1_OFF2ID_LED_ON1_OFF2 0x6 e1000e_defines.h 　
4296
 ID_LED_OFF1_DEF2ID_LED_OFF1_DEF2 0x7 e1000e_defines.h 　
4297
 ID_LED_OFF1_ON2ID_LED_OFF1_ON2 0x8 e1000e_defines.h 　
4298
 ID_LED_OFF1_OFF2ID_LED_OFF1_OFF2 0x9 e1000e_defines.h 　
4299
 IGP_ACTIVITY_LED_MASKIGP_ACTIVITY_LED_MASK 0xFFFFF0FF e1000e_defines.h 　
4300
 IGP_ACTIVITY_LED_ENABLEIGP_ACTIVITY_LED_ENABLE 0x0300 e1000e_defines.h 　
4301
 IGP_LED3_MODEIGP_LED3_MODE 0x07000000 e1000e_defines.h 　
4302
 PCI_HEADER_TYPE_REGISTERPCI_HEADER_TYPE_REGISTER 0x0E e1000e_defines.h 　
4303
 PCIE_LINK_STATUSPCIE_LINK_STATUS 0x12 e1000e_defines.h 　
4304
 PCIE_DEVICE_CONTROL2PCIE_DEVICE_CONTROL2 0x28 e1000e_defines.h 　
4305
 PCI_HEADER_TYPE_MULTIFUNCPCI_HEADER_TYPE_MULTIFUNC 0x80 e1000e_defines.h 　
4306
 PCIE_LINK_WIDTH_MASKPCIE_LINK_WIDTH_MASK 0x3F0 e1000e_defines.h 　
4307
 PCIE_LINK_WIDTH_SHIFTPCIE_LINK_WIDTH_SHIFT 4 e1000e_defines.h 　
4308
 PCIE_DEVICE_CONTROL2_16msPCIE_DEVICE_CONTROL2_16ms 0x0005 e1000e_defines.h 　
4309
 ETH_ADDR_LENETH_ADDR_LEN 6 e1000e_defines.h 　
4310
 PHY_REVISION_MASKPHY_REVISION_MASK 0xFFFFFFF0 e1000e_defines.h 　
4311
 MAX_PHY_REG_ADDRESSMAX_PHY_REG_ADDRESS 0x1F e1000e_defines.h 5 bit address bus (0-0x1F)
4312
 MAX_PHY_MULTI_PAGE_REGMAX_PHY_MULTI_PAGE_REG 0xF e1000e_defines.h 　
4313
 M88E1000_E_PHY_IDM88E1000_E_PHY_ID 0x01410C50 e1000e_defines.h 　
4314
 M88E1000_I_PHY_IDM88E1000_I_PHY_ID 0x01410C30 e1000e_defines.h 　
4315
 M88E1011_I_PHY_IDM88E1011_I_PHY_ID 0x01410C20 e1000e_defines.h 　
4316
 IGP01E1000_I_PHY_IDIGP01E1000_I_PHY_ID 0x02A80380 e1000e_defines.h 　
4317
 M88E1011_I_REV_4M88E1011_I_REV_4 0x04 e1000e_defines.h 　
4318
 M88E1111_I_PHY_IDM88E1111_I_PHY_ID 0x01410CC0 e1000e_defines.h 　
4319
 GG82563_E_PHY_IDGG82563_E_PHY_ID 0x01410CA0 e1000e_defines.h 　
4320
 IGP03E1000_E_PHY_IDIGP03E1000_E_PHY_ID 0x02A80390 e1000e_defines.h 　
4321
 IFE_E_PHY_IDIFE_E_PHY_ID 0x02A80330 e1000e_defines.h 　
4322
 IFE_PLUS_E_PHY_IDIFE_PLUS_E_PHY_ID 0x02A80320 e1000e_defines.h 　
4323
 IFE_C_E_PHY_IDIFE_C_E_PHY_ID 0x02A80310 e1000e_defines.h 　
4324
 BME1000_E_PHY_IDBME1000_E_PHY_ID 0x01410CB0 e1000e_defines.h 　
4325
 BME1000_E_PHY_ID_R2BME1000_E_PHY_ID_R2 0x01410CB1 e1000e_defines.h 　
4326
 I82577_E_PHY_IDI82577_E_PHY_ID 0x01540050 e1000e_defines.h 　
4327
 I82578_E_PHY_IDI82578_E_PHY_ID 0x004DD040 e1000e_defines.h 　
4328
 M88_VENDORM88_VENDOR 0x0141 e1000e_defines.h 　
4329
 M88E1000_PHY_SPEC_CTRLM88E1000_PHY_SPEC_CTRL 0x10 e1000e_defines.h PHY Specific Control Register
4330
 M88E1000_PHY_SPEC_STATUSM88E1000_PHY_SPEC_STATUS 0x11 e1000e_defines.h PHY Specific Status Register
4331
 M88E1000_INT_ENABLEM88E1000_INT_ENABLE 0x12 e1000e_defines.h Interrupt Enable Register
4332
 M88E1000_INT_STATUSM88E1000_INT_STATUS 0x13 e1000e_defines.h Interrupt Status Register
4333
 M88E1000_EXT_PHY_SPEC_CTRLM88E1000_EXT_PHY_SPEC_CTRL 0x14 e1000e_defines.h Extended PHY Specific Control
4334
 M88E1000_RX_ERR_CNTRM88E1000_RX_ERR_CNTR 0x15 e1000e_defines.h Receive Error Counter
4335
 M88E1000_PHY_EXT_CTRLM88E1000_PHY_EXT_CTRL 0x1A e1000e_defines.h PHY extend control register
4336
 M88E1000_PHY_PAGE_SELECTM88E1000_PHY_PAGE_SELECT 0x1D e1000e_defines.h Reg 29 for page number setting
4337
 M88E1000_PHY_GEN_CONTROLM88E1000_PHY_GEN_CONTROL 0x1E e1000e_defines.h Its meaning depends on reg 29
4338
 M88E1000_PHY_VCO_REG_BIT8M88E1000_PHY_VCO_REG_BIT8 0x100 e1000e_defines.h Bits 8 & 11 are adjusted for
4339
 M88E1000_PHY_VCO_REG_BIT11M88E1000_PHY_VCO_REG_BIT11 0x800 e1000e_defines.h improved BER performance
4340
 M88E1000_PSCR_JABBER_DISABLEM88E1000_PSCR_JABBER_DISABLE 0x0001 e1000e_defines.h 1=Jabber Function disabled
4341
 M88E1000_PSCR_POLARITY_REVERSALM88E1000_PSCR_POLARITY_REVERSAL 0x0002 e1000e_defines.h 1=Polarity Reverse enabled
4342
 M88E1000_PSCR_SQE_TESTM88E1000_PSCR_SQE_TEST 0x0004 e1000e_defines.h 1=SQE Test enabled
4343
 M88E1000_PSCR_CLK125_DISABLEM88E1000_PSCR_CLK125_DISABLE 0x0010 e1000e_defines.h 　
4344
 M88E1000_PSCR_MDI_MANUAL_MODEM88E1000_PSCR_MDI_MANUAL_MODE 0x0000 e1000e_defines.h MDI Crossover Mode bits 6:5
4345
 M88E1000_PSCR_MDIX_MANUAL_MODEM88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 e1000e_defines.h Manual MDIX configuration
4346
 M88E1000_PSCR_AUTO_X_1000TM88E1000_PSCR_AUTO_X_1000T 0x0040 e1000e_defines.h 　
4347
 M88E1000_PSCR_AUTO_X_MODEM88E1000_PSCR_AUTO_X_MODE 0x0060 e1000e_defines.h 　
4348
 M88E1000_PSCR_EN_10BT_EXT_DISTM88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 e1000e_defines.h 　
4349
 M88E1000_PSCR_MII_5BIT_ENABLEM88E1000_PSCR_MII_5BIT_ENABLE 0x0100 e1000e_defines.h 　
4350
 M88E1000_PSCR_SCRAMBLER_DISABLEM88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 e1000e_defines.h 1=Scrambler disable
4351
 M88E1000_PSCR_FORCE_LINK_GOODM88E1000_PSCR_FORCE_LINK_GOOD 0x0400 e1000e_defines.h 1=Force link good
4352
 M88E1000_PSCR_ASSERT_CRS_ON_TXM88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 e1000e_defines.h 1=Assert CRS on Tx
4353
 M88E1000_PSSR_JABBERM88E1000_PSSR_JABBER 0x0001 e1000e_defines.h 1=Jabber
4354
 M88E1000_PSSR_REV_POLARITYM88E1000_PSSR_REV_POLARITY 0x0002 e1000e_defines.h 1=Polarity reversed
4355
 M88E1000_PSSR_DOWNSHIFTM88E1000_PSSR_DOWNSHIFT 0x0020 e1000e_defines.h 1=Downshifted
4356
 M88E1000_PSSR_MDIXM88E1000_PSSR_MDIX 0x0040 e1000e_defines.h 1=MDIX; 0=MDI
4357
 M88E1000_PSSR_CABLE_LENGTHM88E1000_PSSR_CABLE_LENGTH 0x0380 e1000e_defines.h 　
4358
 M88E1000_PSSR_LINKM88E1000_PSSR_LINK 0x0400 e1000e_defines.h 1=Link up, 0=Link down
4359
 M88E1000_PSSR_SPD_DPLX_RESOLVEDM88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 e1000e_defines.h 1=Speed & Duplex resolved
4360
 M88E1000_PSSR_PAGE_RCVDM88E1000_PSSR_PAGE_RCVD 0x1000 e1000e_defines.h 1=Page received
4361
 M88E1000_PSSR_DPLXM88E1000_PSSR_DPLX 0x2000 e1000e_defines.h 1=Duplex 0=Half Duplex
4362
 M88E1000_PSSR_SPEEDM88E1000_PSSR_SPEED 0xC000 e1000e_defines.h Speed, bits 14:15
4363
 M88E1000_PSSR_10MBSM88E1000_PSSR_10MBS 0x0000 e1000e_defines.h 00=10Mbs
4364
 M88E1000_PSSR_100MBSM88E1000_PSSR_100MBS 0x4000 e1000e_defines.h 01=100Mbs
4365
 M88E1000_PSSR_1000MBSM88E1000_PSSR_1000MBS 0x8000 e1000e_defines.h 10=1000Mbs
4366
 M88E1000_PSSR_CABLE_LENGTH_SHIFM88E1000_PSSR_CABLE_LENGTH_SHIF 7 e1000e_defines.h 　
4367
 M88E1000_EPSCR_FIBER_LOOPBACKM88E1000_EPSCR_FIBER_LOOPBACK 0x4000 e1000e_defines.h 1=Fiber loopback
4368
 M88E1000_EPSCR_DOWN_NO_IDLEM88E1000_EPSCR_DOWN_NO_IDLE 0x8000 e1000e_defines.h 　
4369
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 e1000e_defines.h 　
4370
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0000 e1000e_defines.h 　
4371
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0400 e1000e_defines.h 　
4372
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0800 e1000e_defines.h 　
4373
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 e1000e_defines.h 　
4374
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 e1000e_defines.h 　
4375
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0000 e1000e_defines.h 　
4376
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0100 e1000e_defines.h 　
4377
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0200 e1000e_defines.h 　
4378
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 e1000e_defines.h 　
4379
 M88E1000_EPSCR_TX_CLK_2_5M88E1000_EPSCR_TX_CLK_2_5 0x0060 e1000e_defines.h 2.5 MHz TX_CLK
4380
 M88E1000_EPSCR_TX_CLK_25M88E1000_EPSCR_TX_CLK_25 0x0070 e1000e_defines.h 25 MHz TX_CLK
4381
 M88E1000_EPSCR_TX_CLK_0M88E1000_EPSCR_TX_CLK_0 0x0000 e1000e_defines.h NO TX_CLK
4382
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 e1000e_defines.h 　
4383
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0000 e1000e_defines.h 　
4384
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0200 e1000e_defines.h 　
4385
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0400 e1000e_defines.h 　
4386
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0600 e1000e_defines.h 　
4387
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0800 e1000e_defines.h 　
4388
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0A00 e1000e_defines.h 　
4389
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0C00 e1000e_defines.h 　
4390
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 e1000e_defines.h 　
4391
 I82578_EPSCR_DOWNSHIFT_ENABLEI82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 e1000e_defines.h 　
4392
 I82578_EPSCR_DOWNSHIFT_COUNTER_I82578_EPSCR_DOWNSHIFT_COUNTER_ 0x001C e1000e_defines.h 　
4393
 BME1000_PSCR_ENABLE_DOWNSHIFTBME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 e1000e_defines.h 1 = enable downshift
4394
 GG82563_PAGE_SHIFTGG82563_PAGE_SHIFT 5 e1000e_defines.h 　
4395
 GG82563_MIN_ALT_REGGG82563_MIN_ALT_REG 30 e1000e_defines.h 　
4396
 GG82563_PHY_SPEC_CTRLGG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) e1000e_defines.h PHY Specific Control
4397
 GG82563_PHY_SPEC_STATUSGG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) e1000e_defines.h PHY Specific Status
4398
 GG82563_PHY_INT_ENABLEGG82563_PHY_INT_ENABLE GG82563_REG(0, 18) e1000e_defines.h Interrupt Enable
4399
 GG82563_PHY_SPEC_STATUS_2GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) e1000e_defines.h PHY Specific Status 2
4400
 GG82563_PHY_RX_ERR_CNTRGG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) e1000e_defines.h Receive Error Counter
4401
 GG82563_PHY_PAGE_SELECTGG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) e1000e_defines.h Page Select
4402
 GG82563_PHY_SPEC_CTRL_2GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) e1000e_defines.h PHY Specific Control 2
4403
 GG82563_PHY_PAGE_SELECT_ALTGG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) e1000e_defines.h Alternate Page Select
4404
 GG82563_PHY_TEST_CLK_CTRLGG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) e1000e_defines.h Test Clock Control (use reg. 29 to select)
4405
 GG82563_PHY_MAC_SPEC_CTRLGG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) e1000e_defines.h MAC Specific Control Register
4406
 GG82563_PHY_MAC_SPEC_CTRL_2GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) e1000e_defines.h MAC Specific Control 2
4407
 GG82563_PHY_DSP_DISTANCEGG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) e1000e_defines.h DSP Distance
4408
 GG82563_PHY_KMRN_MODE_CTRLGG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) e1000e_defines.h Kumeran Mode Control
4409
 GG82563_PHY_PORT_RESETGG82563_PHY_PORT_RESET GG82563_REG(193, 17) e1000e_defines.h Port Reset
4410
 GG82563_PHY_REVISION_IDGG82563_PHY_REVISION_ID GG82563_REG(193, 18) e1000e_defines.h Revision ID
4411
 GG82563_PHY_DEVICE_IDGG82563_PHY_DEVICE_ID GG82563_REG(193, 19) e1000e_defines.h Device ID
4412
 GG82563_PHY_PWR_MGMT_CTRLGG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) e1000e_defines.h Power Management Control
4413
 GG82563_PHY_RATE_ADAPT_CTRLGG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) e1000e_defines.h Rate Adaptation Control
4414
 GG82563_PHY_KMRN_FIFO_CTRL_STATGG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) e1000e_defines.h FIFO's Control/Status
4415
 GG82563_PHY_KMRN_CTRLGG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) e1000e_defines.h Control
4416
 GG82563_PHY_INBAND_CTRLGG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) e1000e_defines.h Inband Control
4417
 GG82563_PHY_KMRN_DIAGNOSTICGG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) e1000e_defines.h Diagnostic
4418
 GG82563_PHY_ACK_TIMEOUTSGG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) e1000e_defines.h Acknowledge Timeouts
4419
 GG82563_PHY_ADV_ABILITYGG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) e1000e_defines.h Advertised Ability
4420
 GG82563_PHY_LINK_PARTNER_ADV_ABGG82563_PHY_LINK_PARTNER_ADV_AB GG82563_REG(194, 23) e1000e_defines.h Link Partner Advertised Ability
4421
 GG82563_PHY_ADV_NEXT_PAGEGG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) e1000e_defines.h Advertised Next Page
4422
 GG82563_PHY_LINK_PARTNER_ADV_NEGG82563_PHY_LINK_PARTNER_ADV_NE GG82563_REG(194, 25) e1000e_defines.h Link Partner Advertised Next page
4423
 GG82563_PHY_KMRN_MISCGG82563_PHY_KMRN_MISC GG82563_REG(194, 26) e1000e_defines.h Misc.
4424
 E1000_MDIC_DATA_MASKE1000_MDIC_DATA_MASK 0x0000FFFF e1000e_defines.h 　
4425
 E1000_MDIC_REG_MASKE1000_MDIC_REG_MASK 0x001F0000 e1000e_defines.h 　
4426
 E1000_MDIC_REG_SHIFTE1000_MDIC_REG_SHIFT 16 e1000e_defines.h 　
4427
 E1000_MDIC_PHY_MASKE1000_MDIC_PHY_MASK 0x03E00000 e1000e_defines.h 　
4428
 E1000_MDIC_PHY_SHIFTE1000_MDIC_PHY_SHIFT 21 e1000e_defines.h 　
4429
 E1000_MDIC_OP_WRITEE1000_MDIC_OP_WRITE 0x04000000 e1000e_defines.h 　
4430
 E1000_MDIC_OP_READE1000_MDIC_OP_READ 0x08000000 e1000e_defines.h 　
4431
 E1000_MDIC_READYE1000_MDIC_READY 0x10000000 e1000e_defines.h 　
4432
 E1000_MDIC_INT_ENE1000_MDIC_INT_EN 0x20000000 e1000e_defines.h 　
4433
 E1000_MDIC_ERRORE1000_MDIC_ERROR 0x40000000 e1000e_defines.h 　
4434
 E1000_GEN_CTL_READYE1000_GEN_CTL_READY 0x80000000 e1000e_defines.h 　
4435
 E1000_GEN_CTL_ADDRESS_SHIFTE1000_GEN_CTL_ADDRESS_SHIFT 8 e1000e_defines.h 　
4436
 E1000_GEN_POLL_TIMEOUTE1000_GEN_POLL_TIMEOUT 640 e1000e_defines.h 　
4437
 E1000_DEV_ID_82571EB_COPPERE1000_DEV_ID_82571EB_COPPER 0x105E e1000e_hw.h 　
4438
 E1000_DEV_ID_82571EB_FIBERE1000_DEV_ID_82571EB_FIBER 0x105F e1000e_hw.h 　
4439
 E1000_DEV_ID_82571EB_SERDESE1000_DEV_ID_82571EB_SERDES 0x1060 e1000e_hw.h 　
4440
 E1000_DEV_ID_82571EB_SERDES_DUAE1000_DEV_ID_82571EB_SERDES_DUA 0x10D9 e1000e_hw.h 　
4441
 E1000_DEV_ID_82571EB_SERDES_QUAE1000_DEV_ID_82571EB_SERDES_QUA 0x10DA e1000e_hw.h 　
4442
 E1000_DEV_ID_82571EB_QUAD_COPPEE1000_DEV_ID_82571EB_QUAD_COPPE 0x10A4 e1000e_hw.h 　
4443
 E1000_DEV_ID_82571PT_QUAD_COPPEE1000_DEV_ID_82571PT_QUAD_COPPE 0x10D5 e1000e_hw.h 　
4444
 E1000_DEV_ID_82571EB_QUAD_FIBERE1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 e1000e_hw.h 　
4445
 E1000_DEV_ID_82571EB_QUAD_COPPEE1000_DEV_ID_82571EB_QUAD_COPPE 0x10BC e1000e_hw.h 　
4446
 E1000_DEV_ID_82572EI_COPPERE1000_DEV_ID_82572EI_COPPER 0x107D e1000e_hw.h 　
4447
 E1000_DEV_ID_82572EI_FIBERE1000_DEV_ID_82572EI_FIBER 0x107E e1000e_hw.h 　
4448
 E1000_DEV_ID_82572EI_SERDESE1000_DEV_ID_82572EI_SERDES 0x107F e1000e_hw.h 　
4449
 E1000_DEV_ID_82572EIE1000_DEV_ID_82572EI 0x10B9 e1000e_hw.h 　
4450
 E1000_DEV_ID_82573EE1000_DEV_ID_82573E 0x108B e1000e_hw.h 　
4451
 E1000_DEV_ID_82573E_IAMTE1000_DEV_ID_82573E_IAMT 0x108C e1000e_hw.h 　
4452
 E1000_DEV_ID_82573LE1000_DEV_ID_82573L 0x109A e1000e_hw.h 　
4453
 E1000_DEV_ID_82574LE1000_DEV_ID_82574L 0x10D3 e1000e_hw.h 　
4454
 E1000_DEV_ID_82574LAE1000_DEV_ID_82574LA 0x10F6 e1000e_hw.h 　
4455
 E1000_DEV_ID_82583VE1000_DEV_ID_82583V 0x150C e1000e_hw.h 　
4456
 E1000_DEV_ID_80003ES2LAN_COPPERE1000_DEV_ID_80003ES2LAN_COPPER 0x1096 e1000e_hw.h 　
4457
 E1000_DEV_ID_80003ES2LAN_SERDESE1000_DEV_ID_80003ES2LAN_SERDES 0x1098 e1000e_hw.h 　
4458
 E1000_DEV_ID_80003ES2LAN_COPPERE1000_DEV_ID_80003ES2LAN_COPPER 0x10BA e1000e_hw.h 　
4459
 E1000_DEV_ID_80003ES2LAN_SERDESE1000_DEV_ID_80003ES2LAN_SERDES 0x10BB e1000e_hw.h 　
4460
 E1000_DEV_ID_ICH8_82567V_3E1000_DEV_ID_ICH8_82567V_3 0x1501 e1000e_hw.h 　
4461
 E1000_DEV_ID_ICH8_IGP_M_AMTE1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 e1000e_hw.h 　
4462
 E1000_DEV_ID_ICH8_IGP_AMTE1000_DEV_ID_ICH8_IGP_AMT 0x104A e1000e_hw.h 　
4463
 E1000_DEV_ID_ICH8_IGP_CE1000_DEV_ID_ICH8_IGP_C 0x104B e1000e_hw.h 　
4464
 E1000_DEV_ID_ICH8_IFEE1000_DEV_ID_ICH8_IFE 0x104C e1000e_hw.h 　
4465
 E1000_DEV_ID_ICH8_IFE_GTE1000_DEV_ID_ICH8_IFE_GT 0x10C4 e1000e_hw.h 　
4466
 E1000_DEV_ID_ICH8_IFE_GE1000_DEV_ID_ICH8_IFE_G 0x10C5 e1000e_hw.h 　
4467
 E1000_DEV_ID_ICH8_IGP_ME1000_DEV_ID_ICH8_IGP_M 0x104D e1000e_hw.h 　
4468
 E1000_DEV_ID_ICH9_IGP_ME1000_DEV_ID_ICH9_IGP_M 0x10BF e1000e_hw.h 　
4469
 E1000_DEV_ID_ICH9_IGP_M_AMTE1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 e1000e_hw.h 　
4470
 E1000_DEV_ID_ICH9_IGP_M_VE1000_DEV_ID_ICH9_IGP_M_V 0x10CB e1000e_hw.h 　
4471
 E1000_DEV_ID_ICH9_IGP_AMTE1000_DEV_ID_ICH9_IGP_AMT 0x10BD e1000e_hw.h 　
4472
 E1000_DEV_ID_ICH9_BME1000_DEV_ID_ICH9_BM 0x10E5 e1000e_hw.h 　
4473
 E1000_DEV_ID_ICH9_IGP_CE1000_DEV_ID_ICH9_IGP_C 0x294C e1000e_hw.h 　
4474
 E1000_DEV_ID_ICH9_IFEE1000_DEV_ID_ICH9_IFE 0x10C0 e1000e_hw.h 　
4475
 E1000_DEV_ID_ICH9_IFE_GTE1000_DEV_ID_ICH9_IFE_GT 0x10C3 e1000e_hw.h 　
4476
 E1000_DEV_ID_ICH9_IFE_GE1000_DEV_ID_ICH9_IFE_G 0x10C2 e1000e_hw.h 　
4477
 E1000_DEV_ID_ICH10_R_BM_LME1000_DEV_ID_ICH10_R_BM_LM 0x10CC e1000e_hw.h 　
4478
 E1000_DEV_ID_ICH10_R_BM_LFE1000_DEV_ID_ICH10_R_BM_LF 0x10CD e1000e_hw.h 　
4479
 E1000_DEV_ID_ICH10_R_BM_VE1000_DEV_ID_ICH10_R_BM_V 0x10CE e1000e_hw.h 　
4480
 E1000_DEV_ID_ICH10_D_BM_LME1000_DEV_ID_ICH10_D_BM_LM 0x10DE e1000e_hw.h 　
4481
 E1000_DEV_ID_ICH10_D_BM_LFE1000_DEV_ID_ICH10_D_BM_LF 0x10DF e1000e_hw.h 　
4482
 E1000_DEV_ID_PCH_M_HV_LME1000_DEV_ID_PCH_M_HV_LM 0x10EA e1000e_hw.h 　
4483
 E1000_DEV_ID_PCH_M_HV_LCE1000_DEV_ID_PCH_M_HV_LC 0x10EB e1000e_hw.h 　
4484
 E1000_DEV_ID_PCH_D_HV_DME1000_DEV_ID_PCH_D_HV_DM 0x10EF e1000e_hw.h 　
4485
 E1000_DEV_ID_PCH_D_HV_DCE1000_DEV_ID_PCH_D_HV_DC 0x10F0 e1000e_hw.h 　
4486
 E1000_REVISION_0E1000_REVISION_0 0 e1000e_hw.h 　
4487
 E1000_REVISION_1E1000_REVISION_1 1 e1000e_hw.h 　
4488
 E1000_REVISION_2E1000_REVISION_2 2 e1000e_hw.h 　
4489
 E1000_REVISION_3E1000_REVISION_3 3 e1000e_hw.h 　
4490
 E1000_REVISION_4E1000_REVISION_4 4 e1000e_hw.h 　
4491
 E1000_FUNC_0E1000_FUNC_0 0 e1000e_hw.h 　
4492
 E1000_FUNC_1E1000_FUNC_1 1 e1000e_hw.h 　
4493
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 0 e1000e_hw.h 　
4494
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 3 e1000e_hw.h 　
4495
 MAX_PS_BUFFERSMAX_PS_BUFFERS 4 e1000e_hw.h 　
4496
 E1000_HI_MAX_DATA_LENGTHE1000_HI_MAX_DATA_LENGTH 252 e1000e_hw.h 　
4497
 E1000_HI_MAX_MNG_DATA_LENGTHE1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 e1000e_hw.h 　
4498
 E1000_ICH8_SHADOW_RAM_WORDSE1000_ICH8_SHADOW_RAM_WORDS 2048 e1000e_hw.h 　
4499
 ICH_FLASH_GFPREGICH_FLASH_GFPREG 0x0000 e1000e_ich8lan.h 　
4500
 ICH_FLASH_HSFSTSICH_FLASH_HSFSTS 0x0004 e1000e_ich8lan.h 　
4501
 ICH_FLASH_HSFCTLICH_FLASH_HSFCTL 0x0006 e1000e_ich8lan.h 　
4502
 ICH_FLASH_FADDRICH_FLASH_FADDR 0x0008 e1000e_ich8lan.h 　
4503
 ICH_FLASH_FDATA0ICH_FLASH_FDATA0 0x0010 e1000e_ich8lan.h 　
4504
 ICH_FLASH_READ_COMMAND_TIMEOUTICH_FLASH_READ_COMMAND_TIMEOUT 10000000 e1000e_ich8lan.h 　
4505
 ICH_FLASH_WRITE_COMMAND_TIMEOUTICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 e1000e_ich8lan.h 　
4506
 ICH_FLASH_ERASE_COMMAND_TIMEOUTICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 e1000e_ich8lan.h 　
4507
 ICH_FLASH_LINEAR_ADDR_MASKICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF e1000e_ich8lan.h 　
4508
 ICH_FLASH_CYCLE_REPEAT_COUNTICH_FLASH_CYCLE_REPEAT_COUNT 10 e1000e_ich8lan.h 　
4509
 ICH_CYCLE_READICH_CYCLE_READ 0 e1000e_ich8lan.h 　
4510
 ICH_CYCLE_WRITEICH_CYCLE_WRITE 2 e1000e_ich8lan.h 　
4511
 ICH_CYCLE_ERASEICH_CYCLE_ERASE 3 e1000e_ich8lan.h 　
4512
 FLASH_GFPREG_BASE_MASKFLASH_GFPREG_BASE_MASK 0x1FFF e1000e_ich8lan.h 　
4513
 FLASH_SECTOR_ADDR_SHIFTFLASH_SECTOR_ADDR_SHIFT 12 e1000e_ich8lan.h 　
4514
 ICH_FLASH_SEG_SIZE_256ICH_FLASH_SEG_SIZE_256 256 e1000e_ich8lan.h 　
4515
 ICH_FLASH_SEG_SIZE_4KICH_FLASH_SEG_SIZE_4K 4096 e1000e_ich8lan.h 　
4516
 ICH_FLASH_SEG_SIZE_8KICH_FLASH_SEG_SIZE_8K 8192 e1000e_ich8lan.h 　
4517
 ICH_FLASH_SEG_SIZE_64KICH_FLASH_SEG_SIZE_64K 65536 e1000e_ich8lan.h 　
4518
 ICH_FLASH_SECTOR_SIZEICH_FLASH_SECTOR_SIZE 4096 e1000e_ich8lan.h 　
4519
 ICH_FLASH_REG_MAPSIZEICH_FLASH_REG_MAPSIZE 0x00A0 e1000e_ich8lan.h 　
4520
 E1000_ICH_FWSM_RSPCIPHYE1000_ICH_FWSM_RSPCIPHY 0x00000040 e1000e_ich8lan.h Reset PHY on PCI Reset
4521
 E1000_ICH_FWSM_DISSWE1000_ICH_FWSM_DISSW 0x10000000 e1000e_ich8lan.h FW Disables SW Writes
4522
 E1000_ICH_FWSM_FW_VALIDE1000_ICH_FWSM_FW_VALID 0x00008000 e1000e_ich8lan.h 　
4523
 E1000_ICH_MNG_IAMT_MODEE1000_ICH_MNG_IAMT_MODE 0x2 e1000e_ich8lan.h 　
4524
 ID_LED_DEFAULT_ICH8LANID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_OFF1_ON2 << 4) | \ (ID_LED_DEF1_DEF2)) e1000e_ich8lan.h 　
4525
 E1000_ICH_NVM_SIG_WORDE1000_ICH_NVM_SIG_WORD 0x13 e1000e_ich8lan.h 　
4526
 E1000_ICH_NVM_SIG_MASKE1000_ICH_NVM_SIG_MASK 0xC000 e1000e_ich8lan.h 　
4527
 E1000_ICH_NVM_VALID_SIG_MASKE1000_ICH_NVM_VALID_SIG_MASK 0xC0 e1000e_ich8lan.h 　
4528
 E1000_ICH_NVM_SIG_VALUEE1000_ICH_NVM_SIG_VALUE 0x80 e1000e_ich8lan.h 　
4529
 E1000_ICH8_LAN_INIT_TIMEOUTE1000_ICH8_LAN_INIT_TIMEOUT 1500 e1000e_ich8lan.h 　
4530
 E1000_FEXTNVM_SW_CONFIGE1000_FEXTNVM_SW_CONFIG 1 e1000e_ich8lan.h 　
4531
 E1000_FEXTNVM_SW_CONFIG_ICH8ME1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) e1000e_ich8lan.h Bit redefined for ICH8M
4532
 PCIE_ICH8_SNOOP_ALLPCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL e1000e_ich8lan.h 　
4533
 E1000_ICH_RAR_ENTRIESE1000_ICH_RAR_ENTRIES 7 e1000e_ich8lan.h 　
4534
 PHY_PAGE_SHIFTPHY_PAGE_SHIFT 5 e1000e_ich8lan.h 　
4535
 IGP3_KMRN_DIAGIGP3_KMRN_DIAG PHY_REG(770, 19) e1000e_ich8lan.h KMRN Diagnostic
4536
 IGP3_VR_CTRLIGP3_VR_CTRL PHY_REG(776, 18) e1000e_ich8lan.h Voltage Regulator Control
4537
 IGP3_CAPABILITYIGP3_CAPABILITY PHY_REG(776, 19) e1000e_ich8lan.h Capability
4538
 IGP3_PM_CTRLIGP3_PM_CTRL PHY_REG(769, 20) e1000e_ich8lan.h Power Management Control
4539
 IGP3_KMRN_DIAG_PCS_LOCK_LOSSIGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 e1000e_ich8lan.h 　
4540
 IGP3_VR_CTRL_DEV_POWERDOWN_MODEIGP3_VR_CTRL_DEV_POWERDOWN_MODE 0x0300 e1000e_ich8lan.h 　
4541
 IGP3_VR_CTRL_MODE_SHUTDOWNIGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 e1000e_ich8lan.h 　
4542
 IGP3_PM_CTRL_FORCE_PWR_DOWNIGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 e1000e_ich8lan.h 　
4543
 BM_RCTLBM_RCTL PHY_REG(BM_WUC_PAGE, 0) e1000e_ich8lan.h 　
4544
 BM_WUCBM_WUC PHY_REG(BM_WUC_PAGE, 1) e1000e_ich8lan.h 　
4545
 BM_WUFCBM_WUFC PHY_REG(BM_WUC_PAGE, 2) e1000e_ich8lan.h 　
4546
 BM_WUSBM_WUS PHY_REG(BM_WUC_PAGE, 3) e1000e_ich8lan.h 　
4547
 BM_RCTL_UPEBM_RCTL_UPE 0x0001 e1000e_ich8lan.h Unicast Promiscuous Mode
4548
 BM_RCTL_MPEBM_RCTL_MPE 0x0002 e1000e_ich8lan.h Multicast Promiscuous Mode
4549
 BM_RCTL_MO_SHIFTBM_RCTL_MO_SHIFT 3 e1000e_ich8lan.h Multicast Offset Shift
4550
 BM_RCTL_MO_MASKBM_RCTL_MO_MASK (3 << 3) e1000e_ich8lan.h Multicast Offset Mask
4551
 BM_RCTL_BAMBM_RCTL_BAM 0x0020 e1000e_ich8lan.h Broadcast Accept Mode
4552
 BM_RCTL_PMCFBM_RCTL_PMCF 0x0040 e1000e_ich8lan.h Pass MAC Control Frames
4553
 BM_RCTL_RFCEBM_RCTL_RFCE 0x0080 e1000e_ich8lan.h Rx Flow Control Enable
4554
 HV_LED_CONFIGHV_LED_CONFIG PHY_REG(768, 30) e1000e_ich8lan.h LED Configuration
4555
 HV_MUX_DATA_CTRLHV_MUX_DATA_CTRL PHY_REG(776, 16) e1000e_ich8lan.h 　
4556
 HV_MUX_DATA_CTRL_GEN_TO_MACHV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 e1000e_ich8lan.h 　
4557
 HV_MUX_DATA_CTRL_FORCE_SPEEDHV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 e1000e_ich8lan.h 　
4558
 HV_SCC_UPPERHV_SCC_UPPER PHY_REG(778, 16) e1000e_ich8lan.h Single Collision Count
4559
 HV_SCC_LOWERHV_SCC_LOWER PHY_REG(778, 17) e1000e_ich8lan.h 　
4560
 HV_ECOL_UPPERHV_ECOL_UPPER PHY_REG(778, 18) e1000e_ich8lan.h Excessive Collision Count
4561
 HV_ECOL_LOWERHV_ECOL_LOWER PHY_REG(778, 19) e1000e_ich8lan.h 　
4562
 HV_MCC_UPPERHV_MCC_UPPER PHY_REG(778, 20) e1000e_ich8lan.h Multiple Collision Count
4563
 HV_MCC_LOWERHV_MCC_LOWER PHY_REG(778, 21) e1000e_ich8lan.h 　
4564
 HV_LATECOL_UPPERHV_LATECOL_UPPER PHY_REG(778, 23) e1000e_ich8lan.h Late Collision Count
4565
 HV_LATECOL_LOWERHV_LATECOL_LOWER PHY_REG(778, 24) e1000e_ich8lan.h 　
4566
 HV_COLC_UPPERHV_COLC_UPPER PHY_REG(778, 25) e1000e_ich8lan.h Collision Count
4567
 HV_COLC_LOWERHV_COLC_LOWER PHY_REG(778, 26) e1000e_ich8lan.h 　
4568
 HV_DC_UPPERHV_DC_UPPER PHY_REG(778, 27) e1000e_ich8lan.h Defer Count
4569
 HV_DC_LOWERHV_DC_LOWER PHY_REG(778, 28) e1000e_ich8lan.h 　
4570
 HV_TNCRS_UPPERHV_TNCRS_UPPER PHY_REG(778, 29) e1000e_ich8lan.h Transmit with no CRS
4571
 HV_TNCRS_LOWERHV_TNCRS_LOWER PHY_REG(778, 30) e1000e_ich8lan.h 　
4572
 E1000_FCRTV_PCHE1000_FCRTV_PCH 0x05F40 e1000e_ich8lan.h PCH Flow Control Refresh Timer Value
4573
 E1000_NVM_K1_CONFIGE1000_NVM_K1_CONFIG 0x1B e1000e_ich8lan.h NVM K1 Config Word
4574
 E1000_NVM_K1_ENABLEE1000_NVM_K1_ENABLE 0x1 e1000e_ich8lan.h NVM Enable K1 bit
4575
 HV_SMB_ADDRHV_SMB_ADDR PHY_REG(768, 26) e1000e_ich8lan.h 　
4576
 HV_SMB_ADDR_PEC_ENHV_SMB_ADDR_PEC_EN 0x0200 e1000e_ich8lan.h 　
4577
 HV_SMB_ADDR_VALIDHV_SMB_ADDR_VALID 0x0080 e1000e_ich8lan.h 　
4578
 E1000_STRAPE1000_STRAP 0x0000C e1000e_ich8lan.h 　
4579
 E1000_STRAP_SMBUS_ADDRESS_MASKE1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 e1000e_ich8lan.h 　
4580
 E1000_STRAP_SMBUS_ADDRESS_SHIFTE1000_STRAP_SMBUS_ADDRESS_SHIFT 17 e1000e_ich8lan.h 　
4581
 HV_OEM_BITSHV_OEM_BITS PHY_REG(768, 25) e1000e_ich8lan.h 　
4582
 HV_OEM_BITS_LPLUHV_OEM_BITS_LPLU 0x0004 e1000e_ich8lan.h Low Power Link Up
4583
 HV_OEM_BITS_GBE_DISHV_OEM_BITS_GBE_DIS 0x0040 e1000e_ich8lan.h Gigabit Disable
4584
 HV_OEM_BITS_RESTART_ANHV_OEM_BITS_RESTART_AN 0x0400 e1000e_ich8lan.h Restart Auto-negotiation
4585
 LCD_CFG_PHY_ADDR_BITLCD_CFG_PHY_ADDR_BIT 0x0020 e1000e_ich8lan.h Phy address bit from LCD Config word
4586
 SW_FLAG_TIMEOUTSW_FLAG_TIMEOUT 1000 e1000e_ich8lan.h SW Semaphore flag timeout in milliseconds
4587
 IMS_ICH_ENABLE_MASKIMS_ICH_ENABLE_MASK (\ E1000_IMS_DSW | \ E1000_IMS_PHYINT | \ E1000_IMS_EPRST) e1000e_ich8lan.h 　
4588
 E1000_ICR_LSECPNCE1000_ICR_LSECPNC 0x00004000 e1000e_ich8lan.h PN threshold - client
4589
 E1000_IMS_LSECPNCE1000_IMS_LSECPNC E1000_ICR_LSECPNC e1000e_ich8lan.h PN threshold - client
4590
 E1000_ICS_LSECPNCE1000_ICS_LSECPNC E1000_ICR_LSECPNC e1000e_ich8lan.h PN threshold - client
4591
 E1000_RXDEXT_LINKSEC_STATUS_LSEE1000_RXDEXT_LINKSEC_STATUS_LSE 0x01000000 e1000e_ich8lan.h 　
4592
 E1000_RXDEXT_LINKSEC_ERROR_BIT_E1000_RXDEXT_LINKSEC_ERROR_BIT_ 0x60000000 e1000e_ich8lan.h 　
4593
 E1000_RXDEXT_LINKSEC_ERROR_NO_SE1000_RXDEXT_LINKSEC_ERROR_NO_S 0x20000000 e1000e_ich8lan.h 　
4594
 E1000_RXDEXT_LINKSEC_ERROR_REPLE1000_RXDEXT_LINKSEC_ERROR_REPL 0x40000000 e1000e_ich8lan.h 　
4595
 E1000_RXDEXT_LINKSEC_ERROR_BAD_E1000_RXDEXT_LINKSEC_ERROR_BAD_ 0x60000000 e1000e_ich8lan.h 　
4596
 E1000_FACTPS_MNGCGE1000_FACTPS_MNGCG 0x20000000 e1000e_manage.h 　
4597
 E1000_FWSM_MODE_MASKE1000_FWSM_MODE_MASK 0xE e1000e_manage.h 　
4598
 E1000_FWSM_MODE_SHIFTE1000_FWSM_MODE_SHIFT 1 e1000e_manage.h 　
4599
 E1000_MNG_IAMT_MODEE1000_MNG_IAMT_MODE 0x3 e1000e_manage.h 　
4600
 E1000_MNG_DHCP_COOKIE_LENGTHE1000_MNG_DHCP_COOKIE_LENGTH 0x10 e1000e_manage.h 　
4601
 E1000_MNG_DHCP_COOKIE_OFFSETE1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 e1000e_manage.h 　
4602
 E1000_MNG_DHCP_COMMAND_TIMEOUTE1000_MNG_DHCP_COMMAND_TIMEOUT 10 e1000e_manage.h 　
4603
 E1000_MNG_DHCP_TX_PAYLOAD_CMDE1000_MNG_DHCP_TX_PAYLOAD_CMD 64 e1000e_manage.h 　
4604
 E1000_MNG_DHCP_COOKIE_STATUS_PAE1000_MNG_DHCP_COOKIE_STATUS_PA 0x1 e1000e_manage.h 　
4605
 E1000_MNG_DHCP_COOKIE_STATUS_VLE1000_MNG_DHCP_COOKIE_STATUS_VL 0x2 e1000e_manage.h 　
4606
 E1000_VFTA_ENTRY_SHIFTE1000_VFTA_ENTRY_SHIFT 5 e1000e_manage.h 　
4607
 E1000_VFTA_ENTRY_MASKE1000_VFTA_ENTRY_MASK 0x7F e1000e_manage.h 　
4608
 E1000_VFTA_ENTRY_BIT_SHIFT_MASKE1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F e1000e_manage.h 　
4609
 E1000_HI_MAX_BLOCK_BYTE_LENGTHE1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 e1000e_manage.h Num of bytes in range
4610
 E1000_HI_MAX_BLOCK_DWORD_LENGTHE1000_HI_MAX_BLOCK_DWORD_LENGTH 448 e1000e_manage.h Num of dwords in range
4611
 E1000_HI_COMMAND_TIMEOUTE1000_HI_COMMAND_TIMEOUT 500 e1000e_manage.h Process HI command limit
4612
 E1000_HICR_ENE1000_HICR_EN 0x01 e1000e_manage.h Enable bit - RO
4613
 E1000_HICR_CE1000_HICR_C 0x02 e1000e_manage.h 　
4614
 E1000_HICR_SVE1000_HICR_SV 0x04 e1000e_manage.h Status Validity
4615
 E1000_HICR_FW_RESET_ENABLEE1000_HICR_FW_RESET_ENABLE 0x40 e1000e_manage.h 　
4616
 E1000_HICR_FW_RESETE1000_HICR_FW_RESET 0x80 e1000e_manage.h 　
4617
 E1000_IAMT_SIGNATUREE1000_IAMT_SIGNATURE 0x544D4149 e1000e_manage.h 　
4618
 E1000_STM_OPCODEE1000_STM_OPCODE 0xDB00 e1000e_nvm.h 　
4619
 E1000_MAX_PHY_ADDRE1000_MAX_PHY_ADDR 4 e1000e_phy.h 　
4620
 IGP01E1000_PHY_PORT_CONFIGIGP01E1000_PHY_PORT_CONFIG 0x10 e1000e_phy.h Port Config
4621
 IGP01E1000_PHY_PORT_STATUSIGP01E1000_PHY_PORT_STATUS 0x11 e1000e_phy.h Status
4622
 IGP01E1000_PHY_PORT_CTRLIGP01E1000_PHY_PORT_CTRL 0x12 e1000e_phy.h Control
4623
 IGP01E1000_PHY_LINK_HEALTHIGP01E1000_PHY_LINK_HEALTH 0x13 e1000e_phy.h PHY Link Health
4624
 IGP01E1000_GMII_FIFOIGP01E1000_GMII_FIFO 0x14 e1000e_phy.h GMII FIFO
4625
 IGP01E1000_PHY_CHANNEL_QUALITYIGP01E1000_PHY_CHANNEL_QUALITY 0x15 e1000e_phy.h PHY Channel Quality
4626
 IGP02E1000_PHY_POWER_MGMTIGP02E1000_PHY_POWER_MGMT 0x19 e1000e_phy.h Power Management
4627
 IGP01E1000_PHY_PAGE_SELECTIGP01E1000_PHY_PAGE_SELECT 0x1F e1000e_phy.h Page Select
4628
 BM_PHY_PAGE_SELECTBM_PHY_PAGE_SELECT 22 e1000e_phy.h Page Select for BM
4629
 IGP_PAGE_SHIFTIGP_PAGE_SHIFT 5 e1000e_phy.h 　
4630
 PHY_REG_MASKPHY_REG_MASK 0x1F e1000e_phy.h 　
4631
 BM_PORT_CTRL_PAGEBM_PORT_CTRL_PAGE 769 e1000e_phy.h 　
4632
 BM_PCIE_PAGEBM_PCIE_PAGE 770 e1000e_phy.h 　
4633
 BM_WUC_PAGEBM_WUC_PAGE 800 e1000e_phy.h 　
4634
 BM_WUC_ADDRESS_OPCODEBM_WUC_ADDRESS_OPCODE 0x11 e1000e_phy.h 　
4635
 BM_WUC_DATA_OPCODEBM_WUC_DATA_OPCODE 0x12 e1000e_phy.h 　
4636
 BM_WUC_ENABLE_PAGEBM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE e1000e_phy.h 　
4637
 BM_WUC_ENABLE_REGBM_WUC_ENABLE_REG 17 e1000e_phy.h 　
4638
 BM_WUC_ENABLE_BITBM_WUC_ENABLE_BIT (1 << 2) e1000e_phy.h 　
4639
 BM_WUC_HOST_WU_BITBM_WUC_HOST_WU_BIT (1 << 4) e1000e_phy.h 　
4640
 PHY_UPPER_SHIFTPHY_UPPER_SHIFT 21 e1000e_phy.h 　
4641
 HV_INTC_FC_PAGE_STARTHV_INTC_FC_PAGE_START 768 e1000e_phy.h 　
4642
 I82578_ADDR_REGI82578_ADDR_REG 29 e1000e_phy.h 　
4643
 I82577_ADDR_REGI82577_ADDR_REG 16 e1000e_phy.h 　
4644
 I82577_CFG_REGI82577_CFG_REG 22 e1000e_phy.h 　
4645
 I82577_CFG_ASSERT_CRS_ON_TXI82577_CFG_ASSERT_CRS_ON_TX (1 << 15) e1000e_phy.h 　
4646
 I82577_CFG_ENABLE_DOWNSHIFTI82577_CFG_ENABLE_DOWNSHIFT (3 << 10) e1000e_phy.h auto downshift 100/10
4647
 I82577_CTRL_REGI82577_CTRL_REG 23 e1000e_phy.h 　
4648
 I82577_PHY_CTRL_2I82577_PHY_CTRL_2 18 e1000e_phy.h 　
4649
 I82577_PHY_LBK_CTRLI82577_PHY_LBK_CTRL 19 e1000e_phy.h 　
4650
 I82577_PHY_STATUS_2I82577_PHY_STATUS_2 26 e1000e_phy.h 　
4651
 I82577_PHY_DIAG_STATUSI82577_PHY_DIAG_STATUS 31 e1000e_phy.h 　
4652
 I82577_PHY_STATUS2_REV_POLARITYI82577_PHY_STATUS2_REV_POLARITY 0x0400 e1000e_phy.h 　
4653
 I82577_PHY_STATUS2_MDIXI82577_PHY_STATUS2_MDIX 0x0800 e1000e_phy.h 　
4654
 I82577_PHY_STATUS2_SPEED_MASKI82577_PHY_STATUS2_SPEED_MASK 0x0300 e1000e_phy.h 　
4655
 I82577_PHY_STATUS2_SPEED_1000MBI82577_PHY_STATUS2_SPEED_1000MB 0x0200 e1000e_phy.h 　
4656
 I82577_PHY_STATUS2_SPEED_100MBPI82577_PHY_STATUS2_SPEED_100MBP 0x0100 e1000e_phy.h 　
4657
 I82577_PHY_CTRL2_AUTO_MDIXI82577_PHY_CTRL2_AUTO_MDIX 0x0400 e1000e_phy.h 　
4658
 I82577_PHY_CTRL2_FORCE_MDI_MDIXI82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 e1000e_phy.h 　
4659
 I82577_DSTATUS_CABLE_LENGTHI82577_DSTATUS_CABLE_LENGTH 0x03FC e1000e_phy.h 　
4660
 I82577_DSTATUS_CABLE_LENGTH_SHII82577_DSTATUS_CABLE_LENGTH_SHI 2 e1000e_phy.h 　
4661
 BM_CS_CTRL1BM_CS_CTRL1 16 e1000e_phy.h 　
4662
 BM_CS_CTRL1_ENERGY_DETECTBM_CS_CTRL1_ENERGY_DETECT 0x0300 e1000e_phy.h Enable Energy Detect
4663
 BM_CS_STATUSBM_CS_STATUS 17 e1000e_phy.h 　
4664
 BM_CS_STATUS_ENERGY_DETECTBM_CS_STATUS_ENERGY_DETECT 0x0010 e1000e_phy.h Energy Detect Status
4665
 BM_CS_STATUS_LINK_UPBM_CS_STATUS_LINK_UP 0x0400 e1000e_phy.h 　
4666
 BM_CS_STATUS_RESOLVEDBM_CS_STATUS_RESOLVED 0x0800 e1000e_phy.h 　
4667
 BM_CS_STATUS_SPEED_MASKBM_CS_STATUS_SPEED_MASK 0xC000 e1000e_phy.h 　
4668
 BM_CS_STATUS_SPEED_1000BM_CS_STATUS_SPEED_1000 0x8000 e1000e_phy.h 　
4669
 HV_M_STATUSHV_M_STATUS 26 e1000e_phy.h 　
4670
 HV_M_STATUS_AUTONEG_COMPLETEHV_M_STATUS_AUTONEG_COMPLETE 0x1000 e1000e_phy.h 　
4671
 HV_M_STATUS_SPEED_MASKHV_M_STATUS_SPEED_MASK 0x0300 e1000e_phy.h 　
4672
 HV_M_STATUS_SPEED_1000HV_M_STATUS_SPEED_1000 0x0200 e1000e_phy.h 　
4673
 HV_M_STATUS_LINK_UPHV_M_STATUS_LINK_UP 0x0040 e1000e_phy.h 　
4674
 IGP01E1000_PHY_PCS_INIT_REGIGP01E1000_PHY_PCS_INIT_REG 0x00B4 e1000e_phy.h 　
4675
 IGP01E1000_PHY_POLARITY_MASKIGP01E1000_PHY_POLARITY_MASK 0x0078 e1000e_phy.h 　
4676
 IGP01E1000_PSCR_AUTO_MDIXIGP01E1000_PSCR_AUTO_MDIX 0x1000 e1000e_phy.h 　
4677
 IGP01E1000_PSCR_FORCE_MDI_MDIXIGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 e1000e_phy.h 0=MDI, 1=MDIX
4678
 IGP01E1000_PSCFR_SMART_SPEEDIGP01E1000_PSCFR_SMART_SPEED 0x0080 e1000e_phy.h 　
4679
 IGP01E1000_GMII_FLEX_SPDIGP01E1000_GMII_FLEX_SPD 0x0010 e1000e_phy.h 　
4680
 IGP01E1000_GMII_SPDIGP01E1000_GMII_SPD 0x0020 e1000e_phy.h Enable SPD
4681
 IGP02E1000_PM_SPDIGP02E1000_PM_SPD 0x0001 e1000e_phy.h Smart Power Down
4682
 IGP02E1000_PM_D0_LPLUIGP02E1000_PM_D0_LPLU 0x0002 e1000e_phy.h For D0a states
4683
 IGP02E1000_PM_D3_LPLUIGP02E1000_PM_D3_LPLU 0x0004 e1000e_phy.h For all other states
4684
 IGP01E1000_PLHR_SS_DOWNGRADEIGP01E1000_PLHR_SS_DOWNGRADE 0x8000 e1000e_phy.h 　
4685
 IGP01E1000_PSSR_POLARITY_REVERSIGP01E1000_PSSR_POLARITY_REVERS 0x0002 e1000e_phy.h 　
4686
 IGP01E1000_PSSR_MDIXIGP01E1000_PSSR_MDIX 0x0800 e1000e_phy.h 　
4687
 IGP01E1000_PSSR_SPEED_MASKIGP01E1000_PSSR_SPEED_MASK 0xC000 e1000e_phy.h 　
4688
 IGP01E1000_PSSR_SPEED_1000MBPSIGP01E1000_PSSR_SPEED_1000MBPS 0xC000 e1000e_phy.h 　
4689
 IGP02E1000_PHY_CHANNEL_NUMIGP02E1000_PHY_CHANNEL_NUM 4 e1000e_phy.h 　
4690
 IGP02E1000_PHY_AGC_AIGP02E1000_PHY_AGC_A 0x11B1 e1000e_phy.h 　
4691
 IGP02E1000_PHY_AGC_BIGP02E1000_PHY_AGC_B 0x12B1 e1000e_phy.h 　
4692
 IGP02E1000_PHY_AGC_CIGP02E1000_PHY_AGC_C 0x14B1 e1000e_phy.h 　
4693
 IGP02E1000_PHY_AGC_DIGP02E1000_PHY_AGC_D 0x18B1 e1000e_phy.h 　
4694
 IGP02E1000_AGC_LENGTH_SHIFTIGP02E1000_AGC_LENGTH_SHIFT 9 e1000e_phy.h Course - 15:13, Fine - 12:9
4695
 IGP02E1000_AGC_LENGTH_MASKIGP02E1000_AGC_LENGTH_MASK 0x7F e1000e_phy.h 　
4696
 IGP02E1000_AGC_RANGEIGP02E1000_AGC_RANGE 15 e1000e_phy.h 　
4697
 IGP03E1000_PHY_MISC_CTRLIGP03E1000_PHY_MISC_CTRL 0x1B e1000e_phy.h 　
4698
 IGP03E1000_PHY_MISC_DUPLEX_MANUIGP03E1000_PHY_MISC_DUPLEX_MANU 0x1000 e1000e_phy.h Manually Set Duplex
4699
 E1000_CABLE_LENGTH_UNDEFINEDE1000_CABLE_LENGTH_UNDEFINED 0xFF e1000e_phy.h 　
4700
 E1000_KMRNCTRLSTA_OFFSETE1000_KMRNCTRLSTA_OFFSET 0x001F0000 e1000e_phy.h 　
4701
 E1000_KMRNCTRLSTA_OFFSET_SHIFTE1000_KMRNCTRLSTA_OFFSET_SHIFT 16 e1000e_phy.h 　
4702
 E1000_KMRNCTRLSTA_RENE1000_KMRNCTRLSTA_REN 0x00200000 e1000e_phy.h 　
4703
 E1000_KMRNCTRLSTA_DIAG_OFFSETE1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 e1000e_phy.h Kumeran Diagnostic
4704
 E1000_KMRNCTRLSTA_TIMEOUTSE1000_KMRNCTRLSTA_TIMEOUTS 0x4 e1000e_phy.h Kumeran Timeouts
4705
 E1000_KMRNCTRLSTA_INBAND_PARAME1000_KMRNCTRLSTA_INBAND_PARAM 0x9 e1000e_phy.h Kumeran InBand Parameters
4706
 E1000_KMRNCTRLSTA_DIAG_NELPBKE1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 e1000e_phy.h Nearend Loopback mode
4707
 E1000_KMRNCTRLSTA_K1_CONFIGE1000_KMRNCTRLSTA_K1_CONFIG 0x7 e1000e_phy.h 　
4708
 E1000_KMRNCTRLSTA_K1_ENABLEE1000_KMRNCTRLSTA_K1_ENABLE 0x0002 e1000e_phy.h 　
4709
 IFE_PHY_EXTENDED_STATUS_CONTROLIFE_PHY_EXTENDED_STATUS_CONTROL 0x10 e1000e_phy.h 　
4710
 IFE_PHY_SPECIAL_CONTROLIFE_PHY_SPECIAL_CONTROL 0x11 e1000e_phy.h 100BaseTx PHY Special Control
4711
 IFE_PHY_SPECIAL_CONTROL_LEDIFE_PHY_SPECIAL_CONTROL_LED 0x1B e1000e_phy.h PHY Special and LED Control
4712
 IFE_PHY_MDIX_CONTROLIFE_PHY_MDIX_CONTROL 0x1C e1000e_phy.h MDI/MDI-X Control
4713
 IFE_PESC_POLARITY_REVERSEDIFE_PESC_POLARITY_REVERSED 0x0100 e1000e_phy.h 　
4714
 IFE_PSC_AUTO_POLARITY_DISABLEIFE_PSC_AUTO_POLARITY_DISABLE 0x0010 e1000e_phy.h 　
4715
 IFE_PSC_FORCE_POLARITYIFE_PSC_FORCE_POLARITY 0x0020 e1000e_phy.h 　
4716
 IFE_PSC_DISABLE_DYNAMIC_POWER_DIFE_PSC_DISABLE_DYNAMIC_POWER_D 0x0100 e1000e_phy.h 　
4717
 IFE_PSCL_PROBE_MODEIFE_PSCL_PROBE_MODE 0x0020 e1000e_phy.h 　
4718
 IFE_PSCL_PROBE_LEDS_OFFIFE_PSCL_PROBE_LEDS_OFF 0x0006 e1000e_phy.h Force LEDs 0 and 2 off
4719
 IFE_PSCL_PROBE_LEDS_ONIFE_PSCL_PROBE_LEDS_ON 0x0007 e1000e_phy.h Force LEDs 0 and 2 on
4720
 IFE_PMC_MDIX_STATUSIFE_PMC_MDIX_STATUS 0x0020 e1000e_phy.h 1=MDI-X, 0=MDI
4721
 IFE_PMC_FORCE_MDIXIFE_PMC_FORCE_MDIX 0x0040 e1000e_phy.h 1=force MDI-X, 0=force MDI
4722
 IFE_PMC_AUTO_MDIXIFE_PMC_AUTO_MDIX 0x0080 e1000e_phy.h 1=enable auto MDI/MDI-X, 0=disable
4723
 E1000_CTRLE1000_CTRL 0x00000 e1000e_regs.h Device Control - RW
4724
 E1000_CTRL_DUPE1000_CTRL_DUP 0x00004 e1000e_regs.h Device Control Duplicate (Shadow) - RW
4725
 E1000_STATUSE1000_STATUS 0x00008 e1000e_regs.h Device Status - RO
4726
 E1000_EECDE1000_EECD 0x00010 e1000e_regs.h EEPROM/Flash Control - RW
4727
 E1000_EERDE1000_EERD 0x00014 e1000e_regs.h EEPROM Read - RW
4728
 E1000_CTRL_EXTE1000_CTRL_EXT 0x00018 e1000e_regs.h Extended Device Control - RW
4729
 E1000_FLAE1000_FLA 0x0001C e1000e_regs.h Flash Access - RW
4730
 E1000_MDICE1000_MDIC 0x00020 e1000e_regs.h MDI Control - RW
4731
 E1000_SCTLE1000_SCTL 0x00024 e1000e_regs.h SerDes Control - RW
4732
 E1000_FCALE1000_FCAL 0x00028 e1000e_regs.h Flow Control Address Low - RW
4733
 E1000_FCAHE1000_FCAH 0x0002C e1000e_regs.h Flow Control Address High -RW
4734
 E1000_FEXTE1000_FEXT 0x0002C e1000e_regs.h Future Extended - RW
4735
 E1000_FEXTNVME1000_FEXTNVM 0x00028 e1000e_regs.h Future Extended NVM - RW
4736
 E1000_FCTE1000_FCT 0x00030 e1000e_regs.h Flow Control Type - RW
4737
 E1000_CONNSWE1000_CONNSW 0x00034 e1000e_regs.h Copper/Fiber switch control - RW
4738
 E1000_VETE1000_VET 0x00038 e1000e_regs.h VLAN Ether Type - RW
4739
 E1000_ICRE1000_ICR 0x000C0 e1000e_regs.h Interrupt Cause Read - R/clr
4740
 E1000_ITRE1000_ITR 0x000C4 e1000e_regs.h Interrupt Throttling Rate - RW
4741
 E1000_ICSE1000_ICS 0x000C8 e1000e_regs.h Interrupt Cause Set - WO
4742
 E1000_IMSE1000_IMS 0x000D0 e1000e_regs.h Interrupt Mask Set - RW
4743
 E1000_IMCE1000_IMC 0x000D8 e1000e_regs.h Interrupt Mask Clear - WO
4744
 E1000_IAME1000_IAM 0x000E0 e1000e_regs.h Interrupt Acknowledge Auto Mask
4745
 E1000_IVARE1000_IVAR 0x000E4 e1000e_regs.h Interrupt Vector Allocation Register - RW
4746
 E1000_SVCRE1000_SVCR 0x000F0 e1000e_regs.h 　
4747
 E1000_SVTE1000_SVT 0x000F4 e1000e_regs.h 　
4748
 E1000_RCTLE1000_RCTL 0x00100 e1000e_regs.h Rx Control - RW
4749
 E1000_FCTTVE1000_FCTTV 0x00170 e1000e_regs.h Flow Control Transmit Timer Value - RW
4750
 E1000_TXCWE1000_TXCW 0x00178 e1000e_regs.h Tx Configuration Word - RW
4751
 E1000_RXCWE1000_RXCW 0x00180 e1000e_regs.h Rx Configuration Word - RO
4752
 E1000_PBA_ECCE1000_PBA_ECC 0x01100 e1000e_regs.h PBA ECC Register
4753
 E1000_TCTLE1000_TCTL 0x00400 e1000e_regs.h Tx Control - RW
4754
 E1000_TCTL_EXTE1000_TCTL_EXT 0x00404 e1000e_regs.h Extended Tx Control - RW
4755
 E1000_TIPGE1000_TIPG 0x00410 e1000e_regs.h Tx Inter-packet gap -RW
4756
 E1000_TBTE1000_TBT 0x00448 e1000e_regs.h Tx Burst Timer - RW
4757
 E1000_AITE1000_AIT 0x00458 e1000e_regs.h Adaptive Interframe Spacing Throttle - RW
4758
 E1000_LEDCTLE1000_LEDCTL 0x00E00 e1000e_regs.h LED Control - RW
4759
 E1000_EXTCNF_CTRLE1000_EXTCNF_CTRL 0x00F00 e1000e_regs.h Extended Configuration Control
4760
 E1000_EXTCNF_SIZEE1000_EXTCNF_SIZE 0x00F08 e1000e_regs.h Extended Configuration Size
4761
 E1000_PHY_CTRLE1000_PHY_CTRL 0x00F10 e1000e_regs.h PHY Control Register in CSR
4762
 E1000_PBAE1000_PBA 0x01000 e1000e_regs.h Packet Buffer Allocation - RW
4763
 E1000_PBSE1000_PBS 0x01008 e1000e_regs.h Packet Buffer Size
4764
 E1000_EEMNGCTLE1000_EEMNGCTL 0x01010 e1000e_regs.h MNG EEprom Control
4765
 E1000_EEARBCE1000_EEARBC 0x01024 e1000e_regs.h EEPROM Auto Read Bus Control
4766
 E1000_FLASHTE1000_FLASHT 0x01028 e1000e_regs.h FLASH Timer Register
4767
 E1000_EEWRE1000_EEWR 0x0102C e1000e_regs.h EEPROM Write Register - RW
4768
 E1000_FLSWCTLE1000_FLSWCTL 0x01030 e1000e_regs.h FLASH control register
4769
 E1000_FLSWDATAE1000_FLSWDATA 0x01034 e1000e_regs.h FLASH data register
4770
 E1000_FLSWCNTE1000_FLSWCNT 0x01038 e1000e_regs.h FLASH Access Counter
4771
 E1000_FLOPE1000_FLOP 0x0103C e1000e_regs.h FLASH Opcode Register
4772
 E1000_I2CCMDE1000_I2CCMD 0x01028 e1000e_regs.h SFPI2C Command Register - RW
4773
 E1000_I2CPARAMSE1000_I2CPARAMS 0x0102C e1000e_regs.h SFPI2C Parameters Register - RW
4774
 E1000_WDSTPE1000_WDSTP 0x01040 e1000e_regs.h Watchdog Setup - RW
4775
 E1000_SWDSTSE1000_SWDSTS 0x01044 e1000e_regs.h SW Device Status - RW
4776
 E1000_FRTIMERE1000_FRTIMER 0x01048 e1000e_regs.h Free Running Timer - RW
4777
 E1000_ERTE1000_ERT 0x02008 e1000e_regs.h Early Rx Threshold - RW
4778
 E1000_FCRTLE1000_FCRTL 0x02160 e1000e_regs.h Flow Control Receive Threshold Low - RW
4779
 E1000_FCRTHE1000_FCRTH 0x02168 e1000e_regs.h Flow Control Receive Threshold High - RW
4780
 E1000_PSRCTLE1000_PSRCTL 0x02170 e1000e_regs.h Packet Split Receive Control - RW
4781
 E1000_PBRTHE1000_PBRTH 0x02458 e1000e_regs.h PB Rx Arbitration Threshold - RW
4782
 E1000_FCRTVE1000_FCRTV 0x02460 e1000e_regs.h Flow Control Refresh Timer Value - RW
4783
 E1000_RDPUMBE1000_RDPUMB 0x025CC e1000e_regs.h DMA Rx Descriptor uC Mailbox - RW
4784
 E1000_RDPUADE1000_RDPUAD 0x025D0 e1000e_regs.h DMA Rx Descriptor uC Addr Command - RW
4785
 E1000_RDPUWDE1000_RDPUWD 0x025D4 e1000e_regs.h DMA Rx Descriptor uC Data Write - RW
4786
 E1000_RDPURDE1000_RDPURD 0x025D8 e1000e_regs.h DMA Rx Descriptor uC Data Read - RW
4787
 E1000_RDPUCTLE1000_RDPUCTL 0x025DC e1000e_regs.h DMA Rx Descriptor uC Control - RW
4788
 E1000_RDTRE1000_RDTR 0x02820 e1000e_regs.h Rx Delay Timer - RW
4789
 E1000_RADVE1000_RADV 0x0282C e1000e_regs.h Rx Interrupt Absolute Delay Timer - RW
4790
 E1000_RSRPDE1000_RSRPD 0x02C00 e1000e_regs.h Rx Small Packet Detect - RW
4791
 E1000_RAIDE1000_RAID 0x02C08 e1000e_regs.h Receive Ack Interrupt Delay - RW
4792
 E1000_TXDMACE1000_TXDMAC 0x03000 e1000e_regs.h Tx DMA Control - RW
4793
 E1000_KABGTXDE1000_KABGTXD 0x03004 e1000e_regs.h AFE Band Gap Transmit Ref Data
4794
 E1000_TDFHE1000_TDFH 0x03410 e1000e_regs.h Tx Data FIFO Head - RW
4795
 E1000_TDFTE1000_TDFT 0x03418 e1000e_regs.h Tx Data FIFO Tail - RW
4796
 E1000_TDFHSE1000_TDFHS 0x03420 e1000e_regs.h Tx Data FIFO Head Saved - RW
4797
 E1000_TDFTSE1000_TDFTS 0x03428 e1000e_regs.h Tx Data FIFO Tail Saved - RW
4798
 E1000_TDFPCE1000_TDFPC 0x03430 e1000e_regs.h Tx Data FIFO Packet Count - RW
4799
 E1000_TDPUMBE1000_TDPUMB 0x0357C e1000e_regs.h DMA Tx Descriptor uC Mail Box - RW
4800
 E1000_TDPUADE1000_TDPUAD 0x03580 e1000e_regs.h DMA Tx Descriptor uC Addr Command - RW
4801
 E1000_TDPUWDE1000_TDPUWD 0x03584 e1000e_regs.h DMA Tx Descriptor uC Data Write - RW
4802
 E1000_TDPURDE1000_TDPURD 0x03588 e1000e_regs.h DMA Tx Descriptor uC Data Read - RW
4803
 E1000_TDPUCTLE1000_TDPUCTL 0x0358C e1000e_regs.h DMA Tx Descriptor uC Control - RW
4804
 E1000_DTXCTLE1000_DTXCTL 0x03590 e1000e_regs.h DMA Tx Control - RW
4805
 E1000_TIDVE1000_TIDV 0x03820 e1000e_regs.h Tx Interrupt Delay Value - RW
4806
 E1000_TADVE1000_TADV 0x0382C e1000e_regs.h Tx Interrupt Absolute Delay Val - RW
4807
 E1000_TSPMTE1000_TSPMT 0x03830 e1000e_regs.h TCP Segmentation PAD & Min Threshold - RW
4808
 E1000_CRCERRSE1000_CRCERRS 0x04000 e1000e_regs.h CRC Error Count - R/clr
4809
 E1000_ALGNERRCE1000_ALGNERRC 0x04004 e1000e_regs.h Alignment Error Count - R/clr
4810
 E1000_SYMERRSE1000_SYMERRS 0x04008 e1000e_regs.h Symbol Error Count - R/clr
4811
 E1000_RXERRCE1000_RXERRC 0x0400C e1000e_regs.h Receive Error Count - R/clr
4812
 E1000_MPCE1000_MPC 0x04010 e1000e_regs.h Missed Packet Count - R/clr
4813
 E1000_SCCE1000_SCC 0x04014 e1000e_regs.h Single Collision Count - R/clr
4814
 E1000_ECOLE1000_ECOL 0x04018 e1000e_regs.h Excessive Collision Count - R/clr
4815
 E1000_MCCE1000_MCC 0x0401C e1000e_regs.h Multiple Collision Count - R/clr
4816
 E1000_LATECOLE1000_LATECOL 0x04020 e1000e_regs.h Late Collision Count - R/clr
4817
 E1000_COLCE1000_COLC 0x04028 e1000e_regs.h Collision Count - R/clr
4818
 E1000_DCE1000_DC 0x04030 e1000e_regs.h Defer Count - R/clr
4819
 E1000_TNCRSE1000_TNCRS 0x04034 e1000e_regs.h Tx-No CRS - R/clr
4820
 E1000_SECE1000_SEC 0x04038 e1000e_regs.h Sequence Error Count - R/clr
4821
 E1000_CEXTERRE1000_CEXTERR 0x0403C e1000e_regs.h Carrier Extension Error Count - R/clr
4822
 E1000_RLECE1000_RLEC 0x04040 e1000e_regs.h Receive Length Error Count - R/clr
4823
 E1000_XONRXCE1000_XONRXC 0x04048 e1000e_regs.h XON Rx Count - R/clr
4824
 E1000_XONTXCE1000_XONTXC 0x0404C e1000e_regs.h XON Tx Count - R/clr
4825
 E1000_XOFFRXCE1000_XOFFRXC 0x04050 e1000e_regs.h XOFF Rx Count - R/clr
4826
 E1000_XOFFTXCE1000_XOFFTXC 0x04054 e1000e_regs.h XOFF Tx Count - R/clr
4827
 E1000_FCRUCE1000_FCRUC 0x04058 e1000e_regs.h Flow Control Rx Unsupported Count- R/clr
4828
 E1000_PRC64E1000_PRC64 0x0405C e1000e_regs.h Packets Rx (64 bytes) - R/clr
4829
 E1000_PRC127E1000_PRC127 0x04060 e1000e_regs.h Packets Rx (65-127 bytes) - R/clr
4830
 E1000_PRC255E1000_PRC255 0x04064 e1000e_regs.h Packets Rx (128-255 bytes) - R/clr
4831
 E1000_PRC511E1000_PRC511 0x04068 e1000e_regs.h Packets Rx (255-511 bytes) - R/clr
4832
 E1000_PRC1023E1000_PRC1023 0x0406C e1000e_regs.h Packets Rx (512-1023 bytes) - R/clr
4833
 E1000_PRC1522E1000_PRC1522 0x04070 e1000e_regs.h Packets Rx (1024-1522 bytes) - R/clr
4834
 E1000_GPRCE1000_GPRC 0x04074 e1000e_regs.h Good Packets Rx Count - R/clr
4835
 E1000_BPRCE1000_BPRC 0x04078 e1000e_regs.h Broadcast Packets Rx Count - R/clr
4836
 E1000_MPRCE1000_MPRC 0x0407C e1000e_regs.h Multicast Packets Rx Count - R/clr
4837
 E1000_GPTCE1000_GPTC 0x04080 e1000e_regs.h Good Packets Tx Count - R/clr
4838
 E1000_GORCLE1000_GORCL 0x04088 e1000e_regs.h Good Octets Rx Count Low - R/clr
4839
 E1000_GORCHE1000_GORCH 0x0408C e1000e_regs.h Good Octets Rx Count High - R/clr
4840
 E1000_GOTCLE1000_GOTCL 0x04090 e1000e_regs.h Good Octets Tx Count Low - R/clr
4841
 E1000_GOTCHE1000_GOTCH 0x04094 e1000e_regs.h Good Octets Tx Count High - R/clr
4842
 E1000_RNBCE1000_RNBC 0x040A0 e1000e_regs.h Rx No Buffers Count - R/clr
4843
 E1000_RUCE1000_RUC 0x040A4 e1000e_regs.h Rx Undersize Count - R/clr
4844
 E1000_RFCE1000_RFC 0x040A8 e1000e_regs.h Rx Fragment Count - R/clr
4845
 E1000_ROCE1000_ROC 0x040AC e1000e_regs.h Rx Oversize Count - R/clr
4846
 E1000_RJCE1000_RJC 0x040B0 e1000e_regs.h Rx Jabber Count - R/clr
4847
 E1000_MGTPRCE1000_MGTPRC 0x040B4 e1000e_regs.h Management Packets Rx Count - R/clr
4848
 E1000_MGTPDCE1000_MGTPDC 0x040B8 e1000e_regs.h Management Packets Dropped Count - R/clr
4849
 E1000_MGTPTCE1000_MGTPTC 0x040BC e1000e_regs.h Management Packets Tx Count - R/clr
4850
 E1000_TORLE1000_TORL 0x040C0 e1000e_regs.h Total Octets Rx Low - R/clr
4851
 E1000_TORHE1000_TORH 0x040C4 e1000e_regs.h Total Octets Rx High - R/clr
4852
 E1000_TOTLE1000_TOTL 0x040C8 e1000e_regs.h Total Octets Tx Low - R/clr
4853
 E1000_TOTHE1000_TOTH 0x040CC e1000e_regs.h Total Octets Tx High - R/clr
4854
 E1000_TPRE1000_TPR 0x040D0 e1000e_regs.h Total Packets Rx - R/clr
4855
 E1000_TPTE1000_TPT 0x040D4 e1000e_regs.h Total Packets Tx - R/clr
4856
 E1000_PTC64E1000_PTC64 0x040D8 e1000e_regs.h Packets Tx (64 bytes) - R/clr
4857
 E1000_PTC127E1000_PTC127 0x040DC e1000e_regs.h Packets Tx (65-127 bytes) - R/clr
4858
 E1000_PTC255E1000_PTC255 0x040E0 e1000e_regs.h Packets Tx (128-255 bytes) - R/clr
4859
 E1000_PTC511E1000_PTC511 0x040E4 e1000e_regs.h Packets Tx (256-511 bytes) - R/clr
4860
 E1000_PTC1023E1000_PTC1023 0x040E8 e1000e_regs.h Packets Tx (512-1023 bytes) - R/clr
4861
 E1000_PTC1522E1000_PTC1522 0x040EC e1000e_regs.h Packets Tx (1024-1522 Bytes) - R/clr
4862
 E1000_MPTCE1000_MPTC 0x040F0 e1000e_regs.h Multicast Packets Tx Count - R/clr
4863
 E1000_BPTCE1000_BPTC 0x040F4 e1000e_regs.h Broadcast Packets Tx Count - R/clr
4864
 E1000_TSCTCE1000_TSCTC 0x040F8 e1000e_regs.h TCP Segmentation Context Tx - R/clr
4865
 E1000_TSCTFCE1000_TSCTFC 0x040FC e1000e_regs.h TCP Segmentation Context Tx Fail - R/clr
4866
 E1000_IACE1000_IAC 0x04100 e1000e_regs.h Interrupt Assertion Count
4867
 E1000_ICRXPTCE1000_ICRXPTC 0x04104 e1000e_regs.h Interrupt Cause Rx Pkt Timer Expire Count
4868
 E1000_ICRXATCE1000_ICRXATC 0x04108 e1000e_regs.h Interrupt Cause Rx Abs Timer Expire Count
4869
 E1000_ICTXPTCE1000_ICTXPTC 0x0410C e1000e_regs.h Interrupt Cause Tx Pkt Timer Expire Count
4870
 E1000_ICTXATCE1000_ICTXATC 0x04110 e1000e_regs.h Interrupt Cause Tx Abs Timer Expire Count
4871
 E1000_ICTXQECE1000_ICTXQEC 0x04118 e1000e_regs.h Interrupt Cause Tx Queue Empty Count
4872
 E1000_ICTXQMTCE1000_ICTXQMTC 0x0411C e1000e_regs.h Interrupt Cause Tx Queue Min Thresh Count
4873
 E1000_ICRXDMTCE1000_ICRXDMTC 0x04120 e1000e_regs.h Interrupt Cause Rx Desc Min Thresh Count
4874
 E1000_ICRXOCE1000_ICRXOC 0x04124 e1000e_regs.h Interrupt Cause Receiver Overrun Count
4875
 E1000_CRC_OFFSETE1000_CRC_OFFSET 0x05F50 e1000e_regs.h CRC Offset register
4876
 E1000_PCS_CFG0E1000_PCS_CFG0 0x04200 e1000e_regs.h PCS Configuration 0 - RW
4877
 E1000_PCS_LCTLE1000_PCS_LCTL 0x04208 e1000e_regs.h PCS Link Control - RW
4878
 E1000_PCS_LSTATE1000_PCS_LSTAT 0x0420C e1000e_regs.h PCS Link Status - RO
4879
 E1000_CBTMPCE1000_CBTMPC 0x0402C e1000e_regs.h Circuit Breaker Tx Packet Count
4880
 E1000_HTDPMCE1000_HTDPMC 0x0403C e1000e_regs.h Host Transmit Discarded Packets
4881
 E1000_CBRDPCE1000_CBRDPC 0x04044 e1000e_regs.h Circuit Breaker Rx Dropped Count
4882
 E1000_CBRMPCE1000_CBRMPC 0x040FC e1000e_regs.h Circuit Breaker Rx Packet Count
4883
 E1000_RPTHCE1000_RPTHC 0x04104 e1000e_regs.h Rx Packets To Host
4884
 E1000_HGPTCE1000_HGPTC 0x04118 e1000e_regs.h Host Good Packets Tx Count
4885
 E1000_HTCBDPCE1000_HTCBDPC 0x04124 e1000e_regs.h Host Tx Circuit Breaker Dropped Count
4886
 E1000_HGORCLE1000_HGORCL 0x04128 e1000e_regs.h Host Good Octets Received Count Low
4887
 E1000_HGORCHE1000_HGORCH 0x0412C e1000e_regs.h Host Good Octets Received Count High
4888
 E1000_HGOTCLE1000_HGOTCL 0x04130 e1000e_regs.h Host Good Octets Transmit Count Low
4889
 E1000_HGOTCHE1000_HGOTCH 0x04134 e1000e_regs.h Host Good Octets Transmit Count High
4890
 E1000_LENERRSE1000_LENERRS 0x04138 e1000e_regs.h Length Errors Count
4891
 E1000_SCVPCE1000_SCVPC 0x04228 e1000e_regs.h SerDes/SGMII Code Violation Pkt Count
4892
 E1000_HRMPCE1000_HRMPC 0x0A018 e1000e_regs.h Header Redirection Missed Packet Count
4893
 E1000_PCS_ANADVE1000_PCS_ANADV 0x04218 e1000e_regs.h AN advertisement - RW
4894
 E1000_PCS_LPABE1000_PCS_LPAB 0x0421C e1000e_regs.h Link Partner Ability - RW
4895
 E1000_PCS_NPTXE1000_PCS_NPTX 0x04220 e1000e_regs.h AN Next Page Transmit - RW
4896
 E1000_PCS_LPABNPE1000_PCS_LPABNP 0x04224 e1000e_regs.h Link Partner Ability Next Page - RW
4897
 E1000_1GSTAT_RCVE1000_1GSTAT_RCV 0x04228 e1000e_regs.h 1GSTAT Code Violation Packet Count - RW
4898
 E1000_RXCSUME1000_RXCSUM 0x05000 e1000e_regs.h Rx Checksum Control - RW
4899
 E1000_RLPMLE1000_RLPML 0x05004 e1000e_regs.h Rx Long Packet Max Length
4900
 E1000_RFCTLE1000_RFCTL 0x05008 e1000e_regs.h Receive Filter Control
4901
 E1000_MTAE1000_MTA 0x05200 e1000e_regs.h Multicast Table Array - RW Array
4902
 E1000_RAE1000_RA 0x05400 e1000e_regs.h Receive Address - RW Array
4903
 E1000_VFTAE1000_VFTA 0x05600 e1000e_regs.h VLAN Filter Table Array - RW Array
4904
 E1000_VT_CTLE1000_VT_CTL 0x0581C e1000e_regs.h VMDq Control - RW
4905
 E1000_VFQA0E1000_VFQA0 0x0B000 e1000e_regs.h VLAN Filter Queue Array 0 - RW Array
4906
 E1000_VFQA1E1000_VFQA1 0x0B200 e1000e_regs.h VLAN Filter Queue Array 1 - RW Array
4907
 E1000_WUCE1000_WUC 0x05800 e1000e_regs.h Wakeup Control - RW
4908
 E1000_WUFCE1000_WUFC 0x05808 e1000e_regs.h Wakeup Filter Control - RW
4909
 E1000_WUSE1000_WUS 0x05810 e1000e_regs.h Wakeup Status - RO
4910
 E1000_MANCE1000_MANC 0x05820 e1000e_regs.h Management Control - RW
4911
 E1000_IPAVE1000_IPAV 0x05838 e1000e_regs.h IP Address Valid - RW
4912
 E1000_IP4ATE1000_IP4AT 0x05840 e1000e_regs.h IPv4 Address Table - RW Array
4913
 E1000_IP6ATE1000_IP6AT 0x05880 e1000e_regs.h IPv6 Address Table - RW Array
4914
 E1000_WUPLE1000_WUPL 0x05900 e1000e_regs.h Wakeup Packet Length - RW
4915
 E1000_WUPME1000_WUPM 0x05A00 e1000e_regs.h Wakeup Packet Memory - RO A
4916
 E1000_PBACLE1000_PBACL 0x05B68 e1000e_regs.h MSIx PBA Clear - Read/Write 1's to clear
4917
 E1000_FFLTE1000_FFLT 0x05F00 e1000e_regs.h Flexible Filter Length Table - RW Array
4918
 E1000_HOST_IFE1000_HOST_IF 0x08800 e1000e_regs.h Host Interface
4919
 E1000_FFMTE1000_FFMT 0x09000 e1000e_regs.h Flexible Filter Mask Table - RW Array
4920
 E1000_FFVTE1000_FFVT 0x09800 e1000e_regs.h Flexible Filter Value Table - RW Array
4921
 E1000_KMRNCTRLSTAE1000_KMRNCTRLSTA 0x00034 e1000e_regs.h MAC-PHY interface - RW
4922
 E1000_MDPHYAE1000_MDPHYA 0x0003C e1000e_regs.h PHY address - RW
4923
 E1000_MANC2HE1000_MANC2H 0x05860 e1000e_regs.h Management Control To Host - RW
4924
 E1000_SW_FW_SYNCE1000_SW_FW_SYNC 0x05B5C e1000e_regs.h Software-Firmware Synchronization - RW
4925
 E1000_CCMCTLE1000_CCMCTL 0x05B48 e1000e_regs.h CCM Control Register
4926
 E1000_GIOCTLE1000_GIOCTL 0x05B44 e1000e_regs.h GIO Analog Control Register
4927
 E1000_SCCTLE1000_SCCTL 0x05B4C e1000e_regs.h PCIc PLL Configuration Register
4928
 E1000_GCRE1000_GCR 0x05B00 e1000e_regs.h PCI-Ex Control
4929
 E1000_GCR2E1000_GCR2 0x05B64 e1000e_regs.h PCI-Ex Control #2
4930
 E1000_GSCL_1E1000_GSCL_1 0x05B10 e1000e_regs.h PCI-Ex Statistic Control #1
4931
 E1000_GSCL_2E1000_GSCL_2 0x05B14 e1000e_regs.h PCI-Ex Statistic Control #2
4932
 E1000_GSCL_3E1000_GSCL_3 0x05B18 e1000e_regs.h PCI-Ex Statistic Control #3
4933
 E1000_GSCL_4E1000_GSCL_4 0x05B1C e1000e_regs.h PCI-Ex Statistic Control #4
4934
 E1000_FACTPSE1000_FACTPS 0x05B30 e1000e_regs.h Function Active and Power State to MNG
4935
 E1000_SWSME1000_SWSM 0x05B50 e1000e_regs.h SW Semaphore
4936
 E1000_FWSME1000_FWSM 0x05B54 e1000e_regs.h FW Semaphore
4937
 E1000_SWSM2E1000_SWSM2 0x05B58 e1000e_regs.h Driver-only SW semaphore (not used by BOOT agents)
4938
 E1000_DCA_IDE1000_DCA_ID 0x05B70 e1000e_regs.h DCA Requester ID Information - RO
4939
 E1000_DCA_CTRLE1000_DCA_CTRL 0x05B74 e1000e_regs.h DCA Control - RW
4940
 E1000_FFLT_DBGE1000_FFLT_DBG 0x05F04 e1000e_regs.h Debug Register
4941
 E1000_HICRE1000_HICR 0x08F00 e1000e_regs.h Host Interface Control
4942
 E1000_CPUVECE1000_CPUVEC 0x02C10 e1000e_regs.h CPU Vector Register - RW
4943
 E1000_MRQCE1000_MRQC 0x05818 e1000e_regs.h Multiple Receive Control - RW
4944
 E1000_IMIRVPE1000_IMIRVP 0x05AC0 e1000e_regs.h Immediate Interrupt Rx VLAN Priority - RW
4945
 E1000_MSIXPBAE1000_MSIXPBA 0x0E000 e1000e_regs.h MSI-X Pending bit array
4946
 E1000_RSSIME1000_RSSIM 0x05864 e1000e_regs.h RSS Interrupt Mask
4947
 E1000_RSSIRE1000_RSSIR 0x05868 e1000e_regs.h RSS Interrupt Request
4948
 E1000_RXMTRLE1000_RXMTRL 0x0B634 e1000e_regs.h Time sync Rx EtherType and Msg Type - RW
4949
 E1000_RXUDPE1000_RXUDP 0x0B638 e1000e_regs.h Time Sync Rx UDP Port - RW
4950
 M88E1000_CABLE_LENGTH_TABLE_SIZM88E1000_CABLE_LENGTH_TABLE_SIZ (sizeof(e1000_m88_cable_length_table) / \ sizeof(e1000_m88_cable_length_table[0])) igb_phy.c 　
4951
 IGP02E1000_CABLE_LENGTH_TABLE_SIGP02E1000_CABLE_LENGTH_TABLE_S (sizeof(e1000_igp_2_cable_length_table) / \ sizeof(e1000_igp_2_cable_length_table[0])) igb_phy.c 　
4952
 IGB_START_ITRIGB_START_ITR 648 igb.h ~6000 ints/sec
4953
 IGB_INT_MODE_LEGACYIGB_INT_MODE_LEGACY 0 igb.h 　
4954
 IGB_INT_MODE_MSIIGB_INT_MODE_MSI 1 igb.h 　
4955
 IGB_INT_MODE_MSIXIGB_INT_MODE_MSIX 2 igb.h 　
4956
 IGB_DEFAULT_TXDIGB_DEFAULT_TXD 256 igb.h 　
4957
 IGB_MIN_TXDIGB_MIN_TXD 80 igb.h 　
4958
 IGB_MAX_TXDIGB_MAX_TXD 4096 igb.h 　
4959
 IGB_DEFAULT_RXDIGB_DEFAULT_RXD 256 igb.h 　
4960
 IGB_MIN_RXDIGB_MIN_RXD 80 igb.h 　
4961
 IGB_MAX_RXDIGB_MAX_RXD 4096 igb.h 　
4962
 IGB_MIN_ITR_USECSIGB_MIN_ITR_USECS 10 igb.h 100k irq/sec
4963
 IGB_MAX_ITR_USECSIGB_MAX_ITR_USECS 8191 igb.h 120 irq/sec
4964
 NON_Q_VECTORSNON_Q_VECTORS 1 igb.h 　
4965
 MAX_Q_VECTORSMAX_Q_VECTORS 8 igb.h 　
4966
 IGB_MAX_RX_QUEUESIGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \ (hw->mac.type > e1000_82575 ? 8 : 4)) igb.h 　
4967
 IGB_ABS_MAX_TX_QUEUESIGB_ABS_MAX_TX_QUEUES 8 igb.h 　
4968
 IGB_MAX_TX_QUEUESIGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES igb.h 　
4969
 IGB_MAX_VF_MC_ENTRIESIGB_MAX_VF_MC_ENTRIES 30 igb.h 　
4970
 IGB_MAX_VF_FUNCTIONSIGB_MAX_VF_FUNCTIONS 8 igb.h 　
4971
 IGB_MAX_VFTA_ENTRIESIGB_MAX_VFTA_ENTRIES 128 igb.h 　
4972
 IGB_MAX_UTA_ENTRIESIGB_MAX_UTA_ENTRIES 128 igb.h 　
4973
 MAX_EMULATION_MAC_ADDRSMAX_EMULATION_MAC_ADDRS 16 igb.h 　
4974
 OUI_LENOUI_LEN 3 igb.h 　
4975
 IGB_VF_FLAG_CTSIGB_VF_FLAG_CTS 0x00000001 igb.h VF is clear to send data
4976
 IGB_VF_FLAG_UNI_PROMISCIGB_VF_FLAG_UNI_PROMISC 0x00000002 igb.h VF has unicast promisc
4977
 IGB_VF_FLAG_MULTI_PROMISCIGB_VF_FLAG_MULTI_PROMISC 0x00000004 igb.h VF has multicast promisc
4978
 IGB_RX_PTHRESHIGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) igb.h 　
4979
 IGB_RX_HTHRESHIGB_RX_HTHRESH 8 igb.h 　
4980
 IGB_RX_WTHRESHIGB_RX_WTHRESH 1 igb.h 　
4981
 IGB_TX_PTHRESHIGB_TX_PTHRESH 8 igb.h 　
4982
 IGB_TX_HTHRESHIGB_TX_HTHRESH 1 igb.h 　
4983
 IGB_TX_WTHRESHIGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ adapter->msix_entries) ? 0 : 16) igb.h 　
4984
 MAXIMUM_ETHERNET_VLAN_SIZEMAXIMUM_ETHERNET_VLAN_SIZE 1522 igb.h 　
4985
 IGB_RXBUFFER_128IGB_RXBUFFER_128 128 igb.h Used for packet split
4986
 IGB_RXBUFFER_256IGB_RXBUFFER_256 256 igb.h Used for packet split
4987
 IGB_RXBUFFER_512IGB_RXBUFFER_512 512 igb.h 　
4988
 IGB_RXBUFFER_1024IGB_RXBUFFER_1024 1024 igb.h 　
4989
 IGB_RXBUFFER_2048IGB_RXBUFFER_2048 2048 igb.h 　
4990
 IGB_RXBUFFER_4096IGB_RXBUFFER_4096 4096 igb.h 　
4991
 IGB_RXBUFFER_8192IGB_RXBUFFER_8192 8192 igb.h 　
4992
 IGB_RXBUFFER_16384IGB_RXBUFFER_16384 16384 igb.h 　
4993
 IGB_PBA_BYTES_SHIFTIGB_PBA_BYTES_SHIFT 0xA igb.h 　
4994
 IGB_TX_HEAD_ADDR_SHIFTIGB_TX_HEAD_ADDR_SHIFT 7 igb.h 　
4995
 IGB_PBA_TX_MASKIGB_PBA_TX_MASK 0xFFFF0000 igb.h 　
4996
 IGB_FC_PAUSE_TIMEIGB_FC_PAUSE_TIME 0x0680 igb.h 858 usec
4997
 IGB_TX_QUEUE_WAKEIGB_TX_QUEUE_WAKE 32 igb.h 　
4998
 IGB_RX_BUFFER_WRITEIGB_RX_BUFFER_WRITE 16 igb.h Must be power of 2
4999
 AUTO_ALL_MODESAUTO_ALL_MODES 0 igb.h 　
5000
 IGB_EEPROM_APMEIGB_EEPROM_APME 0x0400 igb.h 　
5001
 IGB_MASTER_SLAVEIGB_MASTER_SLAVE e1000_ms_hw_default igb.h 　
5002
 IGB_MNG_VLAN_NONEIGB_MNG_VLAN_NONE -1 igb.h 　
5003
 IGB_ADVTXD_DCMDIGB_ADVTXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) igb.h 　
5004
 MAX_MSIX_COUNTMAX_MSIX_COUNT 10 igb.h 　
5005
 IGB_FLAG_HAS_MSIIGB_FLAG_HAS_MSI (1 << 0) igb.h 　
5006
 IGB_FLAG_MSI_ENABLEIGB_FLAG_MSI_ENABLE (1 << 1) igb.h 　
5007
 IGB_FLAG_DCA_ENABLEDIGB_FLAG_DCA_ENABLED (1 << 3) igb.h 　
5008
 IGB_FLAG_LLI_PUSHIGB_FLAG_LLI_PUSH (1 << 4) igb.h 　
5009
 IGB_FLAG_IN_NETPOLLIGB_FLAG_IN_NETPOLL (1 << 5) igb.h 　
5010
 IGB_FLAG_QUAD_PORT_AIGB_FLAG_QUAD_PORT_A (1 << 6) igb.h 　
5011
 IGB_FLAG_QUEUE_PAIRSIGB_FLAG_QUEUE_PAIRS (1 << 7) igb.h 　
5012
 IGB_82576_TSYNC_SHIFTIGB_82576_TSYNC_SHIFT 19 igb.h 　
5013
 ID_LED_DEFAULT_82575_SERDESID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_DEF1_DEF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_OFF1_ON2)) igb_82575.h 　
5014
 E1000_RAR_ENTRIES_82575E1000_RAR_ENTRIES_82575 16 igb_82575.h 　
5015
 E1000_RAR_ENTRIES_82576E1000_RAR_ENTRIES_82576 24 igb_82575.h 　
5016
 E1000_TXD_DTYP_ADV_CE1000_TXD_DTYP_ADV_C 0x2 igb_82575.h Advanced Context Descriptor
5017
 E1000_TXD_DTYP_ADV_DE1000_TXD_DTYP_ADV_D 0x3 igb_82575.h Advanced Data Descriptor
5018
 E1000_ADV_TXD_CMD_DEXTE1000_ADV_TXD_CMD_DEXT 0x20 igb_82575.h Descriptor extension (0 = legacy)
5019
 E1000_ADV_TUCMD_IPV4E1000_ADV_TUCMD_IPV4 0x2 igb_82575.h IP Packet Type: 1=IPv4
5020
 E1000_ADV_TUCMD_IPV6E1000_ADV_TUCMD_IPV6 0x0 igb_82575.h IP Packet Type: 0=IPv6
5021
 E1000_ADV_TUCMD_L4T_UDPE1000_ADV_TUCMD_L4T_UDP 0x0 igb_82575.h L4 Packet TYPE of UDP
5022
 E1000_ADV_TUCMD_L4T_TCPE1000_ADV_TUCMD_L4T_TCP 0x4 igb_82575.h L4 Packet TYPE of TCP
5023
 E1000_ADV_TUCMD_MKRREQE1000_ADV_TUCMD_MKRREQ 0x10 igb_82575.h Indicates markers are required
5024
 E1000_ADV_DCMD_EOPE1000_ADV_DCMD_EOP 0x1 igb_82575.h End of Packet
5025
 E1000_ADV_DCMD_IFCSE1000_ADV_DCMD_IFCS 0x2 igb_82575.h Insert FCS (Ethernet CRC)
5026
 E1000_ADV_DCMD_RSE1000_ADV_DCMD_RS 0x8 igb_82575.h Report Status
5027
 E1000_ADV_DCMD_VLEE1000_ADV_DCMD_VLE 0x40 igb_82575.h Add VLAN tag
5028
 E1000_ADV_DCMD_TSEE1000_ADV_DCMD_TSE 0x80 igb_82575.h TCP Seg enable
5029
 E1000_CTRL_EXT_NSICRE1000_CTRL_EXT_NSICR 0x00000001 igb_82575.h Disable Intr Clear all on read
5030
 E1000_SRRCTL_BSIZEPKT_SHIFTE1000_SRRCTL_BSIZEPKT_SHIFT 10 igb_82575.h Shift _right_
5031
 E1000_SRRCTL_BSIZEHDRSIZE_MASKE1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 igb_82575.h 　
5032
 E1000_SRRCTL_BSIZEHDRSIZE_SHIFTE1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 igb_82575.h Shift _left_
5033
 E1000_SRRCTL_DESCTYPE_LEGACYE1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 igb_82575.h 　
5034
 E1000_SRRCTL_DESCTYPE_ADV_ONEBUE1000_SRRCTL_DESCTYPE_ADV_ONEBU 0x02000000 igb_82575.h 　
5035
 E1000_SRRCTL_DESCTYPE_HDR_SPLITE1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 igb_82575.h 　
5036
 E1000_SRRCTL_DESCTYPE_HDR_SPLITE1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x0A000000 igb_82575.h 　
5037
 E1000_SRRCTL_DESCTYPE_HDR_REPLIE1000_SRRCTL_DESCTYPE_HDR_REPLI 0x06000000 igb_82575.h 　
5038
 E1000_SRRCTL_DESCTYPE_HDR_REPLIE1000_SRRCTL_DESCTYPE_HDR_REPLI 0x08000000 igb_82575.h 　
5039
 E1000_SRRCTL_DESCTYPE_MASKE1000_SRRCTL_DESCTYPE_MASK 0x0E000000 igb_82575.h 　
5040
 E1000_SRRCTL_DROP_ENE1000_SRRCTL_DROP_EN 0x80000000 igb_82575.h 　
5041
 E1000_SRRCTL_BSIZEPKT_MASKE1000_SRRCTL_BSIZEPKT_MASK 0x0000007F igb_82575.h 　
5042
 E1000_SRRCTL_BSIZEHDR_MASKE1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 igb_82575.h 　
5043
 E1000_TX_HEAD_WB_ENABLEE1000_TX_HEAD_WB_ENABLE 0x1 igb_82575.h 　
5044
 E1000_TX_SEQNUM_WB_ENABLEE1000_TX_SEQNUM_WB_ENABLE 0x2 igb_82575.h 　
5045
 E1000_MRQC_ENABLE_RSS_4QE1000_MRQC_ENABLE_RSS_4Q 0x00000002 igb_82575.h 　
5046
 E1000_MRQC_ENABLE_VMDQE1000_MRQC_ENABLE_VMDQ 0x00000003 igb_82575.h 　
5047
 E1000_MRQC_ENABLE_VMDQ_RSS_2QE1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 igb_82575.h 　
5048
 E1000_MRQC_RSS_FIELD_IPV4_UDPE1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 igb_82575.h 　
5049
 E1000_MRQC_RSS_FIELD_IPV6_UDPE1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 igb_82575.h 　
5050
 E1000_MRQC_RSS_FIELD_IPV6_UDP_EE1000_MRQC_RSS_FIELD_IPV6_UDP_E 0x01000000 igb_82575.h 　
5051
 E1000_VMRCTL_MIRROR_PORT_SHIFTE1000_VMRCTL_MIRROR_PORT_SHIFT 8 igb_82575.h 　
5052
 E1000_VMRCTL_MIRROR_DSTPORT_MASE1000_VMRCTL_MIRROR_DSTPORT_MAS (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT) igb_82575.h 　
5053
 E1000_VMRCTL_POOL_MIRROR_ENABLEE1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) igb_82575.h 　
5054
 E1000_VMRCTL_UPLINK_MIRROR_ENABE1000_VMRCTL_UPLINK_MIRROR_ENAB (1 << 1) igb_82575.h 　
5055
 E1000_VMRCTL_DOWNLINK_MIRROR_ENE1000_VMRCTL_DOWNLINK_MIRROR_EN (1 << 2) igb_82575.h 　
5056
 E1000_EICR_TX_QUEUEE1000_EICR_TX_QUEUE ( \ E1000_EICR_TX_QUEUE0 | \ E1000_EICR_TX_QUEUE1 | \ E1000_EICR_TX_QUEUE2 | \ E1000_EICR_TX_QUEUE3) igb_82575.h 　
5057
 E1000_EICR_RX_QUEUEE1000_EICR_RX_QUEUE ( \ E1000_EICR_RX_QUEUE0 | \ E1000_EICR_RX_QUEUE1 | \ E1000_EICR_RX_QUEUE2 | \ E1000_EICR_RX_QUEUE3) igb_82575.h 　
5058
 E1000_EIMS_RX_QUEUEE1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE igb_82575.h 　
5059
 E1000_EIMS_TX_QUEUEE1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE igb_82575.h 　
5060
 EIMS_ENABLE_MASKEIMS_ENABLE_MASK ( \ E1000_EIMS_RX_QUEUE | \ E1000_EIMS_TX_QUEUE | \ E1000_EIMS_TCP_TIMER | \ E1000_EIMS_OTHER) igb_82575.h 　
5061
 E1000_IMIR_PORT_IM_ENE1000_IMIR_PORT_IM_EN 0x00010000 igb_82575.h TCP port enable
5062
 E1000_IMIR_PORT_BPE1000_IMIR_PORT_BP 0x00020000 igb_82575.h TCP port check bypass
5063
 E1000_IMIREXT_SIZE_BPE1000_IMIREXT_SIZE_BP 0x00001000 igb_82575.h Packet size bypass
5064
 E1000_IMIREXT_CTRL_URGE1000_IMIREXT_CTRL_URG 0x00002000 igb_82575.h Check URG bit in header
5065
 E1000_IMIREXT_CTRL_ACKE1000_IMIREXT_CTRL_ACK 0x00004000 igb_82575.h Check ACK bit in header
5066
 E1000_IMIREXT_CTRL_PSHE1000_IMIREXT_CTRL_PSH 0x00008000 igb_82575.h Check PSH bit in header
5067
 E1000_IMIREXT_CTRL_RSTE1000_IMIREXT_CTRL_RST 0x00010000 igb_82575.h Check RST bit in header
5068
 E1000_IMIREXT_CTRL_SYNE1000_IMIREXT_CTRL_SYN 0x00020000 igb_82575.h Check SYN bit in header
5069
 E1000_IMIREXT_CTRL_FINE1000_IMIREXT_CTRL_FIN 0x00040000 igb_82575.h Check FIN bit in header
5070
 E1000_IMIREXT_CTRL_BPE1000_IMIREXT_CTRL_BP 0x00080000 igb_82575.h Bypass check of ctrl bits
5071
 E1000_RXDADV_RSSTYPE_MASKE1000_RXDADV_RSSTYPE_MASK 0x0000000F igb_82575.h 　
5072
 E1000_RXDADV_RSSTYPE_SHIFTE1000_RXDADV_RSSTYPE_SHIFT 12 igb_82575.h 　
5073
 E1000_RXDADV_HDRBUFLEN_MASKE1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 igb_82575.h 　
5074
 E1000_RXDADV_HDRBUFLEN_SHIFTE1000_RXDADV_HDRBUFLEN_SHIFT 5 igb_82575.h 　
5075
 E1000_RXDADV_SPLITHEADER_ENE1000_RXDADV_SPLITHEADER_EN 0x00001000 igb_82575.h 　
5076
 E1000_RXDADV_SPHE1000_RXDADV_SPH 0x8000 igb_82575.h 　
5077
 E1000_RXDADV_STAT_TSE1000_RXDADV_STAT_TS 0x10000 igb_82575.h Pkt was time stamped
5078
 E1000_RXDADV_ERR_HBOE1000_RXDADV_ERR_HBO 0x00800000 igb_82575.h 　
5079
 E1000_RXDADV_RSSTYPE_NONEE1000_RXDADV_RSSTYPE_NONE 0x00000000 igb_82575.h 　
5080
 E1000_RXDADV_RSSTYPE_IPV4_TCPE1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 igb_82575.h 　
5081
 E1000_RXDADV_RSSTYPE_IPV4E1000_RXDADV_RSSTYPE_IPV4 0x00000002 igb_82575.h 　
5082
 E1000_RXDADV_RSSTYPE_IPV6_TCPE1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 igb_82575.h 　
5083
 E1000_RXDADV_RSSTYPE_IPV6_EXE1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 igb_82575.h 　
5084
 E1000_RXDADV_RSSTYPE_IPV6E1000_RXDADV_RSSTYPE_IPV6 0x00000005 igb_82575.h 　
5085
 E1000_RXDADV_RSSTYPE_IPV6_TCP_EE1000_RXDADV_RSSTYPE_IPV6_TCP_E 0x00000006 igb_82575.h 　
5086
 E1000_RXDADV_RSSTYPE_IPV4_UDPE1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 igb_82575.h 　
5087
 E1000_RXDADV_RSSTYPE_IPV6_UDPE1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 igb_82575.h 　
5088
 E1000_RXDADV_RSSTYPE_IPV6_UDP_EE1000_RXDADV_RSSTYPE_IPV6_UDP_E 0x00000009 igb_82575.h 　
5089
 E1000_RXDADV_PKTTYPE_NONEE1000_RXDADV_PKTTYPE_NONE 0x00000000 igb_82575.h 　
5090
 E1000_RXDADV_PKTTYPE_IPV4E1000_RXDADV_PKTTYPE_IPV4 0x00000010 igb_82575.h IPV4 hdr present
5091
 E1000_RXDADV_PKTTYPE_IPV4_EXE1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 igb_82575.h IPV4 hdr + extensions
5092
 E1000_RXDADV_PKTTYPE_IPV6E1000_RXDADV_PKTTYPE_IPV6 0x00000040 igb_82575.h IPV6 hdr present
5093
 E1000_RXDADV_PKTTYPE_IPV6_EXE1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 igb_82575.h IPV6 hdr + extensions
5094
 E1000_RXDADV_PKTTYPE_TCPE1000_RXDADV_PKTTYPE_TCP 0x00000100 igb_82575.h TCP hdr present
5095
 E1000_RXDADV_PKTTYPE_UDPE1000_RXDADV_PKTTYPE_UDP 0x00000200 igb_82575.h UDP hdr present
5096
 E1000_RXDADV_PKTTYPE_SCTPE1000_RXDADV_PKTTYPE_SCTP 0x00000400 igb_82575.h SCTP hdr present
5097
 E1000_RXDADV_PKTTYPE_NFSE1000_RXDADV_PKTTYPE_NFS 0x00000800 igb_82575.h NFS hdr present
5098
 E1000_RXDADV_PKTTYPE_IPSEC_ESPE1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 igb_82575.h IPSec ESP
5099
 E1000_RXDADV_PKTTYPE_IPSEC_AHE1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 igb_82575.h IPSec AH
5100
 E1000_RXDADV_PKTTYPE_LINKSECE1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 igb_82575.h LinkSec Encap
5101
 E1000_RXDADV_PKTTYPE_ETQFE1000_RXDADV_PKTTYPE_ETQF 0x00008000 igb_82575.h PKTTYPE is ETQF index
5102
 E1000_RXDADV_PKTTYPE_ETQF_MASKE1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 igb_82575.h ETQF has 8 indices
5103
 E1000_RXDADV_PKTTYPE_ETQF_SHIFTE1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 igb_82575.h Right-shift 4 bits
5104
 E1000_RXDADV_LNKSEC_STATUS_SECPE1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 igb_82575.h 　
5105
 E1000_RXDADV_LNKSEC_ERROR_BIT_ME1000_RXDADV_LNKSEC_ERROR_BIT_M 0x18000000 igb_82575.h 　
5106
 E1000_RXDADV_LNKSEC_ERROR_NO_SAE1000_RXDADV_LNKSEC_ERROR_NO_SA 0x08000000 igb_82575.h 　
5107
 E1000_RXDADV_LNKSEC_ERROR_REPLAE1000_RXDADV_LNKSEC_ERROR_REPLA 0x10000000 igb_82575.h 　
5108
 E1000_RXDADV_LNKSEC_ERROR_BAD_SE1000_RXDADV_LNKSEC_ERROR_BAD_S 0x18000000 igb_82575.h 　
5109
 E1000_RXDADV_IPSEC_STATUS_SECPE1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 igb_82575.h 　
5110
 E1000_RXDADV_IPSEC_ERROR_BIT_MAE1000_RXDADV_IPSEC_ERROR_BIT_MA 0x18000000 igb_82575.h 　
5111
 E1000_RXDADV_IPSEC_ERROR_INVALIE1000_RXDADV_IPSEC_ERROR_INVALI 0x08000000 igb_82575.h 　
5112
 E1000_RXDADV_IPSEC_ERROR_INVALIE1000_RXDADV_IPSEC_ERROR_INVALI 0x10000000 igb_82575.h 　
5113
 E1000_RXDADV_IPSEC_ERROR_AUTHENE1000_RXDADV_IPSEC_ERROR_AUTHEN 0x18000000 igb_82575.h 　
5114
 E1000_ADVTXD_DTYP_CTXTE1000_ADVTXD_DTYP_CTXT 0x00200000 igb_82575.h Advanced Context Descriptor
5115
 E1000_ADVTXD_DTYP_DATAE1000_ADVTXD_DTYP_DATA 0x00300000 igb_82575.h Advanced Data Descriptor
5116
 E1000_ADVTXD_DCMD_EOPE1000_ADVTXD_DCMD_EOP 0x01000000 igb_82575.h End of Packet
5117
 E1000_ADVTXD_DCMD_IFCSE1000_ADVTXD_DCMD_IFCS 0x02000000 igb_82575.h Insert FCS (Ethernet CRC)
5118
 E1000_ADVTXD_DCMD_RSE1000_ADVTXD_DCMD_RS 0x08000000 igb_82575.h Report Status
5119
 E1000_ADVTXD_DCMD_DDTYP_ISCSIE1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 igb_82575.h DDP hdr type or iSCSI
5120
 E1000_ADVTXD_DCMD_DEXTE1000_ADVTXD_DCMD_DEXT 0x20000000 igb_82575.h Descriptor extension (1=Adv)
5121
 E1000_ADVTXD_DCMD_VLEE1000_ADVTXD_DCMD_VLE 0x40000000 igb_82575.h VLAN pkt enable
5122
 E1000_ADVTXD_DCMD_TSEE1000_ADVTXD_DCMD_TSE 0x80000000 igb_82575.h TCP Seg enable
5123
 E1000_ADVTXD_MAC_LINKSECE1000_ADVTXD_MAC_LINKSEC 0x00040000 igb_82575.h Apply LinkSec on packet
5124
 E1000_ADVTXD_MAC_TSTAMPE1000_ADVTXD_MAC_TSTAMP 0x00080000 igb_82575.h IEEE1588 Timestamp packet
5125
 E1000_ADVTXD_STAT_SN_CRCE1000_ADVTXD_STAT_SN_CRC 0x00000002 igb_82575.h NXTSEQ/SEED present in WB
5126
 E1000_ADVTXD_IDX_SHIFTE1000_ADVTXD_IDX_SHIFT 4 igb_82575.h Adv desc Index shift
5127
 E1000_ADVTXD_POPTS_ISCO_1STE1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 igb_82575.h 1st TSO of iSCSI PDU
5128
 E1000_ADVTXD_POPTS_ISCO_MDLE1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 igb_82575.h Middle TSO of iSCSI PDU
5129
 E1000_ADVTXD_POPTS_ISCO_LASTE1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 igb_82575.h Last TSO of iSCSI PDU
5130
 E1000_ADVTXD_POPTS_ISCO_FULLE1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 igb_82575.h 1st&Last TSO-full iSCSI PDU
5131
 E1000_ADVTXD_POPTS_IPSECE1000_ADVTXD_POPTS_IPSEC 0x00000400 igb_82575.h IPSec offload request
5132
 E1000_ADVTXD_PAYLEN_SHIFTE1000_ADVTXD_PAYLEN_SHIFT 14 igb_82575.h Adv desc PAYLEN shift
5133
 E1000_ADVTXD_MACLEN_SHIFTE1000_ADVTXD_MACLEN_SHIFT 9 igb_82575.h Adv ctxt desc mac len shift
5134
 E1000_ADVTXD_VLAN_SHIFTE1000_ADVTXD_VLAN_SHIFT 16 igb_82575.h Adv ctxt vlan tag shift
5135
 E1000_ADVTXD_TUCMD_IPV4E1000_ADVTXD_TUCMD_IPV4 0x00000400 igb_82575.h IP Packet Type: 1=IPv4
5136
 E1000_ADVTXD_TUCMD_IPV6E1000_ADVTXD_TUCMD_IPV6 0x00000000 igb_82575.h IP Packet Type: 0=IPv6
5137
 E1000_ADVTXD_TUCMD_L4T_UDPE1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 igb_82575.h L4 Packet TYPE of UDP
5138
 E1000_ADVTXD_TUCMD_L4T_TCPE1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 igb_82575.h L4 Packet TYPE of TCP
5139
 E1000_ADVTXD_TUCMD_L4T_SCTPE1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 igb_82575.h L4 Packet TYPE of SCTP
5140
 E1000_ADVTXD_TUCMD_IPSEC_TYPE_EE1000_ADVTXD_TUCMD_IPSEC_TYPE_E 0x00002000 igb_82575.h IPSec Type ESP
5141
 E1000_ADVTXD_TUCMD_IPSEC_ENCRYPE1000_ADVTXD_TUCMD_IPSEC_ENCRYP 0x00004000 igb_82575.h 　
5142
 E1000_ADVTXD_TUCMD_MKRREQE1000_ADVTXD_TUCMD_MKRREQ 0x00002000 igb_82575.h Req requires Markers and CRC
5143
 E1000_ADVTXD_L4LEN_SHIFTE1000_ADVTXD_L4LEN_SHIFT 8 igb_82575.h Adv ctxt L4LEN shift
5144
 E1000_ADVTXD_MSS_SHIFTE1000_ADVTXD_MSS_SHIFT 16 igb_82575.h Adv ctxt MSS shift
5145
 E1000_ADVTXD_IPSEC_SA_INDEX_MASE1000_ADVTXD_IPSEC_SA_INDEX_MAS 0x000000FF igb_82575.h 　
5146
 E1000_ADVTXD_IPSEC_ESP_LEN_MASKE1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF igb_82575.h 　
5147
 E1000_TXDCTL_QUEUE_ENABLEE1000_TXDCTL_QUEUE_ENABLE 0x02000000 igb_82575.h Enable specific Tx Queue
5148
 E1000_TXDCTL_SWFLSHE1000_TXDCTL_SWFLSH 0x04000000 igb_82575.h Tx Desc. write-back flushing
5149
 E1000_TXDCTL_PRIORITYE1000_TXDCTL_PRIORITY 0x08000000 igb_82575.h 　
5150
 E1000_RXDCTL_QUEUE_ENABLEE1000_RXDCTL_QUEUE_ENABLE 0x02000000 igb_82575.h Enable specific Rx Queue
5151
 E1000_RXDCTL_SWFLSHE1000_RXDCTL_SWFLSH 0x04000000 igb_82575.h Rx Desc. write-back flushing
5152
 E1000_DCA_CTRL_DCA_ENABLEE1000_DCA_CTRL_DCA_ENABLE 0x00000000 igb_82575.h DCA Enable
5153
 E1000_DCA_CTRL_DCA_DISABLEE1000_DCA_CTRL_DCA_DISABLE 0x00000001 igb_82575.h DCA Disable
5154
 E1000_DCA_CTRL_DCA_MODE_CB1E1000_DCA_CTRL_DCA_MODE_CB1 0x00 igb_82575.h DCA Mode CB1
5155
 E1000_DCA_CTRL_DCA_MODE_CB2E1000_DCA_CTRL_DCA_MODE_CB2 0x02 igb_82575.h DCA Mode CB2
5156
 E1000_DCA_RXCTRL_CPUID_MASKE1000_DCA_RXCTRL_CPUID_MASK 0x0000001F igb_82575.h Rx CPUID Mask
5157
 E1000_DCA_RXCTRL_DESC_DCA_ENE1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) igb_82575.h DCA Rx Desc enable
5158
 E1000_DCA_RXCTRL_HEAD_DCA_ENE1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) igb_82575.h DCA Rx Desc header enable
5159
 E1000_DCA_RXCTRL_DATA_DCA_ENE1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) igb_82575.h DCA Rx Desc payload enable
5160
 E1000_DCA_TXCTRL_CPUID_MASKE1000_DCA_TXCTRL_CPUID_MASK 0x0000001F igb_82575.h Tx CPUID Mask
5161
 E1000_DCA_TXCTRL_DESC_DCA_ENE1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) igb_82575.h DCA Tx Desc enable
5162
 E1000_DCA_TXCTRL_TX_WB_RO_ENE1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) igb_82575.h Tx Desc writeback RO bit
5163
 E1000_DCA_TXCTRL_CPUID_MASK_825E1000_DCA_TXCTRL_CPUID_MASK_825 0xFF000000 igb_82575.h Tx CPUID Mask
5164
 E1000_DCA_RXCTRL_CPUID_MASK_825E1000_DCA_RXCTRL_CPUID_MASK_825 0xFF000000 igb_82575.h Rx CPUID Mask
5165
 E1000_DCA_TXCTRL_CPUID_SHIFT_82E1000_DCA_TXCTRL_CPUID_SHIFT_82 24 igb_82575.h Tx CPUID
5166
 E1000_DCA_RXCTRL_CPUID_SHIFT_82E1000_DCA_RXCTRL_CPUID_SHIFT_82 24 igb_82575.h Rx CPUID
5167
 E1000_ICR_LSECPNSE1000_ICR_LSECPNS 0x00000020 igb_82575.h PN threshold - server
5168
 E1000_IMS_LSECPNSE1000_IMS_LSECPNS E1000_ICR_LSECPNS igb_82575.h PN threshold - server
5169
 E1000_ICS_LSECPNSE1000_ICS_LSECPNS E1000_ICR_LSECPNS igb_82575.h PN threshold - server
5170
 E1000_ETQF_FILTER_ENABLEE1000_ETQF_FILTER_ENABLE (1 << 26) igb_82575.h 　
5171
 E1000_ETQF_IMM_INTE1000_ETQF_IMM_INT (1 << 29) igb_82575.h 　
5172
 E1000_ETQF_1588E1000_ETQF_1588 (1 << 30) igb_82575.h 　
5173
 E1000_ETQF_QUEUE_ENABLEE1000_ETQF_QUEUE_ENABLE (1 << 31) igb_82575.h 　
5174
 E1000_ETQF_FILTER_EAPOLE1000_ETQF_FILTER_EAPOL 0 igb_82575.h 　
5175
 E1000_FTQF_VF_BPE1000_FTQF_VF_BP 0x00008000 igb_82575.h 　
5176
 E1000_FTQF_1588_TIME_STAMPE1000_FTQF_1588_TIME_STAMP 0x08000000 igb_82575.h 　
5177
 E1000_FTQF_MASKE1000_FTQF_MASK 0xF0000000 igb_82575.h 　
5178
 E1000_FTQF_MASK_PROTO_BPE1000_FTQF_MASK_PROTO_BP 0x10000000 igb_82575.h 　
5179
 E1000_FTQF_MASK_SOURCE_ADDR_BPE1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 igb_82575.h 　
5180
 E1000_FTQF_MASK_DEST_ADDR_BPE1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 igb_82575.h 　
5181
 E1000_FTQF_MASK_SOURCE_PORT_BPE1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 igb_82575.h 　
5182
 E1000_NVM_APME_82575E1000_NVM_APME_82575 0x0400 igb_82575.h 　
5183
 MAX_NUM_VFSMAX_NUM_VFS 8 igb_82575.h 　
5184
 E1000_DTXSWC_MAC_SPOOF_MASKE1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF igb_82575.h Per VF MAC spoof control
5185
 E1000_DTXSWC_VLAN_SPOOF_MASKE1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 igb_82575.h Per VF VLAN spoof control
5186
 E1000_DTXSWC_LLE_MASKE1000_DTXSWC_LLE_MASK 0x00FF0000 igb_82575.h Per VF Local LB enables
5187
 E1000_DTXSWC_VLAN_SPOOF_SHIFTE1000_DTXSWC_VLAN_SPOOF_SHIFT 8 igb_82575.h 　
5188
 E1000_DTXSWC_LLE_SHIFTE1000_DTXSWC_LLE_SHIFT 16 igb_82575.h 　
5189
 E1000_DTXSWC_VMDQ_LOOPBACK_ENE1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) igb_82575.h global VF LB enable
5190
 E1000_VT_CTL_DEFAULT_POOL_SHIFTE1000_VT_CTL_DEFAULT_POOL_SHIFT 7 igb_82575.h 　
5191
 E1000_VT_CTL_DEFAULT_POOL_MASKE1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) igb_82575.h 　
5192
 E1000_VT_CTL_IGNORE_MACE1000_VT_CTL_IGNORE_MAC (1 << 28) igb_82575.h 　
5193
 E1000_VT_CTL_DISABLE_DEF_POOLE1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) igb_82575.h 　
5194
 E1000_VT_CTL_VM_REPL_ENE1000_VT_CTL_VM_REPL_EN (1 << 30) igb_82575.h 　
5195
 E1000_VMOLR_RLPML_MASKE1000_VMOLR_RLPML_MASK 0x00003FFF igb_82575.h Long Packet Maximum Length mask
5196
 E1000_VMOLR_LPEE1000_VMOLR_LPE 0x00010000 igb_82575.h Accept Long packet
5197
 E1000_VMOLR_RSSEE1000_VMOLR_RSSE 0x00020000 igb_82575.h Enable RSS
5198
 E1000_VMOLR_AUPEE1000_VMOLR_AUPE 0x01000000 igb_82575.h Accept untagged packets
5199
 E1000_VMOLR_ROMPEE1000_VMOLR_ROMPE 0x02000000 igb_82575.h Accept overflow multicast
5200
 E1000_VMOLR_ROPEE1000_VMOLR_ROPE 0x04000000 igb_82575.h Accept overflow unicast
5201
 E1000_VMOLR_BAME1000_VMOLR_BAM 0x08000000 igb_82575.h Accept Broadcast packets
5202
 E1000_VMOLR_MPMEE1000_VMOLR_MPME 0x10000000 igb_82575.h Multicast promiscuous mode
5203
 E1000_VMOLR_STRVLANE1000_VMOLR_STRVLAN 0x40000000 igb_82575.h Vlan stripping enable
5204
 E1000_VMOLR_STRCRCE1000_VMOLR_STRCRC 0x80000000 igb_82575.h CRC stripping enable
5205
 E1000_VLVF_ARRAY_SIZEE1000_VLVF_ARRAY_SIZE 32 igb_82575.h 　
5206
 E1000_VLVF_VLANID_MASKE1000_VLVF_VLANID_MASK 0x00000FFF igb_82575.h 　
5207
 E1000_VLVF_POOLSEL_SHIFTE1000_VLVF_POOLSEL_SHIFT 12 igb_82575.h 　
5208
 E1000_VLVF_POOLSEL_MASKE1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) igb_82575.h 　
5209
 E1000_VLVF_LVLANE1000_VLVF_LVLAN 0x00100000 igb_82575.h 　
5210
 E1000_VLVF_VLANID_ENABLEE1000_VLVF_VLANID_ENABLE 0x80000000 igb_82575.h 　
5211
 E1000_VF_INIT_TIMEOUTE1000_VF_INIT_TIMEOUT 200 igb_82575.h Number of retries to clear RSTI
5212
 E1000_IOVCTLE1000_IOVCTL 0x05BBC igb_82575.h 　
5213
 E1000_IOVCTL_REUSE_VFQE1000_IOVCTL_REUSE_VFQ 0x00000001 igb_82575.h 　
5214
 E1000_RPLOLR_STRVLANE1000_RPLOLR_STRVLAN 0x40000000 igb_82575.h 　
5215
 E1000_RPLOLR_STRCRCE1000_RPLOLR_STRCRC 0x80000000 igb_82575.h 　
5216
 E1000_DTXCTL_8023LLE1000_DTXCTL_8023LL 0x0004 igb_82575.h 　
5217
 E1000_DTXCTL_VLAN_ADDEDE1000_DTXCTL_VLAN_ADDED 0x0008 igb_82575.h 　
5218
 E1000_DTXCTL_OOS_ENABLEE1000_DTXCTL_OOS_ENABLE 0x0010 igb_82575.h 　
5219
 E1000_DTXCTL_MDP_ENE1000_DTXCTL_MDP_EN 0x0020 igb_82575.h 　
5220
 E1000_DTXCTL_SPOOF_INTE1000_DTXCTL_SPOOF_INT 0x0040 igb_82575.h 　
5221
 ALL_QUEUESALL_QUEUES 0xFFFF igb_82575.h 　
5222
 E1000_RXPBS_SIZE_MASK_82576E1000_RXPBS_SIZE_MASK_82576 0x0000007F igb_82575.h 　
5223
 CARRIER_EXTENSIONCARRIER_EXTENSION 0x0F igb_api.h 　
5224
 REQ_TX_DESCRIPTOR_MULTIPLEREQ_TX_DESCRIPTOR_MULTIPLE 8 igb_defines.h 　
5225
 REQ_RX_DESCRIPTOR_MULTIPLEREQ_RX_DESCRIPTOR_MULTIPLE 8 igb_defines.h 　
5226
 E1000_WUC_APMEE1000_WUC_APME 0x00000001 igb_defines.h APM Enable
5227
 E1000_WUC_PME_ENE1000_WUC_PME_EN 0x00000002 igb_defines.h PME Enable
5228
 E1000_WUC_PME_STATUSE1000_WUC_PME_STATUS 0x00000004 igb_defines.h PME Status
5229
 E1000_WUC_APMPMEE1000_WUC_APMPME 0x00000008 igb_defines.h Assert PME on APM Wakeup
5230
 E1000_WUC_LSCWEE1000_WUC_LSCWE 0x00000010 igb_defines.h Link Status wake up enable
5231
 E1000_WUC_LSCWOE1000_WUC_LSCWO 0x00000020 igb_defines.h Link Status wake up override
5232
 E1000_WUC_SPME1000_WUC_SPM 0x80000000 igb_defines.h Enable SPM
5233
 E1000_WUC_PHY_WAKEE1000_WUC_PHY_WAKE 0x00000100 igb_defines.h if PHY supports wakeup
5234
 E1000_WUFC_LNKCE1000_WUFC_LNKC 0x00000001 igb_defines.h Link Status Change Wakeup Enable
5235
 E1000_WUFC_MAGE1000_WUFC_MAG 0x00000002 igb_defines.h Magic Packet Wakeup Enable
5236
 E1000_WUFC_EXE1000_WUFC_EX 0x00000004 igb_defines.h Directed Exact Wakeup Enable
5237
 E1000_WUFC_MCE1000_WUFC_MC 0x00000008 igb_defines.h Directed Multicast Wakeup Enable
5238
 E1000_WUFC_BCE1000_WUFC_BC 0x00000010 igb_defines.h Broadcast Wakeup Enable
5239
 E1000_WUFC_ARPE1000_WUFC_ARP 0x00000020 igb_defines.h ARP Request Packet Wakeup Enable
5240
 E1000_WUFC_IPV4E1000_WUFC_IPV4 0x00000040 igb_defines.h Directed IPv4 Packet Wakeup Enable
5241
 E1000_WUFC_IPV6E1000_WUFC_IPV6 0x00000080 igb_defines.h Directed IPv6 Packet Wakeup Enable
5242
 E1000_WUFC_IGNORE_TCOE1000_WUFC_IGNORE_TCO 0x00008000 igb_defines.h Ignore WakeOn TCO packets
5243
 E1000_WUFC_FLX0E1000_WUFC_FLX0 0x00010000 igb_defines.h Flexible Filter 0 Enable
5244
 E1000_WUFC_FLX1E1000_WUFC_FLX1 0x00020000 igb_defines.h Flexible Filter 1 Enable
5245
 E1000_WUFC_FLX2E1000_WUFC_FLX2 0x00040000 igb_defines.h Flexible Filter 2 Enable
5246
 E1000_WUFC_FLX3E1000_WUFC_FLX3 0x00080000 igb_defines.h Flexible Filter 3 Enable
5247
 E1000_WUFC_FLX4E1000_WUFC_FLX4 0x00100000 igb_defines.h Flexible Filter 4 Enable
5248
 E1000_WUFC_FLX5E1000_WUFC_FLX5 0x00200000 igb_defines.h Flexible Filter 5 Enable
5249
 E1000_WUFC_ALL_FILTERSE1000_WUFC_ALL_FILTERS 0x000F00FF igb_defines.h Mask for all wakeup filters
5250
 E1000_WUFC_FLX_OFFSETE1000_WUFC_FLX_OFFSET 16 igb_defines.h Offset to the Flexible Filters bits
5251
 E1000_WUFC_FLX_FILTERSE1000_WUFC_FLX_FILTERS 0x000F0000 igb_defines.h Mask for the 4 flexible filters
5252
 E1000_WUFC_EXT_FLX_FILTERSE1000_WUFC_EXT_FLX_FILTERS 0x00300000 igb_defines.h Ext. FLX filter mask
5253
 E1000_WUS_LNKCE1000_WUS_LNKC E1000_WUFC_LNKC igb_defines.h 　
5254
 E1000_WUS_MAGE1000_WUS_MAG E1000_WUFC_MAG igb_defines.h 　
5255
 E1000_WUS_EXE1000_WUS_EX E1000_WUFC_EX igb_defines.h 　
5256
 E1000_WUS_MCE1000_WUS_MC E1000_WUFC_MC igb_defines.h 　
5257
 E1000_WUS_BCE1000_WUS_BC E1000_WUFC_BC igb_defines.h 　
5258
 E1000_WUS_ARPE1000_WUS_ARP E1000_WUFC_ARP igb_defines.h 　
5259
 E1000_WUS_IPV4E1000_WUS_IPV4 E1000_WUFC_IPV4 igb_defines.h 　
5260
 E1000_WUS_IPV6E1000_WUS_IPV6 E1000_WUFC_IPV6 igb_defines.h 　
5261
 E1000_WUS_FLX0E1000_WUS_FLX0 E1000_WUFC_FLX0 igb_defines.h 　
5262
 E1000_WUS_FLX1E1000_WUS_FLX1 E1000_WUFC_FLX1 igb_defines.h 　
5263
 E1000_WUS_FLX2E1000_WUS_FLX2 E1000_WUFC_FLX2 igb_defines.h 　
5264
 E1000_WUS_FLX3E1000_WUS_FLX3 E1000_WUFC_FLX3 igb_defines.h 　
5265
 E1000_WUS_FLX_FILTERSE1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS igb_defines.h 　
5266
 E1000_WUPL_LENGTH_MASKE1000_WUPL_LENGTH_MASK 0x0FFF igb_defines.h Only the lower 12 bits are valid
5267
 E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 4 igb_defines.h 　
5268
 E1000_EXT_FLEXIBLE_FILTER_COUNTE1000_EXT_FLEXIBLE_FILTER_COUNT 2 igb_defines.h 　
5269
 E1000_FHFT_LENGTH_OFFSETE1000_FHFT_LENGTH_OFFSET 0xFC igb_defines.h Length byte in FHFT
5270
 E1000_FHFT_LENGTH_MASKE1000_FHFT_LENGTH_MASK 0x0FF igb_defines.h Length in lower byte
5271
 E1000_FLEXIBLE_FILTER_SIZE_MAXE1000_FLEXIBLE_FILTER_SIZE_MAX 128 igb_defines.h 　
5272
 E1000_FFLT_SIZEE1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX igb_defines.h 　
5273
 E1000_FFMT_SIZEE1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX igb_defines.h 　
5274
 E1000_FFVT_SIZEE1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX igb_defines.h 　
5275
 E1000_CTRL_EXT_GPI0_ENE1000_CTRL_EXT_GPI0_EN 0x00000001 igb_defines.h Maps SDP4 to GPI0
5276
 E1000_CTRL_EXT_GPI1_ENE1000_CTRL_EXT_GPI1_EN 0x00000002 igb_defines.h Maps SDP5 to GPI1
5277
 E1000_CTRL_EXT_PHYINT_ENE1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN igb_defines.h 　
5278
 E1000_CTRL_EXT_GPI2_ENE1000_CTRL_EXT_GPI2_EN 0x00000004 igb_defines.h Maps SDP6 to GPI2
5279
 E1000_CTRL_EXT_GPI3_ENE1000_CTRL_EXT_GPI3_EN 0x00000008 igb_defines.h Maps SDP7 to GPI3
5280
 E1000_CTRL_EXT_SDP4_DATAE1000_CTRL_EXT_SDP4_DATA 0x00000010 igb_defines.h Value of SW Definable Pin 4
5281
 E1000_CTRL_EXT_SDP5_DATAE1000_CTRL_EXT_SDP5_DATA 0x00000020 igb_defines.h Value of SW Definable Pin 5
5282
 E1000_CTRL_EXT_PHY_INTE1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA igb_defines.h 　
5283
 E1000_CTRL_EXT_SDP6_DATAE1000_CTRL_EXT_SDP6_DATA 0x00000040 igb_defines.h Value of SW Definable Pin 6
5284
 E1000_CTRL_EXT_SDP3_DATAE1000_CTRL_EXT_SDP3_DATA 0x00000080 igb_defines.h Value of SW Definable Pin 3
5285
 E1000_CTRL_EXT_SDP4_DIRE1000_CTRL_EXT_SDP4_DIR 0x00000100 igb_defines.h Direction of SDP4 0=in 1=out
5286
 E1000_CTRL_EXT_SDP5_DIRE1000_CTRL_EXT_SDP5_DIR 0x00000200 igb_defines.h Direction of SDP5 0=in 1=out
5287
 E1000_CTRL_EXT_SDP6_DIRE1000_CTRL_EXT_SDP6_DIR 0x00000400 igb_defines.h Direction of SDP6 0=in 1=out
5288
 E1000_CTRL_EXT_SDP3_DIRE1000_CTRL_EXT_SDP3_DIR 0x00000800 igb_defines.h Direction of SDP3 0=in 1=out
5289
 E1000_CTRL_EXT_ASDCHKE1000_CTRL_EXT_ASDCHK 0x00001000 igb_defines.h Initiate an ASD sequence
5290
 E1000_CTRL_EXT_EE_RSTE1000_CTRL_EXT_EE_RST 0x00002000 igb_defines.h Reinitialize from EEPROM
5291
 E1000_CTRL_EXT_IPSE1000_CTRL_EXT_IPS 0x00004000 igb_defines.h Invert Power State
5292
 E1000_CTRL_EXT_PFRSTDE1000_CTRL_EXT_PFRSTD 0x00004000 igb_defines.h 　
5293
 E1000_CTRL_EXT_SPD_BYPSE1000_CTRL_EXT_SPD_BYPS 0x00008000 igb_defines.h Speed Select Bypass
5294
 E1000_CTRL_EXT_RO_DISE1000_CTRL_EXT_RO_DIS 0x00020000 igb_defines.h Relaxed Ordering disable
5295
 E1000_CTRL_EXT_DMA_DYN_CLK_ENE1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 igb_defines.h DMA Dynamic Clock Gating
5296
 E1000_CTRL_EXT_LINK_MODE_MASKE1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 igb_defines.h 　
5297
 E1000_CTRL_EXT_LINK_MODE_GMIIE1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 igb_defines.h 　
5298
 E1000_CTRL_EXT_LINK_MODE_TBIE1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 igb_defines.h 　
5299
 E1000_CTRL_EXT_LINK_MODE_KMRNE1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 igb_defines.h 　
5300
 E1000_CTRL_EXT_LINK_MODE_PCIE_SE1000_CTRL_EXT_LINK_MODE_PCIE_S 0x00C00000 igb_defines.h 　
5301
 E1000_CTRL_EXT_LINK_MODE_PCIX_SE1000_CTRL_EXT_LINK_MODE_PCIX_S 0x00800000 igb_defines.h 　
5302
 E1000_CTRL_EXT_LINK_MODE_SGMIIE1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 igb_defines.h 　
5303
 E1000_CTRL_EXT_EIAMEE1000_CTRL_EXT_EIAME 0x01000000 igb_defines.h 　
5304
 E1000_CTRL_EXT_IRCAE1000_CTRL_EXT_IRCA 0x00000001 igb_defines.h 　
5305
 E1000_CTRL_EXT_WR_WMARK_MASKE1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 igb_defines.h 　
5306
 E1000_CTRL_EXT_WR_WMARK_256E1000_CTRL_EXT_WR_WMARK_256 0x00000000 igb_defines.h 　
5307
 E1000_CTRL_EXT_WR_WMARK_320E1000_CTRL_EXT_WR_WMARK_320 0x01000000 igb_defines.h 　
5308
 E1000_CTRL_EXT_WR_WMARK_384E1000_CTRL_EXT_WR_WMARK_384 0x02000000 igb_defines.h 　
5309
 E1000_CTRL_EXT_WR_WMARK_448E1000_CTRL_EXT_WR_WMARK_448 0x03000000 igb_defines.h 　
5310
 E1000_CTRL_EXT_CANCE1000_CTRL_EXT_CANC 0x04000000 igb_defines.h Int delay cancellation
5311
 E1000_CTRL_EXT_DRV_LOADE1000_CTRL_EXT_DRV_LOAD 0x10000000 igb_defines.h Driver loaded bit for FW
5312
 E1000_CTRL_EXT_IAMEE1000_CTRL_EXT_IAME 0x08000000 igb_defines.h Int acknowledge Auto-mask
5313
 E1000_CRTL_EXT_PB_PARENE1000_CRTL_EXT_PB_PAREN 0x01000000 igb_defines.h packet buffer parity error
5314
 E1000_CTRL_EXT_DF_PARENE1000_CTRL_EXT_DF_PAREN 0x02000000 igb_defines.h descriptor FIFO parity
5315
 E1000_CTRL_EXT_GHOST_PARENE1000_CTRL_EXT_GHOST_PAREN 0x40000000 igb_defines.h 　
5316
 E1000_CTRL_EXT_PBA_CLRE1000_CTRL_EXT_PBA_CLR 0x80000000 igb_defines.h PBA Clear
5317
 E1000_I2CCMD_REG_ADDR_SHIFTE1000_I2CCMD_REG_ADDR_SHIFT 16 igb_defines.h 　
5318
 E1000_I2CCMD_REG_ADDRE1000_I2CCMD_REG_ADDR 0x00FF0000 igb_defines.h 　
5319
 E1000_I2CCMD_PHY_ADDR_SHIFTE1000_I2CCMD_PHY_ADDR_SHIFT 24 igb_defines.h 　
5320
 E1000_I2CCMD_PHY_ADDRE1000_I2CCMD_PHY_ADDR 0x07000000 igb_defines.h 　
5321
 E1000_I2CCMD_OPCODE_READE1000_I2CCMD_OPCODE_READ 0x08000000 igb_defines.h 　
5322
 E1000_I2CCMD_OPCODE_WRITEE1000_I2CCMD_OPCODE_WRITE 0x00000000 igb_defines.h 　
5323
 E1000_I2CCMD_RESETE1000_I2CCMD_RESET 0x10000000 igb_defines.h 　
5324
 E1000_I2CCMD_READYE1000_I2CCMD_READY 0x20000000 igb_defines.h 　
5325
 E1000_I2CCMD_INTERRUPT_ENAE1000_I2CCMD_INTERRUPT_ENA 0x40000000 igb_defines.h 　
5326
 E1000_I2CCMD_ERRORE1000_I2CCMD_ERROR 0x80000000 igb_defines.h 　
5327
 E1000_MAX_SGMII_PHY_REG_ADDRE1000_MAX_SGMII_PHY_REG_ADDR 255 igb_defines.h 　
5328
 E1000_I2CCMD_PHY_TIMEOUTE1000_I2CCMD_PHY_TIMEOUT 200 igb_defines.h 　
5329
 E1000_IVAR_VALIDE1000_IVAR_VALID 0x80 igb_defines.h 　
5330
 E1000_GPIE_NSICRE1000_GPIE_NSICR 0x00000001 igb_defines.h 　
5331
 E1000_GPIE_MSIX_MODEE1000_GPIE_MSIX_MODE 0x00000010 igb_defines.h 　
5332
 E1000_GPIE_EIAMEE1000_GPIE_EIAME 0x40000000 igb_defines.h 　
5333
 E1000_GPIE_PBAE1000_GPIE_PBA 0x80000000 igb_defines.h 　
5334
 E1000_RXD_STAT_DDE1000_RXD_STAT_DD 0x01 igb_defines.h Descriptor Done
5335
 E1000_RXD_STAT_EOPE1000_RXD_STAT_EOP 0x02 igb_defines.h End of Packet
5336
 E1000_RXD_STAT_IXSME1000_RXD_STAT_IXSM 0x04 igb_defines.h Ignore checksum
5337
 E1000_RXD_STAT_VPE1000_RXD_STAT_VP 0x08 igb_defines.h IEEE VLAN Packet
5338
 E1000_RXD_STAT_UDPCSE1000_RXD_STAT_UDPCS 0x10 igb_defines.h UDP xsum calculated
5339
 E1000_RXD_STAT_TCPCSE1000_RXD_STAT_TCPCS 0x20 igb_defines.h TCP xsum calculated
5340
 E1000_RXD_STAT_IPCSE1000_RXD_STAT_IPCS 0x40 igb_defines.h IP xsum calculated
5341
 E1000_RXD_STAT_PIFE1000_RXD_STAT_PIF 0x80 igb_defines.h passed in-exact filter
5342
 E1000_RXD_STAT_CRCVE1000_RXD_STAT_CRCV 0x100 igb_defines.h Speculative CRC Valid
5343
 E1000_RXD_STAT_IPIDVE1000_RXD_STAT_IPIDV 0x200 igb_defines.h IP identification valid
5344
 E1000_RXD_STAT_UDPVE1000_RXD_STAT_UDPV 0x400 igb_defines.h Valid UDP checksum
5345
 E1000_RXD_STAT_DYNINTE1000_RXD_STAT_DYNINT 0x800 igb_defines.h Pkt caused INT via DYNINT
5346
 E1000_RXD_STAT_ACKE1000_RXD_STAT_ACK 0x8000 igb_defines.h ACK Packet indication
5347
 E1000_RXD_ERR_CEE1000_RXD_ERR_CE 0x01 igb_defines.h CRC Error
5348
 E1000_RXD_ERR_SEE1000_RXD_ERR_SE 0x02 igb_defines.h Symbol Error
5349
 E1000_RXD_ERR_SEQE1000_RXD_ERR_SEQ 0x04 igb_defines.h Sequence Error
5350
 E1000_RXD_ERR_CXEE1000_RXD_ERR_CXE 0x10 igb_defines.h Carrier Extension Error
5351
 E1000_RXD_ERR_TCPEE1000_RXD_ERR_TCPE 0x20 igb_defines.h TCP/UDP Checksum Error
5352
 E1000_RXD_ERR_IPEE1000_RXD_ERR_IPE 0x40 igb_defines.h IP Checksum Error
5353
 E1000_RXD_ERR_RXEE1000_RXD_ERR_RXE 0x80 igb_defines.h Rx Data Error
5354
 E1000_RXD_SPC_VLAN_MASKE1000_RXD_SPC_VLAN_MASK 0x0FFF igb_defines.h VLAN ID is in lower 12 bits
5355
 E1000_RXD_SPC_PRI_MASKE1000_RXD_SPC_PRI_MASK 0xE000 igb_defines.h Priority is in upper 3 bits
5356
 E1000_RXD_SPC_PRI_SHIFTE1000_RXD_SPC_PRI_SHIFT 13 igb_defines.h 　
5357
 E1000_RXD_SPC_CFI_MASKE1000_RXD_SPC_CFI_MASK 0x1000 igb_defines.h CFI is bit 12
5358
 E1000_RXD_SPC_CFI_SHIFTE1000_RXD_SPC_CFI_SHIFT 12 igb_defines.h 　
5359
 E1000_RXDEXT_STATERR_CEE1000_RXDEXT_STATERR_CE 0x01000000 igb_defines.h 　
5360
 E1000_RXDEXT_STATERR_SEE1000_RXDEXT_STATERR_SE 0x02000000 igb_defines.h 　
5361
 E1000_RXDEXT_STATERR_SEQE1000_RXDEXT_STATERR_SEQ 0x04000000 igb_defines.h 　
5362
 E1000_RXDEXT_STATERR_CXEE1000_RXDEXT_STATERR_CXE 0x10000000 igb_defines.h 　
5363
 E1000_RXDEXT_STATERR_TCPEE1000_RXDEXT_STATERR_TCPE 0x20000000 igb_defines.h 　
5364
 E1000_RXDEXT_STATERR_IPEE1000_RXDEXT_STATERR_IPE 0x40000000 igb_defines.h 　
5365
 E1000_RXDEXT_STATERR_RXEE1000_RXDEXT_STATERR_RXE 0x80000000 igb_defines.h 　
5366
 E1000_RXD_ERR_FRAME_ERR_MASKE1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ E1000_RXD_ERR_SE | \ E1000_RXD_ERR_SEQ | \ E1000_RXD_ER igb_defines.h 　
5367
 E1000_RXDEXT_ERR_FRAME_ERR_MASKE1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_SE | \ E1000_RXDEXT_STATERR_SEQ | \ E10 igb_defines.h 　
5368
 E1000_MRQC_ENABLE_MASKE1000_MRQC_ENABLE_MASK 0x00000007 igb_defines.h 　
5369
 E1000_MRQC_ENABLE_RSS_2QE1000_MRQC_ENABLE_RSS_2Q 0x00000001 igb_defines.h 　
5370
 E1000_MRQC_ENABLE_RSS_INTE1000_MRQC_ENABLE_RSS_INT 0x00000004 igb_defines.h 　
5371
 E1000_MRQC_RSS_FIELD_MASKE1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 igb_defines.h 　
5372
 E1000_MRQC_RSS_FIELD_IPV4_TCPE1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 igb_defines.h 　
5373
 E1000_MRQC_RSS_FIELD_IPV4E1000_MRQC_RSS_FIELD_IPV4 0x00020000 igb_defines.h 　
5374
 E1000_MRQC_RSS_FIELD_IPV6_TCP_EE1000_MRQC_RSS_FIELD_IPV6_TCP_E 0x00040000 igb_defines.h 　
5375
 E1000_MRQC_RSS_FIELD_IPV6_EXE1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 igb_defines.h 　
5376
 E1000_MRQC_RSS_FIELD_IPV6E1000_MRQC_RSS_FIELD_IPV6 0x00100000 igb_defines.h 　
5377
 E1000_MRQC_RSS_FIELD_IPV6_TCPE1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 igb_defines.h 　
5378
 E1000_RXDPS_HDRSTAT_HDRSPE1000_RXDPS_HDRSTAT_HDRSP 0x00008000 igb_defines.h 　
5379
 E1000_RXDPS_HDRSTAT_HDRLEN_MASKE1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF igb_defines.h 　
5380
 E1000_MANC_SMBUS_ENE1000_MANC_SMBUS_EN 0x00000001 igb_defines.h SMBus Enabled - RO
5381
 E1000_MANC_ASF_ENE1000_MANC_ASF_EN 0x00000002 igb_defines.h ASF Enabled - RO
5382
 E1000_MANC_R_ON_FORCEE1000_MANC_R_ON_FORCE 0x00000004 igb_defines.h Reset on Force TCO - RO
5383
 E1000_MANC_RMCP_ENE1000_MANC_RMCP_EN 0x00000100 igb_defines.h Enable RCMP 026Fh Filtering
5384
 E1000_MANC_0298_ENE1000_MANC_0298_EN 0x00000200 igb_defines.h Enable RCMP 0298h Filtering
5385
 E1000_MANC_IPV4_ENE1000_MANC_IPV4_EN 0x00000400 igb_defines.h Enable IPv4
5386
 E1000_MANC_IPV6_ENE1000_MANC_IPV6_EN 0x00000800 igb_defines.h Enable IPv6
5387
 E1000_MANC_SNAP_ENE1000_MANC_SNAP_EN 0x00001000 igb_defines.h Accept LLC/SNAP
5388
 E1000_MANC_ARP_ENE1000_MANC_ARP_EN 0x00002000 igb_defines.h Enable ARP Request Filtering
5389
 E1000_MANC_NEIGHBOR_ENE1000_MANC_NEIGHBOR_EN 0x00004000 igb_defines.h 　
5390
 E1000_MANC_ARP_RES_ENE1000_MANC_ARP_RES_EN 0x00008000 igb_defines.h Enable ARP response Filtering
5391
 E1000_MANC_TCO_RESETE1000_MANC_TCO_RESET 0x00010000 igb_defines.h TCO Reset Occurred
5392
 E1000_MANC_RCV_TCO_ENE1000_MANC_RCV_TCO_EN 0x00020000 igb_defines.h Receive TCO Packets Enabled
5393
 E1000_MANC_REPORT_STATUSE1000_MANC_REPORT_STATUS 0x00040000 igb_defines.h Status Reporting Enabled
5394
 E1000_MANC_RCV_ALLE1000_MANC_RCV_ALL 0x00080000 igb_defines.h Receive All Enabled
5395
 E1000_MANC_BLK_PHY_RST_ON_IDEE1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 igb_defines.h Block phy resets
5396
 E1000_MANC_EN_MAC_ADDR_FILTERE1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 igb_defines.h 　
5397
 E1000_MANC_EN_MNG2HOSTE1000_MANC_EN_MNG2HOST 0x00200000 igb_defines.h 　
5398
 E1000_MANC_EN_IP_ADDR_FILTERE1000_MANC_EN_IP_ADDR_FILTER 0x00400000 igb_defines.h 　
5399
 E1000_MANC_EN_XSUM_FILTERE1000_MANC_EN_XSUM_FILTER 0x00800000 igb_defines.h Enable checksum filtering
5400
 E1000_MANC_BR_ENE1000_MANC_BR_EN 0x01000000 igb_defines.h Enable broadcast filtering
5401
 E1000_MANC_SMB_REQE1000_MANC_SMB_REQ 0x01000000 igb_defines.h SMBus Request
5402
 E1000_MANC_SMB_GNTE1000_MANC_SMB_GNT 0x02000000 igb_defines.h SMBus Grant
5403
 E1000_MANC_SMB_CLK_INE1000_MANC_SMB_CLK_IN 0x04000000 igb_defines.h SMBus Clock In
5404
 E1000_MANC_SMB_DATA_INE1000_MANC_SMB_DATA_IN 0x08000000 igb_defines.h SMBus Data In
5405
 E1000_MANC_SMB_DATA_OUTE1000_MANC_SMB_DATA_OUT 0x10000000 igb_defines.h SMBus Data Out
5406
 E1000_MANC_SMB_CLK_OUTE1000_MANC_SMB_CLK_OUT 0x20000000 igb_defines.h SMBus Clock Out
5407
 E1000_MANC_SMB_DATA_OUT_SHIFTE1000_MANC_SMB_DATA_OUT_SHIFT 28 igb_defines.h SMBus Data Out Shift
5408
 E1000_MANC_SMB_CLK_OUT_SHIFTE1000_MANC_SMB_CLK_OUT_SHIFT 29 igb_defines.h SMBus Clock Out Shift
5409
 E1000_RCTL_RSTE1000_RCTL_RST 0x00000001 igb_defines.h Software reset
5410
 E1000_RCTL_ENE1000_RCTL_EN 0x00000002 igb_defines.h enable
5411
 E1000_RCTL_SBPE1000_RCTL_SBP 0x00000004 igb_defines.h store bad packet
5412
 E1000_RCTL_UPEE1000_RCTL_UPE 0x00000008 igb_defines.h unicast promisc enable
5413
 E1000_RCTL_MPEE1000_RCTL_MPE 0x00000010 igb_defines.h multicast promisc enable
5414
 E1000_RCTL_LPEE1000_RCTL_LPE 0x00000020 igb_defines.h long packet enable
5415
 E1000_RCTL_LBM_NOE1000_RCTL_LBM_NO 0x00000000 igb_defines.h no loopback mode
5416
 E1000_RCTL_LBM_MACE1000_RCTL_LBM_MAC 0x00000040 igb_defines.h MAC loopback mode
5417
 E1000_RCTL_LBM_SLPE1000_RCTL_LBM_SLP 0x00000080 igb_defines.h serial link loopback mode
5418
 E1000_RCTL_LBM_TCVRE1000_RCTL_LBM_TCVR 0x000000C0 igb_defines.h tcvr loopback mode
5419
 E1000_RCTL_DTYP_MASKE1000_RCTL_DTYP_MASK 0x00000C00 igb_defines.h Descriptor type mask
5420
 E1000_RCTL_DTYP_PSE1000_RCTL_DTYP_PS 0x00000400 igb_defines.h Packet Split descriptor
5421
 E1000_RCTL_RDMTS_HALFE1000_RCTL_RDMTS_HALF 0x00000000 igb_defines.h rx desc min thresh size
5422
 E1000_RCTL_RDMTS_QUATE1000_RCTL_RDMTS_QUAT 0x00000100 igb_defines.h rx desc min thresh size
5423
 E1000_RCTL_RDMTS_EIGTHE1000_RCTL_RDMTS_EIGTH 0x00000200 igb_defines.h rx desc min thresh size
5424
 E1000_RCTL_MO_SHIFTE1000_RCTL_MO_SHIFT 12 igb_defines.h multicast offset shift
5425
 E1000_RCTL_MO_0E1000_RCTL_MO_0 0x00000000 igb_defines.h multicast offset 11:0
5426
 E1000_RCTL_MO_1E1000_RCTL_MO_1 0x00001000 igb_defines.h multicast offset 12:1
5427
 E1000_RCTL_MO_2E1000_RCTL_MO_2 0x00002000 igb_defines.h multicast offset 13:2
5428
 E1000_RCTL_MO_3E1000_RCTL_MO_3 0x00003000 igb_defines.h multicast offset 15:4
5429
 E1000_RCTL_MDRE1000_RCTL_MDR 0x00004000 igb_defines.h multicast desc ring 0
5430
 E1000_RCTL_BAME1000_RCTL_BAM 0x00008000 igb_defines.h broadcast enable
5431
 E1000_RCTL_SZ_2048E1000_RCTL_SZ_2048 0x00000000 igb_defines.h rx buffer size 2048
5432
 E1000_RCTL_SZ_1024E1000_RCTL_SZ_1024 0x00010000 igb_defines.h rx buffer size 1024
5433
 E1000_RCTL_SZ_512E1000_RCTL_SZ_512 0x00020000 igb_defines.h rx buffer size 512
5434
 E1000_RCTL_SZ_256E1000_RCTL_SZ_256 0x00030000 igb_defines.h rx buffer size 256
5435
 E1000_RCTL_SZ_16384E1000_RCTL_SZ_16384 0x00010000 igb_defines.h rx buffer size 16384
5436
 E1000_RCTL_SZ_8192E1000_RCTL_SZ_8192 0x00020000 igb_defines.h rx buffer size 8192
5437
 E1000_RCTL_SZ_4096E1000_RCTL_SZ_4096 0x00030000 igb_defines.h rx buffer size 4096
5438
 E1000_RCTL_VFEE1000_RCTL_VFE 0x00040000 igb_defines.h vlan filter enable
5439
 E1000_RCTL_CFIENE1000_RCTL_CFIEN 0x00080000 igb_defines.h canonical form enable
5440
 E1000_RCTL_CFIE1000_RCTL_CFI 0x00100000 igb_defines.h canonical form indicator
5441
 E1000_RCTL_DPFE1000_RCTL_DPF 0x00400000 igb_defines.h discard pause frames
5442
 E1000_RCTL_PMCFE1000_RCTL_PMCF 0x00800000 igb_defines.h pass MAC control frames
5443
 E1000_RCTL_BSEXE1000_RCTL_BSEX 0x02000000 igb_defines.h Buffer size extension
5444
 E1000_RCTL_SECRCE1000_RCTL_SECRC 0x04000000 igb_defines.h Strip Ethernet CRC
5445
 E1000_RCTL_FLXBUF_MASKE1000_RCTL_FLXBUF_MASK 0x78000000 igb_defines.h Flexible buffer size
5446
 E1000_RCTL_FLXBUF_SHIFTE1000_RCTL_FLXBUF_SHIFT 27 igb_defines.h Flexible buffer shift
5447
 E1000_PSRCTL_BSIZE0_MASKE1000_PSRCTL_BSIZE0_MASK 0x0000007F igb_defines.h 　
5448
 E1000_PSRCTL_BSIZE1_MASKE1000_PSRCTL_BSIZE1_MASK 0x00003F00 igb_defines.h 　
5449
 E1000_PSRCTL_BSIZE2_MASKE1000_PSRCTL_BSIZE2_MASK 0x003F0000 igb_defines.h 　
5450
 E1000_PSRCTL_BSIZE3_MASKE1000_PSRCTL_BSIZE3_MASK 0x3F000000 igb_defines.h 　
5451
 E1000_PSRCTL_BSIZE0_SHIFTE1000_PSRCTL_BSIZE0_SHIFT 7 igb_defines.h Shift _right_ 7
5452
 E1000_PSRCTL_BSIZE1_SHIFTE1000_PSRCTL_BSIZE1_SHIFT 2 igb_defines.h Shift _right_ 2
5453
 E1000_PSRCTL_BSIZE2_SHIFTE1000_PSRCTL_BSIZE2_SHIFT 6 igb_defines.h Shift _left_ 6
5454
 E1000_PSRCTL_BSIZE3_SHIFTE1000_PSRCTL_BSIZE3_SHIFT 14 igb_defines.h Shift _left_ 14
5455
 E1000_SWFW_EEP_SME1000_SWFW_EEP_SM 0x01 igb_defines.h 　
5456
 E1000_SWFW_PHY0_SME1000_SWFW_PHY0_SM 0x02 igb_defines.h 　
5457
 E1000_SWFW_PHY1_SME1000_SWFW_PHY1_SM 0x04 igb_defines.h 　
5458
 E1000_SWFW_CSR_SME1000_SWFW_CSR_SM 0x08 igb_defines.h 　
5459
 E1000_FACTPS_LFSE1000_FACTPS_LFS 0x40000000 igb_defines.h LAN Function Select
5460
 E1000_CTRL_FDE1000_CTRL_FD 0x00000001 igb_defines.h Full duplex.0=half; 1=full
5461
 E1000_CTRL_BEME1000_CTRL_BEM 0x00000002 igb_defines.h Endian Mode.0=little,1=big
5462
 E1000_CTRL_PRIORE1000_CTRL_PRIOR 0x00000004 igb_defines.h Priority on PCI. 0=rx,1=fair
5463
 E1000_CTRL_GIO_MASTER_DISABLEE1000_CTRL_GIO_MASTER_DISABLE 0x00000004 igb_defines.h Blocks new Master reqs
5464
 E1000_CTRL_LRSTE1000_CTRL_LRST 0x00000008 igb_defines.h Link reset. 0=normal,1=reset
5465
 E1000_CTRL_TMEE1000_CTRL_TME 0x00000010 igb_defines.h Test mode. 0=normal,1=test
5466
 E1000_CTRL_SLEE1000_CTRL_SLE 0x00000020 igb_defines.h Serial Link on 0=dis,1=en
5467
 E1000_CTRL_ASDEE1000_CTRL_ASDE 0x00000020 igb_defines.h Auto-speed detect enable
5468
 E1000_CTRL_SLUE1000_CTRL_SLU 0x00000040 igb_defines.h Set link up (Force Link)
5469
 E1000_CTRL_ILOSE1000_CTRL_ILOS 0x00000080 igb_defines.h Invert Loss-Of Signal
5470
 E1000_CTRL_SPD_SELE1000_CTRL_SPD_SEL 0x00000300 igb_defines.h Speed Select Mask
5471
 E1000_CTRL_SPD_10E1000_CTRL_SPD_10 0x00000000 igb_defines.h Force 10Mb
5472
 E1000_CTRL_SPD_100E1000_CTRL_SPD_100 0x00000100 igb_defines.h Force 100Mb
5473
 E1000_CTRL_SPD_1000E1000_CTRL_SPD_1000 0x00000200 igb_defines.h Force 1Gb
5474
 E1000_CTRL_BEM32E1000_CTRL_BEM32 0x00000400 igb_defines.h Big Endian 32 mode
5475
 E1000_CTRL_FRCSPDE1000_CTRL_FRCSPD 0x00000800 igb_defines.h Force Speed
5476
 E1000_CTRL_FRCDPXE1000_CTRL_FRCDPX 0x00001000 igb_defines.h Force Duplex
5477
 E1000_CTRL_D_UD_ENE1000_CTRL_D_UD_EN 0x00002000 igb_defines.h Dock/Undock enable
5478
 E1000_CTRL_D_UD_POLARITYE1000_CTRL_D_UD_POLARITY 0x00004000 igb_defines.h Defined polarity of Dock/Undock
5479
 E1000_CTRL_FORCE_PHY_RESETE1000_CTRL_FORCE_PHY_RESET 0x00008000 igb_defines.h Reset both PHY ports, through
5480
 E1000_CTRL_EXT_LINK_ENE1000_CTRL_EXT_LINK_EN 0x00010000 igb_defines.h enable link status from external
5481
 E1000_CTRL_SWDPIN0E1000_CTRL_SWDPIN0 0x00040000 igb_defines.h SWDPIN 0 value
5482
 E1000_CTRL_SWDPIN1E1000_CTRL_SWDPIN1 0x00080000 igb_defines.h SWDPIN 1 value
5483
 E1000_CTRL_SWDPIN2E1000_CTRL_SWDPIN2 0x00100000 igb_defines.h SWDPIN 2 value
5484
 E1000_CTRL_ADVD3WUCE1000_CTRL_ADVD3WUC 0x00100000 igb_defines.h D3 WUC
5485
 E1000_CTRL_SWDPIN3E1000_CTRL_SWDPIN3 0x00200000 igb_defines.h SWDPIN 3 value
5486
 E1000_CTRL_SWDPIO0E1000_CTRL_SWDPIO0 0x00400000 igb_defines.h SWDPIN 0 Input or output
5487
 E1000_CTRL_SWDPIO1E1000_CTRL_SWDPIO1 0x00800000 igb_defines.h SWDPIN 1 input or output
5488
 E1000_CTRL_SWDPIO2E1000_CTRL_SWDPIO2 0x01000000 igb_defines.h SWDPIN 2 input or output
5489
 E1000_CTRL_SWDPIO3E1000_CTRL_SWDPIO3 0x02000000 igb_defines.h SWDPIN 3 input or output
5490
 E1000_CTRL_RSTE1000_CTRL_RST 0x04000000 igb_defines.h Global reset
5491
 E1000_CTRL_RFCEE1000_CTRL_RFCE 0x08000000 igb_defines.h Receive Flow Control enable
5492
 E1000_CTRL_TFCEE1000_CTRL_TFCE 0x10000000 igb_defines.h Transmit flow control enable
5493
 E1000_CTRL_RTEE1000_CTRL_RTE 0x20000000 igb_defines.h Routing tag enable
5494
 E1000_CTRL_VMEE1000_CTRL_VME 0x40000000 igb_defines.h IEEE VLAN mode enable
5495
 E1000_CTRL_PHY_RSTE1000_CTRL_PHY_RST 0x80000000 igb_defines.h PHY Reset
5496
 E1000_CTRL_SW2FW_INTE1000_CTRL_SW2FW_INT 0x02000000 igb_defines.h Initiate an interrupt to ME
5497
 E1000_CTRL_I2C_ENAE1000_CTRL_I2C_ENA 0x02000000 igb_defines.h I2C enable
5498
 E1000_CTRL_PHY_RESET_DIRE1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 igb_defines.h 　
5499
 E1000_CTRL_PHY_RESETE1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 igb_defines.h 　
5500
 E1000_CTRL_MDIO_DIRE1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 igb_defines.h 　
5501
 E1000_CTRL_MDIOE1000_CTRL_MDIO E1000_CTRL_SWDPIN2 igb_defines.h 　
5502
 E1000_CTRL_MDC_DIRE1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 igb_defines.h 　
5503
 E1000_CTRL_MDCE1000_CTRL_MDC E1000_CTRL_SWDPIN3 igb_defines.h 　
5504
 E1000_CTRL_PHY_RESET_DIR4E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR igb_defines.h 　
5505
 E1000_CTRL_PHY_RESET4E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA igb_defines.h 　
5506
 E1000_CONNSW_ENRGSRCE1000_CONNSW_ENRGSRC 0x4 igb_defines.h 　
5507
 E1000_PCS_CFG_PCS_ENE1000_PCS_CFG_PCS_EN 8 igb_defines.h 　
5508
 E1000_PCS_LCTL_FLV_LINK_UPE1000_PCS_LCTL_FLV_LINK_UP 1 igb_defines.h 　
5509
 E1000_PCS_LCTL_FSV_10E1000_PCS_LCTL_FSV_10 0 igb_defines.h 　
5510
 E1000_PCS_LCTL_FSV_100E1000_PCS_LCTL_FSV_100 2 igb_defines.h 　
5511
 E1000_PCS_LCTL_FSV_1000E1000_PCS_LCTL_FSV_1000 4 igb_defines.h 　
5512
 E1000_PCS_LCTL_FDV_FULLE1000_PCS_LCTL_FDV_FULL 8 igb_defines.h 　
5513
 E1000_PCS_LCTL_FSDE1000_PCS_LCTL_FSD 0x10 igb_defines.h 　
5514
 E1000_PCS_LCTL_FORCE_LINKE1000_PCS_LCTL_FORCE_LINK 0x20 igb_defines.h 　
5515
 E1000_PCS_LCTL_LOW_LINK_LATCHE1000_PCS_LCTL_LOW_LINK_LATCH 0x40 igb_defines.h 　
5516
 E1000_PCS_LCTL_FORCE_FCTRLE1000_PCS_LCTL_FORCE_FCTRL 0x80 igb_defines.h 　
5517
 E1000_PCS_LCTL_AN_ENABLEE1000_PCS_LCTL_AN_ENABLE 0x10000 igb_defines.h 　
5518
 E1000_PCS_LCTL_AN_RESTARTE1000_PCS_LCTL_AN_RESTART 0x20000 igb_defines.h 　
5519
 E1000_PCS_LCTL_AN_TIMEOUTE1000_PCS_LCTL_AN_TIMEOUT 0x40000 igb_defines.h 　
5520
 E1000_PCS_LCTL_AN_SGMII_BYPASSE1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 igb_defines.h 　
5521
 E1000_PCS_LCTL_AN_SGMII_TRIGGERE1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 igb_defines.h 　
5522
 E1000_PCS_LCTL_FAST_LINK_TIMERE1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 igb_defines.h 　
5523
 E1000_PCS_LCTL_LINK_OK_FIXE1000_PCS_LCTL_LINK_OK_FIX 0x2000000 igb_defines.h 　
5524
 E1000_PCS_LCTL_CRS_ON_NIE1000_PCS_LCTL_CRS_ON_NI 0x4000000 igb_defines.h 　
5525
 E1000_ENABLE_SERDES_LOOPBACKE1000_ENABLE_SERDES_LOOPBACK 0x0410 igb_defines.h 　
5526
 E1000_PCS_LSTS_LINK_OKE1000_PCS_LSTS_LINK_OK 1 igb_defines.h 　
5527
 E1000_PCS_LSTS_SPEED_10E1000_PCS_LSTS_SPEED_10 0 igb_defines.h 　
5528
 E1000_PCS_LSTS_SPEED_100E1000_PCS_LSTS_SPEED_100 2 igb_defines.h 　
5529
 E1000_PCS_LSTS_SPEED_1000E1000_PCS_LSTS_SPEED_1000 4 igb_defines.h 　
5530
 E1000_PCS_LSTS_DUPLEX_FULLE1000_PCS_LSTS_DUPLEX_FULL 8 igb_defines.h 　
5531
 E1000_PCS_LSTS_SYNK_OKE1000_PCS_LSTS_SYNK_OK 0x10 igb_defines.h 　
5532
 E1000_PCS_LSTS_AN_COMPLETEE1000_PCS_LSTS_AN_COMPLETE 0x10000 igb_defines.h 　
5533
 E1000_PCS_LSTS_AN_PAGE_RXE1000_PCS_LSTS_AN_PAGE_RX 0x20000 igb_defines.h 　
5534
 E1000_PCS_LSTS_AN_TIMED_OUTE1000_PCS_LSTS_AN_TIMED_OUT 0x40000 igb_defines.h 　
5535
 E1000_PCS_LSTS_AN_REMOTE_FAULTE1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 igb_defines.h 　
5536
 E1000_PCS_LSTS_AN_ERROR_RWSE1000_PCS_LSTS_AN_ERROR_RWS 0x100000 igb_defines.h 　
5537
 E1000_STATUS_FDE1000_STATUS_FD 0x00000001 igb_defines.h Full duplex.0=half,1=full
5538
 E1000_STATUS_LUE1000_STATUS_LU 0x00000002 igb_defines.h Link up.0=no,1=link
5539
 E1000_STATUS_FUNC_MASKE1000_STATUS_FUNC_MASK 0x0000000C igb_defines.h PCI Function Mask
5540
 E1000_STATUS_FUNC_SHIFTE1000_STATUS_FUNC_SHIFT 2 igb_defines.h 　
5541
 E1000_STATUS_FUNC_0E1000_STATUS_FUNC_0 0x00000000 igb_defines.h Function 0
5542
 E1000_STATUS_FUNC_1E1000_STATUS_FUNC_1 0x00000004 igb_defines.h Function 1
5543
 E1000_STATUS_TXOFFE1000_STATUS_TXOFF 0x00000010 igb_defines.h transmission paused
5544
 E1000_STATUS_TBIMODEE1000_STATUS_TBIMODE 0x00000020 igb_defines.h TBI mode
5545
 E1000_STATUS_SPEED_MASKE1000_STATUS_SPEED_MASK 0x000000C0 igb_defines.h 　
5546
 E1000_STATUS_SPEED_10E1000_STATUS_SPEED_10 0x00000000 igb_defines.h Speed 10Mb/s
5547
 E1000_STATUS_SPEED_100E1000_STATUS_SPEED_100 0x00000040 igb_defines.h Speed 100Mb/s
5548
 E1000_STATUS_SPEED_1000E1000_STATUS_SPEED_1000 0x00000080 igb_defines.h Speed 1000Mb/s
5549
 E1000_STATUS_LAN_INIT_DONEE1000_STATUS_LAN_INIT_DONE 0x00000200 igb_defines.h Lan Init Completion by NVM
5550
 E1000_STATUS_ASDVE1000_STATUS_ASDV 0x00000300 igb_defines.h Auto speed detect value
5551
 E1000_STATUS_PHYRAE1000_STATUS_PHYRA 0x00000400 igb_defines.h PHY Reset Asserted
5552
 E1000_STATUS_DOCK_CIE1000_STATUS_DOCK_CI 0x00000800 igb_defines.h Change in Dock/Undock state.
5553
 E1000_STATUS_GIO_MASTER_ENABLEE1000_STATUS_GIO_MASTER_ENABLE 0x00080000 igb_defines.h Master request status
5554
 E1000_STATUS_MTXCKOKE1000_STATUS_MTXCKOK 0x00000400 igb_defines.h MTX clock running OK
5555
 E1000_STATUS_PCI66E1000_STATUS_PCI66 0x00000800 igb_defines.h In 66Mhz slot
5556
 E1000_STATUS_BUS64E1000_STATUS_BUS64 0x00001000 igb_defines.h In 64 bit slot
5557
 E1000_STATUS_PCIX_MODEE1000_STATUS_PCIX_MODE 0x00002000 igb_defines.h PCI-X mode
5558
 E1000_STATUS_PCIX_SPEEDE1000_STATUS_PCIX_SPEED 0x0000C000 igb_defines.h PCI-X bus speed
5559
 E1000_STATUS_BMC_SKU_0E1000_STATUS_BMC_SKU_0 0x00100000 igb_defines.h BMC USB redirect disabled
5560
 E1000_STATUS_BMC_SKU_1E1000_STATUS_BMC_SKU_1 0x00200000 igb_defines.h BMC SRAM disabled
5561
 E1000_STATUS_BMC_SKU_2E1000_STATUS_BMC_SKU_2 0x00400000 igb_defines.h BMC SDRAM disabled
5562
 E1000_STATUS_BMC_CRYPTOE1000_STATUS_BMC_CRYPTO 0x00800000 igb_defines.h BMC crypto disabled
5563
 E1000_STATUS_BMC_LITEE1000_STATUS_BMC_LITE 0x01000000 igb_defines.h BMC external code execution
5564
 E1000_STATUS_RGMII_ENABLEE1000_STATUS_RGMII_ENABLE 0x02000000 igb_defines.h RGMII disabled
5565
 E1000_STATUS_FUSE_8E1000_STATUS_FUSE_8 0x04000000 igb_defines.h 　
5566
 E1000_STATUS_FUSE_9E1000_STATUS_FUSE_9 0x08000000 igb_defines.h 　
5567
 E1000_STATUS_SERDES0_DISE1000_STATUS_SERDES0_DIS 0x10000000 igb_defines.h SERDES disabled on port 0
5568
 E1000_STATUS_SERDES1_DISE1000_STATUS_SERDES1_DIS 0x20000000 igb_defines.h SERDES disabled on port 1
5569
 E1000_STATUS_PCIX_SPEED_66E1000_STATUS_PCIX_SPEED_66 0x00000000 igb_defines.h PCI-X bus speed 50-66 MHz
5570
 E1000_STATUS_PCIX_SPEED_100E1000_STATUS_PCIX_SPEED_100 0x00004000 igb_defines.h PCI-X bus speed 66-100 MHz
5571
 E1000_STATUS_PCIX_SPEED_133E1000_STATUS_PCIX_SPEED_133 0x00008000 igb_defines.h PCI-X bus speed 100-133 MHz
5572
 SPEED_10SPEED_10 10 igb_defines.h 　
5573
 SPEED_100SPEED_100 100 igb_defines.h 　
5574
 SPEED_1000SPEED_1000 1000 igb_defines.h 　
5575
 HALF_DUPLEXHALF_DUPLEX 1 igb_defines.h 　
5576
 FULL_DUPLEXFULL_DUPLEX 2 igb_defines.h 　
5577
 PHY_FORCE_TIMEPHY_FORCE_TIME 20 igb_defines.h 　
5578
 ADVERTISE_10_HALFADVERTISE_10_HALF 0x0001 igb_defines.h 　
5579
 ADVERTISE_10_FULLADVERTISE_10_FULL 0x0002 igb_defines.h 　
5580
 ADVERTISE_100_HALFADVERTISE_100_HALF 0x0004 igb_defines.h 　
5581
 ADVERTISE_100_FULLADVERTISE_100_FULL 0x0008 igb_defines.h 　
5582
 ADVERTISE_1000_HALFADVERTISE_1000_HALF 0x0010 igb_defines.h Not used, just FYI
5583
 ADVERTISE_1000_FULLADVERTISE_1000_FULL 0x0020 igb_defines.h 　
5584
 E1000_ALL_SPEED_DUPLEXE1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) igb_defines.h 　
5585
 E1000_ALL_NOT_GIGE1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL) igb_defines.h 　
5586
 E1000_ALL_100_SPEEDE1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) igb_defines.h 　
5587
 E1000_ALL_10_SPEEDE1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) igb_defines.h 　
5588
 E1000_ALL_FULL_DUPLEXE1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) igb_defines.h 　
5589
 E1000_ALL_HALF_DUPLEXE1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) igb_defines.h 　
5590
 AUTONEG_ADVERTISE_SPEED_DEFAULTAUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX igb_defines.h 　
5591
 E1000_LEDCTL_LED0_MODE_MASKE1000_LEDCTL_LED0_MODE_MASK 0x0000000F igb_defines.h 　
5592
 E1000_LEDCTL_LED0_MODE_SHIFTE1000_LEDCTL_LED0_MODE_SHIFT 0 igb_defines.h 　
5593
 E1000_LEDCTL_LED0_BLINK_RATEE1000_LEDCTL_LED0_BLINK_RATE 0x00000020 igb_defines.h 　
5594
 E1000_LEDCTL_LED0_IVRTE1000_LEDCTL_LED0_IVRT 0x00000040 igb_defines.h 　
5595
 E1000_LEDCTL_LED0_BLINKE1000_LEDCTL_LED0_BLINK 0x00000080 igb_defines.h 　
5596
 E1000_LEDCTL_LED1_MODE_MASKE1000_LEDCTL_LED1_MODE_MASK 0x00000F00 igb_defines.h 　
5597
 E1000_LEDCTL_LED1_MODE_SHIFTE1000_LEDCTL_LED1_MODE_SHIFT 8 igb_defines.h 　
5598
 E1000_LEDCTL_LED1_BLINK_RATEE1000_LEDCTL_LED1_BLINK_RATE 0x00002000 igb_defines.h 　
5599
 E1000_LEDCTL_LED1_IVRTE1000_LEDCTL_LED1_IVRT 0x00004000 igb_defines.h 　
5600
 E1000_LEDCTL_LED1_BLINKE1000_LEDCTL_LED1_BLINK 0x00008000 igb_defines.h 　
5601
 E1000_LEDCTL_LED2_MODE_MASKE1000_LEDCTL_LED2_MODE_MASK 0x000F0000 igb_defines.h 　
5602
 E1000_LEDCTL_LED2_MODE_SHIFTE1000_LEDCTL_LED2_MODE_SHIFT 16 igb_defines.h 　
5603
 E1000_LEDCTL_LED2_BLINK_RATEE1000_LEDCTL_LED2_BLINK_RATE 0x00200000 igb_defines.h 　
5604
 E1000_LEDCTL_LED2_IVRTE1000_LEDCTL_LED2_IVRT 0x00400000 igb_defines.h 　
5605
 E1000_LEDCTL_LED2_BLINKE1000_LEDCTL_LED2_BLINK 0x00800000 igb_defines.h 　
5606
 E1000_LEDCTL_LED3_MODE_MASKE1000_LEDCTL_LED3_MODE_MASK 0x0F000000 igb_defines.h 　
5607
 E1000_LEDCTL_LED3_MODE_SHIFTE1000_LEDCTL_LED3_MODE_SHIFT 24 igb_defines.h 　
5608
 E1000_LEDCTL_LED3_BLINK_RATEE1000_LEDCTL_LED3_BLINK_RATE 0x20000000 igb_defines.h 　
5609
 E1000_LEDCTL_LED3_IVRTE1000_LEDCTL_LED3_IVRT 0x40000000 igb_defines.h 　
5610
 E1000_LEDCTL_LED3_BLINKE1000_LEDCTL_LED3_BLINK 0x80000000 igb_defines.h 　
5611
 E1000_LEDCTL_MODE_LINK_10_1000E1000_LEDCTL_MODE_LINK_10_1000 0x0 igb_defines.h 　
5612
 E1000_LEDCTL_MODE_LINK_100_1000E1000_LEDCTL_MODE_LINK_100_1000 0x1 igb_defines.h 　
5613
 E1000_LEDCTL_MODE_LINK_UPE1000_LEDCTL_MODE_LINK_UP 0x2 igb_defines.h 　
5614
 E1000_LEDCTL_MODE_ACTIVITYE1000_LEDCTL_MODE_ACTIVITY 0x3 igb_defines.h 　
5615
 E1000_LEDCTL_MODE_LINK_ACTIVITYE1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 igb_defines.h 　
5616
 E1000_LEDCTL_MODE_LINK_10E1000_LEDCTL_MODE_LINK_10 0x5 igb_defines.h 　
5617
 E1000_LEDCTL_MODE_LINK_100E1000_LEDCTL_MODE_LINK_100 0x6 igb_defines.h 　
5618
 E1000_LEDCTL_MODE_LINK_1000E1000_LEDCTL_MODE_LINK_1000 0x7 igb_defines.h 　
5619
 E1000_LEDCTL_MODE_PCIX_MODEE1000_LEDCTL_MODE_PCIX_MODE 0x8 igb_defines.h 　
5620
 E1000_LEDCTL_MODE_FULL_DUPLEXE1000_LEDCTL_MODE_FULL_DUPLEX 0x9 igb_defines.h 　
5621
 E1000_LEDCTL_MODE_COLLISIONE1000_LEDCTL_MODE_COLLISION 0xA igb_defines.h 　
5622
 E1000_LEDCTL_MODE_BUS_SPEEDE1000_LEDCTL_MODE_BUS_SPEED 0xB igb_defines.h 　
5623
 E1000_LEDCTL_MODE_BUS_SIZEE1000_LEDCTL_MODE_BUS_SIZE 0xC igb_defines.h 　
5624
 E1000_LEDCTL_MODE_PAUSEDE1000_LEDCTL_MODE_PAUSED 0xD igb_defines.h 　
5625
 E1000_LEDCTL_MODE_LED_ONE1000_LEDCTL_MODE_LED_ON 0xE igb_defines.h 　
5626
 E1000_LEDCTL_MODE_LED_OFFE1000_LEDCTL_MODE_LED_OFF 0xF igb_defines.h 　
5627
 E1000_TXD_DTYP_DE1000_TXD_DTYP_D 0x00100000 igb_defines.h Data Descriptor
5628
 E1000_TXD_DTYP_CE1000_TXD_DTYP_C 0x00000000 igb_defines.h Context Descriptor
5629
 E1000_TXD_POPTS_SHIFTE1000_TXD_POPTS_SHIFT 8 igb_defines.h POPTS shift
5630
 E1000_TXD_POPTS_IXSME1000_TXD_POPTS_IXSM 0x01 igb_defines.h Insert IP checksum
5631
 E1000_TXD_POPTS_TXSME1000_TXD_POPTS_TXSM 0x02 igb_defines.h Insert TCP/UDP checksum
5632
 E1000_TXD_CMD_EOPE1000_TXD_CMD_EOP 0x01000000 igb_defines.h End of Packet
5633
 E1000_TXD_CMD_IFCSE1000_TXD_CMD_IFCS 0x02000000 igb_defines.h Insert FCS (Ethernet CRC)
5634
 E1000_TXD_CMD_ICE1000_TXD_CMD_IC 0x04000000 igb_defines.h Insert Checksum
5635
 E1000_TXD_CMD_RSE1000_TXD_CMD_RS 0x08000000 igb_defines.h Report Status
5636
 E1000_TXD_CMD_RPSE1000_TXD_CMD_RPS 0x10000000 igb_defines.h Report Packet Sent
5637
 E1000_TXD_CMD_DEXTE1000_TXD_CMD_DEXT 0x20000000 igb_defines.h Descriptor extension (0 = legacy)
5638
 E1000_TXD_CMD_VLEE1000_TXD_CMD_VLE 0x40000000 igb_defines.h Add VLAN tag
5639
 E1000_TXD_CMD_IDEE1000_TXD_CMD_IDE 0x80000000 igb_defines.h Enable Tidv register
5640
 E1000_TXD_STAT_DDE1000_TXD_STAT_DD 0x00000001 igb_defines.h Descriptor Done
5641
 E1000_TXD_STAT_ECE1000_TXD_STAT_EC 0x00000002 igb_defines.h Excess Collisions
5642
 E1000_TXD_STAT_LCE1000_TXD_STAT_LC 0x00000004 igb_defines.h Late Collisions
5643
 E1000_TXD_STAT_TUE1000_TXD_STAT_TU 0x00000008 igb_defines.h Transmit underrun
5644
 E1000_TXD_CMD_TCPE1000_TXD_CMD_TCP 0x01000000 igb_defines.h TCP packet
5645
 E1000_TXD_CMD_IPE1000_TXD_CMD_IP 0x02000000 igb_defines.h IP packet
5646
 E1000_TXD_CMD_TSEE1000_TXD_CMD_TSE 0x04000000 igb_defines.h TCP Seg enable
5647
 E1000_TXD_STAT_TCE1000_TXD_STAT_TC 0x00000004 igb_defines.h Tx Underrun
5648
 E1000_TCTL_RSTE1000_TCTL_RST 0x00000001 igb_defines.h software reset
5649
 E1000_TCTL_ENE1000_TCTL_EN 0x00000002 igb_defines.h enable tx
5650
 E1000_TCTL_BCEE1000_TCTL_BCE 0x00000004 igb_defines.h busy check enable
5651
 E1000_TCTL_PSPE1000_TCTL_PSP 0x00000008 igb_defines.h pad short packets
5652
 E1000_TCTL_CTE1000_TCTL_CT 0x00000ff0 igb_defines.h collision threshold
5653
 E1000_TCTL_COLDE1000_TCTL_COLD 0x003ff000 igb_defines.h collision distance
5654
 E1000_TCTL_SWXOFFE1000_TCTL_SWXOFF 0x00400000 igb_defines.h SW Xoff transmission
5655
 E1000_TCTL_PBEE1000_TCTL_PBE 0x00800000 igb_defines.h Packet Burst Enable
5656
 E1000_TCTL_RTLCE1000_TCTL_RTLC 0x01000000 igb_defines.h Re-transmit on late collision
5657
 E1000_TCTL_NRTUE1000_TCTL_NRTU 0x02000000 igb_defines.h No Re-transmit on underrun
5658
 E1000_TCTL_MULRE1000_TCTL_MULR 0x10000000 igb_defines.h Multiple request support
5659
 E1000_TARC0_ENABLEE1000_TARC0_ENABLE 0x00000400 igb_defines.h Enable Tx Queue 0
5660
 E1000_SCTL_DISABLE_SERDES_LOOPBE1000_SCTL_DISABLE_SERDES_LOOPB 0x0400 igb_defines.h 　
5661
 E1000_RXCSUM_PCSS_MASKE1000_RXCSUM_PCSS_MASK 0x000000FF igb_defines.h Packet Checksum Start
5662
 E1000_RXCSUM_IPOFLE1000_RXCSUM_IPOFL 0x00000100 igb_defines.h IPv4 checksum offload
5663
 E1000_RXCSUM_TUOFLE1000_RXCSUM_TUOFL 0x00000200 igb_defines.h TCP / UDP checksum offload
5664
 E1000_RXCSUM_IPV6OFLE1000_RXCSUM_IPV6OFL 0x00000400 igb_defines.h IPv6 checksum offload
5665
 E1000_RXCSUM_CRCOFLE1000_RXCSUM_CRCOFL 0x00000800 igb_defines.h CRC32 offload enable
5666
 E1000_RXCSUM_IPPCSEE1000_RXCSUM_IPPCSE 0x00001000 igb_defines.h IP payload checksum enable
5667
 E1000_RXCSUM_PCSDE1000_RXCSUM_PCSD 0x00002000 igb_defines.h packet checksum disabled
5668
 E1000_RFCTL_ISCSI_DISE1000_RFCTL_ISCSI_DIS 0x00000001 igb_defines.h 　
5669
 E1000_RFCTL_ISCSI_DWC_MASKE1000_RFCTL_ISCSI_DWC_MASK 0x0000003E igb_defines.h 　
5670
 E1000_RFCTL_ISCSI_DWC_SHIFTE1000_RFCTL_ISCSI_DWC_SHIFT 1 igb_defines.h 　
5671
 E1000_RFCTL_NFSW_DISE1000_RFCTL_NFSW_DIS 0x00000040 igb_defines.h 　
5672
 E1000_RFCTL_NFSR_DISE1000_RFCTL_NFSR_DIS 0x00000080 igb_defines.h 　
5673
 E1000_RFCTL_NFS_VER_MASKE1000_RFCTL_NFS_VER_MASK 0x00000300 igb_defines.h 　
5674
 E1000_RFCTL_NFS_VER_SHIFTE1000_RFCTL_NFS_VER_SHIFT 8 igb_defines.h 　
5675
 E1000_RFCTL_IPV6_DISE1000_RFCTL_IPV6_DIS 0x00000400 igb_defines.h 　
5676
 E1000_RFCTL_IPV6_XSUM_DISE1000_RFCTL_IPV6_XSUM_DIS 0x00000800 igb_defines.h 　
5677
 E1000_RFCTL_ACK_DISE1000_RFCTL_ACK_DIS 0x00001000 igb_defines.h 　
5678
 E1000_RFCTL_ACKD_DISE1000_RFCTL_ACKD_DIS 0x00002000 igb_defines.h 　
5679
 E1000_RFCTL_IPFRSP_DISE1000_RFCTL_IPFRSP_DIS 0x00004000 igb_defines.h 　
5680
 E1000_RFCTL_EXTENE1000_RFCTL_EXTEN 0x00008000 igb_defines.h 　
5681
 E1000_RFCTL_IPV6_EX_DISE1000_RFCTL_IPV6_EX_DIS 0x00010000 igb_defines.h 　
5682
 E1000_RFCTL_NEW_IPV6_EXT_DISE1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 igb_defines.h 　
5683
 E1000_RFCTL_LEFE1000_RFCTL_LEF 0x00040000 igb_defines.h 　
5684
 E1000_COLLISION_THRESHOLDE1000_COLLISION_THRESHOLD 15 igb_defines.h 　
5685
 E1000_CT_SHIFTE1000_CT_SHIFT 4 igb_defines.h 　
5686
 E1000_COLLISION_DISTANCEE1000_COLLISION_DISTANCE 63 igb_defines.h 　
5687
 E1000_COLD_SHIFTE1000_COLD_SHIFT 12 igb_defines.h 　
5688
 DEFAULT_82543_TIPG_IPGT_FIBERDEFAULT_82543_TIPG_IPGT_FIBER 9 igb_defines.h 　
5689
 DEFAULT_82543_TIPG_IPGT_COPPERDEFAULT_82543_TIPG_IPGT_COPPER 8 igb_defines.h 　
5690
 E1000_TIPG_IPGT_MASKE1000_TIPG_IPGT_MASK 0x000003FF igb_defines.h 　
5691
 E1000_TIPG_IPGR1_MASKE1000_TIPG_IPGR1_MASK 0x000FFC00 igb_defines.h 　
5692
 E1000_TIPG_IPGR2_MASKE1000_TIPG_IPGR2_MASK 0x3FF00000 igb_defines.h 　
5693
 DEFAULT_82543_TIPG_IPGR1DEFAULT_82543_TIPG_IPGR1 8 igb_defines.h 　
5694
 E1000_TIPG_IPGR1_SHIFTE1000_TIPG_IPGR1_SHIFT 10 igb_defines.h 　
5695
 DEFAULT_82543_TIPG_IPGR2DEFAULT_82543_TIPG_IPGR2 6 igb_defines.h 　
5696
 DEFAULT_80003ES2LAN_TIPG_IPGR2DEFAULT_80003ES2LAN_TIPG_IPGR2 7 igb_defines.h 　
5697
 E1000_TIPG_IPGR2_SHIFTE1000_TIPG_IPGR2_SHIFT 20 igb_defines.h 　
5698
 ETHERNET_IEEE_VLAN_TYPEETHERNET_IEEE_VLAN_TYPE 0x8100 igb_defines.h 802.3ac packet
5699
 ETHERNET_FCS_SIZEETHERNET_FCS_SIZE 4 igb_defines.h 　
5700
 MAX_JUMBO_FRAME_SIZEMAX_JUMBO_FRAME_SIZE 0x3F00 igb_defines.h 　
5701
 E1000_EXTCNF_CTRL_MDIO_SW_OWNERE1000_EXTCNF_CTRL_MDIO_SW_OWNER 0x00000020 igb_defines.h 　
5702
 E1000_EXTCNF_CTRL_LCD_WRITE_ENAE1000_EXTCNF_CTRL_LCD_WRITE_ENA 0x00000001 igb_defines.h 　
5703
 E1000_EXTCNF_CTRL_OEM_WRITE_ENAE1000_EXTCNF_CTRL_OEM_WRITE_ENA 0x00000008 igb_defines.h 　
5704
 E1000_EXTCNF_CTRL_SWFLAGE1000_EXTCNF_CTRL_SWFLAG 0x00000020 igb_defines.h 　
5705
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 0x00FF0000 igb_defines.h 　
5706
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 16 igb_defines.h 　
5707
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 0x0FFF0000 igb_defines.h 　
5708
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 16 igb_defines.h 　
5709
 E1000_PHY_CTRL_SPD_ENE1000_PHY_CTRL_SPD_EN 0x00000001 igb_defines.h 　
5710
 E1000_PHY_CTRL_D0A_LPLUE1000_PHY_CTRL_D0A_LPLU 0x00000002 igb_defines.h 　
5711
 E1000_PHY_CTRL_NOND0A_LPLUE1000_PHY_CTRL_NOND0A_LPLU 0x00000004 igb_defines.h 　
5712
 E1000_PHY_CTRL_NOND0A_GBE_DISABE1000_PHY_CTRL_NOND0A_GBE_DISAB 0x00000008 igb_defines.h 　
5713
 E1000_PHY_CTRL_GBE_DISABLEE1000_PHY_CTRL_GBE_DISABLE 0x00000040 igb_defines.h 　
5714
 E1000_KABGTXD_BGSQLBIASE1000_KABGTXD_BGSQLBIAS 0x00050000 igb_defines.h 　
5715
 E1000_PBA_6KE1000_PBA_6K 0x0006 igb_defines.h 6KB
5716
 E1000_PBA_8KE1000_PBA_8K 0x0008 igb_defines.h 8KB
5717
 E1000_PBA_10KE1000_PBA_10K 0x000A igb_defines.h 10KB
5718
 E1000_PBA_12KE1000_PBA_12K 0x000C igb_defines.h 12KB
5719
 E1000_PBA_14KE1000_PBA_14K 0x000E igb_defines.h 14KB
5720
 E1000_PBA_16KE1000_PBA_16K 0x0010 igb_defines.h 16KB
5721
 E1000_PBA_18KE1000_PBA_18K 0x0012 igb_defines.h 　
5722
 E1000_PBA_20KE1000_PBA_20K 0x0014 igb_defines.h 　
5723
 E1000_PBA_22KE1000_PBA_22K 0x0016 igb_defines.h 　
5724
 E1000_PBA_24KE1000_PBA_24K 0x0018 igb_defines.h 　
5725
 E1000_PBA_26KE1000_PBA_26K 0x001A igb_defines.h 　
5726
 E1000_PBA_30KE1000_PBA_30K 0x001E igb_defines.h 　
5727
 E1000_PBA_32KE1000_PBA_32K 0x0020 igb_defines.h 　
5728
 E1000_PBA_34KE1000_PBA_34K 0x0022 igb_defines.h 　
5729
 E1000_PBA_35KE1000_PBA_35K 0x0023 igb_defines.h 　
5730
 E1000_PBA_38KE1000_PBA_38K 0x0026 igb_defines.h 　
5731
 E1000_PBA_40KE1000_PBA_40K 0x0028 igb_defines.h 　
5732
 E1000_PBA_48KE1000_PBA_48K 0x0030 igb_defines.h 48KB
5733
 E1000_PBA_64KE1000_PBA_64K 0x0040 igb_defines.h 64KB
5734
 E1000_PBS_16KE1000_PBS_16K E1000_PBA_16K igb_defines.h 　
5735
 E1000_PBS_24KE1000_PBS_24K E1000_PBA_24K igb_defines.h 　
5736
 IFS_MAXIFS_MAX 80 igb_defines.h 　
5737
 IFS_MINIFS_MIN 40 igb_defines.h 　
5738
 IFS_RATIOIFS_RATIO 4 igb_defines.h 　
5739
 IFS_STEPIFS_STEP 10 igb_defines.h 　
5740
 MIN_NUM_XMITSMIN_NUM_XMITS 1000 igb_defines.h 　
5741
 E1000_SWSM_SMBIE1000_SWSM_SMBI 0x00000001 igb_defines.h Driver Semaphore bit
5742
 E1000_SWSM_SWESMBIE1000_SWSM_SWESMBI 0x00000002 igb_defines.h FW Semaphore bit
5743
 E1000_SWSM_WMNGE1000_SWSM_WMNG 0x00000004 igb_defines.h Wake MNG Clock
5744
 E1000_SWSM_DRV_LOADE1000_SWSM_DRV_LOAD 0x00000008 igb_defines.h Driver Loaded Bit
5745
 E1000_SWSM2_LOCKE1000_SWSM2_LOCK 0x00000002 igb_defines.h Secondary driver semaphore bit
5746
 E1000_ICR_TXDWE1000_ICR_TXDW 0x00000001 igb_defines.h Transmit desc written back
5747
 E1000_ICR_TXQEE1000_ICR_TXQE 0x00000002 igb_defines.h Transmit Queue empty
5748
 E1000_ICR_LSCE1000_ICR_LSC 0x00000004 igb_defines.h Link Status Change
5749
 E1000_ICR_RXSEQE1000_ICR_RXSEQ 0x00000008 igb_defines.h rx sequence error
5750
 E1000_ICR_RXDMT0E1000_ICR_RXDMT0 0x00000010 igb_defines.h rx desc min. threshold (0)
5751
 E1000_ICR_RXOE1000_ICR_RXO 0x00000040 igb_defines.h rx overrun
5752
 E1000_ICR_RXT0E1000_ICR_RXT0 0x00000080 igb_defines.h rx timer intr (ring 0)
5753
 E1000_ICR_VMMBE1000_ICR_VMMB 0x00000100 igb_defines.h VM MB event
5754
 E1000_ICR_MDACE1000_ICR_MDAC 0x00000200 igb_defines.h MDIO access complete
5755
 E1000_ICR_RXCFGE1000_ICR_RXCFG 0x00000400 igb_defines.h Rx /c/ ordered set
5756
 E1000_ICR_GPI_EN0E1000_ICR_GPI_EN0 0x00000800 igb_defines.h GP Int 0
5757
 E1000_ICR_GPI_EN1E1000_ICR_GPI_EN1 0x00001000 igb_defines.h GP Int 1
5758
 E1000_ICR_GPI_EN2E1000_ICR_GPI_EN2 0x00002000 igb_defines.h GP Int 2
5759
 E1000_ICR_GPI_EN3E1000_ICR_GPI_EN3 0x00004000 igb_defines.h GP Int 3
5760
 E1000_ICR_TXD_LOWE1000_ICR_TXD_LOW 0x00008000 igb_defines.h 　
5761
 E1000_ICR_SRPDE1000_ICR_SRPD 0x00010000 igb_defines.h 　
5762
 E1000_ICR_ACKE1000_ICR_ACK 0x00020000 igb_defines.h Receive Ack frame
5763
 E1000_ICR_MNGE1000_ICR_MNG 0x00040000 igb_defines.h Manageability event
5764
 E1000_ICR_DOCKE1000_ICR_DOCK 0x00080000 igb_defines.h Dock/Undock
5765
 E1000_ICR_INT_ASSERTEDE1000_ICR_INT_ASSERTED 0x80000000 igb_defines.h If this bit asserted, the driver
5766
 E1000_ICR_RXD_FIFO_PAR0E1000_ICR_RXD_FIFO_PAR0 0x00100000 igb_defines.h Q0 Rx desc FIFO parity error
5767
 E1000_ICR_TXD_FIFO_PAR0E1000_ICR_TXD_FIFO_PAR0 0x00200000 igb_defines.h Q0 Tx desc FIFO parity error
5768
 E1000_ICR_HOST_ARB_PARE1000_ICR_HOST_ARB_PAR 0x00400000 igb_defines.h host arb read buffer parity err
5769
 E1000_ICR_PB_PARE1000_ICR_PB_PAR 0x00800000 igb_defines.h packet buffer parity error
5770
 E1000_ICR_RXD_FIFO_PAR1E1000_ICR_RXD_FIFO_PAR1 0x01000000 igb_defines.h Q1 Rx desc FIFO parity error
5771
 E1000_ICR_TXD_FIFO_PAR1E1000_ICR_TXD_FIFO_PAR1 0x02000000 igb_defines.h Q1 Tx desc FIFO parity error
5772
 E1000_ICR_ALL_PARITYE1000_ICR_ALL_PARITY 0x03F00000 igb_defines.h all parity error bits
5773
 E1000_ICR_DSWE1000_ICR_DSW 0x00000020 igb_defines.h FW changed the status of DISSW
5774
 E1000_ICR_PHYINTE1000_ICR_PHYINT 0x00001000 igb_defines.h LAN connected device generates
5775
 E1000_ICR_DOUTSYNCE1000_ICR_DOUTSYNC 0x10000000 igb_defines.h NIC DMA out of sync
5776
 E1000_ICR_EPRSTE1000_ICR_EPRST 0x00100000 igb_defines.h ME hardware reset occurs
5777
 E1000_EICR_RX_QUEUE0E1000_EICR_RX_QUEUE0 0x00000001 igb_defines.h Rx Queue 0 Interrupt
5778
 E1000_EICR_RX_QUEUE1E1000_EICR_RX_QUEUE1 0x00000002 igb_defines.h Rx Queue 1 Interrupt
5779
 E1000_EICR_RX_QUEUE2E1000_EICR_RX_QUEUE2 0x00000004 igb_defines.h Rx Queue 2 Interrupt
5780
 E1000_EICR_RX_QUEUE3E1000_EICR_RX_QUEUE3 0x00000008 igb_defines.h Rx Queue 3 Interrupt
5781
 E1000_EICR_TX_QUEUE0E1000_EICR_TX_QUEUE0 0x00000100 igb_defines.h Tx Queue 0 Interrupt
5782
 E1000_EICR_TX_QUEUE1E1000_EICR_TX_QUEUE1 0x00000200 igb_defines.h Tx Queue 1 Interrupt
5783
 E1000_EICR_TX_QUEUE2E1000_EICR_TX_QUEUE2 0x00000400 igb_defines.h Tx Queue 2 Interrupt
5784
 E1000_EICR_TX_QUEUE3E1000_EICR_TX_QUEUE3 0x00000800 igb_defines.h Tx Queue 3 Interrupt
5785
 E1000_EICR_TCP_TIMERE1000_EICR_TCP_TIMER 0x40000000 igb_defines.h TCP Timer
5786
 E1000_EICR_OTHERE1000_EICR_OTHER 0x80000000 igb_defines.h Interrupt Cause Active
5787
 E1000_TCPTIMER_KSE1000_TCPTIMER_KS 0x00000100 igb_defines.h KickStart
5788
 E1000_TCPTIMER_COUNT_ENABLEE1000_TCPTIMER_COUNT_ENABLE 0x00000200 igb_defines.h Count Enable
5789
 E1000_TCPTIMER_COUNT_FINISHE1000_TCPTIMER_COUNT_FINISH 0x00000400 igb_defines.h Count finish
5790
 E1000_TCPTIMER_LOOPE1000_TCPTIMER_LOOP 0x00000800 igb_defines.h Loop
5791
 POLL_IMS_ENABLE_MASKPOLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) igb_defines.h 　
5792
 IMS_ENABLE_MASKIMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_LSC) igb_defines.h 　
5793
 E1000_IMS_TXDWE1000_IMS_TXDW E1000_ICR_TXDW igb_defines.h Tx desc written back
5794
 E1000_IMS_TXQEE1000_IMS_TXQE E1000_ICR_TXQE igb_defines.h Transmit Queue empty
5795
 E1000_IMS_LSCE1000_IMS_LSC E1000_ICR_LSC igb_defines.h Link Status Change
5796
 E1000_IMS_VMMBE1000_IMS_VMMB E1000_ICR_VMMB igb_defines.h Mail box activity
5797
 E1000_IMS_RXSEQE1000_IMS_RXSEQ E1000_ICR_RXSEQ igb_defines.h rx sequence error
5798
 E1000_IMS_RXDMT0E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 igb_defines.h rx desc min. threshold
5799
 E1000_IMS_RXOE1000_IMS_RXO E1000_ICR_RXO igb_defines.h rx overrun
5800
 E1000_IMS_RXT0E1000_IMS_RXT0 E1000_ICR_RXT0 igb_defines.h rx timer intr
5801
 E1000_IMS_MDACE1000_IMS_MDAC E1000_ICR_MDAC igb_defines.h MDIO access complete
5802
 E1000_IMS_RXCFGE1000_IMS_RXCFG E1000_ICR_RXCFG igb_defines.h Rx /c/ ordered set
5803
 E1000_IMS_GPI_EN0E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 igb_defines.h GP Int 0
5804
 E1000_IMS_GPI_EN1E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 igb_defines.h GP Int 1
5805
 E1000_IMS_GPI_EN2E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 igb_defines.h GP Int 2
5806
 E1000_IMS_GPI_EN3E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 igb_defines.h GP Int 3
5807
 E1000_IMS_TXD_LOWE1000_IMS_TXD_LOW E1000_ICR_TXD_LOW igb_defines.h 　
5808
 E1000_IMS_SRPDE1000_IMS_SRPD E1000_ICR_SRPD igb_defines.h 　
5809
 E1000_IMS_ACKE1000_IMS_ACK E1000_ICR_ACK igb_defines.h Receive Ack frame
5810
 E1000_IMS_MNGE1000_IMS_MNG E1000_ICR_MNG igb_defines.h Manageability event
5811
 E1000_IMS_DOCKE1000_IMS_DOCK E1000_ICR_DOCK igb_defines.h Dock/Undock
5812
 E1000_IMS_RXD_FIFO_PAR0E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 igb_defines.h Q0 Rx desc FIFO
5813
 E1000_IMS_TXD_FIFO_PAR0E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 igb_defines.h Q0 Tx desc FIFO
5814
 E1000_IMS_HOST_ARB_PARE1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR igb_defines.h host arb read buffer
5815
 E1000_IMS_PB_PARE1000_IMS_PB_PAR E1000_ICR_PB_PAR igb_defines.h packet buffer parity
5816
 E1000_IMS_RXD_FIFO_PAR1E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 igb_defines.h Q1 Rx desc FIFO
5817
 E1000_IMS_TXD_FIFO_PAR1E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 igb_defines.h Q1 Tx desc FIFO
5818
 E1000_IMS_DSWE1000_IMS_DSW E1000_ICR_DSW igb_defines.h 　
5819
 E1000_IMS_PHYINTE1000_IMS_PHYINT E1000_ICR_PHYINT igb_defines.h 　
5820
 E1000_IMS_DOUTSYNCE1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC igb_defines.h NIC DMA out of sync
5821
 E1000_IMS_EPRSTE1000_IMS_EPRST E1000_ICR_EPRST igb_defines.h 　
5822
 E1000_EIMS_RX_QUEUE0E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 igb_defines.h Rx Queue 0 Interrupt
5823
 E1000_EIMS_RX_QUEUE1E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 igb_defines.h Rx Queue 1 Interrupt
5824
 E1000_EIMS_RX_QUEUE2E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 igb_defines.h Rx Queue 2 Interrupt
5825
 E1000_EIMS_RX_QUEUE3E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 igb_defines.h Rx Queue 3 Interrupt
5826
 E1000_EIMS_TX_QUEUE0E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 igb_defines.h Tx Queue 0 Interrupt
5827
 E1000_EIMS_TX_QUEUE1E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 igb_defines.h Tx Queue 1 Interrupt
5828
 E1000_EIMS_TX_QUEUE2E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 igb_defines.h Tx Queue 2 Interrupt
5829
 E1000_EIMS_TX_QUEUE3E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 igb_defines.h Tx Queue 3 Interrupt
5830
 E1000_EIMS_TCP_TIMERE1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER igb_defines.h TCP Timer
5831
 E1000_EIMS_OTHERE1000_EIMS_OTHER E1000_EICR_OTHER igb_defines.h Interrupt Cause Active
5832
 E1000_ICS_TXDWE1000_ICS_TXDW E1000_ICR_TXDW igb_defines.h Tx desc written back
5833
 E1000_ICS_TXQEE1000_ICS_TXQE E1000_ICR_TXQE igb_defines.h Transmit Queue empty
5834
 E1000_ICS_LSCE1000_ICS_LSC E1000_ICR_LSC igb_defines.h Link Status Change
5835
 E1000_ICS_RXSEQE1000_ICS_RXSEQ E1000_ICR_RXSEQ igb_defines.h rx sequence error
5836
 E1000_ICS_RXDMT0E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 igb_defines.h rx desc min. threshold
5837
 E1000_ICS_RXOE1000_ICS_RXO E1000_ICR_RXO igb_defines.h rx overrun
5838
 E1000_ICS_RXT0E1000_ICS_RXT0 E1000_ICR_RXT0 igb_defines.h rx timer intr
5839
 E1000_ICS_MDACE1000_ICS_MDAC E1000_ICR_MDAC igb_defines.h MDIO access complete
5840
 E1000_ICS_RXCFGE1000_ICS_RXCFG E1000_ICR_RXCFG igb_defines.h Rx /c/ ordered set
5841
 E1000_ICS_GPI_EN0E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 igb_defines.h GP Int 0
5842
 E1000_ICS_GPI_EN1E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 igb_defines.h GP Int 1
5843
 E1000_ICS_GPI_EN2E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 igb_defines.h GP Int 2
5844
 E1000_ICS_GPI_EN3E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 igb_defines.h GP Int 3
5845
 E1000_ICS_TXD_LOWE1000_ICS_TXD_LOW E1000_ICR_TXD_LOW igb_defines.h 　
5846
 E1000_ICS_SRPDE1000_ICS_SRPD E1000_ICR_SRPD igb_defines.h 　
5847
 E1000_ICS_ACKE1000_ICS_ACK E1000_ICR_ACK igb_defines.h Receive Ack frame
5848
 E1000_ICS_MNGE1000_ICS_MNG E1000_ICR_MNG igb_defines.h Manageability event
5849
 E1000_ICS_DOCKE1000_ICS_DOCK E1000_ICR_DOCK igb_defines.h Dock/Undock
5850
 E1000_ICS_RXD_FIFO_PAR0E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 igb_defines.h Q0 Rx desc FIFO
5851
 E1000_ICS_TXD_FIFO_PAR0E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 igb_defines.h Q0 Tx desc FIFO
5852
 E1000_ICS_HOST_ARB_PARE1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR igb_defines.h host arb read buffer
5853
 E1000_ICS_PB_PARE1000_ICS_PB_PAR E1000_ICR_PB_PAR igb_defines.h packet buffer parity
5854
 E1000_ICS_RXD_FIFO_PAR1E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 igb_defines.h Q1 Rx desc FIFO
5855
 E1000_ICS_TXD_FIFO_PAR1E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 igb_defines.h Q1 Tx desc FIFO
5856
 E1000_ICS_DSWE1000_ICS_DSW E1000_ICR_DSW igb_defines.h 　
5857
 E1000_ICS_DOUTSYNCE1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC igb_defines.h NIC DMA out of sync
5858
 E1000_ICS_PHYINTE1000_ICS_PHYINT E1000_ICR_PHYINT igb_defines.h 　
5859
 E1000_ICS_EPRSTE1000_ICS_EPRST E1000_ICR_EPRST igb_defines.h 　
5860
 E1000_EICS_RX_QUEUE0E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 igb_defines.h Rx Queue 0 Interrupt
5861
 E1000_EICS_RX_QUEUE1E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 igb_defines.h Rx Queue 1 Interrupt
5862
 E1000_EICS_RX_QUEUE2E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 igb_defines.h Rx Queue 2 Interrupt
5863
 E1000_EICS_RX_QUEUE3E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 igb_defines.h Rx Queue 3 Interrupt
5864
 E1000_EICS_TX_QUEUE0E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 igb_defines.h Tx Queue 0 Interrupt
5865
 E1000_EICS_TX_QUEUE1E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 igb_defines.h Tx Queue 1 Interrupt
5866
 E1000_EICS_TX_QUEUE2E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 igb_defines.h Tx Queue 2 Interrupt
5867
 E1000_EICS_TX_QUEUE3E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 igb_defines.h Tx Queue 3 Interrupt
5868
 E1000_EICS_TCP_TIMERE1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER igb_defines.h TCP Timer
5869
 E1000_EICS_OTHERE1000_EICS_OTHER E1000_EICR_OTHER igb_defines.h Interrupt Cause Active
5870
 E1000_EITR_ITR_INT_MASKE1000_EITR_ITR_INT_MASK 0x0000FFFF igb_defines.h 　
5871
 E1000_TXDCTL_PTHRESHE1000_TXDCTL_PTHRESH 0x0000003F igb_defines.h TXDCTL Prefetch Threshold
5872
 E1000_TXDCTL_HTHRESHE1000_TXDCTL_HTHRESH 0x00003F00 igb_defines.h TXDCTL Host Threshold
5873
 E1000_TXDCTL_WTHRESHE1000_TXDCTL_WTHRESH 0x003F0000 igb_defines.h TXDCTL Writeback Threshold
5874
 E1000_TXDCTL_GRANE1000_TXDCTL_GRAN 0x01000000 igb_defines.h TXDCTL Granularity
5875
 E1000_TXDCTL_LWTHRESHE1000_TXDCTL_LWTHRESH 0xFE000000 igb_defines.h TXDCTL Low Threshold
5876
 E1000_TXDCTL_FULL_TX_DESC_WBE1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 igb_defines.h GRAN=1, WTHRESH=1
5877
 E1000_TXDCTL_MAX_TX_DESC_PREFETE1000_TXDCTL_MAX_TX_DESC_PREFET 0x0100001F igb_defines.h GRAN=1, PTHRESH=31
5878
 E1000_TXDCTL_COUNT_DESCE1000_TXDCTL_COUNT_DESC 0x00400000 igb_defines.h 　
5879
 FLOW_CONTROL_ADDRESS_LOWFLOW_CONTROL_ADDRESS_LOW 0x00C28001 igb_defines.h 　
5880
 FLOW_CONTROL_ADDRESS_HIGHFLOW_CONTROL_ADDRESS_HIGH 0x00000100 igb_defines.h 　
5881
 FLOW_CONTROL_TYPEFLOW_CONTROL_TYPE 0x8808 igb_defines.h 　
5882
 VLAN_TAG_SIZEVLAN_TAG_SIZE 4 igb_defines.h 802.3ac tag (not DMA'd)
5883
 E1000_VLAN_FILTER_TBL_SIZEE1000_VLAN_FILTER_TBL_SIZE 128 igb_defines.h VLAN Filter Table (4096 bits)
5884
 E1000_RAR_ENTRIESE1000_RAR_ENTRIES 15 igb_defines.h 　
5885
 E1000_RAH_AVE1000_RAH_AV 0x80000000 igb_defines.h Receive descriptor valid
5886
 E1000_RAL_MAC_ADDR_LENE1000_RAL_MAC_ADDR_LEN 4 igb_defines.h 　
5887
 E1000_RAH_MAC_ADDR_LENE1000_RAH_MAC_ADDR_LEN 2 igb_defines.h 　
5888
 E1000_RAH_POOL_MASKE1000_RAH_POOL_MASK 0x03FC0000 igb_defines.h 　
5889
 E1000_RAH_POOL_1E1000_RAH_POOL_1 0x00040000 igb_defines.h 　
5890
 E1000_SUCCESSE1000_SUCCESS 0 igb_defines.h 　
5891
 E1000_ERR_NVME1000_ERR_NVM 1 igb_defines.h 　
5892
 E1000_ERR_PHYE1000_ERR_PHY 2 igb_defines.h 　
5893
 E1000_ERR_CONFIGE1000_ERR_CONFIG 3 igb_defines.h 　
5894
 E1000_ERR_PARAME1000_ERR_PARAM 4 igb_defines.h 　
5895
 E1000_ERR_MAC_INITE1000_ERR_MAC_INIT 5 igb_defines.h 　
5896
 E1000_ERR_PHY_TYPEE1000_ERR_PHY_TYPE 6 igb_defines.h 　
5897
 E1000_ERR_RESETE1000_ERR_RESET 9 igb_defines.h 　
5898
 E1000_ERR_MASTER_REQUESTS_PENDIE1000_ERR_MASTER_REQUESTS_PENDI 10 igb_defines.h 　
5899
 E1000_ERR_HOST_INTERFACE_COMMANE1000_ERR_HOST_INTERFACE_COMMAN 11 igb_defines.h 　
5900
 E1000_BLK_PHY_RESETE1000_BLK_PHY_RESET 12 igb_defines.h 　
5901
 E1000_ERR_SWFW_SYNCE1000_ERR_SWFW_SYNC 13 igb_defines.h 　
5902
 E1000_NOT_IMPLEMENTEDE1000_NOT_IMPLEMENTED 14 igb_defines.h 　
5903
 E1000_ERR_MBXE1000_ERR_MBX 15 igb_defines.h 　
5904
 FIBER_LINK_UP_LIMITFIBER_LINK_UP_LIMIT 50 igb_defines.h 　
5905
 COPPER_LINK_UP_LIMITCOPPER_LINK_UP_LIMIT 10 igb_defines.h 　
5906
 PHY_AUTO_NEG_LIMITPHY_AUTO_NEG_LIMIT 45 igb_defines.h 　
5907
 PHY_FORCE_LIMITPHY_FORCE_LIMIT 20 igb_defines.h 　
5908
 MASTER_DISABLE_TIMEOUTMASTER_DISABLE_TIMEOUT 800 igb_defines.h 　
5909
 PHY_CFG_TIMEOUTPHY_CFG_TIMEOUT 100 igb_defines.h 　
5910
 MDIO_OWNERSHIP_TIMEOUTMDIO_OWNERSHIP_TIMEOUT 10 igb_defines.h 　
5911
 AUTO_READ_DONE_TIMEOUTAUTO_READ_DONE_TIMEOUT 10 igb_defines.h 　
5912
 E1000_FCRTH_RTHE1000_FCRTH_RTH 0x0000FFF8 igb_defines.h Mask Bits[15:3] for RTH
5913
 E1000_FCRTH_XFCEE1000_FCRTH_XFCE 0x80000000 igb_defines.h External Flow Control Enable
5914
 E1000_FCRTL_RTLE1000_FCRTL_RTL 0x0000FFF8 igb_defines.h Mask Bits[15:3] for RTL
5915
 E1000_FCRTL_XONEE1000_FCRTL_XONE 0x80000000 igb_defines.h Enable XON frame transmission
5916
 E1000_TXCW_FDE1000_TXCW_FD 0x00000020 igb_defines.h TXCW full duplex
5917
 E1000_TXCW_HDE1000_TXCW_HD 0x00000040 igb_defines.h TXCW half duplex
5918
 E1000_TXCW_PAUSEE1000_TXCW_PAUSE 0x00000080 igb_defines.h TXCW sym pause request
5919
 E1000_TXCW_ASM_DIRE1000_TXCW_ASM_DIR 0x00000100 igb_defines.h TXCW astm pause direction
5920
 E1000_TXCW_PAUSE_MASKE1000_TXCW_PAUSE_MASK 0x00000180 igb_defines.h TXCW pause request mask
5921
 E1000_TXCW_RFE1000_TXCW_RF 0x00003000 igb_defines.h TXCW remote fault
5922
 E1000_TXCW_NPE1000_TXCW_NP 0x00008000 igb_defines.h TXCW next page
5923
 E1000_TXCW_CWE1000_TXCW_CW 0x0000ffff igb_defines.h TxConfigWord mask
5924
 E1000_TXCW_TXCE1000_TXCW_TXC 0x40000000 igb_defines.h Transmit Config control
5925
 E1000_TXCW_ANEE1000_TXCW_ANE 0x80000000 igb_defines.h Auto-neg enable
5926
 E1000_RXCW_CWE1000_RXCW_CW 0x0000ffff igb_defines.h RxConfigWord mask
5927
 E1000_RXCW_NCE1000_RXCW_NC 0x04000000 igb_defines.h Receive config no carrier
5928
 E1000_RXCW_IVE1000_RXCW_IV 0x08000000 igb_defines.h Receive config invalid
5929
 E1000_RXCW_CCE1000_RXCW_CC 0x10000000 igb_defines.h Receive config change
5930
 E1000_RXCW_CE1000_RXCW_C 0x20000000 igb_defines.h Receive config
5931
 E1000_RXCW_SYNCHE1000_RXCW_SYNCH 0x40000000 igb_defines.h Receive config synch
5932
 E1000_RXCW_ANCE1000_RXCW_ANC 0x80000000 igb_defines.h Auto-neg complete
5933
 E1000_TSYNCTXCTL_VALIDE1000_TSYNCTXCTL_VALID 0x00000001 igb_defines.h tx timestamp valid
5934
 E1000_TSYNCTXCTL_ENABLEDE1000_TSYNCTXCTL_ENABLED 0x00000010 igb_defines.h enable tx timestampping
5935
 E1000_TSYNCRXCTL_VALIDE1000_TSYNCRXCTL_VALID 0x00000001 igb_defines.h rx timestamp valid
5936
 E1000_TSYNCRXCTL_TYPE_MASKE1000_TSYNCRXCTL_TYPE_MASK 0x0000000E igb_defines.h rx type mask
5937
 E1000_TSYNCRXCTL_TYPE_L2_V2E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 igb_defines.h 　
5938
 E1000_TSYNCRXCTL_TYPE_L4_V1E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 igb_defines.h 　
5939
 E1000_TSYNCRXCTL_TYPE_L2_L4_V2E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 igb_defines.h 　
5940
 E1000_TSYNCRXCTL_TYPE_ALLE1000_TSYNCRXCTL_TYPE_ALL 0x08 igb_defines.h 　
5941
 E1000_TSYNCRXCTL_TYPE_EVENT_V2E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A igb_defines.h 　
5942
 E1000_TSYNCRXCTL_ENABLEDE1000_TSYNCRXCTL_ENABLED 0x00000010 igb_defines.h enable rx timestampping
5943
 E1000_TSYNCRXCFG_PTP_V1_CTRLT_ME1000_TSYNCRXCFG_PTP_V1_CTRLT_M 0x000000FF igb_defines.h 　
5944
 E1000_TSYNCRXCFG_PTP_V1_SYNC_MEE1000_TSYNCRXCFG_PTP_V1_SYNC_ME 0x00 igb_defines.h 　
5945
 E1000_TSYNCRXCFG_PTP_V1_DELAY_RE1000_TSYNCRXCFG_PTP_V1_DELAY_R 0x01 igb_defines.h 　
5946
 E1000_TSYNCRXCFG_PTP_V1_FOLLOWUE1000_TSYNCRXCFG_PTP_V1_FOLLOWU 0x02 igb_defines.h 　
5947
 E1000_TSYNCRXCFG_PTP_V1_DELAY_RE1000_TSYNCRXCFG_PTP_V1_DELAY_R 0x03 igb_defines.h 　
5948
 E1000_TSYNCRXCFG_PTP_V1_MANAGEME1000_TSYNCRXCFG_PTP_V1_MANAGEM 0x04 igb_defines.h 　
5949
 E1000_TSYNCRXCFG_PTP_V2_MSGID_ME1000_TSYNCRXCFG_PTP_V2_MSGID_M 0x00000F00 igb_defines.h 　
5950
 E1000_TSYNCRXCFG_PTP_V2_SYNC_MEE1000_TSYNCRXCFG_PTP_V2_SYNC_ME 0x0000 igb_defines.h 　
5951
 E1000_TSYNCRXCFG_PTP_V2_DELAY_RE1000_TSYNCRXCFG_PTP_V2_DELAY_R 0x0100 igb_defines.h 　
5952
 E1000_TSYNCRXCFG_PTP_V2_PATH_DEE1000_TSYNCRXCFG_PTP_V2_PATH_DE 0x0200 igb_defines.h 　
5953
 E1000_TSYNCRXCFG_PTP_V2_PATH_DEE1000_TSYNCRXCFG_PTP_V2_PATH_DE 0x0300 igb_defines.h 　
5954
 E1000_TSYNCRXCFG_PTP_V2_FOLLOWUE1000_TSYNCRXCFG_PTP_V2_FOLLOWU 0x0800 igb_defines.h 　
5955
 E1000_TSYNCRXCFG_PTP_V2_DELAY_RE1000_TSYNCRXCFG_PTP_V2_DELAY_R 0x0900 igb_defines.h 　
5956
 E1000_TSYNCRXCFG_PTP_V2_PATH_DEE1000_TSYNCRXCFG_PTP_V2_PATH_DE 0x0A00 igb_defines.h 　
5957
 E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE1000_TSYNCRXCFG_PTP_V2_ANNOUNC 0x0B00 igb_defines.h 　
5958
 E1000_TSYNCRXCFG_PTP_V2_SIGNALLE1000_TSYNCRXCFG_PTP_V2_SIGNALL 0x0C00 igb_defines.h 　
5959
 E1000_TSYNCRXCFG_PTP_V2_MANAGEME1000_TSYNCRXCFG_PTP_V2_MANAGEM 0x0D00 igb_defines.h 　
5960
 E1000_TIMINCA_16NS_SHIFTE1000_TIMINCA_16NS_SHIFT 24 igb_defines.h 　
5961
 E1000_GCR_RXD_NO_SNOOPE1000_GCR_RXD_NO_SNOOP 0x00000001 igb_defines.h 　
5962
 E1000_GCR_RXDSCW_NO_SNOOPE1000_GCR_RXDSCW_NO_SNOOP 0x00000002 igb_defines.h 　
5963
 E1000_GCR_RXDSCR_NO_SNOOPE1000_GCR_RXDSCR_NO_SNOOP 0x00000004 igb_defines.h 　
5964
 E1000_GCR_TXD_NO_SNOOPE1000_GCR_TXD_NO_SNOOP 0x00000008 igb_defines.h 　
5965
 E1000_GCR_TXDSCW_NO_SNOOPE1000_GCR_TXDSCW_NO_SNOOP 0x00000010 igb_defines.h 　
5966
 E1000_GCR_TXDSCR_NO_SNOOPE1000_GCR_TXDSCR_NO_SNOOP 0x00000020 igb_defines.h 　
5967
 E1000_GCR_CMPL_TMOUT_MASKE1000_GCR_CMPL_TMOUT_MASK 0x0000F000 igb_defines.h 　
5968
 E1000_GCR_CMPL_TMOUT_10msE1000_GCR_CMPL_TMOUT_10ms 0x00001000 igb_defines.h 　
5969
 E1000_GCR_CMPL_TMOUT_RESENDE1000_GCR_CMPL_TMOUT_RESEND 0x00010000 igb_defines.h 　
5970
 E1000_GCR_CAP_VER2E1000_GCR_CAP_VER2 0x00040000 igb_defines.h 　
5971
 PCIE_NO_SNOOP_ALLPCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ E1000_GCR_RXDSCW_NO_SNOOP | \ E1000_GCR_RXDSCR_NO_SNOOP | \ E1000_GCR_TXD_NO_SNOO igb_defines.h 　
5972
 MII_CR_SPEED_SELECT_MSBMII_CR_SPEED_SELECT_MSB 0x0040 igb_defines.h bits 6,13: 10=1000, 01=100, 00=10
5973
 MII_CR_COLL_TEST_ENABLEMII_CR_COLL_TEST_ENABLE 0x0080 igb_defines.h Collision test enable
5974
 MII_CR_FULL_DUPLEXMII_CR_FULL_DUPLEX 0x0100 igb_defines.h FDX =1, half duplex =0
5975
 MII_CR_RESTART_AUTO_NEGMII_CR_RESTART_AUTO_NEG 0x0200 igb_defines.h Restart auto negotiation
5976
 MII_CR_ISOLATEMII_CR_ISOLATE 0x0400 igb_defines.h Isolate PHY from MII
5977
 MII_CR_POWER_DOWNMII_CR_POWER_DOWN 0x0800 igb_defines.h Power down
5978
 MII_CR_AUTO_NEG_ENMII_CR_AUTO_NEG_EN 0x1000 igb_defines.h Auto Neg Enable
5979
 MII_CR_SPEED_SELECT_LSBMII_CR_SPEED_SELECT_LSB 0x2000 igb_defines.h bits 6,13: 10=1000, 01=100, 00=10
5980
 MII_CR_LOOPBACKMII_CR_LOOPBACK 0x4000 igb_defines.h 0 = normal, 1 = loopback
5981
 MII_CR_RESETMII_CR_RESET 0x8000 igb_defines.h 0 = normal, 1 = PHY reset
5982
 MII_CR_SPEED_1000MII_CR_SPEED_1000 0x0040 igb_defines.h 　
5983
 MII_CR_SPEED_100MII_CR_SPEED_100 0x2000 igb_defines.h 　
5984
 MII_CR_SPEED_10MII_CR_SPEED_10 0x0000 igb_defines.h 　
5985
 MII_SR_EXTENDED_CAPSMII_SR_EXTENDED_CAPS 0x0001 igb_defines.h Extended register capabilities
5986
 MII_SR_JABBER_DETECTMII_SR_JABBER_DETECT 0x0002 igb_defines.h Jabber Detected
5987
 MII_SR_LINK_STATUSMII_SR_LINK_STATUS 0x0004 igb_defines.h Link Status 1 = link
5988
 MII_SR_AUTONEG_CAPSMII_SR_AUTONEG_CAPS 0x0008 igb_defines.h Auto Neg Capable
5989
 MII_SR_REMOTE_FAULTMII_SR_REMOTE_FAULT 0x0010 igb_defines.h Remote Fault Detect
5990
 MII_SR_AUTONEG_COMPLETEMII_SR_AUTONEG_COMPLETE 0x0020 igb_defines.h Auto Neg Complete
5991
 MII_SR_PREAMBLE_SUPPRESSMII_SR_PREAMBLE_SUPPRESS 0x0040 igb_defines.h Preamble may be suppressed
5992
 MII_SR_EXTENDED_STATUSMII_SR_EXTENDED_STATUS 0x0100 igb_defines.h Ext. status info in Reg 0x0F
5993
 MII_SR_100T2_HD_CAPSMII_SR_100T2_HD_CAPS 0x0200 igb_defines.h 100T2 Half Duplex Capable
5994
 MII_SR_100T2_FD_CAPSMII_SR_100T2_FD_CAPS 0x0400 igb_defines.h 100T2 Full Duplex Capable
5995
 MII_SR_10T_HD_CAPSMII_SR_10T_HD_CAPS 0x0800 igb_defines.h 10T Half Duplex Capable
5996
 MII_SR_10T_FD_CAPSMII_SR_10T_FD_CAPS 0x1000 igb_defines.h 10T Full Duplex Capable
5997
 MII_SR_100X_HD_CAPSMII_SR_100X_HD_CAPS 0x2000 igb_defines.h 100X Half Duplex Capable
5998
 MII_SR_100X_FD_CAPSMII_SR_100X_FD_CAPS 0x4000 igb_defines.h 100X Full Duplex Capable
5999
 MII_SR_100T4_CAPSMII_SR_100T4_CAPS 0x8000 igb_defines.h 100T4 Capable
6000
 NWAY_AR_SELECTOR_FIELDNWAY_AR_SELECTOR_FIELD 0x0001 igb_defines.h indicates IEEE 802.3 CSMA/CD
6001
 NWAY_AR_10T_HD_CAPSNWAY_AR_10T_HD_CAPS 0x0020 igb_defines.h 10T Half Duplex Capable
6002
 NWAY_AR_10T_FD_CAPSNWAY_AR_10T_FD_CAPS 0x0040 igb_defines.h 10T Full Duplex Capable
6003
 NWAY_AR_100TX_HD_CAPSNWAY_AR_100TX_HD_CAPS 0x0080 igb_defines.h 100TX Half Duplex Capable
6004
 NWAY_AR_100TX_FD_CAPSNWAY_AR_100TX_FD_CAPS 0x0100 igb_defines.h 100TX Full Duplex Capable
6005
 NWAY_AR_100T4_CAPSNWAY_AR_100T4_CAPS 0x0200 igb_defines.h 100T4 Capable
6006
 NWAY_AR_PAUSENWAY_AR_PAUSE 0x0400 igb_defines.h Pause operation desired
6007
 NWAY_AR_ASM_DIRNWAY_AR_ASM_DIR 0x0800 igb_defines.h Asymmetric Pause Direction bit
6008
 NWAY_AR_REMOTE_FAULTNWAY_AR_REMOTE_FAULT 0x2000 igb_defines.h Remote Fault detected
6009
 NWAY_AR_NEXT_PAGENWAY_AR_NEXT_PAGE 0x8000 igb_defines.h Next Page ability supported
6010
 NWAY_LPAR_SELECTOR_FIELDNWAY_LPAR_SELECTOR_FIELD 0x0000 igb_defines.h LP protocol selector field
6011
 NWAY_LPAR_10T_HD_CAPSNWAY_LPAR_10T_HD_CAPS 0x0020 igb_defines.h LP is 10T Half Duplex Capable
6012
 NWAY_LPAR_10T_FD_CAPSNWAY_LPAR_10T_FD_CAPS 0x0040 igb_defines.h LP is 10T Full Duplex Capable
6013
 NWAY_LPAR_100TX_HD_CAPSNWAY_LPAR_100TX_HD_CAPS 0x0080 igb_defines.h LP is 100TX Half Duplex Capable
6014
 NWAY_LPAR_100TX_FD_CAPSNWAY_LPAR_100TX_FD_CAPS 0x0100 igb_defines.h LP is 100TX Full Duplex Capable
6015
 NWAY_LPAR_100T4_CAPSNWAY_LPAR_100T4_CAPS 0x0200 igb_defines.h LP is 100T4 Capable
6016
 NWAY_LPAR_PAUSENWAY_LPAR_PAUSE 0x0400 igb_defines.h LP Pause operation desired
6017
 NWAY_LPAR_ASM_DIRNWAY_LPAR_ASM_DIR 0x0800 igb_defines.h LP Asymmetric Pause Direction bit
6018
 NWAY_LPAR_REMOTE_FAULTNWAY_LPAR_REMOTE_FAULT 0x2000 igb_defines.h LP has detected Remote Fault
6019
 NWAY_LPAR_ACKNOWLEDGENWAY_LPAR_ACKNOWLEDGE 0x4000 igb_defines.h LP has rx'd link code word
6020
 NWAY_LPAR_NEXT_PAGENWAY_LPAR_NEXT_PAGE 0x8000 igb_defines.h Next Page ability supported
6021
 NWAY_ER_LP_NWAY_CAPSNWAY_ER_LP_NWAY_CAPS 0x0001 igb_defines.h LP has Auto Neg Capability
6022
 NWAY_ER_PAGE_RXDNWAY_ER_PAGE_RXD 0x0002 igb_defines.h LP is 10T Half Duplex Capable
6023
 NWAY_ER_NEXT_PAGE_CAPSNWAY_ER_NEXT_PAGE_CAPS 0x0004 igb_defines.h LP is 10T Full Duplex Capable
6024
 NWAY_ER_LP_NEXT_PAGE_CAPSNWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 igb_defines.h LP is 100TX Half Duplex Capable
6025
 NWAY_ER_PAR_DETECT_FAULTNWAY_ER_PAR_DETECT_FAULT 0x0010 igb_defines.h LP is 100TX Full Duplex Capable
6026
 CR_1000T_ASYM_PAUSECR_1000T_ASYM_PAUSE 0x0080 igb_defines.h Advertise asymmetric pause bit
6027
 CR_1000T_HD_CAPSCR_1000T_HD_CAPS 0x0100 igb_defines.h Advertise 1000T HD capability
6028
 CR_1000T_FD_CAPSCR_1000T_FD_CAPS 0x0200 igb_defines.h Advertise 1000T FD capability
6029
 CR_1000T_REPEATER_DTECR_1000T_REPEATER_DTE 0x0400 igb_defines.h 1=Repeater/switch device port
6030
 CR_1000T_MS_VALUECR_1000T_MS_VALUE 0x0800 igb_defines.h 1=Configure PHY as Master
6031
 CR_1000T_MS_ENABLECR_1000T_MS_ENABLE 0x1000 igb_defines.h 1=Master/Slave manual config value
6032
 CR_1000T_TEST_MODE_NORMALCR_1000T_TEST_MODE_NORMAL 0x0000 igb_defines.h Normal Operation
6033
 CR_1000T_TEST_MODE_1CR_1000T_TEST_MODE_1 0x2000 igb_defines.h Transmit Waveform test
6034
 CR_1000T_TEST_MODE_2CR_1000T_TEST_MODE_2 0x4000 igb_defines.h Master Transmit Jitter test
6035
 CR_1000T_TEST_MODE_3CR_1000T_TEST_MODE_3 0x6000 igb_defines.h Slave Transmit Jitter test
6036
 CR_1000T_TEST_MODE_4CR_1000T_TEST_MODE_4 0x8000 igb_defines.h Transmitter Distortion test
6037
 SR_1000T_IDLE_ERROR_CNTSR_1000T_IDLE_ERROR_CNT 0x00FF igb_defines.h Num idle errors since last read
6038
 SR_1000T_ASYM_PAUSE_DIRSR_1000T_ASYM_PAUSE_DIR 0x0100 igb_defines.h LP asymmetric pause direction bit
6039
 SR_1000T_LP_HD_CAPSSR_1000T_LP_HD_CAPS 0x0400 igb_defines.h LP is 1000T HD capable
6040
 SR_1000T_LP_FD_CAPSSR_1000T_LP_FD_CAPS 0x0800 igb_defines.h LP is 1000T FD capable
6041
 SR_1000T_REMOTE_RX_STATUSSR_1000T_REMOTE_RX_STATUS 0x1000 igb_defines.h Remote receiver OK
6042
 SR_1000T_LOCAL_RX_STATUSSR_1000T_LOCAL_RX_STATUS 0x2000 igb_defines.h Local receiver OK
6043
 SR_1000T_MS_CONFIG_RESSR_1000T_MS_CONFIG_RES 0x4000 igb_defines.h 1=Local Tx is Master, 0=Slave
6044
 SR_1000T_MS_CONFIG_FAULTSR_1000T_MS_CONFIG_FAULT 0x8000 igb_defines.h Master/Slave config fault
6045
 SR_1000T_PHY_EXCESSIVE_IDLE_ERRSR_1000T_PHY_EXCESSIVE_IDLE_ERR 5 igb_defines.h 　
6046
 PHY_CONTROLPHY_CONTROL 0x00 igb_defines.h Control Register
6047
 PHY_STATUSPHY_STATUS 0x01 igb_defines.h Status Register
6048
 PHY_ID1PHY_ID1 0x02 igb_defines.h Phy Id Reg (word 1)
6049
 PHY_ID2PHY_ID2 0x03 igb_defines.h Phy Id Reg (word 2)
6050
 PHY_AUTONEG_ADVPHY_AUTONEG_ADV 0x04 igb_defines.h Autoneg Advertisement
6051
 PHY_LP_ABILITYPHY_LP_ABILITY 0x05 igb_defines.h Link Partner Ability (Base Page)
6052
 PHY_AUTONEG_EXPPHY_AUTONEG_EXP 0x06 igb_defines.h Autoneg Expansion Reg
6053
 PHY_NEXT_PAGE_TXPHY_NEXT_PAGE_TX 0x07 igb_defines.h Next Page Tx
6054
 PHY_LP_NEXT_PAGEPHY_LP_NEXT_PAGE 0x08 igb_defines.h Link Partner Next Page
6055
 PHY_1000T_CTRLPHY_1000T_CTRL 0x09 igb_defines.h 1000Base-T Control Reg
6056
 PHY_1000T_STATUSPHY_1000T_STATUS 0x0A igb_defines.h 1000Base-T Status Reg
6057
 PHY_EXT_STATUSPHY_EXT_STATUS 0x0F igb_defines.h Extended Status Reg
6058
 PHY_CONTROL_LBPHY_CONTROL_LB 0x4000 igb_defines.h PHY Loopback bit
6059
 E1000_EECD_SKE1000_EECD_SK 0x00000001 igb_defines.h NVM Clock
6060
 E1000_EECD_CSE1000_EECD_CS 0x00000002 igb_defines.h NVM Chip Select
6061
 E1000_EECD_DIE1000_EECD_DI 0x00000004 igb_defines.h NVM Data In
6062
 E1000_EECD_DOE1000_EECD_DO 0x00000008 igb_defines.h NVM Data Out
6063
 E1000_EECD_FWE_MASKE1000_EECD_FWE_MASK 0x00000030 igb_defines.h 　
6064
 E1000_EECD_FWE_DISE1000_EECD_FWE_DIS 0x00000010 igb_defines.h Disable FLASH writes
6065
 E1000_EECD_FWE_ENE1000_EECD_FWE_EN 0x00000020 igb_defines.h Enable FLASH writes
6066
 E1000_EECD_FWE_SHIFTE1000_EECD_FWE_SHIFT 4 igb_defines.h 　
6067
 E1000_EECD_REQE1000_EECD_REQ 0x00000040 igb_defines.h NVM Access Request
6068
 E1000_EECD_GNTE1000_EECD_GNT 0x00000080 igb_defines.h NVM Access Grant
6069
 E1000_EECD_PRESE1000_EECD_PRES 0x00000100 igb_defines.h NVM Present
6070
 E1000_EECD_SIZEE1000_EECD_SIZE 0x00000200 igb_defines.h NVM Size (0=64 word 1=256 word)
6071
 E1000_EECD_ADDR_BITSE1000_EECD_ADDR_BITS 0x00000400 igb_defines.h 　
6072
 E1000_EECD_TYPEE1000_EECD_TYPE 0x00002000 igb_defines.h NVM Type (1-SPI, 0-Microwire)
6073
 E1000_NVM_GRANT_ATTEMPTSE1000_NVM_GRANT_ATTEMPTS 1000 igb_defines.h NVM # attempts to gain grant
6074
 E1000_EECD_AUTO_RDE1000_EECD_AUTO_RD 0x00000200 igb_defines.h NVM Auto Read done
6075
 E1000_EECD_SIZE_EX_MASKE1000_EECD_SIZE_EX_MASK 0x00007800 igb_defines.h NVM Size
6076
 E1000_EECD_SIZE_EX_SHIFTE1000_EECD_SIZE_EX_SHIFT 11 igb_defines.h 　
6077
 E1000_EECD_NVADDSE1000_EECD_NVADDS 0x00018000 igb_defines.h NVM Address Size
6078
 E1000_EECD_SELSHADE1000_EECD_SELSHAD 0x00020000 igb_defines.h Select Shadow RAM
6079
 E1000_EECD_INITSRAME1000_EECD_INITSRAM 0x00040000 igb_defines.h Initialize Shadow RAM
6080
 E1000_EECD_FLUPDE1000_EECD_FLUPD 0x00080000 igb_defines.h Update FLASH
6081
 E1000_EECD_AUPDENE1000_EECD_AUPDEN 0x00100000 igb_defines.h Enable Autonomous FLASH update
6082
 E1000_EECD_SHADVE1000_EECD_SHADV 0x00200000 igb_defines.h Shadow RAM Data Valid
6083
 E1000_EECD_SEC1VALE1000_EECD_SEC1VAL 0x00400000 igb_defines.h Sector One Valid
6084
 E1000_EECD_SECVAL_SHIFTE1000_EECD_SECVAL_SHIFT 22 igb_defines.h 　
6085
 E1000_EECD_SEC1VAL_VALID_MASKE1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) igb_defines.h 　
6086
 E1000_NVM_SWDPIN0E1000_NVM_SWDPIN0 0x0001 igb_defines.h SWDPIN 0 NVM Value
6087
 E1000_NVM_LED_LOGICE1000_NVM_LED_LOGIC 0x0020 igb_defines.h Led Logic Word
6088
 E1000_NVM_RW_REG_DATAE1000_NVM_RW_REG_DATA 16 igb_defines.h Offset to data in NVM read/write regs
6089
 E1000_NVM_RW_REG_DONEE1000_NVM_RW_REG_DONE 2 igb_defines.h Offset to READ/WRITE done bit
6090
 E1000_NVM_RW_REG_STARTE1000_NVM_RW_REG_START 1 igb_defines.h Start operation
6091
 E1000_NVM_RW_ADDR_SHIFTE1000_NVM_RW_ADDR_SHIFT 2 igb_defines.h Shift to the address bits
6092
 E1000_NVM_POLL_WRITEE1000_NVM_POLL_WRITE 1 igb_defines.h Flag for polling for write complete
6093
 E1000_NVM_POLL_READE1000_NVM_POLL_READ 0 igb_defines.h Flag for polling for read complete
6094
 E1000_FLASH_UPDATESE1000_FLASH_UPDATES 2000 igb_defines.h 　
6095
 NVM_COMPATNVM_COMPAT 0x0003 igb_defines.h 　
6096
 NVM_ID_LED_SETTINGSNVM_ID_LED_SETTINGS 0x0004 igb_defines.h 　
6097
 NVM_VERSIONNVM_VERSION 0x0005 igb_defines.h 　
6098
 NVM_SERDES_AMPLITUDENVM_SERDES_AMPLITUDE 0x0006 igb_defines.h SERDES output amplitude
6099
 NVM_PHY_CLASS_WORDNVM_PHY_CLASS_WORD 0x0007 igb_defines.h 　
6100
 NVM_INIT_CONTROL1_REGNVM_INIT_CONTROL1_REG 0x000A igb_defines.h 　
6101
 NVM_INIT_CONTROL2_REGNVM_INIT_CONTROL2_REG 0x000F igb_defines.h 　
6102
 NVM_SWDEF_PINS_CTRL_PORT_1NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 igb_defines.h 　
6103
 NVM_INIT_CONTROL3_PORT_BNVM_INIT_CONTROL3_PORT_B 0x0014 igb_defines.h 　
6104
 NVM_INIT_3GIO_3NVM_INIT_3GIO_3 0x001A igb_defines.h 　
6105
 NVM_SWDEF_PINS_CTRL_PORT_0NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 igb_defines.h 　
6106
 NVM_INIT_CONTROL3_PORT_ANVM_INIT_CONTROL3_PORT_A 0x0024 igb_defines.h 　
6107
 NVM_CFGNVM_CFG 0x0012 igb_defines.h 　
6108
 NVM_FLASH_VERSIONNVM_FLASH_VERSION 0x0032 igb_defines.h 　
6109
 NVM_ALT_MAC_ADDR_PTRNVM_ALT_MAC_ADDR_PTR 0x0037 igb_defines.h 　
6110
 NVM_CHECKSUM_REGNVM_CHECKSUM_REG 0x003F igb_defines.h 　
6111
 E1000_NVM_CFG_DONE_PORT_0E1000_NVM_CFG_DONE_PORT_0 0x040000 igb_defines.h MNG config cycle done
6112
 E1000_NVM_CFG_DONE_PORT_1E1000_NVM_CFG_DONE_PORT_1 0x080000 igb_defines.h ...for second port
6113
 NVM_WORD0F_PAUSE_MASKNVM_WORD0F_PAUSE_MASK 0x3000 igb_defines.h 　
6114
 NVM_WORD0F_PAUSENVM_WORD0F_PAUSE 0x1000 igb_defines.h 　
6115
 NVM_WORD0F_ASM_DIRNVM_WORD0F_ASM_DIR 0x2000 igb_defines.h 　
6116
 NVM_WORD0F_ANENVM_WORD0F_ANE 0x0800 igb_defines.h 　
6117
 NVM_WORD0F_SWPDIO_EXT_MASKNVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 igb_defines.h 　
6118
 NVM_WORD0F_LPLUNVM_WORD0F_LPLU 0x0001 igb_defines.h 　
6119
 NVM_WORD1A_ASPM_MASKNVM_WORD1A_ASPM_MASK 0x000C igb_defines.h 　
6120
 NVM_SUMNVM_SUM 0xBABA igb_defines.h 　
6121
 NVM_MAC_ADDR_OFFSETNVM_MAC_ADDR_OFFSET 0 igb_defines.h 　
6122
 NVM_PBA_OFFSET_0NVM_PBA_OFFSET_0 8 igb_defines.h 　
6123
 NVM_PBA_OFFSET_1NVM_PBA_OFFSET_1 9 igb_defines.h 　
6124
 NVM_RESERVED_WORDNVM_RESERVED_WORD 0xFFFF igb_defines.h 　
6125
 NVM_PHY_CLASS_ANVM_PHY_CLASS_A 0x8000 igb_defines.h 　
6126
 NVM_SERDES_AMPLITUDE_MASKNVM_SERDES_AMPLITUDE_MASK 0x000F igb_defines.h 　
6127
 NVM_SIZE_MASKNVM_SIZE_MASK 0x1C00 igb_defines.h 　
6128
 NVM_SIZE_SHIFTNVM_SIZE_SHIFT 10 igb_defines.h 　
6129
 NVM_WORD_SIZE_BASE_SHIFTNVM_WORD_SIZE_BASE_SHIFT 6 igb_defines.h 　
6130
 NVM_SWDPIO_EXT_SHIFTNVM_SWDPIO_EXT_SHIFT 4 igb_defines.h 　
6131
 NVM_MAX_RETRY_SPINVM_MAX_RETRY_SPI 5000 igb_defines.h Max wait of 5ms, for RDY signal
6132
 NVM_READ_OPCODE_SPINVM_READ_OPCODE_SPI 0x03 igb_defines.h NVM read opcode
6133
 NVM_WRITE_OPCODE_SPINVM_WRITE_OPCODE_SPI 0x02 igb_defines.h NVM write opcode
6134
 NVM_A8_OPCODE_SPINVM_A8_OPCODE_SPI 0x08 igb_defines.h opcode bit-3 = address bit-8
6135
 NVM_WREN_OPCODE_SPINVM_WREN_OPCODE_SPI 0x06 igb_defines.h NVM set Write Enable latch
6136
 NVM_WRDI_OPCODE_SPINVM_WRDI_OPCODE_SPI 0x04 igb_defines.h NVM reset Write Enable latch
6137
 NVM_RDSR_OPCODE_SPINVM_RDSR_OPCODE_SPI 0x05 igb_defines.h NVM read Status register
6138
 NVM_WRSR_OPCODE_SPINVM_WRSR_OPCODE_SPI 0x01 igb_defines.h NVM write Status register
6139
 NVM_STATUS_RDY_SPINVM_STATUS_RDY_SPI 0x01 igb_defines.h 　
6140
 NVM_STATUS_WEN_SPINVM_STATUS_WEN_SPI 0x02 igb_defines.h 　
6141
 NVM_STATUS_BP0_SPINVM_STATUS_BP0_SPI 0x04 igb_defines.h 　
6142
 NVM_STATUS_BP1_SPINVM_STATUS_BP1_SPI 0x08 igb_defines.h 　
6143
 NVM_STATUS_WPEN_SPINVM_STATUS_WPEN_SPI 0x80 igb_defines.h 　
6144
 ID_LED_RESERVED_0000ID_LED_RESERVED_0000 0x0000 igb_defines.h 　
6145
 ID_LED_RESERVED_FFFFID_LED_RESERVED_FFFF 0xFFFF igb_defines.h 　
6146
 ID_LED_DEFAULTID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) igb_defines.h 　
6147
 ID_LED_DEF1_DEF2ID_LED_DEF1_DEF2 0x1 igb_defines.h 　
6148
 ID_LED_DEF1_ON2ID_LED_DEF1_ON2 0x2 igb_defines.h 　
6149
 ID_LED_DEF1_OFF2ID_LED_DEF1_OFF2 0x3 igb_defines.h 　
6150
 ID_LED_ON1_DEF2ID_LED_ON1_DEF2 0x4 igb_defines.h 　
6151
 ID_LED_ON1_ON2ID_LED_ON1_ON2 0x5 igb_defines.h 　
6152
 ID_LED_ON1_OFF2ID_LED_ON1_OFF2 0x6 igb_defines.h 　
6153
 ID_LED_OFF1_DEF2ID_LED_OFF1_DEF2 0x7 igb_defines.h 　
6154
 ID_LED_OFF1_ON2ID_LED_OFF1_ON2 0x8 igb_defines.h 　
6155
 ID_LED_OFF1_OFF2ID_LED_OFF1_OFF2 0x9 igb_defines.h 　
6156
 IGP_ACTIVITY_LED_MASKIGP_ACTIVITY_LED_MASK 0xFFFFF0FF igb_defines.h 　
6157
 IGP_ACTIVITY_LED_ENABLEIGP_ACTIVITY_LED_ENABLE 0x0300 igb_defines.h 　
6158
 IGP_LED3_MODEIGP_LED3_MODE 0x07000000 igb_defines.h 　
6159
 PCI_HEADER_TYPE_REGISTERPCI_HEADER_TYPE_REGISTER 0x0E igb_defines.h 　
6160
 PCIE_LINK_STATUSPCIE_LINK_STATUS 0x12 igb_defines.h 　
6161
 PCIE_DEVICE_CONTROL2PCIE_DEVICE_CONTROL2 0x28 igb_defines.h 　
6162
 PCI_HEADER_TYPE_MULTIFUNCPCI_HEADER_TYPE_MULTIFUNC 0x80 igb_defines.h 　
6163
 PCIE_LINK_WIDTH_MASKPCIE_LINK_WIDTH_MASK 0x3F0 igb_defines.h 　
6164
 PCIE_LINK_WIDTH_SHIFTPCIE_LINK_WIDTH_SHIFT 4 igb_defines.h 　
6165
 PCIE_DEVICE_CONTROL2_16msPCIE_DEVICE_CONTROL2_16ms 0x0005 igb_defines.h 　
6166
 ETH_ADDR_LENETH_ADDR_LEN 6 igb_defines.h 　
6167
 PHY_REVISION_MASKPHY_REVISION_MASK 0xFFFFFFF0 igb_defines.h 　
6168
 MAX_PHY_REG_ADDRESSMAX_PHY_REG_ADDRESS 0x1F igb_defines.h 5 bit address bus (0-0x1F)
6169
 MAX_PHY_MULTI_PAGE_REGMAX_PHY_MULTI_PAGE_REG 0xF igb_defines.h 　
6170
 M88E1000_E_PHY_IDM88E1000_E_PHY_ID 0x01410C50 igb_defines.h 　
6171
 M88E1000_I_PHY_IDM88E1000_I_PHY_ID 0x01410C30 igb_defines.h 　
6172
 M88E1011_I_PHY_IDM88E1011_I_PHY_ID 0x01410C20 igb_defines.h 　
6173
 IGP01E1000_I_PHY_IDIGP01E1000_I_PHY_ID 0x02A80380 igb_defines.h 　
6174
 M88E1011_I_REV_4M88E1011_I_REV_4 0x04 igb_defines.h 　
6175
 M88E1111_I_PHY_IDM88E1111_I_PHY_ID 0x01410CC0 igb_defines.h 　
6176
 GG82563_E_PHY_IDGG82563_E_PHY_ID 0x01410CA0 igb_defines.h 　
6177
 IGP03E1000_E_PHY_IDIGP03E1000_E_PHY_ID 0x02A80390 igb_defines.h 　
6178
 IFE_E_PHY_IDIFE_E_PHY_ID 0x02A80330 igb_defines.h 　
6179
 IFE_PLUS_E_PHY_IDIFE_PLUS_E_PHY_ID 0x02A80320 igb_defines.h 　
6180
 IFE_C_E_PHY_IDIFE_C_E_PHY_ID 0x02A80310 igb_defines.h 　
6181
 IGP04E1000_E_PHY_IDIGP04E1000_E_PHY_ID 0x02A80391 igb_defines.h 　
6182
 M88_VENDORM88_VENDOR 0x0141 igb_defines.h 　
6183
 M88E1000_PHY_SPEC_CTRLM88E1000_PHY_SPEC_CTRL 0x10 igb_defines.h PHY Specific Control Register
6184
 M88E1000_PHY_SPEC_STATUSM88E1000_PHY_SPEC_STATUS 0x11 igb_defines.h PHY Specific Status Register
6185
 M88E1000_INT_ENABLEM88E1000_INT_ENABLE 0x12 igb_defines.h Interrupt Enable Register
6186
 M88E1000_INT_STATUSM88E1000_INT_STATUS 0x13 igb_defines.h Interrupt Status Register
6187
 M88E1000_EXT_PHY_SPEC_CTRLM88E1000_EXT_PHY_SPEC_CTRL 0x14 igb_defines.h Extended PHY Specific Control
6188
 M88E1000_RX_ERR_CNTRM88E1000_RX_ERR_CNTR 0x15 igb_defines.h Receive Error Counter
6189
 M88E1000_PHY_EXT_CTRLM88E1000_PHY_EXT_CTRL 0x1A igb_defines.h PHY extend control register
6190
 M88E1000_PHY_PAGE_SELECTM88E1000_PHY_PAGE_SELECT 0x1D igb_defines.h Reg 29 for page number setting
6191
 M88E1000_PHY_GEN_CONTROLM88E1000_PHY_GEN_CONTROL 0x1E igb_defines.h Its meaning depends on reg 29
6192
 M88E1000_PHY_VCO_REG_BIT8M88E1000_PHY_VCO_REG_BIT8 0x100 igb_defines.h Bits 8 & 11 are adjusted for
6193
 M88E1000_PHY_VCO_REG_BIT11M88E1000_PHY_VCO_REG_BIT11 0x800 igb_defines.h improved BER performance
6194
 M88E1000_PSCR_JABBER_DISABLEM88E1000_PSCR_JABBER_DISABLE 0x0001 igb_defines.h 1=Jabber Function disabled
6195
 M88E1000_PSCR_POLARITY_REVERSALM88E1000_PSCR_POLARITY_REVERSAL 0x0002 igb_defines.h 1=Polarity Reverse enabled
6196
 M88E1000_PSCR_SQE_TESTM88E1000_PSCR_SQE_TEST 0x0004 igb_defines.h 1=SQE Test enabled
6197
 M88E1000_PSCR_CLK125_DISABLEM88E1000_PSCR_CLK125_DISABLE 0x0010 igb_defines.h 　
6198
 M88E1000_PSCR_MDI_MANUAL_MODEM88E1000_PSCR_MDI_MANUAL_MODE 0x0000 igb_defines.h MDI Crossover Mode bits 6:5
6199
 M88E1000_PSCR_MDIX_MANUAL_MODEM88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 igb_defines.h Manual MDIX configuration
6200
 M88E1000_PSCR_AUTO_X_1000TM88E1000_PSCR_AUTO_X_1000T 0x0040 igb_defines.h 　
6201
 M88E1000_PSCR_AUTO_X_MODEM88E1000_PSCR_AUTO_X_MODE 0x0060 igb_defines.h 　
6202
 M88E1000_PSCR_EN_10BT_EXT_DISTM88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 igb_defines.h 　
6203
 M88E1000_PSCR_MII_5BIT_ENABLEM88E1000_PSCR_MII_5BIT_ENABLE 0x0100 igb_defines.h 　
6204
 M88E1000_PSCR_SCRAMBLER_DISABLEM88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 igb_defines.h 1=Scrambler disable
6205
 M88E1000_PSCR_FORCE_LINK_GOODM88E1000_PSCR_FORCE_LINK_GOOD 0x0400 igb_defines.h 1=Force link good
6206
 M88E1000_PSCR_ASSERT_CRS_ON_TXM88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 igb_defines.h 1=Assert CRS on Tx
6207
 M88E1000_PSSR_JABBERM88E1000_PSSR_JABBER 0x0001 igb_defines.h 1=Jabber
6208
 M88E1000_PSSR_REV_POLARITYM88E1000_PSSR_REV_POLARITY 0x0002 igb_defines.h 1=Polarity reversed
6209
 M88E1000_PSSR_DOWNSHIFTM88E1000_PSSR_DOWNSHIFT 0x0020 igb_defines.h 1=Downshifted
6210
 M88E1000_PSSR_MDIXM88E1000_PSSR_MDIX 0x0040 igb_defines.h 1=MDIX; 0=MDI
6211
 M88E1000_PSSR_CABLE_LENGTHM88E1000_PSSR_CABLE_LENGTH 0x0380 igb_defines.h 　
6212
 M88E1000_PSSR_LINKM88E1000_PSSR_LINK 0x0400 igb_defines.h 1=Link up, 0=Link down
6213
 M88E1000_PSSR_SPD_DPLX_RESOLVEDM88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 igb_defines.h 1=Speed & Duplex resolved
6214
 M88E1000_PSSR_PAGE_RCVDM88E1000_PSSR_PAGE_RCVD 0x1000 igb_defines.h 1=Page received
6215
 M88E1000_PSSR_DPLXM88E1000_PSSR_DPLX 0x2000 igb_defines.h 1=Duplex 0=Half Duplex
6216
 M88E1000_PSSR_SPEEDM88E1000_PSSR_SPEED 0xC000 igb_defines.h Speed, bits 14:15
6217
 M88E1000_PSSR_10MBSM88E1000_PSSR_10MBS 0x0000 igb_defines.h 00=10Mbs
6218
 M88E1000_PSSR_100MBSM88E1000_PSSR_100MBS 0x4000 igb_defines.h 01=100Mbs
6219
 M88E1000_PSSR_1000MBSM88E1000_PSSR_1000MBS 0x8000 igb_defines.h 10=1000Mbs
6220
 M88E1000_PSSR_CABLE_LENGTH_SHIFM88E1000_PSSR_CABLE_LENGTH_SHIF 7 igb_defines.h 　
6221
 M88E1000_EPSCR_FIBER_LOOPBACKM88E1000_EPSCR_FIBER_LOOPBACK 0x4000 igb_defines.h 1=Fiber loopback
6222
 M88E1000_EPSCR_DOWN_NO_IDLEM88E1000_EPSCR_DOWN_NO_IDLE 0x8000 igb_defines.h 　
6223
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 igb_defines.h 　
6224
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0000 igb_defines.h 　
6225
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0400 igb_defines.h 　
6226
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0800 igb_defines.h 　
6227
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 igb_defines.h 　
6228
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 igb_defines.h 　
6229
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0000 igb_defines.h 　
6230
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0100 igb_defines.h 　
6231
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0200 igb_defines.h 　
6232
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 igb_defines.h 　
6233
 M88E1000_EPSCR_TX_CLK_2_5M88E1000_EPSCR_TX_CLK_2_5 0x0060 igb_defines.h 2.5 MHz TX_CLK
6234
 M88E1000_EPSCR_TX_CLK_25M88E1000_EPSCR_TX_CLK_25 0x0070 igb_defines.h 25 MHz TX_CLK
6235
 M88E1000_EPSCR_TX_CLK_0M88E1000_EPSCR_TX_CLK_0 0x0000 igb_defines.h NO TX_CLK
6236
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 igb_defines.h 　
6237
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0000 igb_defines.h 　
6238
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0200 igb_defines.h 　
6239
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0400 igb_defines.h 　
6240
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0600 igb_defines.h 　
6241
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0800 igb_defines.h 　
6242
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0A00 igb_defines.h 　
6243
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0C00 igb_defines.h 　
6244
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 igb_defines.h 　
6245
 GG82563_PAGE_SHIFTGG82563_PAGE_SHIFT 5 igb_defines.h 　
6246
 GG82563_MIN_ALT_REGGG82563_MIN_ALT_REG 30 igb_defines.h 　
6247
 GG82563_PHY_SPEC_CTRLGG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) igb_defines.h PHY Specific Control
6248
 GG82563_PHY_SPEC_STATUSGG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) igb_defines.h PHY Specific Status
6249
 GG82563_PHY_INT_ENABLEGG82563_PHY_INT_ENABLE GG82563_REG(0, 18) igb_defines.h Interrupt Enable
6250
 GG82563_PHY_SPEC_STATUS_2GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) igb_defines.h PHY Specific Status 2
6251
 GG82563_PHY_RX_ERR_CNTRGG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) igb_defines.h Receive Error Counter
6252
 GG82563_PHY_PAGE_SELECTGG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) igb_defines.h Page Select
6253
 GG82563_PHY_SPEC_CTRL_2GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) igb_defines.h PHY Specific Control 2
6254
 GG82563_PHY_PAGE_SELECT_ALTGG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) igb_defines.h Alternate Page Select
6255
 GG82563_PHY_TEST_CLK_CTRLGG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) igb_defines.h Test Clock Control (use reg. 29 to select)
6256
 GG82563_PHY_MAC_SPEC_CTRLGG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) igb_defines.h MAC Specific Control Register
6257
 GG82563_PHY_MAC_SPEC_CTRL_2GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) igb_defines.h MAC Specific Control 2
6258
 GG82563_PHY_DSP_DISTANCEGG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) igb_defines.h DSP Distance
6259
 GG82563_PHY_KMRN_MODE_CTRLGG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) igb_defines.h Kumeran Mode Control
6260
 GG82563_PHY_PORT_RESETGG82563_PHY_PORT_RESET GG82563_REG(193, 17) igb_defines.h Port Reset
6261
 GG82563_PHY_REVISION_IDGG82563_PHY_REVISION_ID GG82563_REG(193, 18) igb_defines.h Revision ID
6262
 GG82563_PHY_DEVICE_IDGG82563_PHY_DEVICE_ID GG82563_REG(193, 19) igb_defines.h Device ID
6263
 GG82563_PHY_PWR_MGMT_CTRLGG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) igb_defines.h Power Management Control
6264
 GG82563_PHY_RATE_ADAPT_CTRLGG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) igb_defines.h Rate Adaptation Control
6265
 GG82563_PHY_KMRN_FIFO_CTRL_STATGG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) igb_defines.h FIFO's Control/Status
6266
 GG82563_PHY_KMRN_CTRLGG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) igb_defines.h Control
6267
 GG82563_PHY_INBAND_CTRLGG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) igb_defines.h Inband Control
6268
 GG82563_PHY_KMRN_DIAGNOSTICGG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) igb_defines.h Diagnostic
6269
 GG82563_PHY_ACK_TIMEOUTSGG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) igb_defines.h Acknowledge Timeouts
6270
 GG82563_PHY_ADV_ABILITYGG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) igb_defines.h Advertised Ability
6271
 GG82563_PHY_LINK_PARTNER_ADV_ABGG82563_PHY_LINK_PARTNER_ADV_AB GG82563_REG(194, 23) igb_defines.h Link Partner Advertised Ability
6272
 GG82563_PHY_ADV_NEXT_PAGEGG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) igb_defines.h Advertised Next Page
6273
 GG82563_PHY_LINK_PARTNER_ADV_NEGG82563_PHY_LINK_PARTNER_ADV_NE GG82563_REG(194, 25) igb_defines.h Link Partner Advertised Next page
6274
 GG82563_PHY_KMRN_MISCGG82563_PHY_KMRN_MISC GG82563_REG(194, 26) igb_defines.h Misc.
6275
 E1000_MDIC_DATA_MASKE1000_MDIC_DATA_MASK 0x0000FFFF igb_defines.h 　
6276
 E1000_MDIC_REG_MASKE1000_MDIC_REG_MASK 0x001F0000 igb_defines.h 　
6277
 E1000_MDIC_REG_SHIFTE1000_MDIC_REG_SHIFT 16 igb_defines.h 　
6278
 E1000_MDIC_PHY_MASKE1000_MDIC_PHY_MASK 0x03E00000 igb_defines.h 　
6279
 E1000_MDIC_PHY_SHIFTE1000_MDIC_PHY_SHIFT 21 igb_defines.h 　
6280
 E1000_MDIC_OP_WRITEE1000_MDIC_OP_WRITE 0x04000000 igb_defines.h 　
6281
 E1000_MDIC_OP_READE1000_MDIC_OP_READ 0x08000000 igb_defines.h 　
6282
 E1000_MDIC_READYE1000_MDIC_READY 0x10000000 igb_defines.h 　
6283
 E1000_MDIC_INT_ENE1000_MDIC_INT_EN 0x20000000 igb_defines.h 　
6284
 E1000_MDIC_ERRORE1000_MDIC_ERROR 0x40000000 igb_defines.h 　
6285
 E1000_GEN_CTL_READYE1000_GEN_CTL_READY 0x80000000 igb_defines.h 　
6286
 E1000_GEN_CTL_ADDRESS_SHIFTE1000_GEN_CTL_ADDRESS_SHIFT 8 igb_defines.h 　
6287
 E1000_GEN_POLL_TIMEOUTE1000_GEN_POLL_TIMEOUT 640 igb_defines.h 　
6288
 E1000_LSECTXCAP_SUM_MASKE1000_LSECTXCAP_SUM_MASK 0x00FF0000 igb_defines.h 　
6289
 E1000_LSECTXCAP_SUM_SHIFTE1000_LSECTXCAP_SUM_SHIFT 16 igb_defines.h 　
6290
 E1000_LSECRXCAP_SUM_MASKE1000_LSECRXCAP_SUM_MASK 0x00FF0000 igb_defines.h 　
6291
 E1000_LSECRXCAP_SUM_SHIFTE1000_LSECRXCAP_SUM_SHIFT 16 igb_defines.h 　
6292
 E1000_LSECTXCTRL_EN_MASKE1000_LSECTXCTRL_EN_MASK 0x00000003 igb_defines.h 　
6293
 E1000_LSECTXCTRL_DISABLEE1000_LSECTXCTRL_DISABLE 0x0 igb_defines.h 　
6294
 E1000_LSECTXCTRL_AUTHE1000_LSECTXCTRL_AUTH 0x1 igb_defines.h 　
6295
 E1000_LSECTXCTRL_AUTH_ENCRYPTE1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 igb_defines.h 　
6296
 E1000_LSECTXCTRL_AISCIE1000_LSECTXCTRL_AISCI 0x00000020 igb_defines.h 　
6297
 E1000_LSECTXCTRL_PNTHRSH_MASKE1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 igb_defines.h 　
6298
 E1000_LSECTXCTRL_RSV_MASKE1000_LSECTXCTRL_RSV_MASK 0x000000D8 igb_defines.h 　
6299
 E1000_LSECRXCTRL_EN_MASKE1000_LSECRXCTRL_EN_MASK 0x0000000C igb_defines.h 　
6300
 E1000_LSECRXCTRL_EN_SHIFTE1000_LSECRXCTRL_EN_SHIFT 2 igb_defines.h 　
6301
 E1000_LSECRXCTRL_DISABLEE1000_LSECRXCTRL_DISABLE 0x0 igb_defines.h 　
6302
 E1000_LSECRXCTRL_CHECKE1000_LSECRXCTRL_CHECK 0x1 igb_defines.h 　
6303
 E1000_LSECRXCTRL_STRICTE1000_LSECRXCTRL_STRICT 0x2 igb_defines.h 　
6304
 E1000_LSECRXCTRL_DROPE1000_LSECRXCTRL_DROP 0x3 igb_defines.h 　
6305
 E1000_LSECRXCTRL_PLSHE1000_LSECRXCTRL_PLSH 0x00000040 igb_defines.h 　
6306
 E1000_LSECRXCTRL_RPE1000_LSECRXCTRL_RP 0x00000080 igb_defines.h 　
6307
 E1000_LSECRXCTRL_RSV_MASKE1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 igb_defines.h 　
6308
 E1000_DEV_ID_82576E1000_DEV_ID_82576 0x10C9 igb_hw.h 　
6309
 E1000_DEV_ID_82576_FIBERE1000_DEV_ID_82576_FIBER 0x10E6 igb_hw.h 　
6310
 E1000_DEV_ID_82576_SERDESE1000_DEV_ID_82576_SERDES 0x10E7 igb_hw.h 　
6311
 E1000_DEV_ID_82576_QUAD_COPPERE1000_DEV_ID_82576_QUAD_COPPER 0x10E8 igb_hw.h 　
6312
 E1000_DEV_ID_82576_NSE1000_DEV_ID_82576_NS 0x150A igb_hw.h 　
6313
 E1000_DEV_ID_82576_NS_SERDESE1000_DEV_ID_82576_NS_SERDES 0x1518 igb_hw.h 　
6314
 E1000_DEV_ID_82576_SERDES_QUADE1000_DEV_ID_82576_SERDES_QUAD 0x150D igb_hw.h 　
6315
 E1000_DEV_ID_82575EB_COPPERE1000_DEV_ID_82575EB_COPPER 0x10A7 igb_hw.h 　
6316
 E1000_DEV_ID_82575EB_FIBER_SERDE1000_DEV_ID_82575EB_FIBER_SERD 0x10A9 igb_hw.h 　
6317
 E1000_DEV_ID_82575GB_QUAD_COPPEE1000_DEV_ID_82575GB_QUAD_COPPE 0x10D6 igb_hw.h 　
6318
 E1000_REVISION_0E1000_REVISION_0 0 igb_hw.h 　
6319
 E1000_REVISION_1E1000_REVISION_1 1 igb_hw.h 　
6320
 E1000_REVISION_2E1000_REVISION_2 2 igb_hw.h 　
6321
 E1000_REVISION_3E1000_REVISION_3 3 igb_hw.h 　
6322
 E1000_REVISION_4E1000_REVISION_4 4 igb_hw.h 　
6323
 E1000_FUNC_0E1000_FUNC_0 0 igb_hw.h 　
6324
 E1000_FUNC_1E1000_FUNC_1 1 igb_hw.h 　
6325
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 0 igb_hw.h 　
6326
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 3 igb_hw.h 　
6327
 MAX_PS_BUFFERSMAX_PS_BUFFERS 4 igb_hw.h 　
6328
 E1000_HI_MAX_DATA_LENGTHE1000_HI_MAX_DATA_LENGTH 252 igb_hw.h 　
6329
 E1000_HI_MAX_MNG_DATA_LENGTHE1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 igb_hw.h 　
6330
 E1000_FACTPS_MNGCGE1000_FACTPS_MNGCG 0x20000000 igb_manage.h 　
6331
 E1000_FWSM_MODE_MASKE1000_FWSM_MODE_MASK 0xE igb_manage.h 　
6332
 E1000_FWSM_MODE_SHIFTE1000_FWSM_MODE_SHIFT 1 igb_manage.h 　
6333
 E1000_MNG_IAMT_MODEE1000_MNG_IAMT_MODE 0x3 igb_manage.h 　
6334
 E1000_MNG_DHCP_COOKIE_LENGTHE1000_MNG_DHCP_COOKIE_LENGTH 0x10 igb_manage.h 　
6335
 E1000_MNG_DHCP_COOKIE_OFFSETE1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 igb_manage.h 　
6336
 E1000_MNG_DHCP_COMMAND_TIMEOUTE1000_MNG_DHCP_COMMAND_TIMEOUT 10 igb_manage.h 　
6337
 E1000_MNG_DHCP_TX_PAYLOAD_CMDE1000_MNG_DHCP_TX_PAYLOAD_CMD 64 igb_manage.h 　
6338
 E1000_MNG_DHCP_COOKIE_STATUS_PAE1000_MNG_DHCP_COOKIE_STATUS_PA 0x1 igb_manage.h 　
6339
 E1000_MNG_DHCP_COOKIE_STATUS_VLE1000_MNG_DHCP_COOKIE_STATUS_VL 0x2 igb_manage.h 　
6340
 E1000_VFTA_ENTRY_SHIFTE1000_VFTA_ENTRY_SHIFT 5 igb_manage.h 　
6341
 E1000_VFTA_ENTRY_MASKE1000_VFTA_ENTRY_MASK 0x7F igb_manage.h 　
6342
 E1000_VFTA_ENTRY_BIT_SHIFT_MASKE1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F igb_manage.h 　
6343
 E1000_HI_MAX_BLOCK_BYTE_LENGTHE1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 igb_manage.h Num of bytes in range
6344
 E1000_HI_MAX_BLOCK_DWORD_LENGTHE1000_HI_MAX_BLOCK_DWORD_LENGTH 448 igb_manage.h Num of dwords in range
6345
 E1000_HI_COMMAND_TIMEOUTE1000_HI_COMMAND_TIMEOUT 500 igb_manage.h Process HI command limit
6346
 E1000_HICR_ENE1000_HICR_EN 0x01 igb_manage.h Enable bit - RO
6347
 E1000_HICR_CE1000_HICR_C 0x02 igb_manage.h 　
6348
 E1000_HICR_SVE1000_HICR_SV 0x04 igb_manage.h Status Validity
6349
 E1000_HICR_FW_RESET_ENABLEE1000_HICR_FW_RESET_ENABLE 0x40 igb_manage.h 　
6350
 E1000_HICR_FW_RESETE1000_HICR_FW_RESET 0x80 igb_manage.h 　
6351
 E1000_IAMT_SIGNATUREE1000_IAMT_SIGNATURE 0x544D4149 igb_manage.h 　
6352
 E1000_STM_OPCODEE1000_STM_OPCODE 0xDB00 igb_nvm.h 　
6353
 u8u8 unsigned char igb_osdep.h 　
6354
 boolbool boolean_t igb_osdep.h 　
6355
 dma_addr_tdma_addr_t unsigned long igb_osdep.h 　
6356
 __le16__le16 uint16_t igb_osdep.h 　
6357
 __le32__le32 uint32_t igb_osdep.h 　
6358
 __le64__le64 uint64_t igb_osdep.h 　
6359
 ETH_FCS_LENETH_FCS_LEN 4 igb_osdep.h 　
6360
 TRUETRUE 1 igb_osdep.h 　
6361
 FALSEFALSE 0 igb_osdep.h 　
6362
 PCI_COMMAND_REGISTERPCI_COMMAND_REGISTER PCI_COMMAND igb_osdep.h 　
6363
 CMD_MEM_WRT_INVALIDATECMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE igb_osdep.h 　
6364
 ETH_ADDR_LENETH_ADDR_LEN ETH_ALEN igb_osdep.h 　
6365
 E1000_BIG_ENDIANE1000_BIG_ENDIAN __BIG_ENDIAN igb_osdep.h 　
6366
 DEBUGOUT2DEBUGOUT2 DEBUGOUT1 igb_osdep.h 　
6367
 DEBUGOUT3DEBUGOUT3 DEBUGOUT2 igb_osdep.h 　
6368
 DEBUGOUT7DEBUGOUT7 DEBUGOUT3 igb_osdep.h 　
6369
 E1000_READ_REG_ARRAY_DWORDE1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY igb_osdep.h 　
6370
 E1000_WRITE_REG_ARRAY_DWORDE1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY igb_osdep.h 　
6371
 E1000_MAX_PHY_ADDRE1000_MAX_PHY_ADDR 4 igb_phy.h 　
6372
 IGP01E1000_PHY_PORT_CONFIGIGP01E1000_PHY_PORT_CONFIG 0x10 igb_phy.h Port Config
6373
 IGP01E1000_PHY_PORT_STATUSIGP01E1000_PHY_PORT_STATUS 0x11 igb_phy.h Status
6374
 IGP01E1000_PHY_PORT_CTRLIGP01E1000_PHY_PORT_CTRL 0x12 igb_phy.h Control
6375
 IGP01E1000_PHY_LINK_HEALTHIGP01E1000_PHY_LINK_HEALTH 0x13 igb_phy.h PHY Link Health
6376
 IGP01E1000_GMII_FIFOIGP01E1000_GMII_FIFO 0x14 igb_phy.h GMII FIFO
6377
 IGP01E1000_PHY_CHANNEL_QUALITYIGP01E1000_PHY_CHANNEL_QUALITY 0x15 igb_phy.h PHY Channel Quality
6378
 IGP02E1000_PHY_POWER_MGMTIGP02E1000_PHY_POWER_MGMT 0x19 igb_phy.h Power Management
6379
 IGP01E1000_PHY_PAGE_SELECTIGP01E1000_PHY_PAGE_SELECT 0x1F igb_phy.h Page Select
6380
 BM_PHY_PAGE_SELECTBM_PHY_PAGE_SELECT 22 igb_phy.h Page Select for BM
6381
 IGP_PAGE_SHIFTIGP_PAGE_SHIFT 5 igb_phy.h 　
6382
 PHY_REG_MASKPHY_REG_MASK 0x1F igb_phy.h 　
6383
 IGP01E1000_PHY_PCS_INIT_REGIGP01E1000_PHY_PCS_INIT_REG 0x00B4 igb_phy.h 　
6384
 IGP01E1000_PHY_POLARITY_MASKIGP01E1000_PHY_POLARITY_MASK 0x0078 igb_phy.h 　
6385
 IGP01E1000_PSCR_AUTO_MDIXIGP01E1000_PSCR_AUTO_MDIX 0x1000 igb_phy.h 　
6386
 IGP01E1000_PSCR_FORCE_MDI_MDIXIGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 igb_phy.h 0=MDI, 1=MDIX
6387
 IGP01E1000_PSCFR_SMART_SPEEDIGP01E1000_PSCFR_SMART_SPEED 0x0080 igb_phy.h 　
6388
 IGP01E1000_GMII_FLEX_SPDIGP01E1000_GMII_FLEX_SPD 0x0010 igb_phy.h 　
6389
 IGP01E1000_GMII_SPDIGP01E1000_GMII_SPD 0x0020 igb_phy.h Enable SPD
6390
 IGP02E1000_PM_SPDIGP02E1000_PM_SPD 0x0001 igb_phy.h Smart Power Down
6391
 IGP02E1000_PM_D0_LPLUIGP02E1000_PM_D0_LPLU 0x0002 igb_phy.h For D0a states
6392
 IGP02E1000_PM_D3_LPLUIGP02E1000_PM_D3_LPLU 0x0004 igb_phy.h For all other states
6393
 IGP01E1000_PLHR_SS_DOWNGRADEIGP01E1000_PLHR_SS_DOWNGRADE 0x8000 igb_phy.h 　
6394
 IGP01E1000_PSSR_POLARITY_REVERSIGP01E1000_PSSR_POLARITY_REVERS 0x0002 igb_phy.h 　
6395
 IGP01E1000_PSSR_MDIXIGP01E1000_PSSR_MDIX 0x0800 igb_phy.h 　
6396
 IGP01E1000_PSSR_SPEED_MASKIGP01E1000_PSSR_SPEED_MASK 0xC000 igb_phy.h 　
6397
 IGP01E1000_PSSR_SPEED_1000MBPSIGP01E1000_PSSR_SPEED_1000MBPS 0xC000 igb_phy.h 　
6398
 IGP02E1000_PHY_CHANNEL_NUMIGP02E1000_PHY_CHANNEL_NUM 4 igb_phy.h 　
6399
 IGP02E1000_PHY_AGC_AIGP02E1000_PHY_AGC_A 0x11B1 igb_phy.h 　
6400
 IGP02E1000_PHY_AGC_BIGP02E1000_PHY_AGC_B 0x12B1 igb_phy.h 　
6401
 IGP02E1000_PHY_AGC_CIGP02E1000_PHY_AGC_C 0x14B1 igb_phy.h 　
6402
 IGP02E1000_PHY_AGC_DIGP02E1000_PHY_AGC_D 0x18B1 igb_phy.h 　
6403
 IGP02E1000_AGC_LENGTH_SHIFTIGP02E1000_AGC_LENGTH_SHIFT 9 igb_phy.h Course - 15:13, Fine - 12:9
6404
 IGP02E1000_AGC_LENGTH_MASKIGP02E1000_AGC_LENGTH_MASK 0x7F igb_phy.h 　
6405
 IGP02E1000_AGC_RANGEIGP02E1000_AGC_RANGE 15 igb_phy.h 　
6406
 IGP03E1000_PHY_MISC_CTRLIGP03E1000_PHY_MISC_CTRL 0x1B igb_phy.h 　
6407
 IGP03E1000_PHY_MISC_DUPLEX_MANUIGP03E1000_PHY_MISC_DUPLEX_MANU 0x1000 igb_phy.h Manually Set Duplex
6408
 E1000_CABLE_LENGTH_UNDEFINEDE1000_CABLE_LENGTH_UNDEFINED 0xFF igb_phy.h 　
6409
 E1000_KMRNCTRLSTA_OFFSETE1000_KMRNCTRLSTA_OFFSET 0x001F0000 igb_phy.h 　
6410
 E1000_KMRNCTRLSTA_OFFSET_SHIFTE1000_KMRNCTRLSTA_OFFSET_SHIFT 16 igb_phy.h 　
6411
 E1000_KMRNCTRLSTA_RENE1000_KMRNCTRLSTA_REN 0x00200000 igb_phy.h 　
6412
 E1000_KMRNCTRLSTA_DIAG_OFFSETE1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 igb_phy.h Kumeran Diagnostic
6413
 E1000_KMRNCTRLSTA_TIMEOUTSE1000_KMRNCTRLSTA_TIMEOUTS 0x4 igb_phy.h Kumeran Timeouts
6414
 E1000_KMRNCTRLSTA_INBAND_PARAME1000_KMRNCTRLSTA_INBAND_PARAM 0x9 igb_phy.h Kumeran InBand Parameters
6415
 E1000_KMRNCTRLSTA_DIAG_NELPBKE1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 igb_phy.h Nearend Loopback mode
6416
 IFE_PHY_EXTENDED_STATUS_CONTROLIFE_PHY_EXTENDED_STATUS_CONTROL 0x10 igb_phy.h 　
6417
 IFE_PHY_SPECIAL_CONTROLIFE_PHY_SPECIAL_CONTROL 0x11 igb_phy.h 100BaseTx PHY Special Control
6418
 IFE_PHY_SPECIAL_CONTROL_LEDIFE_PHY_SPECIAL_CONTROL_LED 0x1B igb_phy.h PHY Special and LED Control
6419
 IFE_PHY_MDIX_CONTROLIFE_PHY_MDIX_CONTROL 0x1C igb_phy.h MDI/MDI-X Control
6420
 IFE_PESC_POLARITY_REVERSEDIFE_PESC_POLARITY_REVERSED 0x0100 igb_phy.h 　
6421
 IFE_PSC_AUTO_POLARITY_DISABLEIFE_PSC_AUTO_POLARITY_DISABLE 0x0010 igb_phy.h 　
6422
 IFE_PSC_FORCE_POLARITYIFE_PSC_FORCE_POLARITY 0x0020 igb_phy.h 　
6423
 IFE_PSC_DISABLE_DYNAMIC_POWER_DIFE_PSC_DISABLE_DYNAMIC_POWER_D 0x0100 igb_phy.h 　
6424
 IFE_PSCL_PROBE_MODEIFE_PSCL_PROBE_MODE 0x0020 igb_phy.h 　
6425
 IFE_PSCL_PROBE_LEDS_OFFIFE_PSCL_PROBE_LEDS_OFF 0x0006 igb_phy.h Force LEDs 0 and 2 off
6426
 IFE_PSCL_PROBE_LEDS_ONIFE_PSCL_PROBE_LEDS_ON 0x0007 igb_phy.h Force LEDs 0 and 2 on
6427
 IFE_PMC_MDIX_STATUSIFE_PMC_MDIX_STATUS 0x0020 igb_phy.h 1=MDI-X, 0=MDI
6428
 IFE_PMC_FORCE_MDIXIFE_PMC_FORCE_MDIX 0x0040 igb_phy.h 1=force MDI-X, 0=force MDI
6429
 IFE_PMC_AUTO_MDIXIFE_PMC_AUTO_MDIX 0x0080 igb_phy.h 1=enable auto MDI/MDI-X, 0=disable
6430
 E1000_CTRLE1000_CTRL 0x00000 igb_regs.h Device Control - RW
6431
 E1000_CTRL_DUPE1000_CTRL_DUP 0x00004 igb_regs.h Device Control Duplicate (Shadow) - RW
6432
 E1000_STATUSE1000_STATUS 0x00008 igb_regs.h Device Status - RO
6433
 E1000_EECDE1000_EECD 0x00010 igb_regs.h EEPROM/Flash Control - RW
6434
 E1000_EERDE1000_EERD 0x00014 igb_regs.h EEPROM Read - RW
6435
 E1000_CTRL_EXTE1000_CTRL_EXT 0x00018 igb_regs.h Extended Device Control - RW
6436
 E1000_FLAE1000_FLA 0x0001C igb_regs.h Flash Access - RW
6437
 E1000_MDICE1000_MDIC 0x00020 igb_regs.h MDI Control - RW
6438
 E1000_SCTLE1000_SCTL 0x00024 igb_regs.h SerDes Control - RW
6439
 E1000_FCALE1000_FCAL 0x00028 igb_regs.h Flow Control Address Low - RW
6440
 E1000_FCAHE1000_FCAH 0x0002C igb_regs.h Flow Control Address High -RW
6441
 E1000_FEXTE1000_FEXT 0x0002C igb_regs.h Future Extended - RW
6442
 E1000_FEXTNVME1000_FEXTNVM 0x00028 igb_regs.h Future Extended NVM - RW
6443
 E1000_FCTE1000_FCT 0x00030 igb_regs.h Flow Control Type - RW
6444
 E1000_CONNSWE1000_CONNSW 0x00034 igb_regs.h Copper/Fiber switch control - RW
6445
 E1000_VETE1000_VET 0x00038 igb_regs.h VLAN Ether Type - RW
6446
 E1000_ICRE1000_ICR 0x000C0 igb_regs.h Interrupt Cause Read - R/clr
6447
 E1000_ITRE1000_ITR 0x000C4 igb_regs.h Interrupt Throttling Rate - RW
6448
 E1000_ICSE1000_ICS 0x000C8 igb_regs.h Interrupt Cause Set - WO
6449
 E1000_IMSE1000_IMS 0x000D0 igb_regs.h Interrupt Mask Set - RW
6450
 E1000_IMCE1000_IMC 0x000D8 igb_regs.h Interrupt Mask Clear - WO
6451
 E1000_IAME1000_IAM 0x000E0 igb_regs.h Interrupt Acknowledge Auto Mask
6452
 E1000_RCTLE1000_RCTL 0x00100 igb_regs.h Rx Control - RW
6453
 E1000_FCTTVE1000_FCTTV 0x00170 igb_regs.h Flow Control Transmit Timer Value - RW
6454
 E1000_TXCWE1000_TXCW 0x00178 igb_regs.h Tx Configuration Word - RW
6455
 E1000_RXCWE1000_RXCW 0x00180 igb_regs.h Rx Configuration Word - RO
6456
 E1000_EICRE1000_EICR 0x01580 igb_regs.h Ext. Interrupt Cause Read - R/clr
6457
 E1000_EICSE1000_EICS 0x01520 igb_regs.h Ext. Interrupt Cause Set - W0
6458
 E1000_EIMSE1000_EIMS 0x01524 igb_regs.h Ext. Interrupt Mask Set/Read - RW
6459
 E1000_EIMCE1000_EIMC 0x01528 igb_regs.h Ext. Interrupt Mask Clear - WO
6460
 E1000_EIACE1000_EIAC 0x0152C igb_regs.h Ext. Interrupt Auto Clear - RW
6461
 E1000_EIAME1000_EIAM 0x01530 igb_regs.h Ext. Interrupt Ack Auto Clear Mask - RW
6462
 E1000_GPIEE1000_GPIE 0x01514 igb_regs.h General Purpose Interrupt Enable - RW
6463
 E1000_IVAR0E1000_IVAR0 0x01700 igb_regs.h Interrupt Vector Allocation (array) - RW
6464
 E1000_IVAR_MISCE1000_IVAR_MISC 0x01740 igb_regs.h IVAR for "other" causes - RW
6465
 E1000_TCTLE1000_TCTL 0x00400 igb_regs.h Tx Control - RW
6466
 E1000_TCTL_EXTE1000_TCTL_EXT 0x00404 igb_regs.h Extended Tx Control - RW
6467
 E1000_TIPGE1000_TIPG 0x00410 igb_regs.h Tx Inter-packet gap -RW
6468
 E1000_TBTE1000_TBT 0x00448 igb_regs.h Tx Burst Timer - RW
6469
 E1000_AITE1000_AIT 0x00458 igb_regs.h Adaptive Interframe Spacing Throttle - RW
6470
 E1000_LEDCTLE1000_LEDCTL 0x00E00 igb_regs.h LED Control - RW
6471
 E1000_EXTCNF_CTRLE1000_EXTCNF_CTRL 0x00F00 igb_regs.h Extended Configuration Control
6472
 E1000_EXTCNF_SIZEE1000_EXTCNF_SIZE 0x00F08 igb_regs.h Extended Configuration Size
6473
 E1000_PHY_CTRLE1000_PHY_CTRL 0x00F10 igb_regs.h PHY Control Register in CSR
6474
 E1000_PBAE1000_PBA 0x01000 igb_regs.h Packet Buffer Allocation - RW
6475
 E1000_PBSE1000_PBS 0x01008 igb_regs.h Packet Buffer Size
6476
 E1000_EEMNGCTLE1000_EEMNGCTL 0x01010 igb_regs.h MNG EEprom Control
6477
 E1000_EEARBCE1000_EEARBC 0x01024 igb_regs.h EEPROM Auto Read Bus Control
6478
 E1000_FLASHTE1000_FLASHT 0x01028 igb_regs.h FLASH Timer Register
6479
 E1000_EEWRE1000_EEWR 0x0102C igb_regs.h EEPROM Write Register - RW
6480
 E1000_FLSWCTLE1000_FLSWCTL 0x01030 igb_regs.h FLASH control register
6481
 E1000_FLSWDATAE1000_FLSWDATA 0x01034 igb_regs.h FLASH data register
6482
 E1000_FLSWCNTE1000_FLSWCNT 0x01038 igb_regs.h FLASH Access Counter
6483
 E1000_FLOPE1000_FLOP 0x0103C igb_regs.h FLASH Opcode Register
6484
 E1000_I2CCMDE1000_I2CCMD 0x01028 igb_regs.h SFPI2C Command Register - RW
6485
 E1000_I2CPARAMSE1000_I2CPARAMS 0x0102C igb_regs.h SFPI2C Parameters Register - RW
6486
 E1000_WDSTPE1000_WDSTP 0x01040 igb_regs.h Watchdog Setup - RW
6487
 E1000_SWDSTSE1000_SWDSTS 0x01044 igb_regs.h SW Device Status - RW
6488
 E1000_FRTIMERE1000_FRTIMER 0x01048 igb_regs.h Free Running Timer - RW
6489
 E1000_TCPTIMERE1000_TCPTIMER 0x0104C igb_regs.h TCP Timer - RW
6490
 E1000_VPDDIAGE1000_VPDDIAG 0x01060 igb_regs.h VPD Diagnostic - RO
6491
 E1000_ICR_V2E1000_ICR_V2 0x01500 igb_regs.h Interrupt Cause - new location - RC
6492
 E1000_ICS_V2E1000_ICS_V2 0x01504 igb_regs.h Interrupt Cause Set - new location - WO
6493
 E1000_IMS_V2E1000_IMS_V2 0x01508 igb_regs.h Interrupt Mask Set/Read - new location - RW
6494
 E1000_IMC_V2E1000_IMC_V2 0x0150C igb_regs.h Interrupt Mask Clear - new location - WO
6495
 E1000_IAM_V2E1000_IAM_V2 0x01510 igb_regs.h Interrupt Ack Auto Mask - new location - RW
6496
 E1000_ERTE1000_ERT 0x02008 igb_regs.h Early Rx Threshold - RW
6497
 E1000_FCRTLE1000_FCRTL 0x02160 igb_regs.h Flow Control Receive Threshold Low - RW
6498
 E1000_FCRTHE1000_FCRTH 0x02168 igb_regs.h Flow Control Receive Threshold High - RW
6499
 E1000_PSRCTLE1000_PSRCTL 0x02170 igb_regs.h Packet Split Receive Control - RW
6500
 E1000_PBRTHE1000_PBRTH 0x02458 igb_regs.h PB Rx Arbitration Threshold - RW
6501
 E1000_FCRTVE1000_FCRTV 0x02460 igb_regs.h Flow Control Refresh Timer Value - RW
6502
 E1000_RDPUMBE1000_RDPUMB 0x025CC igb_regs.h DMA Rx Descriptor uC Mailbox - RW
6503
 E1000_RDPUADE1000_RDPUAD 0x025D0 igb_regs.h DMA Rx Descriptor uC Addr Command - RW
6504
 E1000_RDPUWDE1000_RDPUWD 0x025D4 igb_regs.h DMA Rx Descriptor uC Data Write - RW
6505
 E1000_RDPURDE1000_RDPURD 0x025D8 igb_regs.h DMA Rx Descriptor uC Data Read - RW
6506
 E1000_RDPUCTLE1000_RDPUCTL 0x025DC igb_regs.h DMA Rx Descriptor uC Control - RW
6507
 E1000_PBDIAGE1000_PBDIAG 0x02458 igb_regs.h Packet Buffer Diagnostic - RW
6508
 E1000_RXPBSE1000_RXPBS 0x02404 igb_regs.h Rx Packet Buffer Size - RW
6509
 E1000_RDTRE1000_RDTR 0x02820 igb_regs.h Rx Delay Timer - RW
6510
 E1000_RADVE1000_RADV 0x0282C igb_regs.h Rx Interrupt Absolute Delay Timer - RW
6511
 E1000_RSRPDE1000_RSRPD 0x02C00 igb_regs.h Rx Small Packet Detect - RW
6512
 E1000_RAIDE1000_RAID 0x02C08 igb_regs.h Receive Ack Interrupt Delay - RW
6513
 E1000_TXDMACE1000_TXDMAC 0x03000 igb_regs.h Tx DMA Control - RW
6514
 E1000_KABGTXDE1000_KABGTXD 0x03004 igb_regs.h AFE Band Gap Transmit Ref Data
6515
 E1000_PBSLACE1000_PBSLAC 0x03100 igb_regs.h Packet Buffer Slave Access Control
6516
 E1000_TXPBSE1000_TXPBS 0x03404 igb_regs.h Tx Packet Buffer Size - RW
6517
 E1000_TDFHE1000_TDFH 0x03410 igb_regs.h Tx Data FIFO Head - RW
6518
 E1000_TDFTE1000_TDFT 0x03418 igb_regs.h Tx Data FIFO Tail - RW
6519
 E1000_TDFHSE1000_TDFHS 0x03420 igb_regs.h Tx Data FIFO Head Saved - RW
6520
 E1000_TDFTSE1000_TDFTS 0x03428 igb_regs.h Tx Data FIFO Tail Saved - RW
6521
 E1000_TDFPCE1000_TDFPC 0x03430 igb_regs.h Tx Data FIFO Packet Count - RW
6522
 E1000_TDPUMBE1000_TDPUMB 0x0357C igb_regs.h DMA Tx Descriptor uC Mail Box - RW
6523
 E1000_TDPUADE1000_TDPUAD 0x03580 igb_regs.h DMA Tx Descriptor uC Addr Command - RW
6524
 E1000_TDPUWDE1000_TDPUWD 0x03584 igb_regs.h DMA Tx Descriptor uC Data Write - RW
6525
 E1000_TDPURDE1000_TDPURD 0x03588 igb_regs.h DMA Tx Descriptor uC Data Read - RW
6526
 E1000_TDPUCTLE1000_TDPUCTL 0x0358C igb_regs.h DMA Tx Descriptor uC Control - RW
6527
 E1000_DTXCTLE1000_DTXCTL 0x03590 igb_regs.h DMA Tx Control - RW
6528
 E1000_DTXTCPFLGLE1000_DTXTCPFLGL 0x0359C igb_regs.h DMA Tx Control flag low - RW
6529
 E1000_DTXTCPFLGHE1000_DTXTCPFLGH 0x035A0 igb_regs.h DMA Tx Control flag high - RW
6530
 E1000_DTXMXSZRQE1000_DTXMXSZRQ 0x03540 igb_regs.h DMA Tx Max Total Allow Size Requests - RW
6531
 E1000_TIDVE1000_TIDV 0x03820 igb_regs.h Tx Interrupt Delay Value - RW
6532
 E1000_TADVE1000_TADV 0x0382C igb_regs.h Tx Interrupt Absolute Delay Val - RW
6533
 E1000_TSPMTE1000_TSPMT 0x03830 igb_regs.h TCP Segmentation PAD & Min Threshold - RW
6534
 E1000_CRCERRSE1000_CRCERRS 0x04000 igb_regs.h CRC Error Count - R/clr
6535
 E1000_ALGNERRCE1000_ALGNERRC 0x04004 igb_regs.h Alignment Error Count - R/clr
6536
 E1000_SYMERRSE1000_SYMERRS 0x04008 igb_regs.h Symbol Error Count - R/clr
6537
 E1000_RXERRCE1000_RXERRC 0x0400C igb_regs.h Receive Error Count - R/clr
6538
 E1000_MPCE1000_MPC 0x04010 igb_regs.h Missed Packet Count - R/clr
6539
 E1000_SCCE1000_SCC 0x04014 igb_regs.h Single Collision Count - R/clr
6540
 E1000_ECOLE1000_ECOL 0x04018 igb_regs.h Excessive Collision Count - R/clr
6541
 E1000_MCCE1000_MCC 0x0401C igb_regs.h Multiple Collision Count - R/clr
6542
 E1000_LATECOLE1000_LATECOL 0x04020 igb_regs.h Late Collision Count - R/clr
6543
 E1000_COLCE1000_COLC 0x04028 igb_regs.h Collision Count - R/clr
6544
 E1000_DCE1000_DC 0x04030 igb_regs.h Defer Count - R/clr
6545
 E1000_TNCRSE1000_TNCRS 0x04034 igb_regs.h Tx-No CRS - R/clr
6546
 E1000_SECE1000_SEC 0x04038 igb_regs.h Sequence Error Count - R/clr
6547
 E1000_CEXTERRE1000_CEXTERR 0x0403C igb_regs.h Carrier Extension Error Count - R/clr
6548
 E1000_RLECE1000_RLEC 0x04040 igb_regs.h Receive Length Error Count - R/clr
6549
 E1000_XONRXCE1000_XONRXC 0x04048 igb_regs.h XON Rx Count - R/clr
6550
 E1000_XONTXCE1000_XONTXC 0x0404C igb_regs.h XON Tx Count - R/clr
6551
 E1000_XOFFRXCE1000_XOFFRXC 0x04050 igb_regs.h XOFF Rx Count - R/clr
6552
 E1000_XOFFTXCE1000_XOFFTXC 0x04054 igb_regs.h XOFF Tx Count - R/clr
6553
 E1000_FCRUCE1000_FCRUC 0x04058 igb_regs.h Flow Control Rx Unsupported Count- R/clr
6554
 E1000_PRC64E1000_PRC64 0x0405C igb_regs.h Packets Rx (64 bytes) - R/clr
6555
 E1000_PRC127E1000_PRC127 0x04060 igb_regs.h Packets Rx (65-127 bytes) - R/clr
6556
 E1000_PRC255E1000_PRC255 0x04064 igb_regs.h Packets Rx (128-255 bytes) - R/clr
6557
 E1000_PRC511E1000_PRC511 0x04068 igb_regs.h Packets Rx (255-511 bytes) - R/clr
6558
 E1000_PRC1023E1000_PRC1023 0x0406C igb_regs.h Packets Rx (512-1023 bytes) - R/clr
6559
 E1000_PRC1522E1000_PRC1522 0x04070 igb_regs.h Packets Rx (1024-1522 bytes) - R/clr
6560
 E1000_GPRCE1000_GPRC 0x04074 igb_regs.h Good Packets Rx Count - R/clr
6561
 E1000_BPRCE1000_BPRC 0x04078 igb_regs.h Broadcast Packets Rx Count - R/clr
6562
 E1000_MPRCE1000_MPRC 0x0407C igb_regs.h Multicast Packets Rx Count - R/clr
6563
 E1000_GPTCE1000_GPTC 0x04080 igb_regs.h Good Packets Tx Count - R/clr
6564
 E1000_GORCLE1000_GORCL 0x04088 igb_regs.h Good Octets Rx Count Low - R/clr
6565
 E1000_GORCHE1000_GORCH 0x0408C igb_regs.h Good Octets Rx Count High - R/clr
6566
 E1000_GOTCLE1000_GOTCL 0x04090 igb_regs.h Good Octets Tx Count Low - R/clr
6567
 E1000_GOTCHE1000_GOTCH 0x04094 igb_regs.h Good Octets Tx Count High - R/clr
6568
 E1000_RNBCE1000_RNBC 0x040A0 igb_regs.h Rx No Buffers Count - R/clr
6569
 E1000_RUCE1000_RUC 0x040A4 igb_regs.h Rx Undersize Count - R/clr
6570
 E1000_RFCE1000_RFC 0x040A8 igb_regs.h Rx Fragment Count - R/clr
6571
 E1000_ROCE1000_ROC 0x040AC igb_regs.h Rx Oversize Count - R/clr
6572
 E1000_RJCE1000_RJC 0x040B0 igb_regs.h Rx Jabber Count - R/clr
6573
 E1000_MGTPRCE1000_MGTPRC 0x040B4 igb_regs.h Management Packets Rx Count - R/clr
6574
 E1000_MGTPDCE1000_MGTPDC 0x040B8 igb_regs.h Management Packets Dropped Count - R/clr
6575
 E1000_MGTPTCE1000_MGTPTC 0x040BC igb_regs.h Management Packets Tx Count - R/clr
6576
 E1000_TORLE1000_TORL 0x040C0 igb_regs.h Total Octets Rx Low - R/clr
6577
 E1000_TORHE1000_TORH 0x040C4 igb_regs.h Total Octets Rx High - R/clr
6578
 E1000_TOTLE1000_TOTL 0x040C8 igb_regs.h Total Octets Tx Low - R/clr
6579
 E1000_TOTHE1000_TOTH 0x040CC igb_regs.h Total Octets Tx High - R/clr
6580
 E1000_TPRE1000_TPR 0x040D0 igb_regs.h Total Packets Rx - R/clr
6581
 E1000_TPTE1000_TPT 0x040D4 igb_regs.h Total Packets Tx - R/clr
6582
 E1000_PTC64E1000_PTC64 0x040D8 igb_regs.h Packets Tx (64 bytes) - R/clr
6583
 E1000_PTC127E1000_PTC127 0x040DC igb_regs.h Packets Tx (65-127 bytes) - R/clr
6584
 E1000_PTC255E1000_PTC255 0x040E0 igb_regs.h Packets Tx (128-255 bytes) - R/clr
6585
 E1000_PTC511E1000_PTC511 0x040E4 igb_regs.h Packets Tx (256-511 bytes) - R/clr
6586
 E1000_PTC1023E1000_PTC1023 0x040E8 igb_regs.h Packets Tx (512-1023 bytes) - R/clr
6587
 E1000_PTC1522E1000_PTC1522 0x040EC igb_regs.h Packets Tx (1024-1522 Bytes) - R/clr
6588
 E1000_MPTCE1000_MPTC 0x040F0 igb_regs.h Multicast Packets Tx Count - R/clr
6589
 E1000_BPTCE1000_BPTC 0x040F4 igb_regs.h Broadcast Packets Tx Count - R/clr
6590
 E1000_TSCTCE1000_TSCTC 0x040F8 igb_regs.h TCP Segmentation Context Tx - R/clr
6591
 E1000_TSCTFCE1000_TSCTFC 0x040FC igb_regs.h TCP Segmentation Context Tx Fail - R/clr
6592
 E1000_IACE1000_IAC 0x04100 igb_regs.h Interrupt Assertion Count
6593
 E1000_ICRXPTCE1000_ICRXPTC 0x04104 igb_regs.h Interrupt Cause Rx Pkt Timer Expire Count
6594
 E1000_ICRXATCE1000_ICRXATC 0x04108 igb_regs.h Interrupt Cause Rx Abs Timer Expire Count
6595
 E1000_ICTXPTCE1000_ICTXPTC 0x0410C igb_regs.h Interrupt Cause Tx Pkt Timer Expire Count
6596
 E1000_ICTXATCE1000_ICTXATC 0x04110 igb_regs.h Interrupt Cause Tx Abs Timer Expire Count
6597
 E1000_ICTXQECE1000_ICTXQEC 0x04118 igb_regs.h Interrupt Cause Tx Queue Empty Count
6598
 E1000_ICTXQMTCE1000_ICTXQMTC 0x0411C igb_regs.h Interrupt Cause Tx Queue Min Thresh Count
6599
 E1000_ICRXDMTCE1000_ICRXDMTC 0x04120 igb_regs.h Interrupt Cause Rx Desc Min Thresh Count
6600
 E1000_ICRXOCE1000_ICRXOC 0x04124 igb_regs.h Interrupt Cause Receiver Overrun Count
6601
 E1000_LSECTXUTE1000_LSECTXUT 0x04300 igb_regs.h LinkSec Tx Untagged Packet Count - OutPktsUntagged
6602
 E1000_LSECTXPKTEE1000_LSECTXPKTE 0x04304 igb_regs.h LinkSec Encrypted Tx Packets Count - OutPktsEncrypted
6603
 E1000_LSECTXPKTPE1000_LSECTXPKTP 0x04308 igb_regs.h LinkSec Protected Tx Packet Count - OutPktsProtected
6604
 E1000_LSECTXOCTEE1000_LSECTXOCTE 0x0430C igb_regs.h LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted
6605
 E1000_LSECTXOCTPE1000_LSECTXOCTP 0x04310 igb_regs.h LinkSec Protected Tx Octets Count - OutOctetsProtected
6606
 E1000_LSECRXUTE1000_LSECRXUT 0x04314 igb_regs.h LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag
6607
 E1000_LSECRXOCTDE1000_LSECRXOCTD 0x0431C igb_regs.h LinkSec Rx Octets Decrypted Count - InOctetsDecrypted
6608
 E1000_LSECRXOCTVE1000_LSECRXOCTV 0x04320 igb_regs.h LinkSec Rx Octets Validated - InOctetsValidated
6609
 E1000_LSECRXBADE1000_LSECRXBAD 0x04324 igb_regs.h LinkSec Rx Bad Tag - InPktsBadTag
6610
 E1000_LSECRXNOSCIE1000_LSECRXNOSCI 0x04328 igb_regs.h LinkSec Rx Packet No SCI Count - InPktsNoSci
6611
 E1000_LSECRXUNSCIE1000_LSECRXUNSCI 0x0432C igb_regs.h LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci
6612
 E1000_LSECRXUNCHE1000_LSECRXUNCH 0x04330 igb_regs.h LinkSec Rx Unchecked Packets Count - InPktsUnchecked
6613
 E1000_LSECRXDELAYE1000_LSECRXDELAY 0x04340 igb_regs.h LinkSec Rx Delayed Packet Count - InPktsDelayed
6614
 E1000_LSECRXLATEE1000_LSECRXLATE 0x04350 igb_regs.h LinkSec Rx Late Packets Count - InPktsLate
6615
 E1000_LSECRXUNSAE1000_LSECRXUNSA 0x043C0 igb_regs.h LinkSec Rx Unused SA Count - InPktsUnusedSa
6616
 E1000_LSECRXNUSAE1000_LSECRXNUSA 0x043D0 igb_regs.h LinkSec Rx Not Using SA Count - InPktsNotUsingSa
6617
 E1000_LSECTXCAPE1000_LSECTXCAP 0x0B000 igb_regs.h LinkSec Tx Capabilities Register - RO
6618
 E1000_LSECRXCAPE1000_LSECRXCAP 0x0B300 igb_regs.h LinkSec Rx Capabilities Register - RO
6619
 E1000_LSECTXCTRLE1000_LSECTXCTRL 0x0B004 igb_regs.h LinkSec Tx Control - RW
6620
 E1000_LSECRXCTRLE1000_LSECRXCTRL 0x0B304 igb_regs.h LinkSec Rx Control - RW
6621
 E1000_LSECTXSCLE1000_LSECTXSCL 0x0B008 igb_regs.h LinkSec Tx SCI Low - RW
6622
 E1000_LSECTXSCHE1000_LSECTXSCH 0x0B00C igb_regs.h LinkSec Tx SCI High - RW
6623
 E1000_LSECTXSAE1000_LSECTXSA 0x0B010 igb_regs.h LinkSec Tx SA0 - RW
6624
 E1000_LSECTXPN0E1000_LSECTXPN0 0x0B018 igb_regs.h LinkSec Tx SA PN 0 - RW
6625
 E1000_LSECTXPN1E1000_LSECTXPN1 0x0B01C igb_regs.h LinkSec Tx SA PN 1 - RW
6626
 E1000_LSECRXSCLE1000_LSECRXSCL 0x0B3D0 igb_regs.h LinkSec Rx SCI Low - RW
6627
 E1000_LSECRXSCHE1000_LSECRXSCH 0x0B3E0 igb_regs.h LinkSec Rx SCI High - RW
6628
 E1000_SSVPCE1000_SSVPC 0x041A0 igb_regs.h Switch Security Violation Packet Count
6629
 E1000_IPSCTRLE1000_IPSCTRL 0xB430 igb_regs.h IpSec Control Register
6630
 E1000_IPSRXCMDE1000_IPSRXCMD 0x0B408 igb_regs.h IPSec Rx Command Register - RW
6631
 E1000_IPSRXIDXE1000_IPSRXIDX 0x0B400 igb_regs.h IPSec Rx Index - RW
6632
 E1000_IPSRXSALTE1000_IPSRXSALT 0x0B404 igb_regs.h IPSec Rx Salt - RW
6633
 E1000_IPSRXSPIE1000_IPSRXSPI 0x0B40C igb_regs.h IPSec Rx SPI - RW
6634
 E1000_IPSTXSALTE1000_IPSTXSALT 0x0B454 igb_regs.h IPSec Tx Salt - RW
6635
 E1000_IPSTXIDXE1000_IPSTXIDX 0x0B450 igb_regs.h IPSec Tx SA IDX - RW
6636
 E1000_PCS_CFG0E1000_PCS_CFG0 0x04200 igb_regs.h PCS Configuration 0 - RW
6637
 E1000_PCS_LCTLE1000_PCS_LCTL 0x04208 igb_regs.h PCS Link Control - RW
6638
 E1000_PCS_LSTATE1000_PCS_LSTAT 0x0420C igb_regs.h PCS Link Status - RO
6639
 E1000_CBTMPCE1000_CBTMPC 0x0402C igb_regs.h Circuit Breaker Tx Packet Count
6640
 E1000_HTDPMCE1000_HTDPMC 0x0403C igb_regs.h Host Transmit Discarded Packets
6641
 E1000_CBRDPCE1000_CBRDPC 0x04044 igb_regs.h Circuit Breaker Rx Dropped Count
6642
 E1000_CBRMPCE1000_CBRMPC 0x040FC igb_regs.h Circuit Breaker Rx Packet Count
6643
 E1000_RPTHCE1000_RPTHC 0x04104 igb_regs.h Rx Packets To Host
6644
 E1000_HGPTCE1000_HGPTC 0x04118 igb_regs.h Host Good Packets Tx Count
6645
 E1000_HTCBDPCE1000_HTCBDPC 0x04124 igb_regs.h Host Tx Circuit Breaker Dropped Count
6646
 E1000_HGORCLE1000_HGORCL 0x04128 igb_regs.h Host Good Octets Received Count Low
6647
 E1000_HGORCHE1000_HGORCH 0x0412C igb_regs.h Host Good Octets Received Count High
6648
 E1000_HGOTCLE1000_HGOTCL 0x04130 igb_regs.h Host Good Octets Transmit Count Low
6649
 E1000_HGOTCHE1000_HGOTCH 0x04134 igb_regs.h Host Good Octets Transmit Count High
6650
 E1000_LENERRSE1000_LENERRS 0x04138 igb_regs.h Length Errors Count
6651
 E1000_SCVPCE1000_SCVPC 0x04228 igb_regs.h SerDes/SGMII Code Violation Pkt Count
6652
 E1000_HRMPCE1000_HRMPC 0x0A018 igb_regs.h Header Redirection Missed Packet Count
6653
 E1000_PCS_ANADVE1000_PCS_ANADV 0x04218 igb_regs.h AN advertisement - RW
6654
 E1000_PCS_LPABE1000_PCS_LPAB 0x0421C igb_regs.h Link Partner Ability - RW
6655
 E1000_PCS_NPTXE1000_PCS_NPTX 0x04220 igb_regs.h AN Next Page Transmit - RW
6656
 E1000_PCS_LPABNPE1000_PCS_LPABNP 0x04224 igb_regs.h Link Partner Ability Next Page - RW
6657
 E1000_1GSTAT_RCVE1000_1GSTAT_RCV 0x04228 igb_regs.h 1GSTAT Code Violation Packet Count - RW
6658
 E1000_RXCSUME1000_RXCSUM 0x05000 igb_regs.h Rx Checksum Control - RW
6659
 E1000_RLPMLE1000_RLPML 0x05004 igb_regs.h Rx Long Packet Max Length
6660
 E1000_RFCTLE1000_RFCTL 0x05008 igb_regs.h Receive Filter Control
6661
 E1000_MTAE1000_MTA 0x05200 igb_regs.h Multicast Table Array - RW Array
6662
 E1000_RAE1000_RA 0x05400 igb_regs.h Receive Address - RW Array
6663
 E1000_RA2E1000_RA2 0x054E0 igb_regs.h 2nd half of receive address array - RW Array
6664
 E1000_VFTAE1000_VFTA 0x05600 igb_regs.h VLAN Filter Table Array - RW Array
6665
 E1000_VT_CTLE1000_VT_CTL 0x0581C igb_regs.h VMDq Control - RW
6666
 E1000_VFQA0E1000_VFQA0 0x0B000 igb_regs.h VLAN Filter Queue Array 0 - RW Array
6667
 E1000_VFQA1E1000_VFQA1 0x0B200 igb_regs.h VLAN Filter Queue Array 1 - RW Array
6668
 E1000_WUCE1000_WUC 0x05800 igb_regs.h Wakeup Control - RW
6669
 E1000_WUFCE1000_WUFC 0x05808 igb_regs.h Wakeup Filter Control - RW
6670
 E1000_WUSE1000_WUS 0x05810 igb_regs.h Wakeup Status - RO
6671
 E1000_MANCE1000_MANC 0x05820 igb_regs.h Management Control - RW
6672
 E1000_IPAVE1000_IPAV 0x05838 igb_regs.h IP Address Valid - RW
6673
 E1000_IP4ATE1000_IP4AT 0x05840 igb_regs.h IPv4 Address Table - RW Array
6674
 E1000_IP6ATE1000_IP6AT 0x05880 igb_regs.h IPv6 Address Table - RW Array
6675
 E1000_WUPLE1000_WUPL 0x05900 igb_regs.h Wakeup Packet Length - RW
6676
 E1000_WUPME1000_WUPM 0x05A00 igb_regs.h Wakeup Packet Memory - RO A
6677
 E1000_PBACLE1000_PBACL 0x05B68 igb_regs.h MSIx PBA Clear - Read/Write 1's to clear
6678
 E1000_FFLTE1000_FFLT 0x05F00 igb_regs.h Flexible Filter Length Table - RW Array
6679
 E1000_HOST_IFE1000_HOST_IF 0x08800 igb_regs.h Host Interface
6680
 E1000_FFMTE1000_FFMT 0x09000 igb_regs.h Flexible Filter Mask Table - RW Array
6681
 E1000_FFVTE1000_FFVT 0x09800 igb_regs.h Flexible Filter Value Table - RW Array
6682
 E1000_KMRNCTRLSTAE1000_KMRNCTRLSTA 0x00034 igb_regs.h MAC-PHY interface - RW
6683
 E1000_MDPHYAE1000_MDPHYA 0x0003C igb_regs.h PHY address - RW
6684
 E1000_MANC2HE1000_MANC2H 0x05860 igb_regs.h Management Control To Host - RW
6685
 E1000_SW_FW_SYNCE1000_SW_FW_SYNC 0x05B5C igb_regs.h Software-Firmware Synchronization - RW
6686
 E1000_CCMCTLE1000_CCMCTL 0x05B48 igb_regs.h CCM Control Register
6687
 E1000_GIOCTLE1000_GIOCTL 0x05B44 igb_regs.h GIO Analog Control Register
6688
 E1000_SCCTLE1000_SCCTL 0x05B4C igb_regs.h PCIc PLL Configuration Register
6689
 E1000_GCRE1000_GCR 0x05B00 igb_regs.h PCI-Ex Control
6690
 E1000_GCR2E1000_GCR2 0x05B64 igb_regs.h PCI-Ex Control #2
6691
 E1000_GSCL_1E1000_GSCL_1 0x05B10 igb_regs.h PCI-Ex Statistic Control #1
6692
 E1000_GSCL_2E1000_GSCL_2 0x05B14 igb_regs.h PCI-Ex Statistic Control #2
6693
 E1000_GSCL_3E1000_GSCL_3 0x05B18 igb_regs.h PCI-Ex Statistic Control #3
6694
 E1000_GSCL_4E1000_GSCL_4 0x05B1C igb_regs.h PCI-Ex Statistic Control #4
6695
 E1000_FACTPSE1000_FACTPS 0x05B30 igb_regs.h Function Active and Power State to MNG
6696
 E1000_SWSME1000_SWSM 0x05B50 igb_regs.h SW Semaphore
6697
 E1000_FWSME1000_FWSM 0x05B54 igb_regs.h FW Semaphore
6698
 E1000_SWSM2E1000_SWSM2 0x05B58 igb_regs.h Driver-only SW semaphore (not used by BOOT agents)
6699
 E1000_DCA_IDE1000_DCA_ID 0x05B70 igb_regs.h DCA Requester ID Information - RO
6700
 E1000_DCA_CTRLE1000_DCA_CTRL 0x05B74 igb_regs.h DCA Control - RW
6701
 E1000_FFLT_DBGE1000_FFLT_DBG 0x05F04 igb_regs.h Debug Register
6702
 E1000_HICRE1000_HICR 0x08F00 igb_regs.h Host Interface Control
6703
 E1000_CPUVECE1000_CPUVEC 0x02C10 igb_regs.h CPU Vector Register - RW
6704
 E1000_MRQCE1000_MRQC 0x05818 igb_regs.h Multiple Receive Control - RW
6705
 E1000_IMIRVPE1000_IMIRVP 0x05AC0 igb_regs.h Immediate Interrupt Rx VLAN Priority - RW
6706
 E1000_MSIXPBAE1000_MSIXPBA 0x0E000 igb_regs.h MSI-X Pending bit array
6707
 E1000_RSSIME1000_RSSIM 0x05864 igb_regs.h RSS Interrupt Mask
6708
 E1000_RSSIRE1000_RSSIR 0x05868 igb_regs.h RSS Interrupt Request
6709
 E1000_SWPBSE1000_SWPBS 0x03004 igb_regs.h Switch Packet Buffer Size - RW
6710
 E1000_MBVFICRE1000_MBVFICR 0x00C80 igb_regs.h Mailbox VF Cause - RWC
6711
 E1000_MBVFIMRE1000_MBVFIMR 0x00C84 igb_regs.h Mailbox VF int Mask - RW
6712
 E1000_VFLREE1000_VFLRE 0x00C88 igb_regs.h VF Register Events - RWC
6713
 E1000_VFREE1000_VFRE 0x00C8C igb_regs.h VF Receive Enables
6714
 E1000_VFTEE1000_VFTE 0x00C90 igb_regs.h VF Transmit Enables
6715
 E1000_QDEE1000_QDE 0x02408 igb_regs.h Queue Drop Enable - RW
6716
 E1000_DTXSWCE1000_DTXSWC 0x03500 igb_regs.h DMA Tx Switch Control - RW
6717
 E1000_RPLOLRE1000_RPLOLR 0x05AF0 igb_regs.h Replication Offload - RW
6718
 E1000_UTAE1000_UTA 0x0A000 igb_regs.h Unicast Table Array - RW
6719
 E1000_IOVTCLE1000_IOVTCL 0x05BBC igb_regs.h IOV Control Register
6720
 E1000_VMRCTLE1000_VMRCTL 0X05D80 igb_regs.h Virtual Mirror Rule Control
6721
 E1000_TSYNCRXCTLE1000_TSYNCRXCTL 0x0B620 igb_regs.h Rx Time Sync Control register - RW
6722
 E1000_TSYNCTXCTLE1000_TSYNCTXCTL 0x0B614 igb_regs.h Tx Time Sync Control register - RW
6723
 E1000_TSYNCRXCFGE1000_TSYNCRXCFG 0x05F50 igb_regs.h Time Sync Rx Configuration - RW
6724
 E1000_RXSTMPLE1000_RXSTMPL 0x0B624 igb_regs.h Rx timestamp Low - RO
6725
 E1000_RXSTMPHE1000_RXSTMPH 0x0B628 igb_regs.h Rx timestamp High - RO
6726
 E1000_RXSATRLE1000_RXSATRL 0x0B62C igb_regs.h Rx timestamp attribute low - RO
6727
 E1000_RXSATRHE1000_RXSATRH 0x0B630 igb_regs.h Rx timestamp attribute high - RO
6728
 E1000_TXSTMPLE1000_TXSTMPL 0x0B618 igb_regs.h Tx timestamp value Low - RO
6729
 E1000_TXSTMPHE1000_TXSTMPH 0x0B61C igb_regs.h Tx timestamp value High - RO
6730
 E1000_SYSTIMLE1000_SYSTIML 0x0B600 igb_regs.h System time register Low - RO
6731
 E1000_SYSTIMHE1000_SYSTIMH 0x0B604 igb_regs.h System time register High - RO
6732
 E1000_TIMINCAE1000_TIMINCA 0x0B608 igb_regs.h Increment attributes register - RW
6733
 E1000_RTTDCSE1000_RTTDCS 0x3600 igb_regs.h Reedtown Tx Desc plane control and status
6734
 E1000_RTTPCSE1000_RTTPCS 0x3474 igb_regs.h Reedtown Tx Packet Plane control and status
6735
 E1000_RTRPCSE1000_RTRPCS 0x2474 igb_regs.h Rx packet plane control and status
6736
 E1000_RTRUP2TCE1000_RTRUP2TC 0x05AC4 igb_regs.h Rx User Priority to Traffic Class
6737
 E1000_RTTUP2TCE1000_RTTUP2TC 0x0418 igb_regs.h Transmit User Priority to Traffic Class
6738
 E1000_RTTDQSELE1000_RTTDQSEL 0x3604 igb_regs.h Tx Desc Plane Queue Select
6739
 E1000_RTTDVMRCE1000_RTTDVMRC 0x3608 igb_regs.h Tx Desc Plane VM Rate-Scheduler Config
6740
 E1000_RTTDVMRSE1000_RTTDVMRS 0x360C igb_regs.h Tx Desc Plane VM Rate-Scheduler Status
6741
 E1000_RTTBCNRCE1000_RTTBCNRC 0x36B0 igb_regs.h Tx BCN Rate-Scheduler Config
6742
 E1000_RTTBCNRSE1000_RTTBCNRS 0x36B4 igb_regs.h Tx BCN Rate-Scheduler Status
6743
 E1000_RTTBCNCRE1000_RTTBCNCR 0xB200 igb_regs.h Tx BCN Control Register
6744
 E1000_RTTBCNTGE1000_RTTBCNTG 0x35A4 igb_regs.h Tx BCN Tagging
6745
 E1000_RTTBCNCPE1000_RTTBCNCP 0xB208 igb_regs.h Tx BCN Congestion point
6746
 E1000_RTRBCNCRE1000_RTRBCNCR 0xB20C igb_regs.h Rx BCN Control Register
6747
 E1000_RTTBCNRDE1000_RTTBCNRD 0x36B8 igb_regs.h Tx BCN Rate Drift
6748
 E1000_PFCTOPE1000_PFCTOP 0x1080 igb_regs.h Priority Flow Control Type and Opcode
6749
 E1000_RTTBCNIDXE1000_RTTBCNIDX 0xB204 igb_regs.h Tx BCN Congestion Point
6750
 E1000_RTTBCNACHE1000_RTTBCNACH 0x0B214 igb_regs.h Tx BCN Control High
6751
 E1000_RTTBCNACLE1000_RTTBCNACL 0x0B210 igb_regs.h Tx BCN Control Low
6752
 PHN_MAX_NUM_PORTSPHN_MAX_NUM_PORTS 8 phantom.c 　
6753
 PHN_CMDPEG_INIT_TIMEOUT_SECPHN_CMDPEG_INIT_TIMEOUT_SEC 50 phantom.c 　
6754
 PHN_RCVPEG_INIT_TIMEOUT_SECPHN_RCVPEG_INIT_TIMEOUT_SEC 2 phantom.c 　
6755
 PHN_ISSUE_CMD_TIMEOUT_MSPHN_ISSUE_CMD_TIMEOUT_MS 2000 phantom.c 　
6756
 PHN_TEST_MEM_TIMEOUT_MSPHN_TEST_MEM_TIMEOUT_MS 100 phantom.c 　
6757
 PHN_CLP_CMD_TIMEOUT_MSPHN_CLP_CMD_TIMEOUT_MS 500 phantom.c 　
6758
 PHN_LINK_POLL_FREQUENCYPHN_LINK_POLL_FREQUENCY 4096 phantom.c 　
6759
 PHN_NUM_RDSPHN_NUM_RDS 32 phantom.c 　
6760
 PHN_RDS_MAX_FILLPHN_RDS_MAX_FILL 16 phantom.c 　
6761
 PHN_RX_BUFSIZEPHN_RX_BUFSIZE ( 32 + \ ETH_FRAME_LEN ) phantom.c 　
6762
 PHN_NUM_SDSPHN_NUM_SDS 32 phantom.c 　
6763
 PHN_NUM_CDSPHN_NUM_CDS 8 phantom.c 　
6764
 PHN_CLP_TAG_MAGICPHN_CLP_TAG_MAGIC 0xc19c1900UL phantom.c 　
6765
 PHN_CLP_TAG_MAGIC_MASKPHN_CLP_TAG_MAGIC_MASK 0xffffff00UL phantom.c 　
6766
 PHN_CLP_BLKSIZEPHN_CLP_BLKSIZE ( sizeof ( union phantom_clp_data ) ) phantom.c 　
6767
 NX_CDRP_CLEARNX_CDRP_CLEAR 0x00000000 nxhal_nic_interface.h 　
6768
 NX_CDRP_CMD_BITNX_CDRP_CMD_BIT 0x80000000 nxhal_nic_interface.h 　
6769
 NX_CDRP_RSP_OKNX_CDRP_RSP_OK 0x00000001 nxhal_nic_interface.h 　
6770
 NX_CDRP_RSP_FAILNX_CDRP_RSP_FAIL 0x00000002 nxhal_nic_interface.h 　
6771
 NX_CDRP_RSP_TIMEOUTNX_CDRP_RSP_TIMEOUT 0x00000003 nxhal_nic_interface.h 　
6772
 NX_CDRP_CMD_SUBMIT_CAPABILITIESNX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 nxhal_nic_interface.h 　
6773
 NX_CDRP_CMD_READ_MAX_RDS_PER_CTNX_CDRP_CMD_READ_MAX_RDS_PER_CT 0x00000002 nxhal_nic_interface.h 　
6774
 NX_CDRP_CMD_READ_MAX_SDS_PER_CTNX_CDRP_CMD_READ_MAX_SDS_PER_CT 0x00000003 nxhal_nic_interface.h 　
6775
 NX_CDRP_CMD_READ_MAX_RULES_PER_NX_CDRP_CMD_READ_MAX_RULES_PER_ 0x00000004 nxhal_nic_interface.h 　
6776
 NX_CDRP_CMD_READ_MAX_RX_CTXNX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 nxhal_nic_interface.h 　
6777
 NX_CDRP_CMD_READ_MAX_TX_CTXNX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 nxhal_nic_interface.h 　
6778
 NX_CDRP_CMD_CREATE_RX_CTXNX_CDRP_CMD_CREATE_RX_CTX 0x00000007 nxhal_nic_interface.h 　
6779
 NX_CDRP_CMD_DESTROY_RX_CTXNX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 nxhal_nic_interface.h 　
6780
 NX_CDRP_CMD_CREATE_TX_CTXNX_CDRP_CMD_CREATE_TX_CTX 0x00000009 nxhal_nic_interface.h 　
6781
 NX_CDRP_CMD_DESTROY_TX_CTXNX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a nxhal_nic_interface.h 　
6782
 NX_CDRP_CMD_SETUP_STATISTICSNX_CDRP_CMD_SETUP_STATISTICS 0x0000000e nxhal_nic_interface.h 　
6783
 NX_CDRP_CMD_GET_STATISTICSNX_CDRP_CMD_GET_STATISTICS 0x0000000f nxhal_nic_interface.h 　
6784
 NX_CDRP_CMD_DELETE_STATISTICSNX_CDRP_CMD_DELETE_STATISTICS 0x00000010 nxhal_nic_interface.h 　
6785
 NX_CDRP_CMD_MAXNX_CDRP_CMD_MAX 0x00000011 nxhal_nic_interface.h 　
6786
 NX_CAP0_LEGACY_CONTEXTNX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) nxhal_nic_interface.h 　
6787
 NX_CAP0_MULTI_CONTEXTNX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) nxhal_nic_interface.h 　
6788
 NX_CAP0_LEGACY_MNNX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) nxhal_nic_interface.h 　
6789
 NX_CAP0_LEGACY_MSNX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) nxhal_nic_interface.h 　
6790
 NX_CAP0_CUT_THROUGHNX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) nxhal_nic_interface.h 　
6791
 NX_CAP0_LRONX_CAP0_LRO NX_CAP_BIT(0, 5) nxhal_nic_interface.h 　
6792
 NX_CAP0_LSONX_CAP0_LSO NX_CAP_BIT(0, 6) nxhal_nic_interface.h 　
6793
 NX_CAP1_NICNX_CAP1_NIC NX_CAP_BIT(1, 0) nxhal_nic_interface.h 　
6794
 NX_CAP1_PXENX_CAP1_PXE NX_CAP_BIT(1, 1) nxhal_nic_interface.h 　
6795
 NX_CAP1_CHIMNEYNX_CAP1_CHIMNEY NX_CAP_BIT(1, 2) nxhal_nic_interface.h 　
6796
 NX_CAP1_LSANX_CAP1_LSA NX_CAP_BIT(1, 3) nxhal_nic_interface.h 　
6797
 NX_CAP1_RDMANX_CAP1_RDMA NX_CAP_BIT(1, 4) nxhal_nic_interface.h 　
6798
 NX_CAP1_ISCSINX_CAP1_ISCSI NX_CAP_BIT(1, 5) nxhal_nic_interface.h 　
6799
 NX_CAP1_FCOENX_CAP1_FCOE NX_CAP_BIT(1, 6) nxhal_nic_interface.h 　
6800
 NX_RX_RULETYPE_DEFAULTNX_RX_RULETYPE_DEFAULT 0 nxhal_nic_interface.h 　
6801
 NX_RX_RULETYPE_MACNX_RX_RULETYPE_MAC 1 nxhal_nic_interface.h 　
6802
 NX_RX_RULETYPE_MAC_VLANNX_RX_RULETYPE_MAC_VLAN 2 nxhal_nic_interface.h 　
6803
 NX_RX_RULETYPE_MAC_RSSNX_RX_RULETYPE_MAC_RSS 3 nxhal_nic_interface.h 　
6804
 NX_RX_RULETYPE_MAC_VLAN_RSSNX_RX_RULETYPE_MAC_VLAN_RSS 4 nxhal_nic_interface.h 　
6805
 NX_RX_RULETYPE_MAXNX_RX_RULETYPE_MAX 5 nxhal_nic_interface.h 　
6806
 NX_RX_RULECMD_ADDNX_RX_RULECMD_ADD 0 nxhal_nic_interface.h 　
6807
 NX_RX_RULECMD_REMOVENX_RX_RULECMD_REMOVE 1 nxhal_nic_interface.h 　
6808
 NX_RX_RULECMD_MAXNX_RX_RULECMD_MAX 2 nxhal_nic_interface.h 　
6809
 NX_HOST_CTX_STATE_FREEDNX_HOST_CTX_STATE_FREED 0 nxhal_nic_interface.h Invalid state
6810
 NX_HOST_CTX_STATE_ALLOCATEDNX_HOST_CTX_STATE_ALLOCATED 1 nxhal_nic_interface.h Not committed
6811
 NX_HOST_CTX_STATE_ACTIVENX_HOST_CTX_STATE_ACTIVE 2 nxhal_nic_interface.h 　
6812
 NX_HOST_CTX_STATE_DISABLEDNX_HOST_CTX_STATE_DISABLED 3 nxhal_nic_interface.h 　
6813
 NX_HOST_CTX_STATE_QUIESCEDNX_HOST_CTX_STATE_QUIESCED 4 nxhal_nic_interface.h 　
6814
 NX_HOST_CTX_STATE_MAXNX_HOST_CTX_STATE_MAX 5 nxhal_nic_interface.h 　
6815
 NX_HOST_INT_CRB_MODE_UNIQUENX_HOST_INT_CRB_MODE_UNIQUE 0 nxhal_nic_interface.h 　
6816
 NX_HOST_INT_CRB_MODE_SHAREDNX_HOST_INT_CRB_MODE_SHARED 1 nxhal_nic_interface.h <= LEGACY
6817
 NX_HOST_INT_CRB_MODE_NORXNX_HOST_INT_CRB_MODE_NORX 2 nxhal_nic_interface.h 　
6818
 NX_HOST_INT_CRB_MODE_NOTXNX_HOST_INT_CRB_MODE_NOTX 3 nxhal_nic_interface.h 　
6819
 NX_HOST_INT_CRB_MODE_NORXTXNX_HOST_INT_CRB_MODE_NORXTX 4 nxhal_nic_interface.h 　
6820
 NX_DESTROY_CTX_RESETNX_DESTROY_CTX_RESET 0 nxhal_nic_interface.h 　
6821
 NX_DESTROY_CTX_D3_RESETNX_DESTROY_CTX_D3_RESET 1 nxhal_nic_interface.h 　
6822
 NX_DESTROY_CTX_MAXNX_DESTROY_CTX_MAX 2 nxhal_nic_interface.h 　
6823
 NX_HOST_RDS_CRB_MODE_UNIQUENX_HOST_RDS_CRB_MODE_UNIQUE 0 nxhal_nic_interface.h <= LEGACY
6824
 NX_HOST_RDS_CRB_MODE_SHAREDNX_HOST_RDS_CRB_MODE_SHARED 1 nxhal_nic_interface.h 　
6825
 NX_HOST_RDS_CRB_MODE_CUSTOMNX_HOST_RDS_CRB_MODE_CUSTOM 2 nxhal_nic_interface.h 　
6826
 NX_HOST_RDS_CRB_MODE_MAXNX_HOST_RDS_CRB_MODE_MAX 3 nxhal_nic_interface.h 　
6827
 NX_RDS_RING_TYPE_NORMALNX_RDS_RING_TYPE_NORMAL 0 nxhal_nic_interface.h 　
6828
 NX_RDS_RING_TYPE_JUMBONX_RDS_RING_TYPE_JUMBO 1 nxhal_nic_interface.h 　
6829
 NX_RDS_RING_TYPE_LRONX_RDS_RING_TYPE_LRO 2 nxhal_nic_interface.h 　
6830
 NX_RDS_RING_TYPE_MAXNX_RDS_RING_TYPE_MAX 3 nxhal_nic_interface.h 　
6831
 NX_STATISTICS_MODE_INVALIDNX_STATISTICS_MODE_INVALID 0 nxhal_nic_interface.h 　
6832
 NX_STATISTICS_MODE_PULLNX_STATISTICS_MODE_PULL 1 nxhal_nic_interface.h 　
6833
 NX_STATISTICS_MODE_PUSHNX_STATISTICS_MODE_PUSH 2 nxhal_nic_interface.h 　
6834
 NX_STATISTICS_MODE_SINGLE_SHOTNX_STATISTICS_MODE_SINGLE_SHOT 3 nxhal_nic_interface.h 　
6835
 NX_STATISTICS_MODE_MAXNX_STATISTICS_MODE_MAX 4 nxhal_nic_interface.h 　
6836
 NX_STATISTICS_TYPE_INVALIDNX_STATISTICS_TYPE_INVALID 0 nxhal_nic_interface.h 　
6837
 NX_STATISTICS_TYPE_NIC_RX_CORENX_STATISTICS_TYPE_NIC_RX_CORE 1 nxhal_nic_interface.h 　
6838
 NX_STATISTICS_TYPE_NIC_TX_CORENX_STATISTICS_TYPE_NIC_TX_CORE 2 nxhal_nic_interface.h 　
6839
 NX_STATISTICS_TYPE_NIC_RX_ALLNX_STATISTICS_TYPE_NIC_RX_ALL 3 nxhal_nic_interface.h 　
6840
 NX_STATISTICS_TYPE_NIC_TX_ALLNX_STATISTICS_TYPE_NIC_TX_ALL 4 nxhal_nic_interface.h 　
6841
 NX_STATISTICS_TYPE_MAXNX_STATISTICS_TYPE_MAX 5 nxhal_nic_interface.h 　
6842
 NXHAL_VERSIONNXHAL_VERSION 1 phantom.h 　
6843
 UNM_DMA_BUFFER_ALIGNUNM_DMA_BUFFER_ALIGN 16 phantom.h 　
6844
 __unm_dma_aligned__unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) )) phantom.h 　
6845
 UNM_128M_CRB_WINDOWUNM_128M_CRB_WINDOW 0x6110210UL phantom.h 　
6846
 UNM_32M_CRB_WINDOWUNM_32M_CRB_WINDOW 0x0110210UL phantom.h 　
6847
 UNM_2M_CRB_WINDOWUNM_2M_CRB_WINDOW 0x0130060UL phantom.h 　
6848
 UNM_CRB_PCIEUNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE ) phantom.h 　
6849
 UNM_PCIE_SEM2_LOCKUNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 ) phantom.h 　
6850
 UNM_PCIE_SEM2_UNLOCKUNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 ) phantom.h 　
6851
 UNM_PCIE_IRQ_VECTORUNM_PCIE_IRQ_VECTOR ( UNM_CRB_PCIE + 0x10100 ) phantom.h 　
6852
 UNM_PCIE_IRQ_STATEUNM_PCIE_IRQ_STATE ( UNM_CRB_PCIE + 0x1206c ) phantom.h 　
6853
 UNM_PCIE_IRQ_MASK_F0UNM_PCIE_IRQ_MASK_F0 ( UNM_CRB_PCIE + 0x10128 ) phantom.h 　
6854
 UNM_PCIE_IRQ_MASK_F1UNM_PCIE_IRQ_MASK_F1 ( UNM_CRB_PCIE + 0x10170 ) phantom.h 　
6855
 UNM_PCIE_IRQ_MASK_F2UNM_PCIE_IRQ_MASK_F2 ( UNM_CRB_PCIE + 0x10174 ) phantom.h 　
6856
 UNM_PCIE_IRQ_MASK_F3UNM_PCIE_IRQ_MASK_F3 ( UNM_CRB_PCIE + 0x10178 ) phantom.h 　
6857
 UNM_PCIE_IRQ_MASK_F4UNM_PCIE_IRQ_MASK_F4 ( UNM_CRB_PCIE + 0x10370 ) phantom.h 　
6858
 UNM_PCIE_IRQ_MASK_F5UNM_PCIE_IRQ_MASK_F5 ( UNM_CRB_PCIE + 0x10374 ) phantom.h 　
6859
 UNM_PCIE_IRQ_MASK_F6UNM_PCIE_IRQ_MASK_F6 ( UNM_CRB_PCIE + 0x10378 ) phantom.h 　
6860
 UNM_PCIE_IRQ_MASK_F7UNM_PCIE_IRQ_MASK_F7 ( UNM_CRB_PCIE + 0x1037c ) phantom.h 　
6861
 UNM_PCIE_IRQ_MASK_MAGICUNM_PCIE_IRQ_MASK_MAGIC 0x0000fbffUL phantom.h 　
6862
 UNM_PCIE_IRQ_STATUS_F0UNM_PCIE_IRQ_STATUS_F0 ( UNM_CRB_PCIE + 0x10118 ) phantom.h 　
6863
 UNM_PCIE_IRQ_STATUS_F1UNM_PCIE_IRQ_STATUS_F1 ( UNM_CRB_PCIE + 0x10160 ) phantom.h 　
6864
 UNM_PCIE_IRQ_STATUS_F2UNM_PCIE_IRQ_STATUS_F2 ( UNM_CRB_PCIE + 0x10164 ) phantom.h 　
6865
 UNM_PCIE_IRQ_STATUS_F3UNM_PCIE_IRQ_STATUS_F3 ( UNM_CRB_PCIE + 0x10168 ) phantom.h 　
6866
 UNM_PCIE_IRQ_STATUS_F4UNM_PCIE_IRQ_STATUS_F4 ( UNM_CRB_PCIE + 0x10360 ) phantom.h 　
6867
 UNM_PCIE_IRQ_STATUS_F5UNM_PCIE_IRQ_STATUS_F5 ( UNM_CRB_PCIE + 0x10364 ) phantom.h 　
6868
 UNM_PCIE_IRQ_STATUS_F6UNM_PCIE_IRQ_STATUS_F6 ( UNM_CRB_PCIE + 0x10368 ) phantom.h 　
6869
 UNM_PCIE_IRQ_STATUS_F7UNM_PCIE_IRQ_STATUS_F7 ( UNM_CRB_PCIE + 0x1036c ) phantom.h 　
6870
 UNM_PCIE_IRQ_STATUS_MAGICUNM_PCIE_IRQ_STATUS_MAGIC 0xffffffffUL phantom.h 　
6871
 UNM_CRB_CAMUNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM ) phantom.h 　
6872
 UNM_CAM_RAMUNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 ) phantom.h 　
6873
 UNM_CAM_RAM_PORT_MODEUNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 ) phantom.h 　
6874
 UNM_CAM_RAM_PORT_MODE_AUTO_NEGUNM_CAM_RAM_PORT_MODE_AUTO_NEG 4 phantom.h 　
6875
 UNM_CAM_RAM_PORT_MODE_AUTO_NEG_UNM_CAM_RAM_PORT_MODE_AUTO_NEG_ 5 phantom.h 　
6876
 UNM_CAM_RAM_DMESG_SIG_MAGICUNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL phantom.h 　
6877
 UNM_CAM_RAM_NUM_DMESG_BUFFERSUNM_CAM_RAM_NUM_DMESG_BUFFERS 5 phantom.h 　
6878
 UNM_CAM_RAM_CLP_COMMANDUNM_CAM_RAM_CLP_COMMAND ( UNM_CAM_RAM + 0x000c0 ) phantom.h 　
6879
 UNM_CAM_RAM_CLP_COMMAND_LASTUNM_CAM_RAM_CLP_COMMAND_LAST 0x00000080UL phantom.h 　
6880
 UNM_CAM_RAM_CLP_DATA_LOUNM_CAM_RAM_CLP_DATA_LO ( UNM_CAM_RAM + 0x000c4 ) phantom.h 　
6881
 UNM_CAM_RAM_CLP_DATA_HIUNM_CAM_RAM_CLP_DATA_HI ( UNM_CAM_RAM + 0x000c8 ) phantom.h 　
6882
 UNM_CAM_RAM_CLP_STATUSUNM_CAM_RAM_CLP_STATUS ( UNM_CAM_RAM + 0x000cc ) phantom.h 　
6883
 UNM_CAM_RAM_CLP_STATUS_STARTUNM_CAM_RAM_CLP_STATUS_START 0x00000001UL phantom.h 　
6884
 UNM_CAM_RAM_CLP_STATUS_DONEUNM_CAM_RAM_CLP_STATUS_DONE 0x00000002UL phantom.h 　
6885
 UNM_CAM_RAM_CLP_STATUS_ERRORUNM_CAM_RAM_CLP_STATUS_ERROR 0x0000ff00UL phantom.h 　
6886
 UNM_CAM_RAM_CLP_STATUS_UNINITIAUNM_CAM_RAM_CLP_STATUS_UNINITIA 0xffffffffUL phantom.h 　
6887
 UNM_CAM_RAM_BOOT_ENABLEUNM_CAM_RAM_BOOT_ENABLE ( UNM_CAM_RAM + 0x000fc ) phantom.h 　
6888
 UNM_CAM_RAM_WOL_PORT_MODEUNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 ) phantom.h 　
6889
 UNM_CAM_RAM_MAC_ADDRSUNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 ) phantom.h 　
6890
 UNM_CAM_RAM_COLD_BOOTUNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc ) phantom.h 　
6891
 UNM_CAM_RAM_COLD_BOOT_MAGICUNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL phantom.h 　
6892
 UNM_NIC_REGUNM_NIC_REG ( UNM_CRB_CAM + 0x02200 ) phantom.h 　
6893
 UNM_NIC_REG_NX_CDRPUNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 ) phantom.h 　
6894
 UNM_NIC_REG_NX_ARG1UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c ) phantom.h 　
6895
 UNM_NIC_REG_NX_ARG2UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 ) phantom.h 　
6896
 UNM_NIC_REG_NX_ARG3UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 ) phantom.h 　
6897
 UNM_NIC_REG_NX_SIGNUNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 ) phantom.h 　
6898
 UNM_NIC_REG_DUMMY_BUF_ADDR_HIUNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c ) phantom.h 　
6899
 UNM_NIC_REG_DUMMY_BUF_ADDR_LOUNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 ) phantom.h 　
6900
 UNM_NIC_REG_CMDPEG_STATEUNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 ) phantom.h 　
6901
 UNM_NIC_REG_CMDPEG_STATE_INITIAUNM_NIC_REG_CMDPEG_STATE_INITIA 0xff01 phantom.h 　
6902
 UNM_NIC_REG_CMDPEG_STATE_INITIAUNM_NIC_REG_CMDPEG_STATE_INITIA 0xf00f phantom.h 　
6903
 UNM_NIC_REG_DUMMY_BUFUNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc ) phantom.h 　
6904
 UNM_NIC_REG_DUMMY_BUF_INITUNM_NIC_REG_DUMMY_BUF_INIT 0 phantom.h 　
6905
 UNM_NIC_REG_XG_STATE_P3UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 ) phantom.h 　
6906
 UNM_NIC_REG_XG_STATE_P3_LINK_UPUNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01 phantom.h 　
6907
 UNM_NIC_REG_XG_STATE_P3_LINK_DOUNM_NIC_REG_XG_STATE_P3_LINK_DO 0x02 phantom.h 　
6908
 UNM_NIC_REG_RCVPEG_STATEUNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c ) phantom.h 　
6909
 UNM_NIC_REG_RCVPEG_STATE_INITIAUNM_NIC_REG_RCVPEG_STATE_INITIA 0xff01 phantom.h 　
6910
 UNM_CRB_ROMUSBUNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB ) phantom.h 　
6911
 UNM_ROMUSB_GLBUNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 ) phantom.h 　
6912
 UNM_ROMUSB_GLB_STATUSUNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 ) phantom.h 　
6913
 UNM_ROMUSB_GLB_STATUS_ROM_DONEUNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 ) phantom.h 　
6914
 UNM_ROMUSB_GLB_SW_RESETUNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 ) phantom.h 　
6915
 UNM_ROMUSB_GLB_SW_RESET_MAGICUNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL phantom.h 　
6916
 UNM_ROMUSB_GLB_PEGTUNE_DONEUNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c ) phantom.h 　
6917
 UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGUNM_ROMUSB_GLB_PEGTUNE_DONE_MAG 0x31 phantom.h 　
6918
 UNM_ROMUSB_ROMUNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 ) phantom.h 　
6919
 UNM_ROMUSB_ROM_INSTR_OPCODEUNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 ) phantom.h 　
6920
 UNM_ROMUSB_ROM_ADDRESSUNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 ) phantom.h 　
6921
 UNM_ROMUSB_ROM_WDATAUNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c ) phantom.h 　
6922
 UNM_ROMUSB_ROM_ABYTE_CNTUNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 ) phantom.h 　
6923
 UNM_ROMUSB_ROM_DUMMY_BYTE_CNTUNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 ) phantom.h 　
6924
 UNM_ROMUSB_ROM_RDATAUNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 ) phantom.h 　
6925
 UNM_CRB_TESTUNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST ) phantom.h 　
6926
 UNM_TEST_CONTROLUNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 ) phantom.h 　
6927
 UNM_TEST_CONTROL_STARTUNM_TEST_CONTROL_START 0x01 phantom.h 　
6928
 UNM_TEST_CONTROL_ENABLEUNM_TEST_CONTROL_ENABLE 0x02 phantom.h 　
6929
 UNM_TEST_CONTROL_BUSYUNM_TEST_CONTROL_BUSY 0x08 phantom.h 　
6930
 UNM_TEST_ADDR_LOUNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 ) phantom.h 　
6931
 UNM_TEST_ADDR_HIUNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 ) phantom.h 　
6932
 UNM_TEST_RDDATA_LOUNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 ) phantom.h 　
6933
 UNM_TEST_RDDATA_HIUNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac ) phantom.h 　
6934
 UNM_CRB_PEG_0UNM_CRB_PEG_0 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 ) phantom.h 　
6935
 UNM_PEG_0_HALT_STATUSUNM_PEG_0_HALT_STATUS ( UNM_CRB_PEG_0 + 0x00030 ) phantom.h 　
6936
 UNM_PEG_0_HALTUNM_PEG_0_HALT ( UNM_CRB_PEG_0 + 0x0003c ) phantom.h 　
6937
 UNM_CRB_PEG_1UNM_CRB_PEG_1 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 ) phantom.h 　
6938
 UNM_PEG_1_HALT_STATUSUNM_PEG_1_HALT_STATUS ( UNM_CRB_PEG_1 + 0x00030 ) phantom.h 　
6939
 UNM_PEG_1_HALTUNM_PEG_1_HALT ( UNM_CRB_PEG_1 + 0x0003c ) phantom.h 　
6940
 UNM_CRB_PEG_2UNM_CRB_PEG_2 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 ) phantom.h 　
6941
 UNM_PEG_2_HALT_STATUSUNM_PEG_2_HALT_STATUS ( UNM_CRB_PEG_2 + 0x00030 ) phantom.h 　
6942
 UNM_PEG_2_HALTUNM_PEG_2_HALT ( UNM_CRB_PEG_2 + 0x0003c ) phantom.h 　
6943
 UNM_CRB_PEG_3UNM_CRB_PEG_3 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 ) phantom.h 　
6944
 UNM_PEG_3_HALT_STATUSUNM_PEG_3_HALT_STATUS ( UNM_CRB_PEG_3 + 0x00030 ) phantom.h 　
6945
 UNM_PEG_3_HALTUNM_PEG_3_HALT ( UNM_CRB_PEG_3 + 0x0003c ) phantom.h 　
6946
 UNM_CRB_PEG_4UNM_CRB_PEG_4 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 ) phantom.h 　
6947
 UNM_PEG_4_HALT_STATUSUNM_PEG_4_HALT_STATUS ( UNM_CRB_PEG_4 + 0x00030 ) phantom.h 　
6948
 UNM_PEG_4_HALTUNM_PEG_4_HALT ( UNM_CRB_PEG_4 + 0x0003c ) phantom.h 　
6949
 GRF5101_ANTENNAGRF5101_ANTENNA 0xA3 rtl8180_grf5101.c 　
6950
 MAXIM_ANTENNAMAXIM_ANTENNA 0xb3 rtl8180_max2820.c 　
6951
 SA2400_ANTENNASA2400_ANTENNA 0x91 rtl8180_sa2400.c 　
6952
 SA2400_DIG_ANAPARAM_PWR1_ONSA2400_DIG_ANAPARAM_PWR1_ON 0x8 rtl8180_sa2400.c 　
6953
 SA2400_ANA_ANAPARAM_PWR1_ONSA2400_ANA_ANAPARAM_PWR1_ON 0x28 rtl8180_sa2400.c 　
6954
 SA2400_ANAPARAM_PWR0_ONSA2400_ANAPARAM_PWR0_ON 0x3 rtl8180_sa2400.c 　
6955
 SA2400_MAX_SENSSA2400_MAX_SENS 85 rtl8180_sa2400.c 　
6956
 SA2400_REG4_FIRDAC_SHIFTSA2400_REG4_FIRDAC_SHIFT 7 rtl8180_sa2400.c 　
6957
 RTL8225_ANAPARAM_ONRTL8225_ANAPARAM_ON 0xa0000b59 rtl8185_rtl8225.c 　
6958
 RTL8225_ANAPARAM2_ONRTL8225_ANAPARAM2_ON 0x860dec11 rtl8185_rtl8225.c 　
6959
 RTL8225_ANAPARAM_OFFRTL8225_ANAPARAM_OFF 0xa00beb59 rtl8185_rtl8225.c 　
6960
 RTL8225_ANAPARAM2_OFFRTL8225_ANAPARAM2_OFF 0x840dec11 rtl8185_rtl8225.c 　
6961
 RTL818X_NR_B_RATESRTL818X_NR_B_RATES 4 rtl818x.c 　
6962
 RTL818X_NR_RATESRTL818X_NR_RATES 12 rtl818x.c 　
6963
 RTL818X_NR_RF_NAMESRTL818X_NR_RF_NAMES 11 rtl818x.c 　
6964
 RTL_ROMRTL_ROM PCI_ROM rtl818x.c 　
6965
 MAX_RX_SIZEMAX_RX_SIZE IEEE80211_MAX_FRAME_LEN rtl818x.h 　
6966
 RF_PARAM_ANALOGPHYRF_PARAM_ANALOGPHY (1 << 0) rtl818x.h 　
6967
 RF_PARAM_ANTBDEFAULTRF_PARAM_ANTBDEFAULT (1 << 1) rtl818x.h 　
6968
 RF_PARAM_CARRIERSENSE1RF_PARAM_CARRIERSENSE1 (1 << 2) rtl818x.h 　
6969
 RF_PARAM_CARRIERSENSE2RF_PARAM_CARRIERSENSE2 (1 << 3) rtl818x.h 　
6970
 BB_ANTATTEN_CHAN14BB_ANTATTEN_CHAN14 0x0C rtl818x.h 　
6971
 BB_ANTENNA_BBB_ANTENNA_B 0x40 rtl818x.h 　
6972
 BB_HOST_BANGBB_HOST_BANG (1 << 30) rtl818x.h 　
6973
 BB_HOST_BANG_ENBB_HOST_BANG_EN (1 << 2) rtl818x.h 　
6974
 BB_HOST_BANG_CLKBB_HOST_BANG_CLK (1 << 1) rtl818x.h 　
6975
 BB_HOST_BANG_DATABB_HOST_BANG_DATA 1 rtl818x.h 　
6976
 ANAPARAM_TXDACOFF_SHIFTANAPARAM_TXDACOFF_SHIFT 27 rtl818x.h 　
6977
 ANAPARAM_PWR0_SHIFTANAPARAM_PWR0_SHIFT 28 rtl818x.h 　
6978
 ANAPARAM_PWR0_MASKANAPARAM_PWR0_MASK (0x07 << ANAPARAM_PWR0_SHIFT) rtl818x.h 　
6979
 ANAPARAM_PWR1_SHIFTANAPARAM_PWR1_SHIFT 20 rtl818x.h 　
6980
 ANAPARAM_PWR1_MASKANAPARAM_PWR1_MASK (0x7F << ANAPARAM_PWR1_SHIFT) rtl818x.h 　
6981
 RTL818X_RX_RING_SIZERTL818X_RX_RING_SIZE 8 rtl818x.h doesn't have to be a power of 2
6982
 RTL818X_TX_RING_SIZERTL818X_TX_RING_SIZE 8 rtl818x.h nor this [but 2^n is very slightly faster]
6983
 RTL818X_RING_ALIGNRTL818X_RING_ALIGN 256 rtl818x.h 　
6984
 RTL818X_MAX_RETRIESRTL818X_MAX_RETRIES 4 rtl818x.h 　
6985
 RTL818X_RF_DRIVERSRTL818X_RF_DRIVERS __table(struct rtl818x_rf_ops, "rtl818x_rf_drivers") rtl818x.h 　
6986
 __rtl818x_rf_driver__rtl818x_rf_driver __table_entry(RTL818X_RF_DRIVERS, 01) rtl818x.h 　
6987
 ETH_FCS_LENETH_FCS_LEN 4 vxge_traffic.c 　
6988
 VXGE_CACHE_LINE_SIZEVXGE_CACHE_LINE_SIZE 4096 vxge_config.h 　
6989
 WAIT_FACTORWAIT_FACTOR 1 vxge_config.h 　
6990
 VXGE_HW_MAC_MAX_WIRE_PORTSVXGE_HW_MAC_MAX_WIRE_PORTS 2 vxge_config.h 　
6991
 VXGE_HW_MAC_MAX_AGGR_PORTSVXGE_HW_MAC_MAX_AGGR_PORTS 2 vxge_config.h 　
6992
 VXGE_HW_MAC_MAX_PORTSVXGE_HW_MAC_MAX_PORTS 3 vxge_config.h 　
6993
 VXGE_HW_MIN_MTUVXGE_HW_MIN_MTU 68 vxge_config.h 　
6994
 VXGE_HW_MAX_MTUVXGE_HW_MAX_MTU 9600 vxge_config.h 　
6995
 VXGE_HW_DEFAULT_MTUVXGE_HW_DEFAULT_MTU 1500 vxge_config.h 　
6996
 VXGE_NONEVXGE_NONE 0x00 vxge_config.h 　
6997
 VXGE_INFOVXGE_INFO 0x01 vxge_config.h 　
6998
 VXGE_INTRVXGE_INTR 0x02 vxge_config.h 　
6999
 VXGE_XMITVXGE_XMIT 0x04 vxge_config.h 　
7000
 VXGE_POLLVXGE_POLL 0x08 vxge_config.h 　
7001
 VXGE_ERRVXGE_ERR 0x10 vxge_config.h 　
7002
 VXGE_TRACEVXGE_TRACE 0x20 vxge_config.h 　
7003
 VXGE_ALLVXGE_ALL (VXGE_INFO|VXGE_INTR|VXGE_XMIT\ |VXGE_POLL|VXGE_ERR|VXGE_TRACE) vxge_config.h 　
7004
 NULL_VPIDNULL_VPID 0xFFFFFFFF vxge_config.h 　
7005
 VXGE_HW_EVENT_BASEVXGE_HW_EVENT_BASE 0 vxge_config.h 　
7006
 VXGE_LL_EVENT_BASEVXGE_LL_EVENT_BASE 100 vxge_config.h 　
7007
 VXGE_HW_BASE_INFVXGE_HW_BASE_INF 100 vxge_config.h 　
7008
 VXGE_HW_BASE_ERRVXGE_HW_BASE_ERR 200 vxge_config.h 　
7009
 VXGE_HW_BASE_BADCFGVXGE_HW_BASE_BADCFG 300 vxge_config.h 　
7010
 VXGE_HW_DEF_DEVICE_POLL_MILLISVXGE_HW_DEF_DEVICE_POLL_MILLIS 1000 vxge_config.h 　
7011
 VXGE_HW_MAX_PAYLOAD_SIZE_512VXGE_HW_MAX_PAYLOAD_SIZE_512 2 vxge_config.h 　
7012
 VXGE_HW_FW_STRLENVXGE_HW_FW_STRLEN 32 vxge_config.h 　
7013
 VXGE_HW_INFO_LENVXGE_HW_INFO_LEN 64 vxge_config.h 　
7014
 VXGE_HW_PMD_INFO_LENVXGE_HW_PMD_INFO_LEN 16 vxge_config.h 　
7015
 VXGE_MAX_PRINT_BUF_SIZEVXGE_MAX_PRINT_BUF_SIZE 128 vxge_config.h 　
7016
 VXGE_DRIVER_NAMEVXGE_DRIVER_NAME "vxge" vxge_main.h 　
7017
 VXGE_DRIVER_VENDORVXGE_DRIVER_VENDOR "Neterion, Inc" vxge_main.h 　
7018
 PCI_VENDOR_ID_S2IOPCI_VENDOR_ID_S2IO 0x17D5 vxge_main.h 　
7019
 PCI_DEVICE_ID_TITAN_WINPCI_DEVICE_ID_TITAN_WIN 0x5733 vxge_main.h 　
7020
 PCI_DEVICE_ID_TITAN_UNIPCI_DEVICE_ID_TITAN_UNI 0x5833 vxge_main.h 　
7021
 VXGE_HW_TITAN1_PCI_REVISIONVXGE_HW_TITAN1_PCI_REVISION 1 vxge_main.h 　
7022
 VXGE_HW_TITAN1A_PCI_REVISIONVXGE_HW_TITAN1A_PCI_REVISION 2 vxge_main.h 　
7023
 VXGE_HP_ISS_SUBSYS_VENDORIDVXGE_HP_ISS_SUBSYS_VENDORID 0x103C vxge_main.h 　
7024
 VXGE_HP_ISS_SUBSYS_DEVICEID_1VXGE_HP_ISS_SUBSYS_DEVICEID_1 0x323B vxge_main.h 　
7025
 VXGE_HP_ISS_SUBSYS_DEVICEID_2VXGE_HP_ISS_SUBSYS_DEVICEID_2 0x323C vxge_main.h 　
7026
 VXGE_USE_DEFAULTVXGE_USE_DEFAULT 0xffffffff vxge_main.h 　
7027
 VXGE_HW_VPATH_MSIX_ACTIVEVXGE_HW_VPATH_MSIX_ACTIVE 4 vxge_main.h 　
7028
 VXGE_ALARM_MSIX_IDVXGE_ALARM_MSIX_ID 2 vxge_main.h 　
7029
 VXGE_HW_RXSYNC_FREQ_CNTVXGE_HW_RXSYNC_FREQ_CNT 4 vxge_main.h 　
7030
 VXGE_LL_RX_COPY_THRESHOLDVXGE_LL_RX_COPY_THRESHOLD 256 vxge_main.h 　
7031
 VXGE_DEF_FIFO_LENGTHVXGE_DEF_FIFO_LENGTH 84 vxge_main.h 　
7032
 NO_STEERINGNO_STEERING 0 vxge_main.h 　
7033
 PORT_STEERINGPORT_STEERING 0x1 vxge_main.h 　
7034
 RTH_TCP_UDP_STEERINGRTH_TCP_UDP_STEERING 0x2 vxge_main.h 　
7035
 RTH_IPV4_STEERINGRTH_IPV4_STEERING 0x3 vxge_main.h 　
7036
 RTH_IPV6_EX_STEERINGRTH_IPV6_EX_STEERING 0x4 vxge_main.h 　
7037
 RTH_BUCKET_SIZERTH_BUCKET_SIZE 8 vxge_main.h 　
7038
 TX_PRIORITY_STEERINGTX_PRIORITY_STEERING 1 vxge_main.h 　
7039
 TX_VLAN_STEERINGTX_VLAN_STEERING 2 vxge_main.h 　
7040
 TX_PORT_STEERINGTX_PORT_STEERING 3 vxge_main.h 　
7041
 TX_MULTIQ_STEERINGTX_MULTIQ_STEERING 4 vxge_main.h 　
7042
 VXGE_HW_PROM_MODE_ENABLEVXGE_HW_PROM_MODE_ENABLE 1 vxge_main.h 　
7043
 VXGE_HW_PROM_MODE_DISABLEVXGE_HW_PROM_MODE_DISABLE 0 vxge_main.h 　
7044
 VXGE_HW_FW_UPGRADE_DISABLEVXGE_HW_FW_UPGRADE_DISABLE 0 vxge_main.h 　
7045
 VXGE_HW_FW_UPGRADE_ALLVXGE_HW_FW_UPGRADE_ALL 1 vxge_main.h 　
7046
 VXGE_HW_FW_UPGRADE_FORCEVXGE_HW_FW_UPGRADE_FORCE 2 vxge_main.h 　
7047
 VXGE_HW_FUNC_MODE_DISABLEVXGE_HW_FUNC_MODE_DISABLE 0 vxge_main.h 　
7048
 VXGE_TTI_BTIMER_VALVXGE_TTI_BTIMER_VAL 250000 vxge_main.h 　
7049
 VXGE_T1A_TTI_LTIMER_VALVXGE_T1A_TTI_LTIMER_VAL 80 vxge_main.h 　
7050
 VXGE_T1A_TTI_RTIMER_VALVXGE_T1A_TTI_RTIMER_VAL 400 vxge_main.h 　
7051
 VXGE_TTI_LTIMER_VALVXGE_TTI_LTIMER_VAL 1000 vxge_main.h 　
7052
 VXGE_TTI_RTIMER_VALVXGE_TTI_RTIMER_VAL 0 vxge_main.h 　
7053
 VXGE_RTI_BTIMER_VALVXGE_RTI_BTIMER_VAL 250 vxge_main.h 　
7054
 VXGE_RTI_LTIMER_VALVXGE_RTI_LTIMER_VAL 100 vxge_main.h 　
7055
 VXGE_RTI_RTIMER_VALVXGE_RTI_RTIMER_VAL 0 vxge_main.h 　
7056
 VXGE_FIFO_INDICATE_MAX_PKTSVXGE_FIFO_INDICATE_MAX_PKTS VXGE_DEF_FIFO_LENGTH vxge_main.h 　
7057
 VXGE_ISR_POLLING_CNTVXGE_ISR_POLLING_CNT 8 vxge_main.h 　
7058
 VXGE_MAX_CONFIG_DEVVXGE_MAX_CONFIG_DEV 0xFF vxge_main.h 　
7059
 VXGE_EXEC_MODE_DISABLEVXGE_EXEC_MODE_DISABLE 0 vxge_main.h 　
7060
 VXGE_EXEC_MODE_ENABLEVXGE_EXEC_MODE_ENABLE 1 vxge_main.h 　
7061
 VXGE_MAX_CONFIG_PORTVXGE_MAX_CONFIG_PORT 1 vxge_main.h 　
7062
 VXGE_ALL_VID_DISABLEVXGE_ALL_VID_DISABLE 0 vxge_main.h 　
7063
 VXGE_ALL_VID_ENABLEVXGE_ALL_VID_ENABLE 1 vxge_main.h 　
7064
 VXGE_PAUSE_CTRL_DISABLEVXGE_PAUSE_CTRL_DISABLE 0 vxge_main.h 　
7065
 VXGE_PAUSE_CTRL_ENABLEVXGE_PAUSE_CTRL_ENABLE 1 vxge_main.h 　
7066
 TTI_TX_URANGE_ATTI_TX_URANGE_A 5 vxge_main.h 　
7067
 TTI_TX_URANGE_BTTI_TX_URANGE_B 15 vxge_main.h 　
7068
 TTI_TX_URANGE_CTTI_TX_URANGE_C 40 vxge_main.h 　
7069
 TTI_TX_UFC_ATTI_TX_UFC_A 5 vxge_main.h 　
7070
 TTI_TX_UFC_BTTI_TX_UFC_B 40 vxge_main.h 　
7071
 TTI_TX_UFC_CTTI_TX_UFC_C 60 vxge_main.h 　
7072
 TTI_TX_UFC_DTTI_TX_UFC_D 100 vxge_main.h 　
7073
 TTI_T1A_TX_UFC_ATTI_T1A_TX_UFC_A 30 vxge_main.h 　
7074
 TTI_T1A_TX_UFC_BTTI_T1A_TX_UFC_B 80 vxge_main.h 　
7075
 RTI_RX_URANGE_ARTI_RX_URANGE_A 5 vxge_main.h 　
7076
 RTI_RX_URANGE_BRTI_RX_URANGE_B 15 vxge_main.h 　
7077
 RTI_RX_URANGE_CRTI_RX_URANGE_C 40 vxge_main.h 　
7078
 RTI_T1A_RX_URANGE_ARTI_T1A_RX_URANGE_A 1 vxge_main.h 　
7079
 RTI_T1A_RX_URANGE_BRTI_T1A_RX_URANGE_B 20 vxge_main.h 　
7080
 RTI_T1A_RX_URANGE_CRTI_T1A_RX_URANGE_C 50 vxge_main.h 　
7081
 RTI_RX_UFC_ARTI_RX_UFC_A 1 vxge_main.h 　
7082
 RTI_RX_UFC_BRTI_RX_UFC_B 5 vxge_main.h 　
7083
 RTI_RX_UFC_CRTI_RX_UFC_C 10 vxge_main.h 　
7084
 RTI_RX_UFC_DRTI_RX_UFC_D 15 vxge_main.h 　
7085
 RTI_T1A_RX_UFC_BRTI_T1A_RX_UFC_B 20 vxge_main.h 　
7086
 RTI_T1A_RX_UFC_CRTI_T1A_RX_UFC_C 50 vxge_main.h 　
7087
 RTI_T1A_RX_UFC_DRTI_T1A_RX_UFC_D 60 vxge_main.h 　
7088
 VXGE_T1A_MAX_INTERRUPT_COUNTVXGE_T1A_MAX_INTERRUPT_COUNT 100 vxge_main.h 　
7089
 VXGE_ENABLE_NAPIVXGE_ENABLE_NAPI 1 vxge_main.h 　
7090
 VXGE_DISABLE_NAPIVXGE_DISABLE_NAPI 0 vxge_main.h 　
7091
 VXGE_LRO_MAX_BYTESVXGE_LRO_MAX_BYTES 0x4000 vxge_main.h 　
7092
 VXGE_T1A_LRO_MAX_BYTESVXGE_T1A_LRO_MAX_BYTES 0xC000 vxge_main.h 　
7093
 VXGE_HW_MIN_VPATH_TX_BW_SUPPORTVXGE_HW_MIN_VPATH_TX_BW_SUPPORT 0 vxge_main.h 　
7094
 VXGE_HW_MAX_VPATH_TX_BW_SUPPORTVXGE_HW_MAX_VPATH_TX_BW_SUPPORT 7 vxge_main.h 　
7095
 VXGE_TIMER_DELAYVXGE_TIMER_DELAY 10000 vxge_main.h 　
7096
 VXGE_TIMER_COUNTVXGE_TIMER_COUNT (2 * 60) vxge_main.h 　
7097
 VXGE_REG_DUMP_BUFSIZEVXGE_REG_DUMP_BUFSIZE 65000 vxge_main.h 　
7098
 __VXGE_STATE_RESET_CARD__VXGE_STATE_RESET_CARD 0x01 vxge_main.h 　
7099
 __VXGE_STATE_CARD_UP__VXGE_STATE_CARD_UP 0x02 vxge_main.h 　
7100
 VXGE_HW_PF_SW_RESET_COMMANDVXGE_HW_PF_SW_RESET_COMMAND 0xA5 vxge_reg.h 　
7101
 VXGE_HW_TITAN_PCICFGMGMT_REG_SPVXGE_HW_TITAN_PCICFGMGMT_REG_SP 17 vxge_reg.h 　
7102
 VXGE_HW_TITAN_SRPCIM_REG_SPACESVXGE_HW_TITAN_SRPCIM_REG_SPACES 17 vxge_reg.h 　
7103
 VXGE_HW_TITAN_VPMGMT_REG_SPACESVXGE_HW_TITAN_VPMGMT_REG_SPACES 17 vxge_reg.h 　
7104
 VXGE_HW_TITAN_VPATH_REG_SPACESVXGE_HW_TITAN_VPATH_REG_SPACES 17 vxge_reg.h 　
7105
 VXGE_HW_PRIV_FN_ACTIONVXGE_HW_PRIV_FN_ACTION 8 vxge_reg.h 　
7106
 VXGE_HW_PRIV_VP_ACTIONVXGE_HW_PRIV_VP_ACTION 5 vxge_reg.h 　
7107
 VXGE_HW_PRIV_FN_MEMOVXGE_HW_PRIV_FN_MEMO 13 vxge_reg.h 　
7108
 VXGE_HW_EN_DIS_UDP_RTHVXGE_HW_EN_DIS_UDP_RTH 10 vxge_reg.h 　
7109
 VXGE_HW_BW_CONTROLVXGE_HW_BW_CONTROL 12 vxge_reg.h 　
7110
 VXGE_HW_RTS_ACCESS_FW_MEMO_ACTIVXGE_HW_RTS_ACCESS_FW_MEMO_ACTI 17 vxge_reg.h 　
7111
 VXGE_HW_FW_API_FUNC_MODEVXGE_HW_FW_API_FUNC_MODE 11 vxge_reg.h 　
7112
 VXGE_HW_FW_API_GET_FUNC_MODEVXGE_HW_FW_API_GET_FUNC_MODE 29 vxge_reg.h 　
7113
 VXGE_HW_FW_API_FUNC_MODE_COMMITVXGE_HW_FW_API_FUNC_MODE_COMMIT 21 vxge_reg.h 　
7114
 VXGE_HW_BYTES_PER_U64VXGE_HW_BYTES_PER_U64 8 vxge_reg.h 　
7115
 VXGE_HW_FW_UPGRADE_MEMOVXGE_HW_FW_UPGRADE_MEMO 13 vxge_reg.h 　
7116
 VXGE_HW_FW_UPGRADE_ACTIONVXGE_HW_FW_UPGRADE_ACTION 16 vxge_reg.h 　
7117
 VXGE_HW_FW_UPGRADE_OFFSET_STARTVXGE_HW_FW_UPGRADE_OFFSET_START 2 vxge_reg.h Start upgrade
7118
 VXGE_HW_FW_UPGRADE_OFFSET_SENDVXGE_HW_FW_UPGRADE_OFFSET_SEND 3 vxge_reg.h Send upgrade data
7119
 VXGE_HW_FW_UPGRADE_OFFSET_COMMIVXGE_HW_FW_UPGRADE_OFFSET_COMMI 4 vxge_reg.h Commit upgrade
7120
 VXGE_HW_FW_UPGRADE_OFFSET_READVXGE_HW_FW_UPGRADE_OFFSET_READ 5 vxge_reg.h Read upgrade version
7121
 VXGE_HW_FW_UPGRADE_BLK_SIZEVXGE_HW_FW_UPGRADE_BLK_SIZE 16 vxge_reg.h Bytes to write
7122
 VXGE_HW_ASIC_MODE_RESERVEDVXGE_HW_ASIC_MODE_RESERVED 0 vxge_reg.h 　
7123
 VXGE_HW_ASIC_MODE_NO_IOVVXGE_HW_ASIC_MODE_NO_IOV 1 vxge_reg.h 　
7124
 VXGE_HW_ASIC_MODE_SR_IOVVXGE_HW_ASIC_MODE_SR_IOV 2 vxge_reg.h 　
7125
 VXGE_HW_ASIC_MODE_MR_IOVVXGE_HW_ASIC_MODE_MR_IOV 3 vxge_reg.h 　
7126
 VXGE_HW_TXMAC_GEN_CFG1_TMAC_PERVXGE_HW_TXMAC_GEN_CFG1_TMAC_PER vxge_mBIT(3) vxge_reg.h 　
7127
 VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCVXGE_HW_TXMAC_GEN_CFG1_BLOCK_BC vxge_mBIT(19) vxge_reg.h 　
7128
 VXGE_HW_TXMAC_GEN_CFG1_BLOCK_BCVXGE_HW_TXMAC_GEN_CFG1_BLOCK_BC vxge_mBIT(23) vxge_reg.h 　
7129
 VXGE_HW_TXMAC_GEN_CFG1_HOST_APPVXGE_HW_TXMAC_GEN_CFG1_HOST_APP vxge_mBIT(31) vxge_reg.h 　
7130
 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MVXGE_HW_KDFC_TRPL_FIFO_0_CTRL_M 0 vxge_reg.h 　
7131
 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MVXGE_HW_KDFC_TRPL_FIFO_0_CTRL_M 1 vxge_reg.h 　
7132
 VXGE_HW_KDFC_TRPL_FIFO_0_CTRL_MVXGE_HW_KDFC_TRPL_FIFO_0_CTRL_M 2 vxge_reg.h 　
7133
 VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MVXGE_HW_KDFC_TRPL_FIFO_1_CTRL_M 0 vxge_reg.h 　
7134
 VXGE_HW_KDFC_TRPL_FIFO_1_CTRL_MVXGE_HW_KDFC_TRPL_FIFO_1_CTRL_M 1 vxge_reg.h 　
7135
 VXGE_HW_PRC_CFG4_RING_MODE_ONE_VXGE_HW_PRC_CFG4_RING_MODE_ONE_ 0 vxge_reg.h 　
7136
 VXGE_HW_PRC_CFG4_RING_MODE_THREVXGE_HW_PRC_CFG4_RING_MODE_THRE 1 vxge_reg.h 　
7137
 VXGE_HW_PRC_CFG4_RING_MODE_FIVEVXGE_HW_PRC_CFG4_RING_MODE_FIVE 2 vxge_reg.h 　
7138
 VXGE_HW_PRC_CFG7_SCATTER_MODE_AVXGE_HW_PRC_CFG7_SCATTER_MODE_A 0 vxge_reg.h 　
7139
 VXGE_HW_PRC_CFG7_SCATTER_MODE_BVXGE_HW_PRC_CFG7_SCATTER_MODE_B 2 vxge_reg.h 　
7140
 VXGE_HW_PRC_CFG7_SCATTER_MODE_CVXGE_HW_PRC_CFG7_SCATTER_MODE_C 1 vxge_reg.h 　
7141
 VXGE_HW_RTS_MGR_STEER_CTRL_WE_RVXGE_HW_RTS_MGR_STEER_CTRL_WE_R 0 vxge_reg.h 　
7142
 VXGE_HW_RTS_MGR_STEER_CTRL_WE_WVXGE_HW_RTS_MGR_STEER_CTRL_WE_W 1 vxge_reg.h 　
7143
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 0 vxge_reg.h 　
7144
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 1 vxge_reg.h 　
7145
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 2 vxge_reg.h 　
7146
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 3 vxge_reg.h 　
7147
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 4 vxge_reg.h 　
7148
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 5 vxge_reg.h 　
7149
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 6 vxge_reg.h 　
7150
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 7 vxge_reg.h 　
7151
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 8 vxge_reg.h 　
7152
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 9 vxge_reg.h 　
7153
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 10 vxge_reg.h 　
7154
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 11 vxge_reg.h 　
7155
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 12 vxge_reg.h 　
7156
 VXGE_HW_RTS_MGR_STEER_CTRL_DATAVXGE_HW_RTS_MGR_STEER_CTRL_DATA 13 vxge_reg.h 　
7157
 VXGE_HW_RTS_MGR_STEER_DATA1_DA_VXGE_HW_RTS_MGR_STEER_DATA1_DA_ vxge_mBIT(54) vxge_reg.h 　
7158
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 0 vxge_reg.h 　
7159
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 1 vxge_reg.h 　
7160
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 2 vxge_reg.h 　
7161
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 3 vxge_reg.h 　
7162
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 0 vxge_reg.h 　
7163
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 1 vxge_reg.h 　
7164
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 3 vxge_reg.h 　
7165
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 4 vxge_reg.h 　
7166
 VXGE_HW_RTS_ACCESS_STEER_CTRL_AVXGE_HW_RTS_ACCESS_STEER_CTRL_A 172 vxge_reg.h 　
7167
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 0 vxge_reg.h 　
7168
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 1 vxge_reg.h 　
7169
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 2 vxge_reg.h 　
7170
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 3 vxge_reg.h 　
7171
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 5 vxge_reg.h 　
7172
 VXGE_HW_RTS_ACS_STEER_CTRL_DATAVXGE_HW_RTS_ACS_STEER_CTRL_DATA 6 vxge_reg.h 　
7173
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 7 vxge_reg.h 　
7174
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 8 vxge_reg.h 　
7175
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 9 vxge_reg.h 　
7176
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 10 vxge_reg.h 　
7177
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 11 vxge_reg.h 　
7178
 VXGE_HW_RTS_ACS_STEER_CTRL_DATAVXGE_HW_RTS_ACS_STEER_CTRL_DATA 12 vxge_reg.h 　
7179
 VXGE_HW_RTS_ACCESS_STEER_CTRL_DVXGE_HW_RTS_ACCESS_STEER_CTRL_D 13 vxge_reg.h 　
7180
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(51) vxge_reg.h 　
7181
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(3) vxge_reg.h 　
7182
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(7) vxge_reg.h 　
7183
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(3) vxge_reg.h 　
7184
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 0 vxge_reg.h 　
7185
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 1 vxge_reg.h 　
7186
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 2 vxge_reg.h 　
7187
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(15) vxge_reg.h 　
7188
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(19) vxge_reg.h 　
7189
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(23) vxge_reg.h 　
7190
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(27) vxge_reg.h 　
7191
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(31) vxge_reg.h 　
7192
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(35) vxge_reg.h 　
7193
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(39) vxge_reg.h 　
7194
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(43) vxge_reg.h 　
7195
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(3) vxge_reg.h 　
7196
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(8) vxge_reg.h 　
7197
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(24) vxge_reg.h 　
7198
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_mBIT(8) vxge_reg.h 　
7199
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_mBIT(24) vxge_reg.h 　
7200
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_vBIT(val, 0, 64) vxge_reg.h 　
7201
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(3) vxge_reg.h 　
7202
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_mBIT(3) vxge_reg.h 　
7203
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_mBIT(8) vxge_reg.h 　
7204
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_mBIT(24) vxge_reg.h 　
7205
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_mBIT(40) vxge_reg.h 　
7206
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_mBIT(56) vxge_reg.h 　
7207
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 0 vxge_reg.h 　
7208
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 1 vxge_reg.h 　
7209
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 2 vxge_reg.h 　
7210
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 3 vxge_reg.h 　
7211
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 4 vxge_reg.h 　
7212
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 5 vxge_reg.h 　
7213
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 6 vxge_reg.h 　
7214
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 7 vxge_reg.h 　
7215
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 8 vxge_reg.h 　
7216
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 10 vxge_reg.h 　
7217
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 11 vxge_reg.h 　
7218
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 13 vxge_reg.h 　
7219
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 14 vxge_reg.h 　
7220
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 20 vxge_reg.h 　
7221
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 21 vxge_reg.h 　
7222
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 23 vxge_reg.h 　
7223
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 24 vxge_reg.h 　
7224
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 1 vxge_reg.h 　
7225
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ 0 vxge_reg.h 　
7226
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_vBIT(val, 32, 8) vxge_reg.h 　
7227
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_vBIT(val, 40, 8) vxge_reg.h 　
7228
 VXGE_HW_RTS_ACCESS_STEER_DATA0_VXGE_HW_RTS_ACCESS_STEER_DATA0_ vxge_vBIT(val, 48, 16) vxge_reg.h 　
7229
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_vBIT(val, 32, 8) vxge_reg.h 　
7230
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_vBIT(val, 40, 8) vxge_reg.h 　
7231
 VXGE_HW_RTS_ACCESS_STEER_DATA1_VXGE_HW_RTS_ACCESS_STEER_DATA1_ vxge_vBIT(val, 48, 16) vxge_reg.h 　
7232
 \\ VXGE_HW_MRPCIM_DEBUG_STATS3_GET_VPLANE_RDCRDTARB_NPH_CRDT_DEPLETED(bits) \ vxge_bVALn(bits, 32, 32) vxge_reg.h 　
7233
 VXGE_HW_SWAPPER_INITIAL_VALUEVXGE_HW_SWAPPER_INITIAL_VALUE 0x0123456789abcdefULL vxge_reg.h 　
7234
 VXGE_HW_SWAPPER_BYTE_SWAPPEDVXGE_HW_SWAPPER_BYTE_SWAPPED 0xefcdab8967452301ULL vxge_reg.h 　
7235
 VXGE_HW_SWAPPER_BIT_FLIPPEDVXGE_HW_SWAPPER_BIT_FLIPPED 0x80c4a2e691d5b3f7ULL vxge_reg.h 　
7236
 VXGE_HW_SWAPPER_BYTE_SWAPPED_BIVXGE_HW_SWAPPER_BYTE_SWAPPED_BI 0xf7b3d591e6a2c480ULL vxge_reg.h 　
7237
 VXGE_HW_SWAPPER_READ_BYTE_SWAP_VXGE_HW_SWAPPER_READ_BYTE_SWAP_ 0xFFFFFFFFFFFFFFFFULL vxge_reg.h 　
7238
 VXGE_HW_SWAPPER_READ_BYTE_SWAP_VXGE_HW_SWAPPER_READ_BYTE_SWAP_ 0x0000000000000000ULL vxge_reg.h 　
7239
 VXGE_HW_SWAPPER_READ_BIT_FLAP_EVXGE_HW_SWAPPER_READ_BIT_FLAP_E 0xFFFFFFFFFFFFFFFFULL vxge_reg.h 　
7240
 VXGE_HW_SWAPPER_READ_BIT_FLAP_DVXGE_HW_SWAPPER_READ_BIT_FLAP_D 0x0000000000000000ULL vxge_reg.h 　
7241
 VXGE_HW_SWAPPER_WRITE_BYTE_SWAPVXGE_HW_SWAPPER_WRITE_BYTE_SWAP 0xFFFFFFFFFFFFFFFFULL vxge_reg.h 　
7242
 VXGE_HW_SWAPPER_WRITE_BYTE_SWAPVXGE_HW_SWAPPER_WRITE_BYTE_SWAP 0x0000000000000000ULL vxge_reg.h 　
7243
 VXGE_HW_SWAPPER_WRITE_BIT_FLAP_VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ 0xFFFFFFFFFFFFFFFFULL vxge_reg.h 　
7244
 VXGE_HW_SWAPPER_WRITE_BIT_FLAP_VXGE_HW_SWAPPER_WRITE_BIT_FLAP_ 0x0000000000000000ULL vxge_reg.h 　
7245
 VXGE_HW_EEPROM_SIZEVXGE_HW_EEPROM_SIZE (0x01 << 11) vxge_reg.h 　
7246
 VXGE_HW_PCI_EXP_LNKCAP_LNK_SPEEVXGE_HW_PCI_EXP_LNKCAP_LNK_SPEE 0xf vxge_reg.h Supported Link speeds
7247
 VXGE_HW_PCI_EXP_LNKCAP_LNK_WIDTVXGE_HW_PCI_EXP_LNKCAP_LNK_WIDT 0x3f0 vxge_reg.h Supported Link speeds.
7248
 VXGE_HW_PCI_EXP_LNKCAP_LW_RESVXGE_HW_PCI_EXP_LNKCAP_LW_RES 0x0 vxge_reg.h Reserved.
7249
 VXGE_HW_DTR_MAX_T_CODEVXGE_HW_DTR_MAX_T_CODE 16 vxge_traffic.h 　
7250
 VXGE_HW_ALL_FOXESVXGE_HW_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL vxge_traffic.h 　
7251
 VXGE_HW_INTR_MASK_ALLVXGE_HW_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL vxge_traffic.h 　
7252
 VXGE_HW_MAX_VIRTUAL_PATHSVXGE_HW_MAX_VIRTUAL_PATHS 17 vxge_traffic.h 　
7253
 VXGE_HW_MAX_VIRTUAL_FUNCTIONSVXGE_HW_MAX_VIRTUAL_FUNCTIONS 8 vxge_traffic.h 　
7254
 VXGE_HW_MAC_MAX_MAC_PORT_IDVXGE_HW_MAC_MAX_MAC_PORT_ID 3 vxge_traffic.h 　
7255
 VXGE_HW_DEFAULT_32VXGE_HW_DEFAULT_32 0xffffffff vxge_traffic.h 　
7256
 VXGE_HW_HEADER_802_2_SIZEVXGE_HW_HEADER_802_2_SIZE 3 vxge_traffic.h 　
7257
 VXGE_HW_HEADER_SNAP_SIZEVXGE_HW_HEADER_SNAP_SIZE 5 vxge_traffic.h 　
7258
 VXGE_HW_HEADER_VLAN_SIZEVXGE_HW_HEADER_VLAN_SIZE 4 vxge_traffic.h 　
7259
 VXGE_HW_MAC_HEADER_MAX_SIZEVXGE_HW_MAC_HEADER_MAX_SIZE (ETH_HLEN + \ VXGE_HW_HEADER_802_2_SIZE + \ VXGE_HW_HEADER_VLAN_SIZE + \ VXGE_HW_HEADER_SNAP_SIZE) vxge_traffic.h 　
7260
 VXGE_HW_HEADER_ETHERNET_II_802_VXGE_HW_HEADER_ETHERNET_II_802_ 0x12 vxge_traffic.h 　
7261
 VXGE_HW_HEADER_802_2_SNAP_ALIGNVXGE_HW_HEADER_802_2_SNAP_ALIGN 2 vxge_traffic.h 　
7262
 VXGE_HW_HEADER_802_2_ALIGNVXGE_HW_HEADER_802_2_ALIGN 3 vxge_traffic.h 　
7263
 VXGE_HW_HEADER_SNAP_ALIGNVXGE_HW_HEADER_SNAP_ALIGN 1 vxge_traffic.h 　
7264
 VXGE_HW_L3_CKSUM_OKVXGE_HW_L3_CKSUM_OK 0xFFFF vxge_traffic.h 　
7265
 VXGE_HW_L4_CKSUM_OKVXGE_HW_L4_CKSUM_OK 0xFFFF vxge_traffic.h 　
7266
 TRUETRUE 1 vxge_traffic.h 　
7267
 FALSEFALSE 0 vxge_traffic.h 　
7268
 VXGE_HW_EVENT_BASEVXGE_HW_EVENT_BASE 0 vxge_traffic.h 　
7269
 VXGE_LL_EVENT_BASEVXGE_LL_EVENT_BASE 100 vxge_traffic.h 　
7270
 VXGE_HW_MAX_INTR_PER_VPVXGE_HW_MAX_INTR_PER_VP 4 vxge_traffic.h 　
7271
 VXGE_HW_VPATH_INTR_TXVXGE_HW_VPATH_INTR_TX 0 vxge_traffic.h 　
7272
 VXGE_HW_VPATH_INTR_RXVXGE_HW_VPATH_INTR_RX 1 vxge_traffic.h 　
7273
 VXGE_HW_VPATH_INTR_EINTAVXGE_HW_VPATH_INTR_EINTA 2 vxge_traffic.h 　
7274
 VXGE_HW_VPATH_INTR_BMAPVXGE_HW_VPATH_INTR_BMAP 3 vxge_traffic.h 　
7275
 VXGE_HW_BLOCK_SIZEVXGE_HW_BLOCK_SIZE 4096 vxge_traffic.h 　
7276
 VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_ 17 vxge_traffic.h 　
7277
 VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_VXGE_HW_TIM_UTIL_SEL_LEGACY_RX_ 18 vxge_traffic.h 　
7278
 VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_VXGE_HW_TIM_UTIL_SEL_LEGACY_TX_ 19 vxge_traffic.h 　
7279
 VXGE_HW_TIM_UTIL_SEL_PER_VPATHVXGE_HW_TIM_UTIL_SEL_PER_VPATH 63 vxge_traffic.h 　
7280
 VXGE_VERSION_MAJORVXGE_VERSION_MAJOR 3 vxge_version.h 　
7281
 VXGE_VERSION_MINORVXGE_VERSION_MINOR 1 vxge_version.h 　
7282
 VXGE_VERSION_FIXVXGE_VERSION_FIX 0 vxge_version.h 　
7283
 VXGE_VERSION_BUILDVXGE_VERSION_BUILD 0 vxge_version.h 　
7284
 VXGE_CERT_FW_VER_MAJORVXGE_CERT_FW_VER_MAJOR 1 vxge_version.h 　
7285
 VXGE_CERT_FW_VER_MINORVXGE_CERT_FW_VER_MINOR 6 vxge_version.h 　
7286
 VXGE_CERT_FW_VER_BUILDVXGE_CERT_FW_VER_BUILD 0 vxge_version.h 　
7287
 VXGE_CERT_FW_VERVXGE_CERT_FW_VER VXGE_FW_VER(VXGE_CERT_FW_VER_MAJOR, \ VXGE_CERT_FW_VER_MINOR, VXGE_CERT_FW_VER_BUILD) vxge_version.h 　
7288
 READLINE_MAXREADLINE_MAX 256 readline.c 　
7289
 ERRFILEERRFILE 0 strerror.c 　
7290
 ERRFILEERRFILE ERRFILE_net80211 wireless_errors.c 　
7291
 INPUT_DELAYINPUT_DELAY 200 kb.c half-blocking delay timer resolution (ms)
7292
 INPUT_DELAY_TIMEOUTINPUT_DELAY_TIMEOUT 1000 kb.c half-blocking delay timeout
7293
 MIN_SPACE_SIZEMIN_SPACE_SIZE 2 slk.c 　
7294
 SLK_MAX_LABEL_LENSLK_MAX_LABEL_LEN 8 slk.c 　
7295
 SLK_MAX_NUM_LABELSSLK_MAX_NUM_LABELS 12 slk.c 　
7296
 SLK_MAX_NUM_SPACESSLK_MAX_NUM_SPACES 2 slk.c 　
7297
 WRAPWRAP 0 mucurses.h 　
7298
 NOWRAPNOWRAP 1 mucurses.h 　
7299
 EDITBOX_MIN_CHARSEDITBOX_MIN_CHARS 3 editbox.c 　
7300
 CPAIR_NORMALCPAIR_NORMAL 1 login_ui.c 　
7301
 CPAIR_LABELCPAIR_LABEL 2 login_ui.c 　
7302
 CPAIR_EDITBOXCPAIR_EDITBOX 3 login_ui.c 　
7303
 USERNAME_LABEL_ROWUSERNAME_LABEL_ROW 8 login_ui.c 　
7304
 USERNAME_ROWUSERNAME_ROW 10 login_ui.c 　
7305
 PASSWORD_LABEL_ROWPASSWORD_LABEL_ROW 14 login_ui.c 　
7306
 PASSWORD_ROWPASSWORD_ROW 16 login_ui.c 　
7307
 LABEL_COLLABEL_COL 36 login_ui.c 　
7308
 EDITBOX_COLEDITBOX_COL 30 login_ui.c 　
7309
 EDITBOX_WIDTHEDITBOX_WIDTH 20 login_ui.c 　
7310
 CPAIR_NORMALCPAIR_NORMAL 1 settings_ui.c 　
7311
 CPAIR_SELECTCPAIR_SELECT 2 settings_ui.c 　
7312
 CPAIR_EDITCPAIR_EDIT 3 settings_ui.c 　
7313
 CPAIR_ALERTCPAIR_ALERT 4 settings_ui.c 　
7314
 TITLE_ROWTITLE_ROW 1 settings_ui.c 　
7315
 SETTINGS_LIST_ROWSETTINGS_LIST_ROW 3 settings_ui.c 　
7316
 SETTINGS_LIST_COLSETTINGS_LIST_COL 1 settings_ui.c 　
7317
 INFO_ROWINFO_ROW 20 settings_ui.c 　
7318
 ALERT_ROWALERT_ROW 20 settings_ui.c 　
7319
 INSTRUCTION_ROWINSTRUCTION_ROW 22 settings_ui.c 　
7320
 INSTRUCTION_PADINSTRUCTION_PAD " " settings_ui.c 　
7321
 NUM_SETTINGSNUM_SETTINGS table_num_entries ( SETTINGS ) settings_ui.c 　
7322
 ASSERTINGASSERTING 0 assert.h 　
7323
 ASSERTINGASSERTING 1 assert.h 　
7324
 NON_STANDARD_BOOTP_SERVERNON_STANDARD_BOOTP_SERVER 1067 bootp.h 　
7325
 NON_STANDARD_BOOTP_CLIENTNON_STANDARD_BOOTP_CLIENT 1068 bootp.h 　
7326
 BOOTP_SERVERBOOTP_SERVER NON_STANDARD_BOOTP_SERVER bootp.h 　
7327
 BOOTP_SERVERBOOTP_SERVER 67 bootp.h 　
7328
 BOOTP_CLIENTBOOTP_CLIENT NON_STANDARD_BOOTP_CLIENT bootp.h 　
7329
 BOOTP_CLIENTBOOTP_CLIENT 68 bootp.h 　
7330
 PROXYDHCP_SERVERPROXYDHCP_SERVER 4011 bootp.h For PXE
7331
 BOOTP_REQUESTBOOTP_REQUEST 1 bootp.h 　
7332
 BOOTP_REPLYBOOTP_REPLY 2 bootp.h 　
7333
 RFC1533_COOKIERFC1533_COOKIE 99, 130, 83, 99 bootp.h 　
7334
 RFC1533_PADRFC1533_PAD 0 bootp.h 　
7335
 RFC1533_NETMASKRFC1533_NETMASK 1 bootp.h 　
7336
 RFC1533_TIMEOFFSETRFC1533_TIMEOFFSET 2 bootp.h 　
7337
 RFC1533_GATEWAYRFC1533_GATEWAY 3 bootp.h 　
7338
 RFC1533_TIMESERVERRFC1533_TIMESERVER 4 bootp.h 　
7339
 RFC1533_IEN116NSRFC1533_IEN116NS 5 bootp.h 　
7340
 RFC1533_DNSRFC1533_DNS 6 bootp.h 　
7341
 RFC1533_LOGSERVERRFC1533_LOGSERVER 7 bootp.h 　
7342
 RFC1533_COOKIESERVERRFC1533_COOKIESERVER 8 bootp.h 　
7343
 RFC1533_LPRSERVERRFC1533_LPRSERVER 9 bootp.h 　
7344
 RFC1533_IMPRESSSERVERRFC1533_IMPRESSSERVER 10 bootp.h 　
7345
 RFC1533_RESOURCESERVERRFC1533_RESOURCESERVER 11 bootp.h 　
7346
 RFC1533_HOSTNAMERFC1533_HOSTNAME 12 bootp.h 　
7347
 RFC1533_BOOTFILESIZERFC1533_BOOTFILESIZE 13 bootp.h 　
7348
 RFC1533_MERITDUMPFILERFC1533_MERITDUMPFILE 14 bootp.h 　
7349
 RFC1533_DOMAINNAMERFC1533_DOMAINNAME 15 bootp.h 　
7350
 RFC1533_SWAPSERVERRFC1533_SWAPSERVER 16 bootp.h 　
7351
 RFC1533_ROOTPATHRFC1533_ROOTPATH 17 bootp.h 　
7352
 RFC1533_EXTENSIONPATHRFC1533_EXTENSIONPATH 18 bootp.h 　
7353
 RFC1533_IPFORWARDINGRFC1533_IPFORWARDING 19 bootp.h 　
7354
 RFC1533_IPSOURCEROUTINGRFC1533_IPSOURCEROUTING 20 bootp.h 　
7355
 RFC1533_IPPOLICYFILTERRFC1533_IPPOLICYFILTER 21 bootp.h 　
7356
 RFC1533_IPMAXREASSEMBLYRFC1533_IPMAXREASSEMBLY 22 bootp.h 　
7357
 RFC1533_IPTTLRFC1533_IPTTL 23 bootp.h 　
7358
 RFC1533_IPMTURFC1533_IPMTU 24 bootp.h 　
7359
 RFC1533_IPMTUPLATEAURFC1533_IPMTUPLATEAU 25 bootp.h 　
7360
 RFC1533_INTMTURFC1533_INTMTU 26 bootp.h 　
7361
 RFC1533_INTLOCALSUBNETSRFC1533_INTLOCALSUBNETS 27 bootp.h 　
7362
 RFC1533_INTBROADCASTRFC1533_INTBROADCAST 28 bootp.h 　
7363
 RFC1533_INTICMPDISCOVERRFC1533_INTICMPDISCOVER 29 bootp.h 　
7364
 RFC1533_INTICMPRESPONDRFC1533_INTICMPRESPOND 30 bootp.h 　
7365
 RFC1533_INTROUTEDISCOVERRFC1533_INTROUTEDISCOVER 31 bootp.h 　
7366
 RFC1533_INTROUTESOLICITRFC1533_INTROUTESOLICIT 32 bootp.h 　
7367
 RFC1533_INTSTATICROUTESRFC1533_INTSTATICROUTES 33 bootp.h 　
7368
 RFC1533_LLTRAILERENCAPRFC1533_LLTRAILERENCAP 34 bootp.h 　
7369
 RFC1533_LLARPCACHETMORFC1533_LLARPCACHETMO 35 bootp.h 　
7370
 RFC1533_LLETHERNETENCAPRFC1533_LLETHERNETENCAP 36 bootp.h 　
7371
 RFC1533_TCPTTLRFC1533_TCPTTL 37 bootp.h 　
7372
 RFC1533_TCPKEEPALIVETMORFC1533_TCPKEEPALIVETMO 38 bootp.h 　
7373
 RFC1533_TCPKEEPALIVEGBRFC1533_TCPKEEPALIVEGB 39 bootp.h 　
7374
 RFC1533_NISDOMAINRFC1533_NISDOMAIN 40 bootp.h 　
7375
 RFC1533_NISSERVERRFC1533_NISSERVER 41 bootp.h 　
7376
 RFC1533_NTPSERVERRFC1533_NTPSERVER 42 bootp.h 　
7377
 RFC1533_VENDORRFC1533_VENDOR 43 bootp.h 　
7378
 RFC1533_NBNSRFC1533_NBNS 44 bootp.h 　
7379
 RFC1533_NBDDRFC1533_NBDD 45 bootp.h 　
7380
 RFC1533_NBNTRFC1533_NBNT 46 bootp.h 　
7381
 RFC1533_NBSCOPERFC1533_NBSCOPE 47 bootp.h 　
7382
 RFC1533_XFSRFC1533_XFS 48 bootp.h 　
7383
 RFC1533_XDMRFC1533_XDM 49 bootp.h 　
7384
 RFC2132_REQ_ADDRRFC2132_REQ_ADDR 50 bootp.h 　
7385
 RFC2132_MSG_TYPERFC2132_MSG_TYPE 53 bootp.h 　
7386
 RFC2132_SRV_IDRFC2132_SRV_ID 54 bootp.h 　
7387
 RFC2132_PARAM_LISTRFC2132_PARAM_LIST 55 bootp.h 　
7388
 RFC2132_MAX_SIZERFC2132_MAX_SIZE 57 bootp.h 　
7389
 RFC2132_VENDOR_CLASS_IDRFC2132_VENDOR_CLASS_ID 60 bootp.h 　
7390
 RFC2132_CLIENT_IDRFC2132_CLIENT_ID 61 bootp.h 　
7391
 RFC2132_TFTP_SERVER_NAMERFC2132_TFTP_SERVER_NAME 66 bootp.h 　
7392
 RFC2132_BOOTFILE_NAMERFC2132_BOOTFILE_NAME 67 bootp.h 　
7393
 RFC3004_USER_CLASSRFC3004_USER_CLASS 77 bootp.h 　
7394
 RFC3679_PXE_CLIENT_ARCHRFC3679_PXE_CLIENT_ARCH 93 bootp.h 　
7395
 RFC3679_PXE_CLIENT_NDIRFC3679_PXE_CLIENT_NDI 94 bootp.h 　
7396
 RFC3679_PXE_CLIENT_UUIDRFC3679_PXE_CLIENT_UUID 97 bootp.h 　
7397
 RFC3679_PXE_CLIENT_ARCH_LENGTHRFC3679_PXE_CLIENT_ARCH_LENGTH 2 bootp.h 　
7398
 RFC3679_PXE_CLIENT_NDI_LENGTHRFC3679_PXE_CLIENT_NDI_LENGTH 3 bootp.h 　
7399
 RFC3679_PXE_CLIENT_UUID_LENGTHRFC3679_PXE_CLIENT_UUID_LENGTH 17 bootp.h 　
7400
 RFC3679_PXE_CLIENT_ARCH_IAX86PCRFC3679_PXE_CLIENT_ARCH_IAX86PC 0,0 bootp.h 　
7401
 RFC3679_PXE_CLIENT_ARCH_NECPC98RFC3679_PXE_CLIENT_ARCH_NECPC98 0,1 bootp.h 　
7402
 RFC3679_PXE_CLIENT_ARCH_IA64PCRFC3679_PXE_CLIENT_ARCH_IA64PC 0,2 bootp.h 　
7403
 RFC3679_PXE_CLIENT_ARCH_DECALPHRFC3679_PXE_CLIENT_ARCH_DECALPH 0,3 bootp.h 　
7404
 RFC3679_PXE_CLIENT_ARCH_ARCX86RFC3679_PXE_CLIENT_ARCH_ARCX86 0,4 bootp.h 　
7405
 RFC3679_PXE_CLIENT_ARCH_INTELLERFC3679_PXE_CLIENT_ARCH_INTELLE 0,5 bootp.h 　
7406
 RFC3679_PXE_CLIENT_NDI_21RFC3679_PXE_CLIENT_NDI_21 1,2,1 bootp.h 　
7407
 RFC3679_PXE_CLIENT_UUID_TYPERFC3679_PXE_CLIENT_UUID_TYPE 0 bootp.h 　
7408
 RFC3679_PXE_CLIENT_UUID_DEFAULTRFC3679_PXE_CLIENT_UUID_DEFAULT RFC3679_PXE_CLIENT_UUID_TYPE, \ 0xDE,0xAD,0xBE,0xEF, \ 0xDE,0xAD,0xBE,0xEF, \ 0xDE,0xAD,0xBE,0xEF, \ 0xDE,0xAD,0xBE,0xEF bootp.h 　
7409
 RFC2132_VENDOR_CLASS_ID_PXE_LENRFC2132_VENDOR_CLASS_ID_PXE_LEN 32 bootp.h 　
7410
 RFC2132_VENDOR_CLASS_ID_PXERFC2132_VENDOR_CLASS_ID_PXE 'P','X','E','C','l','i','e','n','t',':', \ 'A','r','c','h',':','0','0','0','0','0',':', \ 'U','N','D','I',':','0','0','2','0' bootp.h 　
7411
 RFC1533_VENDOR_PXE_OPT128RFC1533_VENDOR_PXE_OPT128 128 bootp.h 　
7412
 RFC1533_VENDOR_PXE_OPT129RFC1533_VENDOR_PXE_OPT129 129 bootp.h 　
7413
 RFC1533_VENDOR_PXE_OPT130RFC1533_VENDOR_PXE_OPT130 130 bootp.h 　
7414
 RFC1533_VENDOR_PXE_OPT131RFC1533_VENDOR_PXE_OPT131 131 bootp.h 　
7415
 RFC1533_VENDOR_PXE_OPT132RFC1533_VENDOR_PXE_OPT132 132 bootp.h 　
7416
 RFC1533_VENDOR_PXE_OPT133RFC1533_VENDOR_PXE_OPT133 133 bootp.h 　
7417
 RFC1533_VENDOR_PXE_OPT134RFC1533_VENDOR_PXE_OPT134 134 bootp.h 　
7418
 RFC1533_VENDOR_PXE_OPT135RFC1533_VENDOR_PXE_OPT135 135 bootp.h 　
7419
 DHCPDISCOVERDHCPDISCOVER 1 bootp.h 　
7420
 DHCPOFFERDHCPOFFER 2 bootp.h 　
7421
 DHCPREQUESTDHCPREQUEST 3 bootp.h 　
7422
 DHCPACKDHCPACK 5 bootp.h 　
7423
 RFC1533_VENDOR_MAJORRFC1533_VENDOR_MAJOR 0 bootp.h 　
7424
 RFC1533_VENDOR_MINORRFC1533_VENDOR_MINOR 0 bootp.h 　
7425
 RFC1533_VENDOR_MAGICRFC1533_VENDOR_MAGIC 128 bootp.h 　
7426
 RFC1533_VENDOR_ADDPARMRFC1533_VENDOR_ADDPARM 129 bootp.h 　
7427
 RFC1533_VENDOR_ETHDEVRFC1533_VENDOR_ETHDEV 130 bootp.h 　
7428
 RFC1533_VENDOR_ETHERBOOT_ENCAPRFC1533_VENDOR_ETHERBOOT_ENCAP 150 bootp.h 　
7429
 RFC1533_VENDOR_HOWTORFC1533_VENDOR_HOWTO 132 bootp.h 　
7430
 RFC1533_VENDOR_KERNEL_ENVRFC1533_VENDOR_KERNEL_ENV 133 bootp.h 　
7431
 RFC1533_VENDOR_NIC_DEV_IDRFC1533_VENDOR_NIC_DEV_ID 175 bootp.h 　
7432
 RFC1533_VENDOR_ARCHRFC1533_VENDOR_ARCH 177 bootp.h 　
7433
 RFC1533_ENDRFC1533_END 255 bootp.h 　
7434
 BOOTP_VENDOR_LENBOOTP_VENDOR_LEN 64 bootp.h 　
7435
 DHCP_OPT_LENDHCP_OPT_LEN 312 bootp.h 　
7436
 u32u32 unsigned int btext.h 　
7437
 u16u16 unsigned short btext.h 　
7438
 u8u8 unsigned char btext.h 　
7439
 BOOTX_COLORTABLE_SIZEBOOTX_COLORTABLE_SIZE (256UL*3UL*2UL) btext.h 　
7440
 CMDL_BUFFER_SIZECMDL_BUFFER_SIZE 256 cmdlinelib.h 　
7441
 CMDL_PROMPT_SIZECMDL_PROMPT_SIZE 8 cmdlinelib.h 　
7442
 CMDL_MAX_TAB_COMPLETE_RESULTCMDL_MAX_TAB_COMPLETE_RESULT 256 cmdlinelib.h 　
7443
 NULLNULL ((void *)0) cmdlinelib.h 　
7444
 F_RELFLGF_RELFLG 0x0001 coff.h If set, not reloc. info. Clear for executables
7445
 F_EXECF_EXEC 0x0002 coff.h No unresolved symbols. Executable file !
7446
 F_LNNOF_LNNO 0x0004 coff.h If set, line information numbers removed
7447
 F_LSYMSF_LSYMS 0x0008 coff.h If set, local symbols removed
7448
 F_AR32WRF_AR32WR 0x0100 coff.h Indicates little endian file
7449
 EM_E1EM_E1 0x17a coff.h Magic number for Hyperstone. Big endian format
7450
 O_MAGICO_MAGIC 0x017c coff.h Optional's header magic number for Hyperstone
7451
 S_TYPE_TEXTS_TYPE_TEXT 0x0020 coff.h If set, the section contains only executable
7452
 S_TYPE_DATAS_TYPE_DATA 0x0040 coff.h If set, the section contains only initialized data
7453
 S_TYPE_BSSS_TYPE_BSS 0x0080 coff.h If set, the section is BSS no data stored
7454
 OBJECT_SYMBOLOBJECT_SYMBOL PREFIX_OBJECT ( obj_ ) compiler.h 　
7455
 CONFIG_SYMBOLCONFIG_SYMBOL PREFIX_OBJECT ( obj_config_ ) compiler.h 　
7456
 ERRFILEERRFILE PREFIX_OBJECT ( ERRFILE_ ) compiler.h 　
7457
 __weak__weak __attribute__ (( weak )) compiler.h 　
7458
 DEBUG_SYMBOLDEBUG_SYMBOL PREFIX_OBJECT ( debug_ ) compiler.h 　
7459
 DBGLVL_MAXDBGLVL_MAX DEBUG_SYMBOL compiler.h 　
7460
 DBGLVL_MAXDBGLVL_MAX 0 compiler.h 　
7461
 DBGLVLDBGLVL ( DBGLVL_MAX & ~__debug_disable ) compiler.h 　
7462
 DBGLVLDBGLVL 0 compiler.h 　
7463
 DBGLVL_LOGDBGLVL_LOG 1 compiler.h 　
7464
 DBG_LOGDBG_LOG ( DBGLVL & DBGLVL_LOG ) compiler.h 　
7465
 DBGLVL_EXTRADBGLVL_EXTRA 2 compiler.h 　
7466
 DBG_EXTRADBG_EXTRA ( DBGLVL & DBGLVL_EXTRA ) compiler.h 　
7467
 DBGLVL_PROFILEDBGLVL_PROFILE 4 compiler.h 　
7468
 DBG_PROFILEDBG_PROFILE ( DBGLVL & DBGLVL_PROFILE ) compiler.h 　
7469
 DBGLVL_IODBGLVL_IO 8 compiler.h 　
7470
 DBG_IODBG_IO ( DBGLVL & DBGLVL_IO ) compiler.h 　
7471
 PACKEDPACKED __attribute__ (( packed )) compiler.h 　
7472
 __unused__unused __attribute__ (( unused )) compiler.h 　
7473
 __pure__pure __attribute__ (( pure )) compiler.h 　
7474
 __const__const __attribute__ (( const )) compiler.h 　
7475
 __nonnull__nonnull __attribute__ (( nonnull )) compiler.h 　
7476
 __malloc__malloc __attribute__ (( malloc )) compiler.h 　
7477
 __used__used __attribute__ (( used )) compiler.h 　
7478
 __aligned__aligned __attribute__ (( aligned ( 16 ) )) compiler.h 　
7479
 __always_inline__always_inline __attribute__ (( always_inline )) compiler.h 　
7480
 __shared__shared __asm__ ( "_shared_bss" ) __aligned compiler.h 　
7481
 FILE_LICENCE_PUBLIC_DOMAINFILE_LICENCE_PUBLIC_DOMAIN PROVIDE_SYMBOL ( __licence_public_domain ) compiler.h 　
7482
 FILE_LICENCE_GPL2_OR_LATERFILE_LICENCE_GPL2_OR_LATER PROVIDE_SYMBOL ( __licence_gpl2_or_later ) compiler.h 　
7483
 FILE_LICENCE_GPL2_ONLYFILE_LICENCE_GPL2_ONLY PROVIDE_SYMBOL ( __licence_gpl2_only ) compiler.h 　
7484
 FILE_LICENCE_GPL_ANYFILE_LICENCE_GPL_ANY PROVIDE_SYMBOL ( __licence_gpl_any ) compiler.h 　
7485
 FILE_LICENCE_BSD3FILE_LICENCE_BSD3 PROVIDE_SYMBOL ( __licence_bsd3 ) compiler.h 　
7486
 FILE_LICENCE_BSD2FILE_LICENCE_BSD2 PROVIDE_SYMBOL ( __licence_bsd2 ) compiler.h 　
7487
 FILE_LICENCE_MITFILE_LICENCE_MIT PROVIDE_SYMBOL ( __licence_mit ) compiler.h 　
7488
 CONSOLESCONSOLES __table ( struct console_driver, "consoles" ) console.h 　
7489
 __console_driver__console_driver __table_entry ( CONSOLES, 01 ) console.h 　
7490
 ERRERR (-1) curses.h 　
7491
 FALSEFALSE (0) curses.h 　
7492
 OKOK (0) curses.h 　
7493
 TRUETRUE (1) curses.h 　
7494
 stdscrstdscr ( &_stdscr ) curses.h 　
7495
 COLSCOLS _COLS curses.h 　
7496
 LINESLINES _LINES curses.h 　
7497
 CPAIR_SHIFTCPAIR_SHIFT 8 curses.h 　
7498
 ATTRS_SHIFTATTRS_SHIFT 16 curses.h 　
7499
 WA_DEFAULTWA_DEFAULT ( 0x0000 << ATTRS_SHIFT ) curses.h 　
7500
 WA_ALTCHARSETWA_ALTCHARSET ( 0x0001 << ATTRS_SHIFT ) curses.h 　
7501
 WA_BLINKWA_BLINK ( 0x0002 << ATTRS_SHIFT ) curses.h 　
7502
 WA_BOLDWA_BOLD ( 0x0004 << ATTRS_SHIFT ) curses.h 　
7503
 WA_DIMWA_DIM ( 0x0008 << ATTRS_SHIFT ) curses.h 　
7504
 WA_INVISWA_INVIS ( 0x0010 << ATTRS_SHIFT ) curses.h 　
7505
 WA_PROTECTWA_PROTECT ( 0x0020 << ATTRS_SHIFT ) curses.h 　
7506
 WA_REVERSEWA_REVERSE ( 0x0040 << ATTRS_SHIFT ) curses.h 　
7507
 WA_STANDOUTWA_STANDOUT ( 0x0080 << ATTRS_SHIFT ) curses.h 　
7508
 WA_UNDERLINEWA_UNDERLINE ( 0x0100 << ATTRS_SHIFT ) curses.h 　
7509
 WA_HORIZONTALWA_HORIZONTAL ( 0x0200 << ATTRS_SHIFT ) curses.h 　
7510
 WA_VERTICALWA_VERTICAL ( 0x0400 << ATTRS_SHIFT ) curses.h 　
7511
 WA_LEFTWA_LEFT ( 0x0800 << ATTRS_SHIFT ) curses.h 　
7512
 WA_RIGHTWA_RIGHT ( 0x1000 << ATTRS_SHIFT ) curses.h 　
7513
 WA_LOWWA_LOW ( 0x2000 << ATTRS_SHIFT ) curses.h 　
7514
 WA_TOPWA_TOP ( 0x4000 << ATTRS_SHIFT ) curses.h 　
7515
 A_DEFAULTA_DEFAULT WA_DEFAULT curses.h 　
7516
 A_ALTCHARSETA_ALTCHARSET WA_ALTCHARSET curses.h 　
7517
 A_BLINKA_BLINK WA_BLINK curses.h 　
7518
 A_BOLDA_BOLD WA_BOLD curses.h 　
7519
 A_DIMA_DIM WA_DIM curses.h 　
7520
 A_INVISA_INVIS WA_INVIS curses.h 　
7521
 A_PROTECTA_PROTECT WA_PROTECT curses.h 　
7522
 A_REVERSEA_REVERSE WA_REVERSE curses.h 　
7523
 A_STANDOUTA_STANDOUT WA_STANDOUT curses.h 　
7524
 A_UNDERLINEA_UNDERLINE WA_UNDERLINE curses.h 　
7525
 A_ATTRIBUTESA_ATTRIBUTES ( 0xffff << ATTRS_SHIFT ) curses.h 　
7526
 A_CHARTEXTA_CHARTEXT ( 0xff ) curses.h 　
7527
 A_COLOURA_COLOUR ( 0xff << CPAIR_SHIFT ) curses.h 　
7528
 A_COLORA_COLOR A_COLOUR curses.h 　
7529
 COLOUR_PAIRSCOLOUR_PAIRS 8 curses.h Arbitrary limit
7530
 COLOR_PAIRSCOLOR_PAIRS COLOUR_PAIRS curses.h 　
7531
 ACS_ULCORNERACS_ULCORNER '+' curses.h 　
7532
 ACS_LLCORNERACS_LLCORNER '+' curses.h 　
7533
 ACS_URCORNERACS_URCORNER '+' curses.h 　
7534
 ACS_LRCORNERACS_LRCORNER '+' curses.h 　
7535
 ACS_RTEEACS_RTEE '+' curses.h 　
7536
 ACS_LTEEACS_LTEE '+' curses.h 　
7537
 ACS_BTEEACS_BTEE '+' curses.h 　
7538
 ACS_TTEEACS_TTEE '+' curses.h 　
7539
 ACS_HLINEACS_HLINE '-' curses.h 　
7540
 ACS_VLINEACS_VLINE '|' curses.h 　
7541
 ACS_PLUSACS_PLUS '+' curses.h 　
7542
 ACS_S1ACS_S1 '-' curses.h 　
7543
 ACS_S9ACS_S9 '_' curses.h 　
7544
 ACS_DIAMONDACS_DIAMOND '+' curses.h 　
7545
 ACS_CKBOARDACS_CKBOARD ':' curses.h 　
7546
 ACS_DEGREEACS_DEGREE '\'' curses.h 　
7547
 ACS_PLMINUSACS_PLMINUS '#' curses.h 　
7548
 ACS_BULLETACS_BULLET 'o' curses.h 　
7549
 ACS_LARROWACS_LARROW '<' curses.h 　
7550
 ACS_RARROWACS_RARROW '>' curses.h 　
7551
 ACS_DARROWACS_DARROW 'v' curses.h 　
7552
 ACS_UARROWACS_UARROW '^' curses.h 　
7553
 ACS_BOARDACS_BOARD '#' curses.h 　
7554
 ACS_LANTERNACS_LANTERN '#' curses.h 　
7555
 ACS_BLOCKACS_BLOCK '#' curses.h 　
7556
 COLOUR_BLACKCOLOUR_BLACK 0 curses.h 　
7557
 COLOUR_REDCOLOUR_RED 1 curses.h 　
7558
 COLOUR_GREENCOLOUR_GREEN 2 curses.h 　
7559
 COLOUR_YELLOWCOLOUR_YELLOW 3 curses.h 　
7560
 COLOUR_BLUECOLOUR_BLUE 4 curses.h 　
7561
 COLOUR_MAGENTACOLOUR_MAGENTA 5 curses.h 　
7562
 COLOUR_CYANCOLOUR_CYAN 6 curses.h 　
7563
 COLOUR_WHITECOLOUR_WHITE 7 curses.h 　
7564
 COLOURSCOLOURS 7 curses.h 　
7565
 COLOUR_FGCOLOUR_FG 30 curses.h 　
7566
 COLOUR_BGCOLOUR_BG 40 curses.h 　
7567
 COLOR_FGCOLOR_FG COLOUR_FG curses.h 　
7568
 COLOR_BGCOLOR_BG COLOUR_BG curses.h 　
7569
 COLOR_BLACKCOLOR_BLACK COLOUR_BLACK curses.h 　
7570
 COLOR_BLUECOLOR_BLUE COLOUR_BLUE curses.h 　
7571
 COLOR_GREENCOLOR_GREEN COLOUR_GREEN curses.h 　
7572
 COLOR_CYANCOLOR_CYAN COLOUR_CYAN curses.h 　
7573
 COLOR_REDCOLOR_RED COLOUR_RED curses.h 　
7574
 COLOR_MAGENTACOLOR_MAGENTA COLOUR_MAGENTA curses.h 　
7575
 COLOR_YELLOWCOLOR_YELLOW COLOUR_YELLOW curses.h 　
7576
 COLOR_WHITECOLOR_WHITE COLOUR_WHITE curses.h 　
7577
 COLORSCOLORS COLOURS curses.h 　
7578
 init_colorinit_color ( c, r, g, b ) init_colour ( (c), (r), (g), (b) ) curses.h 　
7579
 EI_NIDENTEI_NIDENT 16 elf.h Size of e_ident array.
7580
 ET_NONEET_NONE 0 elf.h No file type
7581
 ET_RELET_REL 1 elf.h Relocatable file
7582
 ET_EXECET_EXEC 2 elf.h Executable file
7583
 ET_DYNET_DYN 3 elf.h Shared object file
7584
 ET_COREET_CORE 4 elf.h Core file
7585
 EM_NONEEM_NONE 0 elf.h No machine
7586
 EM_M32EM_M32 1 elf.h AT&T WE 32100
7587
 EM_SPARCEM_SPARC 2 elf.h SUN SPARC
7588
 EM_386EM_386 3 elf.h Intel 80386+
7589
 EM_68KEM_68K 4 elf.h Motorola m68k family
7590
 EM_88KEM_88K 5 elf.h Motorola m88k family
7591
 EM_486EM_486 6 elf.h Perhaps disused
7592
 EM_860EM_860 7 elf.h Intel 80860
7593
 EM_MIPSEM_MIPS 8 elf.h MIPS R3000 big-endian
7594
 EM_S370EM_S370 9 elf.h IBM System/370
7595
 EM_MIPS_RS3_LEEM_MIPS_RS3_LE 10 elf.h MIPS R3000 little-endian
7596
 EM_PARISCEM_PARISC 15 elf.h HPPA
7597
 EM_VPP500EM_VPP500 17 elf.h Fujitsu VPP500
7598
 EM_SPARC32PLUSEM_SPARC32PLUS 18 elf.h Sun's "v8plus"
7599
 EM_960EM_960 19 elf.h Intel 80960
7600
 EM_PPCEM_PPC 20 elf.h PowerPC
7601
 EM_PPC64EM_PPC64 21 elf.h PowerPC 64-bit
7602
 EM_S390EM_S390 22 elf.h IBM S390
7603
 EM_V800EM_V800 36 elf.h NEC V800 series
7604
 EM_FR20EM_FR20 37 elf.h Fujitsu FR20
7605
 EM_RH32EM_RH32 38 elf.h TRW RH-32
7606
 EM_RCEEM_RCE 39 elf.h Motorola RCE
7607
 EM_ARMEM_ARM 40 elf.h ARM
7608
 EM_FAKE_ALPHAEM_FAKE_ALPHA 41 elf.h Digital Alpha
7609
 EM_SHEM_SH 42 elf.h Hitachi SH
7610
 EM_SPARCV9EM_SPARCV9 43 elf.h SPARC v9 64-bit
7611
 EM_TRICOREEM_TRICORE 44 elf.h Siemens Tricore
7612
 EM_ARCEM_ARC 45 elf.h Argonaut RISC Core
7613
 EM_H8_300EM_H8_300 46 elf.h Hitachi H8/300
7614
 EM_H8_300HEM_H8_300H 47 elf.h Hitachi H8/300H
7615
 EM_H8SEM_H8S 48 elf.h Hitachi H8S
7616
 EM_H8_500EM_H8_500 49 elf.h Hitachi H8/500
7617
 EM_IA_64EM_IA_64 50 elf.h Intel Merced
7618
 EM_MIPS_XEM_MIPS_X 51 elf.h Stanford MIPS-X
7619
 EM_COLDFIREEM_COLDFIRE 52 elf.h Motorola Coldfire
7620
 EM_68HC12EM_68HC12 53 elf.h Motorola M68HC12
7621
 EM_MMAEM_MMA 54 elf.h Fujitsu MMA Multimedia Accelerator
7622
 EM_PCPEM_PCP 55 elf.h Siemens PCP
7623
 EM_NCPUEM_NCPU 56 elf.h Sony nCPU embeeded RISC
7624
 EM_NDR1EM_NDR1 57 elf.h Denso NDR1 microprocessor
7625
 EM_STARCOREEM_STARCORE 58 elf.h Motorola Start*Core processor
7626
 EM_ME16EM_ME16 59 elf.h Toyota ME16 processor
7627
 EM_ST100EM_ST100 60 elf.h STMicroelectronic ST100 processor
7628
 EM_TINYJEM_TINYJ 61 elf.h Advanced Logic Corp. Tinyj emb.fam
7629
 EM_X86_64EM_X86_64 62 elf.h AMD x86-64 architecture
7630
 EM_PDSPEM_PDSP 63 elf.h Sony DSP Processor
7631
 EM_FX66EM_FX66 66 elf.h Siemens FX66 microcontroller
7632
 EM_ST9PLUSEM_ST9PLUS 67 elf.h STMicroelectronics ST9+ 8/16 mc
7633
 EM_ST7EM_ST7 68 elf.h STmicroelectronics ST7 8 bit mc
7634
 EM_68HC16EM_68HC16 69 elf.h Motorola MC68HC16 microcontroller
7635
 EM_68HC11EM_68HC11 70 elf.h Motorola MC68HC11 microcontroller
7636
 EM_68HC08EM_68HC08 71 elf.h Motorola MC68HC08 microcontroller
7637
 EM_68HC05EM_68HC05 72 elf.h Motorola MC68HC05 microcontroller
7638
 EM_SVXEM_SVX 73 elf.h Silicon Graphics SVx
7639
 EM_AT19EM_AT19 74 elf.h STMicroelectronics ST19 8 bit mc
7640
 EM_VAXEM_VAX 75 elf.h Digital VAX
7641
 EM_CRISEM_CRIS 76 elf.h Axis Communications 32-bit embedded processor
7642
 EM_JAVELINEM_JAVELIN 77 elf.h Infineon Technologies 32-bit embedded processor
7643
 EM_FIREPATHEM_FIREPATH 78 elf.h Element 14 64-bit DSP Processor
7644
 EM_ZSPEM_ZSP 79 elf.h LSI Logic 16-bit DSP Processor
7645
 EM_MMIXEM_MMIX 80 elf.h Donald Knuth's educational 64-bit processor
7646
 EM_HUANYEM_HUANY 81 elf.h Harvard University machine-independent object files
7647
 EM_PRISMEM_PRISM 82 elf.h SiTera Prism
7648
 EM_AVREM_AVR 83 elf.h Atmel AVR 8-bit microcontroller
7649
 EM_FR30EM_FR30 84 elf.h Fujitsu FR30
7650
 EM_D10VEM_D10V 85 elf.h Mitsubishi D10V
7651
 EM_D30VEM_D30V 86 elf.h Mitsubishi D30V
7652
 EM_V850EM_V850 87 elf.h NEC v850
7653
 EM_M32REM_M32R 88 elf.h Mitsubishi M32R
7654
 EM_MN10300EM_MN10300 89 elf.h Matsushita MN10300
7655
 EM_MN10200EM_MN10200 90 elf.h Matsushita MN10200
7656
 EM_PJEM_PJ 91 elf.h picoJava
7657
 EM_OPENRISCEM_OPENRISC 92 elf.h OpenRISC 32-bit embedded processor
7658
 EM_ARC_A5EM_ARC_A5 93 elf.h ARC Cores Tangent-A5
7659
 EM_XTENSAEM_XTENSA 94 elf.h Tensilica Xtensa Architecture
7660
 EM_NUMEM_NUM 95 elf.h 　
7661
 PT_NULLPT_NULL 0 elf.h Unused entry.
7662
 PT_LOADPT_LOAD 1 elf.h Loadable segment.
7663
 PT_DYNAMICPT_DYNAMIC 2 elf.h Dynamic linking information segment.
7664
 PT_INTERPPT_INTERP 3 elf.h Pathname of interpreter.
7665
 PT_NOTEPT_NOTE 4 elf.h Auxiliary information.
7666
 PT_SHLIBPT_SHLIB 5 elf.h Reserved (not used).
7667
 PT_PHDRPT_PHDR 6 elf.h Location of program header itself.
7668
 PF_XPF_X 0x1 elf.h Executable.
7669
 PF_WPF_W 0x2 elf.h Writable.
7670
 PF_RPF_R 0x4 elf.h Readable.
7671
 ELF_PROGRAM_RETURNS_BITELF_PROGRAM_RETURNS_BIT 0x8000000 elf.h e_flags bit 31
7672
 EI_MAG0EI_MAG0 0 elf.h 　
7673
 ELFMAG0ELFMAG0 0x7f elf.h 　
7674
 EI_MAG1EI_MAG1 1 elf.h 　
7675
 ELFMAG1ELFMAG1 'E' elf.h 　
7676
 EI_MAG2EI_MAG2 2 elf.h 　
7677
 ELFMAG2ELFMAG2 'L' elf.h 　
7678
 EI_MAG3EI_MAG3 3 elf.h 　
7679
 ELFMAG3ELFMAG3 'F' elf.h 　
7680
 ELFMAGELFMAG "\177ELF" elf.h 　
7681
 SELFMAGSELFMAG 4 elf.h 　
7682
 EI_CLASSEI_CLASS 4 elf.h File class byte index
7683
 ELFCLASSNONEELFCLASSNONE 0 elf.h Invalid class
7684
 ELFCLASS32ELFCLASS32 1 elf.h 32-bit objects
7685
 ELFCLASS64ELFCLASS64 2 elf.h 64-bit objects
7686
 EI_DATAEI_DATA 5 elf.h Data encodeing byte index
7687
 ELFDATANONEELFDATANONE 0 elf.h Invalid data encoding
7688
 ELFDATA2LSBELFDATA2LSB 1 elf.h 2's complement little endian
7689
 ELFDATA2MSBELFDATA2MSB 2 elf.h 2's complement big endian
7690
 EI_VERSIONEI_VERSION 6 elf.h File version byte index
7691
 EV_NONEEV_NONE 0 elf.h Invalid ELF Version
7692
 EV_CURRENTEV_CURRENT 1 elf.h Current version
7693
 ELF32_PHDR_SIZEELF32_PHDR_SIZE (8*4) elf.h Size of an elf program header
7694
 __LITTLE_ENDIAN__LITTLE_ENDIAN 1234 endian.h 　
7695
 __BIG_ENDIAN__BIG_ENDIAN 4321 endian.h 　
7696
 __PDP_ENDIAN__PDP_ENDIAN 3412 endian.h 　
7697
 ERRFILEERRFILE ( 0 * ( ( int ) missing_errfile_declaration ) ) errno.h 　
7698
 PXENV_STATUS_SUCCESSPXENV_STATUS_SUCCESS 0x0000 errno.h 　
7699
 PXENV_STATUS_FAILUREPXENV_STATUS_FAILURE 0x0001 errno.h 　
7700
 PXENV_STATUS_BAD_FUNCPXENV_STATUS_BAD_FUNC 0x0002 errno.h 　
7701
 PXENV_STATUS_UNSUPPORTEDPXENV_STATUS_UNSUPPORTED 0x0003 errno.h 　
7702
 PXENV_STATUS_KEEP_UNDIPXENV_STATUS_KEEP_UNDI 0x0004 errno.h 　
7703
 PXENV_STATUS_KEEP_ALLPXENV_STATUS_KEEP_ALL 0x0005 errno.h 　
7704
 PXENV_STATUS_OUT_OF_RESOURCESPXENV_STATUS_OUT_OF_RESOURCES 0x0006 errno.h 　
7705
 PXENV_STATUS_ARP_TIMEOUTPXENV_STATUS_ARP_TIMEOUT 0x0011 errno.h 　
7706
 PXENV_STATUS_UDP_CLOSEDPXENV_STATUS_UDP_CLOSED 0x0018 errno.h 　
7707
 PXENV_STATUS_UDP_OPENPXENV_STATUS_UDP_OPEN 0x0019 errno.h 　
7708
 PXENV_STATUS_TFTP_CLOSEDPXENV_STATUS_TFTP_CLOSED 0x001a errno.h 　
7709
 PXENV_STATUS_TFTP_OPENPXENV_STATUS_TFTP_OPEN 0x001b errno.h 　
7710
 PXENV_STATUS_MCOPY_PROBLEMPXENV_STATUS_MCOPY_PROBLEM 0x0020 errno.h 　
7711
 PXENV_STATUS_BIS_INTEGRITY_FAILPXENV_STATUS_BIS_INTEGRITY_FAIL 0x0021 errno.h 　
7712
 PXENV_STATUS_BIS_VALIDATE_FAILUPXENV_STATUS_BIS_VALIDATE_FAILU 0x0022 errno.h 　
7713
 PXENV_STATUS_BIS_INIT_FAILUREPXENV_STATUS_BIS_INIT_FAILURE 0x0023 errno.h 　
7714
 PXENV_STATUS_BIS_SHUTDOWN_FAILUPXENV_STATUS_BIS_SHUTDOWN_FAILU 0x0024 errno.h 　
7715
 PXENV_STATUS_BIS_GBOA_FAILUREPXENV_STATUS_BIS_GBOA_FAILURE 0x0025 errno.h 　
7716
 PXENV_STATUS_BIS_FREE_FAILUREPXENV_STATUS_BIS_FREE_FAILURE 0x0026 errno.h 　
7717
 PXENV_STATUS_BIS_GSI_FAILUREPXENV_STATUS_BIS_GSI_FAILURE 0x0027 errno.h 　
7718
 PXENV_STATUS_BIS_BAD_CKSUMPXENV_STATUS_BIS_BAD_CKSUM 0x0028 errno.h 　
7719
 PXENV_STATUS_TFTP_CANNOT_ARP_ADPXENV_STATUS_TFTP_CANNOT_ARP_AD 0x0030 errno.h 　
7720
 PXENV_STATUS_TFTP_OPEN_TIMEOUTPXENV_STATUS_TFTP_OPEN_TIMEOUT 0x0032 errno.h 　
7721
 PXENV_STATUS_TFTP_UNKNOWN_OPCODPXENV_STATUS_TFTP_UNKNOWN_OPCOD 0x0033 errno.h 　
7722
 PXENV_STATUS_TFTP_READ_TIMEOUTPXENV_STATUS_TFTP_READ_TIMEOUT 0x0035 errno.h 　
7723
 PXENV_STATUS_TFTP_ERROR_OPCODEPXENV_STATUS_TFTP_ERROR_OPCODE 0x0036 errno.h 　
7724
 PXENV_STATUS_TFTP_CANNOT_OPEN_CPXENV_STATUS_TFTP_CANNOT_OPEN_C 0x0038 errno.h 　
7725
 PXENV_STATUS_TFTP_CANNOT_READ_FPXENV_STATUS_TFTP_CANNOT_READ_F 0x0039 errno.h 　
7726
 PXENV_STATUS_TFTP_TOO_MANY_PACKPXENV_STATUS_TFTP_TOO_MANY_PACK 0x003a errno.h 　
7727
 PXENV_STATUS_TFTP_FILE_NOT_FOUNPXENV_STATUS_TFTP_FILE_NOT_FOUN 0x003b errno.h 　
7728
 PXENV_STATUS_TFTP_ACCESS_VIOLATPXENV_STATUS_TFTP_ACCESS_VIOLAT 0x003c errno.h 　
7729
 PXENV_STATUS_TFTP_NO_MCAST_ADDRPXENV_STATUS_TFTP_NO_MCAST_ADDR 0x003d errno.h 　
7730
 PXENV_STATUS_TFTP_NO_FILESIZEPXENV_STATUS_TFTP_NO_FILESIZE 0x003e errno.h 　
7731
 PXENV_STATUS_TFTP_INVALID_PACKEPXENV_STATUS_TFTP_INVALID_PACKE 0x003f errno.h 　
7732
 PXENV_STATUS_DHCP_TIMEOUTPXENV_STATUS_DHCP_TIMEOUT 0x0051 errno.h 　
7733
 PXENV_STATUS_DHCP_NO_IP_ADDRESSPXENV_STATUS_DHCP_NO_IP_ADDRESS 0x0052 errno.h 　
7734
 PXENV_STATUS_DHCP_NO_BOOTFILE_NPXENV_STATUS_DHCP_NO_BOOTFILE_N 0x0053 errno.h 　
7735
 PXENV_STATUS_DHCP_BAD_IP_ADDRESPXENV_STATUS_DHCP_BAD_IP_ADDRES 0x0054 errno.h 　
7736
 PXENV_STATUS_UNDI_INVALID_FUNCTPXENV_STATUS_UNDI_INVALID_FUNCT 0x0060 errno.h 　
7737
 PXENV_STATUS_UNDI_MEDIATEST_FAIPXENV_STATUS_UNDI_MEDIATEST_FAI 0x0061 errno.h 　
7738
 PXENV_STATUS_UNDI_CANNOT_INIT_NPXENV_STATUS_UNDI_CANNOT_INIT_N 0x0062 errno.h 　
7739
 PXENV_STATUS_UNDI_CANNOT_INITIAPXENV_STATUS_UNDI_CANNOT_INITIA 0x0063 errno.h 　
7740
 PXENV_STATUS_UNDI_CANNOT_INITIAPXENV_STATUS_UNDI_CANNOT_INITIA 0x0064 errno.h 　
7741
 PXENV_STATUS_UNDI_CANNOT_READ_CPXENV_STATUS_UNDI_CANNOT_READ_C 0x0065 errno.h 　
7742
 PXENV_STATUS_UNDI_CANNOT_READ_IPXENV_STATUS_UNDI_CANNOT_READ_I 0x0066 errno.h 　
7743
 PXENV_STATUS_UNDI_BAD_MAC_ADDREPXENV_STATUS_UNDI_BAD_MAC_ADDRE 0x0067 errno.h 　
7744
 PXENV_STATUS_UNDI_BAD_EEPROM_CHPXENV_STATUS_UNDI_BAD_EEPROM_CH 0x0068 errno.h 　
7745
 PXENV_STATUS_UNDI_ERROR_SETTINGPXENV_STATUS_UNDI_ERROR_SETTING 0x0069 errno.h 　
7746
 PXENV_STATUS_UNDI_INVALID_STATEPXENV_STATUS_UNDI_INVALID_STATE 0x006a errno.h 　
7747
 PXENV_STATUS_UNDI_TRANSMIT_ERROPXENV_STATUS_UNDI_TRANSMIT_ERRO 0x006b errno.h 　
7748
 PXENV_STATUS_UNDI_INVALID_PARAMPXENV_STATUS_UNDI_INVALID_PARAM 0x006c errno.h 　
7749
 PXENV_STATUS_BSTRAP_PROMPT_MENUPXENV_STATUS_BSTRAP_PROMPT_MENU 0x0074 errno.h 　
7750
 PXENV_STATUS_BSTRAP_MCAST_ADDRPXENV_STATUS_BSTRAP_MCAST_ADDR 0x0076 errno.h 　
7751
 PXENV_STATUS_BSTRAP_MISSING_LISPXENV_STATUS_BSTRAP_MISSING_LIS 0x0077 errno.h 　
7752
 PXENV_STATUS_BSTRAP_NO_RESPONSEPXENV_STATUS_BSTRAP_NO_RESPONSE 0x0078 errno.h 　
7753
 PXENV_STATUS_BSTRAP_FILE_TOO_BIPXENV_STATUS_BSTRAP_FILE_TOO_BI 0x0079 errno.h 　
7754
 PXENV_STATUS_BINL_CANCELED_BY_KPXENV_STATUS_BINL_CANCELED_BY_K 0x00a0 errno.h 　
7755
 PXENV_STATUS_BINL_NO_PXE_SERVERPXENV_STATUS_BINL_NO_PXE_SERVER 0x00a1 errno.h 　
7756
 PXENV_STATUS_NOT_AVAILABLE_IN_PPXENV_STATUS_NOT_AVAILABLE_IN_P 0x00a2 errno.h 　
7757
 PXENV_STATUS_NOT_AVAILABLE_IN_RPXENV_STATUS_NOT_AVAILABLE_IN_R 0x00a3 errno.h 　
7758
 PXENV_STATUS_BUSD_DEVICE_NOT_SUPXENV_STATUS_BUSD_DEVICE_NOT_SU 0x00b0 errno.h 　
7759
 PXENV_STATUS_LOADER_NO_FREE_BASPXENV_STATUS_LOADER_NO_FREE_BAS 0x00c0 errno.h 　
7760
 PXENV_STATUS_LOADER_NO_BC_ROMIDPXENV_STATUS_LOADER_NO_BC_ROMID 0x00c1 errno.h 　
7761
 PXENV_STATUS_LOADER_BAD_BC_ROMIPXENV_STATUS_LOADER_BAD_BC_ROMI 0x00c2 errno.h 　
7762
 PXENV_STATUS_LOADER_BAD_BC_RUNTPXENV_STATUS_LOADER_BAD_BC_RUNT 0x00c3 errno.h 　
7763
 PXENV_STATUS_LOADER_NO_UNDI_ROMPXENV_STATUS_LOADER_NO_UNDI_ROM 0x00c4 errno.h 　
7764
 PXENV_STATUS_LOADER_BAD_UNDI_ROPXENV_STATUS_LOADER_BAD_UNDI_RO 0x00c5 errno.h 　
7765
 PXENV_STATUS_LOADER_BAD_UNDI_DRPXENV_STATUS_LOADER_BAD_UNDI_DR 0x00c6 errno.h 　
7766
 PXENV_STATUS_LOADER_NO_PXE_STRUPXENV_STATUS_LOADER_NO_PXE_STRU 0x00c8 errno.h 　
7767
 PXENV_STATUS_LOADER_NO_PXENV_STPXENV_STATUS_LOADER_NO_PXENV_ST 0x00c9 errno.h 　
7768
 PXENV_STATUS_LOADER_UNDI_STARTPXENV_STATUS_LOADER_UNDI_START 0x00ca errno.h 　
7769
 PXENV_STATUS_LOADER_BC_STARTPXENV_STATUS_LOADER_BC_START 0x00cb errno.h 　
7770
 ENOERRENOERR ( ERRFILE | PXENV_STATUS_SUCCESS | 0x00000000 ) errno.h 　
7771
 E2BIGE2BIG ( ERRFILE | PXENV_STATUS_BAD_FUNC | 0x01000000 ) errno.h 　
7772
 EACCESEACCES ( ERRFILE | PXENV_STATUS_TFTP_ACCESS_VIOLATION | 0x02000000 ) errno.h 　
7773
 EADDRINUSEEADDRINUSE ( ERRFILE | PXENV_STATUS_UDP_OPEN | 0x03000000 ) errno.h 　
7774
 EADDRNOTAVAILEADDRNOTAVAIL ( ERRFILE | PXENV_STATUS_UDP_OPEN | 0x04000000 ) errno.h 　
7775
 EAFNOSUPPORTEAFNOSUPPORT ( ERRFILE | PXENV_STATUS_UNSUPPORTED | 0x05000000 ) errno.h 　
7776
 EAGAINEAGAIN ( ERRFILE | PXENV_STATUS_FAILURE | 0x06000000 ) errno.h 　
7777
 EALREADYEALREADY ( ERRFILE | PXENV_STATUS_UDP_OPEN | 0x07000000 ) errno.h 　
7778
 EBADFEBADF ( ERRFILE | PXENV_STATUS_TFTP_CLOSED | 0x08000000 ) errno.h 　
7779
 EBADMSGEBADMSG ( ERRFILE | PXENV_STATUS_FAILURE | 0x09000000 ) errno.h 　
7780
 EBUSYEBUSY ( ERRFILE | PXENV_STATUS_OUT_OF_RESOURCES | 0x0a000000 ) errno.h 　
7781
 ECANCELEDECANCELED ( ERRFILE | PXENV_STATUS_BINL_CANCELED_BY_KEYSTROKE | 0x0b000000 ) errno.h 　
7782
 ECHILDECHILD ( ERRFILE | PXENV_STATUS_TFTP_FILE_NOT_FOUND | 0x0c000000 ) errno.h 　
7783
 ECONNABORTEDECONNABORTED ( ERRFILE | PXENV_STATUS_TFTP_CANNOT_READ_FROM_CONNECTION | 0x0d000000 ) errno.h 　
7784
 ECONNREFUSEDECONNREFUSED ( ERRFILE | PXENV_STATUS_TFTP_CANNOT_OPEN_CONNECTION | 0x0e000000 ) errno.h 　
7785
 ECONNRESETECONNRESET ( ERRFILE | PXENV_STATUS_TFTP_CANNOT_READ_FROM_CONNECTION | 0x0f000000 ) errno.h 　
7786
 EDEADLKEDEADLK ( ERRFILE | PXENV_STATUS_FAILURE | 0x10000000 ) errno.h 　
7787
 EDESTADDRREQEDESTADDRREQ ( ERRFILE | PXENV_STATUS_BAD_FUNC | 0x11000000 ) errno.h 　
7788
 EDOMEDOM ( ERRFILE | PXENV_STATUS_FAILURE | 0x12000000 ) errno.h 　
7789
 EDQUOTEDQUOT ( ERRFILE | PXENV_STATUS_FAILURE | 0x13000000 ) errno.h 　
7790
 EEXISTEEXIST ( ERRFILE | PXENV_STATUS_FAILURE | 0x14000000 ) errno.h 　
7791
 EFAULTEFAULT ( ERRFILE | PXENV_STATUS_MCOPY_PROBLEM | 0x15000000 ) errno.h 　
7792
 EFBIGEFBIG ( ERRFILE | PXENV_STATUS_MCOPY_PROBLEM | 0x16000000 ) errno.h 　
7793
 EHOSTUNREACHEHOSTUNREACH ( ERRFILE | PXENV_STATUS_ARP_TIMEOUT | 0x17000000 ) errno.h 　
7794
 EIDRMEIDRM ( ERRFILE | PXENV_STATUS_FAILURE | 0x18000000 ) errno.h 　
7795
 EILSEQEILSEQ ( ERRFILE | PXENV_STATUS_FAILURE | 0x19000000 ) errno.h 　
7796
 EINPROGRESSEINPROGRESS ( ERRFILE | PXENV_STATUS_FAILURE | 0x1a000000 ) errno.h 　
7797
 EINTREINTR ( ERRFILE | PXENV_STATUS_FAILURE | 0x1b000000 ) errno.h 　
7798
 EINVALEINVAL ( ERRFILE | PXENV_STATUS_BAD_FUNC | 0x1c000000 ) errno.h 　
7799
 EIOEIO ( ERRFILE | PXENV_STATUS_TFTP_CANNOT_READ_FROM_CONNECTION | 0x1d000000 ) errno.h 　
7800
 EISCONNEISCONN ( ERRFILE | PXENV_STATUS_UDP_OPEN | 0x1e000000 ) errno.h 　
7801
 EISDIREISDIR ( ERRFILE | PXENV_STATUS_FAILURE | 0x1f000000 ) errno.h 　
7802
 ELOOPELOOP ( ERRFILE | PXENV_STATUS_FAILURE | 0x20000000 ) errno.h 　
7803
 EMFILEEMFILE ( ERRFILE | PXENV_STATUS_OUT_OF_RESOURCES | 0x21000000 ) errno.h 　
7804
 EMLINKEMLINK ( ERRFILE | PXENV_STATUS_FAILURE | 0x22000000 ) errno.h 　
7805
 EMSGSIZEEMSGSIZE ( ERRFILE | PXENV_STATUS_BAD_FUNC | 0x23000000 ) errno.h 　
7806
 EMULTIHOPEMULTIHOP ( ERRFILE | PXENV_STATUS_FAILURE | 0x24000000 ) errno.h 　
7807
 ENAMETOOLONGENAMETOOLONG ( ERRFILE | PXENV_STATUS_FAILURE | 0x25000000 ) errno.h 　
7808
 ENETDOWNENETDOWN ( ERRFILE | PXENV_STATUS_ARP_TIMEOUT | 0x26000000 ) errno.h 　
7809
 ENETRESETENETRESET ( ERRFILE | PXENV_STATUS_FAILURE | 0x27000000 ) errno.h 　
7810
 ENETUNREACHENETUNREACH ( ERRFILE | PXENV_STATUS_ARP_TIMEOUT | 0x28000000 ) errno.h 　
7811
 ENFILEENFILE ( ERRFILE | PXENV_STATUS_OUT_OF_RESOURCES | 0x29000000 ) errno.h 　
7812
 ENOBUFSENOBUFS ( ERRFILE | PXENV_STATUS_OUT_OF_RESOURCES | 0x2a000000 ) errno.h 　
7813
 ENODATAENODATA ( ERRFILE | PXENV_STATUS_FAILURE | 0x2b000000 ) errno.h 　
7814
 ENODEVENODEV ( ERRFILE | PXENV_STATUS_TFTP_FILE_NOT_FOUND | 0x2c000000 ) errno.h 　
7815
 ENOENTENOENT ( ERRFILE | PXENV_STATUS_TFTP_FILE_NOT_FOUND | 0x2d000000 ) errno.h 　
7816
 ENOEXECENOEXEC ( ERRFILE | PXENV_STATUS_FAILURE | 0x2e000000 ) errno.h 　
7817
 ENOLCKENOLCK ( ERRFILE | PXENV_STATUS_FAILURE | 0x2f000000 ) errno.h 　
7818
 ENOLINKENOLINK ( ERRFILE | PXENV_STATUS_FAILURE | 0x30000000 ) errno.h 　
7819
 ENOMEMENOMEM ( ERRFILE | PXENV_STATUS_OUT_OF_RESOURCES | 0x31000000 ) errno.h 　
7820
 ENOMSGENOMSG ( ERRFILE | PXENV_STATUS_FAILURE | 0x32000000 ) errno.h 　
7821
 ENOPROTOOPTENOPROTOOPT ( ERRFILE | PXENV_STATUS_UNSUPPORTED | 0x33000000 ) errno.h 　
7822
 ENOSPCENOSPC ( ERRFILE | PXENV_STATUS_OUT_OF_RESOURCES | 0x34000000 ) errno.h 　
7823
 ENOSRENOSR ( ERRFILE | PXENV_STATUS_OUT_OF_RESOURCES | 0x35000000 ) errno.h 　
7824
 ENOSTRENOSTR ( ERRFILE | PXENV_STATUS_FAILURE | 0x36000000 ) errno.h 　
7825
 ENOSYSENOSYS ( ERRFILE | PXENV_STATUS_UNSUPPORTED | 0x37000000 ) errno.h 　
7826
 ENOTCONNENOTCONN ( ERRFILE | PXENV_STATUS_FAILURE | 0x38000000 ) errno.h 　
7827
 ENOTDIRENOTDIR ( ERRFILE | PXENV_STATUS_FAILURE | 0x39000000 ) errno.h 　
7828
 ENOTEMPTYENOTEMPTY ( ERRFILE | PXENV_STATUS_FAILURE | 0x3a000000 ) errno.h 　
7829
 ENOTSOCKENOTSOCK ( ERRFILE | PXENV_STATUS_FAILURE | 0x3b000000 ) errno.h 　
7830
 ENOTSUPENOTSUP ( ERRFILE | PXENV_STATUS_UNSUPPORTED | 0x3c000000 ) errno.h 　
7831
 ENOTTYENOTTY ( ERRFILE | PXENV_STATUS_FAILURE | 0x3d000000 ) errno.h 　
7832
 ENXIOENXIO ( ERRFILE | PXENV_STATUS_TFTP_FILE_NOT_FOUND | 0x3e000000 ) errno.h 　
7833
 EOPNOTSUPPEOPNOTSUPP ( ERRFILE | PXENV_STATUS_UNSUPPORTED | 0x3f000000 ) errno.h 　
7834
 EOVERFLOWEOVERFLOW ( ERRFILE | PXENV_STATUS_FAILURE | 0x40000000 ) errno.h 　
7835
 EPERMEPERM ( ERRFILE | PXENV_STATUS_TFTP_ACCESS_VIOLATION | 0x41000000 ) errno.h 　
7836
 EPIPEEPIPE ( ERRFILE | PXENV_STATUS_FAILURE | 0x42000000 ) errno.h 　
7837
 EPROTOEPROTO ( ERRFILE | PXENV_STATUS_FAILURE | 0x43000000 ) errno.h 　
7838
 EPROTONOSUPPORTEPROTONOSUPPORT ( ERRFILE | PXENV_STATUS_UNSUPPORTED | 0x44000000 ) errno.h 　
7839
 EPROTOTYPEEPROTOTYPE ( ERRFILE | PXENV_STATUS_FAILURE | 0x45000000 ) errno.h 　
7840
 ERANGEERANGE ( ERRFILE | PXENV_STATUS_FAILURE | 0x46000000 ) errno.h 　
7841
 EROFSEROFS ( ERRFILE | PXENV_STATUS_FAILURE | 0x47000000 ) errno.h 　
7842
 ESPIPEESPIPE ( ERRFILE | PXENV_STATUS_FAILURE | 0x48000000 ) errno.h 　
7843
 ESRCHESRCH ( ERRFILE | PXENV_STATUS_TFTP_FILE_NOT_FOUND | 0x49000000 ) errno.h 　
7844
 ESTALEESTALE ( ERRFILE | PXENV_STATUS_FAILURE | 0x4a000000 ) errno.h 　
7845
 ETIMEETIME ( ERRFILE | PXENV_STATUS_FAILURE | 0x4b000000 ) errno.h 　
7846
 ETIMEDOUTETIMEDOUT ( ERRFILE | PXENV_STATUS_TFTP_READ_TIMEOUT | 0x4c000000 ) errno.h 　
7847
 ETXTBSYETXTBSY ( ERRFILE | PXENV_STATUS_FAILURE | 0x4d000000 ) errno.h 　
7848
 EWOULDBLOCKEWOULDBLOCK ( ERRFILE | PXENV_STATUS_TFTP_OPEN | 0x4e000000 ) errno.h 　
7849
 EXDEVEXDEV ( ERRFILE | PXENV_STATUS_FAILURE | 0x4f000000 ) errno.h 　
7850
 EUNIQ_01EUNIQ_01 0x00000100 errno.h 　
7851
 EUNIQ_02EUNIQ_02 0x00000200 errno.h 　
7852
 EUNIQ_03EUNIQ_03 0x00000300 errno.h 　
7853
 EUNIQ_04EUNIQ_04 0x00000400 errno.h 　
7854
 EUNIQ_05EUNIQ_05 0x00000500 errno.h 　
7855
 EUNIQ_06EUNIQ_06 0x00000600 errno.h 　
7856
 EUNIQ_07EUNIQ_07 0x00000700 errno.h 　
7857
 EUNIQ_08EUNIQ_08 0x00000800 errno.h 　
7858
 EUNIQ_09EUNIQ_09 0x00000900 errno.h 　
7859
 EUNIQ_0AEUNIQ_0A 0x00000a00 errno.h 　
7860
 EUNIQ_0BEUNIQ_0B 0x00000b00 errno.h 　
7861
 EUNIQ_0CEUNIQ_0C 0x00000c00 errno.h 　
7862
 EUNIQ_0DEUNIQ_0D 0x00000d00 errno.h 　
7863
 EUNIQ_0EEUNIQ_0E 0x00000e00 errno.h 　
7864
 EUNIQ_0FEUNIQ_0F 0x00000f00 errno.h 　
7865
 EUNIQ_10EUNIQ_10 0x00001000 errno.h 　
7866
 EUNIQ_11EUNIQ_11 0x00001100 errno.h 　
7867
 EUNIQ_12EUNIQ_12 0x00001200 errno.h 　
7868
 EUNIQ_13EUNIQ_13 0x00001300 errno.h 　
7869
 EUNIQ_14EUNIQ_14 0x00001400 errno.h 　
7870
 EUNIQ_15EUNIQ_15 0x00001500 errno.h 　
7871
 EUNIQ_16EUNIQ_16 0x00001600 errno.h 　
7872
 EUNIQ_17EUNIQ_17 0x00001700 errno.h 　
7873
 EUNIQ_18EUNIQ_18 0x00001800 errno.h 　
7874
 EUNIQ_19EUNIQ_19 0x00001900 errno.h 　
7875
 EUNIQ_1AEUNIQ_1A 0x00001a00 errno.h 　
7876
 EUNIQ_1BEUNIQ_1B 0x00001b00 errno.h 　
7877
 EUNIQ_1CEUNIQ_1C 0x00001c00 errno.h 　
7878
 EUNIQ_1DEUNIQ_1D 0x00001d00 errno.h 　
7879
 EUNIQ_1EEUNIQ_1E 0x00001e00 errno.h 　
7880
 EUNIQ_1FEUNIQ_1F 0x00001f00 errno.h 　
7881
 VALID_LINK_TIMEOUTVALID_LINK_TIMEOUT 100 etherboot.h 10.0 seconds
7882
 DISK_IDEDISK_IDE 1 fs.h 　
7883
 DISK_MEMDISK_MEM 2 fs.h 　
7884
 DISK_USBDISK_USB 3 fs.h 　
7885
 PARTITION_UNKNOWNPARTITION_UNKNOWN 0xbad6a7 fs.h 　
7886
 I365_IDENTI365_IDENT 0x00 i82365.h Identification and revision
7887
 I365_STATUSI365_STATUS 0x01 i82365.h Interface status
7888
 I365_POWERI365_POWER 0x02 i82365.h Power and RESETDRV control
7889
 I365_INTCTLI365_INTCTL 0x03 i82365.h Interrupt and general control
7890
 I365_CSCI365_CSC 0x04 i82365.h Card status change
7891
 I365_CSCINTI365_CSCINT 0x05 i82365.h Card status change interrupt control
7892
 I365_ADDRWINI365_ADDRWIN 0x06 i82365.h Address window enable
7893
 I365_IOCTLI365_IOCTL 0x07 i82365.h I/O control
7894
 I365_GENCTLI365_GENCTL 0x16 i82365.h Card detect and general control
7895
 I365_GBLCTLI365_GBLCTL 0x1E i82365.h Global control register
7896
 I365_W_STARTI365_W_START 0 i82365.h 　
7897
 I365_W_STOPI365_W_STOP 2 i82365.h 　
7898
 I365_W_OFFI365_W_OFF 4 i82365.h 　
7899
 I365_CS_BVD1I365_CS_BVD1 0x01 i82365.h 　
7900
 I365_CS_STSCHGI365_CS_STSCHG 0x01 i82365.h 　
7901
 I365_CS_BVD2I365_CS_BVD2 0x02 i82365.h 　
7902
 I365_CS_SPKRI365_CS_SPKR 0x02 i82365.h 　
7903
 I365_CS_DETECTI365_CS_DETECT 0x0C i82365.h 　
7904
 I365_CS_WRPROTI365_CS_WRPROT 0x10 i82365.h 　
7905
 I365_CS_READYI365_CS_READY 0x20 i82365.h Inverted
7906
 I365_CS_POWERONI365_CS_POWERON 0x40 i82365.h 　
7907
 I365_CS_GPII365_CS_GPI 0x80 i82365.h 　
7908
 I365_PWR_OFFI365_PWR_OFF 0x00 i82365.h Turn off the socket
7909
 I365_PWR_OUTI365_PWR_OUT 0x80 i82365.h Output enable
7910
 I365_PWR_NORESETI365_PWR_NORESET 0x40 i82365.h Disable RESETDRV on resume
7911
 I365_PWR_AUTOI365_PWR_AUTO 0x20 i82365.h Auto pwr switch enable
7912
 I365_VCC_MASKI365_VCC_MASK 0x18 i82365.h Mask for turning off Vcc
7913
 I365_VCC_5VI365_VCC_5V 0x10 i82365.h Vcc = 5.0v
7914
 I365_VCC_3VI365_VCC_3V 0x18 i82365.h Vcc = 3.3v
7915
 I365_VPP2_MASKI365_VPP2_MASK 0x0c i82365.h Mask for turning off Vpp2
7916
 I365_VPP2_5VI365_VPP2_5V 0x04 i82365.h Vpp2 = 5.0v
7917
 I365_VPP2_12VI365_VPP2_12V 0x08 i82365.h Vpp2 = 12.0v
7918
 I365_VPP1_MASKI365_VPP1_MASK 0x03 i82365.h Mask for turning off Vpp1
7919
 I365_VPP1_5VI365_VPP1_5V 0x01 i82365.h Vpp2 = 5.0v
7920
 I365_VPP1_12VI365_VPP1_12V 0x02 i82365.h Vpp2 = 12.0v
7921
 I365_RING_ENAI365_RING_ENA 0x80 i82365.h 　
7922
 I365_PC_RESETI365_PC_RESET 0x40 i82365.h 　
7923
 I365_PC_IOCARDI365_PC_IOCARD 0x20 i82365.h 　
7924
 I365_INTR_ENAI365_INTR_ENA 0x10 i82365.h 　
7925
 I365_IRQ_MASKI365_IRQ_MASK 0x0F i82365.h 　
7926
 I365_CSC_BVD1I365_CSC_BVD1 0x01 i82365.h 　
7927
 I365_CSC_STSCHGI365_CSC_STSCHG 0x01 i82365.h 　
7928
 I365_CSC_BVD2I365_CSC_BVD2 0x02 i82365.h 　
7929
 I365_CSC_READYI365_CSC_READY 0x04 i82365.h 　
7930
 I365_CSC_DETECTI365_CSC_DETECT 0x08 i82365.h 　
7931
 I365_CSC_ANYI365_CSC_ANY 0x0F i82365.h 　
7932
 I365_CSC_GPII365_CSC_GPI 0x10 i82365.h 　
7933
 I365_CTL_16DELAYI365_CTL_16DELAY 0x01 i82365.h 　
7934
 I365_CTL_RESETI365_CTL_RESET 0x02 i82365.h 　
7935
 I365_CTL_GPI_ENAI365_CTL_GPI_ENA 0x04 i82365.h 　
7936
 I365_CTL_GPI_CTLI365_CTL_GPI_CTL 0x08 i82365.h 　
7937
 I365_CTL_RESUMEI365_CTL_RESUME 0x10 i82365.h 　
7938
 I365_CTL_SW_IRQI365_CTL_SW_IRQ 0x20 i82365.h 　
7939
 I365_GBL_PWRDOWNI365_GBL_PWRDOWN 0x01 i82365.h 　
7940
 I365_GBL_CSC_LEVI365_GBL_CSC_LEV 0x02 i82365.h 　
7941
 I365_GBL_WRBACKI365_GBL_WRBACK 0x04 i82365.h 　
7942
 I365_GBL_IRQ_0_LEVI365_GBL_IRQ_0_LEV 0x08 i82365.h 　
7943
 I365_GBL_IRQ_1_LEVI365_GBL_IRQ_1_LEV 0x10 i82365.h 　
7944
 I365_MEM_16BITI365_MEM_16BIT 0x8000 i82365.h In memory start high byte
7945
 I365_MEM_0WSI365_MEM_0WS 0x4000 i82365.h 　
7946
 I365_MEM_WS1I365_MEM_WS1 0x8000 i82365.h In memory stop high byte
7947
 I365_MEM_WS0I365_MEM_WS0 0x4000 i82365.h 　
7948
 I365_MEM_WRPROTI365_MEM_WRPROT 0x8000 i82365.h In offset high byte
7949
 I365_MEM_REGI365_MEM_REG 0x4000 i82365.h 　
7950
 I365_IDENT_VADEMI365_IDENT_VADEM 0x08 i82365.h 　
7951
 VG468_VPP2_MASKVG468_VPP2_MASK 0x0c i82365.h 　
7952
 VG468_VPP2_5VVG468_VPP2_5V 0x04 i82365.h 　
7953
 VG468_VPP2_12VVG468_VPP2_12V 0x08 i82365.h 　
7954
 VG469_VSENSEVG469_VSENSE 0x1f i82365.h Card voltage sense
7955
 VG469_VSELECTVG469_VSELECT 0x2f i82365.h Card voltage select
7956
 VG468_CTLVG468_CTL 0x38 i82365.h Control register
7957
 VG468_TIMERVG468_TIMER 0x39 i82365.h Timer control
7958
 VG468_MISCVG468_MISC 0x3a i82365.h Miscellaneous
7959
 VG468_GPIO_CFGVG468_GPIO_CFG 0x3b i82365.h GPIO configuration
7960
 VG469_EXT_MODEVG469_EXT_MODE 0x3c i82365.h Extended mode register
7961
 VG468_SELECTVG468_SELECT 0x3d i82365.h Programmable chip select
7962
 VG468_SELECT_CFGVG468_SELECT_CFG 0x3e i82365.h Chip select configuration
7963
 VG468_ATAVG468_ATA 0x3f i82365.h ATA control
7964
 VG469_VSENSE_A_VS1VG469_VSENSE_A_VS1 0x01 i82365.h 　
7965
 VG469_VSENSE_A_VS2VG469_VSENSE_A_VS2 0x02 i82365.h 　
7966
 VG469_VSENSE_B_VS1VG469_VSENSE_B_VS1 0x04 i82365.h 　
7967
 VG469_VSENSE_B_VS2VG469_VSENSE_B_VS2 0x08 i82365.h 　
7968
 VG469_VSEL_VCCVG469_VSEL_VCC 0x03 i82365.h 　
7969
 VG469_VSEL_5VVG469_VSEL_5V 0x00 i82365.h 　
7970
 VG469_VSEL_3VVG469_VSEL_3V 0x03 i82365.h 　
7971
 VG469_VSEL_MAXVG469_VSEL_MAX 0x0c i82365.h 　
7972
 VG469_VSEL_EXT_STATVG469_VSEL_EXT_STAT 0x10 i82365.h 　
7973
 VG469_VSEL_EXT_BUSVG469_VSEL_EXT_BUS 0x20 i82365.h 　
7974
 VG469_VSEL_MIXEDVG469_VSEL_MIXED 0x40 i82365.h 　
7975
 VG469_VSEL_ISAVG469_VSEL_ISA 0x80 i82365.h 　
7976
 VG468_CTL_SLOWVG468_CTL_SLOW 0x01 i82365.h 600ns memory timing
7977
 VG468_CTL_ASYNCVG468_CTL_ASYNC 0x02 i82365.h Asynchronous bus clocking
7978
 VG468_CTL_TSSIVG468_CTL_TSSI 0x08 i82365.h Tri-state some outputs
7979
 VG468_CTL_DELAYVG468_CTL_DELAY 0x10 i82365.h Card detect debounce
7980
 VG468_CTL_INPACKVG468_CTL_INPACK 0x20 i82365.h Obey INPACK signal?
7981
 VG468_CTL_POLARITYVG468_CTL_POLARITY 0x40 i82365.h VCCEN polarity
7982
 VG468_CTL_COMPATVG468_CTL_COMPAT 0x80 i82365.h Compatibility stuff
7983
 VG469_CTL_WS_COMPATVG469_CTL_WS_COMPAT 0x04 i82365.h Wait state compatibility
7984
 VG469_CTL_STRETCHVG469_CTL_STRETCH 0x10 i82365.h LED stretch
7985
 VG468_TIMER_ZEROPWRVG468_TIMER_ZEROPWR 0x10 i82365.h Zero power control
7986
 VG468_TIMER_SIGENVG468_TIMER_SIGEN 0x20 i82365.h Power up
7987
 VG468_TIMER_STATUSVG468_TIMER_STATUS 0x40 i82365.h Activity timer status
7988
 VG468_TIMER_RESVG468_TIMER_RES 0x80 i82365.h Timer resolution
7989
 VG468_TIMER_MASKVG468_TIMER_MASK 0x0f i82365.h Activity timer timeout
7990
 VG468_MISC_GPIOVG468_MISC_GPIO 0x04 i82365.h General-purpose IO
7991
 VG468_MISC_DMAWSBVG468_MISC_DMAWSB 0x08 i82365.h DMA wait state control
7992
 VG469_MISC_LEDENAVG469_MISC_LEDENA 0x10 i82365.h LED enable
7993
 VG468_MISC_VADEMREVVG468_MISC_VADEMREV 0x40 i82365.h Vadem revision control
7994
 VG468_MISC_UNLOCKVG468_MISC_UNLOCK 0x80 i82365.h Unique register lock
7995
 VG469_MODE_VPPSTVG469_MODE_VPPST 0x03 i82365.h Vpp steering control
7996
 VG469_MODE_INT_SENSEVG469_MODE_INT_SENSE 0x04 i82365.h Internal voltage sense
7997
 VG469_MODE_CABLEVG469_MODE_CABLE 0x08 i82365.h 　
7998
 VG469_MODE_COMPATVG469_MODE_COMPAT 0x10 i82365.h i82365sl B or DF step
7999
 VG469_MODE_TESTVG469_MODE_TEST 0x20 i82365.h 　
8000
 VG469_MODE_RIOVG469_MODE_RIO 0x40 i82365.h Steer RIO to INTR?
8001
 VG469_MODE_B_3VVG469_MODE_B_3V 0x01 i82365.h 3.3v for socket B
8002
 RF5C_MODE_CTLRF5C_MODE_CTL 0x1f i82365.h Mode control
8003
 RF5C_PWR_CTLRF5C_PWR_CTL 0x2f i82365.h Mixed voltage control
8004
 RF5C_CHIP_IDRF5C_CHIP_ID 0x3a i82365.h Chip identification
8005
 RF5C_MODE_CTL_3RF5C_MODE_CTL_3 0x3b i82365.h Mode control 3
8006
 RF5C_MODE_ATARF5C_MODE_ATA 0x01 i82365.h ATA mode
8007
 RF5C_MODE_LED_ENARF5C_MODE_LED_ENA 0x02 i82365.h IRQ 12 is LED
8008
 RF5C_MODE_CA21RF5C_MODE_CA21 0x04 i82365.h 　
8009
 RF5C_MODE_CA22RF5C_MODE_CA22 0x08 i82365.h 　
8010
 RF5C_MODE_CA23RF5C_MODE_CA23 0x10 i82365.h 　
8011
 RF5C_MODE_CA24RF5C_MODE_CA24 0x20 i82365.h 　
8012
 RF5C_MODE_CA25RF5C_MODE_CA25 0x40 i82365.h 　
8013
 RF5C_MODE_3STATE_BIT7RF5C_MODE_3STATE_BIT7 0x80 i82365.h 　
8014
 RF5C_PWR_VCC_3VRF5C_PWR_VCC_3V 0x01 i82365.h 　
8015
 RF5C_PWR_IREQ_HIGHRF5C_PWR_IREQ_HIGH 0x02 i82365.h 　
8016
 RF5C_PWR_INPACK_ENARF5C_PWR_INPACK_ENA 0x04 i82365.h 　
8017
 RF5C_PWR_5V_DETRF5C_PWR_5V_DET 0x08 i82365.h 　
8018
 RF5C_PWR_TC_SELRF5C_PWR_TC_SEL 0x10 i82365.h Terminal Count: irq 11 or 15
8019
 RF5C_PWR_DREQ_LOWRF5C_PWR_DREQ_LOW 0x20 i82365.h 　
8020
 RF5C_PWR_DREQ_OFFRF5C_PWR_DREQ_OFF 0x00 i82365.h DREQ steering control
8021
 RF5C_PWR_DREQ_INPACKRF5C_PWR_DREQ_INPACK 0x40 i82365.h 　
8022
 RF5C_PWR_DREQ_SPKRRF5C_PWR_DREQ_SPKR 0x80 i82365.h 　
8023
 RF5C_PWR_DREQ_IOIS16RF5C_PWR_DREQ_IOIS16 0xc0 i82365.h 　
8024
 RF5C_CHIP_RF5C296RF5C_CHIP_RF5C296 0x32 i82365.h 　
8025
 RF5C_CHIP_RF5C396RF5C_CHIP_RF5C396 0xb2 i82365.h 　
8026
 RF5C_MCTL3_DISABLERF5C_MCTL3_DISABLE 0x01 i82365.h Disable PCMCIA interface
8027
 RF5C_MCTL3_DMA_ENARF5C_MCTL3_DMA_ENA 0x02 i82365.h 　
8028
 RL5C46X_BCR_3E0_ENARL5C46X_BCR_3E0_ENA 0x0800 i82365.h 　
8029
 RL5C46X_BCR_3E2_ENARL5C46X_BCR_3E2_ENA 0x1000 i82365.h 　
8030
 RL5C4XX_CONFIGRL5C4XX_CONFIG 0x80 i82365.h 16 bit
8031
 RL5C4XX_CONFIG_IO_1_MODERL5C4XX_CONFIG_IO_1_MODE 0x0200 i82365.h 　
8032
 RL5C4XX_CONFIG_IO_0_MODERL5C4XX_CONFIG_IO_0_MODE 0x0100 i82365.h 　
8033
 RL5C4XX_CONFIG_PREFETCHRL5C4XX_CONFIG_PREFETCH 0x0001 i82365.h 　
8034
 RL5C4XX_MISCRL5C4XX_MISC 0x0082 i82365.h 16 bit
8035
 RL5C4XX_MISC_HW_SUSPEND_ENARL5C4XX_MISC_HW_SUSPEND_ENA 0x0002 i82365.h 　
8036
 RL5C4XX_MISC_VCCEN_POLRL5C4XX_MISC_VCCEN_POL 0x0100 i82365.h 　
8037
 RL5C4XX_MISC_VPPEN_POLRL5C4XX_MISC_VPPEN_POL 0x0200 i82365.h 　
8038
 RL5C46X_MISC_SUSPENDRL5C46X_MISC_SUSPEND 0x0001 i82365.h 　
8039
 RL5C46X_MISC_PWR_SAVE_2RL5C46X_MISC_PWR_SAVE_2 0x0004 i82365.h 　
8040
 RL5C46X_MISC_IFACE_BUSYRL5C46X_MISC_IFACE_BUSY 0x0008 i82365.h 　
8041
 RL5C46X_MISC_B_LOCKRL5C46X_MISC_B_LOCK 0x0010 i82365.h 　
8042
 RL5C46X_MISC_A_LOCKRL5C46X_MISC_A_LOCK 0x0020 i82365.h 　
8043
 RL5C46X_MISC_PCI_LOCKRL5C46X_MISC_PCI_LOCK 0x0040 i82365.h 　
8044
 RL5C47X_MISC_IFACE_BUSYRL5C47X_MISC_IFACE_BUSY 0x0004 i82365.h 　
8045
 RL5C47X_MISC_PCI_INT_MASKRL5C47X_MISC_PCI_INT_MASK 0x0018 i82365.h 　
8046
 RL5C47X_MISC_PCI_INT_DISRL5C47X_MISC_PCI_INT_DIS 0x0020 i82365.h 　
8047
 RL5C47X_MISC_SUBSYS_WRRL5C47X_MISC_SUBSYS_WR 0x0040 i82365.h 　
8048
 RL5C47X_MISC_SRIRQ_ENARL5C47X_MISC_SRIRQ_ENA 0x0080 i82365.h 　
8049
 RL5C47X_MISC_5V_DISABLERL5C47X_MISC_5V_DISABLE 0x0400 i82365.h 　
8050
 RL5C47X_MISC_LED_POLRL5C47X_MISC_LED_POL 0x0800 i82365.h 　
8051
 RL5C4XX_16BIT_CTLRL5C4XX_16BIT_CTL 0x0084 i82365.h 16 bit
8052
 RL5C4XX_16CTL_IO_TIMINGRL5C4XX_16CTL_IO_TIMING 0x0100 i82365.h 　
8053
 RL5C4XX_16CTL_MEM_TIMINGRL5C4XX_16CTL_MEM_TIMING 0x0200 i82365.h 　
8054
 RL5C46X_16CTL_LEVEL_1RL5C46X_16CTL_LEVEL_1 0x0010 i82365.h 　
8055
 RL5C46X_16CTL_LEVEL_2RL5C46X_16CTL_LEVEL_2 0x0020 i82365.h 　
8056
 RL5C4XX_16BIT_IO_0RL5C4XX_16BIT_IO_0 0x0088 i82365.h 16 bit
8057
 RL5C4XX_16BIT_MEM_0RL5C4XX_16BIT_MEM_0 0x0088 i82365.h 16 bit
8058
 RL5C4XX_SETUP_MASKRL5C4XX_SETUP_MASK 0x0007 i82365.h 　
8059
 RL5C4XX_SETUP_SHIFTRL5C4XX_SETUP_SHIFT 0 i82365.h 　
8060
 RL5C4XX_CMD_MASKRL5C4XX_CMD_MASK 0x01f0 i82365.h 　
8061
 RL5C4XX_CMD_SHIFTRL5C4XX_CMD_SHIFT 4 i82365.h 　
8062
 RL5C4XX_HOLD_MASKRL5C4XX_HOLD_MASK 0x1c00 i82365.h 　
8063
 RL5C4XX_HOLD_SHIFTRL5C4XX_HOLD_SHIFT 10 i82365.h 　
8064
 RL5C4XX_MISC_CONTROLRL5C4XX_MISC_CONTROL 0x2F i82365.h 8 bit
8065
 RL5C4XX_ZV_ENABLERL5C4XX_ZV_ENABLE 0x08 i82365.h 　
8066
 PCI_VENDOR_ID_CIRRUSPCI_VENDOR_ID_CIRRUS 0x1013 i82365.h 　
8067
 PCI_DEVICE_ID_CIRRUS_6729PCI_DEVICE_ID_CIRRUS_6729 0x1100 i82365.h 　
8068
 PCI_DEVICE_ID_CIRRUS_6832PCI_DEVICE_ID_CIRRUS_6832 0x1110 i82365.h 　
8069
 PD67_MISC_CTL_1PD67_MISC_CTL_1 0x16 i82365.h Misc control 1
8070
 PD67_FIFO_CTLPD67_FIFO_CTL 0x17 i82365.h FIFO control
8071
 PD67_MISC_CTL_2PD67_MISC_CTL_2 0x1E i82365.h Misc control 2
8072
 PD67_CHIP_INFOPD67_CHIP_INFO 0x1f i82365.h Chip information
8073
 PD67_ATA_CTLPD67_ATA_CTL 0x026 i82365.h 6730: ATA control
8074
 PD67_EXT_INDEXPD67_EXT_INDEX 0x2e i82365.h Extension index
8075
 PD67_EXT_DATAPD67_EXT_DATA 0x2f i82365.h Extension data
8076
 PD67_DATA_MASK0PD67_DATA_MASK0 0x01 i82365.h Data mask 0
8077
 PD67_DATA_MASK1PD67_DATA_MASK1 0x02 i82365.h Data mask 1
8078
 PD67_DMA_CTLPD67_DMA_CTL 0x03 i82365.h DMA control
8079
 PD67_EXT_CTL_1PD67_EXT_CTL_1 0x03 i82365.h Extension control 1
8080
 PD67_EXTERN_DATAPD67_EXTERN_DATA 0x0a i82365.h 　
8081
 PD67_MISC_CTL_3PD67_MISC_CTL_3 0x25 i82365.h 　
8082
 PD67_SMB_PWR_CTLPD67_SMB_PWR_CTL 0x26 i82365.h 　
8083
 PD67_MC1_5V_DETPD67_MC1_5V_DET 0x01 i82365.h 5v detect
8084
 PD67_MC1_MEDIA_ENAPD67_MC1_MEDIA_ENA 0x01 i82365.h 6730: Multimedia enable
8085
 PD67_MC1_VCC_3VPD67_MC1_VCC_3V 0x02 i82365.h 3.3v Vcc
8086
 PD67_MC1_PULSE_MGMTPD67_MC1_PULSE_MGMT 0x04 i82365.h 　
8087
 PD67_MC1_PULSE_IRQPD67_MC1_PULSE_IRQ 0x08 i82365.h 　
8088
 PD67_MC1_SPKR_ENAPD67_MC1_SPKR_ENA 0x10 i82365.h 　
8089
 PD67_MC1_INPACK_ENAPD67_MC1_INPACK_ENA 0x80 i82365.h 　
8090
 PD67_FIFO_EMPTYPD67_FIFO_EMPTY 0x80 i82365.h 　
8091
 PD67_MC2_FREQ_BYPASSPD67_MC2_FREQ_BYPASS 0x01 i82365.h 　
8092
 PD67_MC2_DYNAMIC_MODEPD67_MC2_DYNAMIC_MODE 0x02 i82365.h 　
8093
 PD67_MC2_SUSPENDPD67_MC2_SUSPEND 0x04 i82365.h 　
8094
 PD67_MC2_5V_COREPD67_MC2_5V_CORE 0x08 i82365.h 　
8095
 PD67_MC2_LED_ENAPD67_MC2_LED_ENA 0x10 i82365.h IRQ 12 is LED enable
8096
 PD67_MC2_FAST_PCIPD67_MC2_FAST_PCI 0x10 i82365.h 6729: PCI bus > 25 MHz
8097
 PD67_MC2_3STATE_BIT7PD67_MC2_3STATE_BIT7 0x20 i82365.h Floppy change bit
8098
 PD67_MC2_DMA_MODEPD67_MC2_DMA_MODE 0x40 i82365.h 　
8099
 PD67_MC2_IRQ15_RIPD67_MC2_IRQ15_RI 0x80 i82365.h IRQ 15 is ring enable
8100
 PD67_INFO_SLOTSPD67_INFO_SLOTS 0x20 i82365.h 0 = 1 slot, 1 = 2 slots
8101
 PD67_INFO_CHIP_IDPD67_INFO_CHIP_ID 0xc0 i82365.h 　
8102
 PD67_INFO_REVPD67_INFO_REV 0x1c i82365.h 　
8103
 PD67_TIME_SCALEPD67_TIME_SCALE 0xc0 i82365.h 　
8104
 PD67_TIME_SCALE_1PD67_TIME_SCALE_1 0x00 i82365.h 　
8105
 PD67_TIME_SCALE_16PD67_TIME_SCALE_16 0x40 i82365.h 　
8106
 PD67_TIME_SCALE_256PD67_TIME_SCALE_256 0x80 i82365.h 　
8107
 PD67_TIME_SCALE_4096PD67_TIME_SCALE_4096 0xc0 i82365.h 　
8108
 PD67_TIME_MULTPD67_TIME_MULT 0x3f i82365.h 　
8109
 PD67_DMA_MODEPD67_DMA_MODE 0xc0 i82365.h 　
8110
 PD67_DMA_OFFPD67_DMA_OFF 0x00 i82365.h 　
8111
 PD67_DMA_DREQ_INPACKPD67_DMA_DREQ_INPACK 0x40 i82365.h 　
8112
 PD67_DMA_DREQ_WPPD67_DMA_DREQ_WP 0x80 i82365.h 　
8113
 PD67_DMA_DREQ_BVD2PD67_DMA_DREQ_BVD2 0xc0 i82365.h 　
8114
 PD67_DMA_PULLUPPD67_DMA_PULLUP 0x20 i82365.h Disable socket pullups?
8115
 PD67_EC1_VCC_PWR_LOCKPD67_EC1_VCC_PWR_LOCK 0x01 i82365.h 　
8116
 PD67_EC1_AUTO_PWR_CLEARPD67_EC1_AUTO_PWR_CLEAR 0x02 i82365.h 　
8117
 PD67_EC1_LED_ENAPD67_EC1_LED_ENA 0x04 i82365.h 　
8118
 PD67_EC1_INV_CARD_IRQPD67_EC1_INV_CARD_IRQ 0x08 i82365.h 　
8119
 PD67_EC1_INV_MGMT_IRQPD67_EC1_INV_MGMT_IRQ 0x10 i82365.h 　
8120
 PD67_EC1_PULLUP_CTLPD67_EC1_PULLUP_CTL 0x20 i82365.h 　
8121
 PD67_MC3_IRQ_MASKPD67_MC3_IRQ_MASK 0x03 i82365.h 　
8122
 PD67_MC3_IRQ_PCPCIPD67_MC3_IRQ_PCPCI 0x00 i82365.h 　
8123
 PD67_MC3_IRQ_EXTERNPD67_MC3_IRQ_EXTERN 0x01 i82365.h 　
8124
 PD67_MC3_IRQ_PCIWAYPD67_MC3_IRQ_PCIWAY 0x02 i82365.h 　
8125
 PD67_MC3_IRQ_PCIPD67_MC3_IRQ_PCI 0x03 i82365.h 　
8126
 PD67_MC3_PWR_MASKPD67_MC3_PWR_MASK 0x0c i82365.h 　
8127
 PD67_MC3_PWR_SERIALPD67_MC3_PWR_SERIAL 0x00 i82365.h 　
8128
 PD67_MC3_PWR_TI2202PD67_MC3_PWR_TI2202 0x08 i82365.h 　
8129
 PD67_MC3_PWR_SMBPD67_MC3_PWR_SMB 0x0c i82365.h 　
8130
 PD68_EXT_CTL_2PD68_EXT_CTL_2 0x0b i82365.h 　
8131
 PD68_PCI_SPACEPD68_PCI_SPACE 0x22 i82365.h 　
8132
 PD68_PCCARD_SPACEPD68_PCCARD_SPACE 0x23 i82365.h 　
8133
 PD68_WINDOW_TYPEPD68_WINDOW_TYPE 0x24 i82365.h 　
8134
 PD68_EXT_CSCPD68_EXT_CSC 0x2e i82365.h 　
8135
 PD68_MISC_CTL_4PD68_MISC_CTL_4 0x2f i82365.h 　
8136
 PD68_MISC_CTL_5PD68_MISC_CTL_5 0x30 i82365.h 　
8137
 PD68_MISC_CTL_6PD68_MISC_CTL_6 0x31 i82365.h 　
8138
 PD68_MC3_HW_SUSPPD68_MC3_HW_SUSP 0x10 i82365.h 　
8139
 PD68_MC3_MM_EXPANDPD68_MC3_MM_EXPAND 0x40 i82365.h 　
8140
 PD68_MC3_MM_ARMPD68_MC3_MM_ARM 0x80 i82365.h 　
8141
 PD6832_BCR_MGMT_IRQ_ENAPD6832_BCR_MGMT_IRQ_ENA 0x0800 i82365.h 　
8142
 PD6832_SOCKET_NUMBERPD6832_SOCKET_NUMBER 0x004c i82365.h 8 bit
8143
 MII_BMCRMII_BMCR 0x00 mii.h Basic mode control register
8144
 MII_BMSRMII_BMSR 0x01 mii.h Basic mode status register
8145
 MII_PHYSID1MII_PHYSID1 0x02 mii.h PHYS ID 1
8146
 MII_PHYSID2MII_PHYSID2 0x03 mii.h PHYS ID 2
8147
 MII_ADVERTISEMII_ADVERTISE 0x04 mii.h Advertisement control reg
8148
 MII_LPAMII_LPA 0x05 mii.h Link partner ability reg
8149
 MII_EXPANSIONMII_EXPANSION 0x06 mii.h Expansion register
8150
 MII_CTRL1000MII_CTRL1000 0x09 mii.h 1000BASE-T control
8151
 MII_STAT1000MII_STAT1000 0x0a mii.h 1000BASE-T status
8152
 MII_ESTATUSMII_ESTATUS 0x0f mii.h Extended Status
8153
 MII_DCOUNTERMII_DCOUNTER 0x12 mii.h Disconnect counter
8154
 MII_FCSCOUNTERMII_FCSCOUNTER 0x13 mii.h False carrier counter
8155
 MII_NWAYTESTMII_NWAYTEST 0x14 mii.h N-way auto-neg test reg
8156
 MII_RERRCOUNTERMII_RERRCOUNTER 0x15 mii.h Receive error counter
8157
 MII_SREVISIONMII_SREVISION 0x16 mii.h Silicon revision
8158
 MII_RESV1MII_RESV1 0x17 mii.h Reserved...
8159
 MII_LBRERRORMII_LBRERROR 0x18 mii.h Lpback, rx, bypass error
8160
 MII_PHYADDRMII_PHYADDR 0x19 mii.h PHY address
8161
 MII_RESV2MII_RESV2 0x1a mii.h Reserved...
8162
 MII_TPISTATUSMII_TPISTATUS 0x1b mii.h TPI status for 10mbps
8163
 MII_NCONFIGMII_NCONFIG 0x1c mii.h Network interface config
8164
 BMCR_RESVBMCR_RESV 0x003f mii.h Unused...
8165
 BMCR_SPEED1000BMCR_SPEED1000 0x0040 mii.h MSB of Speed (1000)
8166
 BMCR_CTSTBMCR_CTST 0x0080 mii.h Collision test
8167
 BMCR_FULLDPLXBMCR_FULLDPLX 0x0100 mii.h Full duplex
8168
 BMCR_ANRESTARTBMCR_ANRESTART 0x0200 mii.h Auto negotiation restart
8169
 BMCR_ISOLATEBMCR_ISOLATE 0x0400 mii.h Disconnect DP83840 from MII
8170
 BMCR_PDOWNBMCR_PDOWN 0x0800 mii.h Powerdown the DP83840
8171
 BMCR_ANENABLEBMCR_ANENABLE 0x1000 mii.h Enable auto negotiation
8172
 BMCR_SPEED100BMCR_SPEED100 0x2000 mii.h Select 100Mbps
8173
 BMCR_LOOPBACKBMCR_LOOPBACK 0x4000 mii.h TXD loopback bits
8174
 BMCR_RESETBMCR_RESET 0x8000 mii.h Reset the DP83840
8175
 BMSR_ERCAPBMSR_ERCAP 0x0001 mii.h Ext-reg capability
8176
 BMSR_JCDBMSR_JCD 0x0002 mii.h Jabber detected
8177
 BMSR_LSTATUSBMSR_LSTATUS 0x0004 mii.h Link status
8178
 BMSR_ANEGCAPABLEBMSR_ANEGCAPABLE 0x0008 mii.h Able to do auto-negotiation
8179
 BMSR_RFAULTBMSR_RFAULT 0x0010 mii.h Remote fault detected
8180
 BMSR_ANEGCOMPLETEBMSR_ANEGCOMPLETE 0x0020 mii.h Auto-negotiation complete
8181
 BMSR_RESVBMSR_RESV 0x00c0 mii.h Unused...
8182
 BMSR_ESTATENBMSR_ESTATEN 0x0100 mii.h Extended Status in R15
8183
 BMSR_100HALF2BMSR_100HALF2 0x0200 mii.h Can do 100BASE-T2 HDX
8184
 BMSR_100FULL2BMSR_100FULL2 0x0400 mii.h Can do 100BASE-T2 FDX
8185
 BMSR_10HALFBMSR_10HALF 0x0800 mii.h Can do 10mbps, half-duplex
8186
 BMSR_10FULLBMSR_10FULL 0x1000 mii.h Can do 10mbps, full-duplex
8187
 BMSR_100HALFBMSR_100HALF 0x2000 mii.h Can do 100mbps, half-duplex
8188
 BMSR_100FULLBMSR_100FULL 0x4000 mii.h Can do 100mbps, full-duplex
8189
 BMSR_100BASE4BMSR_100BASE4 0x8000 mii.h Can do 100mbps, 4k packets
8190
 ADVERTISE_SLCTADVERTISE_SLCT 0x001f mii.h Selector bits
8191
 ADVERTISE_CSMAADVERTISE_CSMA 0x0001 mii.h Only selector supported
8192
 ADVERTISE_10HALFADVERTISE_10HALF 0x0020 mii.h Try for 10mbps half-duplex
8193
 ADVERTISE_1000XFULLADVERTISE_1000XFULL 0x0020 mii.h Try for 1000BASE-X full-duplex
8194
 ADVERTISE_10FULLADVERTISE_10FULL 0x0040 mii.h Try for 10mbps full-duplex
8195
 ADVERTISE_1000XHALFADVERTISE_1000XHALF 0x0040 mii.h Try for 1000BASE-X half-duplex
8196
 ADVERTISE_100HALFADVERTISE_100HALF 0x0080 mii.h Try for 100mbps half-duplex
8197
 ADVERTISE_1000XPAUSEADVERTISE_1000XPAUSE 0x0080 mii.h Try for 1000BASE-X pause
8198
 ADVERTISE_100FULLADVERTISE_100FULL 0x0100 mii.h Try for 100mbps full-duplex
8199
 ADVERTISE_1000XPSE_ASYMADVERTISE_1000XPSE_ASYM 0x0100 mii.h Try for 1000BASE-X asym pause
8200
 ADVERTISE_100BASE4ADVERTISE_100BASE4 0x0200 mii.h Try for 100mbps 4k packets
8201
 ADVERTISE_PAUSE_CAPADVERTISE_PAUSE_CAP 0x0400 mii.h Try for pause
8202
 ADVERTISE_PAUSE_ASYMADVERTISE_PAUSE_ASYM 0x0800 mii.h Try for asymetric pause
8203
 ADVERTISE_RESVADVERTISE_RESV 0x1000 mii.h Unused...
8204
 ADVERTISE_RFAULTADVERTISE_RFAULT 0x2000 mii.h Say we can detect faults
8205
 ADVERTISE_LPACKADVERTISE_LPACK 0x4000 mii.h Ack link partners response
8206
 ADVERTISE_NPAGEADVERTISE_NPAGE 0x8000 mii.h Next page bit
8207
 ADVERTISE_FULLADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ ADVERTISE_CSMA) mii.h 　
8208
 ADVERTISE_ALLADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL) mii.h 　
8209
 LPA_SLCTLPA_SLCT 0x001f mii.h Same as advertise selector
8210
 LPA_10HALFLPA_10HALF 0x0020 mii.h Can do 10mbps half-duplex
8211
 LPA_1000XFULLLPA_1000XFULL 0x0020 mii.h Can do 1000BASE-X full-duplex
8212
 LPA_10FULLLPA_10FULL 0x0040 mii.h Can do 10mbps full-duplex
8213
 LPA_1000XHALFLPA_1000XHALF 0x0040 mii.h Can do 1000BASE-X half-duplex
8214
 LPA_100HALFLPA_100HALF 0x0080 mii.h Can do 100mbps half-duplex
8215
 LPA_1000XPAUSELPA_1000XPAUSE 0x0080 mii.h Can do 1000BASE-X pause
8216
 LPA_100FULLLPA_100FULL 0x0100 mii.h Can do 100mbps full-duplex
8217
 LPA_1000XPAUSE_ASYMLPA_1000XPAUSE_ASYM 0x0100 mii.h Can do 1000BASE-X pause asym
8218
 LPA_100BASE4LPA_100BASE4 0x0200 mii.h Can do 100mbps 4k packets
8219
 LPA_PAUSE_CAPLPA_PAUSE_CAP 0x0400 mii.h Can pause
8220
 LPA_PAUSE_ASYMLPA_PAUSE_ASYM 0x0800 mii.h Can pause asymetrically
8221
 LPA_RESVLPA_RESV 0x1000 mii.h Unused...
8222
 LPA_RFAULTLPA_RFAULT 0x2000 mii.h Link partner faulted
8223
 LPA_LPACKLPA_LPACK 0x4000 mii.h Link partner acked us
8224
 LPA_NPAGELPA_NPAGE 0x8000 mii.h Next page bit
8225
 LPA_DUPLEXLPA_DUPLEX (LPA_10FULL | LPA_100FULL) mii.h 　
8226
 LPA_100LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) mii.h 　
8227
 EXPANSION_NWAYEXPANSION_NWAY 0x0001 mii.h Can do N-way auto-nego
8228
 EXPANSION_LCWPEXPANSION_LCWP 0x0002 mii.h Got new RX page code word
8229
 EXPANSION_ENABLENPAGEEXPANSION_ENABLENPAGE 0x0004 mii.h This enables npage words
8230
 EXPANSION_NPCAPABLEEXPANSION_NPCAPABLE 0x0008 mii.h Link partner supports npage
8231
 EXPANSION_MFAULTSEXPANSION_MFAULTS 0x0010 mii.h Multiple faults detected
8232
 EXPANSION_RESVEXPANSION_RESV 0xffe0 mii.h Unused...
8233
 ESTATUS_1000_TFULLESTATUS_1000_TFULL 0x2000 mii.h Can do 1000BT Full
8234
 ESTATUS_1000_THALFESTATUS_1000_THALF 0x1000 mii.h Can do 1000BT Half
8235
 NWAYTEST_RESV1NWAYTEST_RESV1 0x00ff mii.h Unused...
8236
 NWAYTEST_LOOPBACKNWAYTEST_LOOPBACK 0x0100 mii.h Enable loopback for N-way
8237
 NWAYTEST_RESV2NWAYTEST_RESV2 0xfe00 mii.h Unused...
8238
 ADVERTISE_1000FULLADVERTISE_1000FULL 0x0200 mii.h Advertise 1000BASE-T full duplex
8239
 ADVERTISE_1000HALFADVERTISE_1000HALF 0x0100 mii.h Advertise 1000BASE-T half duplex
8240
 LPA_1000LOCALRXOKLPA_1000LOCALRXOK 0x2000 mii.h Link partner local receiver status
8241
 LPA_1000REMRXOKLPA_1000REMRXOK 0x1000 mii.h Link partner remote receiver status
8242
 LPA_1000FULLLPA_1000FULL 0x0800 mii.h Link partner 1000BASE-T full duplex
8243
 LPA_1000HALFLPA_1000HALF 0x0400 mii.h Link partner 1000BASE-T half duplex
8244
 TCP_INITIAL_TIMEOUTTCP_INITIAL_TIMEOUT (3*TICKS_PER_SEC) old_tcp.h 　
8245
 TCP_MAX_TIMEOUTTCP_MAX_TIMEOUT (60*TICKS_PER_SEC) old_tcp.h 　
8246
 TCP_MIN_TIMEOUTTCP_MIN_TIMEOUT (TICKS_PER_SEC) old_tcp.h 　
8247
 TCP_MAX_RETRYTCP_MAX_RETRY 10 old_tcp.h 　
8248
 TCP_MAX_HEADERTCP_MAX_HEADER ((int)sizeof(struct iphdr)+64) old_tcp.h 　
8249
 TCP_MIN_WINDOWTCP_MIN_WINDOW (1500-TCP_MAX_HEADER) old_tcp.h 　
8250
 TCP_MAX_WINDOWTCP_MAX_WINDOW (65535-TCP_MAX_HEADER) old_tcp.h 　
8251
 FINFIN 1 old_tcp.h 　
8252
 SYNSYN 2 old_tcp.h 　
8253
 RSTRST 4 old_tcp.h 　
8254
 PSHPSH 8 old_tcp.h 　
8255
 ACKACK 16 old_tcp.h 　
8256
 URGURG 32 old_tcp.h 　
8257
 _yes__yes_ 1 pcmcia-opts.h 　
8258
 _no__no_ 0 pcmcia-opts.h 　
8259
 SUPPORT_I82365SUPPORT_I82365 (_yes_) pcmcia-opts.h 　
8260
 PCMCIA_SHUTDOWNPCMCIA_SHUTDOWN (_yes_) pcmcia-opts.h 　
8261
 MAP_ATTRMEM_TOMAP_ATTRMEM_TO 0xd0000 pcmcia-opts.h 　
8262
 MAP_ATTRMEM_LENMAP_ATTRMEM_LEN 0x02000 pcmcia-opts.h 　
8263
 PDEBUGPDEBUG 3 pcmcia-opts.h 　
8264
 MAXPCCSOCKSMAXPCCSOCKS 8 pcmcia.h 　
8265
 MAXPCCCONFIGSMAXPCCCONFIGS 8 pcmcia.h 　
8266
 EINVALEINVAL 22 pcmcia.h 　
8267
 SS_WRPROTSS_WRPROT 0x0001 pcmcia.h 　
8268
 SS_CARDLOCKSS_CARDLOCK 0x0002 pcmcia.h 　
8269
 SS_EJECTIONSS_EJECTION 0x0004 pcmcia.h 　
8270
 SS_INSERTIONSS_INSERTION 0x0008 pcmcia.h 　
8271
 SS_BATDEADSS_BATDEAD 0x0010 pcmcia.h 　
8272
 SS_BATWARNSS_BATWARN 0x0020 pcmcia.h 　
8273
 SS_READYSS_READY 0x0040 pcmcia.h 　
8274
 SS_DETECTSS_DETECT 0x0080 pcmcia.h 　
8275
 SS_POWERONSS_POWERON 0x0100 pcmcia.h 　
8276
 SS_GPISS_GPI 0x0200 pcmcia.h 　
8277
 SS_STSCHGSS_STSCHG 0x0400 pcmcia.h 　
8278
 SS_CARDBUSSS_CARDBUS 0x0800 pcmcia.h 　
8279
 SS_3VCARDSS_3VCARD 0x1000 pcmcia.h 　
8280
 SS_XVCARDSS_XVCARD 0x2000 pcmcia.h 　
8281
 SS_PENDINGSS_PENDING 0x4000 pcmcia.h 　
8282
 SS_CAP_PAGE_REGSSS_CAP_PAGE_REGS 0x0001 pcmcia.h 　
8283
 SS_CAP_VIRTUAL_BUSSS_CAP_VIRTUAL_BUS 0x0002 pcmcia.h 　
8284
 SS_CAP_MEM_ALIGNSS_CAP_MEM_ALIGN 0x0004 pcmcia.h 　
8285
 SS_CAP_STATIC_MAPSS_CAP_STATIC_MAP 0x0008 pcmcia.h 　
8286
 SS_CAP_PCCARDSS_CAP_PCCARD 0x4000 pcmcia.h 　
8287
 SS_CAP_CARDBUSSS_CAP_CARDBUS 0x8000 pcmcia.h 　
8288
 SS_PWR_AUTOSS_PWR_AUTO 0x0010 pcmcia.h 　
8289
 SS_IOCARDSS_IOCARD 0x0020 pcmcia.h 　
8290
 SS_RESETSS_RESET 0x0040 pcmcia.h 　
8291
 SS_DMA_MODESS_DMA_MODE 0x0080 pcmcia.h 　
8292
 SS_SPKR_ENASS_SPKR_ENA 0x0100 pcmcia.h 　
8293
 SS_OUTPUT_ENASS_OUTPUT_ENA 0x0200 pcmcia.h 　
8294
 SS_DEBOUNCEDSS_DEBOUNCED 0x0400 pcmcia.h Tell driver that the debounce delay has ended
8295
 SS_ZVCARDSS_ZVCARD 0x0800 pcmcia.h 　
8296
 MAP_ACTIVEMAP_ACTIVE 0x01 pcmcia.h 　
8297
 MAP_16BITMAP_16BIT 0x02 pcmcia.h 　
8298
 MAP_AUTOSZMAP_AUTOSZ 0x04 pcmcia.h 　
8299
 MAP_0WSMAP_0WS 0x08 pcmcia.h 　
8300
 MAP_WRPROTMAP_WRPROT 0x10 pcmcia.h 　
8301
 MAP_ATTRIBMAP_ATTRIB 0x20 pcmcia.h 　
8302
 MAP_USE_WAITMAP_USE_WAIT 0x40 pcmcia.h 　
8303
 MAP_PREFETCHMAP_PREFETCH 0x80 pcmcia.h 　
8304
 MAP_IOSPACEMAP_IOSPACE 0x20 pcmcia.h 　
8305
 NULLNULL ((void *)0) stddef.h 　
8306
 __WCHAR_TYPE____WCHAR_TYPE__ long int stddef.h 　
8307
 __SIZE_TYPE____SIZE_TYPE__ unsigned long stdint.h safe choice on most systems
8308
 AES_BLOCKSIZEAES_BLOCKSIZE 16 aes.h 　
8309
 AES_CTX_SIZEAES_CTX_SIZE sizeof ( struct aes_context ) aes.h 　
8310
 ANSIESC_MAX_PARAMSANSIESC_MAX_PARAMS 4 ansiesc.h 　
8311
 ESCESC 0x1b ansiesc.h 　
8312
 CSICSI "\033[" ansiesc.h 　
8313
 ANSIESC_CUPANSIESC_CUP 'H' ansiesc.h 　
8314
 ANSIESC_EDANSIESC_ED 'J' ansiesc.h 　
8315
 ANSIESC_ED_TO_ENDANSIESC_ED_TO_END 0 ansiesc.h 　
8316
 ANSIESC_ED_FROM_STARTANSIESC_ED_FROM_START 1 ansiesc.h 　
8317
 ANSIESC_ED_ALLANSIESC_ED_ALL 2 ansiesc.h 　
8318
 ANSIESC_SGRANSIESC_SGR 'm' ansiesc.h 　
8319
 AOE_FL_EXTENDEDAOE_FL_EXTENDED 0x40 aoe.h *< LBA48 extended addressing
8320
 AOE_FL_DEV_HEADAOE_FL_DEV_HEAD 0x10 aoe.h *< Device/head flag
8321
 AOE_FL_ASYNCAOE_FL_ASYNC 0x02 aoe.h *< Asynchronous write
8322
 AOE_FL_WRITEAOE_FL_WRITE 0x01 aoe.h *< Write command
8323
 AOE_VERSIONAOE_VERSION 0x10 aoe.h *< Version 1
8324
 AOE_VERSION_MASKAOE_VERSION_MASK 0xf0 aoe.h *< Version part of ver_flags field
8325
 AOE_FL_RESPONSEAOE_FL_RESPONSE 0x08 aoe.h *< Message is a response
8326
 AOE_FL_ERRORAOE_FL_ERROR 0x04 aoe.h *< Command generated an error
8327
 AOE_MAJOR_BROADCASTAOE_MAJOR_BROADCAST 0xffff aoe.h 　
8328
 AOE_MINOR_BROADCASTAOE_MINOR_BROADCAST 0xff aoe.h 　
8329
 AOE_CMD_ATAAOE_CMD_ATA 0x00 aoe.h *< Issue ATA command
8330
 AOE_CMD_CONFIGAOE_CMD_CONFIG 0x01 aoe.h *< Query Config Information
8331
 AOE_TAG_MAGICAOE_TAG_MAGIC 0xebeb0000 aoe.h 　
8332
 AOE_ERR_BAD_COMMANDAOE_ERR_BAD_COMMAND 1 aoe.h *< Unrecognised command code
8333
 AOE_ERR_BAD_PARAMETERAOE_ERR_BAD_PARAMETER 2 aoe.h *< Bad argument parameter
8334
 AOE_ERR_UNAVAILABLEAOE_ERR_UNAVAILABLE 3 aoe.h *< Device unavailable
8335
 AOE_ERR_CONFIG_EXISTSAOE_ERR_CONFIG_EXISTS 4 aoe.h *< Config string present
8336
 AOE_ERR_BAD_VERSIONAOE_ERR_BAD_VERSION 5 aoe.h *< Unsupported version
8337
 AOE_STATUS_ERR_MASKAOE_STATUS_ERR_MASK 0x0f aoe.h *< Error portion of status code
8338
 AOE_STATUS_PENDINGAOE_STATUS_PENDING 0x80 aoe.h *< Command pending
8339
 AOE_MAX_COUNTAOE_MAX_COUNT 2 aoe.h 　
8340
 ARC4_CTX_SIZEARC4_CTX_SIZE sizeof ( struct arc4_ctx ) arc4.h 　
8341
 ARP_NET_PROTOCOLSARP_NET_PROTOCOLS __table ( struct arp_net_protocol, "arp_net_protocols" ) arp.h 　
8342
 __arp_net_protocol__arp_net_protocol __table_entry ( ARP_NET_PROTOCOLS, 01 ) arp.h 　
8343
 ASN1_INTEGERASN1_INTEGER 0x02 asn1.h 　
8344
 ASN1_BIT_STRINGASN1_BIT_STRING 0x03 asn1.h 　
8345
 ASN1_OCTET_STRINGASN1_OCTET_STRING 0x04 asn1.h 　
8346
 ASN1_NULLASN1_NULL 0x05 asn1.h 　
8347
 ASN1_OIDASN1_OID 0x06 asn1.h 　
8348
 ASN1_SEQUENCEASN1_SEQUENCE 0x30 asn1.h 　
8349
 ASN1_IP_ADDRESSASN1_IP_ADDRESS 0x40 asn1.h 　
8350
 ASN1_EXPLICIT_TAGASN1_EXPLICIT_TAG 0xa0 asn1.h 　
8351
 ATA_DEV_OBSOLETEATA_DEV_OBSOLETE 0xa0 ata.h 　
8352
 ATA_DEV_LBAATA_DEV_LBA 0x40 ata.h 　
8353
 ATA_DEV_SLAVEATA_DEV_SLAVE 0x10 ata.h 　
8354
 ATA_DEV_MASTERATA_DEV_MASTER 0x00 ata.h 　
8355
 ATA_DEV_MASKATA_DEV_MASK 0xf0 ata.h 　
8356
 ATA_CMD_READATA_CMD_READ 0x20 ata.h 　
8357
 ATA_CMD_READ_EXTATA_CMD_READ_EXT 0x24 ata.h 　
8358
 ATA_CMD_WRITEATA_CMD_WRITE 0x30 ata.h 　
8359
 ATA_CMD_WRITE_EXTATA_CMD_WRITE_EXT 0x34 ata.h 　
8360
 ATA_CMD_IDENTIFYATA_CMD_IDENTIFY 0xec ata.h 　
8361
 ATA_SUPPORTS_LBA48ATA_SUPPORTS_LBA48 ( 1 << 10 ) ata.h 　
8362
 ATA_SECTOR_SIZEATA_SECTOR_SIZE 512 ata.h 　
8363
 BITMAP_BLKSIZEBITMAP_BLKSIZE ( sizeof ( bitmap_block_t ) * 8 ) bitmap.h 　
8364
 cpu_to_BIT64cpu_to_BIT64 cpu_to_le64 bitops.h 　
8365
 cpu_to_BIT32cpu_to_BIT32 cpu_to_le32 bitops.h 　
8366
 BIT64_to_cpuBIT64_to_cpu le64_to_cpu bitops.h 　
8367
 BIT32_to_cpuBIT32_to_cpu le32_to_cpu bitops.h 　
8368
 cpu_to_BIT64cpu_to_BIT64 cpu_to_be64 bitops.h 　
8369
 cpu_to_BIT32cpu_to_BIT32 cpu_to_be32 bitops.h 　
8370
 BIT64_to_cpuBIT64_to_cpu be64_to_cpu bitops.h 　
8371
 BIT32_to_cpuBIT32_to_cpu be32_to_cpu bitops.h 　
8372
 COMMANDSCOMMANDS __table ( struct command, "commands" ) command.h 　
8373
 __command__command __table_entry ( COMMANDS, 01 ) command.h 　
8374
 CPIO_MAGICCPIO_MAGIC "070701" cpio.h 　
8375
 BUS_TYPE_PCIBUS_TYPE_PCI 1 device.h 　
8376
 BUS_TYPE_ISAPNPBUS_TYPE_ISAPNP 2 device.h 　
8377
 BUS_TYPE_EISABUS_TYPE_EISA 3 device.h 　
8378
 BUS_TYPE_MCABUS_TYPE_MCA 4 device.h 　
8379
 BUS_TYPE_ISABUS_TYPE_ISA 5 device.h 　
8380
 ROOT_DEVICESROOT_DEVICES __table ( struct root_device, "root_devices" ) device.h 　
8381
 __root_device__root_device __table_entry ( ROOT_DEVICES, 01 ) device.h 　
8382
 BOOTPS_PORTBOOTPS_PORT 67 dhcp.h 　
8383
 BOOTPC_PORTBOOTPC_PORT 68 dhcp.h 　
8384
 PXE_PORTPXE_PORT 4011 dhcp.h 　
8385
 DHCP_PADDHCP_PAD 0 dhcp.h 　
8386
 DHCP_MIN_OPTIONDHCP_MIN_OPTION 1 dhcp.h 　
8387
 DHCP_SUBNET_MASKDHCP_SUBNET_MASK 1 dhcp.h 　
8388
 DHCP_ROUTERSDHCP_ROUTERS 3 dhcp.h 　
8389
 DHCP_DNS_SERVERSDHCP_DNS_SERVERS 6 dhcp.h 　
8390
 DHCP_LOG_SERVERSDHCP_LOG_SERVERS 7 dhcp.h 　
8391
 DHCP_HOST_NAMEDHCP_HOST_NAME 12 dhcp.h 　
8392
 DHCP_DOMAIN_NAMEDHCP_DOMAIN_NAME 15 dhcp.h 　
8393
 DHCP_ROOT_PATHDHCP_ROOT_PATH 17 dhcp.h 　
8394
 DHCP_VENDOR_ENCAPDHCP_VENDOR_ENCAP 43 dhcp.h 　
8395
 DHCP_PXE_DISCOVERY_CONTROLDHCP_PXE_DISCOVERY_CONTROL DHCP_ENCAP_OPT ( DHCP_VENDOR_ENCAP, 6 ) dhcp.h 　
8396
 DHCP_PXE_BOOT_SERVER_MCASTDHCP_PXE_BOOT_SERVER_MCAST DHCP_ENCAP_OPT ( DHCP_VENDOR_ENCAP, 7 ) dhcp.h 　
8397
 DHCP_PXE_BOOT_SERVERSDHCP_PXE_BOOT_SERVERS DHCP_ENCAP_OPT ( DHCP_VENDOR_ENCAP, 8 ) dhcp.h 　
8398
 DHCP_PXE_BOOT_MENUDHCP_PXE_BOOT_MENU DHCP_ENCAP_OPT ( DHCP_VENDOR_ENCAP, 9 ) dhcp.h 　
8399
 DHCP_PXE_BOOT_MENU_PROMPTDHCP_PXE_BOOT_MENU_PROMPT DHCP_ENCAP_OPT ( DHCP_VENDOR_ENCAP, 10 ) dhcp.h 　
8400
 DHCP_PXE_BOOT_MENU_ITEMDHCP_PXE_BOOT_MENU_ITEM DHCP_ENCAP_OPT ( DHCP_VENDOR_ENCAP, 71 ) dhcp.h 　
8401
 DHCP_REQUESTED_ADDRESSDHCP_REQUESTED_ADDRESS 50 dhcp.h 　
8402
 DHCP_LEASE_TIMEDHCP_LEASE_TIME 51 dhcp.h 　
8403
 DHCP_OPTION_OVERLOADDHCP_OPTION_OVERLOAD 52 dhcp.h 　
8404
 DHCP_OPTION_OVERLOAD_FILEDHCP_OPTION_OVERLOAD_FILE 1 dhcp.h 　
8405
 DHCP_OPTION_OVERLOAD_SNAMEDHCP_OPTION_OVERLOAD_SNAME 2 dhcp.h 　
8406
 DHCP_MESSAGE_TYPEDHCP_MESSAGE_TYPE 53 dhcp.h 　
8407
 DHCPNONEDHCPNONE 0 dhcp.h 　
8408
 DHCPDISCOVERDHCPDISCOVER 1 dhcp.h 　
8409
 DHCPOFFERDHCPOFFER 2 dhcp.h 　
8410
 DHCPREQUESTDHCPREQUEST 3 dhcp.h 　
8411
 DHCPDECLINEDHCPDECLINE 4 dhcp.h 　
8412
 DHCPACKDHCPACK 5 dhcp.h 　
8413
 DHCPNAKDHCPNAK 6 dhcp.h 　
8414
 DHCPRELEASEDHCPRELEASE 7 dhcp.h 　
8415
 DHCPINFORMDHCPINFORM 8 dhcp.h 　
8416
 DHCP_SERVER_IDENTIFIERDHCP_SERVER_IDENTIFIER 54 dhcp.h 　
8417
 DHCP_PARAMETER_REQUEST_LISTDHCP_PARAMETER_REQUEST_LIST 55 dhcp.h 　
8418
 DHCP_MAX_MESSAGE_SIZEDHCP_MAX_MESSAGE_SIZE 57 dhcp.h 　
8419
 DHCP_VENDOR_CLASS_IDDHCP_VENDOR_CLASS_ID 60 dhcp.h 　
8420
 DHCP_CLIENT_IDDHCP_CLIENT_ID 61 dhcp.h 　
8421
 DHCP_TFTP_SERVER_NAMEDHCP_TFTP_SERVER_NAME 66 dhcp.h 　
8422
 DHCP_BOOTFILE_NAMEDHCP_BOOTFILE_NAME 67 dhcp.h 　
8423
 DHCP_USER_CLASS_IDDHCP_USER_CLASS_ID 77 dhcp.h 　
8424
 DHCP_CLIENT_ARCHITECTUREDHCP_CLIENT_ARCHITECTURE 93 dhcp.h 　
8425
 DHCP_CLIENT_NDIDHCP_CLIENT_NDI 94 dhcp.h 　
8426
 DHCP_CLIENT_UUIDDHCP_CLIENT_UUID 97 dhcp.h 　
8427
 DHCP_CLIENT_UUID_TYPEDHCP_CLIENT_UUID_TYPE 0 dhcp.h 　
8428
 DHCP_EB_ENCAPDHCP_EB_ENCAP 175 dhcp.h 　
8429
 DHCP_EB_PRIORITYDHCP_EB_PRIORITY DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0x01 ) dhcp.h 　
8430
 DHCP_EB_YIADDRDHCP_EB_YIADDR DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0x02 ) dhcp.h 　
8431
 DHCP_EB_SIADDRDHCP_EB_SIADDR DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0x03 ) dhcp.h 　
8432
 DHCP_EB_KEEP_SANDHCP_EB_KEEP_SAN DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0x08 ) dhcp.h 　
8433
 DHCP_EB_NO_PXEDHCPDHCP_EB_NO_PXEDHCP DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xb0 ) dhcp.h 　
8434
 DHCP_EB_BUS_IDDHCP_EB_BUS_ID DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xb1 ) dhcp.h 　
8435
 DHCP_EB_USE_CACHEDDHCP_EB_USE_CACHED DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xb2 ) dhcp.h 　
8436
 DHCP_EB_BIOS_DRIVEDHCP_EB_BIOS_DRIVE DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xbd ) dhcp.h 　
8437
 DHCP_EB_USERNAMEDHCP_EB_USERNAME DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xbe ) dhcp.h 　
8438
 DHCP_EB_PASSWORDDHCP_EB_PASSWORD DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xbf ) dhcp.h 　
8439
 DHCP_EB_REVERSE_USERNAMEDHCP_EB_REVERSE_USERNAME DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xc0 ) dhcp.h 　
8440
 DHCP_EB_REVERSE_PASSWORDDHCP_EB_REVERSE_PASSWORD DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xc1 ) dhcp.h 　
8441
 DHCP_EB_VERSIONDHCP_EB_VERSION DHCP_ENCAP_OPT ( DHCP_EB_ENCAP, 0xeb ) dhcp.h 　
8442
 DHCP_ISCSI_PRIMARY_TARGET_IQNDHCP_ISCSI_PRIMARY_TARGET_IQN 201 dhcp.h 　
8443
 DHCP_ISCSI_SECONDARY_TARGET_IQNDHCP_ISCSI_SECONDARY_TARGET_IQN 202 dhcp.h 　
8444
 DHCP_ISCSI_INITIATOR_IQNDHCP_ISCSI_INITIATOR_IQN 203 dhcp.h 　
8445
 DHCP_MAX_OPTIONDHCP_MAX_OPTION 254 dhcp.h 　
8446
 DHCP_ENDDHCP_END 255 dhcp.h 　
8447
 DHCP_OPTION_HEADER_LENDHCP_OPTION_HEADER_LEN ( offsetof ( struct dhcp_option, data ) ) dhcp.h 　
8448
 DHCP_MAX_LENDHCP_MAX_LEN 0xff dhcp.h 　
8449
 BOOTP_REQUESTBOOTP_REQUEST 1 dhcp.h 　
8450
 BOOTP_REPLYBOOTP_REPLY 2 dhcp.h 　
8451
 BOOTP_FL_BROADCASTBOOTP_FL_BROADCAST 0x8000 dhcp.h 　
8452
 DHCP_MAGIC_COOKIEDHCP_MAGIC_COOKIE 0x63825363UL dhcp.h 　
8453
 DHCP_MIN_LENDHCP_MIN_LEN 552 dhcp.h 　
8454
 DHCP_MIN_TIMEOUTDHCP_MIN_TIMEOUT ( 1 * TICKS_PER_SEC ) dhcp.h 　
8455
 DHCP_MAX_TIMEOUTDHCP_MAX_TIMEOUT ( 10 * TICKS_PER_SEC ) dhcp.h 　
8456
 PROXYDHCP_MAX_TIMEOUTPROXYDHCP_MAX_TIMEOUT ( 2 * TICKS_PER_SEC ) dhcp.h 　
8457
 PXEBS_MAX_TIMEOUTPXEBS_MAX_TIMEOUT ( 3 * TICKS_PER_SEC ) dhcp.h 　
8458
 DHCP_SETTINGS_NAMEDHCP_SETTINGS_NAME "dhcp" dhcp.h 　
8459
 PROXYDHCP_SETTINGS_NAMEPROXYDHCP_SETTINGS_NAME "proxydhcp" dhcp.h 　
8460
 PXEBS_SETTINGS_NAMEPXEBS_SETTINGS_NAME "pxebs" dhcp.h 　
8461
 DNS_TYPE_ADNS_TYPE_A 1 dns.h 　
8462
 DNS_TYPE_CNAMEDNS_TYPE_CNAME 5 dns.h 　
8463
 DNS_TYPE_ANYDNS_TYPE_ANY 255 dns.h 　
8464
 DNS_CLASS_INDNS_CLASS_IN 1 dns.h 　
8465
 DNS_CLASS_CSDNS_CLASS_CS 2 dns.h 　
8466
 DNS_CLASS_CHDNS_CLASS_CH 3 dns.h 　
8467
 DNS_CLASS_HSDNS_CLASS_HS 4 dns.h 　
8468
 DNS_FLAG_QUERYDNS_FLAG_QUERY ( 0x00 << 15 ) dns.h 　
8469
 DNS_FLAG_RESPONSEDNS_FLAG_RESPONSE ( 0x01 << 15 ) dns.h 　
8470
 DNS_FLAG_OPCODE_QUERYDNS_FLAG_OPCODE_QUERY ( 0x00 << 11 ) dns.h 　
8471
 DNS_FLAG_OPCODE_IQUERYDNS_FLAG_OPCODE_IQUERY ( 0x01 << 11 ) dns.h 　
8472
 DNS_FLAG_OPCODE_STATUSDNS_FLAG_OPCODE_STATUS ( 0x02 << 11 ) dns.h 　
8473
 DNS_FLAG_RDDNS_FLAG_RD ( 0x01 << 8 ) dns.h 　
8474
 DNS_FLAG_RADNS_FLAG_RA ( 0x01 << 7 ) dns.h 　
8475
 DNS_FLAG_RCODE_OKDNS_FLAG_RCODE_OK ( 0x00 << 0 ) dns.h 　
8476
 DNS_FLAG_RCODE_NXDNS_FLAG_RCODE_NX ( 0x03 << 0 ) dns.h 　
8477
 DNS_PORTDNS_PORT 53 dns.h 　
8478
 DNS_MAX_RETRIESDNS_MAX_RETRIES 3 dns.h 　
8479
 DNS_MAX_CNAME_RECURSIONDNS_MAX_CNAME_RECURSION 0x30 dns.h 　
8480
 EAPOL_TYPE_EAPEAPOL_TYPE_EAP 0 eapol.h *< EAP authentication handshake packet
8481
 EAPOL_TYPE_STARTEAPOL_TYPE_START 1 eapol.h *< Request by Peer to begin (no data)
8482
 EAPOL_TYPE_LOGOFFEAPOL_TYPE_LOGOFF 2 eapol.h *< Request by Peer to terminate (no data)
8483
 EAPOL_TYPE_KEYEAPOL_TYPE_KEY 3 eapol.h *< EAPOL-Key packet
8484
 EAPOL_THIS_VERSIONEAPOL_THIS_VERSION 1 eapol.h 　
8485
 EAPOL_HDR_LENEAPOL_HDR_LEN 4 eapol.h 　
8486
 EAPOL_HANDLERSEAPOL_HANDLERS __table ( struct eapol_handler, "eapol_handlers" ) eapol.h 　
8487
 __eapol_handler__eapol_handler __table_entry ( EAPOL_HANDLERS, 01 ) eapol.h 　
8488
 EISA_MIN_SLOTEISA_MIN_SLOT (0x1) eisa.h 　
8489
 EISA_MAX_SLOTEISA_MAX_SLOT (0xf) eisa.h Must be 2^n - 1
8490
 EISA_VENDOR_IDEISA_VENDOR_ID ( 0xc80 ) eisa.h 　
8491
 EISA_PROD_IDEISA_PROD_ID ( 0xc82 ) eisa.h 　
8492
 EISA_GLOBAL_CONFIGEISA_GLOBAL_CONFIG ( 0xc84 ) eisa.h 　
8493
 EISA_CMD_RESETEISA_CMD_RESET ( 1 << 2 ) eisa.h 　
8494
 EISA_CMD_ENABLEEISA_CMD_ENABLE ( 1 << 0 ) eisa.h 　
8495
 EISA_DRIVERSEISA_DRIVERS __table ( struct eisa_driver, "eisa_drivers" ) eisa.h 　
8496
 __eisa_driver__eisa_driver __table_entry ( EISA_DRIVERS, 01 ) eisa.h 　
8497
 ERRFILE_COREERRFILE_CORE 0x00002000 errfile.h *< Core code
8498
 ERRFILE_DRIVERERRFILE_DRIVER 0x00004000 errfile.h *< Driver code
8499
 ERRFILE_NETERRFILE_NET 0x00006000 errfile.h *< Networking code
8500
 ERRFILE_IMAGEERRFILE_IMAGE 0x00008000 errfile.h *< Image code
8501
 ERRFILE_OTHERERRFILE_OTHER 0x0000e000 errfile.h *< Any other code
8502
 ERRFILE_ARCHERRFILE_ARCH 0x00800000 errfile.h 　
8503
 ERRFILE_asprintfERRFILE_asprintf ( ERRFILE_CORE | 0x00000000 ) errfile.h 　
8504
 ERRFILE_downloaderERRFILE_downloader ( ERRFILE_CORE | 0x00010000 ) errfile.h 　
8505
 ERRFILE_execERRFILE_exec ( ERRFILE_CORE | 0x00020000 ) errfile.h 　
8506
 ERRFILE_hwERRFILE_hw ( ERRFILE_CORE | 0x00030000 ) errfile.h 　
8507
 ERRFILE_iobufERRFILE_iobuf ( ERRFILE_CORE | 0x00040000 ) errfile.h 　
8508
 ERRFILE_jobERRFILE_job ( ERRFILE_CORE | 0x00050000 ) errfile.h 　
8509
 ERRFILE_linebufERRFILE_linebuf ( ERRFILE_CORE | 0x00060000 ) errfile.h 　
8510
 ERRFILE_monojobERRFILE_monojob ( ERRFILE_CORE | 0x00070000 ) errfile.h 　
8511
 ERRFILE_nvoERRFILE_nvo ( ERRFILE_CORE | 0x00080000 ) errfile.h 　
8512
 ERRFILE_openERRFILE_open ( ERRFILE_CORE | 0x00090000 ) errfile.h 　
8513
 ERRFILE_posix_ioERRFILE_posix_io ( ERRFILE_CORE | 0x000a0000 ) errfile.h 　
8514
 ERRFILE_resolvERRFILE_resolv ( ERRFILE_CORE | 0x000b0000 ) errfile.h 　
8515
 ERRFILE_settingsERRFILE_settings ( ERRFILE_CORE | 0x000c0000 ) errfile.h 　
8516
 ERRFILE_vsprintfERRFILE_vsprintf ( ERRFILE_CORE | 0x000d0000 ) errfile.h 　
8517
 ERRFILE_xferERRFILE_xfer ( ERRFILE_CORE | 0x000e0000 ) errfile.h 　
8518
 ERRFILE_bitmapERRFILE_bitmap ( ERRFILE_CORE | 0x000f0000 ) errfile.h 　
8519
 ERRFILE_base64ERRFILE_base64 ( ERRFILE_CORE | 0x00100000 ) errfile.h 　
8520
 ERRFILE_base16ERRFILE_base16 ( ERRFILE_CORE | 0x00110000 ) errfile.h 　
8521
 ERRFILE_eisaERRFILE_eisa ( ERRFILE_DRIVER | 0x00000000 ) errfile.h 　
8522
 ERRFILE_isaERRFILE_isa ( ERRFILE_DRIVER | 0x00010000 ) errfile.h 　
8523
 ERRFILE_isapnpERRFILE_isapnp ( ERRFILE_DRIVER | 0x00020000 ) errfile.h 　
8524
 ERRFILE_mcaERRFILE_mca ( ERRFILE_DRIVER | 0x00030000 ) errfile.h 　
8525
 ERRFILE_pciERRFILE_pci ( ERRFILE_DRIVER | 0x00040000 ) errfile.h 　
8526
 ERRFILE_nvsERRFILE_nvs ( ERRFILE_DRIVER | 0x00100000 ) errfile.h 　
8527
 ERRFILE_spiERRFILE_spi ( ERRFILE_DRIVER | 0x00110000 ) errfile.h 　
8528
 ERRFILE_i2c_bitERRFILE_i2c_bit ( ERRFILE_DRIVER | 0x00120000 ) errfile.h 　
8529
 ERRFILE_spi_bitERRFILE_spi_bit ( ERRFILE_DRIVER | 0x00130000 ) errfile.h 　
8530
 ERRFILE_3c509ERRFILE_3c509 ( ERRFILE_DRIVER | 0x00200000 ) errfile.h 　
8531
 ERRFILE_bnx2ERRFILE_bnx2 ( ERRFILE_DRIVER | 0x00210000 ) errfile.h 　
8532
 ERRFILE_cs89x0ERRFILE_cs89x0 ( ERRFILE_DRIVER | 0x00220000 ) errfile.h 　
8533
 ERRFILE_eeproERRFILE_eepro ( ERRFILE_DRIVER | 0x00230000 ) errfile.h 　
8534
 ERRFILE_etherfabricERRFILE_etherfabric ( ERRFILE_DRIVER | 0x00240000 ) errfile.h 　
8535
 ERRFILE_legacyERRFILE_legacy ( ERRFILE_DRIVER | 0x00250000 ) errfile.h 　
8536
 ERRFILE_natsemiERRFILE_natsemi ( ERRFILE_DRIVER | 0x00260000 ) errfile.h 　
8537
 ERRFILE_pnicERRFILE_pnic ( ERRFILE_DRIVER | 0x00270000 ) errfile.h 　
8538
 ERRFILE_prism2_pciERRFILE_prism2_pci ( ERRFILE_DRIVER | 0x00280000 ) errfile.h 　
8539
 ERRFILE_prism2_plxERRFILE_prism2_plx ( ERRFILE_DRIVER | 0x00290000 ) errfile.h 　
8540
 ERRFILE_rtl8139ERRFILE_rtl8139 ( ERRFILE_DRIVER | 0x002a0000 ) errfile.h 　
8541
 ERRFILE_smc9000ERRFILE_smc9000 ( ERRFILE_DRIVER | 0x002b0000 ) errfile.h 　
8542
 ERRFILE_tg3ERRFILE_tg3 ( ERRFILE_DRIVER | 0x002c0000 ) errfile.h 　
8543
 ERRFILE_3c509_eisaERRFILE_3c509_eisa ( ERRFILE_DRIVER | 0x002d0000 ) errfile.h 　
8544
 ERRFILE_3c515ERRFILE_3c515 ( ERRFILE_DRIVER | 0x002e0000 ) errfile.h 　
8545
 ERRFILE_3c529ERRFILE_3c529 ( ERRFILE_DRIVER | 0x002f0000 ) errfile.h 　
8546
 ERRFILE_3c595ERRFILE_3c595 ( ERRFILE_DRIVER | 0x00300000 ) errfile.h 　
8547
 ERRFILE_3c5x9ERRFILE_3c5x9 ( ERRFILE_DRIVER | 0x00310000 ) errfile.h 　
8548
 ERRFILE_3c90xERRFILE_3c90x ( ERRFILE_DRIVER | 0x00320000 ) errfile.h 　
8549
 ERRFILE_amd8111eERRFILE_amd8111e ( ERRFILE_DRIVER | 0x00330000 ) errfile.h 　
8550
 ERRFILE_davicomERRFILE_davicom ( ERRFILE_DRIVER | 0x00340000 ) errfile.h 　
8551
 ERRFILE_depcaERRFILE_depca ( ERRFILE_DRIVER | 0x00350000 ) errfile.h 　
8552
 ERRFILE_dmfeERRFILE_dmfe ( ERRFILE_DRIVER | 0x00360000 ) errfile.h 　
8553
 ERRFILE_eepro100ERRFILE_eepro100 ( ERRFILE_DRIVER | 0x00380000 ) errfile.h 　
8554
 ERRFILE_epic100ERRFILE_epic100 ( ERRFILE_DRIVER | 0x00390000 ) errfile.h 　
8555
 ERRFILE_forcedethERRFILE_forcedeth ( ERRFILE_DRIVER | 0x003a0000 ) errfile.h 　
8556
 ERRFILE_mtd80xERRFILE_mtd80x ( ERRFILE_DRIVER | 0x003b0000 ) errfile.h 　
8557
 ERRFILE_ns83820ERRFILE_ns83820 ( ERRFILE_DRIVER | 0x003c0000 ) errfile.h 　
8558
 ERRFILE_ns8390ERRFILE_ns8390 ( ERRFILE_DRIVER | 0x003d0000 ) errfile.h 　
8559
 ERRFILE_pcnet32ERRFILE_pcnet32 ( ERRFILE_DRIVER | 0x003e0000 ) errfile.h 　
8560
 ERRFILE_r8169ERRFILE_r8169 ( ERRFILE_DRIVER | 0x003f0000 ) errfile.h 　
8561
 ERRFILE_sis900ERRFILE_sis900 ( ERRFILE_DRIVER | 0x00400000 ) errfile.h 　
8562
 ERRFILE_sundanceERRFILE_sundance ( ERRFILE_DRIVER | 0x00410000 ) errfile.h 　
8563
 ERRFILE_tlanERRFILE_tlan ( ERRFILE_DRIVER | 0x00420000 ) errfile.h 　
8564
 ERRFILE_tulipERRFILE_tulip ( ERRFILE_DRIVER | 0x00430000 ) errfile.h 　
8565
 ERRFILE_via_rhineERRFILE_via_rhine ( ERRFILE_DRIVER | 0x00440000 ) errfile.h 　
8566
 ERRFILE_via_velocityERRFILE_via_velocity ( ERRFILE_DRIVER | 0x00450000 ) errfile.h 　
8567
 ERRFILE_w89c840ERRFILE_w89c840 ( ERRFILE_DRIVER | 0x00460000 ) errfile.h 　
8568
 ERRFILE_ipoibERRFILE_ipoib ( ERRFILE_DRIVER | 0x00470000 ) errfile.h 　
8569
 ERRFILE_e1000_mainERRFILE_e1000_main ( ERRFILE_DRIVER | 0x00480000 ) errfile.h 　
8570
 ERRFILE_e1000e_mainERRFILE_e1000e_main ( ERRFILE_DRIVER | 0x00490000 ) errfile.h 　
8571
 ERRFILE_mtnicERRFILE_mtnic ( ERRFILE_DRIVER | 0x004a0000 ) errfile.h 　
8572
 ERRFILE_phantomERRFILE_phantom ( ERRFILE_DRIVER | 0x004b0000 ) errfile.h 　
8573
 ERRFILE_ne2k_isaERRFILE_ne2k_isa ( ERRFILE_DRIVER | 0x004c0000 ) errfile.h 　
8574
 ERRFILE_b44ERRFILE_b44 ( ERRFILE_DRIVER | 0x004d0000 ) errfile.h 　
8575
 ERRFILE_rtl818xERRFILE_rtl818x ( ERRFILE_DRIVER | 0x004e0000 ) errfile.h 　
8576
 ERRFILE_sky2ERRFILE_sky2 ( ERRFILE_DRIVER | 0x004f0000 ) errfile.h 　
8577
 ERRFILE_ath5kERRFILE_ath5k ( ERRFILE_DRIVER | 0x00500000 ) errfile.h 　
8578
 ERRFILE_atl1eERRFILE_atl1e ( ERRFILE_DRIVER | 0x00510000 ) errfile.h 　
8579
 ERRFILE_sis190ERRFILE_sis190 ( ERRFILE_DRIVER | 0x00520000 ) errfile.h 　
8580
 ERRFILE_myri10geERRFILE_myri10ge ( ERRFILE_DRIVER | 0x00530000 ) errfile.h 　
8581
 ERRFILE_skgeERRFILE_skge ( ERRFILE_DRIVER | 0x00540000 ) errfile.h 　
8582
 ERRFILE_vxge_mainERRFILE_vxge_main ( ERRFILE_DRIVER | 0x00550000 ) errfile.h 　
8583
 ERRFILE_vxge_configERRFILE_vxge_config ( ERRFILE_DRIVER | 0x00560000 ) errfile.h 　
8584
 ERRFILE_vxge_trafficERRFILE_vxge_traffic ( ERRFILE_DRIVER | 0x00570000 ) errfile.h 　
8585
 ERRFILE_igb_mainERRFILE_igb_main ( ERRFILE_DRIVER | 0x00580000 ) errfile.h 　
8586
 ERRFILE_snpnetERRFILE_snpnet ( ERRFILE_DRIVER | 0x00590000 ) errfile.h 　
8587
 ERRFILE_snponlyERRFILE_snponly ( ERRFILE_DRIVER | 0x005a0000 ) errfile.h 　
8588
 ERRFILE_jmeERRFILE_jme ( ERRFILE_DRIVER | 0x005b0000 ) errfile.h 　
8589
 ERRFILE_scsiERRFILE_scsi ( ERRFILE_DRIVER | 0x00700000 ) errfile.h 　
8590
 ERRFILE_arbelERRFILE_arbel ( ERRFILE_DRIVER | 0x00710000 ) errfile.h 　
8591
 ERRFILE_hermonERRFILE_hermon ( ERRFILE_DRIVER | 0x00720000 ) errfile.h 　
8592
 ERRFILE_lindaERRFILE_linda ( ERRFILE_DRIVER | 0x00730000 ) errfile.h 　
8593
 ERRFILE_ataERRFILE_ata ( ERRFILE_DRIVER | 0x00740000 ) errfile.h 　
8594
 ERRFILE_srpERRFILE_srp ( ERRFILE_DRIVER | 0x00750000 ) errfile.h 　
8595
 ERRFILE_aoeERRFILE_aoe ( ERRFILE_NET | 0x00000000 ) errfile.h 　
8596
 ERRFILE_arpERRFILE_arp ( ERRFILE_NET | 0x00010000 ) errfile.h 　
8597
 ERRFILE_dhcpoptsERRFILE_dhcpopts ( ERRFILE_NET | 0x00020000 ) errfile.h 　
8598
 ERRFILE_ethernetERRFILE_ethernet ( ERRFILE_NET | 0x00030000 ) errfile.h 　
8599
 ERRFILE_icmpv6ERRFILE_icmpv6 ( ERRFILE_NET | 0x00040000 ) errfile.h 　
8600
 ERRFILE_ipv4ERRFILE_ipv4 ( ERRFILE_NET | 0x00050000 ) errfile.h 　
8601
 ERRFILE_ipv6ERRFILE_ipv6 ( ERRFILE_NET | 0x00060000 ) errfile.h 　
8602
 ERRFILE_ndpERRFILE_ndp ( ERRFILE_NET | 0x00070000 ) errfile.h 　
8603
 ERRFILE_netdeviceERRFILE_netdevice ( ERRFILE_NET | 0x00080000 ) errfile.h 　
8604
 ERRFILE_nullnetERRFILE_nullnet ( ERRFILE_NET | 0x00090000 ) errfile.h 　
8605
 ERRFILE_tcpERRFILE_tcp ( ERRFILE_NET | 0x000a0000 ) errfile.h 　
8606
 ERRFILE_ftpERRFILE_ftp ( ERRFILE_NET | 0x000b0000 ) errfile.h 　
8607
 ERRFILE_httpERRFILE_http ( ERRFILE_NET | 0x000c0000 ) errfile.h 　
8608
 ERRFILE_iscsiERRFILE_iscsi ( ERRFILE_NET | 0x000d0000 ) errfile.h 　
8609
 ERRFILE_tcpipERRFILE_tcpip ( ERRFILE_NET | 0x000e0000 ) errfile.h 　
8610
 ERRFILE_udpERRFILE_udp ( ERRFILE_NET | 0x000f0000 ) errfile.h 　
8611
 ERRFILE_dhcpERRFILE_dhcp ( ERRFILE_NET | 0x00100000 ) errfile.h 　
8612
 ERRFILE_dnsERRFILE_dns ( ERRFILE_NET | 0x00110000 ) errfile.h 　
8613
 ERRFILE_tftpERRFILE_tftp ( ERRFILE_NET | 0x00120000 ) errfile.h 　
8614
 ERRFILE_infinibandERRFILE_infiniband ( ERRFILE_NET | 0x00130000 ) errfile.h 　
8615
 ERRFILE_netdev_settingsERRFILE_netdev_settings ( ERRFILE_NET | 0x00140000 ) errfile.h 　
8616
 ERRFILE_dhcppktERRFILE_dhcppkt ( ERRFILE_NET | 0x00150000 ) errfile.h 　
8617
 ERRFILE_slamERRFILE_slam ( ERRFILE_NET | 0x00160000 ) errfile.h 　
8618
 ERRFILE_ib_smaERRFILE_ib_sma ( ERRFILE_NET | 0x00170000 ) errfile.h 　
8619
 ERRFILE_ib_packetERRFILE_ib_packet ( ERRFILE_NET | 0x00180000 ) errfile.h 　
8620
 ERRFILE_icmpERRFILE_icmp ( ERRFILE_NET | 0x00190000 ) errfile.h 　
8621
 ERRFILE_ib_qsetERRFILE_ib_qset ( ERRFILE_NET | 0x001a0000 ) errfile.h 　
8622
 ERRFILE_ib_gmaERRFILE_ib_gma ( ERRFILE_NET | 0x001b0000 ) errfile.h 　
8623
 ERRFILE_ib_pathrecERRFILE_ib_pathrec ( ERRFILE_NET | 0x001c0000 ) errfile.h 　
8624
 ERRFILE_ib_mcastERRFILE_ib_mcast ( ERRFILE_NET | 0x001d0000 ) errfile.h 　
8625
 ERRFILE_ib_cmERRFILE_ib_cm ( ERRFILE_NET | 0x001e0000 ) errfile.h 　
8626
 ERRFILE_net80211ERRFILE_net80211 ( ERRFILE_NET | 0x001f0000 ) errfile.h 　
8627
 ERRFILE_ib_miERRFILE_ib_mi ( ERRFILE_NET | 0x00200000 ) errfile.h 　
8628
 ERRFILE_ib_cmrcERRFILE_ib_cmrc ( ERRFILE_NET | 0x00210000 ) errfile.h 　
8629
 ERRFILE_ib_srpERRFILE_ib_srp ( ERRFILE_NET | 0x00220000 ) errfile.h 　
8630
 ERRFILE_sec80211ERRFILE_sec80211 ( ERRFILE_NET | 0x00230000 ) errfile.h 　
8631
 ERRFILE_wepERRFILE_wep ( ERRFILE_NET | 0x00240000 ) errfile.h 　
8632
 ERRFILE_eapolERRFILE_eapol ( ERRFILE_NET | 0x00250000 ) errfile.h 　
8633
 ERRFILE_wpaERRFILE_wpa ( ERRFILE_NET | 0x00260000 ) errfile.h 　
8634
 ERRFILE_wpa_pskERRFILE_wpa_psk ( ERRFILE_NET | 0x00270000 ) errfile.h 　
8635
 ERRFILE_wpa_tkipERRFILE_wpa_tkip ( ERRFILE_NET | 0x00280000 ) errfile.h 　
8636
 ERRFILE_wpa_ccmpERRFILE_wpa_ccmp ( ERRFILE_NET | 0x00290000 ) errfile.h 　
8637
 ERRFILE_imageERRFILE_image ( ERRFILE_IMAGE | 0x00000000 ) errfile.h 　
8638
 ERRFILE_elfERRFILE_elf ( ERRFILE_IMAGE | 0x00010000 ) errfile.h 　
8639
 ERRFILE_scriptERRFILE_script ( ERRFILE_IMAGE | 0x00020000 ) errfile.h 　
8640
 ERRFILE_segmentERRFILE_segment ( ERRFILE_IMAGE | 0x00030000 ) errfile.h 　
8641
 ERRFILE_efi_imageERRFILE_efi_image ( ERRFILE_IMAGE | 0x00040000 ) errfile.h 　
8642
 ERRFILE_embeddedERRFILE_embedded ( ERRFILE_IMAGE | 0x00050000 ) errfile.h 　
8643
 ERRFILE_asn1ERRFILE_asn1 ( ERRFILE_OTHER | 0x00000000 ) errfile.h 　
8644
 ERRFILE_chapERRFILE_chap ( ERRFILE_OTHER | 0x00010000 ) errfile.h 　
8645
 ERRFILE_aoebootERRFILE_aoeboot ( ERRFILE_OTHER | 0x00020000 ) errfile.h 　
8646
 ERRFILE_autobootERRFILE_autoboot ( ERRFILE_OTHER | 0x00030000 ) errfile.h 　
8647
 ERRFILE_dhcpmgmtERRFILE_dhcpmgmt ( ERRFILE_OTHER | 0x00040000 ) errfile.h 　
8648
 ERRFILE_imgmgmtERRFILE_imgmgmt ( ERRFILE_OTHER | 0x00050000 ) errfile.h 　
8649
 ERRFILE_pxe_tftpERRFILE_pxe_tftp ( ERRFILE_OTHER | 0x00060000 ) errfile.h 　
8650
 ERRFILE_pxe_udpERRFILE_pxe_udp ( ERRFILE_OTHER | 0x00070000 ) errfile.h 　
8651
 ERRFILE_axtls_aesERRFILE_axtls_aes ( ERRFILE_OTHER | 0x00080000 ) errfile.h 　
8652
 ERRFILE_cipherERRFILE_cipher ( ERRFILE_OTHER | 0x00090000 ) errfile.h 　
8653
 ERRFILE_image_cmdERRFILE_image_cmd ( ERRFILE_OTHER | 0x000a0000 ) errfile.h 　
8654
 ERRFILE_uri_testERRFILE_uri_test ( ERRFILE_OTHER | 0x000b0000 ) errfile.h 　
8655
 ERRFILE_ibftERRFILE_ibft ( ERRFILE_OTHER | 0x000c0000 ) errfile.h 　
8656
 ERRFILE_tlsERRFILE_tls ( ERRFILE_OTHER | 0x000d0000 ) errfile.h 　
8657
 ERRFILE_ifmgmtERRFILE_ifmgmt ( ERRFILE_OTHER | 0x000e0000 ) errfile.h 　
8658
 ERRFILE_iscsibootERRFILE_iscsiboot ( ERRFILE_OTHER | 0x000f0000 ) errfile.h 　
8659
 ERRFILE_efi_pciERRFILE_efi_pci ( ERRFILE_OTHER | 0x00100000 ) errfile.h 　
8660
 ERRFILE_efi_snpERRFILE_efi_snp ( ERRFILE_OTHER | 0x00110000 ) errfile.h 　
8661
 ERRFILE_smbiosERRFILE_smbios ( ERRFILE_OTHER | 0x00120000 ) errfile.h 　
8662
 ERRFILE_smbios_settingsERRFILE_smbios_settings ( ERRFILE_OTHER | 0x00130000 ) errfile.h 　
8663
 ERRFILE_efi_smbiosERRFILE_efi_smbios ( ERRFILE_OTHER | 0x00140000 ) errfile.h 　
8664
 ERRFILE_pxemenuERRFILE_pxemenu ( ERRFILE_OTHER | 0x00150000 ) errfile.h 　
8665
 ERRFILE_x509ERRFILE_x509 ( ERRFILE_OTHER | 0x00160000 ) errfile.h 　
8666
 ERRFILE_login_uiERRFILE_login_ui ( ERRFILE_OTHER | 0x00170000 ) errfile.h 　
8667
 ERRFILE_ib_srpbootERRFILE_ib_srpboot ( ERRFILE_OTHER | 0x00180000 ) errfile.h 　
8668
 ERRFILE_iwmgmtERRFILE_iwmgmt ( ERRFILE_OTHER | 0x00190000 ) errfile.h 　
8669
 ERRORTABERRORTAB __table ( struct errortab, "errortab" ) errortab.h 　
8670
 __errortab__errortab __table_entry ( ERRORTAB, 01 ) errortab.h 　
8671
 FEATURE_PROTOCOLFEATURE_PROTOCOL 01 features.h *< Network protocols
8672
 FEATURE_IMAGEFEATURE_IMAGE 02 features.h *< Image formats
8673
 FEATURE_MISCFEATURE_MISC 03 features.h *< Miscellaneous
8674
 DHCP_EB_FEATURE_PXE_EXTDHCP_EB_FEATURE_PXE_EXT 0x10 features.h *< PXE API extensions
8675
 DHCP_EB_FEATURE_ISCSIDHCP_EB_FEATURE_ISCSI 0x11 features.h *< iSCSI protocol
8676
 DHCP_EB_FEATURE_AOEDHCP_EB_FEATURE_AOE 0x12 features.h *< AoE protocol
8677
 DHCP_EB_FEATURE_HTTPDHCP_EB_FEATURE_HTTP 0x13 features.h *< HTTP protocol
8678
 DHCP_EB_FEATURE_HTTPSDHCP_EB_FEATURE_HTTPS 0x14 features.h *< HTTPS protocol
8679
 DHCP_EB_FEATURE_TFTPDHCP_EB_FEATURE_TFTP 0x15 features.h *< TFTP protocol
8680
 DHCP_EB_FEATURE_FTPDHCP_EB_FEATURE_FTP 0x16 features.h *< FTP protocol
8681
 DHCP_EB_FEATURE_DNSDHCP_EB_FEATURE_DNS 0x17 features.h *< DNS protocol
8682
 DHCP_EB_FEATURE_BZIMAGEDHCP_EB_FEATURE_BZIMAGE 0x18 features.h *< bzImage format
8683
 DHCP_EB_FEATURE_MULTIBOOTDHCP_EB_FEATURE_MULTIBOOT 0x19 features.h *< Multiboot format
8684
 DHCP_EB_FEATURE_SLAMDHCP_EB_FEATURE_SLAM 0x1a features.h *< SLAM protocol
8685
 DHCP_EB_FEATURE_SRPDHCP_EB_FEATURE_SRP 0x1b features.h *< SRP protocol
8686
 DHCP_EB_FEATURE_NBIDHCP_EB_FEATURE_NBI 0x20 features.h *< NBI format
8687
 DHCP_EB_FEATURE_PXEDHCP_EB_FEATURE_PXE 0x21 features.h *< PXE format
8688
 DHCP_EB_FEATURE_ELFDHCP_EB_FEATURE_ELF 0x22 features.h *< ELF format
8689
 DHCP_EB_FEATURE_COMBOOTDHCP_EB_FEATURE_COMBOOT 0x23 features.h *< COMBOOT format
8690
 DHCP_EB_FEATURE_EFIDHCP_EB_FEATURE_EFI 0x24 features.h *< EFI format
8691
 DHCP_FEATURESDHCP_FEATURES __table ( uint8_t, "dhcp_features" ) features.h 　
8692
 __dhcp_feature__dhcp_feature __table_entry ( DHCP_FEATURES, 01 ) features.h 　
8693
 FEATURESFEATURES __table ( struct feature, "features" ) features.h 　
8694
 FTP_PORTFTP_PORT 21 ftp.h 　
8695
 GDB_TRANSPORTSGDB_TRANSPORTS __table ( struct gdb_transport, "gdb_transports" ) gdbstub.h 　
8696
 __gdb_transport__gdb_transport __table_entry ( GDB_TRANSPORTS, 01 ) gdbstub.h 　
8697
 HTTP_PORTHTTP_PORT 80 http.h 　
8698
 HTTPS_PORTHTTPS_PORT 443 http.h 　
8699
 I2C_TENBIT_ADDRESSI2C_TENBIT_ADDRESS 0x7800 i2c.h 　
8700
 I2C_WRITEI2C_WRITE 0 i2c.h 　
8701
 I2C_READI2C_READ 1 i2c.h 　
8702
 I2C_UDELAYI2C_UDELAY 5 i2c.h 　
8703
 I2C_RESET_MAX_CYCLESI2C_RESET_MAX_CYCLES 32 i2c.h 　
8704
 IB_SMP_CLASS_VERSIONIB_SMP_CLASS_VERSION 1 ib_mad.h 　
8705
 IB_SMP_STATUS_D_INBOUNDIB_SMP_STATUS_D_INBOUND 0x8000 ib_mad.h 　
8706
 IB_SMP_ATTR_NOTICEIB_SMP_ATTR_NOTICE 0x0002 ib_mad.h 　
8707
 IB_SMP_ATTR_NODE_DESCIB_SMP_ATTR_NODE_DESC 0x0010 ib_mad.h 　
8708
 IB_SMP_ATTR_NODE_INFOIB_SMP_ATTR_NODE_INFO 0x0011 ib_mad.h 　
8709
 IB_SMP_ATTR_SWITCH_INFOIB_SMP_ATTR_SWITCH_INFO 0x0012 ib_mad.h 　
8710
 IB_SMP_ATTR_GUID_INFOIB_SMP_ATTR_GUID_INFO 0x0014 ib_mad.h 　
8711
 IB_SMP_ATTR_PORT_INFOIB_SMP_ATTR_PORT_INFO 0x0015 ib_mad.h 　
8712
 IB_SMP_ATTR_PKEY_TABLEIB_SMP_ATTR_PKEY_TABLE 0x0016 ib_mad.h 　
8713
 IB_SMP_ATTR_SL_TO_VL_TABLEIB_SMP_ATTR_SL_TO_VL_TABLE 0x0017 ib_mad.h 　
8714
 IB_SMP_ATTR_VL_ARB_TABLEIB_SMP_ATTR_VL_ARB_TABLE 0x0018 ib_mad.h 　
8715
 IB_SMP_ATTR_LINEAR_FORWARD_TABLIB_SMP_ATTR_LINEAR_FORWARD_TABL 0x0019 ib_mad.h 　
8716
 IB_SMP_ATTR_RANDOM_FORWARD_TABLIB_SMP_ATTR_RANDOM_FORWARD_TABL 0x001A ib_mad.h 　
8717
 IB_SMP_ATTR_MCAST_FORWARD_TABLEIB_SMP_ATTR_MCAST_FORWARD_TABLE 0x001B ib_mad.h 　
8718
 IB_SMP_ATTR_SM_INFOIB_SMP_ATTR_SM_INFO 0x0020 ib_mad.h 　
8719
 IB_SMP_ATTR_VENDOR_DIAGIB_SMP_ATTR_VENDOR_DIAG 0x0030 ib_mad.h 　
8720
 IB_SMP_ATTR_LED_INFOIB_SMP_ATTR_LED_INFO 0x0031 ib_mad.h 　
8721
 IB_SMP_ATTR_VENDOR_MASKIB_SMP_ATTR_VENDOR_MASK 0xFF00 ib_mad.h 　
8722
 IB_NODE_TYPE_HCAIB_NODE_TYPE_HCA 0x01 ib_mad.h 　
8723
 IB_NODE_TYPE_SWITCHIB_NODE_TYPE_SWITCH 0x02 ib_mad.h 　
8724
 IB_NODE_TYPE_ROUTERIB_NODE_TYPE_ROUTER 0x03 ib_mad.h 　
8725
 IB_LINK_WIDTH_1XIB_LINK_WIDTH_1X 0x01 ib_mad.h 　
8726
 IB_LINK_WIDTH_4XIB_LINK_WIDTH_4X 0x02 ib_mad.h 　
8727
 IB_LINK_WIDTH_8XIB_LINK_WIDTH_8X 0x04 ib_mad.h 　
8728
 IB_LINK_WIDTH_12XIB_LINK_WIDTH_12X 0x08 ib_mad.h 　
8729
 IB_LINK_SPEED_SDRIB_LINK_SPEED_SDR 0x01 ib_mad.h 　
8730
 IB_LINK_SPEED_DDRIB_LINK_SPEED_DDR 0x02 ib_mad.h 　
8731
 IB_LINK_SPEED_QDRIB_LINK_SPEED_QDR 0x04 ib_mad.h 　
8732
 IB_PORT_STATE_DOWNIB_PORT_STATE_DOWN 0x01 ib_mad.h 　
8733
 IB_PORT_STATE_INITIB_PORT_STATE_INIT 0x02 ib_mad.h 　
8734
 IB_PORT_STATE_ARMEDIB_PORT_STATE_ARMED 0x03 ib_mad.h 　
8735
 IB_PORT_STATE_ACTIVEIB_PORT_STATE_ACTIVE 0x04 ib_mad.h 　
8736
 IB_PORT_PHYS_STATE_SLEEPIB_PORT_PHYS_STATE_SLEEP 0x01 ib_mad.h 　
8737
 IB_PORT_PHYS_STATE_POLLINGIB_PORT_PHYS_STATE_POLLING 0x02 ib_mad.h 　
8738
 IB_MTU_256IB_MTU_256 0x01 ib_mad.h 　
8739
 IB_MTU_512IB_MTU_512 0x02 ib_mad.h 　
8740
 IB_MTU_1024IB_MTU_1024 0x03 ib_mad.h 　
8741
 IB_MTU_2048IB_MTU_2048 0x04 ib_mad.h 　
8742
 IB_MTU_4096IB_MTU_4096 0x05 ib_mad.h 　
8743
 IB_VL_0IB_VL_0 0x01 ib_mad.h 　
8744
 IB_VL_0_1IB_VL_0_1 0x02 ib_mad.h 　
8745
 IB_VL_0_3IB_VL_0_3 0x03 ib_mad.h 　
8746
 IB_VL_0_7IB_VL_0_7 0x04 ib_mad.h 　
8747
 IB_VL_0_14IB_VL_0_14 0x05 ib_mad.h 　
8748
 IB_SA_CLASS_VERSIONIB_SA_CLASS_VERSION 2 ib_mad.h 　
8749
 IB_SA_METHOD_DELETE_RESPIB_SA_METHOD_DELETE_RESP 0x95 ib_mad.h 　
8750
 IB_SA_ATTR_MC_MEMBER_RECIB_SA_ATTR_MC_MEMBER_REC 0x38 ib_mad.h 　
8751
 IB_SA_ATTR_PATH_RECIB_SA_ATTR_PATH_REC 0x35 ib_mad.h 　
8752
 IB_SA_PATH_REC_DGIDIB_SA_PATH_REC_DGID (1<<2) ib_mad.h 　
8753
 IB_SA_PATH_REC_SGIDIB_SA_PATH_REC_SGID (1<<3) ib_mad.h 　
8754
 IB_SA_MCMEMBER_REC_MGIDIB_SA_MCMEMBER_REC_MGID (1<<0) ib_mad.h 　
8755
 IB_SA_MCMEMBER_REC_PORT_GIDIB_SA_MCMEMBER_REC_PORT_GID (1<<1) ib_mad.h 　
8756
 IB_SA_MCMEMBER_REC_QKEYIB_SA_MCMEMBER_REC_QKEY (1<<2) ib_mad.h 　
8757
 IB_SA_MCMEMBER_REC_MLIDIB_SA_MCMEMBER_REC_MLID (1<<3) ib_mad.h 　
8758
 IB_SA_MCMEMBER_REC_MTU_SELECTORIB_SA_MCMEMBER_REC_MTU_SELECTOR (1<<4) ib_mad.h 　
8759
 IB_SA_MCMEMBER_REC_MTUIB_SA_MCMEMBER_REC_MTU (1<<5) ib_mad.h 　
8760
 IB_SA_MCMEMBER_REC_TRAFFIC_CLASIB_SA_MCMEMBER_REC_TRAFFIC_CLAS (1<<6) ib_mad.h 　
8761
 IB_SA_MCMEMBER_REC_PKEYIB_SA_MCMEMBER_REC_PKEY (1<<7) ib_mad.h 　
8762
 IB_SA_MCMEMBER_REC_RATE_SELECTOIB_SA_MCMEMBER_REC_RATE_SELECTO (1<<8) ib_mad.h 　
8763
 IB_SA_MCMEMBER_REC_RATEIB_SA_MCMEMBER_REC_RATE (1<<9) ib_mad.h 　
8764
 IB_SA_MCMEMBER_REC_PACKET_LIFE_IB_SA_MCMEMBER_REC_PACKET_LIFE_ (1<<10) ib_mad.h 　
8765
 IB_SA_MCMEMBER_REC_PACKET_LIFE_IB_SA_MCMEMBER_REC_PACKET_LIFE_ (1<<11) ib_mad.h 　
8766
 IB_SA_MCMEMBER_REC_SLIB_SA_MCMEMBER_REC_SL (1<<12) ib_mad.h 　
8767
 IB_SA_MCMEMBER_REC_FLOW_LABELIB_SA_MCMEMBER_REC_FLOW_LABEL (1<<13) ib_mad.h 　
8768
 IB_SA_MCMEMBER_REC_HOP_LIMITIB_SA_MCMEMBER_REC_HOP_LIMIT (1<<14) ib_mad.h 　
8769
 IB_SA_MCMEMBER_REC_SCOPEIB_SA_MCMEMBER_REC_SCOPE (1<<15) ib_mad.h 　
8770
 IB_SA_MCMEMBER_REC_JOIN_STATEIB_SA_MCMEMBER_REC_JOIN_STATE (1<<16) ib_mad.h 　
8771
 IB_SA_MCMEMBER_REC_PROXY_JOINIB_SA_MCMEMBER_REC_PROXY_JOIN (1<<17) ib_mad.h 　
8772
 IB_CM_CLASS_VERSIONIB_CM_CLASS_VERSION 2 ib_mad.h 　
8773
 IB_CM_ATTR_CLASS_PORT_INFOIB_CM_ATTR_CLASS_PORT_INFO 0x0001 ib_mad.h 　
8774
 IB_CM_ATTR_CONNECT_REQUESTIB_CM_ATTR_CONNECT_REQUEST 0x0010 ib_mad.h 　
8775
 IB_CM_ATTR_MSG_RCPT_ACKIB_CM_ATTR_MSG_RCPT_ACK 0x0011 ib_mad.h 　
8776
 IB_CM_ATTR_CONNECT_REJECTIB_CM_ATTR_CONNECT_REJECT 0x0012 ib_mad.h 　
8777
 IB_CM_ATTR_CONNECT_REPLYIB_CM_ATTR_CONNECT_REPLY 0x0013 ib_mad.h 　
8778
 IB_CM_ATTR_READY_TO_USEIB_CM_ATTR_READY_TO_USE 0x0014 ib_mad.h 　
8779
 IB_CM_ATTR_DISCONNECT_REQUESTIB_CM_ATTR_DISCONNECT_REQUEST 0x0015 ib_mad.h 　
8780
 IB_CM_ATTR_DISCONNECT_REPLYIB_CM_ATTR_DISCONNECT_REPLY 0x0016 ib_mad.h 　
8781
 IB_CM_ATTR_SERVICE_ID_RES_REQIB_CM_ATTR_SERVICE_ID_RES_REQ 0x0016 ib_mad.h 　
8782
 IB_CM_ATTR_SERVICE_ID_RES_REQ_RIB_CM_ATTR_SERVICE_ID_RES_REQ_R 0x0018 ib_mad.h 　
8783
 IB_CM_ATTR_LOAD_ALTERNATE_PATHIB_CM_ATTR_LOAD_ALTERNATE_PATH 0x0019 ib_mad.h 　
8784
 IB_CM_ATTR_ALTERNATE_PATH_RESPOIB_CM_ATTR_ALTERNATE_PATH_RESPO 0x001a ib_mad.h 　
8785
 IB_CM_TRANSPORT_RCIB_CM_TRANSPORT_RC 0 ib_mad.h 　
8786
 IB_CM_TRANSPORT_UCIB_CM_TRANSPORT_UC 1 ib_mad.h 　
8787
 IB_CM_TRANSPORT_RDIB_CM_TRANSPORT_RD 2 ib_mad.h 　
8788
 IB_CM_REJECT_BAD_SERVICE_IDIB_CM_REJECT_BAD_SERVICE_ID 8 ib_mad.h 　
8789
 IB_CM_REJECT_STALE_CONNIB_CM_REJECT_STALE_CONN 10 ib_mad.h 　
8790
 IB_CM_REJECT_CONSUMERIB_CM_REJECT_CONSUMER 28 ib_mad.h 　
8791
 IB_MGMT_BASE_VERSIONIB_MGMT_BASE_VERSION 1 ib_mad.h 　
8792
 IB_MGMT_CLASS_SUBN_LID_ROUTEDIB_MGMT_CLASS_SUBN_LID_ROUTED 0x01 ib_mad.h 　
8793
 IB_MGMT_CLASS_SUBN_DIRECTED_ROUIB_MGMT_CLASS_SUBN_DIRECTED_ROU 0x81 ib_mad.h 　
8794
 IB_MGMT_CLASS_SUBN_ADMIB_MGMT_CLASS_SUBN_ADM 0x03 ib_mad.h 　
8795
 IB_MGMT_CLASS_PERF_MGMTIB_MGMT_CLASS_PERF_MGMT 0x04 ib_mad.h 　
8796
 IB_MGMT_CLASS_BMIB_MGMT_CLASS_BM 0x05 ib_mad.h 　
8797
 IB_MGMT_CLASS_DEVICE_MGMTIB_MGMT_CLASS_DEVICE_MGMT 0x06 ib_mad.h 　
8798
 IB_MGMT_CLASS_CMIB_MGMT_CLASS_CM 0x07 ib_mad.h 　
8799
 IB_MGMT_CLASS_SNMPIB_MGMT_CLASS_SNMP 0x08 ib_mad.h 　
8800
 IB_MGMT_CLASS_VENDOR_RANGE2_STAIB_MGMT_CLASS_VENDOR_RANGE2_STA 0x30 ib_mad.h 　
8801
 IB_MGMT_CLASS_VENDOR_RANGE2_ENDIB_MGMT_CLASS_VENDOR_RANGE2_END 0x4f ib_mad.h 　
8802
 IB_MGMT_CLASS_MASKIB_MGMT_CLASS_MASK 0x7f ib_mad.h 　
8803
 IB_MGMT_METHOD_GETIB_MGMT_METHOD_GET 0x01 ib_mad.h 　
8804
 IB_MGMT_METHOD_SETIB_MGMT_METHOD_SET 0x02 ib_mad.h 　
8805
 IB_MGMT_METHOD_GET_RESPIB_MGMT_METHOD_GET_RESP 0x81 ib_mad.h 　
8806
 IB_MGMT_METHOD_SENDIB_MGMT_METHOD_SEND 0x03 ib_mad.h 　
8807
 IB_MGMT_METHOD_TRAPIB_MGMT_METHOD_TRAP 0x05 ib_mad.h 　
8808
 IB_MGMT_METHOD_REPORTIB_MGMT_METHOD_REPORT 0x06 ib_mad.h 　
8809
 IB_MGMT_METHOD_REPORT_RESPIB_MGMT_METHOD_REPORT_RESP 0x86 ib_mad.h 　
8810
 IB_MGMT_METHOD_TRAP_REPRESSIB_MGMT_METHOD_TRAP_REPRESS 0x07 ib_mad.h 　
8811
 IB_MGMT_METHOD_DELETEIB_MGMT_METHOD_DELETE 0x15 ib_mad.h 　
8812
 IB_MGMT_STATUS_OKIB_MGMT_STATUS_OK 0x0000 ib_mad.h 　
8813
 IB_MGMT_STATUS_BAD_VERSIONIB_MGMT_STATUS_BAD_VERSION 0x0001 ib_mad.h 　
8814
 IB_MGMT_STATUS_UNSUPPORTED_METHIB_MGMT_STATUS_UNSUPPORTED_METH 0x0002 ib_mad.h 　
8815
 IB_MGMT_STATUS_UNSUPPORTED_METHIB_MGMT_STATUS_UNSUPPORTED_METH 0x0003 ib_mad.h 　
8816
 IB_MGMT_STATUS_INVALID_VALUEIB_MGMT_STATUS_INVALID_VALUE 0x0004 ib_mad.h 　
8817
 IB_MAD_AGENTSIB_MAD_AGENTS __table ( struct ib_mad_agent, "ib_mad_agents" ) ib_mi.h 　
8818
 __ib_mad_agent__ib_mad_agent __table_entry ( IB_MAD_AGENTS, 01 ) ib_mi.h 　
8819
 IB_LID_NONEIB_LID_NONE 0xffff ib_packet.h 　
8820
 IB_GRH_IPVER_IPv6IB_GRH_IPVER_IPv6 0x06 ib_packet.h 　
8821
 IB_GRH_NXTHDR_IBAIB_GRH_NXTHDR_IBA 0x1b ib_packet.h 　
8822
 IB_MAX_HEADER_SIZEIB_MAX_HEADER_SIZE sizeof ( union ib_headers ) ib_packet.h 　
8823
 ICMP_ECHO_RESPONSEICMP_ECHO_RESPONSE 0 icmp.h 　
8824
 ICMP_ECHO_REQUESTICMP_ECHO_REQUEST 8 icmp.h 　
8825
 ICMP6_NSOLICITICMP6_NSOLICIT 135 icmp6.h 　
8826
 ICMP6_NADVERTICMP6_NADVERT 136 icmp6.h 　
8827
 ICMP6_FLAGS_ROUTERICMP6_FLAGS_ROUTER 0x80 icmp6.h 　
8828
 ICMP6_FLAGS_SOLICITEDICMP6_FLAGS_SOLICITED 0x40 icmp6.h 　
8829
 ICMP6_FLAGS_OVERRIDEICMP6_FLAGS_OVERRIDE 0x20 icmp6.h 　
8830
 IEEE80211_MAX_DATA_LENIEEE80211_MAX_DATA_LEN 2304 ieee80211.h 　
8831
 IEEE80211_LLC_HEADER_LENIEEE80211_LLC_HEADER_LEN 8 ieee80211.h 　
8832
 IEEE80211_MAX_CRYPTO_HEADERIEEE80211_MAX_CRYPTO_HEADER 8 ieee80211.h 　
8833
 IEEE80211_MAX_CRYPTO_TRAILERIEEE80211_MAX_CRYPTO_TRAILER 8 ieee80211.h 　
8834
 IEEE80211_MAX_CRYPTO_OVERHEADIEEE80211_MAX_CRYPTO_OVERHEAD 16 ieee80211.h 　
8835
 IEEE80211_MAX_FRAME_DATAIEEE80211_MAX_FRAME_DATA 2296 ieee80211.h 　
8836
 IEEE80211_TYP_FRAME_HEADER_LENIEEE80211_TYP_FRAME_HEADER_LEN 24 ieee80211.h 　
8837
 IEEE80211_MAX_FRAME_HEADER_LENIEEE80211_MAX_FRAME_HEADER_LEN 32 ieee80211.h 　
8838
 IEEE80211_MAX_FRAME_LENIEEE80211_MAX_FRAME_LEN 2352 ieee80211.h 　
8839
 IEEE80211_MAX_SSID_LENIEEE80211_MAX_SSID_LEN 32 ieee80211.h 　
8840
 IEEE80211_FC_VERSIONIEEE80211_FC_VERSION 0x0003 ieee80211.h 　
8841
 IEEE80211_THIS_VERSIONIEEE80211_THIS_VERSION 0x0000 ieee80211.h 　
8842
 IEEE80211_FC_TYPEIEEE80211_FC_TYPE 0x000C ieee80211.h 　
8843
 IEEE80211_TYPE_MGMTIEEE80211_TYPE_MGMT 0x0000 ieee80211.h 　
8844
 IEEE80211_TYPE_CTRLIEEE80211_TYPE_CTRL 0x0004 ieee80211.h 　
8845
 IEEE80211_TYPE_DATAIEEE80211_TYPE_DATA 0x0008 ieee80211.h 　
8846
 IEEE80211_FC_SUBTYPEIEEE80211_FC_SUBTYPE 0x00F0 ieee80211.h 　
8847
 IEEE80211_STYPE_ASSOC_REQIEEE80211_STYPE_ASSOC_REQ 0x0000 ieee80211.h 　
8848
 IEEE80211_STYPE_ASSOC_RESPIEEE80211_STYPE_ASSOC_RESP 0x0010 ieee80211.h 　
8849
 IEEE80211_STYPE_REASSOC_REQIEEE80211_STYPE_REASSOC_REQ 0x0020 ieee80211.h 　
8850
 IEEE80211_STYPE_REASSOC_RESPIEEE80211_STYPE_REASSOC_RESP 0x0030 ieee80211.h 　
8851
 IEEE80211_STYPE_PROBE_REQIEEE80211_STYPE_PROBE_REQ 0x0040 ieee80211.h 　
8852
 IEEE80211_STYPE_PROBE_RESPIEEE80211_STYPE_PROBE_RESP 0x0050 ieee80211.h 　
8853
 IEEE80211_STYPE_BEACONIEEE80211_STYPE_BEACON 0x0080 ieee80211.h 　
8854
 IEEE80211_STYPE_DISASSOCIEEE80211_STYPE_DISASSOC 0x00A0 ieee80211.h 　
8855
 IEEE80211_STYPE_AUTHIEEE80211_STYPE_AUTH 0x00B0 ieee80211.h 　
8856
 IEEE80211_STYPE_DEAUTHIEEE80211_STYPE_DEAUTH 0x00C0 ieee80211.h 　
8857
 IEEE80211_STYPE_ACTIONIEEE80211_STYPE_ACTION 0x00D0 ieee80211.h 　
8858
 IEEE80211_STYPE_RTSIEEE80211_STYPE_RTS 0x00B0 ieee80211.h 　
8859
 IEEE80211_STYPE_CTSIEEE80211_STYPE_CTS 0x00C0 ieee80211.h 　
8860
 IEEE80211_STYPE_ACKIEEE80211_STYPE_ACK 0x00D0 ieee80211.h 　
8861
 IEEE80211_STYPE_DATAIEEE80211_STYPE_DATA 0x0000 ieee80211.h 　
8862
 IEEE80211_STYPE_NODATAIEEE80211_STYPE_NODATA 0x0040 ieee80211.h 　
8863
 IEEE80211_FC_TODSIEEE80211_FC_TODS 0x0100 ieee80211.h 　
8864
 IEEE80211_FC_FROMDSIEEE80211_FC_FROMDS 0x0200 ieee80211.h 　
8865
 IEEE80211_FC_MORE_FRAGIEEE80211_FC_MORE_FRAG 0x0400 ieee80211.h 　
8866
 IEEE80211_FC_RETRYIEEE80211_FC_RETRY 0x0800 ieee80211.h 　
8867
 IEEE80211_FC_PWR_MGMTIEEE80211_FC_PWR_MGMT 0x1000 ieee80211.h 　
8868
 IEEE80211_FC_MORE_DATAIEEE80211_FC_MORE_DATA 0x2000 ieee80211.h 　
8869
 IEEE80211_FC_PROTECTEDIEEE80211_FC_PROTECTED 0x4000 ieee80211.h 　
8870
 IEEE80211_FC_ORDERIEEE80211_FC_ORDER 0x8000 ieee80211.h 　
8871
 IEEE80211_LLC_DSAPIEEE80211_LLC_DSAP 0xAA ieee80211.h 　
8872
 IEEE80211_LLC_SSAPIEEE80211_LLC_SSAP 0xAA ieee80211.h 　
8873
 IEEE80211_LLC_CTRLIEEE80211_LLC_CTRL 0x03 ieee80211.h 　
8874
 IEEE80211_RTS_LENIEEE80211_RTS_LEN 16 ieee80211.h 　
8875
 ieee80211_ctsieee80211_cts ieee80211_cts_or_ack ieee80211.h 　
8876
 ieee80211_ackieee80211_ack ieee80211_cts_or_ack ieee80211.h 　
8877
 IEEE80211_CTS_LENIEEE80211_CTS_LEN 10 ieee80211.h 　
8878
 IEEE80211_ACK_LENIEEE80211_ACK_LEN 10 ieee80211.h 　
8879
 IEEE80211_CAPAB_MANAGEDIEEE80211_CAPAB_MANAGED 0x0001 ieee80211.h 　
8880
 IEEE80211_CAPAB_ADHOCIEEE80211_CAPAB_ADHOC 0x0002 ieee80211.h 　
8881
 IEEE80211_CAPAB_CFPOLLIEEE80211_CAPAB_CFPOLL 0x0004 ieee80211.h 　
8882
 IEEE80211_CAPAB_CFPRIEEE80211_CAPAB_CFPR 0x0008 ieee80211.h 　
8883
 IEEE80211_CAPAB_PRIVACYIEEE80211_CAPAB_PRIVACY 0x0010 ieee80211.h 　
8884
 IEEE80211_CAPAB_SHORT_PMBLIEEE80211_CAPAB_SHORT_PMBL 0x0020 ieee80211.h 　
8885
 IEEE80211_CAPAB_PBCCIEEE80211_CAPAB_PBCC 0x0040 ieee80211.h 　
8886
 IEEE80211_CAPAB_CHAN_AGILITYIEEE80211_CAPAB_CHAN_AGILITY 0x0080 ieee80211.h 　
8887
 IEEE80211_CAPAB_SPECTRUM_MGMTIEEE80211_CAPAB_SPECTRUM_MGMT 0x0100 ieee80211.h 　
8888
 IEEE80211_CAPAB_QOSIEEE80211_CAPAB_QOS 0x0200 ieee80211.h 　
8889
 IEEE80211_CAPAB_SHORT_SLOTIEEE80211_CAPAB_SHORT_SLOT 0x0400 ieee80211.h 　
8890
 IEEE80211_CAPAB_APSDIEEE80211_CAPAB_APSD 0x0800 ieee80211.h 　
8891
 IEEE80211_CAPAB_DSSS_OFDMIEEE80211_CAPAB_DSSS_OFDM 0x2000 ieee80211.h 　
8892
 IEEE80211_CAPAB_DELAYED_BACKIEEE80211_CAPAB_DELAYED_BACK 0x4000 ieee80211.h 　
8893
 IEEE80211_CAPAB_IMMED_BACKIEEE80211_CAPAB_IMMED_BACK 0x8000 ieee80211.h 　
8894
 IEEE80211_STATUS_SUCCESSIEEE80211_STATUS_SUCCESS 0 ieee80211.h 　
8895
 IEEE80211_STATUS_FAILUREIEEE80211_STATUS_FAILURE 1 ieee80211.h 　
8896
 IEEE80211_STATUS_CAPAB_UNSUPPIEEE80211_STATUS_CAPAB_UNSUPP 10 ieee80211.h 　
8897
 IEEE80211_STATUS_REASSOC_INVALIIEEE80211_STATUS_REASSOC_INVALI 11 ieee80211.h 　
8898
 IEEE80211_STATUS_ASSOC_DENIEDIEEE80211_STATUS_ASSOC_DENIED 12 ieee80211.h 　
8899
 IEEE80211_STATUS_AUTH_ALGO_UNSUIEEE80211_STATUS_AUTH_ALGO_UNSU 13 ieee80211.h 　
8900
 IEEE80211_STATUS_AUTH_SEQ_INVALIEEE80211_STATUS_AUTH_SEQ_INVAL 14 ieee80211.h 　
8901
 IEEE80211_STATUS_AUTH_CHALL_INVIEEE80211_STATUS_AUTH_CHALL_INV 15 ieee80211.h 　
8902
 IEEE80211_STATUS_AUTH_TIMEOUTIEEE80211_STATUS_AUTH_TIMEOUT 16 ieee80211.h 　
8903
 IEEE80211_STATUS_ASSOC_NO_ROOMIEEE80211_STATUS_ASSOC_NO_ROOM 17 ieee80211.h 　
8904
 IEEE80211_STATUS_ASSOC_NEED_RATIEEE80211_STATUS_ASSOC_NEED_RAT 18 ieee80211.h 　
8905
 IEEE80211_STATUS_ASSOC_NEED_SHOIEEE80211_STATUS_ASSOC_NEED_SHO 19 ieee80211.h 　
8906
 IEEE80211_STATUS_ASSOC_NEED_PBCIEEE80211_STATUS_ASSOC_NEED_PBC 20 ieee80211.h 　
8907
 IEEE80211_STATUS_ASSOC_NEED_CHAIEEE80211_STATUS_ASSOC_NEED_CHA 21 ieee80211.h 　
8908
 IEEE80211_STATUS_ASSOC_NEED_SPEIEEE80211_STATUS_ASSOC_NEED_SPE 22 ieee80211.h 　
8909
 IEEE80211_STATUS_ASSOC_BAD_POWEIEEE80211_STATUS_ASSOC_BAD_POWE 23 ieee80211.h 　
8910
 IEEE80211_STATUS_ASSOC_BAD_CHANIEEE80211_STATUS_ASSOC_BAD_CHAN 24 ieee80211.h 　
8911
 IEEE80211_STATUS_ASSOC_NEED_SHOIEEE80211_STATUS_ASSOC_NEED_SHO 25 ieee80211.h 　
8912
 IEEE80211_STATUS_ASSOC_NEED_DSSIEEE80211_STATUS_ASSOC_NEED_DSS 26 ieee80211.h 　
8913
 IEEE80211_STATUS_QOS_FAILUREIEEE80211_STATUS_QOS_FAILURE 32 ieee80211.h 　
8914
 IEEE80211_STATUS_QOS_NO_ROOMIEEE80211_STATUS_QOS_NO_ROOM 33 ieee80211.h 　
8915
 IEEE80211_STATUS_LINK_IS_HORRIBIEEE80211_STATUS_LINK_IS_HORRIB 34 ieee80211.h 　
8916
 IEEE80211_STATUS_ASSOC_NEED_QOSIEEE80211_STATUS_ASSOC_NEED_QOS 35 ieee80211.h 　
8917
 IEEE80211_STATUS_REQUEST_DECLINIEEE80211_STATUS_REQUEST_DECLIN 37 ieee80211.h 　
8918
 IEEE80211_STATUS_REQUEST_INVALIIEEE80211_STATUS_REQUEST_INVALI 38 ieee80211.h 　
8919
 IEEE80211_STATUS_TS_NOT_CREATEDIEEE80211_STATUS_TS_NOT_CREATED 39 ieee80211.h 　
8920
 IEEE80211_STATUS_INVALID_IEIEEE80211_STATUS_INVALID_IE 40 ieee80211.h 　
8921
 IEEE80211_STATUS_GROUP_CIPHER_IIEEE80211_STATUS_GROUP_CIPHER_I 41 ieee80211.h 　
8922
 IEEE80211_STATUS_PAIR_CIPHER_INIEEE80211_STATUS_PAIR_CIPHER_IN 42 ieee80211.h 　
8923
 IEEE80211_STATUS_AKMP_INVALIDIEEE80211_STATUS_AKMP_INVALID 43 ieee80211.h 　
8924
 IEEE80211_STATUS_RSN_VERSION_UNIEEE80211_STATUS_RSN_VERSION_UN 44 ieee80211.h 　
8925
 IEEE80211_STATUS_RSN_CAPAB_INVAIEEE80211_STATUS_RSN_CAPAB_INVA 45 ieee80211.h 　
8926
 IEEE80211_STATUS_CIPHER_REJECTEIEEE80211_STATUS_CIPHER_REJECTE 46 ieee80211.h 　
8927
 IEEE80211_STATUS_TS_NOT_CREATEDIEEE80211_STATUS_TS_NOT_CREATED 47 ieee80211.h 　
8928
 IEEE80211_STATUS_DIRECT_LINK_FOIEEE80211_STATUS_DIRECT_LINK_FO 48 ieee80211.h 　
8929
 IEEE80211_STATUS_DEST_NOT_PRESEIEEE80211_STATUS_DEST_NOT_PRESE 49 ieee80211.h 　
8930
 IEEE80211_STATUS_DEST_NOT_QOSIEEE80211_STATUS_DEST_NOT_QOS 50 ieee80211.h 　
8931
 IEEE80211_STATUS_ASSOC_LISTEN_TIEEE80211_STATUS_ASSOC_LISTEN_T 51 ieee80211.h 　
8932
 IEEE80211_REASON_NONEIEEE80211_REASON_NONE 0 ieee80211.h 　
8933
 IEEE80211_REASON_UNSPECIFIEDIEEE80211_REASON_UNSPECIFIED 1 ieee80211.h 　
8934
 IEEE80211_REASON_AUTH_NO_LONGERIEEE80211_REASON_AUTH_NO_LONGER 2 ieee80211.h 　
8935
 IEEE80211_REASON_LEAVINGIEEE80211_REASON_LEAVING 3 ieee80211.h 　
8936
 IEEE80211_REASON_INACTIVITYIEEE80211_REASON_INACTIVITY 4 ieee80211.h 　
8937
 IEEE80211_REASON_OUT_OF_RESOURCIEEE80211_REASON_OUT_OF_RESOURC 5 ieee80211.h 　
8938
 IEEE80211_REASON_NEED_AUTHIEEE80211_REASON_NEED_AUTH 6 ieee80211.h 　
8939
 IEEE80211_REASON_NEED_ASSOCIEEE80211_REASON_NEED_ASSOC 7 ieee80211.h 　
8940
 IEEE80211_REASON_LEAVING_TO_ROAIEEE80211_REASON_LEAVING_TO_ROA 8 ieee80211.h 　
8941
 IEEE80211_REASON_REASSOC_INVALIIEEE80211_REASON_REASSOC_INVALI 9 ieee80211.h 　
8942
 IEEE80211_REASON_BAD_POWERIEEE80211_REASON_BAD_POWER 10 ieee80211.h 　
8943
 IEEE80211_REASON_BAD_CHANNELSIEEE80211_REASON_BAD_CHANNELS 11 ieee80211.h 　
8944
 IEEE80211_REASON_INVALID_IEIEEE80211_REASON_INVALID_IE 13 ieee80211.h 　
8945
 IEEE80211_REASON_MIC_FAILUREIEEE80211_REASON_MIC_FAILURE 14 ieee80211.h 　
8946
 IEEE80211_REASON_4WAY_TIMEOUTIEEE80211_REASON_4WAY_TIMEOUT 15 ieee80211.h 　
8947
 IEEE80211_REASON_GROUPKEY_TIMEOIEEE80211_REASON_GROUPKEY_TIMEO 16 ieee80211.h 　
8948
 IEEE80211_REASON_4WAY_INVALIDIEEE80211_REASON_4WAY_INVALID 17 ieee80211.h 　
8949
 IEEE80211_REASON_GROUP_CIPHER_IIEEE80211_REASON_GROUP_CIPHER_I 18 ieee80211.h 　
8950
 IEEE80211_REASON_PAIR_CIPHER_INIEEE80211_REASON_PAIR_CIPHER_IN 19 ieee80211.h 　
8951
 IEEE80211_REASON_AKMP_INVALIDIEEE80211_REASON_AKMP_INVALID 20 ieee80211.h 　
8952
 IEEE80211_REASON_RSN_VERSION_INIEEE80211_REASON_RSN_VERSION_IN 21 ieee80211.h 　
8953
 IEEE80211_REASON_RSN_CAPAB_INVAIEEE80211_REASON_RSN_CAPAB_INVA 22 ieee80211.h 　
8954
 IEEE80211_REASON_8021X_FAILUREIEEE80211_REASON_8021X_FAILURE 23 ieee80211.h 　
8955
 IEEE80211_REASON_CIPHER_REJECTEIEEE80211_REASON_CIPHER_REJECTE 24 ieee80211.h 　
8956
 IEEE80211_REASON_QOS_UNSPECIFIEIEEE80211_REASON_QOS_UNSPECIFIE 32 ieee80211.h 　
8957
 IEEE80211_REASON_QOS_OUT_OF_RESIEEE80211_REASON_QOS_OUT_OF_RES 33 ieee80211.h 　
8958
 IEEE80211_REASON_LINK_IS_HORRIBIEEE80211_REASON_LINK_IS_HORRIB 34 ieee80211.h 　
8959
 IEEE80211_REASON_INVALID_TXOPIEEE80211_REASON_INVALID_TXOP 35 ieee80211.h 　
8960
 IEEE80211_REASON_REQUESTED_LEAVIEEE80211_REASON_REQUESTED_LEAV 36 ieee80211.h 　
8961
 IEEE80211_REASON_REQUESTED_NO_UIEEE80211_REASON_REQUESTED_NO_U 37 ieee80211.h 　
8962
 IEEE80211_REASON_REQUESTED_NEEDIEEE80211_REASON_REQUESTED_NEED 38 ieee80211.h 　
8963
 IEEE80211_REASON_REQUESTED_TIMEIEEE80211_REASON_REQUESTED_TIME 39 ieee80211.h 　
8964
 IEEE80211_REASON_CIPHER_UNSUPPOIEEE80211_REASON_CIPHER_UNSUPPO 45 ieee80211.h 　
8965
 IEEE80211_IE_SSIDIEEE80211_IE_SSID 0 ieee80211.h 　
8966
 IEEE80211_IE_RATESIEEE80211_IE_RATES 1 ieee80211.h 　
8967
 IEEE80211_IE_EXT_RATESIEEE80211_IE_EXT_RATES 50 ieee80211.h 　
8968
 IEEE80211_IE_DS_PARAMIEEE80211_IE_DS_PARAM 3 ieee80211.h 　
8969
 IEEE80211_IE_COUNTRYIEEE80211_IE_COUNTRY 7 ieee80211.h 　
8970
 IEEE80211_IE_REQUESTIEEE80211_IE_REQUEST 10 ieee80211.h 　
8971
 IEEE80211_IE_CHALLENGE_TEXTIEEE80211_IE_CHALLENGE_TEXT 16 ieee80211.h 　
8972
 IEEE80211_IE_POWER_CONSTRAINTIEEE80211_IE_POWER_CONSTRAINT 52 ieee80211.h 　
8973
 IEEE80211_IE_POWER_CAPABIEEE80211_IE_POWER_CAPAB 33 ieee80211.h 　
8974
 IEEE80211_IE_CHANNELSIEEE80211_IE_CHANNELS 36 ieee80211.h 　
8975
 IEEE80211_IE_ERP_INFOIEEE80211_IE_ERP_INFO 42 ieee80211.h 　
8976
 IEEE80211_ERP_NONERP_PRESENTIEEE80211_ERP_NONERP_PRESENT 0x01 ieee80211.h 　
8977
 IEEE80211_ERP_USE_PROTECTIONIEEE80211_ERP_USE_PROTECTION 0x02 ieee80211.h 　
8978
 IEEE80211_ERP_BARKER_LONGIEEE80211_ERP_BARKER_LONG 0x04 ieee80211.h 　
8979
 IEEE80211_IE_RSNIEEE80211_IE_RSN 48 ieee80211.h 　
8980
 OUI_ORG_MASKOUI_ORG_MASK 0xFFFFFF00 ieee80211.h 　
8981
 OUI_TYPE_MASKOUI_TYPE_MASK 0x000000FF ieee80211.h 　
8982
 OUI_ORG_MASKOUI_ORG_MASK 0x00FFFFFF ieee80211.h 　
8983
 OUI_TYPE_MASKOUI_TYPE_MASK 0xFF000000 ieee80211.h 　
8984
 IEEE80211_RSN_OUIIEEE80211_RSN_OUI _MKOUI ( 0x00, 0x0F, 0xAC, 0 ) ieee80211.h 　
8985
 IEEE80211_WPA_OUIIEEE80211_WPA_OUI _MKOUI ( 0x00, 0x50, 0xF2, 0 ) ieee80211.h 　
8986
 IEEE80211_WPA_OUI_VENIEEE80211_WPA_OUI_VEN _MKOUI ( 0x00, 0x50, 0xF2, 0x01 ) ieee80211.h 　
8987
 IEEE80211_RSN_VERSIONIEEE80211_RSN_VERSION 1 ieee80211.h 　
8988
 IEEE80211_RSN_CTYPE_WEP40IEEE80211_RSN_CTYPE_WEP40 _MKOUI ( 0, 0, 0, 0x01 ) ieee80211.h 　
8989
 IEEE80211_RSN_CTYPE_WEP104IEEE80211_RSN_CTYPE_WEP104 _MKOUI ( 0, 0, 0, 0x05 ) ieee80211.h 　
8990
 IEEE80211_RSN_CTYPE_TKIPIEEE80211_RSN_CTYPE_TKIP _MKOUI ( 0, 0, 0, 0x02 ) ieee80211.h 　
8991
 IEEE80211_RSN_CTYPE_CCMPIEEE80211_RSN_CTYPE_CCMP _MKOUI ( 0, 0, 0, 0x04 ) ieee80211.h 　
8992
 IEEE80211_RSN_CTYPE_USEGROUPIEEE80211_RSN_CTYPE_USEGROUP _MKOUI ( 0, 0, 0, 0x00 ) ieee80211.h 　
8993
 IEEE80211_RSN_ATYPE_8021XIEEE80211_RSN_ATYPE_8021X _MKOUI ( 0, 0, 0, 0x01 ) ieee80211.h 　
8994
 IEEE80211_RSN_ATYPE_PSKIEEE80211_RSN_ATYPE_PSK _MKOUI ( 0, 0, 0, 0x02 ) ieee80211.h 　
8995
 IEEE80211_RSN_CAPAB_PREAUTHIEEE80211_RSN_CAPAB_PREAUTH 0x001 ieee80211.h 　
8996
 IEEE80211_RSN_CAPAB_NO_PAIRWISEIEEE80211_RSN_CAPAB_NO_PAIRWISE 0x002 ieee80211.h 　
8997
 IEEE80211_RSN_CAPAB_PTKSA_REPLAIEEE80211_RSN_CAPAB_PTKSA_REPLA 0x00C ieee80211.h 　
8998
 IEEE80211_RSN_CAPAB_GTKSA_REPLAIEEE80211_RSN_CAPAB_GTKSA_REPLA 0x030 ieee80211.h 　
8999
 IEEE80211_RSN_CAPAB_PEERKEYIEEE80211_RSN_CAPAB_PEERKEY 0x200 ieee80211.h 　
9000
 IEEE80211_RSN_1_CTRIEEE80211_RSN_1_CTR 0x000 ieee80211.h 　
9001
 IEEE80211_RSN_2_CTRIEEE80211_RSN_2_CTR 0x014 ieee80211.h 　
9002
 IEEE80211_RSN_4_CTRIEEE80211_RSN_4_CTR 0x028 ieee80211.h 　
9003
 IEEE80211_RSN_16_CTRIEEE80211_RSN_16_CTR 0x03C ieee80211.h 　
9004
 IEEE80211_IE_VENDORIEEE80211_IE_VENDOR 221 ieee80211.h 　
9005
 ieee80211_beaconieee80211_beacon ieee80211_beacon_or_probe_resp ieee80211.h 　
9006
 ieee80211_probe_respieee80211_probe_resp ieee80211_beacon_or_probe_resp ieee80211.h 　
9007
 ieee80211_disassocieee80211_disassoc ieee80211_disassoc_or_deauth ieee80211.h 　
9008
 ieee80211_deauthieee80211_deauth ieee80211_disassoc_or_deauth ieee80211.h 　
9009
 ieee80211_assoc_respieee80211_assoc_resp ieee80211_assoc_or_reassoc_resp ieee80211.h 　
9010
 ieee80211_reassoc_respieee80211_reassoc_resp ieee80211_assoc_or_reassoc_resp ieee80211.h 　
9011
 IEEE80211_AUTH_OPEN_SYSTEMIEEE80211_AUTH_OPEN_SYSTEM 0 ieee80211.h 　
9012
 IEEE80211_AUTH_SHARED_KEYIEEE80211_AUTH_SHARED_KEY 1 ieee80211.h 　
9013
 ARPHRD_NETROMARPHRD_NETROM 0 if_arp.h *< from KA9Q: NET/ROM pseudo
9014
 ARPHRD_ETHERARPHRD_ETHER 1 if_arp.h *< Ethernet 10Mbps
9015
 ARPHRD_EETHERARPHRD_EETHER 2 if_arp.h *< Experimental Ethernet
9016
 ARPHRD_AX25ARPHRD_AX25 3 if_arp.h *< AX.25 Level 2
9017
 ARPHRD_PRONETARPHRD_PRONET 4 if_arp.h *< PROnet token ring
9018
 ARPHRD_CHAOSARPHRD_CHAOS 5 if_arp.h *< Chaosnet
9019
 ARPHRD_IEEE802ARPHRD_IEEE802 6 if_arp.h *< IEEE 802.2 Ethernet/TR/TB
9020
 ARPHRD_ARCNETARPHRD_ARCNET 7 if_arp.h *< ARCnet
9021
 ARPHRD_APPLETLKARPHRD_APPLETLK 8 if_arp.h *< APPLEtalk
9022
 ARPHRD_DLCIARPHRD_DLCI 15 if_arp.h *< Frame Relay DLCI
9023
 ARPHRD_ATMARPHRD_ATM 19 if_arp.h *< ATM
9024
 ARPHRD_METRICOMARPHRD_METRICOM 23 if_arp.h *< Metricom STRIP (new IANA id)
9025
 ARPHRD_IEEE1394ARPHRD_IEEE1394 24 if_arp.h *< IEEE 1394 IPv4 - RFC 2734
9026
 ARPHRD_EUI64ARPHRD_EUI64 27 if_arp.h *< EUI-64
9027
 ARPHRD_INFINIBANDARPHRD_INFINIBAND 32 if_arp.h *< InfiniBand
9028
 ARPOP_REQUESTARPOP_REQUEST 1 if_arp.h *< ARP request
9029
 ARPOP_REPLYARPOP_REPLY 2 if_arp.h *< ARP reply
9030
 ARPOP_RREQUESTARPOP_RREQUEST 3 if_arp.h *< RARP request
9031
 ARPOP_RREPLYARPOP_RREPLY 4 if_arp.h *< RARP reply
9032
 ARPOP_InREQUESTARPOP_InREQUEST 8 if_arp.h *< InARP request
9033
 ARPOP_InREPLYARPOP_InREPLY 9 if_arp.h *< InARP reply
9034
 ARPOP_NAKARPOP_NAK 10 if_arp.h *< (ATM)ARP NAK
9035
 ETH_ALENETH_ALEN 6 if_ether.h Size of Ethernet address
9036
 ETH_HLENETH_HLEN 14 if_ether.h Size of ethernet header
9037
 ETH_ZLENETH_ZLEN 60 if_ether.h Minimum packet
9038
 ETH_FRAME_LENETH_FRAME_LEN 1514 if_ether.h Maximum packet
9039
 ETH_DATA_ALIGNETH_DATA_ALIGN 2 if_ether.h Amount needed to align the data after an ethernet header
9040
 ETH_MAX_MTUETH_MAX_MTU (ETH_FRAME_LEN-ETH_HLEN) if_ether.h 　
9041
 ETH_P_RAWETH_P_RAW 0x0000 if_ether.h Raw packet
9042
 ETH_P_IPETH_P_IP 0x0800 if_ether.h Internet Protocl Packet
9043
 ETH_P_ARPETH_P_ARP 0x0806 if_ether.h Address Resolution Protocol
9044
 ETH_P_RARPETH_P_RARP 0x8035 if_ether.h Reverse Address resolution Protocol
9045
 ETH_P_IPV6ETH_P_IPV6 0x86DD if_ether.h IPv6 over blueblook
9046
 ETH_P_SLOWETH_P_SLOW 0x8809 if_ether.h Ethernet slow protocols
9047
 ETH_P_EAPOLETH_P_EAPOL 0x888E if_ether.h 802.1X EAP over LANs
9048
 ETH_P_AOEETH_P_AOE 0x88A2 if_ether.h ATA over Ethernet
9049
 IMAGE_LOADEDIMAGE_LOADED 0x0001 image.h 　
9050
 PROBE_MULTIBOOTPROBE_MULTIBOOT 01 image.h 　
9051
 PROBE_NORMALPROBE_NORMAL 02 image.h 　
9052
 PROBE_PXEPROBE_PXE 03 image.h 　
9053
 IMAGE_TYPESIMAGE_TYPES __table ( struct image_type, "image_types" ) image.h 　
9054
 IP_ICMPIP_ICMP 1 in.h 　
9055
 IP_TCPIP_TCP 6 in.h 　
9056
 IP_UDPIP_UDP 17 in.h 　
9057
 IP_ICMP6IP_ICMP6 58 in.h 　
9058
 INADDR_NONEINADDR_NONE 0xffffffff in.h 　
9059
 INADDR_BROADCASTINADDR_BROADCAST 0xffffffff in.h 　
9060
 IN_CLASSA_NETIN_CLASSA_NET 0xff000000 in.h 　
9061
 IN_CLASSB_NETIN_CLASSB_NET 0xffff0000 in.h 　
9062
 IN_CLASSC_NETIN_CLASSC_NET 0xffffff00 in.h 　
9063
 IB_QPN_SMIIB_QPN_SMI 0 infiniband.h 　
9064
 IB_QKEY_SMIIB_QKEY_SMI 0 infiniband.h 　
9065
 IB_QPN_GSIIB_QPN_GSI 1 infiniband.h 　
9066
 IB_QKEY_GSIIB_QKEY_GSI 0x80010000UL infiniband.h 　
9067
 IB_QPN_BROADCASTIB_QPN_BROADCAST 0xffffffUL infiniband.h 　
9068
 IB_QPN_MASKIB_QPN_MASK 0xffffffUL infiniband.h 　
9069
 IB_PKEY_DEFAULTIB_PKEY_DEFAULT 0xffff infiniband.h 　
9070
 IB_PKEY_FULLIB_PKEY_FULL 0x8000 infiniband.h 　
9071
 IB_MAX_PAYLOAD_SIZEIB_MAX_PAYLOAD_SIZE 2048 infiniband.h 　
9072
 INIT_FNSINIT_FNS __table ( struct init_fn, "init_fns" ) init.h 　
9073
 INIT_EARLYINIT_EARLY 01 init.h *< Early initialisation
9074
 INIT_SERIALINIT_SERIAL 02 init.h *< Serial driver initialisation
9075
 INIT_CONSOLEINIT_CONSOLE 03 init.h *< Console initialisation
9076
 INIT_NORMALINIT_NORMAL 04 init.h *< Normal initialisation
9077
 STARTUP_FNSSTARTUP_FNS __table ( struct startup_fn, "startup_fns" ) init.h 　
9078
 STARTUP_EARLYSTARTUP_EARLY 01 init.h *< Early startup
9079
 STARTUP_NORMALSTARTUP_NORMAL 02 init.h *< Normal startup
9080
 STARTUP_LATESTARTUP_LATE 03 init.h *< Late startup
9081
 IOB_ALIGNIOB_ALIGN 2048 iobuf.h 　
9082
 IOB_ZLENIOB_ZLEN 64 iobuf.h 　
9083
 IP_VERIP_VER 0x40U ip.h 　
9084
 IP_MASK_VERIP_MASK_VER 0xf0U ip.h 　
9085
 IP_MASK_HLENIP_MASK_HLEN 0x0fU ip.h 　
9086
 IP_MASK_OFFSETIP_MASK_OFFSET 0x1fffU ip.h 　
9087
 IP_MASK_DONOTFRAGIP_MASK_DONOTFRAG 0x4000U ip.h 　
9088
 IP_MASK_MOREFRAGSIP_MASK_MOREFRAGS 0x2000U ip.h 　
9089
 IP_PSHLENIP_PSHLEN 12 ip.h 　
9090
 IP_TOSIP_TOS 0 ip.h 　
9091
 IP_TTLIP_TTL 64 ip.h 　
9092
 IP_FRAG_IOB_SIZEIP_FRAG_IOB_SIZE 1500 ip.h 　
9093
 IP_FRAG_TIMEOUTIP_FRAG_TIMEOUT 50 ip.h 　
9094
 IP6_VERSIONIP6_VERSION 0x6 ip6.h 　
9095
 IP6_HOP_LIMITIP6_HOP_LIMIT 255 ip6.h 　
9096
 MAX_HDR_LENMAX_HDR_LEN 100 ip6.h 　
9097
 MAX_IOB_LENMAX_IOB_LEN 1500 ip6.h 　
9098
 MIN_IOB_LENMIN_IOB_LEN MAX_HDR_LEN + 100 ip6.h To account for padding by LL
9099
 IP6_HOPBYHOPIP6_HOPBYHOP 0x00 ip6.h 　
9100
 IP6_ROUTINGIP6_ROUTING 0x43 ip6.h 　
9101
 IP6_FRAGMENTIP6_FRAGMENT 0x44 ip6.h 　
9102
 IP6_AUTHENTICATIONIP6_AUTHENTICATION 0x51 ip6.h 　
9103
 IP6_DEST_OPTSIP6_DEST_OPTS 0x60 ip6.h 　
9104
 IP6_ESPIP6_ESP 0x50 ip6.h 　
9105
 IP6_ICMP6IP6_ICMP6 0x58 ip6.h 　
9106
 IP6_NO_HEADERIP6_NO_HEADER 0x59 ip6.h 　
9107
 IPOIB_ALENIPOIB_ALEN 20 ipoib.h 　
9108
 IPOIB_HLENIPOIB_HLEN 4 ipoib.h 　
9109
 ISA_DRIVERSISA_DRIVERS __table ( struct isa_driver, "isa_drivers" ) isa.h 　
9110
 __isa_driver__isa_driver __table_entry ( ISA_DRIVERS, 01 ) isa.h 　
9111
 ISAPNP_ADDRESSISAPNP_ADDRESS 0x279 isapnp.h 　
9112
 ISAPNP_WRITE_DATAISAPNP_WRITE_DATA 0xa79 isapnp.h 　
9113
 ISAPNP_READ_PORT_MINISAPNP_READ_PORT_MIN 0x203 isapnp.h 　
9114
 ISAPNP_READ_PORT_STARTISAPNP_READ_PORT_START 0x213 isapnp.h ISAPnP spec says 0x203, but
9115
 ISAPNP_READ_PORT_MAXISAPNP_READ_PORT_MAX 0x3ff isapnp.h 　
9116
 ISAPNP_READ_PORT_STEPISAPNP_READ_PORT_STEP 0x10 isapnp.h Can be any multiple of 4
9117
 ISAPNP_CSN_MINISAPNP_CSN_MIN 0x01 isapnp.h 　
9118
 ISAPNP_CSN_MAXISAPNP_CSN_MAX 0x0f isapnp.h 　
9119
 ISAPNP_READPORTISAPNP_READPORT 0x00 isapnp.h 　
9120
 ISAPNP_SERIALISOLATIONISAPNP_SERIALISOLATION 0x01 isapnp.h 　
9121
 ISAPNP_CONFIGCONTROLISAPNP_CONFIGCONTROL 0x02 isapnp.h 　
9122
 ISAPNP_WAKEISAPNP_WAKE 0x03 isapnp.h 　
9123
 ISAPNP_RESOURCEDATAISAPNP_RESOURCEDATA 0x04 isapnp.h 　
9124
 ISAPNP_STATUSISAPNP_STATUS 0x05 isapnp.h 　
9125
 ISAPNP_CARDSELECTNUMBERISAPNP_CARDSELECTNUMBER 0x06 isapnp.h 　
9126
 ISAPNP_LOGICALDEVICENUMBERISAPNP_LOGICALDEVICENUMBER 0x07 isapnp.h 　
9127
 ISAPNP_ACTIVATEISAPNP_ACTIVATE 0x30 isapnp.h 　
9128
 ISAPNP_IORANGECHECKISAPNP_IORANGECHECK 0x31 isapnp.h 　
9129
 ISAPNP_CONFIG_RESETISAPNP_CONFIG_RESET ( 1 << 0 ) isapnp.h 　
9130
 ISAPNP_CONFIG_WAIT_FOR_KEYISAPNP_CONFIG_WAIT_FOR_KEY ( 1 << 1 ) isapnp.h 　
9131
 ISAPNP_CONFIG_RESET_CSNISAPNP_CONFIG_RESET_CSN ( 1 << 2 ) isapnp.h 　
9132
 ISAPNP_CONFIG_RESET_DRVISAPNP_CONFIG_RESET_DRV ( ISAPNP_CONFIG_RESET | \ ISAPNP_CONFIG_WAIT_FOR_KEY | \ ISAPNP_CONFIG_RESET_CSN ) isapnp.h 　
9133
 ISAPNP_LFSR_SEEDISAPNP_LFSR_SEED 0x6a isapnp.h 　
9134
 ISAPNP_TAG_PNPVERNOISAPNP_TAG_PNPVERNO 0x01 isapnp.h 　
9135
 ISAPNP_TAG_LOGDEVIDISAPNP_TAG_LOGDEVID 0x02 isapnp.h 　
9136
 ISAPNP_TAG_COMPATDEVIDISAPNP_TAG_COMPATDEVID 0x03 isapnp.h 　
9137
 ISAPNP_TAG_IRQISAPNP_TAG_IRQ 0x04 isapnp.h 　
9138
 ISAPNP_TAG_DMAISAPNP_TAG_DMA 0x05 isapnp.h 　
9139
 ISAPNP_TAG_STARTDEPISAPNP_TAG_STARTDEP 0x06 isapnp.h 　
9140
 ISAPNP_TAG_ENDDEPISAPNP_TAG_ENDDEP 0x07 isapnp.h 　
9141
 ISAPNP_TAG_IOPORTISAPNP_TAG_IOPORT 0x08 isapnp.h 　
9142
 ISAPNP_TAG_FIXEDIOISAPNP_TAG_FIXEDIO 0x09 isapnp.h 　
9143
 ISAPNP_TAG_RSVDSHORTAISAPNP_TAG_RSVDSHORTA 0x0A isapnp.h 　
9144
 ISAPNP_TAG_RSVDSHORTBISAPNP_TAG_RSVDSHORTB 0x0B isapnp.h 　
9145
 ISAPNP_TAG_RSVDSHORTCISAPNP_TAG_RSVDSHORTC 0x0C isapnp.h 　
9146
 ISAPNP_TAG_RSVDSHORTDISAPNP_TAG_RSVDSHORTD 0x0D isapnp.h 　
9147
 ISAPNP_TAG_VENDORSHORTISAPNP_TAG_VENDORSHORT 0x0E isapnp.h 　
9148
 ISAPNP_TAG_ENDISAPNP_TAG_END 0x0F isapnp.h 　
9149
 ISAPNP_TAG_MEMRANGEISAPNP_TAG_MEMRANGE 0x81 isapnp.h 　
9150
 ISAPNP_TAG_ANSISTRISAPNP_TAG_ANSISTR 0x82 isapnp.h 　
9151
 ISAPNP_TAG_UNICODESTRISAPNP_TAG_UNICODESTR 0x83 isapnp.h 　
9152
 ISAPNP_TAG_VENDORLONGISAPNP_TAG_VENDORLONG 0x84 isapnp.h 　
9153
 ISAPNP_TAG_MEM32RANGEISAPNP_TAG_MEM32RANGE 0x85 isapnp.h 　
9154
 ISAPNP_TAG_FIXEDMEM32RANGEISAPNP_TAG_FIXEDMEM32RANGE 0x86 isapnp.h 　
9155
 ISAPNP_TAG_RSVDLONG0ISAPNP_TAG_RSVDLONG0 0xF0 isapnp.h 　
9156
 ISAPNP_TAG_RSVDLONG1ISAPNP_TAG_RSVDLONG1 0xF1 isapnp.h 　
9157
 ISAPNP_TAG_RSVDLONG2ISAPNP_TAG_RSVDLONG2 0xF2 isapnp.h 　
9158
 ISAPNP_TAG_RSVDLONG3ISAPNP_TAG_RSVDLONG3 0xF3 isapnp.h 　
9159
 ISAPNP_TAG_RSVDLONG4ISAPNP_TAG_RSVDLONG4 0xF4 isapnp.h 　
9160
 ISAPNP_TAG_RSVDLONG5ISAPNP_TAG_RSVDLONG5 0xF5 isapnp.h 　
9161
 ISAPNP_TAG_RSVDLONG6ISAPNP_TAG_RSVDLONG6 0xF6 isapnp.h 　
9162
 ISAPNP_TAG_RSVDLONG7ISAPNP_TAG_RSVDLONG7 0xF7 isapnp.h 　
9163
 ISAPNP_TAG_RSVDLONG8ISAPNP_TAG_RSVDLONG8 0xF8 isapnp.h 　
9164
 ISAPNP_TAG_RSVDLONG9ISAPNP_TAG_RSVDLONG9 0xF9 isapnp.h 　
9165
 ISAPNP_TAG_RSVDLONGAISAPNP_TAG_RSVDLONGA 0xFA isapnp.h 　
9166
 ISAPNP_TAG_RSVDLONGBISAPNP_TAG_RSVDLONGB 0xFB isapnp.h 　
9167
 ISAPNP_TAG_RSVDLONGCISAPNP_TAG_RSVDLONGC 0xFC isapnp.h 　
9168
 ISAPNP_TAG_RSVDLONGDISAPNP_TAG_RSVDLONGD 0xFD isapnp.h 　
9169
 ISAPNP_TAG_RSVDLONGEISAPNP_TAG_RSVDLONGE 0xFE isapnp.h 　
9170
 ISAPNP_TAG_RSVDLONGFISAPNP_TAG_RSVDLONGF 0xFF isapnp.h 　
9171
 ISAPNP_TAG_PSEUDO_NEWBOARDISAPNP_TAG_PSEUDO_NEWBOARD 0x100 isapnp.h 　
9172
 ISAPNP_DRIVERSISAPNP_DRIVERS __table ( struct isapnp_driver, "isapnp_drivers" ) isapnp.h 　
9173
 __isapnp_driver__isapnp_driver __table_entry ( ISAPNP_DRIVERS, 01 ) isapnp.h 　
9174
 GENERIC_ISAPNP_VENDORGENERIC_ISAPNP_VENDOR ISAPNP_VENDOR ( 'P','N','P' ) isa_ids.h 　
9175
 ISA_PROD_ID_MASKISA_PROD_ID_MASK ( 0xf0ff ) isa_ids.h 　
9176
 ISCSI_PORTISCSI_PORT 3260 iscsi.h 　
9177
 ISCSI_OPCODE_MASKISCSI_OPCODE_MASK 0x3f iscsi.h 　
9178
 ISCSI_FLAG_IMMEDIATEISCSI_FLAG_IMMEDIATE 0x40 iscsi.h 　
9179
 ISCSI_FLAG_FINALISCSI_FLAG_FINAL 0x80 iscsi.h 　
9180
 ISCSI_OPCODE_LOGIN_REQUESTISCSI_OPCODE_LOGIN_REQUEST 0x03 iscsi.h 　
9181
 ISCSI_LOGIN_FLAG_TRANSITIONISCSI_LOGIN_FLAG_TRANSITION 0x80 iscsi.h 　
9182
 ISCSI_LOGIN_FLAG_CONTINUEISCSI_LOGIN_FLAG_CONTINUE 0x40 iscsi.h 　
9183
 ISCSI_LOGIN_CSG_MASKISCSI_LOGIN_CSG_MASK 0x0c iscsi.h 　
9184
 ISCSI_LOGIN_CSG_SECURITY_NEGOTIISCSI_LOGIN_CSG_SECURITY_NEGOTI 0x00 iscsi.h 　
9185
 ISCSI_LOGIN_CSG_OPERATIONAL_NEGISCSI_LOGIN_CSG_OPERATIONAL_NEG 0x04 iscsi.h 　
9186
 ISCSI_LOGIN_CSG_FULL_FEATURE_PHISCSI_LOGIN_CSG_FULL_FEATURE_PH 0x0c iscsi.h 　
9187
 ISCSI_LOGIN_NSG_MASKISCSI_LOGIN_NSG_MASK 0x03 iscsi.h 　
9188
 ISCSI_LOGIN_NSG_SECURITY_NEGOTIISCSI_LOGIN_NSG_SECURITY_NEGOTI 0x00 iscsi.h 　
9189
 ISCSI_LOGIN_NSG_OPERATIONAL_NEGISCSI_LOGIN_NSG_OPERATIONAL_NEG 0x01 iscsi.h 　
9190
 ISCSI_LOGIN_NSG_FULL_FEATURE_PHISCSI_LOGIN_NSG_FULL_FEATURE_PH 0x03 iscsi.h 　
9191
 ISCSI_ISID_IANAISCSI_ISID_IANA 0x40000000 iscsi.h 　
9192
 IANA_EN_FEN_SYSTEMSIANA_EN_FEN_SYSTEMS 10019 iscsi.h 　
9193
 ISCSI_OPCODE_LOGIN_RESPONSEISCSI_OPCODE_LOGIN_RESPONSE 0x23 iscsi.h 　
9194
 ISCSI_STATUS_SUCCESSISCSI_STATUS_SUCCESS 0x00 iscsi.h 　
9195
 ISCSI_STATUS_REDIRECTISCSI_STATUS_REDIRECT 0x01 iscsi.h 　
9196
 ISCSI_STATUS_INITIATOR_ERRORISCSI_STATUS_INITIATOR_ERROR 0x02 iscsi.h 　
9197
 ISCSI_STATUS_INITIATOR_ERROR_AUISCSI_STATUS_INITIATOR_ERROR_AU 0x01 iscsi.h 　
9198
 ISCSI_STATUS_INITIATOR_ERROR_AUISCSI_STATUS_INITIATOR_ERROR_AU 0x02 iscsi.h 　
9199
 ISCSI_STATUS_INITIATOR_ERROR_NOISCSI_STATUS_INITIATOR_ERROR_NO 0x03 iscsi.h 　
9200
 ISCSI_STATUS_INITIATOR_ERROR_REISCSI_STATUS_INITIATOR_ERROR_RE 0x04 iscsi.h 　
9201
 ISCSI_STATUS_TARGET_ERRORISCSI_STATUS_TARGET_ERROR 0x03 iscsi.h 　
9202
 ISCSI_OPCODE_SCSI_COMMANDISCSI_OPCODE_SCSI_COMMAND 0x01 iscsi.h 　
9203
 ISCSI_COMMAND_FLAG_READISCSI_COMMAND_FLAG_READ 0x40 iscsi.h 　
9204
 ISCSI_COMMAND_FLAG_WRITEISCSI_COMMAND_FLAG_WRITE 0x20 iscsi.h 　
9205
 ISCSI_COMMAND_ATTR_UNTAGGEDISCSI_COMMAND_ATTR_UNTAGGED 0x00 iscsi.h 　
9206
 ISCSI_COMMAND_ATTR_SIMPLEISCSI_COMMAND_ATTR_SIMPLE 0x01 iscsi.h 　
9207
 ISCSI_COMMAND_ATTR_ORDEREDISCSI_COMMAND_ATTR_ORDERED 0x02 iscsi.h 　
9208
 ISCSI_COMMAND_ATTR_HEAD_OF_QUEUISCSI_COMMAND_ATTR_HEAD_OF_QUEU 0x03 iscsi.h 　
9209
 ISCSI_COMMAND_ATTR_ACAISCSI_COMMAND_ATTR_ACA 0x04 iscsi.h 　
9210
 ISCSI_OPCODE_SCSI_RESPONSEISCSI_OPCODE_SCSI_RESPONSE 0x21 iscsi.h 　
9211
 ISCSI_RESPONSE_COMMAND_COMPLETEISCSI_RESPONSE_COMMAND_COMPLETE 0x00 iscsi.h 　
9212
 ISCSI_RESPONSE_TARGET_FAILUREISCSI_RESPONSE_TARGET_FAILURE 0x01 iscsi.h 　
9213
 ISCSI_SENSE_RESPONSE_CODE_OFFSEISCSI_SENSE_RESPONSE_CODE_OFFSE 2 iscsi.h 　
9214
 ISCSI_OPCODE_DATA_INISCSI_OPCODE_DATA_IN 0x25 iscsi.h 　
9215
 ISCSI_DATA_FLAG_ACKNOWLEDGEISCSI_DATA_FLAG_ACKNOWLEDGE 0x40 iscsi.h 　
9216
 ISCSI_DATA_FLAG_OVERFLOWISCSI_DATA_FLAG_OVERFLOW 0x04 iscsi.h 　
9217
 ISCSI_DATA_FLAG_UNDERFLOWISCSI_DATA_FLAG_UNDERFLOW 0x02 iscsi.h 　
9218
 ISCSI_DATA_FLAG_STATUSISCSI_DATA_FLAG_STATUS 0x01 iscsi.h 　
9219
 ISCSI_OPCODE_DATA_OUTISCSI_OPCODE_DATA_OUT 0x05 iscsi.h 　
9220
 ISCSI_OPCODE_R2TISCSI_OPCODE_R2T 0x31 iscsi.h 　
9221
 ISCSI_STATUS_SECURITY_NEGOTIATIISCSI_STATUS_SECURITY_NEGOTIATI ( ISCSI_LOGIN_CSG_SECURITY_NEGOTIATION | \ ISCSI_LOGIN_NSG_OPERATIONAL_NEGOTIATION ) iscsi.h 　
9222
 ISCSI_STATUS_OPERATIONAL_NEGOTIISCSI_STATUS_OPERATIONAL_NEGOTI ( ISCSI_LOGIN_CSG_OPERATIONAL_NEGOTIATION | \ ISCSI_LOGIN_NSG_FULL_FEATURE_PHASE ) iscsi.h 　
9223
 ISCSI_STATUS_FULL_FEATURE_PHASEISCSI_STATUS_FULL_FEATURE_PHASE ISCSI_LOGIN_CSG_FULL_FEATURE_PHASE iscsi.h 　
9224
 ISCSI_STATUS_PHASE_MASKISCSI_STATUS_PHASE_MASK ( ISCSI_LOGIN_CSG_MASK | ISCSI_LOGIN_NSG_MASK ) iscsi.h 　
9225
 ISCSI_STATUS_STRINGS_SECURITYISCSI_STATUS_STRINGS_SECURITY 0x0100 iscsi.h 　
9226
 ISCSI_STATUS_STRINGS_CHAP_ALGORISCSI_STATUS_STRINGS_CHAP_ALGOR 0x0200 iscsi.h 　
9227
 ISCSI_STATUS_STRINGS_CHAP_RESPOISCSI_STATUS_STRINGS_CHAP_RESPO 0x0400 iscsi.h 　
9228
 ISCSI_STATUS_STRINGS_CHAP_CHALLISCSI_STATUS_STRINGS_CHAP_CHALL 0x0800 iscsi.h 　
9229
 ISCSI_STATUS_STRINGS_OPERATIONAISCSI_STATUS_STRINGS_OPERATIONA 0x1000 iscsi.h 　
9230
 ISCSI_STATUS_STRINGS_MASKISCSI_STATUS_STRINGS_MASK 0xff00 iscsi.h 　
9231
 ISCSI_STATUS_AUTH_FORWARD_REQUIISCSI_STATUS_AUTH_FORWARD_REQUI 0x00010000 iscsi.h 　
9232
 ISCSI_STATUS_AUTH_REVERSE_REQUIISCSI_STATUS_AUTH_REVERSE_REQUI 0x00020000 iscsi.h 　
9233
 ISCSI_STATUS_AUTH_REVERSE_OKISCSI_STATUS_AUTH_REVERSE_OK 0x00040000 iscsi.h 　
9234
 ISCSI_MAX_RETRIESISCSI_MAX_RETRIES 2 iscsi.h 　
9235
 NULNUL 0x00 keys.h 　
9236
 CTRL_ACTRL_A 0x01 keys.h 　
9237
 CTRL_BCTRL_B 0x02 keys.h 　
9238
 CTRL_CCTRL_C 0x03 keys.h 　
9239
 CTRL_DCTRL_D 0x04 keys.h 　
9240
 CTRL_ECTRL_E 0x05 keys.h 　
9241
 CTRL_FCTRL_F 0x06 keys.h 　
9242
 CTRL_GCTRL_G 0x07 keys.h 　
9243
 CTRL_HCTRL_H 0x08 keys.h 　
9244
 CTRL_ICTRL_I 0x09 keys.h 　
9245
 CTRL_JCTRL_J 0x0a keys.h 　
9246
 CTRL_KCTRL_K 0x0b keys.h 　
9247
 CTRL_LCTRL_L 0x0c keys.h 　
9248
 CTRL_MCTRL_M 0x0d keys.h 　
9249
 CTRL_NCTRL_N 0x0e keys.h 　
9250
 CTRL_OCTRL_O 0x0f keys.h 　
9251
 CTRL_PCTRL_P 0x10 keys.h 　
9252
 CTRL_QCTRL_Q 0x11 keys.h 　
9253
 CTRL_RCTRL_R 0x12 keys.h 　
9254
 CTRL_SCTRL_S 0x13 keys.h 　
9255
 CTRL_TCTRL_T 0x14 keys.h 　
9256
 CTRL_UCTRL_U 0x15 keys.h 　
9257
 CTRL_VCTRL_V 0x16 keys.h 　
9258
 CTRL_WCTRL_W 0x17 keys.h 　
9259
 CTRL_XCTRL_X 0x18 keys.h 　
9260
 CTRL_YCTRL_Y 0x19 keys.h 　
9261
 CTRL_ZCTRL_Z 0x1a keys.h 　
9262
 BACKSPACEBACKSPACE CTRL_H keys.h 　
9263
 TABTAB CTRL_I keys.h 　
9264
 LFLF CTRL_J keys.h 　
9265
 CRCR CTRL_M keys.h 　
9266
 ESCESC 0x1b keys.h 　
9267
 KEY_MINKEY_MIN 0x101 keys.h 　
9268
 KEY_UPKEY_UP KEY_ANSI ( 0, 'A' ) keys.h *< Up arrow
9269
 KEY_DOWNKEY_DOWN KEY_ANSI ( 0, 'B' ) keys.h *< Down arrow
9270
 KEY_RIGHTKEY_RIGHT KEY_ANSI ( 0, 'C' ) keys.h *< Right arrow
9271
 KEY_LEFTKEY_LEFT KEY_ANSI ( 0, 'D' ) keys.h *< Left arrow
9272
 KEY_ENDKEY_END KEY_ANSI ( 0, 'F' ) keys.h *< End
9273
 KEY_HOMEKEY_HOME KEY_ANSI ( 0, 'H' ) keys.h *< Home
9274
 KEY_ICKEY_IC KEY_ANSI ( 2, '~' ) keys.h *< Insert
9275
 KEY_DCKEY_DC KEY_ANSI ( 3, '~' ) keys.h *< Delete
9276
 KEY_PPAGEKEY_PPAGE KEY_ANSI ( 5, '~' ) keys.h *< Page up
9277
 KEY_NPAGEKEY_NPAGE KEY_ANSI ( 6, '~' ) keys.h *< Page down
9278
 KEY_F8KEY_F8 KEY_ANSI ( 19, '~' ) keys.h *< F8 (for PXE)
9279
 KEY_BACKSPACEKEY_BACKSPACE BACKSPACE keys.h 　
9280
 KEY_ENTERKEY_ENTER LF keys.h 　
9281
 printkprintk printf linux_compat.h 　
9282
 MCA_MOTHERBOARD_SETUP_REGMCA_MOTHERBOARD_SETUP_REG 0x94 mca.h 　
9283
 MCA_ADAPTER_SETUP_REGMCA_ADAPTER_SETUP_REG 0x96 mca.h 　
9284
 MCA_MAX_SLOT_NRMCA_MAX_SLOT_NR 0x07 mca.h Must be 2^n - 1
9285
 GENERIC_MCA_VENDORGENERIC_MCA_VENDOR ISA_VENDOR ( 'M', 'C', 'A' ) mca.h 　
9286
 MCA_DRIVERSMCA_DRIVERS __table ( struct mca_driver, "mca_drivers" ) mca.h 　
9287
 __mca_driver__mca_driver __table_entry ( MCA_DRIVERS, 01 ) mca.h 　
9288
 MD5_DIGEST_SIZEMD5_DIGEST_SIZE 16 md5.h 　
9289
 MD5_BLOCK_WORDSMD5_BLOCK_WORDS 16 md5.h 　
9290
 MD5_HASH_WORDSMD5_HASH_WORDS 4 md5.h 　
9291
 MD5_CTX_SIZEMD5_CTX_SIZE sizeof ( struct md5_ctx ) md5.h 　
9292
 MAX_MEMORY_REGIONSMAX_MEMORY_REGIONS 8 memmap.h 　
9293
 NDP_STATE_INVALIDNDP_STATE_INVALID 0 ndp.h 　
9294
 NDP_STATE_INCOMPLETENDP_STATE_INCOMPLETE 1 ndp.h 　
9295
 NDP_STATE_REACHABLENDP_STATE_REACHABLE 2 ndp.h 　
9296
 NDP_STATE_DELAYNDP_STATE_DELAY 3 ndp.h 　
9297
 NDP_STATE_PROBENDP_STATE_PROBE 4 ndp.h 　
9298
 NDP_STATE_STALENDP_STATE_STALE 5 ndp.h 　
9299
 NET80211_BAND_2GHZNET80211_BAND_2GHZ 0 net80211.h 　
9300
 NET80211_BAND_5GHZNET80211_BAND_5GHZ 1 net80211.h 　
9301
 NET80211_NR_BANDSNET80211_NR_BANDS 2 net80211.h 　
9302
 NET80211_BAND_BIT_2GHZNET80211_BAND_BIT_2GHZ (1 << 0) net80211.h 　
9303
 NET80211_BAND_BIT_5GHZNET80211_BAND_BIT_5GHZ (1 << 1) net80211.h 　
9304
 NET80211_MODE_ANET80211_MODE_A (1 << 0) net80211.h 　
9305
 NET80211_MODE_BNET80211_MODE_B (1 << 1) net80211.h 　
9306
 NET80211_MODE_GNET80211_MODE_G (1 << 2) net80211.h 　
9307
 NET80211_MODE_NNET80211_MODE_N (1 << 3) net80211.h 　
9308
 NET80211_CFG_CHANNELNET80211_CFG_CHANNEL (1 << 0) net80211.h 　
9309
 NET80211_CFG_RATENET80211_CFG_RATE (1 << 1) net80211.h 　
9310
 NET80211_CFG_ASSOCNET80211_CFG_ASSOC (1 << 2) net80211.h 　
9311
 NET80211_CFG_PHY_PARAMSNET80211_CFG_PHY_PARAMS (1 << 3) net80211.h 　
9312
 NET80211_STATUS_MASKNET80211_STATUS_MASK 0x7F net80211.h 　
9313
 NET80211_IS_REASONNET80211_IS_REASON 0x80 net80211.h 　
9314
 NET80211_PROBEDNET80211_PROBED (1 << 8) net80211.h 　
9315
 NET80211_AUTHENTICATEDNET80211_AUTHENTICATED (1 << 9) net80211.h 　
9316
 NET80211_ASSOCIATEDNET80211_ASSOCIATED (1 << 10) net80211.h 　
9317
 NET80211_CRYPTO_SYNCEDNET80211_CRYPTO_SYNCED (1 << 11) net80211.h 　
9318
 NET80211_WORKINGNET80211_WORKING (1 << 12) net80211.h 　
9319
 NET80211_WAITINGNET80211_WAITING (1 << 13) net80211.h 　
9320
 NET80211_NO_ASSOCNET80211_NO_ASSOC (1 << 14) net80211.h 　
9321
 NET80211_AUTO_SSIDNET80211_AUTO_SSID (1 << 15) net80211.h 　
9322
 NET80211_PHY_USE_PROTECTIONNET80211_PHY_USE_PROTECTION (1 << 1) net80211.h 　
9323
 NET80211_PHY_USE_SHORT_PREAMBLENET80211_PHY_USE_SHORT_PREAMBLE (1 << 2) net80211.h 　
9324
 NET80211_PHY_USE_SHORT_SLOTNET80211_PHY_USE_SHORT_SLOT (1 << 3) net80211.h 　
9325
 NET80211_MAX_RATESNET80211_MAX_RATES 16 net80211.h 　
9326
 NET80211_MAX_CHANNELSNET80211_MAX_CHANNELS 32 net80211.h 　
9327
 NET80211_FRAG_TIMEOUTNET80211_FRAG_TIMEOUT 2 net80211.h 　
9328
 NET80211_NR_CONCURRENT_FRAGSNET80211_NR_CONCURRENT_FRAGS 3 net80211.h 　
9329
 NET80211_REG_TXPOWERNET80211_REG_TXPOWER 20 net80211.h 　
9330
 NET80211_HANDSHAKERSNET80211_HANDSHAKERS __table ( struct net80211_handshaker, \ "net80211_handshakers" ) net80211.h 　
9331
 __net80211_handshaker__net80211_handshaker __table_entry ( NET80211_HANDSHAKERS, 01 ) net80211.h 　
9332
 NET80211_CRYPTOSNET80211_CRYPTOS __table ( struct net80211_crypto, "net80211_cryptos" ) net80211.h 　
9333
 __net80211_crypto__net80211_crypto __table_entry ( NET80211_CRYPTOS, 01 ) net80211.h 　
9334
 MAX_HW_ADDR_LENMAX_HW_ADDR_LEN 8 netdevice.h 　
9335
 MAX_LL_ADDR_LENMAX_LL_ADDR_LEN 20 netdevice.h 　
9336
 MAX_LL_HEADER_LENMAX_LL_HEADER_LEN 32 netdevice.h 　
9337
 MAX_NET_ADDR_LENMAX_NET_ADDR_LEN 4 netdevice.h 　
9338
 NETDEV_MAX_UNIQUE_ERRORSNETDEV_MAX_UNIQUE_ERRORS 4 netdevice.h 　
9339
 NETDEV_OPENNETDEV_OPEN 0x0001 netdevice.h 　
9340
 NETDEV_IRQ_ENABLEDNETDEV_IRQ_ENABLED 0x0002 netdevice.h 　
9341
 LL_PROTOCOLSLL_PROTOCOLS __table ( struct ll_protocol, "ll_protocols" ) netdevice.h 　
9342
 __ll_protocol__ll_protocol __table_entry ( LL_PROTOCOLS, 01 ) netdevice.h 　
9343
 NET_PROTOCOLSNET_PROTOCOLS __table ( struct net_protocol, "net_protocols" ) netdevice.h 　
9344
 __net_protocol__net_protocol __table_entry ( NET_PROTOCOLS, 01 ) netdevice.h 　
9345
 NAP_PREFIX_nullNAP_PREFIX_null __null_ null_nap.h 　
9346
 URI_OPENERSURI_OPENERS __table ( struct uri_opener, "uri_openers" ) open.h 　
9347
 __uri_opener__uri_opener __table_entry ( URI_OPENERS, 01 ) open.h 　
9348
 SOCKET_OPENERSSOCKET_OPENERS __table ( struct socket_opener, "socket_openers" ) open.h 　
9349
 __socket_opener__socket_opener __table_entry ( SOCKET_OPENERS, 01 ) open.h 　
9350
 PCI_COMMAND_IOPCI_COMMAND_IO 0x1 pci.h Enable response in I/O space
9351
 PCI_COMMAND_MEMPCI_COMMAND_MEM 0x2 pci.h Enable response in mem space
9352
 PCI_COMMAND_MASTERPCI_COMMAND_MASTER 0x4 pci.h Enable bus mastering
9353
 PCI_CACHE_LINE_SIZEPCI_CACHE_LINE_SIZE 0x0c pci.h 8 bits
9354
 PCI_LATENCY_TIMERPCI_LATENCY_TIMER 0x0d pci.h 8 bits
9355
 PCI_COMMAND_SPECIALPCI_COMMAND_SPECIAL 0x8 pci.h Enable response to special cycles
9356
 PCI_COMMAND_INVALIDATEPCI_COMMAND_INVALIDATE 0x10 pci.h Use memory write and invalidate
9357
 PCI_COMMAND_VGA_PALETTEPCI_COMMAND_VGA_PALETTE 0x20 pci.h Enable palette snooping
9358
 PCI_COMMAND_PARITYPCI_COMMAND_PARITY 0x40 pci.h Enable parity checking
9359
 PCI_COMMAND_WAITPCI_COMMAND_WAIT 0x80 pci.h Enable address/data stepping
9360
 PCI_COMMAND_SERRPCI_COMMAND_SERR 0x100 pci.h Enable SERR
9361
 PCI_COMMAND_FAST_BACKPCI_COMMAND_FAST_BACK 0x200 pci.h Enable back-to-back writes
9362
 PCI_COMMAND_INTX_DISABLEPCI_COMMAND_INTX_DISABLE 0x400 pci.h INTx Emulation Disable
9363
 PCI_VENDOR_IDPCI_VENDOR_ID 0x00 pci.h 16 bits
9364
 PCI_DEVICE_IDPCI_DEVICE_ID 0x02 pci.h 16 bits
9365
 PCI_COMMANDPCI_COMMAND 0x04 pci.h 16 bits
9366
 PCI_STATUSPCI_STATUS 0x06 pci.h 16 bits
9367
 PCI_STATUS_CAP_LISTPCI_STATUS_CAP_LIST 0x10 pci.h Support Capability List
9368
 PCI_STATUS_66MHZPCI_STATUS_66MHZ 0x20 pci.h Support 66 Mhz PCI 2.1 bus
9369
 PCI_STATUS_UDFPCI_STATUS_UDF 0x40 pci.h Support User Definable Features [obsolete]
9370
 PCI_STATUS_FAST_BACKPCI_STATUS_FAST_BACK 0x80 pci.h Accept fast-back to back
9371
 PCI_STATUS_PARITYPCI_STATUS_PARITY 0x100 pci.h Detected parity error
9372
 PCI_STATUS_DEVSEL_MASKPCI_STATUS_DEVSEL_MASK 0x600 pci.h DEVSEL timing
9373
 PCI_STATUS_DEVSEL_FASTPCI_STATUS_DEVSEL_FAST 0x000 pci.h 　
9374
 PCI_STATUS_DEVSEL_MEDIUMPCI_STATUS_DEVSEL_MEDIUM 0x200 pci.h 　
9375
 PCI_STATUS_DEVSEL_SLOWPCI_STATUS_DEVSEL_SLOW 0x400 pci.h 　
9376
 PCI_STATUS_SIG_TARGET_ABORTPCI_STATUS_SIG_TARGET_ABORT 0x800 pci.h Set on target abort
9377
 PCI_STATUS_REC_TARGET_ABORTPCI_STATUS_REC_TARGET_ABORT 0x1000 pci.h Master ack of "
9378
 PCI_STATUS_REC_MASTER_ABORTPCI_STATUS_REC_MASTER_ABORT 0x2000 pci.h Set on master abort
9379
 PCI_STATUS_SIG_SYSTEM_ERRORPCI_STATUS_SIG_SYSTEM_ERROR 0x4000 pci.h Set when we drive SERR
9380
 PCI_STATUS_DETECTED_PARITYPCI_STATUS_DETECTED_PARITY 0x8000 pci.h Set on parity error
9381
 PCI_REVISIONPCI_REVISION 0x08 pci.h 8 bits
9382
 PCI_REVISION_IDPCI_REVISION_ID 0x08 pci.h 8 bits
9383
 PCI_CLASS_REVISIONPCI_CLASS_REVISION 0x08 pci.h 32 bits
9384
 PCI_CLASS_CODEPCI_CLASS_CODE 0x0b pci.h 8 bits
9385
 PCI_SUBCLASS_CODEPCI_SUBCLASS_CODE 0x0a pci.h 8 bits
9386
 PCI_HEADER_TYPEPCI_HEADER_TYPE 0x0e pci.h 8 bits
9387
 PCI_HEADER_TYPE_NORMALPCI_HEADER_TYPE_NORMAL 0 pci.h 　
9388
 PCI_HEADER_TYPE_BRIDGEPCI_HEADER_TYPE_BRIDGE 1 pci.h 　
9389
 PCI_HEADER_TYPE_CARDBUSPCI_HEADER_TYPE_CARDBUS 2 pci.h 　
9390
 PCI_CARDBUS_CISPCI_CARDBUS_CIS 0x28 pci.h 　
9391
 PCI_SUBSYSTEM_VENDOR_IDPCI_SUBSYSTEM_VENDOR_ID 0x2c pci.h 　
9392
 PCI_SUBSYSTEM_IDPCI_SUBSYSTEM_ID 0x2e pci.h 　
9393
 PCI_BASE_ADDRESS_0PCI_BASE_ADDRESS_0 0x10 pci.h 32 bits
9394
 PCI_BASE_ADDRESS_1PCI_BASE_ADDRESS_1 0x14 pci.h 32 bits
9395
 PCI_BASE_ADDRESS_2PCI_BASE_ADDRESS_2 0x18 pci.h 32 bits
9396
 PCI_BASE_ADDRESS_3PCI_BASE_ADDRESS_3 0x1c pci.h 32 bits
9397
 PCI_BASE_ADDRESS_4PCI_BASE_ADDRESS_4 0x20 pci.h 32 bits
9398
 PCI_BASE_ADDRESS_5PCI_BASE_ADDRESS_5 0x24 pci.h 32 bits
9399
 PCI_BASE_ADDRESS_SPACEPCI_BASE_ADDRESS_SPACE 0x01 pci.h 0 = memory, 1 = I/O
9400
 PCI_BASE_ADDRESS_SPACE_IOPCI_BASE_ADDRESS_SPACE_IO 0x01 pci.h 　
9401
 PCI_BASE_ADDRESS_SPACE_MEMORYPCI_BASE_ADDRESS_SPACE_MEMORY 0x00 pci.h 　
9402
 PCI_BASE_ADDRESS_MEM_TYPE_MASKPCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 pci.h 　
9403
 PCI_BASE_ADDRESS_MEM_TYPE_32PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 pci.h 32 bit address
9404
 PCI_BASE_ADDRESS_MEM_TYPE_1MPCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 pci.h Below 1M [obsolete]
9405
 PCI_BASE_ADDRESS_MEM_TYPE_64PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 pci.h 64 bit address
9406
 PCI_BASE_ADDRESS_MEM_MASKPCI_BASE_ADDRESS_MEM_MASK (~0x0f) pci.h 　
9407
 PCI_BASE_ADDRESS_IO_MASKPCI_BASE_ADDRESS_IO_MASK (~0x03) pci.h 　
9408
 PCI_ROM_ADDRESSPCI_ROM_ADDRESS 0x30 pci.h 32 bits
9409
 PCI_ROM_ADDRESS_ENABLEPCI_ROM_ADDRESS_ENABLE 0x01 pci.h Write 1 to enable ROM,
9410
 PCI_CAPABILITY_LISTPCI_CAPABILITY_LIST 0x34 pci.h Offset of first capability list entry
9411
 PCI_INTERRUPT_LINEPCI_INTERRUPT_LINE 0x3c pci.h IRQ number (0-15)
9412
 PCI_INTERRUPT_PINPCI_INTERRUPT_PIN 0x3d pci.h IRQ pin on PCI bus (A-D)
9413
 PCI_PRIMARY_BUSPCI_PRIMARY_BUS 0x18 pci.h Primary bus number
9414
 PCI_SECONDARY_BUSPCI_SECONDARY_BUS 0x19 pci.h Secondary bus number
9415
 PCI_SUBORDINATE_BUSPCI_SUBORDINATE_BUS 0x1a pci.h Highest bus number behind the bridge
9416
 PCI_SEC_LATENCY_TIMERPCI_SEC_LATENCY_TIMER 0x1b pci.h Latency timer for secondary interface
9417
 PCI_IO_BASEPCI_IO_BASE 0x1c pci.h I/O range behind the bridge
9418
 PCI_IO_LIMITPCI_IO_LIMIT 0x1d pci.h 　
9419
 PCI_IO_RANGE_TYPE_MASKPCI_IO_RANGE_TYPE_MASK 0x0f pci.h I/O bridging type
9420
 PCI_IO_RANGE_TYPE_16PCI_IO_RANGE_TYPE_16 0x00 pci.h 　
9421
 PCI_IO_RANGE_TYPE_32PCI_IO_RANGE_TYPE_32 0x01 pci.h 　
9422
 PCI_IO_RANGE_MASKPCI_IO_RANGE_MASK ~0x0f pci.h 　
9423
 PCI_SEC_STATUSPCI_SEC_STATUS 0x1e pci.h Secondary status register, only bit 14 used
9424
 PCI_MEMORY_BASEPCI_MEMORY_BASE 0x20 pci.h Memory range behind
9425
 PCI_MEMORY_LIMITPCI_MEMORY_LIMIT 0x22 pci.h 　
9426
 PCI_MEMORY_RANGE_TYPE_MASKPCI_MEMORY_RANGE_TYPE_MASK 0x0f pci.h 　
9427
 PCI_MEMORY_RANGE_MASKPCI_MEMORY_RANGE_MASK ~0x0f pci.h 　
9428
 PCI_PREF_MEMORY_BASEPCI_PREF_MEMORY_BASE 0x24 pci.h Prefetchable memory range behind
9429
 PCI_PREF_MEMORY_LIMITPCI_PREF_MEMORY_LIMIT 0x26 pci.h 　
9430
 PCI_PREF_RANGE_TYPE_MASKPCI_PREF_RANGE_TYPE_MASK 0x0f pci.h 　
9431
 PCI_PREF_RANGE_TYPE_32PCI_PREF_RANGE_TYPE_32 0x00 pci.h 　
9432
 PCI_PREF_RANGE_TYPE_64PCI_PREF_RANGE_TYPE_64 0x01 pci.h 　
9433
 PCI_PREF_RANGE_MASKPCI_PREF_RANGE_MASK ~0x0f pci.h 　
9434
 PCI_PREF_BASE_UPPER32PCI_PREF_BASE_UPPER32 0x28 pci.h Upper half of prefetchable memory range
9435
 PCI_PREF_LIMIT_UPPER32PCI_PREF_LIMIT_UPPER32 0x2c pci.h 　
9436
 PCI_IO_BASE_UPPER16PCI_IO_BASE_UPPER16 0x30 pci.h Upper half of I/O addresses
9437
 PCI_IO_LIMIT_UPPER16PCI_IO_LIMIT_UPPER16 0x32 pci.h 　
9438
 PCI_ROM_ADDRESS1PCI_ROM_ADDRESS1 0x38 pci.h Same as PCI_ROM_ADDRESS, but for htype 1
9439
 PCI_BRIDGE_CONTROLPCI_BRIDGE_CONTROL 0x3e pci.h 　
9440
 PCI_BRIDGE_CTL_PARITYPCI_BRIDGE_CTL_PARITY 0x01 pci.h Enable parity detection on secondary interface
9441
 PCI_BRIDGE_CTL_SERRPCI_BRIDGE_CTL_SERR 0x02 pci.h The same for SERR forwarding
9442
 PCI_BRIDGE_CTL_NO_ISAPCI_BRIDGE_CTL_NO_ISA 0x04 pci.h Disable bridging of ISA ports
9443
 PCI_BRIDGE_CTL_VGAPCI_BRIDGE_CTL_VGA 0x08 pci.h Forward VGA addresses
9444
 PCI_BRIDGE_CTL_MASTER_ABORTPCI_BRIDGE_CTL_MASTER_ABORT 0x20 pci.h Report master aborts
9445
 PCI_BRIDGE_CTL_BUS_RESETPCI_BRIDGE_CTL_BUS_RESET 0x40 pci.h Secondary bus reset
9446
 PCI_BRIDGE_CTL_FAST_BACKPCI_BRIDGE_CTL_FAST_BACK 0x80 pci.h Fast Back2Back enabled on secondary interface
9447
 PCI_CB_CAPABILITY_LISTPCI_CB_CAPABILITY_LIST 0x14 pci.h 　
9448
 PCI_CAP_LIST_IDPCI_CAP_LIST_ID 0 pci.h Capability ID
9449
 PCI_CAP_ID_PMPCI_CAP_ID_PM 0x01 pci.h Power Management
9450
 PCI_CAP_ID_AGPPCI_CAP_ID_AGP 0x02 pci.h Accelerated Graphics Port
9451
 PCI_CAP_ID_VPDPCI_CAP_ID_VPD 0x03 pci.h Vital Product Data
9452
 PCI_CAP_ID_SLOTIDPCI_CAP_ID_SLOTID 0x04 pci.h Slot Identification
9453
 PCI_CAP_ID_MSIPCI_CAP_ID_MSI 0x05 pci.h Message Signalled Interrupts
9454
 PCI_CAP_ID_CHSWPPCI_CAP_ID_CHSWP 0x06 pci.h CompactPCI HotSwap
9455
 PCI_CAP_ID_EXPPCI_CAP_ID_EXP 0x10 pci.h PCI Express
9456
 PCI_CAP_LIST_NEXTPCI_CAP_LIST_NEXT 1 pci.h Next capability in the list
9457
 PCI_CAP_FLAGSPCI_CAP_FLAGS 2 pci.h Capability defined flags (16 bits)
9458
 PCI_CAP_SIZEOFPCI_CAP_SIZEOF 4 pci.h 　
9459
 PCI_PM_PMCPCI_PM_PMC 2 pci.h PM Capabilities Register
9460
 PCI_PM_CAP_VER_MASKPCI_PM_CAP_VER_MASK 0x0007 pci.h Version
9461
 PCI_PM_CAP_PME_CLOCKPCI_PM_CAP_PME_CLOCK 0x0008 pci.h PME clock required
9462
 PCI_PM_CAP_RESERVEDPCI_PM_CAP_RESERVED 0x0010 pci.h Reserved field
9463
 PCI_PM_CAP_DSIPCI_PM_CAP_DSI 0x0020 pci.h Device specific initialization
9464
 PCI_PM_CAP_AUX_POWERPCI_PM_CAP_AUX_POWER 0x01C0 pci.h Auxilliary power support mask
9465
 PCI_PM_CAP_D1PCI_PM_CAP_D1 0x0200 pci.h D1 power state support
9466
 PCI_PM_CAP_D2PCI_PM_CAP_D2 0x0400 pci.h D2 power state support
9467
 PCI_PM_CAP_PMEPCI_PM_CAP_PME 0x0800 pci.h PME pin supported
9468
 PCI_PM_CAP_PME_MASKPCI_PM_CAP_PME_MASK 0xF800 pci.h PME Mask of all supported states
9469
 PCI_PM_CAP_PME_D0PCI_PM_CAP_PME_D0 0x0800 pci.h PME# from D0
9470
 PCI_PM_CAP_PME_D1PCI_PM_CAP_PME_D1 0x1000 pci.h PME# from D1
9471
 PCI_PM_CAP_PME_D2PCI_PM_CAP_PME_D2 0x2000 pci.h PME# from D2
9472
 PCI_PM_CAP_PME_D3PCI_PM_CAP_PME_D3 0x4000 pci.h PME# from D3 (hot)
9473
 PCI_PM_CAP_PME_D3coldPCI_PM_CAP_PME_D3cold 0x8000 pci.h PME# from D3 (cold)
9474
 PCI_PM_CTRLPCI_PM_CTRL 4 pci.h PM control and status register
9475
 PCI_PM_CTRL_STATE_MASKPCI_PM_CTRL_STATE_MASK 0x0003 pci.h Current power state (D0 to D3)
9476
 PCI_PM_CTRL_PME_ENABLEPCI_PM_CTRL_PME_ENABLE 0x0100 pci.h PME pin enable
9477
 PCI_PM_CTRL_DATA_SEL_MASKPCI_PM_CTRL_DATA_SEL_MASK 0x1e00 pci.h Data select (??)
9478
 PCI_PM_CTRL_DATA_SCALE_MASKPCI_PM_CTRL_DATA_SCALE_MASK 0x6000 pci.h Data scale (??)
9479
 PCI_PM_CTRL_PME_STATUSPCI_PM_CTRL_PME_STATUS 0x8000 pci.h PME pin status
9480
 PCI_PM_PPB_EXTENSIONSPCI_PM_PPB_EXTENSIONS 6 pci.h PPB support extensions (??)
9481
 PCI_PM_PPB_B2_B3PCI_PM_PPB_B2_B3 0x40 pci.h Stop clock when in D3hot (??)
9482
 PCI_PM_BPCC_ENABLEPCI_PM_BPCC_ENABLE 0x80 pci.h Bus power/clock control enable (??)
9483
 PCI_PM_DATA_REGISTERPCI_PM_DATA_REGISTER 7 pci.h (??)
9484
 PCI_PM_SIZEOFPCI_PM_SIZEOF 8 pci.h 　
9485
 PCI_AGP_VERSIONPCI_AGP_VERSION 2 pci.h BCD version number
9486
 PCI_AGP_RFUPCI_AGP_RFU 3 pci.h Rest of capability flags
9487
 PCI_AGP_STATUSPCI_AGP_STATUS 4 pci.h Status register
9488
 PCI_AGP_STATUS_RQ_MASKPCI_AGP_STATUS_RQ_MASK 0xff000000 pci.h Maximum number of requests - 1
9489
 PCI_AGP_STATUS_SBAPCI_AGP_STATUS_SBA 0x0200 pci.h Sideband addressing supported
9490
 PCI_AGP_STATUS_64BITPCI_AGP_STATUS_64BIT 0x0020 pci.h 64-bit addressing supported
9491
 PCI_AGP_STATUS_FWPCI_AGP_STATUS_FW 0x0010 pci.h FW transfers supported
9492
 PCI_AGP_STATUS_RATE4PCI_AGP_STATUS_RATE4 0x0004 pci.h 4x transfer rate supported
9493
 PCI_AGP_STATUS_RATE2PCI_AGP_STATUS_RATE2 0x0002 pci.h 2x transfer rate supported
9494
 PCI_AGP_STATUS_RATE1PCI_AGP_STATUS_RATE1 0x0001 pci.h 1x transfer rate supported
9495
 PCI_AGP_COMMANDPCI_AGP_COMMAND 8 pci.h Control register
9496
 PCI_AGP_COMMAND_RQ_MASKPCI_AGP_COMMAND_RQ_MASK 0xff000000 pci.h Master: Maximum number of requests
9497
 PCI_AGP_COMMAND_SBAPCI_AGP_COMMAND_SBA 0x0200 pci.h Sideband addressing enabled
9498
 PCI_AGP_COMMAND_AGPPCI_AGP_COMMAND_AGP 0x0100 pci.h Allow processing of AGP transactions
9499
 PCI_AGP_COMMAND_64BITPCI_AGP_COMMAND_64BIT 0x0020 pci.h Allow processing of 64-bit addresses
9500
 PCI_AGP_COMMAND_FWPCI_AGP_COMMAND_FW 0x0010 pci.h Force FW transfers
9501
 PCI_AGP_COMMAND_RATE4PCI_AGP_COMMAND_RATE4 0x0004 pci.h Use 4x rate
9502
 PCI_AGP_COMMAND_RATE2PCI_AGP_COMMAND_RATE2 0x0002 pci.h Use 2x rate
9503
 PCI_AGP_COMMAND_RATE1PCI_AGP_COMMAND_RATE1 0x0001 pci.h Use 1x rate
9504
 PCI_AGP_SIZEOFPCI_AGP_SIZEOF 12 pci.h 　
9505
 PCI_SID_ESRPCI_SID_ESR 2 pci.h Expansion Slot Register
9506
 PCI_SID_ESR_NSLOTSPCI_SID_ESR_NSLOTS 0x1f pci.h Number of expansion slots available
9507
 PCI_SID_ESR_FICPCI_SID_ESR_FIC 0x20 pci.h First In Chassis Flag
9508
 PCI_SID_CHASSIS_NRPCI_SID_CHASSIS_NR 3 pci.h Chassis Number
9509
 PCI_MSI_FLAGSPCI_MSI_FLAGS 2 pci.h Various flags
9510
 PCI_MSI_FLAGS_64BITPCI_MSI_FLAGS_64BIT 0x80 pci.h 64-bit addresses allowed
9511
 PCI_MSI_FLAGS_QSIZEPCI_MSI_FLAGS_QSIZE 0x70 pci.h Message queue size configured
9512
 PCI_MSI_FLAGS_QMASKPCI_MSI_FLAGS_QMASK 0x0e pci.h Maximum queue size available
9513
 PCI_MSI_FLAGS_ENABLEPCI_MSI_FLAGS_ENABLE 0x01 pci.h MSI feature enabled
9514
 PCI_MSI_RFUPCI_MSI_RFU 3 pci.h Rest of capability flags
9515
 PCI_MSI_ADDRESS_LOPCI_MSI_ADDRESS_LO 4 pci.h Lower 32 bits
9516
 PCI_MSI_ADDRESS_HIPCI_MSI_ADDRESS_HI 8 pci.h Upper 32 bits (if PCI_MSI_FLAGS_64BIT set)
9517
 PCI_MSI_DATA_32PCI_MSI_DATA_32 8 pci.h 16 bits of data for 32-bit devices
9518
 PCI_MSI_DATA_64PCI_MSI_DATA_64 12 pci.h 16 bits of data for 64-bit devices
9519
 PCI_ERR_UNCOR_STATUSPCI_ERR_UNCOR_STATUS 4 pci.h Uncorrectable Error Status
9520
 PCI_ERR_UNC_TRAINPCI_ERR_UNC_TRAIN 0x00000001 pci.h Training
9521
 PCI_ERR_UNC_DLPPCI_ERR_UNC_DLP 0x00000010 pci.h Data Link Protocol
9522
 PCI_ERR_UNC_POISON_TLPPCI_ERR_UNC_POISON_TLP 0x00001000 pci.h Poisoned TLP
9523
 PCI_ERR_UNC_FCPPCI_ERR_UNC_FCP 0x00002000 pci.h Flow Control Protocol
9524
 PCI_ERR_UNC_COMP_TIMEPCI_ERR_UNC_COMP_TIME 0x00004000 pci.h Completion Timeout
9525
 PCI_ERR_UNC_COMP_ABORTPCI_ERR_UNC_COMP_ABORT 0x00008000 pci.h Completer Abort
9526
 PCI_ERR_UNC_UNX_COMPPCI_ERR_UNC_UNX_COMP 0x00010000 pci.h Unexpected Completion
9527
 PCI_ERR_UNC_RX_OVERPCI_ERR_UNC_RX_OVER 0x00020000 pci.h Receiver Overflow
9528
 PCI_ERR_UNC_MALF_TLPPCI_ERR_UNC_MALF_TLP 0x00040000 pci.h Malformed TLP
9529
 PCI_ERR_UNC_ECRCPCI_ERR_UNC_ECRC 0x00080000 pci.h ECRC Error Status
9530
 PCI_ERR_UNC_UNSUPPCI_ERR_UNC_UNSUP 0x00100000 pci.h Unsupported Request
9531
 PCI_ERR_UNCOR_MASKPCI_ERR_UNCOR_MASK 8 pci.h Uncorrectable Error Mask
9532
 PCI_ERR_UNCOR_SEVERPCI_ERR_UNCOR_SEVER 12 pci.h Uncorrectable Error Severity
9533
 PCI_ERR_COR_STATUSPCI_ERR_COR_STATUS 16 pci.h Correctable Error Status
9534
 PCI_ERR_COR_RCVRPCI_ERR_COR_RCVR 0x00000001 pci.h Receiver Error Status
9535
 PCI_ERR_COR_BAD_TLPPCI_ERR_COR_BAD_TLP 0x00000040 pci.h Bad TLP Status
9536
 PCI_ERR_COR_BAD_DLLPPCI_ERR_COR_BAD_DLLP 0x00000080 pci.h Bad DLLP Status
9537
 PCI_ERR_COR_REP_ROLLPCI_ERR_COR_REP_ROLL 0x00000100 pci.h REPLAY_NUM Rollover
9538
 PCI_ERR_COR_REP_TIMERPCI_ERR_COR_REP_TIMER 0x00001000 pci.h Replay Timer Timeout
9539
 PCI_ERR_COR_MASKPCI_ERR_COR_MASK 20 pci.h Correctable Error Mask
9540
 PCI_ANY_IDPCI_ANY_ID 0xffff pci.h 　
9541
 PCI_DRIVERSPCI_DRIVERS __table ( struct pci_driver, "pci_drivers" ) pci.h 　
9542
 __pci_driver__pci_driver __table_entry ( PCI_DRIVERS, 01 ) pci.h 　
9543
 PCI_CONFIG_BACKUP_EXCLUDE_ENDPCI_CONFIG_BACKUP_EXCLUDE_END 0xff pcibackup.h 　
9544
 PCI_CLASS_NOT_DEFINEDPCI_CLASS_NOT_DEFINED 0x0000 pci_ids.h 　
9545
 PCI_CLASS_NOT_DEFINED_VGAPCI_CLASS_NOT_DEFINED_VGA 0x0001 pci_ids.h 　
9546
 PCI_BASE_CLASS_STORAGEPCI_BASE_CLASS_STORAGE 0x01 pci_ids.h 　
9547
 PCI_CLASS_STORAGE_SCSIPCI_CLASS_STORAGE_SCSI 0x0100 pci_ids.h 　
9548
 PCI_CLASS_STORAGE_IDEPCI_CLASS_STORAGE_IDE 0x0101 pci_ids.h 　
9549
 PCI_CLASS_STORAGE_FLOPPYPCI_CLASS_STORAGE_FLOPPY 0x0102 pci_ids.h 　
9550
 PCI_CLASS_STORAGE_IPIPCI_CLASS_STORAGE_IPI 0x0103 pci_ids.h 　
9551
 PCI_CLASS_STORAGE_RAIDPCI_CLASS_STORAGE_RAID 0x0104 pci_ids.h 　
9552
 PCI_CLASS_STORAGE_OTHERPCI_CLASS_STORAGE_OTHER 0x0180 pci_ids.h 　
9553
 PCI_BASE_CLASS_NETWORKPCI_BASE_CLASS_NETWORK 0x02 pci_ids.h 　
9554
 PCI_CLASS_NETWORK_ETHERNETPCI_CLASS_NETWORK_ETHERNET 0x0200 pci_ids.h 　
9555
 PCI_CLASS_NETWORK_TOKEN_RINGPCI_CLASS_NETWORK_TOKEN_RING 0x0201 pci_ids.h 　
9556
 PCI_CLASS_NETWORK_FDDIPCI_CLASS_NETWORK_FDDI 0x0202 pci_ids.h 　
9557
 PCI_CLASS_NETWORK_ATMPCI_CLASS_NETWORK_ATM 0x0203 pci_ids.h 　
9558
 PCI_CLASS_NETWORK_OTHERPCI_CLASS_NETWORK_OTHER 0x0280 pci_ids.h 　
9559
 PCI_BASE_CLASS_DISPLAYPCI_BASE_CLASS_DISPLAY 0x03 pci_ids.h 　
9560
 PCI_CLASS_DISPLAY_VGAPCI_CLASS_DISPLAY_VGA 0x0300 pci_ids.h 　
9561
 PCI_CLASS_DISPLAY_XGAPCI_CLASS_DISPLAY_XGA 0x0301 pci_ids.h 　
9562
 PCI_CLASS_DISPLAY_3DPCI_CLASS_DISPLAY_3D 0x0302 pci_ids.h 　
9563
 PCI_CLASS_DISPLAY_OTHERPCI_CLASS_DISPLAY_OTHER 0x0380 pci_ids.h 　
9564
 PCI_BASE_CLASS_MULTIMEDIAPCI_BASE_CLASS_MULTIMEDIA 0x04 pci_ids.h 　
9565
 PCI_CLASS_MULTIMEDIA_VIDEOPCI_CLASS_MULTIMEDIA_VIDEO 0x0400 pci_ids.h 　
9566
 PCI_CLASS_MULTIMEDIA_AUDIOPCI_CLASS_MULTIMEDIA_AUDIO 0x0401 pci_ids.h 　
9567
 PCI_CLASS_MULTIMEDIA_PHONEPCI_CLASS_MULTIMEDIA_PHONE 0x0402 pci_ids.h 　
9568
 PCI_CLASS_MULTIMEDIA_OTHERPCI_CLASS_MULTIMEDIA_OTHER 0x0480 pci_ids.h 　
9569
 PCI_BASE_CLASS_MEMORYPCI_BASE_CLASS_MEMORY 0x05 pci_ids.h 　
9570
 PCI_CLASS_MEMORY_RAMPCI_CLASS_MEMORY_RAM 0x0500 pci_ids.h 　
9571
 PCI_CLASS_MEMORY_FLASHPCI_CLASS_MEMORY_FLASH 0x0501 pci_ids.h 　
9572
 PCI_CLASS_MEMORY_OTHERPCI_CLASS_MEMORY_OTHER 0x0580 pci_ids.h 　
9573
 PCI_BASE_CLASS_BRIDGEPCI_BASE_CLASS_BRIDGE 0x06 pci_ids.h 　
9574
 PCI_CLASS_BRIDGE_HOSTPCI_CLASS_BRIDGE_HOST 0x0600 pci_ids.h 　
9575
 PCI_CLASS_BRIDGE_ISAPCI_CLASS_BRIDGE_ISA 0x0601 pci_ids.h 　
9576
 PCI_CLASS_BRIDGE_EISAPCI_CLASS_BRIDGE_EISA 0x0602 pci_ids.h 　
9577
 PCI_CLASS_BRIDGE_MCPCI_CLASS_BRIDGE_MC 0x0603 pci_ids.h 　
9578
 PCI_CLASS_BRIDGE_PCIPCI_CLASS_BRIDGE_PCI 0x0604 pci_ids.h 　
9579
 PCI_CLASS_BRIDGE_PCMCIAPCI_CLASS_BRIDGE_PCMCIA 0x0605 pci_ids.h 　
9580
 PCI_CLASS_BRIDGE_NUBUSPCI_CLASS_BRIDGE_NUBUS 0x0606 pci_ids.h 　
9581
 PCI_CLASS_BRIDGE_CARDBUSPCI_CLASS_BRIDGE_CARDBUS 0x0607 pci_ids.h 　
9582
 PCI_CLASS_BRIDGE_RACEWAYPCI_CLASS_BRIDGE_RACEWAY 0x0608 pci_ids.h 　
9583
 PCI_CLASS_BRIDGE_OTHERPCI_CLASS_BRIDGE_OTHER 0x0680 pci_ids.h 　
9584
 PCI_BASE_CLASS_COMMUNICATIONPCI_BASE_CLASS_COMMUNICATION 0x07 pci_ids.h 　
9585
 PCI_CLASS_COMMUNICATION_SERIALPCI_CLASS_COMMUNICATION_SERIAL 0x0700 pci_ids.h 　
9586
 PCI_CLASS_COMMUNICATION_PARALLEPCI_CLASS_COMMUNICATION_PARALLE 0x0701 pci_ids.h 　
9587
 PCI_CLASS_COMMUNICATION_MULTISEPCI_CLASS_COMMUNICATION_MULTISE 0x0702 pci_ids.h 　
9588
 PCI_CLASS_COMMUNICATION_MODEMPCI_CLASS_COMMUNICATION_MODEM 0x0703 pci_ids.h 　
9589
 PCI_CLASS_COMMUNICATION_OTHERPCI_CLASS_COMMUNICATION_OTHER 0x0780 pci_ids.h 　
9590
 PCI_BASE_CLASS_SYSTEMPCI_BASE_CLASS_SYSTEM 0x08 pci_ids.h 　
9591
 PCI_CLASS_SYSTEM_PICPCI_CLASS_SYSTEM_PIC 0x0800 pci_ids.h 　
9592
 PCI_CLASS_SYSTEM_DMAPCI_CLASS_SYSTEM_DMA 0x0801 pci_ids.h 　
9593
 PCI_CLASS_SYSTEM_TIMERPCI_CLASS_SYSTEM_TIMER 0x0802 pci_ids.h 　
9594
 PCI_CLASS_SYSTEM_RTCPCI_CLASS_SYSTEM_RTC 0x0803 pci_ids.h 　
9595
 PCI_CLASS_SYSTEM_PCI_HOTPLUGPCI_CLASS_SYSTEM_PCI_HOTPLUG 0x0804 pci_ids.h 　
9596
 PCI_CLASS_SYSTEM_OTHERPCI_CLASS_SYSTEM_OTHER 0x0880 pci_ids.h 　
9597
 PCI_BASE_CLASS_INPUTPCI_BASE_CLASS_INPUT 0x09 pci_ids.h 　
9598
 PCI_CLASS_INPUT_KEYBOARDPCI_CLASS_INPUT_KEYBOARD 0x0900 pci_ids.h 　
9599
 PCI_CLASS_INPUT_PENPCI_CLASS_INPUT_PEN 0x0901 pci_ids.h 　
9600
 PCI_CLASS_INPUT_MOUSEPCI_CLASS_INPUT_MOUSE 0x0902 pci_ids.h 　
9601
 PCI_CLASS_INPUT_SCANNERPCI_CLASS_INPUT_SCANNER 0x0903 pci_ids.h 　
9602
 PCI_CLASS_INPUT_GAMEPORTPCI_CLASS_INPUT_GAMEPORT 0x0904 pci_ids.h 　
9603
 PCI_CLASS_INPUT_OTHERPCI_CLASS_INPUT_OTHER 0x0980 pci_ids.h 　
9604
 PCI_BASE_CLASS_DOCKINGPCI_BASE_CLASS_DOCKING 0x0a pci_ids.h 　
9605
 PCI_CLASS_DOCKING_GENERICPCI_CLASS_DOCKING_GENERIC 0x0a00 pci_ids.h 　
9606
 PCI_CLASS_DOCKING_OTHERPCI_CLASS_DOCKING_OTHER 0x0a80 pci_ids.h 　
9607
 PCI_BASE_CLASS_PROCESSORPCI_BASE_CLASS_PROCESSOR 0x0b pci_ids.h 　
9608
 PCI_CLASS_PROCESSOR_386PCI_CLASS_PROCESSOR_386 0x0b00 pci_ids.h 　
9609
 PCI_CLASS_PROCESSOR_486PCI_CLASS_PROCESSOR_486 0x0b01 pci_ids.h 　
9610
 PCI_CLASS_PROCESSOR_PENTIUMPCI_CLASS_PROCESSOR_PENTIUM 0x0b02 pci_ids.h 　
9611
 PCI_CLASS_PROCESSOR_ALPHAPCI_CLASS_PROCESSOR_ALPHA 0x0b10 pci_ids.h 　
9612
 PCI_CLASS_PROCESSOR_POWERPCPCI_CLASS_PROCESSOR_POWERPC 0x0b20 pci_ids.h 　
9613
 PCI_CLASS_PROCESSOR_MIPSPCI_CLASS_PROCESSOR_MIPS 0x0b30 pci_ids.h 　
9614
 PCI_CLASS_PROCESSOR_COPCI_CLASS_PROCESSOR_CO 0x0b40 pci_ids.h 　
9615
 PCI_BASE_CLASS_SERIALPCI_BASE_CLASS_SERIAL 0x0c pci_ids.h 　
9616
 PCI_CLASS_SERIAL_FIREWIREPCI_CLASS_SERIAL_FIREWIRE 0x0c00 pci_ids.h 　
9617
 PCI_CLASS_SERIAL_ACCESSPCI_CLASS_SERIAL_ACCESS 0x0c01 pci_ids.h 　
9618
 PCI_CLASS_SERIAL_SSAPCI_CLASS_SERIAL_SSA 0x0c02 pci_ids.h 　
9619
 PCI_CLASS_SERIAL_USBPCI_CLASS_SERIAL_USB 0x0c03 pci_ids.h 　
9620
 PCI_CLASS_SERIAL_FIBERPCI_CLASS_SERIAL_FIBER 0x0c04 pci_ids.h 　
9621
 PCI_CLASS_SERIAL_SMBUSPCI_CLASS_SERIAL_SMBUS 0x0c05 pci_ids.h 　
9622
 PCI_BASE_CLASS_INTELLIGENTPCI_BASE_CLASS_INTELLIGENT 0x0e pci_ids.h 　
9623
 PCI_CLASS_INTELLIGENT_I2OPCI_CLASS_INTELLIGENT_I2O 0x0e00 pci_ids.h 　
9624
 PCI_BASE_CLASS_SATELLITEPCI_BASE_CLASS_SATELLITE 0x0f pci_ids.h 　
9625
 PCI_CLASS_SATELLITE_TVPCI_CLASS_SATELLITE_TV 0x0f00 pci_ids.h 　
9626
 PCI_CLASS_SATELLITE_AUDIOPCI_CLASS_SATELLITE_AUDIO 0x0f01 pci_ids.h 　
9627
 PCI_CLASS_SATELLITE_VOICEPCI_CLASS_SATELLITE_VOICE 0x0f03 pci_ids.h 　
9628
 PCI_CLASS_SATELLITE_DATAPCI_CLASS_SATELLITE_DATA 0x0f04 pci_ids.h 　
9629
 PCI_BASE_CLASS_CRYPTPCI_BASE_CLASS_CRYPT 0x10 pci_ids.h 　
9630
 PCI_CLASS_CRYPT_NETWORKPCI_CLASS_CRYPT_NETWORK 0x1000 pci_ids.h 　
9631
 PCI_CLASS_CRYPT_ENTERTAINMENTPCI_CLASS_CRYPT_ENTERTAINMENT 0x1001 pci_ids.h 　
9632
 PCI_CLASS_CRYPT_OTHERPCI_CLASS_CRYPT_OTHER 0x1080 pci_ids.h 　
9633
 PCI_BASE_CLASS_SIGNAL_PROCESSINPCI_BASE_CLASS_SIGNAL_PROCESSIN 0x11 pci_ids.h 　
9634
 PCI_CLASS_SP_DPIOPCI_CLASS_SP_DPIO 0x1100 pci_ids.h 　
9635
 PCI_CLASS_SP_OTHERPCI_CLASS_SP_OTHER 0x1180 pci_ids.h 　
9636
 PCI_CLASS_OTHERSPCI_CLASS_OTHERS 0xff pci_ids.h 　
9637
 PCI_VENDOR_ID_DYNALINKPCI_VENDOR_ID_DYNALINK 0x0675 pci_ids.h 　
9638
 PCI_VENDOR_ID_BERKOMPCI_VENDOR_ID_BERKOM 0x0871 pci_ids.h 　
9639
 PCI_VENDOR_ID_COMPAQPCI_VENDOR_ID_COMPAQ 0x0e11 pci_ids.h 　
9640
 PCI_VENDOR_ID_NCRPCI_VENDOR_ID_NCR 0x1000 pci_ids.h 　
9641
 PCI_VENDOR_ID_LSI_LOGICPCI_VENDOR_ID_LSI_LOGIC 0x1000 pci_ids.h 　
9642
 PCI_VENDOR_ID_ATIPCI_VENDOR_ID_ATI 0x1002 pci_ids.h 　
9643
 PCI_VENDOR_ID_VLSIPCI_VENDOR_ID_VLSI 0x1004 pci_ids.h 　
9644
 PCI_VENDOR_ID_ADLPCI_VENDOR_ID_ADL 0x1005 pci_ids.h 　
9645
 PCI_VENDOR_ID_NSPCI_VENDOR_ID_NS 0x100b pci_ids.h 　
9646
 PCI_VENDOR_ID_TSENGPCI_VENDOR_ID_TSENG 0x100c pci_ids.h 　
9647
 PCI_VENDOR_ID_WEITEKPCI_VENDOR_ID_WEITEK 0x100e pci_ids.h 　
9648
 PCI_VENDOR_ID_DECPCI_VENDOR_ID_DEC 0x1011 pci_ids.h 　
9649
 PCI_VENDOR_ID_CIRRUSPCI_VENDOR_ID_CIRRUS 0x1013 pci_ids.h 　
9650
 PCI_VENDOR_ID_IBMPCI_VENDOR_ID_IBM 0x1014 pci_ids.h 　
9651
 PCI_VENDOR_ID_COMPEX2PCI_VENDOR_ID_COMPEX2 0x101a pci_ids.h 　
9652
 PCI_VENDOR_ID_WDPCI_VENDOR_ID_WD 0x101c pci_ids.h 　
9653
 PCI_VENDOR_ID_AMIPCI_VENDOR_ID_AMI 0x101e pci_ids.h 　
9654
 PCI_VENDOR_ID_AMDPCI_VENDOR_ID_AMD 0x1022 pci_ids.h 　
9655
 PCI_VENDOR_ID_TRIDENTPCI_VENDOR_ID_TRIDENT 0x1023 pci_ids.h 　
9656
 PCI_VENDOR_ID_AIPCI_VENDOR_ID_AI 0x1025 pci_ids.h 　
9657
 PCI_VENDOR_ID_DELLPCI_VENDOR_ID_DELL 0x1028 pci_ids.h 　
9658
 PCI_VENDOR_ID_MATROXPCI_VENDOR_ID_MATROX 0x102B pci_ids.h 　
9659
 PCI_VENDOR_ID_CTPCI_VENDOR_ID_CT 0x102c pci_ids.h 　
9660
 PCI_VENDOR_ID_MIROPCI_VENDOR_ID_MIRO 0x1031 pci_ids.h 　
9661
 PCI_VENDOR_ID_NECPCI_VENDOR_ID_NEC 0x1033 pci_ids.h 　
9662
 PCI_VENDOR_ID_FDPCI_VENDOR_ID_FD 0x1036 pci_ids.h 　
9663
 PCI_VENDOR_ID_SISPCI_VENDOR_ID_SIS 0x1039 pci_ids.h 　
9664
 PCI_VENDOR_ID_SIPCI_VENDOR_ID_SI 0x1039 pci_ids.h 　
9665
 PCI_VENDOR_ID_HPPCI_VENDOR_ID_HP 0x103c pci_ids.h 　
9666
 PCI_VENDOR_ID_PCTECHPCI_VENDOR_ID_PCTECH 0x1042 pci_ids.h 　
9667
 PCI_VENDOR_ID_ASUSTEKPCI_VENDOR_ID_ASUSTEK 0x1043 pci_ids.h 　
9668
 PCI_VENDOR_ID_DPTPCI_VENDOR_ID_DPT 0x1044 pci_ids.h 　
9669
 PCI_VENDOR_ID_OPTIPCI_VENDOR_ID_OPTI 0x1045 pci_ids.h 　
9670
 PCI_VENDOR_ID_ELSAPCI_VENDOR_ID_ELSA 0x1048 pci_ids.h 　
9671
 PCI_VENDOR_ID_ELSAPCI_VENDOR_ID_ELSA 0x1048 pci_ids.h 　
9672
 PCI_VENDOR_ID_SGSPCI_VENDOR_ID_SGS 0x104a pci_ids.h 　
9673
 PCI_VENDOR_ID_BUSLOGICPCI_VENDOR_ID_BUSLOGIC 0x104B pci_ids.h 　
9674
 PCI_VENDOR_ID_TIPCI_VENDOR_ID_TI 0x104c pci_ids.h 　
9675
 PCI_VENDOR_ID_SONYPCI_VENDOR_ID_SONY 0x104d pci_ids.h 　
9676
 PCI_VENDOR_ID_OAKPCI_VENDOR_ID_OAK 0x104e pci_ids.h 　
9677
 PCI_VENDOR_ID_WINBOND2PCI_VENDOR_ID_WINBOND2 0x1050 pci_ids.h 　
9678
 PCI_VENDOR_ID_ANIGMAPCI_VENDOR_ID_ANIGMA 0x1051 pci_ids.h 　
9679
 PCI_VENDOR_ID_EFARPCI_VENDOR_ID_EFAR 0x1055 pci_ids.h 　
9680
 PCI_VENDOR_ID_MOTOROLAPCI_VENDOR_ID_MOTOROLA 0x1057 pci_ids.h 　
9681
 PCI_VENDOR_ID_MOTOROLA_OOPSPCI_VENDOR_ID_MOTOROLA_OOPS 0x1507 pci_ids.h 　
9682
 PCI_VENDOR_ID_PROMISEPCI_VENDOR_ID_PROMISE 0x105a pci_ids.h 　
9683
 PCI_VENDOR_ID_N9PCI_VENDOR_ID_N9 0x105d pci_ids.h 　
9684
 PCI_VENDOR_ID_UMCPCI_VENDOR_ID_UMC 0x1060 pci_ids.h 　
9685
 PCI_VENDOR_ID_XPCI_VENDOR_ID_X 0x1061 pci_ids.h 　
9686
 PCI_VENDOR_ID_MYLEXPCI_VENDOR_ID_MYLEX 0x1069 pci_ids.h 　
9687
 PCI_VENDOR_ID_PICOPPCI_VENDOR_ID_PICOP 0x1066 pci_ids.h 　
9688
 PCI_VENDOR_ID_APPLEPCI_VENDOR_ID_APPLE 0x106b pci_ids.h 　
9689
 PCI_VENDOR_ID_YAMAHAPCI_VENDOR_ID_YAMAHA 0x1073 pci_ids.h 　
9690
 PCI_VENDOR_ID_NEXGENPCI_VENDOR_ID_NEXGEN 0x1074 pci_ids.h 　
9691
 PCI_VENDOR_ID_QLOGICPCI_VENDOR_ID_QLOGIC 0x1077 pci_ids.h 　
9692
 PCI_VENDOR_ID_CYRIXPCI_VENDOR_ID_CYRIX 0x1078 pci_ids.h 　
9693
 PCI_VENDOR_ID_LEADTEKPCI_VENDOR_ID_LEADTEK 0x107d pci_ids.h 　
9694
 PCI_VENDOR_ID_INTERPHASEPCI_VENDOR_ID_INTERPHASE 0x107e pci_ids.h 　
9695
 PCI_VENDOR_ID_CONTAQPCI_VENDOR_ID_CONTAQ 0x1080 pci_ids.h 　
9696
 PCI_VENDOR_ID_FOREXPCI_VENDOR_ID_FOREX 0x1083 pci_ids.h 　
9697
 PCI_VENDOR_ID_OLICOMPCI_VENDOR_ID_OLICOM 0x108d pci_ids.h 　
9698
 PCI_VENDOR_ID_SUNPCI_VENDOR_ID_SUN 0x108e pci_ids.h 　
9699
 PCI_VENDOR_ID_CMDPCI_VENDOR_ID_CMD 0x1095 pci_ids.h 　
9700
 PCI_VENDOR_ID_VISIONPCI_VENDOR_ID_VISION 0x1098 pci_ids.h 　
9701
 PCI_VENDOR_ID_BROOKTREEPCI_VENDOR_ID_BROOKTREE 0x109e pci_ids.h 　
9702
 PCI_VENDOR_ID_SIERRAPCI_VENDOR_ID_SIERRA 0x10a8 pci_ids.h 　
9703
 PCI_VENDOR_ID_SGIPCI_VENDOR_ID_SGI 0x10a9 pci_ids.h 　
9704
 PCI_VENDOR_ID_ACCPCI_VENDOR_ID_ACC 0x10aa pci_ids.h 　
9705
 PCI_VENDOR_ID_WINBONDPCI_VENDOR_ID_WINBOND 0x10ad pci_ids.h 　
9706
 PCI_VENDOR_ID_DATABOOKPCI_VENDOR_ID_DATABOOK 0x10b3 pci_ids.h 　
9707
 PCI_VENDOR_ID_PLXPCI_VENDOR_ID_PLX 0x10b5 pci_ids.h 　
9708
 PCI_VENDOR_ID_MADGEPCI_VENDOR_ID_MADGE 0x10b6 pci_ids.h 　
9709
 PCI_VENDOR_ID_3COMPCI_VENDOR_ID_3COM 0x10b7 pci_ids.h 　
9710
 PCI_VENDOR_ID_SMCPCI_VENDOR_ID_SMC 0x10b8 pci_ids.h 　
9711
 PCI_VENDOR_ID_SUNDANCEPCI_VENDOR_ID_SUNDANCE 0x13F0 pci_ids.h 　
9712
 PCI_VENDOR_ID_ALPCI_VENDOR_ID_AL 0x10b9 pci_ids.h 　
9713
 PCI_VENDOR_ID_MITSUBISHIPCI_VENDOR_ID_MITSUBISHI 0x10ba pci_ids.h 　
9714
 PCI_VENDOR_ID_SURECOMPCI_VENDOR_ID_SURECOM 0x10bd pci_ids.h 　
9715
 PCI_VENDOR_ID_NEOMAGICPCI_VENDOR_ID_NEOMAGIC 0x10c8 pci_ids.h 　
9716
 PCI_VENDOR_ID_ASPPCI_VENDOR_ID_ASP 0x10cd pci_ids.h 　
9717
 PCI_VENDOR_ID_MACRONIXPCI_VENDOR_ID_MACRONIX 0x10d9 pci_ids.h 　
9718
 PCI_VENDOR_ID_TCONRADPCI_VENDOR_ID_TCONRAD 0x10da pci_ids.h 　
9719
 PCI_VENDOR_ID_CERNPCI_VENDOR_ID_CERN 0x10dc pci_ids.h 　
9720
 PCI_VENDOR_ID_NVIDIAPCI_VENDOR_ID_NVIDIA 0x10de pci_ids.h 　
9721
 PCI_VENDOR_ID_IMSPCI_VENDOR_ID_IMS 0x10e0 pci_ids.h 　
9722
 PCI_VENDOR_ID_TEKRAM2PCI_VENDOR_ID_TEKRAM2 0x10e1 pci_ids.h 　
9723
 PCI_VENDOR_ID_TUNDRAPCI_VENDOR_ID_TUNDRA 0x10e3 pci_ids.h 　
9724
 PCI_VENDOR_ID_AMCCPCI_VENDOR_ID_AMCC 0x10e8 pci_ids.h 　
9725
 PCI_VENDOR_ID_INTERGPCI_VENDOR_ID_INTERG 0x10ea pci_ids.h 　
9726
 PCI_VENDOR_ID_REALTEKPCI_VENDOR_ID_REALTEK 0x10ec pci_ids.h 　
9727
 PCI_VENDOR_ID_XILINXPCI_VENDOR_ID_XILINX 0x10ee pci_ids.h 　
9728
 PCI_VENDOR_ID_TRUEVISIONPCI_VENDOR_ID_TRUEVISION 0x10fa pci_ids.h 　
9729
 PCI_VENDOR_ID_INITPCI_VENDOR_ID_INIT 0x1101 pci_ids.h 　
9730
 PCI_VENDOR_ID_CREATIVEPCI_VENDOR_ID_CREATIVE 0x1102 pci_ids.h 　
9731
 PCI_VENDOR_ID_ECTIVAPCI_VENDOR_ID_ECTIVA 0x1102 pci_ids.h 　
9732
 PCI_VENDOR_ID_TTIPCI_VENDOR_ID_TTI 0x1103 pci_ids.h 　
9733
 PCI_VENDOR_ID_VIAPCI_VENDOR_ID_VIA 0x1106 pci_ids.h 　
9734
 PCI_VENDOR_ID_VIATECPCI_VENDOR_ID_VIATEC 0x1106 pci_ids.h 　
9735
 PCI_VENDOR_ID_SIEMENSPCI_VENDOR_ID_SIEMENS 0x110A pci_ids.h 　
9736
 PCI_VENDOR_ID_SMC2PCI_VENDOR_ID_SMC2 0x1113 pci_ids.h 　
9737
 PCI_VENDOR_ID_VORTEXPCI_VENDOR_ID_VORTEX 0x1119 pci_ids.h 　
9738
 PCI_VENDOR_ID_EFPCI_VENDOR_ID_EF 0x111a pci_ids.h 　
9739
 PCI_VENDOR_ID_IDTPCI_VENDOR_ID_IDT 0x111d pci_ids.h 　
9740
 PCI_VENDOR_ID_FOREPCI_VENDOR_ID_FORE 0x1127 pci_ids.h 　
9741
 PCI_VENDOR_ID_IMAGINGTECHPCI_VENDOR_ID_IMAGINGTECH 0x112f pci_ids.h 　
9742
 PCI_VENDOR_ID_PHILIPSPCI_VENDOR_ID_PHILIPS 0x1131 pci_ids.h 　
9743
 PCI_VENDOR_ID_EICONPCI_VENDOR_ID_EICON 0x1133 pci_ids.h 　
9744
 PCI_VENDOR_ID_CYCLONEPCI_VENDOR_ID_CYCLONE 0x113c pci_ids.h 　
9745
 PCI_VENDOR_ID_ALLIANCEPCI_VENDOR_ID_ALLIANCE 0x1142 pci_ids.h 　
9746
 PCI_VENDOR_ID_SYSKONNECTPCI_VENDOR_ID_SYSKONNECT 0x1148 pci_ids.h 　
9747
 PCI_VENDOR_ID_VMICPCI_VENDOR_ID_VMIC 0x114a pci_ids.h 　
9748
 PCI_VENDOR_ID_DIGIPCI_VENDOR_ID_DIGI 0x114f pci_ids.h 　
9749
 PCI_VENDOR_ID_MUTECHPCI_VENDOR_ID_MUTECH 0x1159 pci_ids.h 　
9750
 PCI_VENDOR_ID_XIRCOMPCI_VENDOR_ID_XIRCOM 0x115d pci_ids.h 　
9751
 PCI_VENDOR_ID_RENDITIONPCI_VENDOR_ID_RENDITION 0x1163 pci_ids.h 　
9752
 PCI_VENDOR_ID_SERVERWORKSPCI_VENDOR_ID_SERVERWORKS 0x1166 pci_ids.h 　
9753
 PCI_VENDOR_ID_SBEPCI_VENDOR_ID_SBE 0x1176 pci_ids.h 　
9754
 PCI_VENDOR_ID_TOSHIBAPCI_VENDOR_ID_TOSHIBA 0x1179 pci_ids.h 　
9755
 PCI_VENDOR_ID_RICOHPCI_VENDOR_ID_RICOH 0x1180 pci_ids.h 　
9756
 PCI_VENDOR_ID_DLINKPCI_VENDOR_ID_DLINK 0x1186 pci_ids.h 　
9757
 PCI_VENDOR_ID_ARTOPPCI_VENDOR_ID_ARTOP 0x1191 pci_ids.h 　
9758
 PCI_VENDOR_ID_ZEITNETPCI_VENDOR_ID_ZEITNET 0x1193 pci_ids.h 　
9759
 PCI_VENDOR_ID_OMEGAPCI_VENDOR_ID_OMEGA 0x119b pci_ids.h 　
9760
 PCI_VENDOR_ID_FUJITSU_MEPCI_VENDOR_ID_FUJITSU_ME 0x119e pci_ids.h 　
9761
 PCI_SUBVENDOR_ID_KEYSPANPCI_SUBVENDOR_ID_KEYSPAN 0x11a9 pci_ids.h 　
9762
 PCI_VENDOR_ID_GALILEOPCI_VENDOR_ID_GALILEO 0x11ab pci_ids.h 　
9763
 PCI_VENDOR_ID_LINKSYSPCI_VENDOR_ID_LINKSYS 0x11ad pci_ids.h 　
9764
 PCI_VENDOR_ID_LITEONPCI_VENDOR_ID_LITEON 0x11ad pci_ids.h 　
9765
 PCI_VENDOR_ID_V3PCI_VENDOR_ID_V3 0x11b0 pci_ids.h 　
9766
 PCI_VENDOR_ID_NPPCI_VENDOR_ID_NP 0x11bc pci_ids.h 　
9767
 PCI_VENDOR_ID_ATTPCI_VENDOR_ID_ATT 0x11c1 pci_ids.h 　
9768
 PCI_VENDOR_ID_SPECIALIXPCI_VENDOR_ID_SPECIALIX 0x11cb pci_ids.h 　
9769
 PCI_VENDOR_ID_AURAVISIONPCI_VENDOR_ID_AURAVISION 0x11d1 pci_ids.h 　
9770
 PCI_VENDOR_ID_ANALOG_DEVICESPCI_VENDOR_ID_ANALOG_DEVICES 0x11d4 pci_ids.h 　
9771
 PCI_VENDOR_ID_IKONPCI_VENDOR_ID_IKON 0x11d5 pci_ids.h 　
9772
 PCI_VENDOR_ID_ZORANPCI_VENDOR_ID_ZORAN 0x11de pci_ids.h 　
9773
 PCI_VENDOR_ID_KINETICPCI_VENDOR_ID_KINETIC 0x11f4 pci_ids.h 　
9774
 PCI_VENDOR_ID_COMPEXPCI_VENDOR_ID_COMPEX 0x11f6 pci_ids.h 　
9775
 PCI_VENDOR_ID_RPPCI_VENDOR_ID_RP 0x11fe pci_ids.h 　
9776
 PCI_VENDOR_ID_CYCLADESPCI_VENDOR_ID_CYCLADES 0x120e pci_ids.h 　
9777
 PCI_VENDOR_ID_ESSENTIALPCI_VENDOR_ID_ESSENTIAL 0x120f pci_ids.h 　
9778
 PCI_VENDOR_ID_O2PCI_VENDOR_ID_O2 0x1217 pci_ids.h 　
9779
 PCI_VENDOR_ID_3DFXPCI_VENDOR_ID_3DFX 0x121a pci_ids.h 　
9780
 PCI_VENDOR_ID_SIGMADESPCI_VENDOR_ID_SIGMADES 0x1236 pci_ids.h 　
9781
 PCI_VENDOR_ID_CCUBEPCI_VENDOR_ID_CCUBE 0x123f pci_ids.h 　
9782
 PCI_VENDOR_ID_AVMPCI_VENDOR_ID_AVM 0x1244 pci_ids.h 　
9783
 PCI_VENDOR_ID_DIPIXPCI_VENDOR_ID_DIPIX 0x1246 pci_ids.h 　
9784
 PCI_VENDOR_ID_STALLIONPCI_VENDOR_ID_STALLION 0x124d pci_ids.h 　
9785
 PCI_VENDOR_ID_OPTIBASEPCI_VENDOR_ID_OPTIBASE 0x1255 pci_ids.h 　
9786
 PCI_VENDOR_ID_ESSPCI_VENDOR_ID_ESS 0x125d pci_ids.h 　
9787
 PCI_VENDOR_ID_HARRISPCI_VENDOR_ID_HARRIS 0x1260 pci_ids.h 　
9788
 PCI_VENDOR_ID_SATSAGEMPCI_VENDOR_ID_SATSAGEM 0x1267 pci_ids.h 　
9789
 PCI_VENDOR_ID_HUGHESPCI_VENDOR_ID_HUGHES 0x1273 pci_ids.h 　
9790
 PCI_VENDOR_ID_ENSONIQPCI_VENDOR_ID_ENSONIQ 0x1274 pci_ids.h 　
9791
 PCI_VENDOR_ID_ROCKWELLPCI_VENDOR_ID_ROCKWELL 0x127A pci_ids.h 　
9792
 PCI_VENDOR_ID_DAVICOMPCI_VENDOR_ID_DAVICOM 0x1282 pci_ids.h 　
9793
 PCI_VENDOR_ID_ITEPCI_VENDOR_ID_ITE 0x1283 pci_ids.h 　
9794
 PCI_VENDOR_ID_ESS_OLDPCI_VENDOR_ID_ESS_OLD 0x1285 pci_ids.h 　
9795
 PCI_VENDOR_ID_ALTEONPCI_VENDOR_ID_ALTEON 0x12ae pci_ids.h 　
9796
 PCI_VENDOR_ID_USRPCI_VENDOR_ID_USR 0x12B9 pci_ids.h 　
9797
 PCI_VENDOR_ID_HOLTEKPCI_VENDOR_ID_HOLTEK 0x12c3 pci_ids.h 　
9798
 PCI_SUBVENDOR_ID_CONNECT_TECHPCI_SUBVENDOR_ID_CONNECT_TECH 0x12c4 pci_ids.h 　
9799
 PCI_VENDOR_ID_PICTURELPCI_VENDOR_ID_PICTUREL 0x12c5 pci_ids.h 　
9800
 PCI_VENDOR_ID_NVIDIA_SGSPCI_VENDOR_ID_NVIDIA_SGS 0x12d2 pci_ids.h 　
9801
 PCI_SUBVENDOR_ID_CHASE_PCIFASTPCI_SUBVENDOR_ID_CHASE_PCIFAST 0x12E0 pci_ids.h 　
9802
 PCI_SUBVENDOR_ID_CHASE_PCIRASPCI_SUBVENDOR_ID_CHASE_PCIRAS 0x124D pci_ids.h 　
9803
 PCI_VENDOR_ID_AUREALPCI_VENDOR_ID_AUREAL 0x12eb pci_ids.h 　
9804
 PCI_VENDOR_ID_CBOARDSPCI_VENDOR_ID_CBOARDS 0x1307 pci_ids.h 　
9805
 PCI_VENDOR_ID_SIIGPCI_VENDOR_ID_SIIG 0x131f pci_ids.h 　
9806
 PCI_VENDOR_ID_ADMTEKPCI_VENDOR_ID_ADMTEK 0x1317 pci_ids.h 　
9807
 PCI_VENDOR_ID_DOMEXPCI_VENDOR_ID_DOMEX 0x134a pci_ids.h 　
9808
 PCI_VENDOR_ID_QUATECHPCI_VENDOR_ID_QUATECH 0x135C pci_ids.h 　
9809
 PCI_VENDOR_ID_SEALEVELPCI_VENDOR_ID_SEALEVEL 0x135e pci_ids.h 　
9810
 PCI_VENDOR_ID_HYPERCOPEPCI_VENDOR_ID_HYPERCOPE 0x1365 pci_ids.h 　
9811
 PCI_VENDOR_ID_KAWASAKIPCI_VENDOR_ID_KAWASAKI 0x136b pci_ids.h 　
9812
 PCI_VENDOR_ID_LMCPCI_VENDOR_ID_LMC 0x1376 pci_ids.h 　
9813
 PCI_VENDOR_ID_NETGEARPCI_VENDOR_ID_NETGEAR 0x1385 pci_ids.h 　
9814
 PCI_VENDOR_ID_APPLICOMPCI_VENDOR_ID_APPLICOM 0x1389 pci_ids.h 　
9815
 PCI_VENDOR_ID_MOXAPCI_VENDOR_ID_MOXA 0x1393 pci_ids.h 　
9816
 PCI_VENDOR_ID_CCDPCI_VENDOR_ID_CCD 0x1397 pci_ids.h 　
9817
 PCI_VENDOR_ID_MICROGATEPCI_VENDOR_ID_MICROGATE 0x13c0 pci_ids.h 　
9818
 PCI_VENDOR_ID_3WAREPCI_VENDOR_ID_3WARE 0x13C1 pci_ids.h 　
9819
 PCI_VENDOR_ID_ABOCOMPCI_VENDOR_ID_ABOCOM 0x13D1 pci_ids.h 　
9820
 PCI_VENDOR_ID_CMEDIAPCI_VENDOR_ID_CMEDIA 0x13f6 pci_ids.h 　
9821
 PCI_VENDOR_ID_LAVAPCI_VENDOR_ID_LAVA 0x1407 pci_ids.h 　
9822
 PCI_VENDOR_ID_TIMEDIAPCI_VENDOR_ID_TIMEDIA 0x1409 pci_ids.h 　
9823
 PCI_VENDOR_ID_OXSEMIPCI_VENDOR_ID_OXSEMI 0x1415 pci_ids.h 　
9824
 PCI_VENDOR_ID_AIRONETPCI_VENDOR_ID_AIRONET 0x14b9 pci_ids.h 　
9825
 PCI_VENDOR_ID_MYRICOMPCI_VENDOR_ID_MYRICOM 0x14c1 pci_ids.h 　
9826
 PCI_VENDOR_ID_TITANPCI_VENDOR_ID_TITAN 0x14D2 pci_ids.h 　
9827
 PCI_VENDOR_ID_PANACOMPCI_VENDOR_ID_PANACOM 0x14d4 pci_ids.h 　
9828
 PCI_VENDOR_ID_BROADCOMPCI_VENDOR_ID_BROADCOM 0x14e4 pci_ids.h 　
9829
 PCI_VENDOR_ID_SYBAPCI_VENDOR_ID_SYBA 0x1592 pci_ids.h 　
9830
 PCI_VENDOR_ID_MORETONPCI_VENDOR_ID_MORETON 0x15aa pci_ids.h 　
9831
 PCI_VENDOR_ID_ZOLTRIXPCI_VENDOR_ID_ZOLTRIX 0x15b0 pci_ids.h 　
9832
 PCI_VENDOR_ID_PDCPCI_VENDOR_ID_PDC 0x15e9 pci_ids.h 　
9833
 PCI_VENDOR_ID_FSCPCI_VENDOR_ID_FSC 0x1734 pci_ids.h 　
9834
 PCI_VENDOR_ID_SYMPHONYPCI_VENDOR_ID_SYMPHONY 0x1c1c pci_ids.h 　
9835
 PCI_VENDOR_ID_TEKRAMPCI_VENDOR_ID_TEKRAM 0x1de1 pci_ids.h 　
9836
 PCI_VENDOR_ID_3DLABSPCI_VENDOR_ID_3DLABS 0x3d3d pci_ids.h 　
9837
 PCI_VENDOR_ID_AVANCEPCI_VENDOR_ID_AVANCE 0x4005 pci_ids.h 　
9838
 PCI_VENDOR_ID_AKSPCI_VENDOR_ID_AKS 0x416c pci_ids.h 　
9839
 PCI_VENDOR_ID_NETVINPCI_VENDOR_ID_NETVIN 0x4a14 pci_ids.h 　
9840
 PCI_VENDOR_ID_S3PCI_VENDOR_ID_S3 0x5333 pci_ids.h 　
9841
 PCI_VENDOR_ID_DCIPCI_VENDOR_ID_DCI 0x6666 pci_ids.h 　
9842
 PCI_VENDOR_ID_GENROCOPCI_VENDOR_ID_GENROCO 0x5555 pci_ids.h 　
9843
 PCI_VENDOR_ID_INTELPCI_VENDOR_ID_INTEL 0x8086 pci_ids.h 　
9844
 PCI_VENDOR_ID_COMPUTONEPCI_VENDOR_ID_COMPUTONE 0x8e0e pci_ids.h 　
9845
 PCI_SUBVENDOR_ID_COMPUTONEPCI_SUBVENDOR_ID_COMPUTONE 0x8e0e pci_ids.h 　
9846
 PCI_VENDOR_ID_KTIPCI_VENDOR_ID_KTI 0x8e2e pci_ids.h 　
9847
 PCI_VENDOR_ID_ADAPTECPCI_VENDOR_ID_ADAPTEC 0x9004 pci_ids.h 　
9848
 PCI_VENDOR_ID_ADAPTEC2PCI_VENDOR_ID_ADAPTEC2 0x9005 pci_ids.h 　
9849
 PCI_VENDOR_ID_ATRONICSPCI_VENDOR_ID_ATRONICS 0x907f pci_ids.h 　
9850
 PCI_VENDOR_ID_HOLTEK2PCI_VENDOR_ID_HOLTEK2 0x9412 pci_ids.h 　
9851
 PCI_VENDOR_ID_NETMOSPCI_VENDOR_ID_NETMOS 0x9710 pci_ids.h 　
9852
 PCI_SUBVENDOR_ID_EXSYSPCI_SUBVENDOR_ID_EXSYS 0xd84d pci_ids.h 　
9853
 PCI_VENDOR_ID_TIGERJETPCI_VENDOR_ID_TIGERJET 0xe159 pci_ids.h 　
9854
 PCI_VENDOR_ID_ARKPCI_VENDOR_ID_ARK 0xedd8 pci_ids.h 　
9855
 POSIX_FD_MINPOSIX_FD_MIN ( 1 ) posix_io.h 　
9856
 POSIX_FD_MAXPOSIX_FD_MAX ( 31 ) posix_io.h 　
9857
 RESOLV_NUMERICRESOLV_NUMERIC 01 resolv.h 　
9858
 RESOLV_NORMALRESOLV_NORMAL 02 resolv.h 　
9859
 RESOLVERSRESOLVERS __table ( struct resolver, "resolvers" ) resolv.h 　
9860
 DEFAULT_MIN_TIMEOUTDEFAULT_MIN_TIMEOUT ( TICKS_PER_SEC / 4 ) retry.h 　
9861
 DEFAULT_MAX_TIMEOUTDEFAULT_MAX_TIMEOUT ( 10 * TICKS_PER_SEC ) retry.h 　
9862
 SANBOOT_PROTOCOLSSANBOOT_PROTOCOLS __table ( struct sanboot_protocol, "sanboot_protocols" ) sanboot.h 　
9863
 __sanboot_protocol__sanboot_protocol __table_entry ( SANBOOT_PROTOCOLS, 01 ) sanboot.h 　
9864
 SCSI_OPCODE_READ_10SCSI_OPCODE_READ_10 0x28 scsi.h *< READ (10)
9865
 SCSI_OPCODE_READ_16SCSI_OPCODE_READ_16 0x88 scsi.h *< READ (16)
9866
 SCSI_OPCODE_WRITE_10SCSI_OPCODE_WRITE_10 0x2a scsi.h *< WRITE (10)
9867
 SCSI_OPCODE_WRITE_16SCSI_OPCODE_WRITE_16 0x8a scsi.h *< WRITE (16)
9868
 SCSI_OPCODE_READ_CAPACITY_10SCSI_OPCODE_READ_CAPACITY_10 0x25 scsi.h *< READ CAPACITY (10)
9869
 SCSI_OPCODE_SERVICE_ACTION_INSCSI_OPCODE_SERVICE_ACTION_IN 0x9e scsi.h *< SERVICE ACTION IN
9870
 SCSI_SERVICE_ACTION_READ_CAPACISCSI_SERVICE_ACTION_READ_CAPACI 0x10 scsi.h *< READ CAPACITY (16)
9871
 SCSI_FL_FUA_NVSCSI_FL_FUA_NV 0x02 scsi.h *< Force unit access to NVS
9872
 SCSI_FL_FUASCSI_FL_FUA 0x08 scsi.h *< Force unit access
9873
 SCSI_FL_DPOSCSI_FL_DPO 0x10 scsi.h *< Disable cache page out
9874
 SCSI_CDB_FORMATSCSI_CDB_FORMAT "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:" \ "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x" scsi.h 　
9875
 SETTINGSSETTINGS __table ( struct setting, "settings" ) settings.h 　
9876
 __setting__setting __table_entry ( SETTINGS, 01 ) settings.h 　
9877
 SETTING_TYPESSETTING_TYPES __table ( struct setting_type, "setting_types" ) settings.h 　
9878
 __setting_type__setting_type __table_entry ( SETTING_TYPES, 01 ) settings.h 　
9879
 SETTINGS_APPLICATORSSETTINGS_APPLICATORS __table ( struct settings_applicator, "settings_applicators" ) settings.h 　
9880
 __settings_applicator__settings_applicator __table_entry ( SETTINGS_APPLICATORS, 01 ) settings.h 　
9881
 SHA1_CTX_SIZESHA1_CTX_SIZE sizeof ( SHA1_CTX ) sha1.h 　
9882
 SHA1_DIGEST_SIZESHA1_DIGEST_SIZE SHA1_SIZE sha1.h 　
9883
 SMBIOS_SIGNATURESMBIOS_SIGNATURE ( ( '_' << 0 ) + ( 'S' << 8 ) + ( 'M' << 16 ) + ( '_' << 24 ) ) smbios.h 　
9884
 SMBIOS_TYPE_SYSTEM_INFORMATIONSMBIOS_TYPE_SYSTEM_INFORMATION 1 smbios.h 　
9885
 SMBIOS_TYPE_ENCLOSURE_INFORMATISMBIOS_TYPE_ENCLOSURE_INFORMATI 3 smbios.h 　
9886
 TCP_SOCK_STREAMTCP_SOCK_STREAM 0x1 socket.h 　
9887
 SOCK_STREAMSOCK_STREAM tcp_sock_stream socket.h 　
9888
 UDP_SOCK_DGRAMUDP_SOCK_DGRAM 0x2 socket.h 　
9889
 SOCK_DGRAMSOCK_DGRAM udp_sock_dgram socket.h 　
9890
 AF_INETAF_INET 1 socket.h *< IPv4 Internet addresses
9891
 AF_INET6AF_INET6 2 socket.h *< IPv6 Internet addresses
9892
 SA_LENSA_LEN 32 socket.h 　
9893
 SPI_WRSRSPI_WRSR 0x01 spi.h 　
9894
 SPI_WRITESPI_WRITE 0x02 spi.h 　
9895
 SPI_READSPI_READ 0x03 spi.h 　
9896
 SPI_WRDISPI_WRDI 0x04 spi.h 　
9897
 SPI_RDSRSPI_RDSR 0x05 spi.h 　
9898
 SPI_WRENSPI_WREN 0x06 spi.h 　
9899
 ATMEL_SECTOR_ERASEATMEL_SECTOR_ERASE 0x52 spi.h 　
9900
 ATMEL_CHIP_ERASEATMEL_CHIP_ERASE 0x62 spi.h 　
9901
 ATMEL_RDIDATMEL_RDID 0x15 spi.h 　
9902
 SPI_STATUS_WPENSPI_STATUS_WPEN 0x80 spi.h 　
9903
 SPI_STATUS_BP2SPI_STATUS_BP2 0x10 spi.h 　
9904
 SPI_STATUS_BP1SPI_STATUS_BP1 0x08 spi.h 　
9905
 SPI_STATUS_BP0SPI_STATUS_BP0 0x04 spi.h 　
9906
 SPI_STATUS_WENSPI_STATUS_WEN 0x02 spi.h 　
9907
 SPI_STATUS_NRDYSPI_STATUS_NRDY 0x01 spi.h 　
9908
 SPI_AUTODETECT_ADDRESS_LENSPI_AUTODETECT_ADDRESS_LEN 0 spi.h 　
9909
 SPI_MODE_CPHASPI_MODE_CPHA 0x01 spi.h 　
9910
 SPI_MODE_CPOLSPI_MODE_CPOL 0x02 spi.h 　
9911
 SPI_MODE_SSPOLSPI_MODE_SSPOL 0x10 spi.h 　
9912
 SPI_MODE_MICROWIRESPI_MODE_MICROWIRE 1 spi.h 　
9913
 SPI_MODE_MICROWIRE_PLUSSPI_MODE_MICROWIRE_PLUS 0 spi.h 　
9914
 SPI_MODE_THREEWIRESPI_MODE_THREEWIRE ( SPI_MODE_MICROWIRE_PLUS | SPI_MODE_SSPOL ) spi.h 　
9915
 SPI_BIT_UDELAYSPI_BIT_UDELAY 1 spi_bit.h 　
9916
 SPI_BIT_BIG_ENDIANSPI_BIT_BIG_ENDIAN 0 spi_bit.h 　
9917
 SPI_BIT_LITTLE_ENDIANSPI_BIT_LITTLE_ENDIAN 1 spi_bit.h 　
9918
 SRP_LOGIN_REQSRP_LOGIN_REQ 0x00 srp.h 　
9919
 SRP_LOGIN_REQ_FMT_IDBDSRP_LOGIN_REQ_FMT_IDBD 0x04 srp.h 　
9920
 SRP_LOGIN_REQ_FMT_DDBDSRP_LOGIN_REQ_FMT_DDBD 0x02 srp.h 　
9921
 SRP_LOGIN_REQ_FLAG_AESOLNTSRP_LOGIN_REQ_FLAG_AESOLNT 0x40 srp.h 　
9922
 SRP_LOGIN_REQ_FLAG_CRSOLNTSRP_LOGIN_REQ_FLAG_CRSOLNT 0x20 srp.h 　
9923
 SRP_LOGIN_REQ_FLAG_LOSOLNTSRP_LOGIN_REQ_FLAG_LOSOLNT 0x10 srp.h 　
9924
 SRP_LOGIN_REQ_MCA_MASKSRP_LOGIN_REQ_MCA_MASK 0x03 srp.h 　
9925
 SRP_LOGIN_REQ_MCA_SINGLE_CHANNESRP_LOGIN_REQ_MCA_SINGLE_CHANNE 0x00 srp.h 　
9926
 SRP_LOGIN_REQ_MCA_MULTIPLE_CHANSRP_LOGIN_REQ_MCA_MULTIPLE_CHAN 0x01 srp.h 　
9927
 SRP_LOGIN_RSPSRP_LOGIN_RSP 0xc0 srp.h 　
9928
 SRP_LOGIN_RSP_FMT_IDBDSRP_LOGIN_RSP_FMT_IDBD 0x04 srp.h 　
9929
 SRP_LOGIN_RSP_FMT_DDBDSRP_LOGIN_RSP_FMT_DDBD 0x02 srp.h 　
9930
 SRP_LOGIN_RSP_FLAG_SOLNTSUPSRP_LOGIN_RSP_FLAG_SOLNTSUP 0x10 srp.h 　
9931
 SRP_LOGIN_RSP_MCR_MASKSRP_LOGIN_RSP_MCR_MASK 0x03 srp.h 　
9932
 SRP_LOGIN_RSP_MCR_NO_EXISTING_CSRP_LOGIN_RSP_MCR_NO_EXISTING_C 0x00 srp.h 　
9933
 SRP_LOGIN_RSP_MCR_EXISTING_CHANSRP_LOGIN_RSP_MCR_EXISTING_CHAN 0x01 srp.h 　
9934
 SRP_LOGIN_RSP_MCR_EXISTING_CHANSRP_LOGIN_RSP_MCR_EXISTING_CHAN 0x02 srp.h 　
9935
 SRP_LOGIN_REJSRP_LOGIN_REJ 0xc2 srp.h 　
9936
 SRP_LOGIN_REJ_REASON_UNKNOWNSRP_LOGIN_REJ_REASON_UNKNOWN 0x00010000UL srp.h 　
9937
 SRP_LOGIN_REJ_REASON_INSUFFICIESRP_LOGIN_REJ_REASON_INSUFFICIE 0x00010001UL srp.h 　
9938
 SRP_LOGIN_REJ_REASON_BAD_MAX_I_SRP_LOGIN_REJ_REASON_BAD_MAX_I_ 0x00010002UL srp.h 　
9939
 SRP_LOGIN_REJ_REASON_CANNOT_ASSSRP_LOGIN_REJ_REASON_CANNOT_ASS 0x00010003UL srp.h 　
9940
 SRP_LOGIN_REJ_REASON_UNSUPPORTESRP_LOGIN_REJ_REASON_UNSUPPORTE 0x00010004UL srp.h 　
9941
 SRP_LOGIN_REJ_REASON_NO_MULTIPLSRP_LOGIN_REJ_REASON_NO_MULTIPL 0x00010005UL srp.h 　
9942
 SRP_LOGIN_REJ_REASON_NO_MORE_CHSRP_LOGIN_REJ_REASON_NO_MORE_CH 0x00010006UL srp.h 　
9943
 SRP_LOGIN_REJ_FMT_IDBDSRP_LOGIN_REJ_FMT_IDBD 0x04 srp.h 　
9944
 SRP_LOGIN_REJ_FMT_DDBDSRP_LOGIN_REJ_FMT_DDBD 0x02 srp.h 　
9945
 SRP_I_LOGOUTSRP_I_LOGOUT 0x03 srp.h 　
9946
 SRP_T_LOGOUTSRP_T_LOGOUT 0x80 srp.h 　
9947
 SRP_T_LOGOUT_FLAG_SOLNTSRP_T_LOGOUT_FLAG_SOLNT 0x01 srp.h 　
9948
 SRP_T_LOGOUT_REASON_UNKNOWNSRP_T_LOGOUT_REASON_UNKNOWN 0x00000000UL srp.h 　
9949
 SRP_T_LOGOUT_REASON_INACTIVESRP_T_LOGOUT_REASON_INACTIVE 0x00000001UL srp.h 　
9950
 SRP_T_LOGOUT_REASON_INVALID_TYPSRP_T_LOGOUT_REASON_INVALID_TYP 0x00000002UL srp.h 　
9951
 SRP_T_LOGOUT_REASON_SPURIOUS_RESRP_T_LOGOUT_REASON_SPURIOUS_RE 0x00000003UL srp.h 　
9952
 SRP_T_LOGOUT_REASON_MCASRP_T_LOGOUT_REASON_MCA 0x00000004UL srp.h 　
9953
 SRP_T_LOGOUT_UNSUPPORTED_DATA_OSRP_T_LOGOUT_UNSUPPORTED_DATA_O 0x00000005UL srp.h 　
9954
 SRP_T_LOGOUT_UNSUPPORTED_DATA_ISRP_T_LOGOUT_UNSUPPORTED_DATA_I 0x00000006UL srp.h 　
9955
 SRP_T_LOGOUT_INVALID_IU_LENSRP_T_LOGOUT_INVALID_IU_LEN 0x00000008UL srp.h 　
9956
 SRP_TSK_MGMTSRP_TSK_MGMT 0x01 srp.h 　
9957
 SRP_TSK_MGMT_FLAG_UCSOLNTSRP_TSK_MGMT_FLAG_UCSOLNT 0x04 srp.h 　
9958
 SRP_TSK_MGMT_FLAG_SCSOLNTSRP_TSK_MGMT_FLAG_SCSOLNT 0x02 srp.h 　
9959
 SRP_TSK_MGMT_FUNC_ABORT_TASKSRP_TSK_MGMT_FUNC_ABORT_TASK 0x01 srp.h 　
9960
 SRP_TSK_MGMT_FUNC_ABORT_TASK_SESRP_TSK_MGMT_FUNC_ABORT_TASK_SE 0x02 srp.h 　
9961
 SRP_TSK_MGMT_FUNC_CLEAR_TASK_SESRP_TSK_MGMT_FUNC_CLEAR_TASK_SE 0x04 srp.h 　
9962
 SRP_TSK_MGMT_FUNC_LOGICAL_UNIT_SRP_TSK_MGMT_FUNC_LOGICAL_UNIT_ 0x08 srp.h 　
9963
 SRP_TSK_MGMT_FUNC_CLEAR_ACASRP_TSK_MGMT_FUNC_CLEAR_ACA 0x40 srp.h 　
9964
 SRP_CMDSRP_CMD 0x02 srp.h 　
9965
 SRP_CMD_FLAG_UCSOLNTSRP_CMD_FLAG_UCSOLNT 0x04 srp.h 　
9966
 SRP_CMD_FLAG_SCSOLNTSRP_CMD_FLAG_SCSOLNT 0x02 srp.h 　
9967
 SRP_CMD_DO_FMT_MASKSRP_CMD_DO_FMT_MASK 0xf0 srp.h 　
9968
 SRP_CMD_DO_FMT_DIRECTSRP_CMD_DO_FMT_DIRECT 0x10 srp.h 　
9969
 SRP_CMD_DO_FMT_INDIRECTSRP_CMD_DO_FMT_INDIRECT 0x20 srp.h 　
9970
 SRP_CMD_DI_FMT_MASKSRP_CMD_DI_FMT_MASK 0x0f srp.h 　
9971
 SRP_CMD_DI_FMT_DIRECTSRP_CMD_DI_FMT_DIRECT 0x01 srp.h 　
9972
 SRP_CMD_DI_FMT_INDIRECTSRP_CMD_DI_FMT_INDIRECT 0x02 srp.h 　
9973
 SRP_CMD_TASK_ATTR_SIMPLESRP_CMD_TASK_ATTR_SIMPLE 0x00 srp.h 　
9974
 SRP_CMD_TASK_ATTR_QUEUE_HEADSRP_CMD_TASK_ATTR_QUEUE_HEAD 0x01 srp.h 　
9975
 SRP_CMD_TASK_ATTR_ORDEREDSRP_CMD_TASK_ATTR_ORDERED 0x02 srp.h 　
9976
 SRP_CMD_TASK_ATTR_AUTOMATIC_CONSRP_CMD_TASK_ATTR_AUTOMATIC_CON 0x08 srp.h 　
9977
 SRP_RSPSRP_RSP 0xc1 srp.h 　
9978
 SRP_RSP_FLAG_SOLNTSRP_RSP_FLAG_SOLNT 0x01 srp.h 　
9979
 SRP_RSP_VALID_DIUNDERSRP_RSP_VALID_DIUNDER 0x20 srp.h 　
9980
 SRP_RSP_VALID_DIOVERSRP_RSP_VALID_DIOVER 0x10 srp.h 　
9981
 SRP_RSP_VALID_DOUNDERSRP_RSP_VALID_DOUNDER 0x08 srp.h 　
9982
 SRP_RSP_VALID_DOOVERSRP_RSP_VALID_DOOVER 0x04 srp.h 　
9983
 SRP_RSP_VALID_SNSVALIDSRP_RSP_VALID_SNSVALID 0x02 srp.h 　
9984
 SRP_RSP_VALID_RSPVALIDSRP_RSP_VALID_RSPVALID 0x01 srp.h 　
9985
 SRP_CRED_REQSRP_CRED_REQ 0x81 srp.h 　
9986
 SRP_CRED_REQ_FLAG_SOLNTSRP_CRED_REQ_FLAG_SOLNT 0x01 srp.h 　
9987
 SRP_CRED_RSPSRP_CRED_RSP 0x41 srp.h 　
9988
 SRP_AER_REQSRP_AER_REQ 0x82 srp.h 　
9989
 SRP_AER_REQ_FLAG_SOLNTSRP_AER_REQ_FLAG_SOLNT 0x01 srp.h 　
9990
 SRP_AER_RSPSRP_AER_RSP 0x42 srp.h 　
9991
 SRP_MAX_I_T_IU_LENSRP_MAX_I_T_IU_LEN 80 srp.h 　
9992
 SRP_MAX_RETRIESSRP_MAX_RETRIES 3 srp.h 　
9993
 ICC_ALIGN_HACK_FACTORICC_ALIGN_HACK_FACTOR 128 tables.h 　
9994
 TCP_OPTION_ENDTCP_OPTION_END 0 tcp.h 　
9995
 TCP_OPTION_NOPTCP_OPTION_NOP 1 tcp.h 　
9996
 TCP_OPTION_MSSTCP_OPTION_MSS 2 tcp.h 　
9997
 TCP_OPTION_TSTCP_OPTION_TS 8 tcp.h 　
9998
 TCP_CWRTCP_CWR 0x80 tcp.h 　
9999
 TCP_ECETCP_ECE 0x40 tcp.h 　
10000
 TCP_URGTCP_URG 0x20 tcp.h 　
10001
 TCP_ACKTCP_ACK 0x10 tcp.h 　
10002
 TCP_PSHTCP_PSH 0x08 tcp.h 　
10003
 TCP_RSTTCP_RST 0x04 tcp.h 　
10004
 TCP_SYNTCP_SYN 0x02 tcp.h 　
10005
 TCP_FINTCP_FIN 0x01 tcp.h 　
10006
 TCP_CLOSEDTCP_CLOSED TCP_RST tcp.h 　
10007
 TCP_LISTENTCP_LISTEN 0 tcp.h 　
10008
 TCP_SYN_SENTTCP_SYN_SENT ( TCP_STATE_SENT ( TCP_SYN ) ) tcp.h 　
10009
 TCP_SYN_RCVDTCP_SYN_RCVD ( TCP_STATE_SENT ( TCP_SYN | TCP_ACK ) | \ TCP_STATE_RCVD ( TCP_SYN ) ) tcp.h 　
10010
 TCP_ESTABLISHEDTCP_ESTABLISHED ( TCP_STATE_SENT ( TCP_SYN | TCP_ACK ) | \ TCP_STATE_ACKED ( TCP_SYN ) | \ TCP_STATE_RCVD ( TCP_SYN ) ) tcp.h 　
10011
 TCP_FIN_WAIT_1TCP_FIN_WAIT_1 ( TCP_STATE_SENT ( TCP_SYN | TCP_ACK | TCP_FIN ) | \ TCP_STATE_ACKED ( TCP_SYN ) | \ TCP_STATE_RCVD ( TCP_SYN ) ) tcp.h 　
10012
 TCP_FIN_WAIT_2TCP_FIN_WAIT_2 ( TCP_STATE_SENT ( TCP_SYN | TCP_ACK | TCP_FIN ) | \ TCP_STATE_ACKED ( TCP_SYN | TCP_FIN ) | \ TCP_STATE_RCVD ( TCP_SYN ) tcp.h 　
10013
 TCP_CLOSING_OR_LAST_ACKTCP_CLOSING_OR_LAST_ACK ( TCP_STATE_SENT ( TCP_SYN | TCP_ACK | TCP_FIN ) | \ TCP_STATE_ACKED ( TCP_SYN ) | \ TCP_STATE_RCVD ( TCP_SYN | TCP_FI tcp.h 　
10014
 TCP_TIME_WAITTCP_TIME_WAIT ( TCP_STATE_SENT ( TCP_SYN | TCP_ACK | TCP_FIN ) | \ TCP_STATE_ACKED ( TCP_SYN | TCP_FIN ) | \ TCP_STATE_RCVD ( TCP_SYN | tcp.h 　
10015
 TCP_CLOSE_WAITTCP_CLOSE_WAIT ( TCP_STATE_SENT ( TCP_SYN | TCP_ACK ) | \ TCP_STATE_ACKED ( TCP_SYN ) | \ TCP_STATE_RCVD ( TCP_SYN | TCP_FIN ) ) tcp.h 　
10016
 TCP_MASK_HLENTCP_MASK_HLEN 0xf0 tcp.h 　
10017
 TCP_MIN_PORTTCP_MIN_PORT 1 tcp.h 　
10018
 MAX_HDR_LENMAX_HDR_LEN 100 tcp.h 　
10019
 MAX_IOB_LENMAX_IOB_LEN 1500 tcp.h 　
10020
 MIN_IOB_LENMIN_IOB_LEN MAX_HDR_LEN + 100 tcp.h To account for padding by LL
10021
 TCP_MAX_WINDOW_SIZETCP_MAX_WINDOW_SIZE 4096 tcp.h 　
10022
 TCP_PATH_MTUTCP_PATH_MTU 1460 tcp.h 　
10023
 TCP_MSSTCP_MSS 1460 tcp.h 　
10024
 TCP_MSLTCP_MSL ( 2 * 60 * TICKS_PER_SEC ) tcp.h 　
10025
 TCPIP_EMPTY_CSUMTCPIP_EMPTY_CSUM 0xffff tcpip.h 　
10026
 TCPIP_PROTOCOLSTCPIP_PROTOCOLS __table ( struct tcpip_protocol, "tcpip_protocols" ) tcpip.h 　
10027
 __tcpip_protocol__tcpip_protocol __table_entry ( TCPIP_PROTOCOLS, 01 ) tcpip.h 　
10028
 TCPIP_NET_PROTOCOLSTCPIP_NET_PROTOCOLS __table ( struct tcpip_net_protocol, "tcpip_net_protocols" ) tcpip.h 　
10029
 __tcpip_net_protocol__tcpip_net_protocol __table_entry ( TCPIP_NET_PROTOCOLS, 01 ) tcpip.h 　
10030
 TFTP_PORTTFTP_PORT 69 tftp.h *< Default TFTP server port
10031
 TFTP_DEFAULT_BLKSIZETFTP_DEFAULT_BLKSIZE 512 tftp.h *< Default TFTP data block size
10032
 TFTP_MAX_BLKSIZETFTP_MAX_BLKSIZE 1432 tftp.h 　
10033
 TFTP_RRQTFTP_RRQ 1 tftp.h *< Read request opcode
10034
 TFTP_WRQTFTP_WRQ 2 tftp.h *< Write request opcode
10035
 TFTP_DATATFTP_DATA 3 tftp.h *< Data block opcode
10036
 TFTP_ACKTFTP_ACK 4 tftp.h *< Data block acknowledgement opcode
10037
 TFTP_ERRORTFTP_ERROR 5 tftp.h *< Error opcode
10038
 TFTP_OACKTFTP_OACK 6 tftp.h *< Options acknowledgement opcode
10039
 TFTP_ERR_FILE_NOT_FOUNDTFTP_ERR_FILE_NOT_FOUND 1 tftp.h *< File not found
10040
 TFTP_ERR_ACCESS_DENIEDTFTP_ERR_ACCESS_DENIED 2 tftp.h *< Access violation
10041
 TFTP_ERR_DISK_FULLTFTP_ERR_DISK_FULL 3 tftp.h *< Disk full or allocation exceeded
10042
 TFTP_ERR_ILLEGAL_OPTFTP_ERR_ILLEGAL_OP 4 tftp.h *< Illegal TFTP operation
10043
 TFTP_ERR_UNKNOWN_TIDTFTP_ERR_UNKNOWN_TID 5 tftp.h *< Unknown transfer ID
10044
 TFTP_ERR_FILE_EXISTSTFTP_ERR_FILE_EXISTS 6 tftp.h *< File already exists
10045
 TFTP_ERR_UNKNOWN_USERTFTP_ERR_UNKNOWN_USER 7 tftp.h *< No such user
10046
 TFTP_ERR_BAD_OPTSTFTP_ERR_BAD_OPTS 8 tftp.h *< Option negotiation failed
10047
 MTFTP_PORTMTFTP_PORT 1759 tftp.h *< Default MTFTP server port
10048
 THREEWIRE_READTHREEWIRE_READ 0x6 threewire.h 　
10049
 THREEWIRE_WRITETHREEWIRE_WRITE 0x5 threewire.h 　
10050
 THREEWIRE_EWENTHREEWIRE_EWEN 0x4 threewire.h 　
10051
 THREEWIRE_EWEN_ADDRESSTHREEWIRE_EWEN_ADDRESS INT_MAX threewire.h 　
10052
 THREEWIRE_WRITE_MDELAYTHREEWIRE_WRITE_MDELAY 10 threewire.h 　
10053
 TICKS_PER_SECTICKS_PER_SEC ( ticks_per_sec() ) timer.h 　
10054
 TLS_VERSION_TLS_1_0TLS_VERSION_TLS_1_0 0x0301 tls.h 　
10055
 TLS_VERSION_TLS_1_1TLS_VERSION_TLS_1_1 0x0302 tls.h 　
10056
 TLS_TYPE_CHANGE_CIPHERTLS_TYPE_CHANGE_CIPHER 20 tls.h 　
10057
 TLS_TYPE_ALERTTLS_TYPE_ALERT 21 tls.h 　
10058
 TLS_TYPE_HANDSHAKETLS_TYPE_HANDSHAKE 22 tls.h 　
10059
 TLS_TYPE_DATATLS_TYPE_DATA 23 tls.h 　
10060
 TLS_HELLO_REQUESTTLS_HELLO_REQUEST 0 tls.h 　
10061
 TLS_CLIENT_HELLOTLS_CLIENT_HELLO 1 tls.h 　
10062
 TLS_SERVER_HELLOTLS_SERVER_HELLO 2 tls.h 　
10063
 TLS_CERTIFICATETLS_CERTIFICATE 11 tls.h 　
10064
 TLS_SERVER_KEY_EXCHANGETLS_SERVER_KEY_EXCHANGE 12 tls.h 　
10065
 TLS_CERTIFICATE_REQUESTTLS_CERTIFICATE_REQUEST 13 tls.h 　
10066
 TLS_SERVER_HELLO_DONETLS_SERVER_HELLO_DONE 14 tls.h 　
10067
 TLS_CERTIFICATE_VERIFYTLS_CERTIFICATE_VERIFY 15 tls.h 　
10068
 TLS_CLIENT_KEY_EXCHANGETLS_CLIENT_KEY_EXCHANGE 16 tls.h 　
10069
 TLS_FINISHEDTLS_FINISHED 20 tls.h 　
10070
 TLS_ALERT_WARNINGTLS_ALERT_WARNING 1 tls.h 　
10071
 TLS_ALERT_FATALTLS_ALERT_FATAL 2 tls.h 　
10072
 TLS_RSA_WITH_NULL_MD5TLS_RSA_WITH_NULL_MD5 0x0001 tls.h 　
10073
 TLS_RSA_WITH_NULL_SHATLS_RSA_WITH_NULL_SHA 0x0002 tls.h 　
10074
 TLS_RSA_WITH_AES_128_CBC_SHATLS_RSA_WITH_AES_128_CBC_SHA 0x002f tls.h 　
10075
 TLS_RSA_WITH_AES_256_CBC_SHATLS_RSA_WITH_AES_256_CBC_SHA 0x0035 tls.h 　
10076
 UNULLUNULL ( ( userptr_t ) 0 ) uaccess.h 　
10077
 UDP_MAX_HLENUDP_MAX_HLEN 72 udp.h 　
10078
 UDP_MAX_TXIOBUDP_MAX_TXIOB ETH_MAX_MTU udp.h 　
10079
 UDP_MIN_TXIOBUDP_MIN_TXIOB ETH_ZLEN udp.h 　
10080
 URI_ALLURI_ALL ( URI_SCHEME_BIT | URI_OPAQUE_BIT | URI_USER_BIT | \ URI_PASSWORD_BIT | URI_HOST_BIT | URI_PORT_BIT | \ URI_PATH_BIT | URI_QUER uri.h 　
10081
 URI_ENCODEDURI_ENCODED ( URI_USER_BIT | URI_PASSWORD_BIT | URI_HOST_BIT | \ URI_PATH_BIT | URI_QUERY_BIT | URI_FRAGMENT_BIT ) uri.h 　
10082
 VIRTIO_PCI_HOST_FEATURESVIRTIO_PCI_HOST_FEATURES 0 virtio-pci.h 　
10083
 VIRTIO_PCI_GUEST_FEATURESVIRTIO_PCI_GUEST_FEATURES 4 virtio-pci.h 　
10084
 VIRTIO_PCI_QUEUE_PFNVIRTIO_PCI_QUEUE_PFN 8 virtio-pci.h 　
10085
 VIRTIO_PCI_QUEUE_NUMVIRTIO_PCI_QUEUE_NUM 12 virtio-pci.h 　
10086
 VIRTIO_PCI_QUEUE_SELVIRTIO_PCI_QUEUE_SEL 14 virtio-pci.h 　
10087
 VIRTIO_PCI_QUEUE_NOTIFYVIRTIO_PCI_QUEUE_NOTIFY 16 virtio-pci.h 　
10088
 VIRTIO_PCI_STATUSVIRTIO_PCI_STATUS 18 virtio-pci.h 　
10089
 VIRTIO_PCI_ISRVIRTIO_PCI_ISR 19 virtio-pci.h 　
10090
 VIRTIO_PCI_ISR_CONFIGVIRTIO_PCI_ISR_CONFIG 0x2 virtio-pci.h 　
10091
 VIRTIO_PCI_CONFIGVIRTIO_PCI_CONFIG 20 virtio-pci.h 　
10092
 VIRTIO_PCI_ABI_VERSIONVIRTIO_PCI_ABI_VERSION 0 virtio-pci.h 　
10093
 PAGE_SHIFTPAGE_SHIFT (12) virtio-ring.h 　
10094
 PAGE_SIZEPAGE_SIZE (1<<PAGE_SHIFT) virtio-ring.h 　
10095
 PAGE_MASKPAGE_MASK (PAGE_SIZE-1) virtio-ring.h 　
10096
 VIRTIO_CONFIG_S_ACKNOWLEDGEVIRTIO_CONFIG_S_ACKNOWLEDGE 1 virtio-ring.h 　
10097
 VIRTIO_CONFIG_S_DRIVERVIRTIO_CONFIG_S_DRIVER 2 virtio-ring.h 　
10098
 VIRTIO_CONFIG_S_DRIVER_OKVIRTIO_CONFIG_S_DRIVER_OK 4 virtio-ring.h 　
10099
 VIRTIO_CONFIG_S_FAILEDVIRTIO_CONFIG_S_FAILED 0x80 virtio-ring.h 　
10100
 MAX_QUEUE_NUMMAX_QUEUE_NUM (512) virtio-ring.h 　
10101
 VRING_DESC_F_NEXTVRING_DESC_F_NEXT 1 virtio-ring.h 　
10102
 VRING_DESC_F_WRITEVRING_DESC_F_WRITE 2 virtio-ring.h 　
10103
 VRING_AVAIL_F_NO_INTERRUPTVRING_AVAIL_F_NO_INTERRUPT 1 virtio-ring.h 　
10104
 VRING_USED_F_NO_NOTIFYVRING_USED_F_NO_NOTIFY 1 virtio-ring.h 　
10105
 EAPOL_KEY_TYPE_RSNEAPOL_KEY_TYPE_RSN 2 wpa.h 　
10106
 EAPOL_KEY_TYPE_WPAEAPOL_KEY_TYPE_WPA 254 wpa.h 　
10107
 EAPOL_KEY_INFO_VERSIONEAPOL_KEY_INFO_VERSION 0x0007 wpa.h 　
10108
 EAPOL_KEY_INFO_TYPEEAPOL_KEY_INFO_TYPE 0x0008 wpa.h 　
10109
 EAPOL_KEY_INFO_INSTALLEAPOL_KEY_INFO_INSTALL 0x0040 wpa.h 　
10110
 EAPOL_KEY_INFO_KEY_ACKEAPOL_KEY_INFO_KEY_ACK 0x0080 wpa.h 　
10111
 EAPOL_KEY_INFO_KEY_MICEAPOL_KEY_INFO_KEY_MIC 0x0100 wpa.h 　
10112
 EAPOL_KEY_INFO_SECUREEAPOL_KEY_INFO_SECURE 0x0200 wpa.h 　
10113
 EAPOL_KEY_INFO_ERROREAPOL_KEY_INFO_ERROR 0x0400 wpa.h 　
10114
 EAPOL_KEY_INFO_REQUESTEAPOL_KEY_INFO_REQUEST 0x0800 wpa.h 　
10115
 EAPOL_KEY_INFO_KEY_ENCEAPOL_KEY_INFO_KEY_ENC 0x1000 wpa.h 　
10116
 EAPOL_KEY_INFO_SMC_MESSEAPOL_KEY_INFO_SMC_MESS 0x2000 wpa.h 　
10117
 EAPOL_KEY_VERSION_WPAEAPOL_KEY_VERSION_WPA 1 wpa.h 　
10118
 EAPOL_KEY_VERSION_WPA2EAPOL_KEY_VERSION_WPA2 2 wpa.h 　
10119
 EAPOL_KEY_TYPE_PTKEAPOL_KEY_TYPE_PTK 0x0008 wpa.h 　
10120
 EAPOL_KEY_TYPE_GTKEAPOL_KEY_TYPE_GTK 0x0000 wpa.h 　
10121
 WPA_NONCE_LENWPA_NONCE_LEN 32 wpa.h 　
10122
 WPA_TKIP_KEY_LENWPA_TKIP_KEY_LEN 16 wpa.h 　
10123
 WPA_TKIP_MIC_KEY_LENWPA_TKIP_MIC_KEY_LEN 8 wpa.h 　
10124
 WPA_CCMP_KEY_LENWPA_CCMP_KEY_LEN 16 wpa.h 　
10125
 WPA_KCK_LENWPA_KCK_LEN 16 wpa.h 　
10126
 WPA_KEK_LENWPA_KEK_LEN 16 wpa.h 　
10127
 WPA_PMK_LENWPA_PMK_LEN 32 wpa.h 　
10128
 WPA_PMKID_LENWPA_PMKID_LEN 16 wpa.h 　
10129
 WPA_KIESWPA_KIES __table ( struct wpa_kie, "wpa_kies" ) wpa.h 　
10130
 __wpa_kie__wpa_kie __table_entry ( WPA_KIES, 01 ) wpa.h 　
10131
 WPA_GTK_KIDWPA_GTK_KID 0x03 wpa.h 　
10132
 WPA_GTK_TXBITWPA_GTK_TXBIT 0x04 wpa.h 　
10133
 WPA_KDE_GTKWPA_KDE_GTK _MKOUI ( 0x00, 0x0F, 0xAC, 0x01 ) wpa.h 　
10134
 WPA_KDE_MACWPA_KDE_MAC _MKOUI ( 0x00, 0x0F, 0xAC, 0x03 ) wpa.h 　
10135
 WPA_KDE_PMKIDWPA_KDE_PMKID _MKOUI ( 0x00, 0x0F, 0xAC, 0x04 ) wpa.h 　
10136
 WPA_KDE_NONCEWPA_KDE_NONCE _MKOUI ( 0x00, 0x0F, 0xAC, 0x06 ) wpa.h 　
10137
 WPA_KDE_LIFETIMEWPA_KDE_LIFETIME _MKOUI ( 0x00, 0x0F, 0xAC, 0x07 ) wpa.h 　
10138
 GLOBAL_REMOVE_IF_UNREFERENCEDGLOBAL_REMOVE_IF_UNREFERENCED __declspec(selectany) Base.h 　
10139
 ASM_FUNCTION_REMOVE_IF_UNREFEREASM_FUNCTION_REMOVE_IF_UNREFERE .subsections_via_symbols Base.h 　
10140
 CONSTCONST const Base.h 　
10141
 STATICSTATIC static Base.h 　
10142
 VOIDVOID void Base.h 　
10143
 TRUETRUE ((BOOLEAN)(1==1)) Base.h 　
10144
 FALSEFALSE ((BOOLEAN)(0==1)) Base.h 　
10145
 NULLNULL ((VOID *) 0) Base.h 　
10146
 BIT0BIT0 0x00000001 Base.h 　
10147
 BIT1BIT1 0x00000002 Base.h 　
10148
 BIT2BIT2 0x00000004 Base.h 　
10149
 BIT3BIT3 0x00000008 Base.h 　
10150
 BIT4BIT4 0x00000010 Base.h 　
10151
 BIT5BIT5 0x00000020 Base.h 　
10152
 BIT6BIT6 0x00000040 Base.h 　
10153
 BIT7BIT7 0x00000080 Base.h 　
10154
 BIT8BIT8 0x00000100 Base.h 　
10155
 BIT9BIT9 0x00000200 Base.h 　
10156
 BIT10BIT10 0x00000400 Base.h 　
10157
 BIT11BIT11 0x00000800 Base.h 　
10158
 BIT12BIT12 0x00001000 Base.h 　
10159
 BIT13BIT13 0x00002000 Base.h 　
10160
 BIT14BIT14 0x00004000 Base.h 　
10161
 BIT15BIT15 0x00008000 Base.h 　
10162
 BIT16BIT16 0x00010000 Base.h 　
10163
 BIT17BIT17 0x00020000 Base.h 　
10164
 BIT18BIT18 0x00040000 Base.h 　
10165
 BIT19BIT19 0x00080000 Base.h 　
10166
 BIT20BIT20 0x00100000 Base.h 　
10167
 BIT21BIT21 0x00200000 Base.h 　
10168
 BIT22BIT22 0x00400000 Base.h 　
10169
 BIT23BIT23 0x00800000 Base.h 　
10170
 BIT24BIT24 0x01000000 Base.h 　
10171
 BIT25BIT25 0x02000000 Base.h 　
10172
 BIT26BIT26 0x04000000 Base.h 　
10173
 BIT27BIT27 0x08000000 Base.h 　
10174
 BIT28BIT28 0x10000000 Base.h 　
10175
 BIT29BIT29 0x20000000 Base.h 　
10176
 BIT30BIT30 0x40000000 Base.h 　
10177
 BIT31BIT31 0x80000000 Base.h 　
10178
 BIT32BIT32 0x0000000100000000ULL Base.h 　
10179
 BIT33BIT33 0x0000000200000000ULL Base.h 　
10180
 BIT34BIT34 0x0000000400000000ULL Base.h 　
10181
 BIT35BIT35 0x0000000800000000ULL Base.h 　
10182
 BIT36BIT36 0x0000001000000000ULL Base.h 　
10183
 BIT37BIT37 0x0000002000000000ULL Base.h 　
10184
 BIT38BIT38 0x0000004000000000ULL Base.h 　
10185
 BIT39BIT39 0x0000008000000000ULL Base.h 　
10186
 BIT40BIT40 0x0000010000000000ULL Base.h 　
10187
 BIT41BIT41 0x0000020000000000ULL Base.h 　
10188
 BIT42BIT42 0x0000040000000000ULL Base.h 　
10189
 BIT43BIT43 0x0000080000000000ULL Base.h 　
10190
 BIT44BIT44 0x0000100000000000ULL Base.h 　
10191
 BIT45BIT45 0x0000200000000000ULL Base.h 　
10192
 BIT46BIT46 0x0000400000000000ULL Base.h 　
10193
 BIT47BIT47 0x0000800000000000ULL Base.h 　
10194
 BIT48BIT48 0x0001000000000000ULL Base.h 　
10195
 BIT49BIT49 0x0002000000000000ULL Base.h 　
10196
 BIT50BIT50 0x0004000000000000ULL Base.h 　
10197
 BIT51BIT51 0x0008000000000000ULL Base.h 　
10198
 BIT52BIT52 0x0010000000000000ULL Base.h 　
10199
 BIT53BIT53 0x0020000000000000ULL Base.h 　
10200
 BIT54BIT54 0x0040000000000000ULL Base.h 　
10201
 BIT55BIT55 0x0080000000000000ULL Base.h 　
10202
 BIT56BIT56 0x0100000000000000ULL Base.h 　
10203
 BIT57BIT57 0x0200000000000000ULL Base.h 　
10204
 BIT58BIT58 0x0400000000000000ULL Base.h 　
10205
 BIT59BIT59 0x0800000000000000ULL Base.h 　
10206
 BIT60BIT60 0x1000000000000000ULL Base.h 　
10207
 BIT61BIT61 0x2000000000000000ULL Base.h 　
10208
 BIT62BIT62 0x4000000000000000ULL Base.h 　
10209
 BIT63BIT63 0x8000000000000000ULL Base.h 　
10210
 SIZE_1KBSIZE_1KB 0x00000400 Base.h 　
10211
 SIZE_2KBSIZE_2KB 0x00000800 Base.h 　
10212
 SIZE_4KBSIZE_4KB 0x00001000 Base.h 　
10213
 SIZE_8KBSIZE_8KB 0x00002000 Base.h 　
10214
 SIZE_16KBSIZE_16KB 0x00004000 Base.h 　
10215
 SIZE_32KBSIZE_32KB 0x00008000 Base.h 　
10216
 SIZE_64KBSIZE_64KB 0x00010000 Base.h 　
10217
 SIZE_128KBSIZE_128KB 0x00020000 Base.h 　
10218
 SIZE_256KBSIZE_256KB 0x00040000 Base.h 　
10219
 SIZE_512KBSIZE_512KB 0x00080000 Base.h 　
10220
 SIZE_1MBSIZE_1MB 0x00100000 Base.h 　
10221
 SIZE_2MBSIZE_2MB 0x00200000 Base.h 　
10222
 SIZE_4MBSIZE_4MB 0x00400000 Base.h 　
10223
 SIZE_8MBSIZE_8MB 0x00800000 Base.h 　
10224
 SIZE_16MBSIZE_16MB 0x01000000 Base.h 　
10225
 SIZE_32MBSIZE_32MB 0x02000000 Base.h 　
10226
 SIZE_64MBSIZE_64MB 0x04000000 Base.h 　
10227
 SIZE_128MBSIZE_128MB 0x08000000 Base.h 　
10228
 SIZE_256MBSIZE_256MB 0x10000000 Base.h 　
10229
 SIZE_512MBSIZE_512MB 0x20000000 Base.h 　
10230
 SIZE_1GBSIZE_1GB 0x40000000 Base.h 　
10231
 SIZE_2GBSIZE_2GB 0x80000000 Base.h 　
10232
 SIZE_4GBSIZE_4GB 0x0000000100000000ULL Base.h 　
10233
 SIZE_8GBSIZE_8GB 0x0000000200000000ULL Base.h 　
10234
 SIZE_16GBSIZE_16GB 0x0000000400000000ULL Base.h 　
10235
 SIZE_32GBSIZE_32GB 0x0000000800000000ULL Base.h 　
10236
 SIZE_64GBSIZE_64GB 0x0000001000000000ULL Base.h 　
10237
 SIZE_128GBSIZE_128GB 0x0000002000000000ULL Base.h 　
10238
 SIZE_256GBSIZE_256GB 0x0000004000000000ULL Base.h 　
10239
 SIZE_512GBSIZE_512GB 0x0000008000000000ULL Base.h 　
10240
 SIZE_1TBSIZE_1TB 0x0000010000000000ULL Base.h 　
10241
 SIZE_2TBSIZE_2TB 0x0000020000000000ULL Base.h 　
10242
 SIZE_4TBSIZE_4TB 0x0000040000000000ULL Base.h 　
10243
 SIZE_8TBSIZE_8TB 0x0000080000000000ULL Base.h 　
10244
 SIZE_16TBSIZE_16TB 0x0000100000000000ULL Base.h 　
10245
 SIZE_32TBSIZE_32TB 0x0000200000000000ULL Base.h 　
10246
 SIZE_64TBSIZE_64TB 0x0000400000000000ULL Base.h 　
10247
 SIZE_128TBSIZE_128TB 0x0000800000000000ULL Base.h 　
10248
 SIZE_256TBSIZE_256TB 0x0001000000000000ULL Base.h 　
10249
 SIZE_512TBSIZE_512TB 0x0002000000000000ULL Base.h 　
10250
 SIZE_1PBSIZE_1PB 0x0004000000000000ULL Base.h 　
10251
 SIZE_2PBSIZE_2PB 0x0008000000000000ULL Base.h 　
10252
 SIZE_4PBSIZE_4PB 0x0010000000000000ULL Base.h 　
10253
 SIZE_8PBSIZE_8PB 0x0020000000000000ULL Base.h 　
10254
 SIZE_16PBSIZE_16PB 0x0040000000000000ULL Base.h 　
10255
 SIZE_32PBSIZE_32PB 0x0080000000000000ULL Base.h 　
10256
 SIZE_64PBSIZE_64PB 0x0100000000000000ULL Base.h 　
10257
 SIZE_128PBSIZE_128PB 0x0200000000000000ULL Base.h 　
10258
 SIZE_256PBSIZE_256PB 0x0400000000000000ULL Base.h 　
10259
 SIZE_512PBSIZE_512PB 0x0800000000000000ULL Base.h 　
10260
 SIZE_1EBSIZE_1EB 0x1000000000000000ULL Base.h 　
10261
 SIZE_2EBSIZE_2EB 0x2000000000000000ULL Base.h 　
10262
 SIZE_4EBSIZE_4EB 0x4000000000000000ULL Base.h 　
10263
 SIZE_8EBSIZE_8EB 0x8000000000000000ULL Base.h 　
10264
 BASE_1KBBASE_1KB 0x00000400 Base.h 　
10265
 BASE_2KBBASE_2KB 0x00000800 Base.h 　
10266
 BASE_4KBBASE_4KB 0x00001000 Base.h 　
10267
 BASE_8KBBASE_8KB 0x00002000 Base.h 　
10268
 BASE_16KBBASE_16KB 0x00004000 Base.h 　
10269
 BASE_32KBBASE_32KB 0x00008000 Base.h 　
10270
 BASE_64KBBASE_64KB 0x00010000 Base.h 　
10271
 BASE_128KBBASE_128KB 0x00020000 Base.h 　
10272
 BASE_256KBBASE_256KB 0x00040000 Base.h 　
10273
 BASE_512KBBASE_512KB 0x00080000 Base.h 　
10274
 BASE_1MBBASE_1MB 0x00100000 Base.h 　
10275
 BASE_2MBBASE_2MB 0x00200000 Base.h 　
10276
 BASE_4MBBASE_4MB 0x00400000 Base.h 　
10277
 BASE_8MBBASE_8MB 0x00800000 Base.h 　
10278
 BASE_16MBBASE_16MB 0x01000000 Base.h 　
10279
 BASE_32MBBASE_32MB 0x02000000 Base.h 　
10280
 BASE_64MBBASE_64MB 0x04000000 Base.h 　
10281
 BASE_128MBBASE_128MB 0x08000000 Base.h 　
10282
 BASE_256MBBASE_256MB 0x10000000 Base.h 　
10283
 BASE_512MBBASE_512MB 0x20000000 Base.h 　
10284
 BASE_1GBBASE_1GB 0x40000000 Base.h 　
10285
 BASE_2GBBASE_2GB 0x80000000 Base.h 　
10286
 BASE_4GBBASE_4GB 0x0000000100000000ULL Base.h 　
10287
 BASE_8GBBASE_8GB 0x0000000200000000ULL Base.h 　
10288
 BASE_16GBBASE_16GB 0x0000000400000000ULL Base.h 　
10289
 BASE_32GBBASE_32GB 0x0000000800000000ULL Base.h 　
10290
 BASE_64GBBASE_64GB 0x0000001000000000ULL Base.h 　
10291
 BASE_128GBBASE_128GB 0x0000002000000000ULL Base.h 　
10292
 BASE_256GBBASE_256GB 0x0000004000000000ULL Base.h 　
10293
 BASE_512GBBASE_512GB 0x0000008000000000ULL Base.h 　
10294
 BASE_1TBBASE_1TB 0x0000010000000000ULL Base.h 　
10295
 BASE_2TBBASE_2TB 0x0000020000000000ULL Base.h 　
10296
 BASE_4TBBASE_4TB 0x0000040000000000ULL Base.h 　
10297
 BASE_8TBBASE_8TB 0x0000080000000000ULL Base.h 　
10298
 BASE_16TBBASE_16TB 0x0000100000000000ULL Base.h 　
10299
 BASE_32TBBASE_32TB 0x0000200000000000ULL Base.h 　
10300
 BASE_64TBBASE_64TB 0x0000400000000000ULL Base.h 　
10301
 BASE_128TBBASE_128TB 0x0000800000000000ULL Base.h 　
10302
 BASE_256TBBASE_256TB 0x0001000000000000ULL Base.h 　
10303
 BASE_512TBBASE_512TB 0x0002000000000000ULL Base.h 　
10304
 BASE_1PBBASE_1PB 0x0004000000000000ULL Base.h 　
10305
 BASE_2PBBASE_2PB 0x0008000000000000ULL Base.h 　
10306
 BASE_4PBBASE_4PB 0x0010000000000000ULL Base.h 　
10307
 BASE_8PBBASE_8PB 0x0020000000000000ULL Base.h 　
10308
 BASE_16PBBASE_16PB 0x0040000000000000ULL Base.h 　
10309
 BASE_32PBBASE_32PB 0x0080000000000000ULL Base.h 　
10310
 BASE_64PBBASE_64PB 0x0100000000000000ULL Base.h 　
10311
 BASE_128PBBASE_128PB 0x0200000000000000ULL Base.h 　
10312
 BASE_256PBBASE_256PB 0x0400000000000000ULL Base.h 　
10313
 BASE_512PBBASE_512PB 0x0800000000000000ULL Base.h 　
10314
 BASE_1EBBASE_1EB 0x1000000000000000ULL Base.h 　
10315
 BASE_2EBBASE_2EB 0x2000000000000000ULL Base.h 　
10316
 BASE_4EBBASE_4EB 0x4000000000000000ULL Base.h 　
10317
 BASE_8EBBASE_8EB 0x8000000000000000ULL Base.h 　
10318
 VA_LISTVA_LIST va_list Base.h 　
10319
 VA_LISTVA_LIST va_list Base.h 　
10320
 RETURN_SUCCESSRETURN_SUCCESS 0 Base.h 　
10321
 RETURN_LOAD_ERRORRETURN_LOAD_ERROR ENCODE_ERROR (1) Base.h 　
10322
 RETURN_INVALID_PARAMETERRETURN_INVALID_PARAMETER ENCODE_ERROR (2) Base.h 　
10323
 RETURN_UNSUPPORTEDRETURN_UNSUPPORTED ENCODE_ERROR (3) Base.h 　
10324
 RETURN_BAD_BUFFER_SIZERETURN_BAD_BUFFER_SIZE ENCODE_ERROR (4) Base.h 　
10325
 RETURN_BUFFER_TOO_SMALLRETURN_BUFFER_TOO_SMALL ENCODE_ERROR (5) Base.h 　
10326
 RETURN_NOT_READYRETURN_NOT_READY ENCODE_ERROR (6) Base.h 　
10327
 RETURN_DEVICE_ERRORRETURN_DEVICE_ERROR ENCODE_ERROR (7) Base.h 　
10328
 RETURN_WRITE_PROTECTEDRETURN_WRITE_PROTECTED ENCODE_ERROR (8) Base.h 　
10329
 RETURN_OUT_OF_RESOURCESRETURN_OUT_OF_RESOURCES ENCODE_ERROR (9) Base.h 　
10330
 RETURN_VOLUME_CORRUPTEDRETURN_VOLUME_CORRUPTED ENCODE_ERROR (10) Base.h 　
10331
 RETURN_VOLUME_FULLRETURN_VOLUME_FULL ENCODE_ERROR (11) Base.h 　
10332
 RETURN_NO_MEDIARETURN_NO_MEDIA ENCODE_ERROR (12) Base.h 　
10333
 RETURN_MEDIA_CHANGEDRETURN_MEDIA_CHANGED ENCODE_ERROR (13) Base.h 　
10334
 RETURN_NOT_FOUNDRETURN_NOT_FOUND ENCODE_ERROR (14) Base.h 　
10335
 RETURN_ACCESS_DENIEDRETURN_ACCESS_DENIED ENCODE_ERROR (15) Base.h 　
10336
 RETURN_NO_RESPONSERETURN_NO_RESPONSE ENCODE_ERROR (16) Base.h 　
10337
 RETURN_NO_MAPPINGRETURN_NO_MAPPING ENCODE_ERROR (17) Base.h 　
10338
 RETURN_TIMEOUTRETURN_TIMEOUT ENCODE_ERROR (18) Base.h 　
10339
 RETURN_NOT_STARTEDRETURN_NOT_STARTED ENCODE_ERROR (19) Base.h 　
10340
 RETURN_ALREADY_STARTEDRETURN_ALREADY_STARTED ENCODE_ERROR (20) Base.h 　
10341
 RETURN_ABORTEDRETURN_ABORTED ENCODE_ERROR (21) Base.h 　
10342
 RETURN_ICMP_ERRORRETURN_ICMP_ERROR ENCODE_ERROR (22) Base.h 　
10343
 RETURN_TFTP_ERRORRETURN_TFTP_ERROR ENCODE_ERROR (23) Base.h 　
10344
 RETURN_PROTOCOL_ERRORRETURN_PROTOCOL_ERROR ENCODE_ERROR (24) Base.h 　
10345
 RETURN_INCOMPATIBLE_VERSIONRETURN_INCOMPATIBLE_VERSION ENCODE_ERROR (25) Base.h 　
10346
 RETURN_SECURITY_VIOLATIONRETURN_SECURITY_VIOLATION ENCODE_ERROR (26) Base.h 　
10347
 RETURN_CRC_ERRORRETURN_CRC_ERROR ENCODE_ERROR (27) Base.h 　
10348
 RETURN_END_OF_MEDIARETURN_END_OF_MEDIA ENCODE_ERROR (28) Base.h 　
10349
 RETURN_END_OF_FILERETURN_END_OF_FILE ENCODE_ERROR (31) Base.h 　
10350
 RETURN_INVALID_LANGUAGERETURN_INVALID_LANGUAGE ENCODE_ERROR (32) Base.h 　
10351
 RETURN_WARN_UNKNOWN_GLYPHRETURN_WARN_UNKNOWN_GLYPH ENCODE_WARNING (1) Base.h 　
10352
 RETURN_WARN_DELETE_FAILURERETURN_WARN_DELETE_FAILURE ENCODE_WARNING (2) Base.h 　
10353
 RETURN_WARN_WRITE_FAILURERETURN_WARN_WRITE_FAILURE ENCODE_WARNING (3) Base.h 　
10354
 RETURN_WARN_BUFFER_TOO_SMALLRETURN_WARN_BUFFER_TOO_SMALL ENCODE_WARNING (4) Base.h 　
10355
 __GNUC____GNUC__ 1 efi.h 　
10356
 EFIAPIEFIAPI __attribute__((ms_abi)) efi.h 　
10357
 EFIAPIEFIAPI __attribute__((cdecl,regparm(0))) efi.h 　
10358
 EFI_PROTOCOLSEFI_PROTOCOLS __table ( struct efi_protocol, "efi_protocols" ) efi.h 　
10359
 __efi_protocol__efi_protocol __table_entry ( EFI_PROTOCOLS, 01 ) efi.h 　
10360
 EFI_CONFIG_TABLESEFI_CONFIG_TABLES __table ( struct efi_config_table, "efi_config_tables" ) efi.h 　
10361
 __efi_config_table__efi_config_table __table_entry ( EFI_CONFIG_TABLES, 01 ) efi.h 　
10362
 IOAPI_PREFIX_efiIOAPI_PREFIX_efi __efi_ efi_io.h 　
10363
 PCIAPI_PREFIX_efiPCIAPI_PREFIX_efi __efi_ efi_pci.h 　
10364
 EFIPCI_WIDTH_BYTEEFIPCI_WIDTH_BYTE 0 efi_pci.h 　
10365
 EFIPCI_WIDTH_WORDEFIPCI_WIDTH_WORD 1 efi_pci.h 　
10366
 EFIPCI_WIDTH_DWORDEFIPCI_WIDTH_DWORD 2 efi_pci.h 　
10367
 SMBIOS_PREFIX_efiSMBIOS_PREFIX_efi __efi_ efi_smbios.h 　
10368
 TIMER_PREFIX_efiTIMER_PREFIX_efi __efi_ efi_timer.h 　
10369
 UACCESS_PREFIX_efiUACCESS_PREFIX_efi __efi_ efi_uaccess.h 　
10370
 UMALLOC_PREFIX_efiUMALLOC_PREFIX_efi __efi_ efi_umalloc.h 　
10371
 EFI_HII_STANDARD_FORM_GUIDEFI_HII_STANDARD_FORM_GUID { 0x3bd2f4ec, 0xe524, 0x46e4, { 0xa9, 0xd8, 0x51, 0x1, 0x17, 0x42, 0x55, 0x62 } } HiiFormMapMethodGuid.h 　
10372
 EFI_PC_ANSI_GUIDEFI_PC_ANSI_GUID { \ 0xe0c14753, 0xf9be, 0x11d2, {0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ } PcAnsi.h 　
10373
 EFI_VT_100_GUIDEFI_VT_100_GUID { \ 0xdfa66065, 0xb419, 0x11d3, {0x9a, 0x2d, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ } PcAnsi.h 　
10374
 EFI_VT_100_PLUS_GUIDEFI_VT_100_PLUS_GUID { \ 0x7baec70b, 0x57e0, 0x4c76, {0x8e, 0x87, 0x2f, 0x9e, 0x28, 0x08, 0x83, 0x43 } \ } PcAnsi.h 　
10375
 EFI_VT_UTF8_GUIDEFI_VT_UTF8_GUID { \ 0xad15a0d6, 0x8bec, 0x4acf, {0xa0, 0x73, 0xd0, 0x1d, 0xe7, 0x7e, 0x2d, 0x88 } \ } PcAnsi.h 　
10376
 DEVICE_PATH_MESSAGING_UART_FLOWDEVICE_PATH_MESSAGING_UART_FLOW { \ 0x37499a9d, 0x542f, 0x4c89, {0xa0, 0x26, 0x35, 0xda, 0x14, 0x20, 0x94, 0xe4 } \ } PcAnsi.h 　
10377
 EFI_SAS_DEVICE_PATH_GUIDEFI_SAS_DEVICE_PATH_GUID { \ 0xd487ddb4, 0x008b, 0x11d9, {0xaf, 0xdc, 0x00, 0x10, 0x83, 0xff, 0xca, 0x4d } \ } PcAnsi.h 　
10378
 SMBIOS_TABLE_GUIDSMBIOS_TABLE_GUID { \ 0xeb9d2d31, 0x2d88, 0x11d3, {0x9a, 0x16, 0x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ } SmBios.h 　
10379
 WIN_CERT_TYPE_PKCS_SIGNED_DATAWIN_CERT_TYPE_PKCS_SIGNED_DATA 0x0002 WinCertificate.h 　
10380
 WIN_CERT_TYPE_EFI_PKCS115WIN_CERT_TYPE_EFI_PKCS115 0x0EF0 WinCertificate.h 　
10381
 WIN_CERT_TYPE_EFI_GUIDWIN_CERT_TYPE_EFI_GUID 0x0EF1 WinCertificate.h 　
10382
 EFI_CERT_TYPE_RSA2048_SHA256_GUEFI_CERT_TYPE_RSA2048_SHA256_GU {0xa7717414, 0xc616, 0x4977, {0x94, 0x20, 0x84, 0x47, 0x12, 0xa7, 0x35, 0xbf } } WinCertificate.h 　
10383
 MAX_BITMAX_BIT 0x80000000 ProcessorBind.h 　
10384
 MAX_2_BITSMAX_2_BITS 0xC0000000 ProcessorBind.h 　
10385
 MAX_ADDRESSMAX_ADDRESS 0xFFFFFFFF ProcessorBind.h 　
10386
 CPU_STACK_ALIGNMENTCPU_STACK_ALIGNMENT sizeof(UINTN) ProcessorBind.h 　
10387
 EFIAPIEFIAPI __cdecl ProcessorBind.h 　
10388
 EFIAPIEFIAPI __attribute__((cdecl)) ProcessorBind.h 　
10389
 ASM_GLOBALASM_GLOBAL .globl ProcessorBind.h 　
10390
 PCI_MAX_BUSPCI_MAX_BUS 255 Pci22.h 　
10391
 PCI_MAX_DEVICEPCI_MAX_DEVICE 31 Pci22.h 　
10392
 PCI_MAX_FUNCPCI_MAX_FUNC 7 Pci22.h 　
10393
 PCI_CLASS_OLDPCI_CLASS_OLD 0x00 Pci22.h 　
10394
 PCI_CLASS_OLD_OTHERPCI_CLASS_OLD_OTHER 0x00 Pci22.h 　
10395
 PCI_CLASS_OLD_VGAPCI_CLASS_OLD_VGA 0x01 Pci22.h 　
10396
 PCI_CLASS_MASS_STORAGEPCI_CLASS_MASS_STORAGE 0x01 Pci22.h 　
10397
 PCI_CLASS_MASS_STORAGE_SCSIPCI_CLASS_MASS_STORAGE_SCSI 0x00 Pci22.h 　
10398
 PCI_CLASS_MASS_STORAGE_IDEPCI_CLASS_MASS_STORAGE_IDE 0x01 Pci22.h 　
10399
 PCI_CLASS_MASS_STORAGE_FLOPPYPCI_CLASS_MASS_STORAGE_FLOPPY 0x02 Pci22.h 　
10400
 PCI_CLASS_MASS_STORAGE_IPIPCI_CLASS_MASS_STORAGE_IPI 0x03 Pci22.h 　
10401
 PCI_CLASS_MASS_STORAGE_RAIDPCI_CLASS_MASS_STORAGE_RAID 0x04 Pci22.h 　
10402
 PCI_CLASS_MASS_STORAGE_OTHERPCI_CLASS_MASS_STORAGE_OTHER 0x80 Pci22.h 　
10403
 PCI_CLASS_NETWORKPCI_CLASS_NETWORK 0x02 Pci22.h 　
10404
 PCI_CLASS_NETWORK_ETHERNETPCI_CLASS_NETWORK_ETHERNET 0x00 Pci22.h 　
10405
 PCI_CLASS_NETWORK_TOKENRINGPCI_CLASS_NETWORK_TOKENRING 0x01 Pci22.h 　
10406
 PCI_CLASS_NETWORK_FDDIPCI_CLASS_NETWORK_FDDI 0x02 Pci22.h 　
10407
 PCI_CLASS_NETWORK_ATMPCI_CLASS_NETWORK_ATM 0x03 Pci22.h 　
10408
 PCI_CLASS_NETWORK_ISDNPCI_CLASS_NETWORK_ISDN 0x04 Pci22.h 　
10409
 PCI_CLASS_NETWORK_OTHERPCI_CLASS_NETWORK_OTHER 0x80 Pci22.h 　
10410
 PCI_CLASS_DISPLAYPCI_CLASS_DISPLAY 0x03 Pci22.h 　
10411
 PCI_CLASS_DISPLAY_VGAPCI_CLASS_DISPLAY_VGA 0x00 Pci22.h 　
10412
 PCI_IF_VGA_VGAPCI_IF_VGA_VGA 0x00 Pci22.h 　
10413
 PCI_IF_VGA_8514PCI_IF_VGA_8514 0x01 Pci22.h 　
10414
 PCI_CLASS_DISPLAY_XGAPCI_CLASS_DISPLAY_XGA 0x01 Pci22.h 　
10415
 PCI_CLASS_DISPLAY_3DPCI_CLASS_DISPLAY_3D 0x02 Pci22.h 　
10416
 PCI_CLASS_DISPLAY_OTHERPCI_CLASS_DISPLAY_OTHER 0x80 Pci22.h 　
10417
 PCI_CLASS_MEDIAPCI_CLASS_MEDIA 0x04 Pci22.h 　
10418
 PCI_CLASS_MEDIA_VIDEOPCI_CLASS_MEDIA_VIDEO 0x00 Pci22.h 　
10419
 PCI_CLASS_MEDIA_AUDIOPCI_CLASS_MEDIA_AUDIO 0x01 Pci22.h 　
10420
 PCI_CLASS_MEDIA_TELEPHONEPCI_CLASS_MEDIA_TELEPHONE 0x02 Pci22.h 　
10421
 PCI_CLASS_MEDIA_OTHERPCI_CLASS_MEDIA_OTHER 0x80 Pci22.h 　
10422
 PCI_CLASS_MEMORY_CONTROLLERPCI_CLASS_MEMORY_CONTROLLER 0x05 Pci22.h 　
10423
 PCI_CLASS_MEMORY_RAMPCI_CLASS_MEMORY_RAM 0x00 Pci22.h 　
10424
 PCI_CLASS_MEMORY_FLASHPCI_CLASS_MEMORY_FLASH 0x01 Pci22.h 　
10425
 PCI_CLASS_MEMORY_OTHERPCI_CLASS_MEMORY_OTHER 0x80 Pci22.h 　
10426
 PCI_CLASS_BRIDGEPCI_CLASS_BRIDGE 0x06 Pci22.h 　
10427
 PCI_CLASS_BRIDGE_HOSTPCI_CLASS_BRIDGE_HOST 0x00 Pci22.h 　
10428
 PCI_CLASS_BRIDGE_ISAPCI_CLASS_BRIDGE_ISA 0x01 Pci22.h 　
10429
 PCI_CLASS_BRIDGE_EISAPCI_CLASS_BRIDGE_EISA 0x02 Pci22.h 　
10430
 PCI_CLASS_BRIDGE_MCAPCI_CLASS_BRIDGE_MCA 0x03 Pci22.h 　
10431
 PCI_CLASS_BRIDGE_P2PPCI_CLASS_BRIDGE_P2P 0x04 Pci22.h 　
10432
 PCI_IF_BRIDGE_P2PPCI_IF_BRIDGE_P2P 0x00 Pci22.h 　
10433
 PCI_IF_BRIDGE_P2P_SUBTRACTIVEPCI_IF_BRIDGE_P2P_SUBTRACTIVE 0x01 Pci22.h 　
10434
 PCI_CLASS_BRIDGE_PCMCIAPCI_CLASS_BRIDGE_PCMCIA 0x05 Pci22.h 　
10435
 PCI_CLASS_BRIDGE_NUBUSPCI_CLASS_BRIDGE_NUBUS 0x06 Pci22.h 　
10436
 PCI_CLASS_BRIDGE_CARDBUSPCI_CLASS_BRIDGE_CARDBUS 0x07 Pci22.h 　
10437
 PCI_CLASS_BRIDGE_RACEWAYPCI_CLASS_BRIDGE_RACEWAY 0x08 Pci22.h 　
10438
 PCI_CLASS_BRIDGE_OTHERPCI_CLASS_BRIDGE_OTHER 0x80 Pci22.h 　
10439
 PCI_CLASS_BRIDGE_ISA_PDECODEPCI_CLASS_BRIDGE_ISA_PDECODE 0x80 Pci22.h 　
10440
 PCI_CLASS_SCCPCI_CLASS_SCC 0x07 Pci22.h < Simple communications controllers
10441
 PCI_SUBCLASS_SERIALPCI_SUBCLASS_SERIAL 0x00 Pci22.h 　
10442
 PCI_IF_GENERIC_XTPCI_IF_GENERIC_XT 0x00 Pci22.h 　
10443
 PCI_IF_16450PCI_IF_16450 0x01 Pci22.h 　
10444
 PCI_IF_16550PCI_IF_16550 0x02 Pci22.h 　
10445
 PCI_IF_16650PCI_IF_16650 0x03 Pci22.h 　
10446
 PCI_IF_16750PCI_IF_16750 0x04 Pci22.h 　
10447
 PCI_IF_16850PCI_IF_16850 0x05 Pci22.h 　
10448
 PCI_IF_16950PCI_IF_16950 0x06 Pci22.h 　
10449
 PCI_SUBCLASS_PARALLELPCI_SUBCLASS_PARALLEL 0x01 Pci22.h 　
10450
 PCI_IF_PARALLEL_PORTPCI_IF_PARALLEL_PORT 0x00 Pci22.h 　
10451
 PCI_IF_BI_DIR_PARALLEL_PORTPCI_IF_BI_DIR_PARALLEL_PORT 0x01 Pci22.h 　
10452
 PCI_IF_ECP_PARALLEL_PORTPCI_IF_ECP_PARALLEL_PORT 0x02 Pci22.h 　
10453
 PCI_IF_1284_CONTROLLERPCI_IF_1284_CONTROLLER 0x03 Pci22.h 　
10454
 PCI_IF_1284_DEVICEPCI_IF_1284_DEVICE 0xFE Pci22.h 　
10455
 PCI_SUBCLASS_MULTIPORT_SERIALPCI_SUBCLASS_MULTIPORT_SERIAL 0x02 Pci22.h 　
10456
 PCI_SUBCLASS_MODEMPCI_SUBCLASS_MODEM 0x03 Pci22.h 　
10457
 PCI_IF_GENERIC_MODEMPCI_IF_GENERIC_MODEM 0x00 Pci22.h 　
10458
 PCI_IF_16450_MODEMPCI_IF_16450_MODEM 0x01 Pci22.h 　
10459
 PCI_IF_16550_MODEMPCI_IF_16550_MODEM 0x02 Pci22.h 　
10460
 PCI_IF_16650_MODEMPCI_IF_16650_MODEM 0x03 Pci22.h 　
10461
 PCI_IF_16750_MODEMPCI_IF_16750_MODEM 0x04 Pci22.h 　
10462
 PCI_SUBCLASS_SCC_OTHERPCI_SUBCLASS_SCC_OTHER 0x80 Pci22.h 　
10463
 PCI_CLASS_SYSTEM_PERIPHERALPCI_CLASS_SYSTEM_PERIPHERAL 0x08 Pci22.h 　
10464
 PCI_SUBCLASS_PICPCI_SUBCLASS_PIC 0x00 Pci22.h 　
10465
 PCI_IF_8259_PICPCI_IF_8259_PIC 0x00 Pci22.h 　
10466
 PCI_IF_ISA_PICPCI_IF_ISA_PIC 0x01 Pci22.h 　
10467
 PCI_IF_EISA_PICPCI_IF_EISA_PIC 0x02 Pci22.h 　
10468
 PCI_IF_APIC_CONTROLLERPCI_IF_APIC_CONTROLLER 0x10 Pci22.h < I/O APIC interrupt controller , 32 bye none-prefectable memory.
10469
 PCI_IF_APIC_CONTROLLER2PCI_IF_APIC_CONTROLLER2 0x20 Pci22.h 　
10470
 PCI_SUBCLASS_DMAPCI_SUBCLASS_DMA 0x01 Pci22.h 　
10471
 PCI_IF_8237_DMAPCI_IF_8237_DMA 0x00 Pci22.h 　
10472
 PCI_IF_ISA_DMAPCI_IF_ISA_DMA 0x01 Pci22.h 　
10473
 PCI_IF_EISA_DMAPCI_IF_EISA_DMA 0x02 Pci22.h 　
10474
 PCI_SUBCLASS_TIMERPCI_SUBCLASS_TIMER 0x02 Pci22.h 　
10475
 PCI_IF_8254_TIMERPCI_IF_8254_TIMER 0x00 Pci22.h 　
10476
 PCI_IF_ISA_TIMERPCI_IF_ISA_TIMER 0x01 Pci22.h 　
10477
 PCI_IF_EISA_TIMERPCI_IF_EISA_TIMER 0x02 Pci22.h 　
10478
 PCI_SUBCLASS_RTCPCI_SUBCLASS_RTC 0x03 Pci22.h 　
10479
 PCI_IF_GENERIC_RTCPCI_IF_GENERIC_RTC 0x00 Pci22.h 　
10480
 PCI_IF_ISA_RTCPCI_IF_ISA_RTC 0x00 Pci22.h 　
10481
 PCI_SUBCLASS_PNP_CONTROLLERPCI_SUBCLASS_PNP_CONTROLLER 0x04 Pci22.h < HotPlug Controller
10482
 PCI_SUBCLASS_PERIPHERAL_OTHERPCI_SUBCLASS_PERIPHERAL_OTHER 0x80 Pci22.h 　
10483
 PCI_CLASS_INPUT_DEVICEPCI_CLASS_INPUT_DEVICE 0x09 Pci22.h 　
10484
 PCI_SUBCLASS_KEYBOARDPCI_SUBCLASS_KEYBOARD 0x00 Pci22.h 　
10485
 PCI_SUBCLASS_PENPCI_SUBCLASS_PEN 0x01 Pci22.h 　
10486
 PCI_SUBCLASS_MOUSE_CONTROLLERPCI_SUBCLASS_MOUSE_CONTROLLER 0x02 Pci22.h 　
10487
 PCI_SUBCLASS_SCAN_CONTROLLERPCI_SUBCLASS_SCAN_CONTROLLER 0x03 Pci22.h 　
10488
 PCI_SUBCLASS_GAMEPORTPCI_SUBCLASS_GAMEPORT 0x04 Pci22.h 　
10489
 PCI_IF_GAMEPORTPCI_IF_GAMEPORT 0x00 Pci22.h 　
10490
 PCI_IF_GAMEPORT1PCI_IF_GAMEPORT1 0x01 Pci22.h 　
10491
 PCI_SUBCLASS_INPUT_OTHERPCI_SUBCLASS_INPUT_OTHER 0x80 Pci22.h 　
10492
 PCI_CLASS_DOCKING_STATIONPCI_CLASS_DOCKING_STATION 0x0A Pci22.h 　
10493
 PCI_CLASS_PROCESSORPCI_CLASS_PROCESSOR 0x0B Pci22.h 　
10494
 PCI_SUBCLASS_PROC_386PCI_SUBCLASS_PROC_386 0x00 Pci22.h 　
10495
 PCI_SUBCLASS_PROC_486PCI_SUBCLASS_PROC_486 0x01 Pci22.h 　
10496
 PCI_SUBCLASS_PROC_PENTIUMPCI_SUBCLASS_PROC_PENTIUM 0x02 Pci22.h 　
10497
 PCI_SUBCLASS_PROC_ALPHAPCI_SUBCLASS_PROC_ALPHA 0x10 Pci22.h 　
10498
 PCI_SUBCLASS_PROC_POWERPCPCI_SUBCLASS_PROC_POWERPC 0x20 Pci22.h 　
10499
 PCI_SUBCLASS_PROC_MIPSPCI_SUBCLASS_PROC_MIPS 0x30 Pci22.h 　
10500
 PCI_SUBCLASS_PROC_CO_PORCPCI_SUBCLASS_PROC_CO_PORC 0x40 Pci22.h < Co-Processor
10501
 PCI_CLASS_SERIALPCI_CLASS_SERIAL 0x0C Pci22.h 　
10502
 PCI_CLASS_SERIAL_FIREWIREPCI_CLASS_SERIAL_FIREWIRE 0x00 Pci22.h 　
10503
 PCI_IF_1394PCI_IF_1394 0x00 Pci22.h 　
10504
 PCI_IF_1394_OPEN_HCIPCI_IF_1394_OPEN_HCI 0x10 Pci22.h 　
10505
 PCI_CLASS_SERIAL_ACCESS_BUSPCI_CLASS_SERIAL_ACCESS_BUS 0x01 Pci22.h 　
10506
 PCI_CLASS_SERIAL_SSAPCI_CLASS_SERIAL_SSA 0x02 Pci22.h 　
10507
 PCI_CLASS_SERIAL_USBPCI_CLASS_SERIAL_USB 0x03 Pci22.h 　
10508
 PCI_IF_UHCIPCI_IF_UHCI 0x00 Pci22.h 　
10509
 PCI_IF_OHCIPCI_IF_OHCI 0x10 Pci22.h 　
10510
 PCI_IF_USB_OTHERPCI_IF_USB_OTHER 0x80 Pci22.h 　
10511
 PCI_IF_USB_DEVICEPCI_IF_USB_DEVICE 0xFE Pci22.h 　
10512
 PCI_CLASS_SERIAL_FIBRECHANNELPCI_CLASS_SERIAL_FIBRECHANNEL 0x04 Pci22.h 　
10513
 PCI_CLASS_SERIAL_SMBPCI_CLASS_SERIAL_SMB 0x05 Pci22.h 　
10514
 PCI_CLASS_WIRELESSPCI_CLASS_WIRELESS 0x0D Pci22.h 　
10515
 PCI_SUBCLASS_IRDAPCI_SUBCLASS_IRDA 0x00 Pci22.h 　
10516
 PCI_SUBCLASS_IRPCI_SUBCLASS_IR 0x01 Pci22.h 　
10517
 PCI_SUBCLASS_RFPCI_SUBCLASS_RF 0x02 Pci22.h 　
10518
 PCI_SUBCLASS_WIRELESS_OTHERPCI_SUBCLASS_WIRELESS_OTHER 0x80 Pci22.h 　
10519
 PCI_CLASS_INTELLIGENT_IOPCI_CLASS_INTELLIGENT_IO 0x0E Pci22.h 　
10520
 PCI_CLASS_SATELLITEPCI_CLASS_SATELLITE 0x0F Pci22.h 　
10521
 PCI_SUBCLASS_TVPCI_SUBCLASS_TV 0x01 Pci22.h 　
10522
 PCI_SUBCLASS_AUDIOPCI_SUBCLASS_AUDIO 0x02 Pci22.h 　
10523
 PCI_SUBCLASS_VOICEPCI_SUBCLASS_VOICE 0x03 Pci22.h 　
10524
 PCI_SUBCLASS_DATAPCI_SUBCLASS_DATA 0x04 Pci22.h 　
10525
 PCI_SECURITY_CONTROLLERPCI_SECURITY_CONTROLLER 0x10 Pci22.h < Encryption and decryption controller
10526
 PCI_SUBCLASS_NET_COMPUTPCI_SUBCLASS_NET_COMPUT 0x00 Pci22.h 　
10527
 PCI_SUBCLASS_ENTERTAINMENTPCI_SUBCLASS_ENTERTAINMENT 0x10 Pci22.h 　
10528
 PCI_SUBCLASS_SECURITY_OTHERPCI_SUBCLASS_SECURITY_OTHER 0x80 Pci22.h 　
10529
 PCI_CLASS_DPIOPCI_CLASS_DPIO 0x11 Pci22.h 　
10530
 PCI_SUBCLASS_DPIOPCI_SUBCLASS_DPIO 0x00 Pci22.h 　
10531
 PCI_SUBCLASS_DPIO_OTHERPCI_SUBCLASS_DPIO_OTHER 0x80 Pci22.h 　
10532
 HEADER_TYPE_DEVICEHEADER_TYPE_DEVICE 0x00 Pci22.h 　
10533
 HEADER_TYPE_PCI_TO_PCI_BRIDGEHEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01 Pci22.h 　
10534
 HEADER_TYPE_CARDBUS_BRIDGEHEADER_TYPE_CARDBUS_BRIDGE 0x02 Pci22.h 　
10535
 HEADER_TYPE_MULTI_FUNCTIONHEADER_TYPE_MULTI_FUNCTION 0x80 Pci22.h 　
10536
 HEADER_LAYOUT_CODEHEADER_LAYOUT_CODE 0x7f Pci22.h 　
10537
 PCI_BRIDGE_ROMBARPCI_BRIDGE_ROMBAR 0x38 Pci22.h 　
10538
 PCI_MAX_BARPCI_MAX_BAR 0x0006 Pci22.h 　
10539
 PCI_MAX_CONFIG_OFFSETPCI_MAX_CONFIG_OFFSET 0x0100 Pci22.h 　
10540
 PCI_VENDOR_ID_OFFSETPCI_VENDOR_ID_OFFSET 0x00 Pci22.h 　
10541
 PCI_DEVICE_ID_OFFSETPCI_DEVICE_ID_OFFSET 0x02 Pci22.h 　
10542
 PCI_COMMAND_OFFSETPCI_COMMAND_OFFSET 0x04 Pci22.h 　
10543
 PCI_PRIMARY_STATUS_OFFSETPCI_PRIMARY_STATUS_OFFSET 0x06 Pci22.h 　
10544
 PCI_REVISION_ID_OFFSETPCI_REVISION_ID_OFFSET 0x08 Pci22.h 　
10545
 PCI_CLASSCODE_OFFSETPCI_CLASSCODE_OFFSET 0x09 Pci22.h 　
10546
 PCI_CACHELINE_SIZE_OFFSETPCI_CACHELINE_SIZE_OFFSET 0x0C Pci22.h 　
10547
 PCI_LATENCY_TIMER_OFFSETPCI_LATENCY_TIMER_OFFSET 0x0D Pci22.h 　
10548
 PCI_HEADER_TYPE_OFFSETPCI_HEADER_TYPE_OFFSET 0x0E Pci22.h 　
10549
 PCI_BIST_OFFSETPCI_BIST_OFFSET 0x0F Pci22.h 　
10550
 PCI_BASE_ADDRESSREG_OFFSETPCI_BASE_ADDRESSREG_OFFSET 0x10 Pci22.h 　
10551
 PCI_CARDBUS_CIS_OFFSETPCI_CARDBUS_CIS_OFFSET 0x28 Pci22.h 　
10552
 PCI_SVID_OFFSETPCI_SVID_OFFSET 0x2C Pci22.h < SubSystem Vendor id
10553
 PCI_SUBSYSTEM_VENDOR_ID_OFFSETPCI_SUBSYSTEM_VENDOR_ID_OFFSET 0x2C Pci22.h 　
10554
 PCI_SID_OFFSETPCI_SID_OFFSET 0x2E Pci22.h < SubSystem ID
10555
 PCI_SUBSYSTEM_ID_OFFSETPCI_SUBSYSTEM_ID_OFFSET 0x2E Pci22.h 　
10556
 PCI_EXPANSION_ROM_BASEPCI_EXPANSION_ROM_BASE 0x30 Pci22.h 　
10557
 PCI_CAPBILITY_POINTER_OFFSETPCI_CAPBILITY_POINTER_OFFSET 0x34 Pci22.h 　
10558
 PCI_INT_LINE_OFFSETPCI_INT_LINE_OFFSET 0x3C Pci22.h < Interrupt Line Register
10559
 PCI_INT_PIN_OFFSETPCI_INT_PIN_OFFSET 0x3D Pci22.h < Interrupt Pin Register
10560
 PCI_MAXGNT_OFFSETPCI_MAXGNT_OFFSET 0x3E Pci22.h < Max Grant Register
10561
 PCI_MAXLAT_OFFSETPCI_MAXLAT_OFFSET 0x3F Pci22.h < Max Latency Register
10562
 PCI_BRIDGE_PRIMARY_BUS_REGISTERPCI_BRIDGE_PRIMARY_BUS_REGISTER 0x18 Pci22.h 　
10563
 PCI_BRIDGE_SECONDARY_BUS_REGISTPCI_BRIDGE_SECONDARY_BUS_REGIST 0x19 Pci22.h 　
10564
 PCI_BRIDGE_SUBORDINATE_BUS_REGIPCI_BRIDGE_SUBORDINATE_BUS_REGI 0x1a Pci22.h 　
10565
 PCI_BRIDGE_STATUS_REGISTER_OFFSPCI_BRIDGE_STATUS_REGISTER_OFFS 0x1E Pci22.h 　
10566
 PCI_BRIDGE_CONTROL_REGISTER_OFFPCI_BRIDGE_CONTROL_REGISTER_OFF 0x3E Pci22.h 　
10567
 PCI_INT_LINE_UNKNOWNPCI_INT_LINE_UNKNOWN 0xFF Pci22.h 　
10568
 EFI_PCI_COMMAND_IO_SPACEEFI_PCI_COMMAND_IO_SPACE BIT0 Pci22.h < 0x0001
10569
 EFI_PCI_COMMAND_MEMORY_SPACEEFI_PCI_COMMAND_MEMORY_SPACE BIT1 Pci22.h < 0x0002
10570
 EFI_PCI_COMMAND_BUS_MASTEREFI_PCI_COMMAND_BUS_MASTER BIT2 Pci22.h < 0x0004
10571
 EFI_PCI_COMMAND_SPECIAL_CYCLEEFI_PCI_COMMAND_SPECIAL_CYCLE BIT3 Pci22.h < 0x0008
10572
 EFI_PCI_COMMAND_MEMORY_WRITE_ANEFI_PCI_COMMAND_MEMORY_WRITE_AN BIT4 Pci22.h < 0x0010
10573
 EFI_PCI_COMMAND_VGA_PALETTE_SNOEFI_PCI_COMMAND_VGA_PALETTE_SNO BIT5 Pci22.h < 0x0020
10574
 EFI_PCI_COMMAND_PARITY_ERROR_REEFI_PCI_COMMAND_PARITY_ERROR_RE BIT6 Pci22.h < 0x0040
10575
 EFI_PCI_COMMAND_STEPPING_CONTROEFI_PCI_COMMAND_STEPPING_CONTRO BIT7 Pci22.h < 0x0080
10576
 EFI_PCI_COMMAND_SERREFI_PCI_COMMAND_SERR BIT8 Pci22.h < 0x0100
10577
 EFI_PCI_COMMAND_FAST_BACK_TO_BAEFI_PCI_COMMAND_FAST_BACK_TO_BA BIT9 Pci22.h < 0x0200
10578
 EFI_PCI_BRIDGE_CONTROL_PARITY_EEFI_PCI_BRIDGE_CONTROL_PARITY_E BIT0 Pci22.h < 0x0001
10579
 EFI_PCI_BRIDGE_CONTROL_SERREFI_PCI_BRIDGE_CONTROL_SERR BIT1 Pci22.h < 0x0002
10580
 EFI_PCI_BRIDGE_CONTROL_ISAEFI_PCI_BRIDGE_CONTROL_ISA BIT2 Pci22.h < 0x0004
10581
 EFI_PCI_BRIDGE_CONTROL_VGAEFI_PCI_BRIDGE_CONTROL_VGA BIT3 Pci22.h < 0x0008
10582
 EFI_PCI_BRIDGE_CONTROL_VGA_16EFI_PCI_BRIDGE_CONTROL_VGA_16 BIT4 Pci22.h < 0x0010
10583
 EFI_PCI_BRIDGE_CONTROL_MASTER_AEFI_PCI_BRIDGE_CONTROL_MASTER_A BIT5 Pci22.h < 0x0020
10584
 EFI_PCI_BRIDGE_CONTROL_RESET_SEEFI_PCI_BRIDGE_CONTROL_RESET_SE BIT6 Pci22.h < 0x0040
10585
 EFI_PCI_BRIDGE_CONTROL_FAST_BACEFI_PCI_BRIDGE_CONTROL_FAST_BAC BIT7 Pci22.h < 0x0080
10586
 EFI_PCI_BRIDGE_CONTROL_PRIMARY_EFI_PCI_BRIDGE_CONTROL_PRIMARY_ BIT8 Pci22.h < 0x0100
10587
 EFI_PCI_BRIDGE_CONTROL_SECONDAREFI_PCI_BRIDGE_CONTROL_SECONDAR BIT9 Pci22.h < 0x0200
10588
 EFI_PCI_BRIDGE_CONTROL_TIMER_STEFI_PCI_BRIDGE_CONTROL_TIMER_ST BIT10 Pci22.h < 0x0400
10589
 EFI_PCI_BRIDGE_CONTROL_DISCARD_EFI_PCI_BRIDGE_CONTROL_DISCARD_ BIT11 Pci22.h < 0x0800
10590
 EFI_PCI_BRIDGE_CONTROL_IREQINT_EFI_PCI_BRIDGE_CONTROL_IREQINT_ BIT7 Pci22.h < 0x0080
10591
 EFI_PCI_BRIDGE_CONTROL_RANGE0_MEFI_PCI_BRIDGE_CONTROL_RANGE0_M BIT8 Pci22.h < 0x0100
10592
 EFI_PCI_BRIDGE_CONTROL_RANGE1_MEFI_PCI_BRIDGE_CONTROL_RANGE1_M BIT9 Pci22.h < 0x0200
10593
 EFI_PCI_BRIDGE_CONTROL_WRITE_POEFI_PCI_BRIDGE_CONTROL_WRITE_PO BIT10 Pci22.h < 0x0400
10594
 EFI_PCI_STATUS_CAPABILITYEFI_PCI_STATUS_CAPABILITY BIT4 Pci22.h < 0x0010
10595
 EFI_PCI_STATUS_66MZ_CAPABLEEFI_PCI_STATUS_66MZ_CAPABLE BIT5 Pci22.h < 0x0020
10596
 EFI_PCI_FAST_BACK_TO_BACK_CAPABEFI_PCI_FAST_BACK_TO_BACK_CAPAB BIT7 Pci22.h < 0x0080
10597
 EFI_PCI_MASTER_DATA_PARITY_ERROEFI_PCI_MASTER_DATA_PARITY_ERRO BIT8 Pci22.h < 0x0100
10598
 EFI_PCI_CARDBUS_BRIDGE_CAPABILIEFI_PCI_CARDBUS_BRIDGE_CAPABILI 0x14 Pci22.h 　
10599
 EFI_PCI_CAPABILITY_ID_PMIEFI_PCI_CAPABILITY_ID_PMI 0x01 Pci22.h 　
10600
 EFI_PCI_CAPABILITY_ID_AGPEFI_PCI_CAPABILITY_ID_AGP 0x02 Pci22.h 　
10601
 EFI_PCI_CAPABILITY_ID_VPDEFI_PCI_CAPABILITY_ID_VPD 0x03 Pci22.h 　
10602
 EFI_PCI_CAPABILITY_ID_SLOTIDEFI_PCI_CAPABILITY_ID_SLOTID 0x04 Pci22.h 　
10603
 EFI_PCI_CAPABILITY_ID_MSIEFI_PCI_CAPABILITY_ID_MSI 0x05 Pci22.h 　
10604
 EFI_PCI_CAPABILITY_ID_HOTPLUGEFI_PCI_CAPABILITY_ID_HOTPLUG 0x06 Pci22.h 　
10605
 DEVICE_ID_NOCAREDEVICE_ID_NOCARE 0xFFFF Pci22.h 　
10606
 PCI_ACPI_UNUSEDPCI_ACPI_UNUSED 0 Pci22.h 　
10607
 PCI_BAR_NOCHANGEPCI_BAR_NOCHANGE 0 Pci22.h 　
10608
 PCI_BAR_OLD_ALIGNPCI_BAR_OLD_ALIGN 0xFFFFFFFFFFFFFFFFULL Pci22.h 　
10609
 PCI_BAR_EVEN_ALIGNPCI_BAR_EVEN_ALIGN 0xFFFFFFFFFFFFFFFEULL Pci22.h 　
10610
 PCI_BAR_SQUAD_ALIGNPCI_BAR_SQUAD_ALIGN 0xFFFFFFFFFFFFFFFDULL Pci22.h 　
10611
 PCI_BAR_DQUAD_ALIGNPCI_BAR_DQUAD_ALIGN 0xFFFFFFFFFFFFFFFCULL Pci22.h 　
10612
 PCI_BAR_IDX0PCI_BAR_IDX0 0x00 Pci22.h 　
10613
 PCI_BAR_IDX1PCI_BAR_IDX1 0x01 Pci22.h 　
10614
 PCI_BAR_IDX2PCI_BAR_IDX2 0x02 Pci22.h 　
10615
 PCI_BAR_IDX3PCI_BAR_IDX3 0x03 Pci22.h 　
10616
 PCI_BAR_IDX4PCI_BAR_IDX4 0x04 Pci22.h 　
10617
 PCI_BAR_IDX5PCI_BAR_IDX5 0x05 Pci22.h 　
10618
 PCI_BAR_ALLPCI_BAR_ALL 0xFF Pci22.h 　
10619
 EFI_ROOT_BRIDGE_LISTEFI_ROOT_BRIDGE_LIST 'eprb' Pci22.h 　
10620
 EFI_PCI_EXPANSION_ROM_HEADER_EFEFI_PCI_EXPANSION_ROM_HEADER_EF 0x0EF1 Pci22.h < defined in UEFI Spec.
10621
 PCI_EXPANSION_ROM_HEADER_SIGNATPCI_EXPANSION_ROM_HEADER_SIGNAT 0xaa55 Pci22.h 　
10622
 PCI_DATA_STRUCTURE_SIGNATUREPCI_DATA_STRUCTURE_SIGNATURE SIGNATURE_32 ('P', 'C', 'I', 'R') Pci22.h 　
10623
 PCI_CODE_TYPE_PCAT_IMAGEPCI_CODE_TYPE_PCAT_IMAGE 0x00 Pci22.h 　
10624
 EFI_PCI_EXPANSION_ROM_HEADER_COEFI_PCI_EXPANSION_ROM_HEADER_CO 0x0001 Pci22.h < defined in UEFI spec.
10625
 EFI_IMAGE_SUBSYSTEM_EFI_APPLICAEFI_IMAGE_SUBSYSTEM_EFI_APPLICA 10 PeImage.h 　
10626
 EFI_IMAGE_SUBSYSTEM_EFI_BOOT_SEEFI_IMAGE_SUBSYSTEM_EFI_BOOT_SE 11 PeImage.h 　
10627
 EFI_IMAGE_SUBSYSTEM_EFI_RUNTIMEEFI_IMAGE_SUBSYSTEM_EFI_RUNTIME 12 PeImage.h 　
10628
 EFI_IMAGE_SUBSYSTEM_SAL_RUNTIMEEFI_IMAGE_SUBSYSTEM_SAL_RUNTIME 13 PeImage.h < defined PI Specification, 1.0
10629
 IMAGE_FILE_MACHINE_I386IMAGE_FILE_MACHINE_I386 0x014c PeImage.h 　
10630
 IMAGE_FILE_MACHINE_IA64IMAGE_FILE_MACHINE_IA64 0x0200 PeImage.h 　
10631
 IMAGE_FILE_MACHINE_EBCIMAGE_FILE_MACHINE_EBC 0x0EBC PeImage.h 　
10632
 IMAGE_FILE_MACHINE_X64IMAGE_FILE_MACHINE_X64 0x8664 PeImage.h 　
10633
 IMAGE_FILE_MACHINE_ARMTHUMB_MIXIMAGE_FILE_MACHINE_ARMTHUMB_MIX 0x01c2 PeImage.h 　
10634
 EFI_IMAGE_DOS_SIGNATUREEFI_IMAGE_DOS_SIGNATURE SIGNATURE_16('M', 'Z') PeImage.h 　
10635
 EFI_IMAGE_OS2_SIGNATUREEFI_IMAGE_OS2_SIGNATURE SIGNATURE_16('N', 'E') PeImage.h 　
10636
 EFI_IMAGE_OS2_SIGNATURE_LEEFI_IMAGE_OS2_SIGNATURE_LE SIGNATURE_16('L', 'E') PeImage.h 　
10637
 EFI_IMAGE_NT_SIGNATUREEFI_IMAGE_NT_SIGNATURE SIGNATURE_32('P', 'E', '\0', '\0') PeImage.h 　
10638
 EFI_IMAGE_SIZEOF_FILE_HEADEREFI_IMAGE_SIZEOF_FILE_HEADER 20 PeImage.h 　
10639
 EFI_IMAGE_FILE_RELOCS_STRIPPEDEFI_IMAGE_FILE_RELOCS_STRIPPED BIT0 PeImage.h < 0x0001 Relocation info stripped from file.
10640
 EFI_IMAGE_FILE_EXECUTABLE_IMAGEEFI_IMAGE_FILE_EXECUTABLE_IMAGE BIT1 PeImage.h < 0x0002 File is executable (i.e. no unresolved externel references).
10641
 EFI_IMAGE_FILE_LINE_NUMS_STRIPPEFI_IMAGE_FILE_LINE_NUMS_STRIPP BIT2 PeImage.h < 0x0004 Line nunbers stripped from file.
10642
 EFI_IMAGE_FILE_LOCAL_SYMS_STRIPEFI_IMAGE_FILE_LOCAL_SYMS_STRIP BIT3 PeImage.h < 0x0008 Local symbols stripped from file.
10643
 EFI_IMAGE_FILE_BYTES_REVERSED_LEFI_IMAGE_FILE_BYTES_REVERSED_L BIT7 PeImage.h < 0x0080 Bytes of machine word are reversed.
10644
 EFI_IMAGE_FILE_32BIT_MACHINEEFI_IMAGE_FILE_32BIT_MACHINE BIT8 PeImage.h < 0x0100 32 bit word machine.
10645
 EFI_IMAGE_FILE_DEBUG_STRIPPEDEFI_IMAGE_FILE_DEBUG_STRIPPED BIT9 PeImage.h < 0x0200 Debugging info stripped from file in .DBG file.
10646
 EFI_IMAGE_FILE_SYSTEMEFI_IMAGE_FILE_SYSTEM BIT12 PeImage.h < 0x1000 System File.
10647
 EFI_IMAGE_FILE_DLLEFI_IMAGE_FILE_DLL BIT13 PeImage.h < 0x2000 File is a DLL.
10648
 EFI_IMAGE_FILE_BYTES_REVERSED_HEFI_IMAGE_FILE_BYTES_REVERSED_H BIT15 PeImage.h < 0x8000 Bytes of machine word are reversed.
10649
 EFI_IMAGE_DIRECTORY_ENTRY_EXPOREFI_IMAGE_DIRECTORY_ENTRY_EXPOR 0 PeImage.h 　
10650
 EFI_IMAGE_DIRECTORY_ENTRY_IMPOREFI_IMAGE_DIRECTORY_ENTRY_IMPOR 1 PeImage.h 　
10651
 EFI_IMAGE_DIRECTORY_ENTRY_RESOUEFI_IMAGE_DIRECTORY_ENTRY_RESOU 2 PeImage.h 　
10652
 EFI_IMAGE_DIRECTORY_ENTRY_EXCEPEFI_IMAGE_DIRECTORY_ENTRY_EXCEP 3 PeImage.h 　
10653
 EFI_IMAGE_DIRECTORY_ENTRY_SECUREFI_IMAGE_DIRECTORY_ENTRY_SECUR 4 PeImage.h 　
10654
 EFI_IMAGE_DIRECTORY_ENTRY_BASEREFI_IMAGE_DIRECTORY_ENTRY_BASER 5 PeImage.h 　
10655
 EFI_IMAGE_DIRECTORY_ENTRY_DEBUGEFI_IMAGE_DIRECTORY_ENTRY_DEBUG 6 PeImage.h 　
10656
 EFI_IMAGE_DIRECTORY_ENTRY_COPYREFI_IMAGE_DIRECTORY_ENTRY_COPYR 7 PeImage.h 　
10657
 EFI_IMAGE_DIRECTORY_ENTRY_GLOBAEFI_IMAGE_DIRECTORY_ENTRY_GLOBA 8 PeImage.h 　
10658
 EFI_IMAGE_DIRECTORY_ENTRY_TLSEFI_IMAGE_DIRECTORY_ENTRY_TLS 9 PeImage.h 　
10659
 EFI_IMAGE_DIRECTORY_ENTRY_LOAD_EFI_IMAGE_DIRECTORY_ENTRY_LOAD_ 10 PeImage.h 　
10660
 EFI_IMAGE_NUMBER_OF_DIRECTORY_EEFI_IMAGE_NUMBER_OF_DIRECTORY_E 16 PeImage.h 　
10661
 EFI_IMAGE_NT_OPTIONAL_HDR32_MAGEFI_IMAGE_NT_OPTIONAL_HDR32_MAG 0x10b PeImage.h 　
10662
 EFI_IMAGE_NT_OPTIONAL_HDR64_MAGEFI_IMAGE_NT_OPTIONAL_HDR64_MAG 0x20b PeImage.h 　
10663
 EFI_IMAGE_SIZEOF_NT_OPTIONAL32_EFI_IMAGE_SIZEOF_NT_OPTIONAL32_ sizeof (EFI_IMAGE_NT_HEADERS32) PeImage.h 　
10664
 EFI_IMAGE_SIZEOF_NT_OPTIONAL64_EFI_IMAGE_SIZEOF_NT_OPTIONAL64_ sizeof (EFI_IMAGE_NT_HEADERS64) PeImage.h 　
10665
 EFI_IMAGE_SUBSYSTEM_UNKNOWNEFI_IMAGE_SUBSYSTEM_UNKNOWN 0 PeImage.h 　
10666
 EFI_IMAGE_SUBSYSTEM_NATIVEEFI_IMAGE_SUBSYSTEM_NATIVE 1 PeImage.h 　
10667
 EFI_IMAGE_SUBSYSTEM_WINDOWS_GUIEFI_IMAGE_SUBSYSTEM_WINDOWS_GUI 2 PeImage.h 　
10668
 EFI_IMAGE_SUBSYSTEM_WINDOWS_CUIEFI_IMAGE_SUBSYSTEM_WINDOWS_CUI 3 PeImage.h 　
10669
 EFI_IMAGE_SUBSYSTEM_OS2_CUIEFI_IMAGE_SUBSYSTEM_OS2_CUI 5 PeImage.h 　
10670
 EFI_IMAGE_SUBSYSTEM_POSIX_CUIEFI_IMAGE_SUBSYSTEM_POSIX_CUI 7 PeImage.h 　
10671
 EFI_IMAGE_SIZEOF_SHORT_NAMEEFI_IMAGE_SIZEOF_SHORT_NAME 8 PeImage.h 　
10672
 EFI_IMAGE_SIZEOF_SECTION_HEADEREFI_IMAGE_SIZEOF_SECTION_HEADER 40 PeImage.h 　
10673
 EFI_IMAGE_SCN_TYPE_NO_PADEFI_IMAGE_SCN_TYPE_NO_PAD BIT3 PeImage.h < 0x00000008 ///< Reserved.
10674
 EFI_IMAGE_SCN_CNT_CODEEFI_IMAGE_SCN_CNT_CODE BIT5 PeImage.h < 0x00000020
10675
 EFI_IMAGE_SCN_CNT_INITIALIZED_DEFI_IMAGE_SCN_CNT_INITIALIZED_D BIT6 PeImage.h < 0x00000040
10676
 EFI_IMAGE_SCN_CNT_UNINITIALIZEDEFI_IMAGE_SCN_CNT_UNINITIALIZED BIT7 PeImage.h < 0x00000080
10677
 EFI_IMAGE_SCN_LNK_OTHEREFI_IMAGE_SCN_LNK_OTHER BIT8 PeImage.h < 0x00000100 ///< Reserved.
10678
 EFI_IMAGE_SCN_LNK_INFOEFI_IMAGE_SCN_LNK_INFO BIT9 PeImage.h < 0x00000200 ///< Section contains comments or some other type of information.
10679
 EFI_IMAGE_SCN_LNK_REMOVEEFI_IMAGE_SCN_LNK_REMOVE BIT11 PeImage.h < 0x00000800 ///< Section contents will not become part of image.
10680
 EFI_IMAGE_SCN_LNK_COMDATEFI_IMAGE_SCN_LNK_COMDAT BIT12 PeImage.h < 0x00001000
10681
 EFI_IMAGE_SCN_ALIGN_1BYTESEFI_IMAGE_SCN_ALIGN_1BYTES BIT20 PeImage.h < 0x00100000
10682
 EFI_IMAGE_SCN_ALIGN_2BYTESEFI_IMAGE_SCN_ALIGN_2BYTES BIT21 PeImage.h < 0x00200000
10683
 EFI_IMAGE_SCN_ALIGN_4BYTESEFI_IMAGE_SCN_ALIGN_4BYTES (BIT20|BIT21) PeImage.h < 0x00300000
10684
 EFI_IMAGE_SCN_ALIGN_8BYTESEFI_IMAGE_SCN_ALIGN_8BYTES BIT22 PeImage.h < 0x00400000
10685
 EFI_IMAGE_SCN_ALIGN_16BYTESEFI_IMAGE_SCN_ALIGN_16BYTES (BIT20|BIT22) PeImage.h < 0x00500000
10686
 EFI_IMAGE_SCN_ALIGN_32BYTESEFI_IMAGE_SCN_ALIGN_32BYTES (BIT21|BIT22) PeImage.h < 0x00600000
10687
 EFI_IMAGE_SCN_ALIGN_64BYTESEFI_IMAGE_SCN_ALIGN_64BYTES (BIT20|BIT21|BIT22) PeImage.h < 0x00700000
10688
 EFI_IMAGE_SCN_MEM_DISCARDABLEEFI_IMAGE_SCN_MEM_DISCARDABLE BIT25 PeImage.h < 0x02000000
10689
 EFI_IMAGE_SCN_MEM_NOT_CACHEDEFI_IMAGE_SCN_MEM_NOT_CACHED BIT26 PeImage.h < 0x04000000
10690
 EFI_IMAGE_SCN_MEM_NOT_PAGEDEFI_IMAGE_SCN_MEM_NOT_PAGED BIT27 PeImage.h < 0x08000000
10691
 EFI_IMAGE_SCN_MEM_SHAREDEFI_IMAGE_SCN_MEM_SHARED BIT28 PeImage.h < 0x10000000
10692
 EFI_IMAGE_SCN_MEM_EXECUTEEFI_IMAGE_SCN_MEM_EXECUTE BIT29 PeImage.h < 0x20000000
10693
 EFI_IMAGE_SCN_MEM_READEFI_IMAGE_SCN_MEM_READ BIT30 PeImage.h < 0x40000000
10694
 EFI_IMAGE_SCN_MEM_WRITEEFI_IMAGE_SCN_MEM_WRITE BIT31 PeImage.h < 0x80000000
10695
 EFI_IMAGE_SIZEOF_SYMBOLEFI_IMAGE_SIZEOF_SYMBOL 18 PeImage.h 　
10696
 EFI_IMAGE_SYM_UNDEFINEDEFI_IMAGE_SYM_UNDEFINED (UINT16) 0 PeImage.h < Symbol is undefined or is common.
10697
 EFI_IMAGE_SYM_ABSOLUTEEFI_IMAGE_SYM_ABSOLUTE (UINT16) -1 PeImage.h < Symbol is an absolute value.
10698
 EFI_IMAGE_SYM_DEBUGEFI_IMAGE_SYM_DEBUG (UINT16) -2 PeImage.h < Symbol is a special debug item.
10699
 EFI_IMAGE_SYM_TYPE_NULLEFI_IMAGE_SYM_TYPE_NULL 0 PeImage.h < no type.
10700
 EFI_IMAGE_SYM_TYPE_VOIDEFI_IMAGE_SYM_TYPE_VOID 1 PeImage.h < no valid type.
10701
 EFI_IMAGE_SYM_TYPE_CHAREFI_IMAGE_SYM_TYPE_CHAR 2 PeImage.h < type character.
10702
 EFI_IMAGE_SYM_TYPE_SHORTEFI_IMAGE_SYM_TYPE_SHORT 3 PeImage.h < type short integer.
10703
 EFI_IMAGE_SYM_TYPE_INTEFI_IMAGE_SYM_TYPE_INT 4 PeImage.h 　
10704
 EFI_IMAGE_SYM_TYPE_LONGEFI_IMAGE_SYM_TYPE_LONG 5 PeImage.h 　
10705
 EFI_IMAGE_SYM_TYPE_FLOATEFI_IMAGE_SYM_TYPE_FLOAT 6 PeImage.h 　
10706
 EFI_IMAGE_SYM_TYPE_DOUBLEEFI_IMAGE_SYM_TYPE_DOUBLE 7 PeImage.h 　
10707
 EFI_IMAGE_SYM_TYPE_STRUCTEFI_IMAGE_SYM_TYPE_STRUCT 8 PeImage.h 　
10708
 EFI_IMAGE_SYM_TYPE_UNIONEFI_IMAGE_SYM_TYPE_UNION 9 PeImage.h 　
10709
 EFI_IMAGE_SYM_TYPE_ENUMEFI_IMAGE_SYM_TYPE_ENUM 10 PeImage.h < enumeration.
10710
 EFI_IMAGE_SYM_TYPE_MOEEFI_IMAGE_SYM_TYPE_MOE 11 PeImage.h < member of enumeration.
10711
 EFI_IMAGE_SYM_TYPE_BYTEEFI_IMAGE_SYM_TYPE_BYTE 12 PeImage.h 　
10712
 EFI_IMAGE_SYM_TYPE_WORDEFI_IMAGE_SYM_TYPE_WORD 13 PeImage.h 　
10713
 EFI_IMAGE_SYM_TYPE_UINTEFI_IMAGE_SYM_TYPE_UINT 14 PeImage.h 　
10714
 EFI_IMAGE_SYM_TYPE_DWORDEFI_IMAGE_SYM_TYPE_DWORD 15 PeImage.h 　
10715
 EFI_IMAGE_SYM_DTYPE_NULLEFI_IMAGE_SYM_DTYPE_NULL 0 PeImage.h < no derived type.
10716
 EFI_IMAGE_SYM_DTYPE_POINTEREFI_IMAGE_SYM_DTYPE_POINTER 1 PeImage.h 　
10717
 EFI_IMAGE_SYM_DTYPE_FUNCTIONEFI_IMAGE_SYM_DTYPE_FUNCTION 2 PeImage.h 　
10718
 EFI_IMAGE_SYM_DTYPE_ARRAYEFI_IMAGE_SYM_DTYPE_ARRAY 3 PeImage.h 　
10719
 EFI_IMAGE_SYM_CLASS_END_OF_FUNCEFI_IMAGE_SYM_CLASS_END_OF_FUNC ((UINT8) -1) PeImage.h 　
10720
 EFI_IMAGE_SYM_CLASS_NULLEFI_IMAGE_SYM_CLASS_NULL 0 PeImage.h 　
10721
 EFI_IMAGE_SYM_CLASS_AUTOMATICEFI_IMAGE_SYM_CLASS_AUTOMATIC 1 PeImage.h 　
10722
 EFI_IMAGE_SYM_CLASS_EXTERNALEFI_IMAGE_SYM_CLASS_EXTERNAL 2 PeImage.h 　
10723
 EFI_IMAGE_SYM_CLASS_STATICEFI_IMAGE_SYM_CLASS_STATIC 3 PeImage.h 　
10724
 EFI_IMAGE_SYM_CLASS_REGISTEREFI_IMAGE_SYM_CLASS_REGISTER 4 PeImage.h 　
10725
 EFI_IMAGE_SYM_CLASS_EXTERNAL_DEEFI_IMAGE_SYM_CLASS_EXTERNAL_DE 5 PeImage.h 　
10726
 EFI_IMAGE_SYM_CLASS_LABELEFI_IMAGE_SYM_CLASS_LABEL 6 PeImage.h 　
10727
 EFI_IMAGE_SYM_CLASS_UNDEFINED_LEFI_IMAGE_SYM_CLASS_UNDEFINED_L 7 PeImage.h 　
10728
 EFI_IMAGE_SYM_CLASS_MEMBER_OF_SEFI_IMAGE_SYM_CLASS_MEMBER_OF_S 8 PeImage.h 　
10729
 EFI_IMAGE_SYM_CLASS_ARGUMENTEFI_IMAGE_SYM_CLASS_ARGUMENT 9 PeImage.h 　
10730
 EFI_IMAGE_SYM_CLASS_STRUCT_TAGEFI_IMAGE_SYM_CLASS_STRUCT_TAG 10 PeImage.h 　
10731
 EFI_IMAGE_SYM_CLASS_MEMBER_OF_UEFI_IMAGE_SYM_CLASS_MEMBER_OF_U 11 PeImage.h 　
10732
 EFI_IMAGE_SYM_CLASS_UNION_TAGEFI_IMAGE_SYM_CLASS_UNION_TAG 12 PeImage.h 　
10733
 EFI_IMAGE_SYM_CLASS_TYPE_DEFINIEFI_IMAGE_SYM_CLASS_TYPE_DEFINI 13 PeImage.h 　
10734
 EFI_IMAGE_SYM_CLASS_UNDEFINED_SEFI_IMAGE_SYM_CLASS_UNDEFINED_S 14 PeImage.h 　
10735
 EFI_IMAGE_SYM_CLASS_ENUM_TAGEFI_IMAGE_SYM_CLASS_ENUM_TAG 15 PeImage.h 　
10736
 EFI_IMAGE_SYM_CLASS_MEMBER_OF_EEFI_IMAGE_SYM_CLASS_MEMBER_OF_E 16 PeImage.h 　
10737
 EFI_IMAGE_SYM_CLASS_REGISTER_PAEFI_IMAGE_SYM_CLASS_REGISTER_PA 17 PeImage.h 　
10738
 EFI_IMAGE_SYM_CLASS_BIT_FIELDEFI_IMAGE_SYM_CLASS_BIT_FIELD 18 PeImage.h 　
10739
 EFI_IMAGE_SYM_CLASS_BLOCKEFI_IMAGE_SYM_CLASS_BLOCK 100 PeImage.h 　
10740
 EFI_IMAGE_SYM_CLASS_FUNCTIONEFI_IMAGE_SYM_CLASS_FUNCTION 101 PeImage.h 　
10741
 EFI_IMAGE_SYM_CLASS_END_OF_STRUEFI_IMAGE_SYM_CLASS_END_OF_STRU 102 PeImage.h 　
10742
 EFI_IMAGE_SYM_CLASS_FILEEFI_IMAGE_SYM_CLASS_FILE 103 PeImage.h 　
10743
 EFI_IMAGE_SYM_CLASS_SECTIONEFI_IMAGE_SYM_CLASS_SECTION 104 PeImage.h 　
10744
 EFI_IMAGE_SYM_CLASS_WEAK_EXTERNEFI_IMAGE_SYM_CLASS_WEAK_EXTERN 105 PeImage.h 　
10745
 EFI_IMAGE_N_BTMASKEFI_IMAGE_N_BTMASK 017 PeImage.h 　
10746
 EFI_IMAGE_N_TMASKEFI_IMAGE_N_TMASK 060 PeImage.h 　
10747
 EFI_IMAGE_N_TMASK1EFI_IMAGE_N_TMASK1 0300 PeImage.h 　
10748
 EFI_IMAGE_N_TMASK2EFI_IMAGE_N_TMASK2 0360 PeImage.h 　
10749
 EFI_IMAGE_N_BTSHFTEFI_IMAGE_N_BTSHFT 4 PeImage.h 　
10750
 EFI_IMAGE_N_TSHIFTEFI_IMAGE_N_TSHIFT 2 PeImage.h 　
10751
 EFI_IMAGE_COMDAT_SELECT_NODUPLIEFI_IMAGE_COMDAT_SELECT_NODUPLI 1 PeImage.h 　
10752
 EFI_IMAGE_COMDAT_SELECT_ANYEFI_IMAGE_COMDAT_SELECT_ANY 2 PeImage.h 　
10753
 EFI_IMAGE_COMDAT_SELECT_SAME_SIEFI_IMAGE_COMDAT_SELECT_SAME_SI 3 PeImage.h 　
10754
 EFI_IMAGE_COMDAT_SELECT_EXACT_MEFI_IMAGE_COMDAT_SELECT_EXACT_M 4 PeImage.h 　
10755
 EFI_IMAGE_COMDAT_SELECT_ASSOCIAEFI_IMAGE_COMDAT_SELECT_ASSOCIA 5 PeImage.h 　
10756
 EFI_IMAGE_WEAK_EXTERN_SEARCH_NOEFI_IMAGE_WEAK_EXTERN_SEARCH_NO 1 PeImage.h 　
10757
 EFI_IMAGE_WEAK_EXTERN_SEARCH_LIEFI_IMAGE_WEAK_EXTERN_SEARCH_LI 2 PeImage.h 　
10758
 EFI_IMAGE_WEAK_EXTERN_SEARCH_ALEFI_IMAGE_WEAK_EXTERN_SEARCH_AL 3 PeImage.h 　
10759
 EFI_IMAGE_SIZEOF_RELOCATIONEFI_IMAGE_SIZEOF_RELOCATION 10 PeImage.h 　
10760
 EFI_IMAGE_REL_I386_ABSOLUTEEFI_IMAGE_REL_I386_ABSOLUTE 0x0000 PeImage.h < Reference is absolute, no relocation is necessary.
10761
 EFI_IMAGE_REL_I386_DIR16EFI_IMAGE_REL_I386_DIR16 0x0001 PeImage.h < Direct 16-bit reference to the symbols virtual address.
10762
 EFI_IMAGE_REL_I386_REL16EFI_IMAGE_REL_I386_REL16 0x0002 PeImage.h < PC-relative 16-bit reference to the symbols virtual address.
10763
 EFI_IMAGE_REL_I386_DIR32EFI_IMAGE_REL_I386_DIR32 0x0006 PeImage.h < Direct 32-bit reference to the symbols virtual address.
10764
 EFI_IMAGE_REL_I386_DIR32NBEFI_IMAGE_REL_I386_DIR32NB 0x0007 PeImage.h < Direct 32-bit reference to the symbols virtual address, base not included.
10765
 EFI_IMAGE_REL_I386_SEG12EFI_IMAGE_REL_I386_SEG12 0x0009 PeImage.h < Direct 16-bit reference to the segment-selector bits of a 32-bit virtual address.
10766
 EFI_IMAGE_REL_I386_SECTIONEFI_IMAGE_REL_I386_SECTION 0x000A PeImage.h 　
10767
 EFI_IMAGE_REL_I386_SECRELEFI_IMAGE_REL_I386_SECREL 0x000B PeImage.h 　
10768
 EFI_IMAGE_REL_I386_REL32EFI_IMAGE_REL_I386_REL32 0x0014 PeImage.h < PC-relative 32-bit reference to the symbols virtual address.
10769
 IMAGE_REL_AMD64_ABSOLUTEIMAGE_REL_AMD64_ABSOLUTE 0x0000 PeImage.h 　
10770
 IMAGE_REL_AMD64_ADDR64IMAGE_REL_AMD64_ADDR64 0x0001 PeImage.h 　
10771
 IMAGE_REL_AMD64_ADDR32IMAGE_REL_AMD64_ADDR32 0x0002 PeImage.h 　
10772
 IMAGE_REL_AMD64_ADDR32NBIMAGE_REL_AMD64_ADDR32NB 0x0003 PeImage.h 　
10773
 IMAGE_REL_AMD64_REL32IMAGE_REL_AMD64_REL32 0x0004 PeImage.h 　
10774
 IMAGE_REL_AMD64_REL32_1IMAGE_REL_AMD64_REL32_1 0x0005 PeImage.h 　
10775
 IMAGE_REL_AMD64_REL32_2IMAGE_REL_AMD64_REL32_2 0x0006 PeImage.h 　
10776
 IMAGE_REL_AMD64_REL32_3IMAGE_REL_AMD64_REL32_3 0x0007 PeImage.h 　
10777
 IMAGE_REL_AMD64_REL32_4IMAGE_REL_AMD64_REL32_4 0x0008 PeImage.h 　
10778
 IMAGE_REL_AMD64_REL32_5IMAGE_REL_AMD64_REL32_5 0x0009 PeImage.h 　
10779
 IMAGE_REL_AMD64_SECTIONIMAGE_REL_AMD64_SECTION 0x000A PeImage.h 　
10780
 IMAGE_REL_AMD64_SECRELIMAGE_REL_AMD64_SECREL 0x000B PeImage.h 　
10781
 IMAGE_REL_AMD64_SECREL7IMAGE_REL_AMD64_SECREL7 0x000C PeImage.h 　
10782
 IMAGE_REL_AMD64_TOKENIMAGE_REL_AMD64_TOKEN 0x000D PeImage.h 　
10783
 IMAGE_REL_AMD64_SREL32IMAGE_REL_AMD64_SREL32 0x000E PeImage.h 　
10784
 IMAGE_REL_AMD64_PAIRIMAGE_REL_AMD64_PAIR 0x000F PeImage.h 　
10785
 IMAGE_REL_AMD64_SSPAN32IMAGE_REL_AMD64_SSPAN32 0x0010 PeImage.h 　
10786
 EFI_IMAGE_SIZEOF_BASE_RELOCATIOEFI_IMAGE_SIZEOF_BASE_RELOCATIO 8 PeImage.h 　
10787
 EFI_IMAGE_REL_BASED_ABSOLUTEEFI_IMAGE_REL_BASED_ABSOLUTE 0 PeImage.h 　
10788
 EFI_IMAGE_REL_BASED_HIGHEFI_IMAGE_REL_BASED_HIGH 1 PeImage.h 　
10789
 EFI_IMAGE_REL_BASED_LOWEFI_IMAGE_REL_BASED_LOW 2 PeImage.h 　
10790
 EFI_IMAGE_REL_BASED_HIGHLOWEFI_IMAGE_REL_BASED_HIGHLOW 3 PeImage.h 　
10791
 EFI_IMAGE_REL_BASED_HIGHADJEFI_IMAGE_REL_BASED_HIGHADJ 4 PeImage.h 　
10792
 EFI_IMAGE_REL_BASED_MIPS_JMPADDEFI_IMAGE_REL_BASED_MIPS_JMPADD 5 PeImage.h 　
10793
 EFI_IMAGE_REL_BASED_IA64_IMM64EFI_IMAGE_REL_BASED_IA64_IMM64 9 PeImage.h 　
10794
 EFI_IMAGE_REL_BASED_MIPS_JMPADDEFI_IMAGE_REL_BASED_MIPS_JMPADD 9 PeImage.h 　
10795
 EFI_IMAGE_REL_BASED_DIR64EFI_IMAGE_REL_BASED_DIR64 10 PeImage.h 　
10796
 EFI_IMAGE_SIZEOF_LINENUMBEREFI_IMAGE_SIZEOF_LINENUMBER 6 PeImage.h 　
10797
 EFI_IMAGE_ARCHIVE_START_SIZEEFI_IMAGE_ARCHIVE_START_SIZE 8 PeImage.h 　
10798
 EFI_IMAGE_ARCHIVE_STARTEFI_IMAGE_ARCHIVE_START "!<arch>\n" PeImage.h 　
10799
 EFI_IMAGE_ARCHIVE_ENDEFI_IMAGE_ARCHIVE_END "`\n" PeImage.h 　
10800
 EFI_IMAGE_ARCHIVE_PADEFI_IMAGE_ARCHIVE_PAD "\n" PeImage.h 　
10801
 EFI_IMAGE_ARCHIVE_LINKER_MEMBEREFI_IMAGE_ARCHIVE_LINKER_MEMBER "/ " PeImage.h 　
10802
 EFI_IMAGE_ARCHIVE_LONGNAMES_MEMEFI_IMAGE_ARCHIVE_LONGNAMES_MEM "// " PeImage.h 　
10803
 EFI_IMAGE_SIZEOF_ARCHIVE_MEMBEREFI_IMAGE_SIZEOF_ARCHIVE_MEMBER 60 PeImage.h 　
10804
 EFI_IMAGE_ORDINAL_FLAGEFI_IMAGE_ORDINAL_FLAG BIT31 PeImage.h < Flag for PE32.
10805
 EFI_IMAGE_DEBUG_TYPE_CODEVIEWEFI_IMAGE_DEBUG_TYPE_CODEVIEW 2 PeImage.h < The Visual C++ debug information.
10806
 CODEVIEW_SIGNATURE_NB10CODEVIEW_SIGNATURE_NB10 SIGNATURE_32('N', 'B', '1', '0') PeImage.h 　
10807
 CODEVIEW_SIGNATURE_RSDSCODEVIEW_SIGNATURE_RSDS SIGNATURE_32('R', 'S', 'D', 'S') PeImage.h 　
10808
 CODEVIEW_SIGNATURE_MTOCCODEVIEW_SIGNATURE_MTOC SIGNATURE_32('M', 'T', 'O', 'C') PeImage.h 　
10809
 EFI_TE_IMAGE_HEADER_SIGNATUREEFI_TE_IMAGE_HEADER_SIGNATURE SIGNATURE_16('V', 'Z') PeImage.h 　
10810
 EFI_TE_IMAGE_DIRECTORY_ENTRY_BAEFI_TE_IMAGE_DIRECTORY_ENTRY_BA 0 PeImage.h 　
10811
 EFI_TE_IMAGE_DIRECTORY_ENTRY_DEEFI_TE_IMAGE_DIRECTORY_ENTRY_DE 1 PeImage.h 　
10812
 BOOT_WITH_FULL_CONFIGURATIONBOOT_WITH_FULL_CONFIGURATION 0x00 PiBootMode.h 　
10813
 BOOT_WITH_MINIMAL_CONFIGURATIONBOOT_WITH_MINIMAL_CONFIGURATION 0x01 PiBootMode.h 　
10814
 BOOT_ASSUMING_NO_CONFIGURATION_BOOT_ASSUMING_NO_CONFIGURATION_ 0x02 PiBootMode.h 　
10815
 BOOT_WITH_FULL_CONFIGURATION_PLBOOT_WITH_FULL_CONFIGURATION_PL 0x03 PiBootMode.h 　
10816
 BOOT_WITH_DEFAULT_SETTINGSBOOT_WITH_DEFAULT_SETTINGS 0x04 PiBootMode.h 　
10817
 BOOT_ON_S4_RESUMEBOOT_ON_S4_RESUME 0x05 PiBootMode.h 　
10818
 BOOT_ON_S5_RESUMEBOOT_ON_S5_RESUME 0x06 PiBootMode.h 　
10819
 BOOT_ON_S2_RESUMEBOOT_ON_S2_RESUME 0x10 PiBootMode.h 　
10820
 BOOT_ON_S3_RESUMEBOOT_ON_S3_RESUME 0x11 PiBootMode.h 　
10821
 BOOT_ON_FLASH_UPDATEBOOT_ON_FLASH_UPDATE 0x12 PiBootMode.h 　
10822
 BOOT_IN_RECOVERY_MODEBOOT_IN_RECOVERY_MODE 0x20 PiBootMode.h 　
10823
 EFI_DEP_BEFOREEFI_DEP_BEFORE 0x00 PiDependency.h 　
10824
 EFI_DEP_AFTEREFI_DEP_AFTER 0x01 PiDependency.h 　
10825
 EFI_DEP_PUSHEFI_DEP_PUSH 0x02 PiDependency.h 　
10826
 EFI_DEP_ANDEFI_DEP_AND 0x03 PiDependency.h 　
10827
 EFI_DEP_OREFI_DEP_OR 0x04 PiDependency.h 　
10828
 EFI_DEP_NOTEFI_DEP_NOT 0x05 PiDependency.h 　
10829
 EFI_DEP_TRUEEFI_DEP_TRUE 0x06 PiDependency.h 　
10830
 EFI_DEP_FALSEEFI_DEP_FALSE 0x07 PiDependency.h 　
10831
 EFI_DEP_ENDEFI_DEP_END 0x08 PiDependency.h 　
10832
 EFI_DEP_SOREFI_DEP_SOR 0x09 PiDependency.h 　
10833
 DXE_SERVICES_SIGNATUREDXE_SERVICES_SIGNATURE 0x565245535f455844ULL PiDxeCis.h 　
10834
 DXE_SERVICES_REVISIONDXE_SERVICES_REVISION ((1<<16) | (00)) PiDxeCis.h 　
10835
 FFS_FIXED_CHECKSUMFFS_FIXED_CHECKSUM 0xAA PiFirmwareFile.h 　
10836
 EFI_FV_FILETYPE_ALLEFI_FV_FILETYPE_ALL 0x00 PiFirmwareFile.h 　
10837
 EFI_FV_FILETYPE_RAWEFI_FV_FILETYPE_RAW 0x01 PiFirmwareFile.h 　
10838
 EFI_FV_FILETYPE_FREEFORMEFI_FV_FILETYPE_FREEFORM 0x02 PiFirmwareFile.h 　
10839
 EFI_FV_FILETYPE_SECURITY_COREEFI_FV_FILETYPE_SECURITY_CORE 0x03 PiFirmwareFile.h 　
10840
 EFI_FV_FILETYPE_PEI_COREEFI_FV_FILETYPE_PEI_CORE 0x04 PiFirmwareFile.h 　
10841
 EFI_FV_FILETYPE_DXE_COREEFI_FV_FILETYPE_DXE_CORE 0x05 PiFirmwareFile.h 　
10842
 EFI_FV_FILETYPE_PEIMEFI_FV_FILETYPE_PEIM 0x06 PiFirmwareFile.h 　
10843
 EFI_FV_FILETYPE_DRIVEREFI_FV_FILETYPE_DRIVER 0x07 PiFirmwareFile.h 　
10844
 EFI_FV_FILETYPE_COMBINED_PEIM_DEFI_FV_FILETYPE_COMBINED_PEIM_D 0x08 PiFirmwareFile.h 　
10845
 EFI_FV_FILETYPE_APPLICATIONEFI_FV_FILETYPE_APPLICATION 0x09 PiFirmwareFile.h 　
10846
 EFI_FV_FILETYPE_SMMEFI_FV_FILETYPE_SMM 0x0A PiFirmwareFile.h 　
10847
 EFI_FV_FILETYPE_FIRMWARE_VOLUMEEFI_FV_FILETYPE_FIRMWARE_VOLUME 0x0B PiFirmwareFile.h 　
10848
 EFI_FV_FILETYPE_COMBINED_SMM_DXEFI_FV_FILETYPE_COMBINED_SMM_DX 0x0C PiFirmwareFile.h 　
10849
 EFI_FV_FILETYPE_SMM_COREEFI_FV_FILETYPE_SMM_CORE 0x0D PiFirmwareFile.h 　
10850
 EFI_FV_FILETYPE_OEM_MINEFI_FV_FILETYPE_OEM_MIN 0xc0 PiFirmwareFile.h 　
10851
 EFI_FV_FILETYPE_OEM_MAXEFI_FV_FILETYPE_OEM_MAX 0xdf PiFirmwareFile.h 　
10852
 EFI_FV_FILETYPE_DEBUG_MINEFI_FV_FILETYPE_DEBUG_MIN 0xe0 PiFirmwareFile.h 　
10853
 EFI_FV_FILETYPE_DEBUG_MAXEFI_FV_FILETYPE_DEBUG_MAX 0xef PiFirmwareFile.h 　
10854
 EFI_FV_FILETYPE_FFS_MINEFI_FV_FILETYPE_FFS_MIN 0xf0 PiFirmwareFile.h 　
10855
 EFI_FV_FILETYPE_FFS_MAXEFI_FV_FILETYPE_FFS_MAX 0xff PiFirmwareFile.h 　
10856
 EFI_FV_FILETYPE_FFS_PADEFI_FV_FILETYPE_FFS_PAD 0xf0 PiFirmwareFile.h 　
10857
 FFS_ATTRIB_LARGE_FILEFFS_ATTRIB_LARGE_FILE 0x01 PiFirmwareFile.h 　
10858
 FFS_ATTRIB_FIXEDFFS_ATTRIB_FIXED 0x04 PiFirmwareFile.h 　
10859
 FFS_ATTRIB_DATA_ALIGNMENTFFS_ATTRIB_DATA_ALIGNMENT 0x38 PiFirmwareFile.h 　
10860
 FFS_ATTRIB_CHECKSUMFFS_ATTRIB_CHECKSUM 0x40 PiFirmwareFile.h 　
10861
 EFI_FILE_HEADER_CONSTRUCTIONEFI_FILE_HEADER_CONSTRUCTION 0x01 PiFirmwareFile.h 　
10862
 EFI_FILE_HEADER_VALIDEFI_FILE_HEADER_VALID 0x02 PiFirmwareFile.h 　
10863
 EFI_FILE_DATA_VALIDEFI_FILE_DATA_VALID 0x04 PiFirmwareFile.h 　
10864
 EFI_FILE_MARKED_FOR_UPDATEEFI_FILE_MARKED_FOR_UPDATE 0x08 PiFirmwareFile.h 　
10865
 EFI_FILE_DELETEDEFI_FILE_DELETED 0x10 PiFirmwareFile.h 　
10866
 EFI_FILE_HEADER_INVALIDEFI_FILE_HEADER_INVALID 0x20 PiFirmwareFile.h 　
10867
 EFI_SECTION_ALLEFI_SECTION_ALL 0x00 PiFirmwareFile.h 　
10868
 EFI_SECTION_COMPRESSIONEFI_SECTION_COMPRESSION 0x01 PiFirmwareFile.h 　
10869
 EFI_SECTION_GUID_DEFINEDEFI_SECTION_GUID_DEFINED 0x02 PiFirmwareFile.h 　
10870
 EFI_SECTION_DISPOSABLEEFI_SECTION_DISPOSABLE 0x03 PiFirmwareFile.h 　
10871
 EFI_SECTION_PE32EFI_SECTION_PE32 0x10 PiFirmwareFile.h 　
10872
 EFI_SECTION_PICEFI_SECTION_PIC 0x11 PiFirmwareFile.h 　
10873
 EFI_SECTION_TEEFI_SECTION_TE 0x12 PiFirmwareFile.h 　
10874
 EFI_SECTION_DXE_DEPEXEFI_SECTION_DXE_DEPEX 0x13 PiFirmwareFile.h 　
10875
 EFI_SECTION_VERSIONEFI_SECTION_VERSION 0x14 PiFirmwareFile.h 　
10876
 EFI_SECTION_USER_INTERFACEEFI_SECTION_USER_INTERFACE 0x15 PiFirmwareFile.h 　
10877
 EFI_SECTION_COMPATIBILITY16EFI_SECTION_COMPATIBILITY16 0x16 PiFirmwareFile.h 　
10878
 EFI_SECTION_FIRMWARE_VOLUME_IMAEFI_SECTION_FIRMWARE_VOLUME_IMA 0x17 PiFirmwareFile.h 　
10879
 EFI_SECTION_FREEFORM_SUBTYPE_GUEFI_SECTION_FREEFORM_SUBTYPE_GU 0x18 PiFirmwareFile.h 　
10880
 EFI_SECTION_RAWEFI_SECTION_RAW 0x19 PiFirmwareFile.h 　
10881
 EFI_SECTION_PEI_DEPEXEFI_SECTION_PEI_DEPEX 0x1B PiFirmwareFile.h 　
10882
 EFI_SECTION_SMM_DEPEXEFI_SECTION_SMM_DEPEX 0x1C PiFirmwareFile.h 　
10883
 EFI_NOT_COMPRESSEDEFI_NOT_COMPRESSED 0x00 PiFirmwareFile.h 　
10884
 EFI_STANDARD_COMPRESSIONEFI_STANDARD_COMPRESSION 0x01 PiFirmwareFile.h 　
10885
 EFI_GUIDED_SECTION_PROCESSING_REFI_GUIDED_SECTION_PROCESSING_R 0x01 PiFirmwareFile.h 　
10886
 EFI_GUIDED_SECTION_AUTH_STATUS_EFI_GUIDED_SECTION_AUTH_STATUS_ 0x02 PiFirmwareFile.h 　
10887
 EFI_FV_FILE_ATTRIB_ALIGNMENTEFI_FV_FILE_ATTRIB_ALIGNMENT 0x0000001F PiFirmwareVolume.h 　
10888
 EFI_FV_FILE_ATTRIB_FIXEDEFI_FV_FILE_ATTRIB_FIXED 0x00000100 PiFirmwareVolume.h 　
10889
 EFI_FV_FILE_ATTRIB_MEMORY_MAPPEEFI_FV_FILE_ATTRIB_MEMORY_MAPPE 0x00000200 PiFirmwareVolume.h 　
10890
 EFI_FVB2_READ_DISABLED_CAPEFI_FVB2_READ_DISABLED_CAP 0x00000001 PiFirmwareVolume.h 　
10891
 EFI_FVB2_READ_ENABLED_CAPEFI_FVB2_READ_ENABLED_CAP 0x00000002 PiFirmwareVolume.h 　
10892
 EFI_FVB2_READ_STATUSEFI_FVB2_READ_STATUS 0x00000004 PiFirmwareVolume.h 　
10893
 EFI_FVB2_WRITE_DISABLED_CAPEFI_FVB2_WRITE_DISABLED_CAP 0x00000008 PiFirmwareVolume.h 　
10894
 EFI_FVB2_WRITE_ENABLED_CAPEFI_FVB2_WRITE_ENABLED_CAP 0x00000010 PiFirmwareVolume.h 　
10895
 EFI_FVB2_WRITE_STATUSEFI_FVB2_WRITE_STATUS 0x00000020 PiFirmwareVolume.h 　
10896
 EFI_FVB2_LOCK_CAPEFI_FVB2_LOCK_CAP 0x00000040 PiFirmwareVolume.h 　
10897
 EFI_FVB2_LOCK_STATUSEFI_FVB2_LOCK_STATUS 0x00000080 PiFirmwareVolume.h 　
10898
 EFI_FVB2_STICKY_WRITEEFI_FVB2_STICKY_WRITE 0x00000200 PiFirmwareVolume.h 　
10899
 EFI_FVB2_MEMORY_MAPPEDEFI_FVB2_MEMORY_MAPPED 0x00000400 PiFirmwareVolume.h 　
10900
 EFI_FVB2_ERASE_POLARITYEFI_FVB2_ERASE_POLARITY 0x00000800 PiFirmwareVolume.h 　
10901
 EFI_FVB2_READ_LOCK_CAPEFI_FVB2_READ_LOCK_CAP 0x00001000 PiFirmwareVolume.h 　
10902
 EFI_FVB2_READ_LOCK_STATUSEFI_FVB2_READ_LOCK_STATUS 0x00002000 PiFirmwareVolume.h 　
10903
 EFI_FVB2_WRITE_LOCK_CAPEFI_FVB2_WRITE_LOCK_CAP 0x00004000 PiFirmwareVolume.h 　
10904
 EFI_FVB2_WRITE_LOCK_STATUSEFI_FVB2_WRITE_LOCK_STATUS 0x00008000 PiFirmwareVolume.h 　
10905
 EFI_FVB2_ALIGNMENTEFI_FVB2_ALIGNMENT 0x001F0000 PiFirmwareVolume.h 　
10906
 EFI_FVB2_ALIGNMENT_1EFI_FVB2_ALIGNMENT_1 0x00000000 PiFirmwareVolume.h 　
10907
 EFI_FVB2_ALIGNMENT_2EFI_FVB2_ALIGNMENT_2 0x00010000 PiFirmwareVolume.h 　
10908
 EFI_FVB2_ALIGNMENT_4EFI_FVB2_ALIGNMENT_4 0x00020000 PiFirmwareVolume.h 　
10909
 EFI_FVB2_ALIGNMENT_8EFI_FVB2_ALIGNMENT_8 0x00030000 PiFirmwareVolume.h 　
10910
 EFI_FVB2_ALIGNMENT_16EFI_FVB2_ALIGNMENT_16 0x00040000 PiFirmwareVolume.h 　
10911
 EFI_FVB2_ALIGNMENT_32EFI_FVB2_ALIGNMENT_32 0x00050000 PiFirmwareVolume.h 　
10912
 EFI_FVB2_ALIGNMENT_64EFI_FVB2_ALIGNMENT_64 0x00060000 PiFirmwareVolume.h 　
10913
 EFI_FVB2_ALIGNMENT_128EFI_FVB2_ALIGNMENT_128 0x00070000 PiFirmwareVolume.h 　
10914
 EFI_FVB2_ALIGNMENT_256EFI_FVB2_ALIGNMENT_256 0x00080000 PiFirmwareVolume.h 　
10915
 EFI_FVB2_ALIGNMENT_512EFI_FVB2_ALIGNMENT_512 0x00090000 PiFirmwareVolume.h 　
10916
 EFI_FVB2_ALIGNMENT_1KEFI_FVB2_ALIGNMENT_1K 0x000A0000 PiFirmwareVolume.h 　
10917
 EFI_FVB2_ALIGNMENT_2KEFI_FVB2_ALIGNMENT_2K 0x000B0000 PiFirmwareVolume.h 　
10918
 EFI_FVB2_ALIGNMENT_4KEFI_FVB2_ALIGNMENT_4K 0x000C0000 PiFirmwareVolume.h 　
10919
 EFI_FVB2_ALIGNMENT_8KEFI_FVB2_ALIGNMENT_8K 0x000D0000 PiFirmwareVolume.h 　
10920
 EFI_FVB2_ALIGNMENT_16KEFI_FVB2_ALIGNMENT_16K 0x000E0000 PiFirmwareVolume.h 　
10921
 EFI_FVB2_ALIGNMENT_32KEFI_FVB2_ALIGNMENT_32K 0x000F0000 PiFirmwareVolume.h 　
10922
 EFI_FVB2_ALIGNMENT_64KEFI_FVB2_ALIGNMENT_64K 0x00100000 PiFirmwareVolume.h 　
10923
 EFI_FVB2_ALIGNMENT_128KEFI_FVB2_ALIGNMENT_128K 0x00110000 PiFirmwareVolume.h 　
10924
 EFI_FVB2_ALIGNMENT_256KEFI_FVB2_ALIGNMENT_256K 0x00120000 PiFirmwareVolume.h 　
10925
 EFI_FVB2_ALIGNMNET_512KEFI_FVB2_ALIGNMNET_512K 0x00130000 PiFirmwareVolume.h 　
10926
 EFI_FVB2_ALIGNMENT_1MEFI_FVB2_ALIGNMENT_1M 0x00140000 PiFirmwareVolume.h 　
10927
 EFI_FVB2_ALIGNMENT_2MEFI_FVB2_ALIGNMENT_2M 0x00150000 PiFirmwareVolume.h 　
10928
 EFI_FVB2_ALIGNMENT_4MEFI_FVB2_ALIGNMENT_4M 0x00160000 PiFirmwareVolume.h 　
10929
 EFI_FVB2_ALIGNMENT_8MEFI_FVB2_ALIGNMENT_8M 0x00170000 PiFirmwareVolume.h 　
10930
 EFI_FVB2_ALIGNMENT_16MEFI_FVB2_ALIGNMENT_16M 0x00180000 PiFirmwareVolume.h 　
10931
 EFI_FVB2_ALIGNMENT_32MEFI_FVB2_ALIGNMENT_32M 0x00190000 PiFirmwareVolume.h 　
10932
 EFI_FVB2_ALIGNMENT_64MEFI_FVB2_ALIGNMENT_64M 0x001A0000 PiFirmwareVolume.h 　
10933
 EFI_FVB2_ALIGNMENT_128MEFI_FVB2_ALIGNMENT_128M 0x001B0000 PiFirmwareVolume.h 　
10934
 EFI_FVB2_ALIGNMENT_256MEFI_FVB2_ALIGNMENT_256M 0x001C0000 PiFirmwareVolume.h 　
10935
 EFI_FVB2_ALIGNMENT_512MEFI_FVB2_ALIGNMENT_512M 0x001D0000 PiFirmwareVolume.h 　
10936
 EFI_FVB2_ALIGNMENT_1GEFI_FVB2_ALIGNMENT_1G 0x001E0000 PiFirmwareVolume.h 　
10937
 EFI_FVB2_ALIGNMENT_2GEFI_FVB2_ALIGNMENT_2G 0x001F0000 PiFirmwareVolume.h 　
10938
 EFI_FVH_SIGNATUREEFI_FVH_SIGNATURE SIGNATURE_32 ('_', 'F', 'V', 'H') PiFirmwareVolume.h 　
10939
 EFI_FVH_REVISIONEFI_FVH_REVISION 0x02 PiFirmwareVolume.h 　
10940
 EFI_FV_EXT_TYPE_OEM_TYPEEFI_FV_EXT_TYPE_OEM_TYPE 0x01 PiFirmwareVolume.h 　
10941
 EFI_HOB_TYPE_HANDOFFEFI_HOB_TYPE_HANDOFF 0x0001 PiHob.h 　
10942
 EFI_HOB_TYPE_MEMORY_ALLOCATIONEFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 PiHob.h 　
10943
 EFI_HOB_TYPE_RESOURCE_DESCRIPTOEFI_HOB_TYPE_RESOURCE_DESCRIPTO 0x0003 PiHob.h 　
10944
 EFI_HOB_TYPE_GUID_EXTENSIONEFI_HOB_TYPE_GUID_EXTENSION 0x0004 PiHob.h 　
10945
 EFI_HOB_TYPE_FVEFI_HOB_TYPE_FV 0x0005 PiHob.h 　
10946
 EFI_HOB_TYPE_CPUEFI_HOB_TYPE_CPU 0x0006 PiHob.h 　
10947
 EFI_HOB_TYPE_MEMORY_POOLEFI_HOB_TYPE_MEMORY_POOL 0x0007 PiHob.h 　
10948
 EFI_HOB_TYPE_FV2EFI_HOB_TYPE_FV2 0x0009 PiHob.h 　
10949
 EFI_HOB_TYPE_LOAD_PEIM_UNUSEDEFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A PiHob.h 　
10950
 EFI_HOB_TYPE_UEFI_CAPSULEEFI_HOB_TYPE_UEFI_CAPSULE 0x000B PiHob.h 　
10951
 EFI_HOB_TYPE_UNUSEDEFI_HOB_TYPE_UNUSED 0xFFFE PiHob.h 　
10952
 EFI_HOB_TYPE_END_OF_HOB_LISTEFI_HOB_TYPE_END_OF_HOB_LIST 0xFFFF PiHob.h 　
10953
 EFI_HOB_HANDOFF_TABLE_VERSIONEFI_HOB_HANDOFF_TABLE_VERSION 0x0009 PiHob.h 　
10954
 EFI_RESOURCE_SYSTEM_MEMORYEFI_RESOURCE_SYSTEM_MEMORY 0x00000000 PiHob.h 　
10955
 EFI_RESOURCE_MEMORY_MAPPED_IOEFI_RESOURCE_MEMORY_MAPPED_IO 0x00000001 PiHob.h 　
10956
 EFI_RESOURCE_IOEFI_RESOURCE_IO 0x00000002 PiHob.h 　
10957
 EFI_RESOURCE_FIRMWARE_DEVICEEFI_RESOURCE_FIRMWARE_DEVICE 0x00000003 PiHob.h 　
10958
 EFI_RESOURCE_MEMORY_MAPPED_IO_PEFI_RESOURCE_MEMORY_MAPPED_IO_P 0x00000004 PiHob.h 　
10959
 EFI_RESOURCE_MEMORY_RESERVEDEFI_RESOURCE_MEMORY_RESERVED 0x00000005 PiHob.h 　
10960
 EFI_RESOURCE_IO_RESERVEDEFI_RESOURCE_IO_RESERVED 0x00000006 PiHob.h 　
10961
 EFI_RESOURCE_MAX_MEMORY_TYPEEFI_RESOURCE_MAX_MEMORY_TYPE 0x00000007 PiHob.h 　
10962
 EFI_RESOURCE_ATTRIBUTE_PRESENTEFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 PiHob.h 　
10963
 EFI_RESOURCE_ATTRIBUTE_INITIALIEFI_RESOURCE_ATTRIBUTE_INITIALI 0x00000002 PiHob.h 　
10964
 EFI_RESOURCE_ATTRIBUTE_TESTEDEFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 PiHob.h 　
10965
 EFI_RESOURCE_ATTRIBUTE_SINGLE_BEFI_RESOURCE_ATTRIBUTE_SINGLE_B 0x00000008 PiHob.h 　
10966
 EFI_RESOURCE_ATTRIBUTE_MULTIPLEEFI_RESOURCE_ATTRIBUTE_MULTIPLE 0x00000010 PiHob.h 　
10967
 EFI_RESOURCE_ATTRIBUTE_ECC_RESEEFI_RESOURCE_ATTRIBUTE_ECC_RESE 0x00000020 PiHob.h 　
10968
 EFI_RESOURCE_ATTRIBUTE_ECC_RESEEFI_RESOURCE_ATTRIBUTE_ECC_RESE 0x00000040 PiHob.h 　
10969
 EFI_RESOURCE_ATTRIBUTE_READ_PROEFI_RESOURCE_ATTRIBUTE_READ_PRO 0x00000080 PiHob.h 　
10970
 EFI_RESOURCE_ATTRIBUTE_WRITE_PREFI_RESOURCE_ATTRIBUTE_WRITE_PR 0x00000100 PiHob.h 　
10971
 EFI_RESOURCE_ATTRIBUTE_EXECUTIOEFI_RESOURCE_ATTRIBUTE_EXECUTIO 0x00000200 PiHob.h 　
10972
 EFI_RESOURCE_ATTRIBUTE_UNCACHEAEFI_RESOURCE_ATTRIBUTE_UNCACHEA 0x00000400 PiHob.h 　
10973
 EFI_RESOURCE_ATTRIBUTE_WRITE_COEFI_RESOURCE_ATTRIBUTE_WRITE_CO 0x00000800 PiHob.h 　
10974
 EFI_RESOURCE_ATTRIBUTE_WRITE_THEFI_RESOURCE_ATTRIBUTE_WRITE_TH 0x00001000 PiHob.h 　
10975
 EFI_RESOURCE_ATTRIBUTE_WRITE_BAEFI_RESOURCE_ATTRIBUTE_WRITE_BA 0x00002000 PiHob.h 　
10976
 EFI_RESOURCE_ATTRIBUTE_16_BIT_IEFI_RESOURCE_ATTRIBUTE_16_BIT_I 0x00004000 PiHob.h 　
10977
 EFI_RESOURCE_ATTRIBUTE_32_BIT_IEFI_RESOURCE_ATTRIBUTE_32_BIT_I 0x00008000 PiHob.h 　
10978
 EFI_RESOURCE_ATTRIBUTE_64_BIT_IEFI_RESOURCE_ATTRIBUTE_64_BIT_I 0x00010000 PiHob.h 　
10979
 EFI_RESOURCE_ATTRIBUTE_UNCACHEDEFI_RESOURCE_ATTRIBUTE_UNCACHED 0x00020000 PiHob.h 　
10980
 EFI_REQUEST_UNLOAD_IMAGEEFI_REQUEST_UNLOAD_IMAGE DXE_ERROR (1) PiMultiPhase.h 　
10981
 EFI_NOT_AVAILABLE_YETEFI_NOT_AVAILABLE_YET DXE_ERROR (2) PiMultiPhase.h 　
10982
 EFI_INTERRUPT_PENDINGEFI_INTERRUPT_PENDING PI_ENCODE_ERROR (0) PiMultiPhase.h 　
10983
 EFI_WARN_INTERRUPT_SOURCE_PENDIEFI_WARN_INTERRUPT_SOURCE_PENDI PI_ENCODE_WARNING (0) PiMultiPhase.h 　
10984
 EFI_WARN_INTERRUPT_SOURCE_QUIESEFI_WARN_INTERRUPT_SOURCE_QUIES PI_ENCODE_WARNING (1) PiMultiPhase.h 　
10985
 EFI_AUTH_STATUS_PLATFORM_OVERRIEFI_AUTH_STATUS_PLATFORM_OVERRI 0x01 PiMultiPhase.h 　
10986
 EFI_AUTH_STATUS_IMAGE_SIGNEDEFI_AUTH_STATUS_IMAGE_SIGNED 0x02 PiMultiPhase.h 　
10987
 EFI_AUTH_STATUS_NOT_TESTEDEFI_AUTH_STATUS_NOT_TESTED 0x04 PiMultiPhase.h 　
10988
 EFI_AUTH_STATUS_TEST_FAILEDEFI_AUTH_STATUS_TEST_FAILED 0x08 PiMultiPhase.h 　
10989
 EFI_AUTH_STATUS_ALLEFI_AUTH_STATUS_ALL 0x0f PiMultiPhase.h 　
10990
 EFI_SMRAM_OPENEFI_SMRAM_OPEN 0x00000001 PiMultiPhase.h 　
10991
 EFI_SMRAM_CLOSEDEFI_SMRAM_CLOSED 0x00000002 PiMultiPhase.h 　
10992
 EFI_SMRAM_LOCKEDEFI_SMRAM_LOCKED 0x00000004 PiMultiPhase.h 　
10993
 EFI_CACHEABLEEFI_CACHEABLE 0x00000008 PiMultiPhase.h 　
10994
 EFI_ALLOCATEDEFI_ALLOCATED 0x00000010 PiMultiPhase.h 　
10995
 EFI_NEEDS_TESTINGEFI_NEEDS_TESTING 0x00000020 PiMultiPhase.h 　
10996
 EFI_NEEDS_ECC_INITIALIZATIONEFI_NEEDS_ECC_INITIALIZATION 0x00000040 PiMultiPhase.h 　
10997
 EFI_BOOT_SCRIPT_IO_WRITE_OPCODEEFI_BOOT_SCRIPT_IO_WRITE_OPCODE 0x00 PiS3BootScript.h 　
10998
 EFI_BOOT_SCRIPT_IO_READ_WRITE_OEFI_BOOT_SCRIPT_IO_READ_WRITE_O 0x01 PiS3BootScript.h 　
10999
 EFI_BOOT_SCRIPT_MEM_WRITE_OPCODEFI_BOOT_SCRIPT_MEM_WRITE_OPCOD 0x02 PiS3BootScript.h 　
11000
 EFI_BOOT_SCRIPT_MEM_READ_WRITE_EFI_BOOT_SCRIPT_MEM_READ_WRITE_ 0x03 PiS3BootScript.h 　
11001
 EFI_BOOT_SCRIPT_PCI_CONFIG_WRITEFI_BOOT_SCRIPT_PCI_CONFIG_WRIT 0x04 PiS3BootScript.h 　
11002
 EFI_BOOT_SCRIPT_PCI_CONFIG_READEFI_BOOT_SCRIPT_PCI_CONFIG_READ 0x05 PiS3BootScript.h 　
11003
 EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OEFI_BOOT_SCRIPT_SMBUS_EXECUTE_O 0x06 PiS3BootScript.h 　
11004
 EFI_BOOT_SCRIPT_STALL_OPCODEEFI_BOOT_SCRIPT_STALL_OPCODE 0x07 PiS3BootScript.h 　
11005
 EFI_BOOT_SCRIPT_DISPATCH_OPCODEEFI_BOOT_SCRIPT_DISPATCH_OPCODE 0x08 PiS3BootScript.h 　
11006
 EFI_BOOT_SCRIPT_DISPATCH_2_OPCOEFI_BOOT_SCRIPT_DISPATCH_2_OPCO 0x09 PiS3BootScript.h 　
11007
 EFI_BOOT_SCRIPT_INFORMATION_OPCEFI_BOOT_SCRIPT_INFORMATION_OPC 0x0A PiS3BootScript.h 　
11008
 EFI_BOOT_SCRIPT_PCI_CONFIG2_WRIEFI_BOOT_SCRIPT_PCI_CONFIG2_WRI 0x0B PiS3BootScript.h 　
11009
 EFI_BOOT_SCRIPT_PCI_CONFIG2_REAEFI_BOOT_SCRIPT_PCI_CONFIG2_REA 0x0C PiS3BootScript.h 　
11010
 EFI_BOOT_SCRIPT_IO_POLL_OPCODEEFI_BOOT_SCRIPT_IO_POLL_OPCODE 0x0D PiS3BootScript.h 　
11011
 EFI_BOOT_SCRIPT_MEM_POLL_OPCODEEFI_BOOT_SCRIPT_MEM_POLL_OPCODE 0x0E PiS3BootScript.h 　
11012
 EFI_BOOT_SCRIPT_PCI_CONFIG_POLLEFI_BOOT_SCRIPT_PCI_CONFIG_POLL 0x0F PiS3BootScript.h 　
11013
 EFI_BOOT_SCRIPT_PCI_CONFIG2_POLEFI_BOOT_SCRIPT_PCI_CONFIG2_POL 0x10 PiS3BootScript.h 　
11014
 EFI_STATUS_CODE_TYPE_MASKEFI_STATUS_CODE_TYPE_MASK 0x000000FF PiStatusCode.h 　
11015
 EFI_STATUS_CODE_SEVERITY_MASKEFI_STATUS_CODE_SEVERITY_MASK 0xFF000000 PiStatusCode.h 　
11016
 EFI_STATUS_CODE_RESERVED_MASKEFI_STATUS_CODE_RESERVED_MASK 0x00FFFF00 PiStatusCode.h 　
11017
 EFI_PROGRESS_CODEEFI_PROGRESS_CODE 0x00000001 PiStatusCode.h 　
11018
 EFI_ERROR_CODEEFI_ERROR_CODE 0x00000002 PiStatusCode.h 　
11019
 EFI_DEBUG_CODEEFI_DEBUG_CODE 0x00000003 PiStatusCode.h 　
11020
 EFI_ERROR_MINOREFI_ERROR_MINOR 0x40000000 PiStatusCode.h 　
11021
 EFI_ERROR_MAJOREFI_ERROR_MAJOR 0x80000000 PiStatusCode.h 　
11022
 EFI_ERROR_UNRECOVEREDEFI_ERROR_UNRECOVERED 0x90000000 PiStatusCode.h 　
11023
 EFI_ERROR_UNCONTAINEDEFI_ERROR_UNCONTAINED 0xa0000000 PiStatusCode.h 　
11024
 EFI_STATUS_CODE_CLASS_MASKEFI_STATUS_CODE_CLASS_MASK 0xFF000000 PiStatusCode.h 　
11025
 EFI_STATUS_CODE_SUBCLASS_MASKEFI_STATUS_CODE_SUBCLASS_MASK 0x00FF0000 PiStatusCode.h 　
11026
 EFI_STATUS_CODE_OPERATION_MASKEFI_STATUS_CODE_OPERATION_MASK 0x0000FFFF PiStatusCode.h 　
11027
 EFI_SUBCLASS_SPECIFICEFI_SUBCLASS_SPECIFIC 0x1000 PiStatusCode.h 　
11028
 EFI_OEM_SPECIFICEFI_OEM_SPECIFIC 0x8000 PiStatusCode.h 　
11029
 EFI_DC_UNSPECIFIEDEFI_DC_UNSPECIFIED 0x0 PiStatusCode.h 　
11030
 EFI_COMPUTING_UNITEFI_COMPUTING_UNIT 0x00000000 PiStatusCode.h 　
11031
 EFI_PERIPHERALEFI_PERIPHERAL 0x01000000 PiStatusCode.h 　
11032
 EFI_IO_BUSEFI_IO_BUS 0x02000000 PiStatusCode.h 　
11033
 EFI_SOFTWAREEFI_SOFTWARE 0x03000000 PiStatusCode.h 　
11034
 EFI_COMPUTING_UNIT_UNSPECIFIEDEFI_COMPUTING_UNIT_UNSPECIFIED (EFI_COMPUTING_UNIT | 0x00000000) PiStatusCode.h 　
11035
 EFI_COMPUTING_UNIT_HOST_PROCESSEFI_COMPUTING_UNIT_HOST_PROCESS (EFI_COMPUTING_UNIT | 0x00010000) PiStatusCode.h 　
11036
 EFI_COMPUTING_UNIT_FIRMWARE_PROEFI_COMPUTING_UNIT_FIRMWARE_PRO (EFI_COMPUTING_UNIT | 0x00020000) PiStatusCode.h 　
11037
 EFI_COMPUTING_UNIT_IO_PROCESSOREFI_COMPUTING_UNIT_IO_PROCESSOR (EFI_COMPUTING_UNIT | 0x00030000) PiStatusCode.h 　
11038
 EFI_COMPUTING_UNIT_CACHEEFI_COMPUTING_UNIT_CACHE (EFI_COMPUTING_UNIT | 0x00040000) PiStatusCode.h 　
11039
 EFI_COMPUTING_UNIT_MEMORYEFI_COMPUTING_UNIT_MEMORY (EFI_COMPUTING_UNIT | 0x00050000) PiStatusCode.h 　
11040
 EFI_COMPUTING_UNIT_CHIPSETEFI_COMPUTING_UNIT_CHIPSET (EFI_COMPUTING_UNIT | 0x00060000) PiStatusCode.h 　
11041
 EFI_CU_PC_INIT_BEGINEFI_CU_PC_INIT_BEGIN 0x00000000 PiStatusCode.h 　
11042
 EFI_CU_PC_INIT_ENDEFI_CU_PC_INIT_END 0x00000001 PiStatusCode.h 　
11043
 EFI_CU_HP_PC_POWER_ON_INITEFI_CU_HP_PC_POWER_ON_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11044
 EFI_CU_HP_PC_CACHE_INITEFI_CU_HP_PC_CACHE_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11045
 EFI_CU_HP_PC_RAM_INITEFI_CU_HP_PC_RAM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11046
 EFI_CU_HP_PC_MEMORY_CONTROLLER_EFI_CU_HP_PC_MEMORY_CONTROLLER_ (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11047
 EFI_CU_HP_PC_IO_INITEFI_CU_HP_PC_IO_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11048
 EFI_CU_HP_PC_BSP_SELECTEFI_CU_HP_PC_BSP_SELECT (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11049
 EFI_CU_HP_PC_BSP_RESELECTEFI_CU_HP_PC_BSP_RESELECT (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11050
 EFI_CU_HP_PC_AP_INITEFI_CU_HP_PC_AP_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000007) PiStatusCode.h 　
11051
 EFI_CU_HP_PC_SMM_INITEFI_CU_HP_PC_SMM_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000008) PiStatusCode.h 　
11052
 EFI_CU_CACHE_PC_PRESENCE_DETECTEFI_CU_CACHE_PC_PRESENCE_DETECT (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11053
 EFI_CU_CACHE_PC_CONFIGURATIONEFI_CU_CACHE_PC_CONFIGURATION (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11054
 EFI_CU_MEMORY_PC_SPD_READEFI_CU_MEMORY_PC_SPD_READ (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11055
 EFI_CU_MEMORY_PC_PRESENCE_DETECEFI_CU_MEMORY_PC_PRESENCE_DETEC (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11056
 EFI_CU_MEMORY_PC_TIMINGEFI_CU_MEMORY_PC_TIMING (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11057
 EFI_CU_MEMORY_PC_CONFIGURINGEFI_CU_MEMORY_PC_CONFIGURING (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11058
 EFI_CU_MEMORY_PC_OPTIMIZINGEFI_CU_MEMORY_PC_OPTIMIZING (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11059
 EFI_CU_MEMORY_PC_INITEFI_CU_MEMORY_PC_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11060
 EFI_CU_MEMORY_PC_TESTEFI_CU_MEMORY_PC_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11061
 EFI_CHIPSET_PC_PEI_CAR_SB_INITEFI_CHIPSET_PC_PEI_CAR_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000000) PiStatusCode.h 　
11062
 EFI_CHIPSET_PC_PEI_CAR_NB_INITEFI_CHIPSET_PC_PEI_CAR_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000001) PiStatusCode.h 　
11063
 EFI_CHIPSET_PC_PEI_MEM_SB_INITEFI_CHIPSET_PC_PEI_MEM_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000002) PiStatusCode.h 　
11064
 EFI_CHIPSET_PC_PEI_MEM_NB_INITEFI_CHIPSET_PC_PEI_MEM_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000003) PiStatusCode.h 　
11065
 EFI_CHIPSET_PC_DXE_HB_INITEFI_CHIPSET_PC_DXE_HB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000004) PiStatusCode.h 　
11066
 EFI_CHIPSET_PC_DXE_NB_INITEFI_CHIPSET_PC_DXE_NB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000005) PiStatusCode.h 　
11067
 EFI_CHIPSET_PC_DXE_NB_SMM_INITEFI_CHIPSET_PC_DXE_NB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000006) PiStatusCode.h 　
11068
 EFI_CHIPSET_PC_DXE_SB_RT_INITEFI_CHIPSET_PC_DXE_SB_RT_INIT (EFI_SUBCLASS_SPECIFIC|0x00000007) PiStatusCode.h 　
11069
 EFI_CHIPSET_PC_DXE_SB_INITEFI_CHIPSET_PC_DXE_SB_INIT (EFI_SUBCLASS_SPECIFIC|0x00000008) PiStatusCode.h 　
11070
 EFI_CHIPSET_PC_DXE_SB_SMM_INITEFI_CHIPSET_PC_DXE_SB_SMM_INIT (EFI_SUBCLASS_SPECIFIC|0x00000009) PiStatusCode.h 　
11071
 EFI_CHIPSET_PC_DXE_SB_DEVICES_IEFI_CHIPSET_PC_DXE_SB_DEVICES_I (EFI_SUBCLASS_SPECIFIC|0x0000000a) PiStatusCode.h 　
11072
 EFI_CU_EC_NON_SPECIFICEFI_CU_EC_NON_SPECIFIC 0x00000000 PiStatusCode.h 　
11073
 EFI_CU_EC_DISABLEDEFI_CU_EC_DISABLED 0x00000001 PiStatusCode.h 　
11074
 EFI_CU_EC_NOT_SUPPORTEDEFI_CU_EC_NOT_SUPPORTED 0x00000002 PiStatusCode.h 　
11075
 EFI_CU_EC_NOT_DETECTEDEFI_CU_EC_NOT_DETECTED 0x00000003 PiStatusCode.h 　
11076
 EFI_CU_EC_NOT_CONFIGUREDEFI_CU_EC_NOT_CONFIGURED 0x00000004 PiStatusCode.h 　
11077
 EFI_CU_HP_EC_INVALID_TYPEEFI_CU_HP_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11078
 EFI_CU_HP_EC_INVALID_SPEEDEFI_CU_HP_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11079
 EFI_CU_HP_EC_MISMATCHEFI_CU_HP_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11080
 EFI_CU_HP_EC_TIMER_EXPIREDEFI_CU_HP_EC_TIMER_EXPIRED (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11081
 EFI_CU_HP_EC_SELF_TESTEFI_CU_HP_EC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11082
 EFI_CU_HP_EC_INTERNALEFI_CU_HP_EC_INTERNAL (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11083
 EFI_CU_HP_EC_THERMALEFI_CU_HP_EC_THERMAL (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11084
 EFI_CU_HP_EC_LOW_VOLTAGEEFI_CU_HP_EC_LOW_VOLTAGE (EFI_SUBCLASS_SPECIFIC | 0x00000007) PiStatusCode.h 　
11085
 EFI_CU_HP_EC_HIGH_VOLTAGEEFI_CU_HP_EC_HIGH_VOLTAGE (EFI_SUBCLASS_SPECIFIC | 0x00000008) PiStatusCode.h 　
11086
 EFI_CU_HP_EC_CACHEEFI_CU_HP_EC_CACHE (EFI_SUBCLASS_SPECIFIC | 0x00000009) PiStatusCode.h 　
11087
 EFI_CU_HP_EC_MICROCODE_UPDATEEFI_CU_HP_EC_MICROCODE_UPDATE (EFI_SUBCLASS_SPECIFIC | 0x0000000A) PiStatusCode.h 　
11088
 EFI_CU_HP_EC_CORRECTABLEEFI_CU_HP_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x0000000B) PiStatusCode.h 　
11089
 EFI_CU_HP_EC_UNCORRECTABLEEFI_CU_HP_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x0000000C) PiStatusCode.h 　
11090
 EFI_CU_HP_EC_NO_MICROCODE_UPDATEFI_CU_HP_EC_NO_MICROCODE_UPDAT (EFI_SUBCLASS_SPECIFIC | 0x0000000D) PiStatusCode.h 　
11091
 EFI_CU_FP_EC_HARD_FAILEFI_CU_FP_EC_HARD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11092
 EFI_CU_FP_EC_SOFT_FAILEFI_CU_FP_EC_SOFT_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11093
 EFI_CU_FP_EC_COMM_ERROREFI_CU_FP_EC_COMM_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11094
 EFI_CU_CACHE_EC_INVALID_TYPEEFI_CU_CACHE_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11095
 EFI_CU_CACHE_EC_INVALID_SPEEDEFI_CU_CACHE_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11096
 EFI_CU_CACHE_EC_INVALID_SIZEEFI_CU_CACHE_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11097
 EFI_CU_CACHE_EC_MISMATCHEFI_CU_CACHE_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11098
 EFI_CU_MEMORY_EC_INVALID_TYPEEFI_CU_MEMORY_EC_INVALID_TYPE (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11099
 EFI_CU_MEMORY_EC_INVALID_SPEEDEFI_CU_MEMORY_EC_INVALID_SPEED (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11100
 EFI_CU_MEMORY_EC_CORRECTABLEEFI_CU_MEMORY_EC_CORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11101
 EFI_CU_MEMORY_EC_UNCORRECTABLEEFI_CU_MEMORY_EC_UNCORRECTABLE (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11102
 EFI_CU_MEMORY_EC_SPD_FAILEFI_CU_MEMORY_EC_SPD_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11103
 EFI_CU_MEMORY_EC_INVALID_SIZEEFI_CU_MEMORY_EC_INVALID_SIZE (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11104
 EFI_CU_MEMORY_EC_MISMATCHEFI_CU_MEMORY_EC_MISMATCH (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11105
 EFI_CU_MEMORY_EC_S3_RESUME_FAILEFI_CU_MEMORY_EC_S3_RESUME_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000007) PiStatusCode.h 　
11106
 EFI_CU_MEMORY_EC_UPDATE_FAILEFI_CU_MEMORY_EC_UPDATE_FAIL (EFI_SUBCLASS_SPECIFIC | 0x00000008) PiStatusCode.h 　
11107
 EFI_CU_MEMORY_EC_NONE_DETECTEDEFI_CU_MEMORY_EC_NONE_DETECTED (EFI_SUBCLASS_SPECIFIC | 0x00000009) PiStatusCode.h 　
11108
 EFI_CU_MEMORY_EC_NONE_USEFULEFI_CU_MEMORY_EC_NONE_USEFUL (EFI_SUBCLASS_SPECIFIC | 0x0000000A) PiStatusCode.h 　
11109
 EFI_CHIPSET_EC_BAD_BATTERYEFI_CHIPSET_EC_BAD_BATTERY (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11110
 EFI_CHIPSET_EC_DXE_NB_ERROREFI_CHIPSET_EC_DXE_NB_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11111
 EFI_CHIPSET_EC_DXE_SB_ERROREFI_CHIPSET_EC_DXE_SB_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11112
 EFI_PERIPHERAL_UNSPECIFIEDEFI_PERIPHERAL_UNSPECIFIED (EFI_PERIPHERAL | 0x00000000) PiStatusCode.h 　
11113
 EFI_PERIPHERAL_KEYBOARDEFI_PERIPHERAL_KEYBOARD (EFI_PERIPHERAL | 0x00010000) PiStatusCode.h 　
11114
 EFI_PERIPHERAL_MOUSEEFI_PERIPHERAL_MOUSE (EFI_PERIPHERAL | 0x00020000) PiStatusCode.h 　
11115
 EFI_PERIPHERAL_LOCAL_CONSOLEEFI_PERIPHERAL_LOCAL_CONSOLE (EFI_PERIPHERAL | 0x00030000) PiStatusCode.h 　
11116
 EFI_PERIPHERAL_REMOTE_CONSOLEEFI_PERIPHERAL_REMOTE_CONSOLE (EFI_PERIPHERAL | 0x00040000) PiStatusCode.h 　
11117
 EFI_PERIPHERAL_SERIAL_PORTEFI_PERIPHERAL_SERIAL_PORT (EFI_PERIPHERAL | 0x00050000) PiStatusCode.h 　
11118
 EFI_PERIPHERAL_PARALLEL_PORTEFI_PERIPHERAL_PARALLEL_PORT (EFI_PERIPHERAL | 0x00060000) PiStatusCode.h 　
11119
 EFI_PERIPHERAL_FIXED_MEDIAEFI_PERIPHERAL_FIXED_MEDIA (EFI_PERIPHERAL | 0x00070000) PiStatusCode.h 　
11120
 EFI_PERIPHERAL_REMOVABLE_MEDIAEFI_PERIPHERAL_REMOVABLE_MEDIA (EFI_PERIPHERAL | 0x00080000) PiStatusCode.h 　
11121
 EFI_PERIPHERAL_AUDIO_INPUTEFI_PERIPHERAL_AUDIO_INPUT (EFI_PERIPHERAL | 0x00090000) PiStatusCode.h 　
11122
 EFI_PERIPHERAL_AUDIO_OUTPUTEFI_PERIPHERAL_AUDIO_OUTPUT (EFI_PERIPHERAL | 0x000A0000) PiStatusCode.h 　
11123
 EFI_PERIPHERAL_LCD_DEVICEEFI_PERIPHERAL_LCD_DEVICE (EFI_PERIPHERAL | 0x000B0000) PiStatusCode.h 　
11124
 EFI_PERIPHERAL_NETWORKEFI_PERIPHERAL_NETWORK (EFI_PERIPHERAL | 0x000C0000) PiStatusCode.h 　
11125
 EFI_P_PC_INITEFI_P_PC_INIT 0x00000000 PiStatusCode.h 　
11126
 EFI_P_PC_RESETEFI_P_PC_RESET 0x00000001 PiStatusCode.h 　
11127
 EFI_P_PC_DISABLEEFI_P_PC_DISABLE 0x00000002 PiStatusCode.h 　
11128
 EFI_P_PC_PRESENCE_DETECTEFI_P_PC_PRESENCE_DETECT 0x00000003 PiStatusCode.h 　
11129
 EFI_P_PC_ENABLEEFI_P_PC_ENABLE 0x00000004 PiStatusCode.h 　
11130
 EFI_P_PC_RECONFIGEFI_P_PC_RECONFIG 0x00000005 PiStatusCode.h 　
11131
 EFI_P_PC_DETECTEDEFI_P_PC_DETECTED 0x00000006 PiStatusCode.h 　
11132
 EFI_P_KEYBOARD_PC_CLEAR_BUFFEREFI_P_KEYBOARD_PC_CLEAR_BUFFER (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11133
 EFI_P_KEYBOARD_PC_SELF_TESTEFI_P_KEYBOARD_PC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11134
 EFI_P_MOUSE_PC_SELF_TESTEFI_P_MOUSE_PC_SELF_TEST (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11135
 EFI_P_SERIAL_PORT_PC_CLEAR_BUFFEFI_P_SERIAL_PORT_PC_CLEAR_BUFF (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11136
 EFI_P_EC_NON_SPECIFICEFI_P_EC_NON_SPECIFIC 0x00000000 PiStatusCode.h 　
11137
 EFI_P_EC_DISABLEDEFI_P_EC_DISABLED 0x00000001 PiStatusCode.h 　
11138
 EFI_P_EC_NOT_SUPPORTEDEFI_P_EC_NOT_SUPPORTED 0x00000002 PiStatusCode.h 　
11139
 EFI_P_EC_NOT_DETECTEDEFI_P_EC_NOT_DETECTED 0x00000003 PiStatusCode.h 　
11140
 EFI_P_EC_NOT_CONFIGUREDEFI_P_EC_NOT_CONFIGURED 0x00000004 PiStatusCode.h 　
11141
 EFI_P_EC_INTERFACE_ERROREFI_P_EC_INTERFACE_ERROR 0x00000005 PiStatusCode.h 　
11142
 EFI_P_EC_CONTROLLER_ERROREFI_P_EC_CONTROLLER_ERROR 0x00000006 PiStatusCode.h 　
11143
 EFI_P_EC_INPUT_ERROREFI_P_EC_INPUT_ERROR 0x00000007 PiStatusCode.h 　
11144
 EFI_P_EC_OUTPUT_ERROREFI_P_EC_OUTPUT_ERROR 0x00000008 PiStatusCode.h 　
11145
 EFI_P_EC_RESOURCE_CONFLICTEFI_P_EC_RESOURCE_CONFLICT 0x00000009 PiStatusCode.h 　
11146
 EFI_P_KEYBOARD_EC_LOCKEDEFI_P_KEYBOARD_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11147
 EFI_P_KEYBOARD_EC_STUCK_KEYEFI_P_KEYBOARD_EC_STUCK_KEY (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11148
 EFI_P_MOUSE_EC_LOCKEDEFI_P_MOUSE_EC_LOCKED (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11149
 EFI_IO_BUS_UNSPECIFIEDEFI_IO_BUS_UNSPECIFIED (EFI_IO_BUS | 0x00000000) PiStatusCode.h 　
11150
 EFI_IO_BUS_PCIEFI_IO_BUS_PCI (EFI_IO_BUS | 0x00010000) PiStatusCode.h 　
11151
 EFI_IO_BUS_USBEFI_IO_BUS_USB (EFI_IO_BUS | 0x00020000) PiStatusCode.h 　
11152
 EFI_IO_BUS_IBAEFI_IO_BUS_IBA (EFI_IO_BUS | 0x00030000) PiStatusCode.h 　
11153
 EFI_IO_BUS_AGPEFI_IO_BUS_AGP (EFI_IO_BUS | 0x00040000) PiStatusCode.h 　
11154
 EFI_IO_BUS_PC_CARDEFI_IO_BUS_PC_CARD (EFI_IO_BUS | 0x00050000) PiStatusCode.h 　
11155
 EFI_IO_BUS_LPCEFI_IO_BUS_LPC (EFI_IO_BUS | 0x00060000) PiStatusCode.h 　
11156
 EFI_IO_BUS_SCSIEFI_IO_BUS_SCSI (EFI_IO_BUS | 0x00070000) PiStatusCode.h 　
11157
 EFI_IO_BUS_ATA_ATAPIEFI_IO_BUS_ATA_ATAPI (EFI_IO_BUS | 0x00080000) PiStatusCode.h 　
11158
 EFI_IO_BUS_FCEFI_IO_BUS_FC (EFI_IO_BUS | 0x00090000) PiStatusCode.h 　
11159
 EFI_IO_BUS_IP_NETWORKEFI_IO_BUS_IP_NETWORK (EFI_IO_BUS | 0x000A0000) PiStatusCode.h 　
11160
 EFI_IO_BUS_SMBUSEFI_IO_BUS_SMBUS (EFI_IO_BUS | 0x000B0000) PiStatusCode.h 　
11161
 EFI_IO_BUS_I2CEFI_IO_BUS_I2C (EFI_IO_BUS | 0x000C0000) PiStatusCode.h 　
11162
 EFI_IOB_PC_INITEFI_IOB_PC_INIT 0x00000000 PiStatusCode.h 　
11163
 EFI_IOB_PC_RESETEFI_IOB_PC_RESET 0x00000001 PiStatusCode.h 　
11164
 EFI_IOB_PC_DISABLEEFI_IOB_PC_DISABLE 0x00000002 PiStatusCode.h 　
11165
 EFI_IOB_PC_DETECTEFI_IOB_PC_DETECT 0x00000003 PiStatusCode.h 　
11166
 EFI_IOB_PC_ENABLEEFI_IOB_PC_ENABLE 0x00000004 PiStatusCode.h 　
11167
 EFI_IOB_PC_RECONFIGEFI_IOB_PC_RECONFIG 0x00000005 PiStatusCode.h 　
11168
 EFI_IOB_PC_HOTPLUGEFI_IOB_PC_HOTPLUG 0x00000006 PiStatusCode.h 　
11169
 EFI_IOB_PCI_PC_BUS_ENUMEFI_IOB_PCI_PC_BUS_ENUM (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11170
 EFI_IOB_PCI_PC_RES_ALLOCEFI_IOB_PCI_PC_RES_ALLOC (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11171
 EFI_IOB_PCI_PC_HPC_INITEFI_IOB_PCI_PC_HPC_INIT (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11172
 EFI_IOB_EC_NON_SPECIFICEFI_IOB_EC_NON_SPECIFIC 0x00000000 PiStatusCode.h 　
11173
 EFI_IOB_EC_DISABLEDEFI_IOB_EC_DISABLED 0x00000001 PiStatusCode.h 　
11174
 EFI_IOB_EC_NOT_SUPPORTEDEFI_IOB_EC_NOT_SUPPORTED 0x00000002 PiStatusCode.h 　
11175
 EFI_IOB_EC_NOT_DETECTEDEFI_IOB_EC_NOT_DETECTED 0x00000003 PiStatusCode.h 　
11176
 EFI_IOB_EC_NOT_CONFIGUREDEFI_IOB_EC_NOT_CONFIGURED 0x00000004 PiStatusCode.h 　
11177
 EFI_IOB_EC_INTERFACE_ERROREFI_IOB_EC_INTERFACE_ERROR 0x00000005 PiStatusCode.h 　
11178
 EFI_IOB_EC_CONTROLLER_ERROREFI_IOB_EC_CONTROLLER_ERROR 0x00000006 PiStatusCode.h 　
11179
 EFI_IOB_EC_READ_ERROREFI_IOB_EC_READ_ERROR 0x00000007 PiStatusCode.h 　
11180
 EFI_IOB_EC_WRITE_ERROREFI_IOB_EC_WRITE_ERROR 0x00000008 PiStatusCode.h 　
11181
 EFI_IOB_EC_RESOURCE_CONFLICTEFI_IOB_EC_RESOURCE_CONFLICT 0x00000009 PiStatusCode.h 　
11182
 EFI_IOB_PCI_EC_PERREFI_IOB_PCI_EC_PERR (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11183
 EFI_IOB_PCI_EC_SERREFI_IOB_PCI_EC_SERR (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11184
 EFI_SOFTWARE_UNSPECIFIEDEFI_SOFTWARE_UNSPECIFIED (EFI_SOFTWARE | 0x00000000) PiStatusCode.h 　
11185
 EFI_SOFTWARE_SECEFI_SOFTWARE_SEC (EFI_SOFTWARE | 0x00010000) PiStatusCode.h 　
11186
 EFI_SOFTWARE_PEI_COREEFI_SOFTWARE_PEI_CORE (EFI_SOFTWARE | 0x00020000) PiStatusCode.h 　
11187
 EFI_SOFTWARE_PEI_MODULEEFI_SOFTWARE_PEI_MODULE (EFI_SOFTWARE | 0x00030000) PiStatusCode.h 　
11188
 EFI_SOFTWARE_DXE_COREEFI_SOFTWARE_DXE_CORE (EFI_SOFTWARE | 0x00040000) PiStatusCode.h 　
11189
 EFI_SOFTWARE_DXE_BS_DRIVEREFI_SOFTWARE_DXE_BS_DRIVER (EFI_SOFTWARE | 0x00050000) PiStatusCode.h 　
11190
 EFI_SOFTWARE_DXE_RT_DRIVEREFI_SOFTWARE_DXE_RT_DRIVER (EFI_SOFTWARE | 0x00060000) PiStatusCode.h 　
11191
 EFI_SOFTWARE_SMM_DRIVEREFI_SOFTWARE_SMM_DRIVER (EFI_SOFTWARE | 0x00070000) PiStatusCode.h 　
11192
 EFI_SOFTWARE_EFI_APPLICATIONEFI_SOFTWARE_EFI_APPLICATION (EFI_SOFTWARE | 0x00080000) PiStatusCode.h 　
11193
 EFI_SOFTWARE_EFI_OS_LOADEREFI_SOFTWARE_EFI_OS_LOADER (EFI_SOFTWARE | 0x00090000) PiStatusCode.h 　
11194
 EFI_SOFTWARE_RTEFI_SOFTWARE_RT (EFI_SOFTWARE | 0x000A0000) PiStatusCode.h 　
11195
 EFI_SOFTWARE_ALEFI_SOFTWARE_AL (EFI_SOFTWARE | 0x000B0000) PiStatusCode.h 　
11196
 EFI_SOFTWARE_EBC_EXCEPTIONEFI_SOFTWARE_EBC_EXCEPTION (EFI_SOFTWARE | 0x000C0000) PiStatusCode.h 　
11197
 EFI_SOFTWARE_IA32_EXCEPTIONEFI_SOFTWARE_IA32_EXCEPTION (EFI_SOFTWARE | 0x000D0000) PiStatusCode.h 　
11198
 EFI_SOFTWARE_IPF_EXCEPTIONEFI_SOFTWARE_IPF_EXCEPTION (EFI_SOFTWARE | 0x000E0000) PiStatusCode.h 　
11199
 EFI_SOFTWARE_PEI_SERVICEEFI_SOFTWARE_PEI_SERVICE (EFI_SOFTWARE | 0x000F0000) PiStatusCode.h 　
11200
 EFI_SOFTWARE_EFI_BOOT_SERVICEEFI_SOFTWARE_EFI_BOOT_SERVICE (EFI_SOFTWARE | 0x00100000) PiStatusCode.h 　
11201
 EFI_SOFTWARE_EFI_RUNTIME_SERVICEFI_SOFTWARE_EFI_RUNTIME_SERVIC (EFI_SOFTWARE | 0x00110000) PiStatusCode.h 　
11202
 EFI_SOFTWARE_EFI_DXE_SERVICEEFI_SOFTWARE_EFI_DXE_SERVICE (EFI_SOFTWARE | 0x00120000) PiStatusCode.h 　
11203
 EFI_SW_PC_INITEFI_SW_PC_INIT 0x00000000 PiStatusCode.h 　
11204
 EFI_SW_PC_LOADEFI_SW_PC_LOAD 0x00000001 PiStatusCode.h 　
11205
 EFI_SW_PC_INIT_BEGINEFI_SW_PC_INIT_BEGIN 0x00000002 PiStatusCode.h 　
11206
 EFI_SW_PC_INIT_ENDEFI_SW_PC_INIT_END 0x00000003 PiStatusCode.h 　
11207
 EFI_SW_PC_AUTHENTICATE_BEGINEFI_SW_PC_AUTHENTICATE_BEGIN 0x00000004 PiStatusCode.h 　
11208
 EFI_SW_PC_AUTHENTICATE_ENDEFI_SW_PC_AUTHENTICATE_END 0x00000005 PiStatusCode.h 　
11209
 EFI_SW_PC_INPUT_WAITEFI_SW_PC_INPUT_WAIT 0x00000006 PiStatusCode.h 　
11210
 EFI_SW_PC_USER_SETUPEFI_SW_PC_USER_SETUP 0x00000007 PiStatusCode.h 　
11211
 EFI_SW_SEC_PC_ENTRY_POINTEFI_SW_SEC_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11212
 EFI_SW_SEC_PC_HANDOFF_TO_NEXTEFI_SW_SEC_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11213
 EFI_SW_PEI_CORE_PC_ENTRY_POINTEFI_SW_PEI_CORE_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11214
 EFI_SW_PEI_CORE_PC_HANDOFF_TO_NEFI_SW_PEI_CORE_PC_HANDOFF_TO_N (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11215
 EFI_SW_PEI_CORE_PC_RETURN_TO_LAEFI_SW_PEI_CORE_PC_RETURN_TO_LA (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11216
 EFI_SW_PEIM_PC_RECOVERY_BEGINEFI_SW_PEIM_PC_RECOVERY_BEGIN (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11217
 EFI_SW_PEIM_PC_CAPSULE_LOADEFI_SW_PEIM_PC_CAPSULE_LOAD (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11218
 EFI_SW_PEIM_PC_CAPSULE_STARTEFI_SW_PEIM_PC_CAPSULE_START (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11219
 EFI_SW_PEIM_PC_RECOVERY_USEREFI_SW_PEIM_PC_RECOVERY_USER (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11220
 EFI_SW_PEIM_PC_RECOVERY_AUTOEFI_SW_PEIM_PC_RECOVERY_AUTO (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11221
 EFI_SW_PEI_PC_S3_BOOT_SCRIPTEFI_SW_PEI_PC_S3_BOOT_SCRIPT (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11222
 EFI_SW_PEI_PC_OS_WAKEEFI_SW_PEI_PC_OS_WAKE (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11223
 EFI_SW_DXE_CORE_PC_ENTRY_POINTEFI_SW_DXE_CORE_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11224
 EFI_SW_DXE_CORE_PC_HANDOFF_TO_NEFI_SW_DXE_CORE_PC_HANDOFF_TO_N (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11225
 EFI_SW_DXE_CORE_PC_RETURN_TO_LAEFI_SW_DXE_CORE_PC_RETURN_TO_LA (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11226
 EFI_SW_DXE_CORE_PC_START_DRIVEREFI_SW_DXE_CORE_PC_START_DRIVER (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11227
 EFI_SW_DXE_CORE_PC_ARCH_READYEFI_SW_DXE_CORE_PC_ARCH_READY (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11228
 EFI_SW_DXE_BS_PC_LEGACY_OPROM_IEFI_SW_DXE_BS_PC_LEGACY_OPROM_I (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11229
 EFI_SW_DXE_BS_PC_READY_TO_BOOT_EFI_SW_DXE_BS_PC_READY_TO_BOOT_ (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11230
 EFI_SW_DXE_BS_PC_LEGACY_BOOT_EVEFI_SW_DXE_BS_PC_LEGACY_BOOT_EV (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11231
 EFI_SW_DXE_BS_PC_EXIT_BOOT_SERVEFI_SW_DXE_BS_PC_EXIT_BOOT_SERV (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11232
 EFI_SW_DXE_BS_PC_VIRTUAL_ADDRESEFI_SW_DXE_BS_PC_VIRTUAL_ADDRES (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11233
 EFI_SW_RT_PC_ENTRY_POINTEFI_SW_RT_PC_ENTRY_POINT (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11234
 EFI_SW_RT_PC_HANDOFF_TO_NEXTEFI_SW_RT_PC_HANDOFF_TO_NEXT (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11235
 EFI_SW_RT_PC_RETURN_TO_LASTEFI_SW_RT_PC_RETURN_TO_LAST (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11236
 EFI_SW_PS_PC_INSTALL_PPIEFI_SW_PS_PC_INSTALL_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11237
 EFI_SW_PS_PC_REINSTALL_PPIEFI_SW_PS_PC_REINSTALL_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11238
 EFI_SW_PS_PC_LOCATE_PPIEFI_SW_PS_PC_LOCATE_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11239
 EFI_SW_PS_PC_NOTIFY_PPIEFI_SW_PS_PC_NOTIFY_PPI (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11240
 EFI_SW_PS_PC_GET_BOOT_MODEEFI_SW_PS_PC_GET_BOOT_MODE (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11241
 EFI_SW_PS_PC_SET_BOOT_MODEEFI_SW_PS_PC_SET_BOOT_MODE (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11242
 EFI_SW_PS_PC_GET_HOB_LISTEFI_SW_PS_PC_GET_HOB_LIST (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11243
 EFI_SW_PS_PC_CREATE_HOBEFI_SW_PS_PC_CREATE_HOB (EFI_SUBCLASS_SPECIFIC | 0x00000007) PiStatusCode.h 　
11244
 EFI_SW_PS_PC_FFS_FIND_NEXT_VOLUEFI_SW_PS_PC_FFS_FIND_NEXT_VOLU (EFI_SUBCLASS_SPECIFIC | 0x00000008) PiStatusCode.h 　
11245
 EFI_SW_PS_PC_FFS_FIND_NEXT_FILEEFI_SW_PS_PC_FFS_FIND_NEXT_FILE (EFI_SUBCLASS_SPECIFIC | 0x00000009) PiStatusCode.h 　
11246
 EFI_SW_PS_PC_FFS_FIND_SECTION_DEFI_SW_PS_PC_FFS_FIND_SECTION_D (EFI_SUBCLASS_SPECIFIC | 0x0000000A) PiStatusCode.h 　
11247
 EFI_SW_PS_PC_INSTALL_PEI_MEMORYEFI_SW_PS_PC_INSTALL_PEI_MEMORY (EFI_SUBCLASS_SPECIFIC | 0x0000000B) PiStatusCode.h 　
11248
 EFI_SW_PS_PC_ALLOCATE_PAGESEFI_SW_PS_PC_ALLOCATE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x0000000C) PiStatusCode.h 　
11249
 EFI_SW_PS_PC_ALLOCATE_POOLEFI_SW_PS_PC_ALLOCATE_POOL (EFI_SUBCLASS_SPECIFIC | 0x0000000D) PiStatusCode.h 　
11250
 EFI_SW_PS_PC_COPY_MEMEFI_SW_PS_PC_COPY_MEM (EFI_SUBCLASS_SPECIFIC | 0x0000000E) PiStatusCode.h 　
11251
 EFI_SW_PS_PC_SET_MEMEFI_SW_PS_PC_SET_MEM (EFI_SUBCLASS_SPECIFIC | 0x0000000F) PiStatusCode.h 　
11252
 EFI_SW_PS_PC_RESET_SYSTEMEFI_SW_PS_PC_RESET_SYSTEM (EFI_SUBCLASS_SPECIFIC | 0x00000010) PiStatusCode.h 　
11253
 EFI_SW_PS_PC_FFS_FIND_FILE_BY_NEFI_SW_PS_PC_FFS_FIND_FILE_BY_N (EFI_SUBCLASS_SPECIFIC | 0x00000013) PiStatusCode.h 　
11254
 EFI_SW_PS_PC_FFS_GET_FILE_INFOEFI_SW_PS_PC_FFS_GET_FILE_INFO (EFI_SUBCLASS_SPECIFIC | 0x00000014) PiStatusCode.h 　
11255
 EFI_SW_PS_PC_FFS_GET_VOLUME_INFEFI_SW_PS_PC_FFS_GET_VOLUME_INF (EFI_SUBCLASS_SPECIFIC | 0x00000015) PiStatusCode.h 　
11256
 EFI_SW_PS_PC_FFS_REGISTER_FOR_SEFI_SW_PS_PC_FFS_REGISTER_FOR_S (EFI_SUBCLASS_SPECIFIC | 0x00000016) PiStatusCode.h 　
11257
 EFI_SW_BS_PC_RAISE_TPLEFI_SW_BS_PC_RAISE_TPL (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11258
 EFI_SW_BS_PC_RESTORE_TPLEFI_SW_BS_PC_RESTORE_TPL (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11259
 EFI_SW_BS_PC_ALLOCATE_PAGESEFI_SW_BS_PC_ALLOCATE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11260
 EFI_SW_BS_PC_FREE_PAGESEFI_SW_BS_PC_FREE_PAGES (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11261
 EFI_SW_BS_PC_GET_MEMORY_MAPEFI_SW_BS_PC_GET_MEMORY_MAP (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11262
 EFI_SW_BS_PC_ALLOCATE_POOLEFI_SW_BS_PC_ALLOCATE_POOL (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11263
 EFI_SW_BS_PC_FREE_POOLEFI_SW_BS_PC_FREE_POOL (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11264
 EFI_SW_BS_PC_CREATE_EVENTEFI_SW_BS_PC_CREATE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000007) PiStatusCode.h 　
11265
 EFI_SW_BS_PC_SET_TIMEREFI_SW_BS_PC_SET_TIMER (EFI_SUBCLASS_SPECIFIC | 0x00000008) PiStatusCode.h 　
11266
 EFI_SW_BS_PC_WAIT_FOR_EVENTEFI_SW_BS_PC_WAIT_FOR_EVENT (EFI_SUBCLASS_SPECIFIC | 0x00000009) PiStatusCode.h 　
11267
 EFI_SW_BS_PC_SIGNAL_EVENTEFI_SW_BS_PC_SIGNAL_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000A) PiStatusCode.h 　
11268
 EFI_SW_BS_PC_CLOSE_EVENTEFI_SW_BS_PC_CLOSE_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000B) PiStatusCode.h 　
11269
 EFI_SW_BS_PC_CHECK_EVENTEFI_SW_BS_PC_CHECK_EVENT (EFI_SUBCLASS_SPECIFIC | 0x0000000C) PiStatusCode.h 　
11270
 EFI_SW_BS_PC_INSTALL_PROTOCOL_IEFI_SW_BS_PC_INSTALL_PROTOCOL_I (EFI_SUBCLASS_SPECIFIC | 0x0000000D) PiStatusCode.h 　
11271
 EFI_SW_BS_PC_REINSTALL_PROTOCOLEFI_SW_BS_PC_REINSTALL_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x0000000E) PiStatusCode.h 　
11272
 EFI_SW_BS_PC_UNINSTALL_PROTOCOLEFI_SW_BS_PC_UNINSTALL_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x0000000F) PiStatusCode.h 　
11273
 EFI_SW_BS_PC_HANDLE_PROTOCOLEFI_SW_BS_PC_HANDLE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000010) PiStatusCode.h 　
11274
 EFI_SW_BS_PC_PC_HANDLE_PROTOCOLEFI_SW_BS_PC_PC_HANDLE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000011) PiStatusCode.h 　
11275
 EFI_SW_BS_PC_REGISTER_PROTOCOL_EFI_SW_BS_PC_REGISTER_PROTOCOL_ (EFI_SUBCLASS_SPECIFIC | 0x00000012) PiStatusCode.h 　
11276
 EFI_SW_BS_PC_LOCATE_HANDLEEFI_SW_BS_PC_LOCATE_HANDLE (EFI_SUBCLASS_SPECIFIC | 0x00000013) PiStatusCode.h 　
11277
 EFI_SW_BS_PC_INSTALL_CONFIGURATEFI_SW_BS_PC_INSTALL_CONFIGURAT (EFI_SUBCLASS_SPECIFIC | 0x00000014) PiStatusCode.h 　
11278
 EFI_SW_BS_PC_LOAD_IMAGEEFI_SW_BS_PC_LOAD_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000015) PiStatusCode.h 　
11279
 EFI_SW_BS_PC_START_IMAGEEFI_SW_BS_PC_START_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000016) PiStatusCode.h 　
11280
 EFI_SW_BS_PC_EXITEFI_SW_BS_PC_EXIT (EFI_SUBCLASS_SPECIFIC | 0x00000017) PiStatusCode.h 　
11281
 EFI_SW_BS_PC_UNLOAD_IMAGEEFI_SW_BS_PC_UNLOAD_IMAGE (EFI_SUBCLASS_SPECIFIC | 0x00000018) PiStatusCode.h 　
11282
 EFI_SW_BS_PC_EXIT_BOOT_SERVICESEFI_SW_BS_PC_EXIT_BOOT_SERVICES (EFI_SUBCLASS_SPECIFIC | 0x00000019) PiStatusCode.h 　
11283
 EFI_SW_BS_PC_GET_NEXT_MONOTONICEFI_SW_BS_PC_GET_NEXT_MONOTONIC (EFI_SUBCLASS_SPECIFIC | 0x0000001A) PiStatusCode.h 　
11284
 EFI_SW_BS_PC_STALLEFI_SW_BS_PC_STALL (EFI_SUBCLASS_SPECIFIC | 0x0000001B) PiStatusCode.h 　
11285
 EFI_SW_BS_PC_SET_WATCHDOG_TIMEREFI_SW_BS_PC_SET_WATCHDOG_TIMER (EFI_SUBCLASS_SPECIFIC | 0x0000001C) PiStatusCode.h 　
11286
 EFI_SW_BS_PC_CONNECT_CONTROLLEREFI_SW_BS_PC_CONNECT_CONTROLLER (EFI_SUBCLASS_SPECIFIC | 0x0000001D) PiStatusCode.h 　
11287
 EFI_SW_BS_PC_DISCONNECT_CONTROLEFI_SW_BS_PC_DISCONNECT_CONTROL (EFI_SUBCLASS_SPECIFIC | 0x0000001E) PiStatusCode.h 　
11288
 EFI_SW_BS_PC_OPEN_PROTOCOLEFI_SW_BS_PC_OPEN_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x0000001F) PiStatusCode.h 　
11289
 EFI_SW_BS_PC_CLOSE_PROTOCOLEFI_SW_BS_PC_CLOSE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000020) PiStatusCode.h 　
11290
 EFI_SW_BS_PC_OPEN_PROTOCOL_INFOEFI_SW_BS_PC_OPEN_PROTOCOL_INFO (EFI_SUBCLASS_SPECIFIC | 0x00000021) PiStatusCode.h 　
11291
 EFI_SW_BS_PC_PROTOCOLS_PER_HANDEFI_SW_BS_PC_PROTOCOLS_PER_HAND (EFI_SUBCLASS_SPECIFIC | 0x00000022) PiStatusCode.h 　
11292
 EFI_SW_BS_PC_LOCATE_HANDLE_BUFFEFI_SW_BS_PC_LOCATE_HANDLE_BUFF (EFI_SUBCLASS_SPECIFIC | 0x00000023) PiStatusCode.h 　
11293
 EFI_SW_BS_PC_LOCATE_PROTOCOLEFI_SW_BS_PC_LOCATE_PROTOCOL (EFI_SUBCLASS_SPECIFIC | 0x00000024) PiStatusCode.h 　
11294
 EFI_SW_BS_PC_INSTALL_MULTIPLE_IEFI_SW_BS_PC_INSTALL_MULTIPLE_I (EFI_SUBCLASS_SPECIFIC | 0x00000025) PiStatusCode.h 　
11295
 EFI_SW_BS_PC_UNINSTALL_MULTIPLEEFI_SW_BS_PC_UNINSTALL_MULTIPLE (EFI_SUBCLASS_SPECIFIC | 0x00000026) PiStatusCode.h 　
11296
 EFI_SW_BS_PC_CALCULATE_CRC_32EFI_SW_BS_PC_CALCULATE_CRC_32 (EFI_SUBCLASS_SPECIFIC | 0x00000027) PiStatusCode.h 　
11297
 EFI_SW_BS_PC_COPY_MEMEFI_SW_BS_PC_COPY_MEM (EFI_SUBCLASS_SPECIFIC | 0x00000028) PiStatusCode.h 　
11298
 EFI_SW_BS_PC_SET_MEMEFI_SW_BS_PC_SET_MEM (EFI_SUBCLASS_SPECIFIC | 0x00000029) PiStatusCode.h 　
11299
 EFI_SW_BS_PC_CREATE_EVENT_EXEFI_SW_BS_PC_CREATE_EVENT_EX (EFI_SUBCLASS_SPECIFIC | 0x0000002A) PiStatusCode.h 　
11300
 EFI_SW_RS_PC_GET_TIMEEFI_SW_RS_PC_GET_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11301
 EFI_SW_RS_PC_SET_TIMEEFI_SW_RS_PC_SET_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11302
 EFI_SW_RS_PC_GET_WAKEUP_TIMEEFI_SW_RS_PC_GET_WAKEUP_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11303
 EFI_SW_RS_PC_SET_WAKEUP_TIMEEFI_SW_RS_PC_SET_WAKEUP_TIME (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11304
 EFI_SW_RS_PC_SET_VIRTUAL_ADDRESEFI_SW_RS_PC_SET_VIRTUAL_ADDRES (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11305
 EFI_SW_RS_PC_CONVERT_POINTEREFI_SW_RS_PC_CONVERT_POINTER (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11306
 EFI_SW_RS_PC_GET_VARIABLEEFI_SW_RS_PC_GET_VARIABLE (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11307
 EFI_SW_RS_PC_GET_NEXT_VARIABLE_EFI_SW_RS_PC_GET_NEXT_VARIABLE_ (EFI_SUBCLASS_SPECIFIC | 0x00000007) PiStatusCode.h 　
11308
 EFI_SW_RS_PC_SET_VARIABLEEFI_SW_RS_PC_SET_VARIABLE (EFI_SUBCLASS_SPECIFIC | 0x00000008) PiStatusCode.h 　
11309
 EFI_SW_RS_PC_GET_NEXT_HIGH_MONOEFI_SW_RS_PC_GET_NEXT_HIGH_MONO (EFI_SUBCLASS_SPECIFIC | 0x00000009) PiStatusCode.h 　
11310
 EFI_SW_RS_PC_RESET_SYSTEMEFI_SW_RS_PC_RESET_SYSTEM (EFI_SUBCLASS_SPECIFIC | 0x0000000A) PiStatusCode.h 　
11311
 EFI_SW_RS_PC_UPDATE_CAPSULEEFI_SW_RS_PC_UPDATE_CAPSULE (EFI_SUBCLASS_SPECIFIC | 0x0000000B) PiStatusCode.h 　
11312
 EFI_SW_RS_PC_QUERY_CAPSULE_CAPAEFI_SW_RS_PC_QUERY_CAPSULE_CAPA (EFI_SUBCLASS_SPECIFIC | 0x0000000C) PiStatusCode.h 　
11313
 EFI_SW_RS_PC_QUERY_VARIABLE_INFEFI_SW_RS_PC_QUERY_VARIABLE_INF (EFI_SUBCLASS_SPECIFIC | 0x0000000D) PiStatusCode.h 　
11314
 EFI_SW_DS_PC_ADD_MEMORY_SPACEEFI_SW_DS_PC_ADD_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11315
 EFI_SW_DS_PC_ALLOCATE_MEMORY_SPEFI_SW_DS_PC_ALLOCATE_MEMORY_SP (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11316
 EFI_SW_DS_PC_FREE_MEMORY_SPACEEFI_SW_DS_PC_FREE_MEMORY_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11317
 EFI_SW_DS_PC_REMOVE_MEMORY_SPACEFI_SW_DS_PC_REMOVE_MEMORY_SPAC (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11318
 EFI_SW_DS_PC_GET_MEMORY_SPACE_DEFI_SW_DS_PC_GET_MEMORY_SPACE_D (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11319
 EFI_SW_DS_PC_SET_MEMORY_SPACE_AEFI_SW_DS_PC_SET_MEMORY_SPACE_A (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11320
 EFI_SW_DS_PC_GET_MEMORY_SPACE_MEFI_SW_DS_PC_GET_MEMORY_SPACE_M (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11321
 EFI_SW_DS_PC_ADD_IO_SPACEEFI_SW_DS_PC_ADD_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000007) PiStatusCode.h 　
11322
 EFI_SW_DS_PC_ALLOCATE_IO_SPACEEFI_SW_DS_PC_ALLOCATE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000008) PiStatusCode.h 　
11323
 EFI_SW_DS_PC_FREE_IO_SPACEEFI_SW_DS_PC_FREE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x00000009) PiStatusCode.h 　
11324
 EFI_SW_DS_PC_REMOVE_IO_SPACEEFI_SW_DS_PC_REMOVE_IO_SPACE (EFI_SUBCLASS_SPECIFIC | 0x0000000A) PiStatusCode.h 　
11325
 EFI_SW_DS_PC_GET_IO_SPACE_DESCREFI_SW_DS_PC_GET_IO_SPACE_DESCR (EFI_SUBCLASS_SPECIFIC | 0x0000000B) PiStatusCode.h 　
11326
 EFI_SW_DS_PC_GET_IO_SPACE_MAPEFI_SW_DS_PC_GET_IO_SPACE_MAP (EFI_SUBCLASS_SPECIFIC | 0x0000000C) PiStatusCode.h 　
11327
 EFI_SW_DS_PC_DISPATCHEFI_SW_DS_PC_DISPATCH (EFI_SUBCLASS_SPECIFIC | 0x0000000D) PiStatusCode.h 　
11328
 EFI_SW_DS_PC_SCHEDULEEFI_SW_DS_PC_SCHEDULE (EFI_SUBCLASS_SPECIFIC | 0x0000000E) PiStatusCode.h 　
11329
 EFI_SW_DS_PC_TRUSTEFI_SW_DS_PC_TRUST (EFI_SUBCLASS_SPECIFIC | 0x0000000F) PiStatusCode.h 　
11330
 EFI_SW_DS_PC_PROCESS_FIRMWARE_VEFI_SW_DS_PC_PROCESS_FIRMWARE_V (EFI_SUBCLASS_SPECIFIC | 0x00000010) PiStatusCode.h 　
11331
 EFI_SW_EC_NON_SPECIFICEFI_SW_EC_NON_SPECIFIC 0x00000000 PiStatusCode.h 　
11332
 EFI_SW_EC_LOAD_ERROREFI_SW_EC_LOAD_ERROR 0x00000001 PiStatusCode.h 　
11333
 EFI_SW_EC_INVALID_PARAMETEREFI_SW_EC_INVALID_PARAMETER 0x00000002 PiStatusCode.h 　
11334
 EFI_SW_EC_UNSUPPORTEDEFI_SW_EC_UNSUPPORTED 0x00000003 PiStatusCode.h 　
11335
 EFI_SW_EC_INVALID_BUFFEREFI_SW_EC_INVALID_BUFFER 0x00000004 PiStatusCode.h 　
11336
 EFI_SW_EC_OUT_OF_RESOURCESEFI_SW_EC_OUT_OF_RESOURCES 0x00000005 PiStatusCode.h 　
11337
 EFI_SW_EC_ABORTEDEFI_SW_EC_ABORTED 0x00000006 PiStatusCode.h 　
11338
 EFI_SW_EC_ILLEGAL_SOFTWARE_STATEFI_SW_EC_ILLEGAL_SOFTWARE_STAT 0x00000007 PiStatusCode.h 　
11339
 EFI_SW_EC_ILLEGAL_HARDWARE_STATEFI_SW_EC_ILLEGAL_HARDWARE_STAT 0x00000008 PiStatusCode.h 　
11340
 EFI_SW_EC_START_ERROREFI_SW_EC_START_ERROR 0x00000009 PiStatusCode.h 　
11341
 EFI_SW_EC_BAD_DATE_TIMEEFI_SW_EC_BAD_DATE_TIME 0x0000000A PiStatusCode.h 　
11342
 EFI_SW_EC_CFG_INVALIDEFI_SW_EC_CFG_INVALID 0x0000000B PiStatusCode.h 　
11343
 EFI_SW_EC_CFG_CLR_REQUESTEFI_SW_EC_CFG_CLR_REQUEST 0x0000000C PiStatusCode.h 　
11344
 EFI_SW_EC_CFG_DEFAULTEFI_SW_EC_CFG_DEFAULT 0x0000000D PiStatusCode.h 　
11345
 EFI_SW_EC_PWD_INVALIDEFI_SW_EC_PWD_INVALID 0x0000000E PiStatusCode.h 　
11346
 EFI_SW_EC_PWD_CLR_REQUESTEFI_SW_EC_PWD_CLR_REQUEST 0x0000000F PiStatusCode.h 　
11347
 EFI_SW_EC_PWD_CLEAREDEFI_SW_EC_PWD_CLEARED 0x00000010 PiStatusCode.h 　
11348
 EFI_SW_EC_EVENT_LOG_FULLEFI_SW_EC_EVENT_LOG_FULL 0x00000011 PiStatusCode.h 　
11349
 EFI_SW_PEI_CORE_EC_DXE_CORRUPTEFI_SW_PEI_CORE_EC_DXE_CORRUPT (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11350
 EFI_SW_PEI_CORE_EC_DXEIPL_NOT_FEFI_SW_PEI_CORE_EC_DXEIPL_NOT_F (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11351
 EFI_SW_PEI_CORE_EC_MEMORY_NOT_IEFI_SW_PEI_CORE_EC_MEMORY_NOT_I (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11352
 EFI_SW_PEIM_EC_NO_RECOVERY_CAPSEFI_SW_PEIM_EC_NO_RECOVERY_CAPS (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11353
 EFI_SW_PEIM_EC_INVALID_CAPSULE_EFI_SW_PEIM_EC_INVALID_CAPSULE_ (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11354
 EFI_SW_PEI_EC_S3_RESUME_PPI_NOTEFI_SW_PEI_EC_S3_RESUME_PPI_NOT (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11355
 EFI_SW_PEI_EC_S3_BOOT_SCRIPT_EREFI_SW_PEI_EC_S3_BOOT_SCRIPT_ER (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11356
 EFI_SW_PEI_EC_S3_OS_WAKE_ERROREFI_SW_PEI_EC_S3_OS_WAKE_ERROR (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11357
 EFI_SW_PEI_EC_S3_RESUME_FAILEDEFI_SW_PEI_EC_S3_RESUME_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000005) PiStatusCode.h 　
11358
 EFI_SW_PEI_EC_RECOVERY_PPI_NOT_EFI_SW_PEI_EC_RECOVERY_PPI_NOT_ (EFI_SUBCLASS_SPECIFIC | 0x00000006) PiStatusCode.h 　
11359
 EFI_SW_PEI_EC_RECOVERY_FAILEDEFI_SW_PEI_EC_RECOVERY_FAILED (EFI_SUBCLASS_SPECIFIC | 0x00000007) PiStatusCode.h 　
11360
 EFI_SW_DXE_CORE_EC_NO_ARCHEFI_SW_DXE_CORE_EC_NO_ARCH (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11361
 EFI_SW_DXE_BS_EC_LEGACY_OPROM_NEFI_SW_DXE_BS_EC_LEGACY_OPROM_N (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11362
 EFI_SW_DXE_BS_EC_INVALID_PASSWOEFI_SW_DXE_BS_EC_INVALID_PASSWO (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11363
 EFI_SW_DXE_BS_EC_BOOT_OPTION_LOEFI_SW_DXE_BS_EC_BOOT_OPTION_LO (EFI_SUBCLASS_SPECIFIC | 0x00000002) PiStatusCode.h 　
11364
 EFI_SW_DXE_BS_EC_BOOT_OPTION_FAEFI_SW_DXE_BS_EC_BOOT_OPTION_FA (EFI_SUBCLASS_SPECIFIC | 0x00000003) PiStatusCode.h 　
11365
 EFI_SW_DXE_BS_EC_INVALID_IDE_PAEFI_SW_DXE_BS_EC_INVALID_IDE_PA (EFI_SUBCLASS_SPECIFIC | 0x00000004) PiStatusCode.h 　
11366
 EFI_SW_EC_EBC_UNDEFINEDEFI_SW_EC_EBC_UNDEFINED 0x00000000 PiStatusCode.h 　
11367
 EFI_SW_EC_EBC_DIVIDE_ERROREFI_SW_EC_EBC_DIVIDE_ERROR EXCEPT_EBC_DIVIDE_ERROR PiStatusCode.h 　
11368
 EFI_SW_EC_EBC_DEBUGEFI_SW_EC_EBC_DEBUG EXCEPT_EBC_DEBUG PiStatusCode.h 　
11369
 EFI_SW_EC_EBC_BREAKPOINTEFI_SW_EC_EBC_BREAKPOINT EXCEPT_EBC_BREAKPOINT PiStatusCode.h 　
11370
 EFI_SW_EC_EBC_OVERFLOWEFI_SW_EC_EBC_OVERFLOW EXCEPT_EBC_OVERFLOW PiStatusCode.h 　
11371
 EFI_SW_EC_EBC_INVALID_OPCODEEFI_SW_EC_EBC_INVALID_OPCODE EXCEPT_EBC_INVALID_OPCODE PiStatusCode.h 　
11372
 EFI_SW_EC_EBC_STACK_FAULTEFI_SW_EC_EBC_STACK_FAULT EXCEPT_EBC_STACK_FAULT PiStatusCode.h 　
11373
 EFI_SW_EC_EBC_ALIGNMENT_CHECKEFI_SW_EC_EBC_ALIGNMENT_CHECK EXCEPT_EBC_ALIGNMENT_CHECK PiStatusCode.h 　
11374
 EFI_SW_EC_EBC_INSTRUCTION_ENCODEFI_SW_EC_EBC_INSTRUCTION_ENCOD EXCEPT_EBC_INSTRUCTION_ENCODING PiStatusCode.h 　
11375
 EFI_SW_EC_EBC_BAD_BREAKEFI_SW_EC_EBC_BAD_BREAK EXCEPT_EBC_BAD_BREAK PiStatusCode.h 　
11376
 EFI_SW_EC_EBC_STEPEFI_SW_EC_EBC_STEP EXCEPT_EBC_STEP PiStatusCode.h 　
11377
 EFI_SW_EC_IA32_DIVIDE_ERROREFI_SW_EC_IA32_DIVIDE_ERROR EXCEPT_IA32_DIVIDE_ERROR PiStatusCode.h 　
11378
 EFI_SW_EC_IA32_DEBUGEFI_SW_EC_IA32_DEBUG EXCEPT_IA32_DEBUG PiStatusCode.h 　
11379
 EFI_SW_EC_IA32_NMIEFI_SW_EC_IA32_NMI EXCEPT_IA32_NMI PiStatusCode.h 　
11380
 EFI_SW_EC_IA32_BREAKPOINTEFI_SW_EC_IA32_BREAKPOINT EXCEPT_IA32_BREAKPOINT PiStatusCode.h 　
11381
 EFI_SW_EC_IA32_OVERFLOWEFI_SW_EC_IA32_OVERFLOW EXCEPT_IA32_OVERFLOW PiStatusCode.h 　
11382
 EFI_SW_EC_IA32_BOUNDEFI_SW_EC_IA32_BOUND EXCEPT_IA32_BOUND PiStatusCode.h 　
11383
 EFI_SW_EC_IA32_INVALID_OPCODEEFI_SW_EC_IA32_INVALID_OPCODE EXCEPT_IA32_INVALID_OPCODE PiStatusCode.h 　
11384
 EFI_SW_EC_IA32_DOUBLE_FAULTEFI_SW_EC_IA32_DOUBLE_FAULT EXCEPT_IA32_DOUBLE_FAULT PiStatusCode.h 　
11385
 EFI_SW_EC_IA32_INVALID_TSSEFI_SW_EC_IA32_INVALID_TSS EXCEPT_IA32_INVALID_TSS PiStatusCode.h 　
11386
 EFI_SW_EC_IA32_SEG_NOT_PRESENTEFI_SW_EC_IA32_SEG_NOT_PRESENT EXCEPT_IA32_SEG_NOT_PRESENT PiStatusCode.h 　
11387
 EFI_SW_EC_IA32_STACK_FAULTEFI_SW_EC_IA32_STACK_FAULT EXCEPT_IA32_STACK_FAULT PiStatusCode.h 　
11388
 EFI_SW_EC_IA32_GP_FAULTEFI_SW_EC_IA32_GP_FAULT EXCEPT_IA32_GP_FAULT PiStatusCode.h 　
11389
 EFI_SW_EC_IA32_PAGE_FAULTEFI_SW_EC_IA32_PAGE_FAULT EXCEPT_IA32_PAGE_FAULT PiStatusCode.h 　
11390
 EFI_SW_EC_IA32_FP_ERROREFI_SW_EC_IA32_FP_ERROR EXCEPT_IA32_FP_ERROR PiStatusCode.h 　
11391
 EFI_SW_EC_IA32_ALIGNMENT_CHECKEFI_SW_EC_IA32_ALIGNMENT_CHECK EXCEPT_IA32_ALIGNMENT_CHECK PiStatusCode.h 　
11392
 EFI_SW_EC_IA32_MACHINE_CHECKEFI_SW_EC_IA32_MACHINE_CHECK EXCEPT_IA32_MACHINE_CHECK PiStatusCode.h 　
11393
 EFI_SW_EC_IA32_SIMDEFI_SW_EC_IA32_SIMD EXCEPT_IA32_SIMD PiStatusCode.h 　
11394
 EFI_SW_EC_IPF_ALT_DTLBEFI_SW_EC_IPF_ALT_DTLB EXCEPT_IPF_ALT_DTLB PiStatusCode.h 　
11395
 EFI_SW_EC_IPF_DNESTED_TLBEFI_SW_EC_IPF_DNESTED_TLB EXCEPT_IPF_DNESTED_TLB PiStatusCode.h 　
11396
 EFI_SW_EC_IPF_BREAKPOINTEFI_SW_EC_IPF_BREAKPOINT EXCEPT_IPF_BREAKPOINT PiStatusCode.h 　
11397
 EFI_SW_EC_IPF_EXTERNAL_INTERRUPEFI_SW_EC_IPF_EXTERNAL_INTERRUP EXCEPT_IPF_EXTERNAL_INTERRUPT PiStatusCode.h 　
11398
 EFI_SW_EC_IPF_GEN_EXCEPTEFI_SW_EC_IPF_GEN_EXCEPT EXCEPT_IPF_GEN_EXCEPT PiStatusCode.h 　
11399
 EFI_SW_EC_IPF_NAT_CONSUMPTIONEFI_SW_EC_IPF_NAT_CONSUMPTION EXCEPT_IPF_NAT_CONSUMPTION PiStatusCode.h 　
11400
 EFI_SW_EC_IPF_DEBUG_EXCEPTEFI_SW_EC_IPF_DEBUG_EXCEPT EXCEPT_IPF_DEBUG_EXCEPT PiStatusCode.h 　
11401
 EFI_SW_EC_IPF_UNALIGNED_ACCESSEFI_SW_EC_IPF_UNALIGNED_ACCESS EXCEPT_IPF_UNALIGNED_ACCESS PiStatusCode.h 　
11402
 EFI_SW_EC_IPF_FP_FAULTEFI_SW_EC_IPF_FP_FAULT EXCEPT_IPF_FP_FAULT PiStatusCode.h 　
11403
 EFI_SW_EC_IPF_FP_TRAPEFI_SW_EC_IPF_FP_TRAP EXCEPT_IPF_FP_TRAP PiStatusCode.h 　
11404
 EFI_SW_EC_IPF_TAKEN_BRANCHEFI_SW_EC_IPF_TAKEN_BRANCH EXCEPT_IPF_TAKEN_BRANCH PiStatusCode.h 　
11405
 EFI_SW_EC_IPF_SINGLE_STEPEFI_SW_EC_IPF_SINGLE_STEP EXCEPT_IPF_SINGLE_STEP PiStatusCode.h 　
11406
 EFI_SW_PS_EC_RESET_NOT_AVAILABLEFI_SW_PS_EC_RESET_NOT_AVAILABL (EFI_SUBCLASS_SPECIFIC | 0x00000000) PiStatusCode.h 　
11407
 EFI_SW_PS_EC_MEMORY_INSTALLED_TEFI_SW_PS_EC_MEMORY_INSTALLED_T (EFI_SUBCLASS_SPECIFIC | 0x00000001) PiStatusCode.h 　
11408
 EFI_COMPONENT_NAME2_PROTOCOL_GUEFI_COMPONENT_NAME2_PROTOCOL_GU {0x6a7a5cff, 0xe8d9, 0x4f70, { 0xba, 0xda, 0x75, 0xab, 0x30, 0x25, 0xce, 0x14 } } ComponentName2.h 　
11409
 EFI_CPU_ARCH_PROTOCOL_GUIDEFI_CPU_ARCH_PROTOCOL_GUID { 0x26baccb1, 0x6f42, 0x11d4, {0xbc, 0xe7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } } Cpu.h 　
11410
 EFI_CPU_IO_PROTOCOL_GUIDEFI_CPU_IO_PROTOCOL_GUID { \ 0xB0732526, 0x38C8, 0x4b40, {0x88, 0x77, 0x61, 0xC7, 0xB0, 0x6A, 0xAC, 0x45 } \ } CpuIo.h 　
11411
 EFI_CPU_IO2_PROTOCOL_GUIDEFI_CPU_IO2_PROTOCOL_GUID { \ 0xad61f191, 0xae5f, 0x4c0e, {0xb9, 0xfa, 0xe8, 0x69, 0xd2, 0x88, 0xc6, 0x4f} \ } CpuIo2.h 　
11412
 EFI_DEBUG_SUPPORT_PROTOCOL_GUIDEFI_DEBUG_SUPPORT_PROTOCOL_GUID { \ 0x2755590C, 0x6F3C, 0x42FA, {0x9E, 0xA4, 0xA3, 0xBA, 0x54, 0x3C, 0xDA, 0x25 } \ } DebugSupport.h 　
11413
 EXCEPT_IA32_DIVIDE_ERROREXCEPT_IA32_DIVIDE_ERROR 0 DebugSupport.h 　
11414
 EXCEPT_IA32_DEBUGEXCEPT_IA32_DEBUG 1 DebugSupport.h 　
11415
 EXCEPT_IA32_NMIEXCEPT_IA32_NMI 2 DebugSupport.h 　
11416
 EXCEPT_IA32_BREAKPOINTEXCEPT_IA32_BREAKPOINT 3 DebugSupport.h 　
11417
 EXCEPT_IA32_OVERFLOWEXCEPT_IA32_OVERFLOW 4 DebugSupport.h 　
11418
 EXCEPT_IA32_BOUNDEXCEPT_IA32_BOUND 5 DebugSupport.h 　
11419
 EXCEPT_IA32_INVALID_OPCODEEXCEPT_IA32_INVALID_OPCODE 6 DebugSupport.h 　
11420
 EXCEPT_IA32_DOUBLE_FAULTEXCEPT_IA32_DOUBLE_FAULT 8 DebugSupport.h 　
11421
 EXCEPT_IA32_INVALID_TSSEXCEPT_IA32_INVALID_TSS 10 DebugSupport.h 　
11422
 EXCEPT_IA32_SEG_NOT_PRESENTEXCEPT_IA32_SEG_NOT_PRESENT 11 DebugSupport.h 　
11423
 EXCEPT_IA32_STACK_FAULTEXCEPT_IA32_STACK_FAULT 12 DebugSupport.h 　
11424
 EXCEPT_IA32_GP_FAULTEXCEPT_IA32_GP_FAULT 13 DebugSupport.h 　
11425
 EXCEPT_IA32_PAGE_FAULTEXCEPT_IA32_PAGE_FAULT 14 DebugSupport.h 　
11426
 EXCEPT_IA32_FP_ERROREXCEPT_IA32_FP_ERROR 16 DebugSupport.h 　
11427
 EXCEPT_IA32_ALIGNMENT_CHECKEXCEPT_IA32_ALIGNMENT_CHECK 17 DebugSupport.h 　
11428
 EXCEPT_IA32_MACHINE_CHECKEXCEPT_IA32_MACHINE_CHECK 18 DebugSupport.h 　
11429
 EXCEPT_IA32_SIMDEXCEPT_IA32_SIMD 19 DebugSupport.h 　
11430
 EXCEPT_X64_DIVIDE_ERROREXCEPT_X64_DIVIDE_ERROR 0 DebugSupport.h 　
11431
 EXCEPT_X64_DEBUGEXCEPT_X64_DEBUG 1 DebugSupport.h 　
11432
 EXCEPT_X64_NMIEXCEPT_X64_NMI 2 DebugSupport.h 　
11433
 EXCEPT_X64_BREAKPOINTEXCEPT_X64_BREAKPOINT 3 DebugSupport.h 　
11434
 EXCEPT_X64_OVERFLOWEXCEPT_X64_OVERFLOW 4 DebugSupport.h 　
11435
 EXCEPT_X64_BOUNDEXCEPT_X64_BOUND 5 DebugSupport.h 　
11436
 EXCEPT_X64_INVALID_OPCODEEXCEPT_X64_INVALID_OPCODE 6 DebugSupport.h 　
11437
 EXCEPT_X64_DOUBLE_FAULTEXCEPT_X64_DOUBLE_FAULT 8 DebugSupport.h 　
11438
 EXCEPT_X64_INVALID_TSSEXCEPT_X64_INVALID_TSS 10 DebugSupport.h 　
11439
 EXCEPT_X64_SEG_NOT_PRESENTEXCEPT_X64_SEG_NOT_PRESENT 11 DebugSupport.h 　
11440
 EXCEPT_X64_STACK_FAULTEXCEPT_X64_STACK_FAULT 12 DebugSupport.h 　
11441
 EXCEPT_X64_GP_FAULTEXCEPT_X64_GP_FAULT 13 DebugSupport.h 　
11442
 EXCEPT_X64_PAGE_FAULTEXCEPT_X64_PAGE_FAULT 14 DebugSupport.h 　
11443
 EXCEPT_X64_FP_ERROREXCEPT_X64_FP_ERROR 16 DebugSupport.h 　
11444
 EXCEPT_X64_ALIGNMENT_CHECKEXCEPT_X64_ALIGNMENT_CHECK 17 DebugSupport.h 　
11445
 EXCEPT_X64_MACHINE_CHECKEXCEPT_X64_MACHINE_CHECK 18 DebugSupport.h 　
11446
 EXCEPT_X64_SIMDEXCEPT_X64_SIMD 19 DebugSupport.h 　
11447
 EXCEPT_IPF_VHTP_TRANSLATIONEXCEPT_IPF_VHTP_TRANSLATION 0 DebugSupport.h 　
11448
 EXCEPT_IPF_INSTRUCTION_TLBEXCEPT_IPF_INSTRUCTION_TLB 1 DebugSupport.h 　
11449
 EXCEPT_IPF_DATA_TLBEXCEPT_IPF_DATA_TLB 2 DebugSupport.h 　
11450
 EXCEPT_IPF_ALT_INSTRUCTION_TLBEXCEPT_IPF_ALT_INSTRUCTION_TLB 3 DebugSupport.h 　
11451
 EXCEPT_IPF_ALT_DATA_TLBEXCEPT_IPF_ALT_DATA_TLB 4 DebugSupport.h 　
11452
 EXCEPT_IPF_DATA_NESTED_TLBEXCEPT_IPF_DATA_NESTED_TLB 5 DebugSupport.h 　
11453
 EXCEPT_IPF_INSTRUCTION_KEY_MISSEXCEPT_IPF_INSTRUCTION_KEY_MISS 6 DebugSupport.h 　
11454
 EXCEPT_IPF_DATA_KEY_MISSEDEXCEPT_IPF_DATA_KEY_MISSED 7 DebugSupport.h 　
11455
 EXCEPT_IPF_DIRTY_BITEXCEPT_IPF_DIRTY_BIT 8 DebugSupport.h 　
11456
 EXCEPT_IPF_INSTRUCTION_ACCESS_BEXCEPT_IPF_INSTRUCTION_ACCESS_B 9 DebugSupport.h 　
11457
 EXCEPT_IPF_DATA_ACCESS_BITEXCEPT_IPF_DATA_ACCESS_BIT 10 DebugSupport.h 　
11458
 EXCEPT_IPF_BREAKPOINTEXCEPT_IPF_BREAKPOINT 11 DebugSupport.h 　
11459
 EXCEPT_IPF_EXTERNAL_INTERRUPTEXCEPT_IPF_EXTERNAL_INTERRUPT 12 DebugSupport.h 　
11460
 EXCEPT_IPF_PAGE_NOT_PRESENTEXCEPT_IPF_PAGE_NOT_PRESENT 20 DebugSupport.h 　
11461
 EXCEPT_IPF_KEY_PERMISSIONEXCEPT_IPF_KEY_PERMISSION 21 DebugSupport.h 　
11462
 EXCEPT_IPF_INSTRUCTION_ACCESS_REXCEPT_IPF_INSTRUCTION_ACCESS_R 22 DebugSupport.h 　
11463
 EXCEPT_IPF_DATA_ACCESS_RIGHTSEXCEPT_IPF_DATA_ACCESS_RIGHTS 23 DebugSupport.h 　
11464
 EXCEPT_IPF_GENERAL_EXCEPTIONEXCEPT_IPF_GENERAL_EXCEPTION 24 DebugSupport.h 　
11465
 EXCEPT_IPF_DISABLED_FP_REGISTEREXCEPT_IPF_DISABLED_FP_REGISTER 25 DebugSupport.h 　
11466
 EXCEPT_IPF_NAT_CONSUMPTIONEXCEPT_IPF_NAT_CONSUMPTION 26 DebugSupport.h 　
11467
 EXCEPT_IPF_SPECULATIONEXCEPT_IPF_SPECULATION 27 DebugSupport.h 　
11468
 EXCEPT_IPF_DEBUGEXCEPT_IPF_DEBUG 29 DebugSupport.h 　
11469
 EXCEPT_IPF_UNALIGNED_REFERENCEEXCEPT_IPF_UNALIGNED_REFERENCE 30 DebugSupport.h 　
11470
 EXCEPT_IPF_UNSUPPORTED_DATA_REFEXCEPT_IPF_UNSUPPORTED_DATA_REF 31 DebugSupport.h 　
11471
 EXCEPT_IPF_FP_FAULTEXCEPT_IPF_FP_FAULT 32 DebugSupport.h 　
11472
 EXCEPT_IPF_FP_TRAPEXCEPT_IPF_FP_TRAP 33 DebugSupport.h 　
11473
 EXCEPT_IPF_LOWER_PRIVILEGE_TRANEXCEPT_IPF_LOWER_PRIVILEGE_TRAN 34 DebugSupport.h 　
11474
 EXCEPT_IPF_TAKEN_BRANCHEXCEPT_IPF_TAKEN_BRANCH 35 DebugSupport.h 　
11475
 EXCEPT_IPF_SINGLE_STEPEXCEPT_IPF_SINGLE_STEP 36 DebugSupport.h 　
11476
 EXCEPT_IPF_IA32_EXCEPTIONEXCEPT_IPF_IA32_EXCEPTION 45 DebugSupport.h 　
11477
 EXCEPT_IPF_IA32_INTERCEPTEXCEPT_IPF_IA32_INTERCEPT 46 DebugSupport.h 　
11478
 EXCEPT_IPF_IA32_INTERRUPTEXCEPT_IPF_IA32_INTERRUPT 47 DebugSupport.h 　
11479
 EXCEPT_EBC_UNDEFINEDEXCEPT_EBC_UNDEFINED 0 DebugSupport.h 　
11480
 EXCEPT_EBC_DIVIDE_ERROREXCEPT_EBC_DIVIDE_ERROR 1 DebugSupport.h 　
11481
 EXCEPT_EBC_DEBUGEXCEPT_EBC_DEBUG 2 DebugSupport.h 　
11482
 EXCEPT_EBC_BREAKPOINTEXCEPT_EBC_BREAKPOINT 3 DebugSupport.h 　
11483
 EXCEPT_EBC_OVERFLOWEXCEPT_EBC_OVERFLOW 4 DebugSupport.h 　
11484
 EXCEPT_EBC_INVALID_OPCODEEXCEPT_EBC_INVALID_OPCODE 5 DebugSupport.h < Opcode out of range.
11485
 EXCEPT_EBC_STACK_FAULTEXCEPT_EBC_STACK_FAULT 6 DebugSupport.h 　
11486
 EXCEPT_EBC_ALIGNMENT_CHECKEXCEPT_EBC_ALIGNMENT_CHECK 7 DebugSupport.h 　
11487
 EXCEPT_EBC_INSTRUCTION_ENCODINGEXCEPT_EBC_INSTRUCTION_ENCODING 8 DebugSupport.h < Malformed instruction.
11488
 EXCEPT_EBC_BAD_BREAKEXCEPT_EBC_BAD_BREAK 9 DebugSupport.h < BREAK 0 or undefined BREAK.
11489
 EXCEPT_EBC_STEPEXCEPT_EBC_STEP 10 DebugSupport.h < To support debug stepping.
11490
 MAX_EBC_EXCEPTIONMAX_EBC_EXCEPTION EXCEPT_EBC_STEP DebugSupport.h 　
11491
 EXCEPT_ARM_RESETEXCEPT_ARM_RESET 0 DebugSupport.h 　
11492
 EXCEPT_ARM_UNDEFINED_INSTRUCTIOEXCEPT_ARM_UNDEFINED_INSTRUCTIO 1 DebugSupport.h 　
11493
 EXCEPT_ARM_SOFTWARE_INTERRUPTEXCEPT_ARM_SOFTWARE_INTERRUPT 2 DebugSupport.h 　
11494
 EXCEPT_ARM_PREFETCH_ABORTEXCEPT_ARM_PREFETCH_ABORT 3 DebugSupport.h 　
11495
 EXCEPT_ARM_DATA_ABORTEXCEPT_ARM_DATA_ABORT 4 DebugSupport.h 　
11496
 EXCEPT_ARM_RESERVEDEXCEPT_ARM_RESERVED 5 DebugSupport.h 　
11497
 EXCEPT_ARM_IRQEXCEPT_ARM_IRQ 6 DebugSupport.h 　
11498
 EXCEPT_ARM_FIQEXCEPT_ARM_FIQ 7 DebugSupport.h 　
11499
 MAX_ARM_EXCEPTIONMAX_ARM_EXCEPTION EXCEPT_ARM_FIQ DebugSupport.h 　
11500
 EFI_DEVICE_PATH_PROTOCOL_GUIDEFI_DEVICE_PATH_PROTOCOL_GUID { \ 0x9576e91, 0x6d3f, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ } DevicePath.h 　
11501
 DEVICE_PATH_PROTOCOLDEVICE_PATH_PROTOCOL EFI_DEVICE_PATH_PROTOCOL_GUID DevicePath.h 　
11502
 HARDWARE_DEVICE_PATHHARDWARE_DEVICE_PATH 0x01 DevicePath.h 　
11503
 HW_PCI_DPHW_PCI_DP 0x01 DevicePath.h 　
11504
 HW_PCCARD_DPHW_PCCARD_DP 0x02 DevicePath.h 　
11505
 HW_MEMMAP_DPHW_MEMMAP_DP 0x03 DevicePath.h 　
11506
 HW_VENDOR_DPHW_VENDOR_DP 0x04 DevicePath.h 　
11507
 HW_CONTROLLER_DPHW_CONTROLLER_DP 0x05 DevicePath.h 　
11508
 ACPI_DEVICE_PATHACPI_DEVICE_PATH 0x02 DevicePath.h 　
11509
 ACPI_DPACPI_DP 0x01 DevicePath.h 　
11510
 ACPI_EXTENDED_DPACPI_EXTENDED_DP 0x02 DevicePath.h 　
11511
 PNP_EISA_ID_CONSTPNP_EISA_ID_CONST 0x41d0 DevicePath.h 　
11512
 PNP_EISA_ID_MASKPNP_EISA_ID_MASK 0xffff DevicePath.h 　
11513
 ACPI_ADR_DPACPI_ADR_DP 0x03 DevicePath.h 　
11514
 ACPI_ADR_DISPLAY_TYPE_OTHERACPI_ADR_DISPLAY_TYPE_OTHER 0 DevicePath.h 　
11515
 ACPI_ADR_DISPLAY_TYPE_VGAACPI_ADR_DISPLAY_TYPE_VGA 1 DevicePath.h 　
11516
 ACPI_ADR_DISPLAY_TYPE_TVACPI_ADR_DISPLAY_TYPE_TV 2 DevicePath.h 　
11517
 ACPI_ADR_DISPLAY_TYPE_EXTERNAL_ACPI_ADR_DISPLAY_TYPE_EXTERNAL_ 3 DevicePath.h 　
11518
 ACPI_ADR_DISPLAY_TYPE_INTERNAL_ACPI_ADR_DISPLAY_TYPE_INTERNAL_ 4 DevicePath.h 　
11519
 MESSAGING_DEVICE_PATHMESSAGING_DEVICE_PATH 0x03 DevicePath.h 　
11520
 MSG_ATAPI_DPMSG_ATAPI_DP 0x01 DevicePath.h 　
11521
 MSG_SCSI_DPMSG_SCSI_DP 0x02 DevicePath.h 　
11522
 MSG_FIBRECHANNEL_DPMSG_FIBRECHANNEL_DP 0x03 DevicePath.h 　
11523
 MSG_1394_DPMSG_1394_DP 0x04 DevicePath.h 　
11524
 MSG_USB_DPMSG_USB_DP 0x05 DevicePath.h 　
11525
 MSG_USB_CLASS_DPMSG_USB_CLASS_DP 0x0f DevicePath.h 　
11526
 MSG_USB_WWID_DPMSG_USB_WWID_DP 0x10 DevicePath.h 　
11527
 MSG_DEVICE_LOGICAL_UNIT_DPMSG_DEVICE_LOGICAL_UNIT_DP 0x11 DevicePath.h 　
11528
 MSG_SATA_DPMSG_SATA_DP 0x12 DevicePath.h 　
11529
 SATA_HBA_DIRECT_CONNECT_FLAGSATA_HBA_DIRECT_CONNECT_FLAG 0x8000 DevicePath.h 　
11530
 MSG_I2O_DPMSG_I2O_DP 0x06 DevicePath.h 　
11531
 MSG_MAC_ADDR_DPMSG_MAC_ADDR_DP 0x0b DevicePath.h 　
11532
 MSG_IPv4_DPMSG_IPv4_DP 0x0c DevicePath.h 　
11533
 MSG_IPv6_DPMSG_IPv6_DP 0x0d DevicePath.h 　
11534
 MSG_INFINIBAND_DPMSG_INFINIBAND_DP 0x09 DevicePath.h 　
11535
 INFINIBAND_RESOURCE_FLAG_IOC_SEINFINIBAND_RESOURCE_FLAG_IOC_SE 0x01 DevicePath.h 　
11536
 INFINIBAND_RESOURCE_FLAG_EXTENDINFINIBAND_RESOURCE_FLAG_EXTEND 0x02 DevicePath.h 　
11537
 INFINIBAND_RESOURCE_FLAG_CONSOLINFINIBAND_RESOURCE_FLAG_CONSOL 0x04 DevicePath.h 　
11538
 INFINIBAND_RESOURCE_FLAG_STORAGINFINIBAND_RESOURCE_FLAG_STORAG 0x08 DevicePath.h 　
11539
 INFINIBAND_RESOURCE_FLAG_NETWORINFINIBAND_RESOURCE_FLAG_NETWOR 0x10 DevicePath.h 　
11540
 MSG_UART_DPMSG_UART_DP 0x0e DevicePath.h 　
11541
 MSG_VENDOR_DPMSG_VENDOR_DP 0x0a DevicePath.h 　
11542
 DEVICE_PATH_MESSAGING_PC_ANSIDEVICE_PATH_MESSAGING_PC_ANSI EFI_PC_ANSI_GUID DevicePath.h 　
11543
 DEVICE_PATH_MESSAGING_VT_100DEVICE_PATH_MESSAGING_VT_100 EFI_VT_100_GUID DevicePath.h 　
11544
 DEVICE_PATH_MESSAGING_VT_100_PLDEVICE_PATH_MESSAGING_VT_100_PL EFI_VT_100_PLUS_GUID DevicePath.h 　
11545
 DEVICE_PATH_MESSAGING_VT_UTF8DEVICE_PATH_MESSAGING_VT_UTF8 EFI_VT_UTF8_GUID DevicePath.h 　
11546
 UART_FLOW_CONTROL_HARDWAREUART_FLOW_CONTROL_HARDWARE 0x00000001 DevicePath.h 　
11547
 UART_FLOW_CONTROL_XON_XOFFUART_FLOW_CONTROL_XON_XOFF 0x00000010 DevicePath.h 　
11548
 DEVICE_PATH_MESSAGING_SASDEVICE_PATH_MESSAGING_SAS EFI_SAS_DEVICE_PATH_GUID DevicePath.h 　
11549
 MSG_ISCSI_DPMSG_ISCSI_DP 0x13 DevicePath.h 　
11550
 ISCSI_LOGIN_OPTION_NO_HEADER_DIISCSI_LOGIN_OPTION_NO_HEADER_DI 0x0000 DevicePath.h 　
11551
 ISCSI_LOGIN_OPTION_HEADER_DIGESISCSI_LOGIN_OPTION_HEADER_DIGES 0x0002 DevicePath.h 　
11552
 ISCSI_LOGIN_OPTION_NO_DATA_DIGEISCSI_LOGIN_OPTION_NO_DATA_DIGE 0x0000 DevicePath.h 　
11553
 ISCSI_LOGIN_OPTION_DATA_DIGEST_ISCSI_LOGIN_OPTION_DATA_DIGEST_ 0x0008 DevicePath.h 　
11554
 ISCSI_LOGIN_OPTION_AUTHMETHOD_CISCSI_LOGIN_OPTION_AUTHMETHOD_C 0x0000 DevicePath.h 　
11555
 ISCSI_LOGIN_OPTION_AUTHMETHOD_NISCSI_LOGIN_OPTION_AUTHMETHOD_N 0x1000 DevicePath.h 　
11556
 ISCSI_LOGIN_OPTION_CHAP_BIISCSI_LOGIN_OPTION_CHAP_BI 0x0000 DevicePath.h 　
11557
 ISCSI_LOGIN_OPTION_CHAP_UNIISCSI_LOGIN_OPTION_CHAP_UNI 0x2000 DevicePath.h 　
11558
 MSG_VLAN_DPMSG_VLAN_DP 0x14 DevicePath.h 　
11559
 MEDIA_DEVICE_PATHMEDIA_DEVICE_PATH 0x04 DevicePath.h 　
11560
 MEDIA_HARDDRIVE_DPMEDIA_HARDDRIVE_DP 0x01 DevicePath.h 　
11561
 MBR_TYPE_PCATMBR_TYPE_PCAT 0x01 DevicePath.h 　
11562
 MBR_TYPE_EFI_PARTITION_TABLE_HEMBR_TYPE_EFI_PARTITION_TABLE_HE 0x02 DevicePath.h 　
11563
 NO_DISK_SIGNATURENO_DISK_SIGNATURE 0x00 DevicePath.h 　
11564
 SIGNATURE_TYPE_MBRSIGNATURE_TYPE_MBR 0x01 DevicePath.h 　
11565
 SIGNATURE_TYPE_GUIDSIGNATURE_TYPE_GUID 0x02 DevicePath.h 　
11566
 MEDIA_CDROM_DPMEDIA_CDROM_DP 0x02 DevicePath.h 　
11567
 MEDIA_VENDOR_DPMEDIA_VENDOR_DP 0x03 DevicePath.h < Media vendor device path subtype.
11568
 MEDIA_FILEPATH_DPMEDIA_FILEPATH_DP 0x04 DevicePath.h 　
11569
 SIZE_OF_FILEPATH_DEVICE_PATHSIZE_OF_FILEPATH_DEVICE_PATH OFFSET_OF(FILEPATH_DEVICE_PATH,PathName) DevicePath.h 　
11570
 MEDIA_PROTOCOL_DPMEDIA_PROTOCOL_DP 0x05 DevicePath.h 　
11571
 MEDIA_PIWG_FW_FILE_DPMEDIA_PIWG_FW_FILE_DP 0x06 DevicePath.h 　
11572
 MEDIA_PIWG_FW_VOL_DPMEDIA_PIWG_FW_VOL_DP 0x07 DevicePath.h 　
11573
 MEDIA_RELATIVE_OFFSET_RANGE_DPMEDIA_RELATIVE_OFFSET_RANGE_DP 0x08 DevicePath.h 　
11574
 BBS_DEVICE_PATHBBS_DEVICE_PATH 0x05 DevicePath.h 　
11575
 BBS_BBS_DPBBS_BBS_DP 0x01 DevicePath.h 　
11576
 BBS_TYPE_FLOPPYBBS_TYPE_FLOPPY 0x01 DevicePath.h 　
11577
 BBS_TYPE_HARDDRIVEBBS_TYPE_HARDDRIVE 0x02 DevicePath.h 　
11578
 BBS_TYPE_CDROMBBS_TYPE_CDROM 0x03 DevicePath.h 　
11579
 BBS_TYPE_PCMCIABBS_TYPE_PCMCIA 0x04 DevicePath.h 　
11580
 BBS_TYPE_USBBBS_TYPE_USB 0x05 DevicePath.h 　
11581
 BBS_TYPE_EMBEDDED_NETWORKBBS_TYPE_EMBEDDED_NETWORK 0x06 DevicePath.h 　
11582
 BBS_TYPE_BEVBBS_TYPE_BEV 0x80 DevicePath.h 　
11583
 BBS_TYPE_UNKNOWNBBS_TYPE_UNKNOWN 0xFF DevicePath.h 　
11584
 END_DEVICE_PATH_TYPEEND_DEVICE_PATH_TYPE 0x7f DevicePath.h 　
11585
 END_ENTIRE_DEVICE_PATH_SUBTYPEEND_ENTIRE_DEVICE_PATH_SUBTYPE 0xFF DevicePath.h 　
11586
 END_INSTANCE_DEVICE_PATH_SUBTYPEND_INSTANCE_DEVICE_PATH_SUBTYP 0x01 DevicePath.h 　
11587
 EFI_DRIVER_BINDING_PROTOCOL_GUIEFI_DRIVER_BINDING_PROTOCOL_GUI { \ 0x18a031ab, 0xb443, 0x4d1a, {0xa5, 0xc0, 0xc, 0x9, 0x26, 0x1e, 0x9f, 0x71 } \ } DriverBinding.h 　
11588
 EFI_LOADED_IMAGE_PROTOCOL_GUIDEFI_LOADED_IMAGE_PROTOCOL_GUID { \ 0x5B1B31A1, 0x9562, 0x11d2, {0x8E, 0x3F, 0x00, 0xA0, 0xC9, 0x69, 0x72, 0x3B } \ } LoadedImage.h 　
11589
 EFI_LOADED_IMAGE_DEVICE_PATH_PREFI_LOADED_IMAGE_DEVICE_PATH_PR { \ 0xbc62157e, 0x3e33, 0x4fec, {0x99, 0x20, 0x2d, 0x3b, 0x36, 0xd7, 0x50, 0xdf } \ } LoadedImage.h 　
11590
 LOADED_IMAGE_PROTOCOLLOADED_IMAGE_PROTOCOL EFI_LOADED_IMAGE_PROTOCOL_GUID LoadedImage.h 　
11591
 EFI_LOADED_IMAGE_PROTOCOL_REVISEFI_LOADED_IMAGE_PROTOCOL_REVIS 0x1000 LoadedImage.h 　
11592
 EFI_LOADED_IMAGE_INFORMATION_REEFI_LOADED_IMAGE_INFORMATION_RE EFI_LOADED_IMAGE_PROTOCOL_REVISION LoadedImage.h 　
11593
 EFI_NETWORK_INTERFACE_IDENTIFIEEFI_NETWORK_INTERFACE_IDENTIFIE { \ 0xE18541CD, 0xF755, 0x4f73, {0x92, 0x8D, 0x64, 0x3C, 0x8A, 0x79, 0xB2, 0x29 } \ } NetworkInterfaceIdentifier.h 　
11594
 EFI_NETWORK_INTERFACE_IDENTIFIEEFI_NETWORK_INTERFACE_IDENTIFIE { \ 0x1ACED566, 0x76ED, 0x4218, {0xBC, 0x81, 0x76, 0x7F, 0x1F, 0x97, 0x7A, 0x89 } \ } NetworkInterfaceIdentifier.h 　
11595
 EFI_NETWORK_INTERFACE_IDENTIFIEEFI_NETWORK_INTERFACE_IDENTIFIE 0x00010000 NetworkInterfaceIdentifier.h 　
11596
 EFI_NETWORK_INTERFACE_IDENTIFIEEFI_NETWORK_INTERFACE_IDENTIFIE EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION NetworkInterfaceIdentifier.h 　
11597
 EFI_PCI_IO_PROTOCOL_GUIDEFI_PCI_IO_PROTOCOL_GUID { \ 0x4cf5b200, 0x68b8, 0x4ca5, {0x9e, 0xec, 0xb2, 0x3e, 0x3f, 0x50, 0x2, 0x9a } \ } PciIo.h 　
11598
 EFI_PCI_IO_PASS_THROUGH_BAREFI_PCI_IO_PASS_THROUGH_BAR 0xff PciIo.h < Special BAR that passes a memory or I/O cycle through unchanged
11599
 EFI_PCI_IO_ATTRIBUTE_MASKEFI_PCI_IO_ATTRIBUTE_MASK 0x077f PciIo.h < All the following I/O and Memory cycles
11600
 EFI_PCI_IO_ATTRIBUTE_ISA_MOTHEREFI_PCI_IO_ATTRIBUTE_ISA_MOTHER 0x0001 PciIo.h < I/O cycles 0x0000-0x00FF (10 bit decode)
11601
 EFI_PCI_IO_ATTRIBUTE_ISA_IOEFI_PCI_IO_ATTRIBUTE_ISA_IO 0x0002 PciIo.h < I/O cycles 0x0100-0x03FF or greater (10 bit decode)
11602
 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTEFI_PCI_IO_ATTRIBUTE_VGA_PALETT 0x0004 PciIo.h < I/O cycles 0x3C6, 0x3C8, 0x3C9 (10 bit decode)
11603
 EFI_PCI_IO_ATTRIBUTE_VGA_MEMORYEFI_PCI_IO_ATTRIBUTE_VGA_MEMORY 0x0008 PciIo.h < MEM cycles 0xA0000-0xBFFFF (24 bit decode)
11604
 EFI_PCI_IO_ATTRIBUTE_VGA_IOEFI_PCI_IO_ATTRIBUTE_VGA_IO 0x0010 PciIo.h < I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (10 bit decode)
11605
 EFI_PCI_IO_ATTRIBUTE_IDE_PRIMAREFI_PCI_IO_ATTRIBUTE_IDE_PRIMAR 0x0020 PciIo.h < I/O cycles 0x1F0-0x1F7, 0x3F6, 0x3F7 (10 bit decode)
11606
 EFI_PCI_IO_ATTRIBUTE_IDE_SECONDEFI_PCI_IO_ATTRIBUTE_IDE_SECOND 0x0040 PciIo.h < I/O cycles 0x170-0x177, 0x376, 0x377 (10 bit decode)
11607
 EFI_PCI_IO_ATTRIBUTE_MEMORY_WRIEFI_PCI_IO_ATTRIBUTE_MEMORY_WRI 0x0080 PciIo.h < Map a memory range so writes are combined
11608
 EFI_PCI_IO_ATTRIBUTE_IOEFI_PCI_IO_ATTRIBUTE_IO 0x0100 PciIo.h < Enable the I/O decode bit in the PCI Config Header
11609
 EFI_PCI_IO_ATTRIBUTE_MEMORYEFI_PCI_IO_ATTRIBUTE_MEMORY 0x0200 PciIo.h < Enable the Memory decode bit in the PCI Config Header
11610
 EFI_PCI_IO_ATTRIBUTE_BUS_MASTEREFI_PCI_IO_ATTRIBUTE_BUS_MASTER 0x0400 PciIo.h < Enable the DMA bit in the PCI Config Header
11611
 EFI_PCI_IO_ATTRIBUTE_MEMORY_CACEFI_PCI_IO_ATTRIBUTE_MEMORY_CAC 0x0800 PciIo.h < Map a memory range so all r/w accesses are cached
11612
 EFI_PCI_IO_ATTRIBUTE_MEMORY_DISEFI_PCI_IO_ATTRIBUTE_MEMORY_DIS 0x1000 PciIo.h < Disable a memory range
11613
 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_DEFI_PCI_IO_ATTRIBUTE_EMBEDDED_D 0x2000 PciIo.h < Clear for an add-in PCI Device
11614
 EFI_PCI_IO_ATTRIBUTE_EMBEDDED_REFI_PCI_IO_ATTRIBUTE_EMBEDDED_R 0x4000 PciIo.h < Clear for a physical PCI Option ROM accessed through ROM BAR
11615
 EFI_PCI_IO_ATTRIBUTE_DUAL_ADDREEFI_PCI_IO_ATTRIBUTE_DUAL_ADDRE 0x8000 PciIo.h < Clear for PCI controllers that can not genrate a DAC
11616
 EFI_PCI_IO_ATTRIBUTE_ISA_IO_16EFI_PCI_IO_ATTRIBUTE_ISA_IO_16 0x10000 PciIo.h < I/O cycles 0x0100-0x03FF or greater (16 bit decode)
11617
 EFI_PCI_IO_ATTRIBUTE_VGA_PALETTEFI_PCI_IO_ATTRIBUTE_VGA_PALETT 0x20000 PciIo.h < I/O cycles 0x3C6, 0x3C8, 0x3C9 (16 bit decode)
11618
 EFI_PCI_IO_ATTRIBUTE_VGA_IO_16EFI_PCI_IO_ATTRIBUTE_VGA_IO_16 0x30000 PciIo.h < I/O cycles 0x3B0-0x3BB and 0x3C0-0x3DF (16 bit decode)
11619
 EFI_PCI_DEVICE_ENABLEEFI_PCI_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_IO | EFI_PCI_IO_ATTRIBUTE_MEMORY | EFI_PCI_IO_ATTRIBUTE_BUS_MASTER) PciIo.h 　
11620
 EFI_VGA_DEVICE_ENABLEEFI_VGA_DEVICE_ENABLE (EFI_PCI_IO_ATTRIBUTE_VGA_PALETTE_IO | EFI_PCI_IO_ATTRIBUTE_VGA_MEMORY | EFI_PCI_IO_ATTRIBUTE_VGA_IO | EFI_PCI_IO_ATTRIBUTE_IO) PciIo.h 　
11621
 EFI_PCI_ROOT_BRIDGE_IO_PROTOCOLEFI_PCI_ROOT_BRIDGE_IO_PROTOCOL { \ 0x2f707ebb, 0x4a1a, 0x11d4, {0x9a, 0x38, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d } \ } PciRootBridgeIo.h 　
11622
 EFI_PCI_ATTRIBUTE_ISA_MOTHERBOAEFI_PCI_ATTRIBUTE_ISA_MOTHERBOA 0x0001 PciRootBridgeIo.h 　
11623
 EFI_PCI_ATTRIBUTE_ISA_IOEFI_PCI_ATTRIBUTE_ISA_IO 0x0002 PciRootBridgeIo.h 　
11624
 EFI_PCI_ATTRIBUTE_VGA_PALETTE_IEFI_PCI_ATTRIBUTE_VGA_PALETTE_I 0x0004 PciRootBridgeIo.h 　
11625
 EFI_PCI_ATTRIBUTE_VGA_MEMORYEFI_PCI_ATTRIBUTE_VGA_MEMORY 0x0008 PciRootBridgeIo.h 　
11626
 EFI_PCI_ATTRIBUTE_VGA_IOEFI_PCI_ATTRIBUTE_VGA_IO 0x0010 PciRootBridgeIo.h 　
11627
 EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IEFI_PCI_ATTRIBUTE_IDE_PRIMARY_I 0x0020 PciRootBridgeIo.h 　
11628
 EFI_PCI_ATTRIBUTE_IDE_SECONDARYEFI_PCI_ATTRIBUTE_IDE_SECONDARY 0x0040 PciRootBridgeIo.h 　
11629
 EFI_PCI_ATTRIBUTE_MEMORY_WRITE_EFI_PCI_ATTRIBUTE_MEMORY_WRITE_ 0x0080 PciRootBridgeIo.h 　
11630
 EFI_PCI_ATTRIBUTE_MEMORY_CACHEDEFI_PCI_ATTRIBUTE_MEMORY_CACHED 0x0800 PciRootBridgeIo.h 　
11631
 EFI_PCI_ATTRIBUTE_MEMORY_DISABLEFI_PCI_ATTRIBUTE_MEMORY_DISABL 0x1000 PciRootBridgeIo.h 　
11632
 EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_ 0x8000 PciRootBridgeIo.h 　
11633
 EFI_PCI_ATTRIBUTE_VALID_FOR_ALLEFI_PCI_ATTRIBUTE_VALID_FOR_ALL (EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE | EFI_PCI_ATTRIBUTE_MEMORY_CACHED | EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE) PciRootBridgeIo.h 　
11634
 EFI_PCI_ATTRIBUTE_INVALID_FOR_AEFI_PCI_ATTRIBUTE_INVALID_FOR_A (~EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER) PciRootBridgeIo.h 　
11635
 EFI_SIMPLE_NETWORK_PROTOCOL_GUIEFI_SIMPLE_NETWORK_PROTOCOL_GUI { \ 0xA19832B9, 0xAC25, 0x11D3, {0x9A, 0x2D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D } \ } SimpleNetwork.h 　
11636
 EFI_SIMPLE_NETWORK_RECEIVE_UNICEFI_SIMPLE_NETWORK_RECEIVE_UNIC 0x01 SimpleNetwork.h 　
11637
 EFI_SIMPLE_NETWORK_RECEIVE_MULTEFI_SIMPLE_NETWORK_RECEIVE_MULT 0x02 SimpleNetwork.h 　
11638
 EFI_SIMPLE_NETWORK_RECEIVE_BROAEFI_SIMPLE_NETWORK_RECEIVE_BROA 0x04 SimpleNetwork.h 　
11639
 EFI_SIMPLE_NETWORK_RECEIVE_PROMEFI_SIMPLE_NETWORK_RECEIVE_PROM 0x08 SimpleNetwork.h 　
11640
 EFI_SIMPLE_NETWORK_RECEIVE_PROMEFI_SIMPLE_NETWORK_RECEIVE_PROM 0x10 SimpleNetwork.h 　
11641
 EFI_SIMPLE_NETWORK_RECEIVE_INTEEFI_SIMPLE_NETWORK_RECEIVE_INTE 0x01 SimpleNetwork.h 　
11642
 EFI_SIMPLE_NETWORK_TRANSMIT_INTEFI_SIMPLE_NETWORK_TRANSMIT_INT 0x02 SimpleNetwork.h 　
11643
 EFI_SIMPLE_NETWORK_COMMAND_INTEEFI_SIMPLE_NETWORK_COMMAND_INTE 0x04 SimpleNetwork.h 　
11644
 EFI_SIMPLE_NETWORK_SOFTWARE_INTEFI_SIMPLE_NETWORK_SOFTWARE_INT 0x08 SimpleNetwork.h 　
11645
 MAX_MCAST_FILTER_CNTMAX_MCAST_FILTER_CNT 16 SimpleNetwork.h 　
11646
 EFI_SIMPLE_NETWORK_PROTOCOL_REVEFI_SIMPLE_NETWORK_PROTOCOL_REV 0x00010000 SimpleNetwork.h 　
11647
 EFI_SIMPLE_NETWORK_INTERFACE_REEFI_SIMPLE_NETWORK_INTERFACE_RE EFI_SIMPLE_NETWORK_PROTOCOL_REVISION SimpleNetwork.h 　
11648
 EFI_SIMPLE_TEXT_INPUT_PROTOCOL_EFI_SIMPLE_TEXT_INPUT_PROTOCOL_ { \ 0x387477c1, 0x69c7, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ } SimpleTextIn.h 　
11649
 SIMPLE_INPUT_PROTOCOLSIMPLE_INPUT_PROTOCOL EFI_SIMPLE_TEXT_INPUT_PROTOCOL_GUID SimpleTextIn.h 　
11650
 CHAR_NULLCHAR_NULL 0x0000 SimpleTextIn.h 　
11651
 CHAR_BACKSPACECHAR_BACKSPACE 0x0008 SimpleTextIn.h 　
11652
 CHAR_TABCHAR_TAB 0x0009 SimpleTextIn.h 　
11653
 CHAR_LINEFEEDCHAR_LINEFEED 0x000A SimpleTextIn.h 　
11654
 CHAR_CARRIAGE_RETURNCHAR_CARRIAGE_RETURN 0x000D SimpleTextIn.h 　
11655
 SCAN_NULLSCAN_NULL 0x0000 SimpleTextIn.h 　
11656
 SCAN_UPSCAN_UP 0x0001 SimpleTextIn.h 　
11657
 SCAN_DOWNSCAN_DOWN 0x0002 SimpleTextIn.h 　
11658
 SCAN_RIGHTSCAN_RIGHT 0x0003 SimpleTextIn.h 　
11659
 SCAN_LEFTSCAN_LEFT 0x0004 SimpleTextIn.h 　
11660
 SCAN_HOMESCAN_HOME 0x0005 SimpleTextIn.h 　
11661
 SCAN_ENDSCAN_END 0x0006 SimpleTextIn.h 　
11662
 SCAN_INSERTSCAN_INSERT 0x0007 SimpleTextIn.h 　
11663
 SCAN_DELETESCAN_DELETE 0x0008 SimpleTextIn.h 　
11664
 SCAN_PAGE_UPSCAN_PAGE_UP 0x0009 SimpleTextIn.h 　
11665
 SCAN_PAGE_DOWNSCAN_PAGE_DOWN 0x000A SimpleTextIn.h 　
11666
 SCAN_F1SCAN_F1 0x000B SimpleTextIn.h 　
11667
 SCAN_F2SCAN_F2 0x000C SimpleTextIn.h 　
11668
 SCAN_F3SCAN_F3 0x000D SimpleTextIn.h 　
11669
 SCAN_F4SCAN_F4 0x000E SimpleTextIn.h 　
11670
 SCAN_F5SCAN_F5 0x000F SimpleTextIn.h 　
11671
 SCAN_F6SCAN_F6 0x0010 SimpleTextIn.h 　
11672
 SCAN_F7SCAN_F7 0x0011 SimpleTextIn.h 　
11673
 SCAN_F8SCAN_F8 0x0012 SimpleTextIn.h 　
11674
 SCAN_F9SCAN_F9 0x0013 SimpleTextIn.h 　
11675
 SCAN_F10SCAN_F10 0x0014 SimpleTextIn.h 　
11676
 SCAN_F11SCAN_F11 0x0015 SimpleTextIn.h 　
11677
 SCAN_F12SCAN_F12 0x0016 SimpleTextIn.h 　
11678
 SCAN_ESCSCAN_ESC 0x0017 SimpleTextIn.h 　
11679
 EFI_SIMPLE_TEXT_OUTPUT_PROTOCOLEFI_SIMPLE_TEXT_OUTPUT_PROTOCOL { \ 0x387477c2, 0x69c7, 0x11d2, {0x8e, 0x39, 0x0, 0xa0, 0xc9, 0x69, 0x72, 0x3b } \ } SimpleTextOut.h 　
11680
 SIMPLE_TEXT_OUTPUT_PROTOCOLSIMPLE_TEXT_OUTPUT_PROTOCOL EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL_GUID SimpleTextOut.h 　
11681
 BOXDRAW_HORIZONTALBOXDRAW_HORIZONTAL 0x2500 SimpleTextOut.h 　
11682
 BOXDRAW_VERTICALBOXDRAW_VERTICAL 0x2502 SimpleTextOut.h 　
11683
 BOXDRAW_DOWN_RIGHTBOXDRAW_DOWN_RIGHT 0x250c SimpleTextOut.h 　
11684
 BOXDRAW_DOWN_LEFTBOXDRAW_DOWN_LEFT 0x2510 SimpleTextOut.h 　
11685
 BOXDRAW_UP_RIGHTBOXDRAW_UP_RIGHT 0x2514 SimpleTextOut.h 　
11686
 BOXDRAW_UP_LEFTBOXDRAW_UP_LEFT 0x2518 SimpleTextOut.h 　
11687
 BOXDRAW_VERTICAL_RIGHTBOXDRAW_VERTICAL_RIGHT 0x251c SimpleTextOut.h 　
11688
 BOXDRAW_VERTICAL_LEFTBOXDRAW_VERTICAL_LEFT 0x2524 SimpleTextOut.h 　
11689
 BOXDRAW_DOWN_HORIZONTALBOXDRAW_DOWN_HORIZONTAL 0x252c SimpleTextOut.h 　
11690
 BOXDRAW_UP_HORIZONTALBOXDRAW_UP_HORIZONTAL 0x2534 SimpleTextOut.h 　
11691
 BOXDRAW_VERTICAL_HORIZONTALBOXDRAW_VERTICAL_HORIZONTAL 0x253c SimpleTextOut.h 　
11692
 BOXDRAW_DOUBLE_HORIZONTALBOXDRAW_DOUBLE_HORIZONTAL 0x2550 SimpleTextOut.h 　
11693
 BOXDRAW_DOUBLE_VERTICALBOXDRAW_DOUBLE_VERTICAL 0x2551 SimpleTextOut.h 　
11694
 BOXDRAW_DOWN_RIGHT_DOUBLEBOXDRAW_DOWN_RIGHT_DOUBLE 0x2552 SimpleTextOut.h 　
11695
 BOXDRAW_DOWN_DOUBLE_RIGHTBOXDRAW_DOWN_DOUBLE_RIGHT 0x2553 SimpleTextOut.h 　
11696
 BOXDRAW_DOUBLE_DOWN_RIGHTBOXDRAW_DOUBLE_DOWN_RIGHT 0x2554 SimpleTextOut.h 　
11697
 BOXDRAW_DOWN_LEFT_DOUBLEBOXDRAW_DOWN_LEFT_DOUBLE 0x2555 SimpleTextOut.h 　
11698
 BOXDRAW_DOWN_DOUBLE_LEFTBOXDRAW_DOWN_DOUBLE_LEFT 0x2556 SimpleTextOut.h 　
11699
 BOXDRAW_DOUBLE_DOWN_LEFTBOXDRAW_DOUBLE_DOWN_LEFT 0x2557 SimpleTextOut.h 　
11700
 BOXDRAW_UP_RIGHT_DOUBLEBOXDRAW_UP_RIGHT_DOUBLE 0x2558 SimpleTextOut.h 　
11701
 BOXDRAW_UP_DOUBLE_RIGHTBOXDRAW_UP_DOUBLE_RIGHT 0x2559 SimpleTextOut.h 　
11702
 BOXDRAW_DOUBLE_UP_RIGHTBOXDRAW_DOUBLE_UP_RIGHT 0x255a SimpleTextOut.h 　
11703
 BOXDRAW_UP_LEFT_DOUBLEBOXDRAW_UP_LEFT_DOUBLE 0x255b SimpleTextOut.h 　
11704
 BOXDRAW_UP_DOUBLE_LEFTBOXDRAW_UP_DOUBLE_LEFT 0x255c SimpleTextOut.h 　
11705
 BOXDRAW_DOUBLE_UP_LEFTBOXDRAW_DOUBLE_UP_LEFT 0x255d SimpleTextOut.h 　
11706
 BOXDRAW_VERTICAL_RIGHT_DOUBLEBOXDRAW_VERTICAL_RIGHT_DOUBLE 0x255e SimpleTextOut.h 　
11707
 BOXDRAW_VERTICAL_DOUBLE_RIGHTBOXDRAW_VERTICAL_DOUBLE_RIGHT 0x255f SimpleTextOut.h 　
11708
 BOXDRAW_DOUBLE_VERTICAL_RIGHTBOXDRAW_DOUBLE_VERTICAL_RIGHT 0x2560 SimpleTextOut.h 　
11709
 BOXDRAW_VERTICAL_LEFT_DOUBLEBOXDRAW_VERTICAL_LEFT_DOUBLE 0x2561 SimpleTextOut.h 　
11710
 BOXDRAW_VERTICAL_DOUBLE_LEFTBOXDRAW_VERTICAL_DOUBLE_LEFT 0x2562 SimpleTextOut.h 　
11711
 BOXDRAW_DOUBLE_VERTICAL_LEFTBOXDRAW_DOUBLE_VERTICAL_LEFT 0x2563 SimpleTextOut.h 　
11712
 BOXDRAW_DOWN_HORIZONTAL_DOUBLEBOXDRAW_DOWN_HORIZONTAL_DOUBLE 0x2564 SimpleTextOut.h 　
11713
 BOXDRAW_DOWN_DOUBLE_HORIZONTALBOXDRAW_DOWN_DOUBLE_HORIZONTAL 0x2565 SimpleTextOut.h 　
11714
 BOXDRAW_DOUBLE_DOWN_HORIZONTALBOXDRAW_DOUBLE_DOWN_HORIZONTAL 0x2566 SimpleTextOut.h 　
11715
 BOXDRAW_UP_HORIZONTAL_DOUBLEBOXDRAW_UP_HORIZONTAL_DOUBLE 0x2567 SimpleTextOut.h 　
11716
 BOXDRAW_UP_DOUBLE_HORIZONTALBOXDRAW_UP_DOUBLE_HORIZONTAL 0x2568 SimpleTextOut.h 　
11717
 BOXDRAW_DOUBLE_UP_HORIZONTALBOXDRAW_DOUBLE_UP_HORIZONTAL 0x2569 SimpleTextOut.h 　
11718
 BOXDRAW_VERTICAL_HORIZONTAL_DOUBOXDRAW_VERTICAL_HORIZONTAL_DOU 0x256a SimpleTextOut.h 　
11719
 BOXDRAW_VERTICAL_DOUBLE_HORIZONBOXDRAW_VERTICAL_DOUBLE_HORIZON 0x256b SimpleTextOut.h 　
11720
 BOXDRAW_DOUBLE_VERTICAL_HORIZONBOXDRAW_DOUBLE_VERTICAL_HORIZON 0x256c SimpleTextOut.h 　
11721
 BLOCKELEMENT_FULL_BLOCKBLOCKELEMENT_FULL_BLOCK 0x2588 SimpleTextOut.h 　
11722
 BLOCKELEMENT_LIGHT_SHADEBLOCKELEMENT_LIGHT_SHADE 0x2591 SimpleTextOut.h 　
11723
 GEOMETRICSHAPE_UP_TRIANGLEGEOMETRICSHAPE_UP_TRIANGLE 0x25b2 SimpleTextOut.h 　
11724
 GEOMETRICSHAPE_RIGHT_TRIANGLEGEOMETRICSHAPE_RIGHT_TRIANGLE 0x25ba SimpleTextOut.h 　
11725
 GEOMETRICSHAPE_DOWN_TRIANGLEGEOMETRICSHAPE_DOWN_TRIANGLE 0x25bc SimpleTextOut.h 　
11726
 GEOMETRICSHAPE_LEFT_TRIANGLEGEOMETRICSHAPE_LEFT_TRIANGLE 0x25c4 SimpleTextOut.h 　
11727
 ARROW_LEFTARROW_LEFT 0x2190 SimpleTextOut.h 　
11728
 ARROW_UPARROW_UP 0x2191 SimpleTextOut.h 　
11729
 ARROW_RIGHTARROW_RIGHT 0x2192 SimpleTextOut.h 　
11730
 ARROW_DOWNARROW_DOWN 0x2193 SimpleTextOut.h 　
11731
 EFI_BLACKEFI_BLACK 0x00 SimpleTextOut.h 　
11732
 EFI_BLUEEFI_BLUE 0x01 SimpleTextOut.h 　
11733
 EFI_GREENEFI_GREEN 0x02 SimpleTextOut.h 　
11734
 EFI_CYANEFI_CYAN (EFI_BLUE | EFI_GREEN) SimpleTextOut.h 　
11735
 EFI_REDEFI_RED 0x04 SimpleTextOut.h 　
11736
 EFI_MAGENTAEFI_MAGENTA (EFI_BLUE | EFI_RED) SimpleTextOut.h 　
11737
 EFI_BROWNEFI_BROWN (EFI_GREEN | EFI_RED) SimpleTextOut.h 　
11738
 EFI_LIGHTGRAYEFI_LIGHTGRAY (EFI_BLUE | EFI_GREEN | EFI_RED) SimpleTextOut.h 　
11739
 EFI_BRIGHTEFI_BRIGHT 0x08 SimpleTextOut.h 　
11740
 EFI_DARKGRAYEFI_DARKGRAY (EFI_BRIGHT) SimpleTextOut.h 　
11741
 EFI_LIGHTBLUEEFI_LIGHTBLUE (EFI_BLUE | EFI_BRIGHT) SimpleTextOut.h 　
11742
 EFI_LIGHTGREENEFI_LIGHTGREEN (EFI_GREEN | EFI_BRIGHT) SimpleTextOut.h 　
11743
 EFI_LIGHTCYANEFI_LIGHTCYAN (EFI_CYAN | EFI_BRIGHT) SimpleTextOut.h 　
11744
 EFI_LIGHTREDEFI_LIGHTRED (EFI_RED | EFI_BRIGHT) SimpleTextOut.h 　
11745
 EFI_LIGHTMAGENTAEFI_LIGHTMAGENTA (EFI_MAGENTA | EFI_BRIGHT) SimpleTextOut.h 　
11746
 EFI_YELLOWEFI_YELLOW (EFI_BROWN | EFI_BRIGHT) SimpleTextOut.h 　
11747
 EFI_WHITEEFI_WHITE (EFI_BLUE | EFI_GREEN | EFI_RED | EFI_BRIGHT) SimpleTextOut.h 　
11748
 EFI_BACKGROUND_BLACKEFI_BACKGROUND_BLACK 0x00 SimpleTextOut.h 　
11749
 EFI_BACKGROUND_BLUEEFI_BACKGROUND_BLUE 0x10 SimpleTextOut.h 　
11750
 EFI_BACKGROUND_GREENEFI_BACKGROUND_GREEN 0x20 SimpleTextOut.h 　
11751
 EFI_BACKGROUND_CYANEFI_BACKGROUND_CYAN (EFI_BACKGROUND_BLUE | EFI_BACKGROUND_GREEN) SimpleTextOut.h 　
11752
 EFI_BACKGROUND_REDEFI_BACKGROUND_RED 0x40 SimpleTextOut.h 　
11753
 EFI_BACKGROUND_MAGENTAEFI_BACKGROUND_MAGENTA (EFI_BACKGROUND_BLUE | EFI_BACKGROUND_RED) SimpleTextOut.h 　
11754
 EFI_BACKGROUND_BROWNEFI_BACKGROUND_BROWN (EFI_BACKGROUND_GREEN | EFI_BACKGROUND_RED) SimpleTextOut.h 　
11755
 EFI_BACKGROUND_LIGHTGRAYEFI_BACKGROUND_LIGHTGRAY (EFI_BACKGROUND_BLUE | EFI_BACKGROUND_GREEN | EFI_BACKGROUND_RED) SimpleTextOut.h 　
11756
 EFI_WIDE_ATTRIBUTEEFI_WIDE_ATTRIBUTE 0x80 SimpleTextOut.h 　
11757
 EFI_SUCCESSEFI_SUCCESS RETURN_SUCCESS UefiBaseType.h 　
11758
 EFI_LOAD_ERROREFI_LOAD_ERROR RETURN_LOAD_ERROR UefiBaseType.h 　
11759
 EFI_INVALID_PARAMETEREFI_INVALID_PARAMETER RETURN_INVALID_PARAMETER UefiBaseType.h 　
11760
 EFI_UNSUPPORTEDEFI_UNSUPPORTED RETURN_UNSUPPORTED UefiBaseType.h 　
11761
 EFI_BAD_BUFFER_SIZEEFI_BAD_BUFFER_SIZE RETURN_BAD_BUFFER_SIZE UefiBaseType.h 　
11762
 EFI_BUFFER_TOO_SMALLEFI_BUFFER_TOO_SMALL RETURN_BUFFER_TOO_SMALL UefiBaseType.h 　
11763
 EFI_NOT_READYEFI_NOT_READY RETURN_NOT_READY UefiBaseType.h 　
11764
 EFI_DEVICE_ERROREFI_DEVICE_ERROR RETURN_DEVICE_ERROR UefiBaseType.h 　
11765
 EFI_WRITE_PROTECTEDEFI_WRITE_PROTECTED RETURN_WRITE_PROTECTED UefiBaseType.h 　
11766
 EFI_OUT_OF_RESOURCESEFI_OUT_OF_RESOURCES RETURN_OUT_OF_RESOURCES UefiBaseType.h 　
11767
 EFI_VOLUME_CORRUPTEDEFI_VOLUME_CORRUPTED RETURN_VOLUME_CORRUPTED UefiBaseType.h 　
11768
 EFI_VOLUME_FULLEFI_VOLUME_FULL RETURN_VOLUME_FULL UefiBaseType.h 　
11769
 EFI_NO_MEDIAEFI_NO_MEDIA RETURN_NO_MEDIA UefiBaseType.h 　
11770
 EFI_MEDIA_CHANGEDEFI_MEDIA_CHANGED RETURN_MEDIA_CHANGED UefiBaseType.h 　
11771
 EFI_NOT_FOUNDEFI_NOT_FOUND RETURN_NOT_FOUND UefiBaseType.h 　
11772
 EFI_ACCESS_DENIEDEFI_ACCESS_DENIED RETURN_ACCESS_DENIED UefiBaseType.h 　
11773
 EFI_NO_RESPONSEEFI_NO_RESPONSE RETURN_NO_RESPONSE UefiBaseType.h 　
11774
 EFI_NO_MAPPINGEFI_NO_MAPPING RETURN_NO_MAPPING UefiBaseType.h 　
11775
 EFI_TIMEOUTEFI_TIMEOUT RETURN_TIMEOUT UefiBaseType.h 　
11776
 EFI_NOT_STARTEDEFI_NOT_STARTED RETURN_NOT_STARTED UefiBaseType.h 　
11777
 EFI_ALREADY_STARTEDEFI_ALREADY_STARTED RETURN_ALREADY_STARTED UefiBaseType.h 　
11778
 EFI_ABORTEDEFI_ABORTED RETURN_ABORTED UefiBaseType.h 　
11779
 EFI_ICMP_ERROREFI_ICMP_ERROR RETURN_ICMP_ERROR UefiBaseType.h 　
11780
 EFI_TFTP_ERROREFI_TFTP_ERROR RETURN_TFTP_ERROR UefiBaseType.h 　
11781
 EFI_PROTOCOL_ERROREFI_PROTOCOL_ERROR RETURN_PROTOCOL_ERROR UefiBaseType.h 　
11782
 EFI_INCOMPATIBLE_VERSIONEFI_INCOMPATIBLE_VERSION RETURN_INCOMPATIBLE_VERSION UefiBaseType.h 　
11783
 EFI_SECURITY_VIOLATIONEFI_SECURITY_VIOLATION RETURN_SECURITY_VIOLATION UefiBaseType.h 　
11784
 EFI_CRC_ERROREFI_CRC_ERROR RETURN_CRC_ERROR UefiBaseType.h 　
11785
 EFI_END_OF_MEDIAEFI_END_OF_MEDIA RETURN_END_OF_MEDIA UefiBaseType.h 　
11786
 EFI_END_OF_FILEEFI_END_OF_FILE RETURN_END_OF_FILE UefiBaseType.h 　
11787
 EFI_INVALID_LANGUAGEEFI_INVALID_LANGUAGE RETURN_INVALID_LANGUAGE UefiBaseType.h 　
11788
 EFI_WARN_UNKNOWN_GLYPHEFI_WARN_UNKNOWN_GLYPH RETURN_WARN_UNKNOWN_GLYPH UefiBaseType.h 　
11789
 EFI_WARN_DELETE_FAILUREEFI_WARN_DELETE_FAILURE RETURN_WARN_DELETE_FAILURE UefiBaseType.h 　
11790
 EFI_WARN_WRITE_FAILUREEFI_WARN_WRITE_FAILURE RETURN_WARN_WRITE_FAILURE UefiBaseType.h 　
11791
 EFI_WARN_BUFFER_TOO_SMALLEFI_WARN_BUFFER_TOO_SMALL RETURN_WARN_BUFFER_TOO_SMALL UefiBaseType.h 　
11792
 EFI_NETWORK_UNREACHABLEEFI_NETWORK_UNREACHABLE EFIERR(100) UefiBaseType.h 　
11793
 EFI_HOST_UNREACHABLEEFI_HOST_UNREACHABLE EFIERR(101) UefiBaseType.h 　
11794
 EFI_PROTOCOL_UNREACHABLEEFI_PROTOCOL_UNREACHABLE EFIERR(102) UefiBaseType.h 　
11795
 EFI_PORT_UNREACHABLEEFI_PORT_UNREACHABLE EFIERR(103) UefiBaseType.h 　
11796
 EFI_CONNECTION_FINEFI_CONNECTION_FIN EFIERR(104) UefiBaseType.h 　
11797
 EFI_CONNECTION_RESETEFI_CONNECTION_RESET EFIERR(105) UefiBaseType.h 　
11798
 EFI_CONNECTION_REFUSEDEFI_CONNECTION_REFUSED EFIERR(106) UefiBaseType.h 　
11799
 EFI_PAGE_SIZEEFI_PAGE_SIZE 0x1000 UefiBaseType.h 　
11800
 EFI_PAGE_MASKEFI_PAGE_MASK 0xFFF UefiBaseType.h 　
11801
 EFI_PAGE_SHIFTEFI_PAGE_SHIFT 12 UefiBaseType.h 　
11802
 EFI_IMAGE_MACHINE_IA32EFI_IMAGE_MACHINE_IA32 0x014C UefiBaseType.h 　
11803
 EFI_IMAGE_MACHINE_IA64EFI_IMAGE_MACHINE_IA64 0x0200 UefiBaseType.h 　
11804
 EFI_IMAGE_MACHINE_EBCEFI_IMAGE_MACHINE_EBC 0x0EBC UefiBaseType.h 　
11805
 EFI_IMAGE_MACHINE_X64EFI_IMAGE_MACHINE_X64 0x8664 UefiBaseType.h 　
11806
 EFI_IMAGE_MACHINE_ARMTHUMB_MIXEEFI_IMAGE_MACHINE_ARMTHUMB_MIXE 0x01C2 UefiBaseType.h 　
11807
 PRIMARY_PART_HEADER_LBAPRIMARY_PART_HEADER_LBA 1 UefiGpt.h 　
11808
 EFI_PTAB_HEADER_IDEFI_PTAB_HEADER_ID SIGNATURE_64 ('E','F','I',' ','P','A','R','T') UefiGpt.h 　
11809
 EFI_HII_PACKAGE_TYPE_ALLEFI_HII_PACKAGE_TYPE_ALL 0x00 UefiInternalFormRepresentation.h 　
11810
 EFI_HII_PACKAGE_TYPE_GUIDEFI_HII_PACKAGE_TYPE_GUID 0x01 UefiInternalFormRepresentation.h 　
11811
 EFI_HII_PACKAGE_FORMSEFI_HII_PACKAGE_FORMS 0x02 UefiInternalFormRepresentation.h 　
11812
 EFI_HII_PACKAGE_STRINGSEFI_HII_PACKAGE_STRINGS 0x04 UefiInternalFormRepresentation.h 　
11813
 EFI_HII_PACKAGE_FONTSEFI_HII_PACKAGE_FONTS 0x05 UefiInternalFormRepresentation.h 　
11814
 EFI_HII_PACKAGE_IMAGESEFI_HII_PACKAGE_IMAGES 0x06 UefiInternalFormRepresentation.h 　
11815
 EFI_HII_PACKAGE_SIMPLE_FONTSEFI_HII_PACKAGE_SIMPLE_FONTS 0x07 UefiInternalFormRepresentation.h 　
11816
 EFI_HII_PACKAGE_DEVICE_PATHEFI_HII_PACKAGE_DEVICE_PATH 0x08 UefiInternalFormRepresentation.h 　
11817
 EFI_HII_PACKAGE_KEYBOARD_LAYOUTEFI_HII_PACKAGE_KEYBOARD_LAYOUT 0x09 UefiInternalFormRepresentation.h 　
11818
 EFI_HII_PACKAGE_ANIMATIONSEFI_HII_PACKAGE_ANIMATIONS 0x0A UefiInternalFormRepresentation.h 　
11819
 EFI_HII_PACKAGE_ENDEFI_HII_PACKAGE_END 0xDF UefiInternalFormRepresentation.h 　
11820
 EFI_HII_PACKAGE_TYPE_SYSTEM_BEGEFI_HII_PACKAGE_TYPE_SYSTEM_BEG 0xE0 UefiInternalFormRepresentation.h 　
11821
 EFI_HII_PACKAGE_TYPE_SYSTEM_ENDEFI_HII_PACKAGE_TYPE_SYSTEM_END 0xFF UefiInternalFormRepresentation.h 　
11822
 EFI_GLYPH_NON_SPACINGEFI_GLYPH_NON_SPACING 0x01 UefiInternalFormRepresentation.h 　
11823
 EFI_GLYPH_WIDEEFI_GLYPH_WIDE 0x02 UefiInternalFormRepresentation.h 　
11824
 EFI_GLYPH_HEIGHTEFI_GLYPH_HEIGHT 19 UefiInternalFormRepresentation.h 　
11825
 EFI_GLYPH_WIDTHEFI_GLYPH_WIDTH 8 UefiInternalFormRepresentation.h 　
11826
 EFI_HII_FONT_STYLE_NORMALEFI_HII_FONT_STYLE_NORMAL 0x00000000 UefiInternalFormRepresentation.h 　
11827
 EFI_HII_FONT_STYLE_BOLDEFI_HII_FONT_STYLE_BOLD 0x00000001 UefiInternalFormRepresentation.h 　
11828
 EFI_HII_FONT_STYLE_ITALICEFI_HII_FONT_STYLE_ITALIC 0x00000002 UefiInternalFormRepresentation.h 　
11829
 EFI_HII_FONT_STYLE_EMBOSSEFI_HII_FONT_STYLE_EMBOSS 0x00010000 UefiInternalFormRepresentation.h 　
11830
 EFI_HII_FONT_STYLE_OUTLINEEFI_HII_FONT_STYLE_OUTLINE 0x00020000 UefiInternalFormRepresentation.h 　
11831
 EFI_HII_FONT_STYLE_SHADOWEFI_HII_FONT_STYLE_SHADOW 0x00040000 UefiInternalFormRepresentation.h 　
11832
 EFI_HII_FONT_STYLE_UNDERLINEEFI_HII_FONT_STYLE_UNDERLINE 0x00080000 UefiInternalFormRepresentation.h 　
11833
 EFI_HII_FONT_STYLE_DBL_UNDEREFI_HII_FONT_STYLE_DBL_UNDER 0x00100000 UefiInternalFormRepresentation.h 　
11834
 EFI_HII_GIBT_ENDEFI_HII_GIBT_END 0x00 UefiInternalFormRepresentation.h 　
11835
 EFI_HII_GIBT_GLYPHEFI_HII_GIBT_GLYPH 0x10 UefiInternalFormRepresentation.h 　
11836
 EFI_HII_GIBT_GLYPHSEFI_HII_GIBT_GLYPHS 0x11 UefiInternalFormRepresentation.h 　
11837
 EFI_HII_GIBT_GLYPH_DEFAULTEFI_HII_GIBT_GLYPH_DEFAULT 0x12 UefiInternalFormRepresentation.h 　
11838
 EFI_HII_GIBT_GLYPHS_DEFAULTEFI_HII_GIBT_GLYPHS_DEFAULT 0x13 UefiInternalFormRepresentation.h 　
11839
 EFI_HII_GIBT_DUPLICATEEFI_HII_GIBT_DUPLICATE 0x20 UefiInternalFormRepresentation.h 　
11840
 EFI_HII_GIBT_SKIP2EFI_HII_GIBT_SKIP2 0x21 UefiInternalFormRepresentation.h 　
11841
 EFI_HII_GIBT_SKIP1EFI_HII_GIBT_SKIP1 0x22 UefiInternalFormRepresentation.h 　
11842
 EFI_HII_GIBT_DEFAULTSEFI_HII_GIBT_DEFAULTS 0x23 UefiInternalFormRepresentation.h 　
11843
 EFI_HII_GIBT_EXT1EFI_HII_GIBT_EXT1 0x30 UefiInternalFormRepresentation.h 　
11844
 EFI_HII_GIBT_EXT2EFI_HII_GIBT_EXT2 0x31 UefiInternalFormRepresentation.h 　
11845
 EFI_HII_GIBT_EXT4EFI_HII_GIBT_EXT4 0x32 UefiInternalFormRepresentation.h 　
11846
 UEFI_CONFIG_LANGUEFI_CONFIG_LANG "x-UEFI" UefiInternalFormRepresentation.h 　
11847
 UEFI_CONFIG_LANG_2UEFI_CONFIG_LANG_2 "x-i-UEFI" UefiInternalFormRepresentation.h 　
11848
 EFI_HII_SIBT_ENDEFI_HII_SIBT_END 0x00 UefiInternalFormRepresentation.h 　
11849
 EFI_HII_SIBT_STRING_SCSUEFI_HII_SIBT_STRING_SCSU 0x10 UefiInternalFormRepresentation.h 　
11850
 EFI_HII_SIBT_STRING_SCSU_FONTEFI_HII_SIBT_STRING_SCSU_FONT 0x11 UefiInternalFormRepresentation.h 　
11851
 EFI_HII_SIBT_STRINGS_SCSUEFI_HII_SIBT_STRINGS_SCSU 0x12 UefiInternalFormRepresentation.h 　
11852
 EFI_HII_SIBT_STRINGS_SCSU_FONTEFI_HII_SIBT_STRINGS_SCSU_FONT 0x13 UefiInternalFormRepresentation.h 　
11853
 EFI_HII_SIBT_STRING_UCS2EFI_HII_SIBT_STRING_UCS2 0x14 UefiInternalFormRepresentation.h 　
11854
 EFI_HII_SIBT_STRING_UCS2_FONTEFI_HII_SIBT_STRING_UCS2_FONT 0x15 UefiInternalFormRepresentation.h 　
11855
 EFI_HII_SIBT_STRINGS_UCS2EFI_HII_SIBT_STRINGS_UCS2 0x16 UefiInternalFormRepresentation.h 　
11856
 EFI_HII_SIBT_STRINGS_UCS2_FONTEFI_HII_SIBT_STRINGS_UCS2_FONT 0x17 UefiInternalFormRepresentation.h 　
11857
 EFI_HII_SIBT_DUPLICATEEFI_HII_SIBT_DUPLICATE 0x20 UefiInternalFormRepresentation.h 　
11858
 EFI_HII_SIBT_SKIP2EFI_HII_SIBT_SKIP2 0x21 UefiInternalFormRepresentation.h 　
11859
 EFI_HII_SIBT_SKIP1EFI_HII_SIBT_SKIP1 0x22 UefiInternalFormRepresentation.h 　
11860
 EFI_HII_SIBT_EXT1EFI_HII_SIBT_EXT1 0x30 UefiInternalFormRepresentation.h 　
11861
 EFI_HII_SIBT_EXT2EFI_HII_SIBT_EXT2 0x31 UefiInternalFormRepresentation.h 　
11862
 EFI_HII_SIBT_EXT4EFI_HII_SIBT_EXT4 0x32 UefiInternalFormRepresentation.h 　
11863
 EFI_HII_SIBT_FONTEFI_HII_SIBT_FONT 0x40 UefiInternalFormRepresentation.h 　
11864
 EFI_HII_IIBT_ENDEFI_HII_IIBT_END 0x00 UefiInternalFormRepresentation.h 　
11865
 EFI_HII_IIBT_IMAGE_1BITEFI_HII_IIBT_IMAGE_1BIT 0x10 UefiInternalFormRepresentation.h 　
11866
 EFI_HII_IIBT_IMAGE_1BIT_TRANSEFI_HII_IIBT_IMAGE_1BIT_TRANS 0x11 UefiInternalFormRepresentation.h 　
11867
 EFI_HII_IIBT_IMAGE_4BITEFI_HII_IIBT_IMAGE_4BIT 0x12 UefiInternalFormRepresentation.h 　
11868
 EFI_HII_IIBT_IMAGE_4BIT_TRANSEFI_HII_IIBT_IMAGE_4BIT_TRANS 0x13 UefiInternalFormRepresentation.h 　
11869
 EFI_HII_IIBT_IMAGE_8BITEFI_HII_IIBT_IMAGE_8BIT 0x14 UefiInternalFormRepresentation.h 　
11870
 EFI_HII_IIBT_IMAGE_8BIT_TRANSEFI_HII_IIBT_IMAGE_8BIT_TRANS 0x15 UefiInternalFormRepresentation.h 　
11871
 EFI_HII_IIBT_IMAGE_24BITEFI_HII_IIBT_IMAGE_24BIT 0x16 UefiInternalFormRepresentation.h 　
11872
 EFI_HII_IIBT_IMAGE_24BIT_TRANSEFI_HII_IIBT_IMAGE_24BIT_TRANS 0x17 UefiInternalFormRepresentation.h 　
11873
 EFI_HII_IIBT_IMAGE_JPEGEFI_HII_IIBT_IMAGE_JPEG 0x18 UefiInternalFormRepresentation.h 　
11874
 EFI_HII_IIBT_DUPLICATEEFI_HII_IIBT_DUPLICATE 0x20 UefiInternalFormRepresentation.h 　
11875
 EFI_HII_IIBT_SKIP2EFI_HII_IIBT_SKIP2 0x21 UefiInternalFormRepresentation.h 　
11876
 EFI_HII_IIBT_SKIP1EFI_HII_IIBT_SKIP1 0x22 UefiInternalFormRepresentation.h 　
11877
 EFI_HII_IIBT_EXT1EFI_HII_IIBT_EXT1 0x30 UefiInternalFormRepresentation.h 　
11878
 EFI_HII_IIBT_EXT2EFI_HII_IIBT_EXT2 0x31 UefiInternalFormRepresentation.h 　
11879
 EFI_HII_IIBT_EXT4EFI_HII_IIBT_EXT4 0x32 UefiInternalFormRepresentation.h 　
11880
 EFI_IFR_FORM_OPEFI_IFR_FORM_OP 0x01 UefiInternalFormRepresentation.h 　
11881
 EFI_IFR_SUBTITLE_OPEFI_IFR_SUBTITLE_OP 0x02 UefiInternalFormRepresentation.h 　
11882
 EFI_IFR_TEXT_OPEFI_IFR_TEXT_OP 0x03 UefiInternalFormRepresentation.h 　
11883
 EFI_IFR_IMAGE_OPEFI_IFR_IMAGE_OP 0x04 UefiInternalFormRepresentation.h 　
11884
 EFI_IFR_ONE_OF_OPEFI_IFR_ONE_OF_OP 0x05 UefiInternalFormRepresentation.h 　
11885
 EFI_IFR_CHECKBOX_OPEFI_IFR_CHECKBOX_OP 0x06 UefiInternalFormRepresentation.h 　
11886
 EFI_IFR_NUMERIC_OPEFI_IFR_NUMERIC_OP 0x07 UefiInternalFormRepresentation.h 　
11887
 EFI_IFR_PASSWORD_OPEFI_IFR_PASSWORD_OP 0x08 UefiInternalFormRepresentation.h 　
11888
 EFI_IFR_ONE_OF_OPTION_OPEFI_IFR_ONE_OF_OPTION_OP 0x09 UefiInternalFormRepresentation.h 　
11889
 EFI_IFR_SUPPRESS_IF_OPEFI_IFR_SUPPRESS_IF_OP 0x0A UefiInternalFormRepresentation.h 　
11890
 EFI_IFR_LOCKED_OPEFI_IFR_LOCKED_OP 0x0B UefiInternalFormRepresentation.h 　
11891
 EFI_IFR_ACTION_OPEFI_IFR_ACTION_OP 0x0C UefiInternalFormRepresentation.h 　
11892
 EFI_IFR_RESET_BUTTON_OPEFI_IFR_RESET_BUTTON_OP 0x0D UefiInternalFormRepresentation.h 　
11893
 EFI_IFR_FORM_SET_OPEFI_IFR_FORM_SET_OP 0x0E UefiInternalFormRepresentation.h 　
11894
 EFI_IFR_REF_OPEFI_IFR_REF_OP 0x0F UefiInternalFormRepresentation.h 　
11895
 EFI_IFR_NO_SUBMIT_IF_OPEFI_IFR_NO_SUBMIT_IF_OP 0x10 UefiInternalFormRepresentation.h 　
11896
 EFI_IFR_INCONSISTENT_IF_OPEFI_IFR_INCONSISTENT_IF_OP 0x11 UefiInternalFormRepresentation.h 　
11897
 EFI_IFR_EQ_ID_VAL_OPEFI_IFR_EQ_ID_VAL_OP 0x12 UefiInternalFormRepresentation.h 　
11898
 EFI_IFR_EQ_ID_ID_OPEFI_IFR_EQ_ID_ID_OP 0x13 UefiInternalFormRepresentation.h 　
11899
 EFI_IFR_EQ_ID_LIST_OPEFI_IFR_EQ_ID_LIST_OP 0x14 UefiInternalFormRepresentation.h 　
11900
 EFI_IFR_AND_OPEFI_IFR_AND_OP 0x15 UefiInternalFormRepresentation.h 　
11901
 EFI_IFR_OR_OPEFI_IFR_OR_OP 0x16 UefiInternalFormRepresentation.h 　
11902
 EFI_IFR_NOT_OPEFI_IFR_NOT_OP 0x17 UefiInternalFormRepresentation.h 　
11903
 EFI_IFR_RULE_OPEFI_IFR_RULE_OP 0x18 UefiInternalFormRepresentation.h 　
11904
 EFI_IFR_GRAY_OUT_IF_OPEFI_IFR_GRAY_OUT_IF_OP 0x19 UefiInternalFormRepresentation.h 　
11905
 EFI_IFR_DATE_OPEFI_IFR_DATE_OP 0x1A UefiInternalFormRepresentation.h 　
11906
 EFI_IFR_TIME_OPEFI_IFR_TIME_OP 0x1B UefiInternalFormRepresentation.h 　
11907
 EFI_IFR_STRING_OPEFI_IFR_STRING_OP 0x1C UefiInternalFormRepresentation.h 　
11908
 EFI_IFR_REFRESH_OPEFI_IFR_REFRESH_OP 0x1D UefiInternalFormRepresentation.h 　
11909
 EFI_IFR_DISABLE_IF_OPEFI_IFR_DISABLE_IF_OP 0x1E UefiInternalFormRepresentation.h 　
11910
 EFI_IFR_ANIMATION_OPEFI_IFR_ANIMATION_OP 0x1F UefiInternalFormRepresentation.h 　
11911
 EFI_IFR_TO_LOWER_OPEFI_IFR_TO_LOWER_OP 0x20 UefiInternalFormRepresentation.h 　
11912
 EFI_IFR_TO_UPPER_OPEFI_IFR_TO_UPPER_OP 0x21 UefiInternalFormRepresentation.h 　
11913
 EFI_IFR_MAP_OPEFI_IFR_MAP_OP 0x22 UefiInternalFormRepresentation.h 　
11914
 EFI_IFR_ORDERED_LIST_OPEFI_IFR_ORDERED_LIST_OP 0x23 UefiInternalFormRepresentation.h 　
11915
 EFI_IFR_VARSTORE_OPEFI_IFR_VARSTORE_OP 0x24 UefiInternalFormRepresentation.h 　
11916
 EFI_IFR_VARSTORE_NAME_VALUE_OPEFI_IFR_VARSTORE_NAME_VALUE_OP 0x25 UefiInternalFormRepresentation.h 　
11917
 EFI_IFR_VARSTORE_EFI_OPEFI_IFR_VARSTORE_EFI_OP 0x26 UefiInternalFormRepresentation.h 　
11918
 EFI_IFR_VARSTORE_DEVICE_OPEFI_IFR_VARSTORE_DEVICE_OP 0x27 UefiInternalFormRepresentation.h 　
11919
 EFI_IFR_VERSION_OPEFI_IFR_VERSION_OP 0x28 UefiInternalFormRepresentation.h 　
11920
 EFI_IFR_END_OPEFI_IFR_END_OP 0x29 UefiInternalFormRepresentation.h 　
11921
 EFI_IFR_MATCH_OPEFI_IFR_MATCH_OP 0x2A UefiInternalFormRepresentation.h 　
11922
 EFI_IFR_GET_OPEFI_IFR_GET_OP 0x2B UefiInternalFormRepresentation.h 　
11923
 EFI_IFR_SET_OPEFI_IFR_SET_OP 0x2C UefiInternalFormRepresentation.h 　
11924
 EFI_IFR_READ_OPEFI_IFR_READ_OP 0x2D UefiInternalFormRepresentation.h 　
11925
 EFI_IFR_WRITE_OPEFI_IFR_WRITE_OP 0x2E UefiInternalFormRepresentation.h 　
11926
 EFI_IFR_EQUAL_OPEFI_IFR_EQUAL_OP 0x2F UefiInternalFormRepresentation.h 　
11927
 EFI_IFR_NOT_EQUAL_OPEFI_IFR_NOT_EQUAL_OP 0x30 UefiInternalFormRepresentation.h 　
11928
 EFI_IFR_GREATER_THAN_OPEFI_IFR_GREATER_THAN_OP 0x31 UefiInternalFormRepresentation.h 　
11929
 EFI_IFR_GREATER_EQUAL_OPEFI_IFR_GREATER_EQUAL_OP 0x32 UefiInternalFormRepresentation.h 　
11930
 EFI_IFR_LESS_THAN_OPEFI_IFR_LESS_THAN_OP 0x33 UefiInternalFormRepresentation.h 　
11931
 EFI_IFR_LESS_EQUAL_OPEFI_IFR_LESS_EQUAL_OP 0x34 UefiInternalFormRepresentation.h 　
11932
 EFI_IFR_BITWISE_AND_OPEFI_IFR_BITWISE_AND_OP 0x35 UefiInternalFormRepresentation.h 　
11933
 EFI_IFR_BITWISE_OR_OPEFI_IFR_BITWISE_OR_OP 0x36 UefiInternalFormRepresentation.h 　
11934
 EFI_IFR_BITWISE_NOT_OPEFI_IFR_BITWISE_NOT_OP 0x37 UefiInternalFormRepresentation.h 　
11935
 EFI_IFR_SHIFT_LEFT_OPEFI_IFR_SHIFT_LEFT_OP 0x38 UefiInternalFormRepresentation.h 　
11936
 EFI_IFR_SHIFT_RIGHT_OPEFI_IFR_SHIFT_RIGHT_OP 0x39 UefiInternalFormRepresentation.h 　
11937
 EFI_IFR_ADD_OPEFI_IFR_ADD_OP 0x3A UefiInternalFormRepresentation.h 　
11938
 EFI_IFR_SUBTRACT_OPEFI_IFR_SUBTRACT_OP 0x3B UefiInternalFormRepresentation.h 　
11939
 EFI_IFR_MULTIPLY_OPEFI_IFR_MULTIPLY_OP 0x3C UefiInternalFormRepresentation.h 　
11940
 EFI_IFR_DIVIDE_OPEFI_IFR_DIVIDE_OP 0x3D UefiInternalFormRepresentation.h 　
11941
 EFI_IFR_MODULO_OPEFI_IFR_MODULO_OP 0x3E UefiInternalFormRepresentation.h 　
11942
 EFI_IFR_RULE_REF_OPEFI_IFR_RULE_REF_OP 0x3F UefiInternalFormRepresentation.h 　
11943
 EFI_IFR_QUESTION_REF1_OPEFI_IFR_QUESTION_REF1_OP 0x40 UefiInternalFormRepresentation.h 　
11944
 EFI_IFR_QUESTION_REF2_OPEFI_IFR_QUESTION_REF2_OP 0x41 UefiInternalFormRepresentation.h 　
11945
 EFI_IFR_UINT8_OPEFI_IFR_UINT8_OP 0x42 UefiInternalFormRepresentation.h 　
11946
 EFI_IFR_UINT16_OPEFI_IFR_UINT16_OP 0x43 UefiInternalFormRepresentation.h 　
11947
 EFI_IFR_UINT32_OPEFI_IFR_UINT32_OP 0x44 UefiInternalFormRepresentation.h 　
11948
 EFI_IFR_UINT64_OPEFI_IFR_UINT64_OP 0x45 UefiInternalFormRepresentation.h 　
11949
 EFI_IFR_TRUE_OPEFI_IFR_TRUE_OP 0x46 UefiInternalFormRepresentation.h 　
11950
 EFI_IFR_FALSE_OPEFI_IFR_FALSE_OP 0x47 UefiInternalFormRepresentation.h 　
11951
 EFI_IFR_TO_UINT_OPEFI_IFR_TO_UINT_OP 0x48 UefiInternalFormRepresentation.h 　
11952
 EFI_IFR_TO_STRING_OPEFI_IFR_TO_STRING_OP 0x49 UefiInternalFormRepresentation.h 　
11953
 EFI_IFR_TO_BOOLEAN_OPEFI_IFR_TO_BOOLEAN_OP 0x4A UefiInternalFormRepresentation.h 　
11954
 EFI_IFR_MID_OPEFI_IFR_MID_OP 0x4B UefiInternalFormRepresentation.h 　
11955
 EFI_IFR_FIND_OPEFI_IFR_FIND_OP 0x4C UefiInternalFormRepresentation.h 　
11956
 EFI_IFR_TOKEN_OPEFI_IFR_TOKEN_OP 0x4D UefiInternalFormRepresentation.h 　
11957
 EFI_IFR_STRING_REF1_OPEFI_IFR_STRING_REF1_OP 0x4E UefiInternalFormRepresentation.h 　
11958
 EFI_IFR_STRING_REF2_OPEFI_IFR_STRING_REF2_OP 0x4F UefiInternalFormRepresentation.h 　
11959
 EFI_IFR_CONDITIONAL_OPEFI_IFR_CONDITIONAL_OP 0x50 UefiInternalFormRepresentation.h 　
11960
 EFI_IFR_QUESTION_REF3_OPEFI_IFR_QUESTION_REF3_OP 0x51 UefiInternalFormRepresentation.h 　
11961
 EFI_IFR_ZERO_OPEFI_IFR_ZERO_OP 0x52 UefiInternalFormRepresentation.h 　
11962
 EFI_IFR_ONE_OPEFI_IFR_ONE_OP 0x53 UefiInternalFormRepresentation.h 　
11963
 EFI_IFR_ONES_OPEFI_IFR_ONES_OP 0x54 UefiInternalFormRepresentation.h 　
11964
 EFI_IFR_UNDEFINED_OPEFI_IFR_UNDEFINED_OP 0x55 UefiInternalFormRepresentation.h 　
11965
 EFI_IFR_LENGTH_OPEFI_IFR_LENGTH_OP 0x56 UefiInternalFormRepresentation.h 　
11966
 EFI_IFR_DUP_OPEFI_IFR_DUP_OP 0x57 UefiInternalFormRepresentation.h 　
11967
 EFI_IFR_THIS_OPEFI_IFR_THIS_OP 0x58 UefiInternalFormRepresentation.h 　
11968
 EFI_IFR_SPAN_OPEFI_IFR_SPAN_OP 0x59 UefiInternalFormRepresentation.h 　
11969
 EFI_IFR_VALUE_OPEFI_IFR_VALUE_OP 0x5A UefiInternalFormRepresentation.h 　
11970
 EFI_IFR_DEFAULT_OPEFI_IFR_DEFAULT_OP 0x5B UefiInternalFormRepresentation.h 　
11971
 EFI_IFR_DEFAULTSTORE_OPEFI_IFR_DEFAULTSTORE_OP 0x5C UefiInternalFormRepresentation.h 　
11972
 EFI_IFR_FORM_MAP_OPEFI_IFR_FORM_MAP_OP 0x5D UefiInternalFormRepresentation.h 　
11973
 EFI_IFR_CATENATE_OPEFI_IFR_CATENATE_OP 0x5E UefiInternalFormRepresentation.h 　
11974
 EFI_IFR_GUID_OPEFI_IFR_GUID_OP 0x5F UefiInternalFormRepresentation.h 　
11975
 EFI_IFR_SECURITY_OPEFI_IFR_SECURITY_OP 0x60 UefiInternalFormRepresentation.h 　
11976
 EFI_IFR_FLAG_READ_ONLYEFI_IFR_FLAG_READ_ONLY 0x01 UefiInternalFormRepresentation.h 　
11977
 EFI_IFR_FLAG_CALLBACKEFI_IFR_FLAG_CALLBACK 0x04 UefiInternalFormRepresentation.h 　
11978
 EFI_IFR_FLAG_RESET_REQUIREDEFI_IFR_FLAG_RESET_REQUIRED 0x10 UefiInternalFormRepresentation.h 　
11979
 EFI_IFR_FLAG_OPTIONS_ONLYEFI_IFR_FLAG_OPTIONS_ONLY 0x80 UefiInternalFormRepresentation.h 　
11980
 EFI_HII_DEFAULT_CLASS_STANDARDEFI_HII_DEFAULT_CLASS_STANDARD 0x0000 UefiInternalFormRepresentation.h 　
11981
 EFI_HII_DEFAULT_CLASS_MANUFACTUEFI_HII_DEFAULT_CLASS_MANUFACTU 0x0001 UefiInternalFormRepresentation.h 　
11982
 EFI_HII_DEFAULT_CLASS_SAFEEFI_HII_DEFAULT_CLASS_SAFE 0x0002 UefiInternalFormRepresentation.h 　
11983
 EFI_HII_DEFAULT_CLASS_PLATFORM_EFI_HII_DEFAULT_CLASS_PLATFORM_ 0x4000 UefiInternalFormRepresentation.h 　
11984
 EFI_HII_DEFAULT_CLASS_PLATFORM_EFI_HII_DEFAULT_CLASS_PLATFORM_ 0x7fff UefiInternalFormRepresentation.h 　
11985
 EFI_HII_DEFAULT_CLASS_HARDWARE_EFI_HII_DEFAULT_CLASS_HARDWARE_ 0x8000 UefiInternalFormRepresentation.h 　
11986
 EFI_HII_DEFAULT_CLASS_HARDWARE_EFI_HII_DEFAULT_CLASS_HARDWARE_ 0xbfff UefiInternalFormRepresentation.h 　
11987
 EFI_HII_DEFAULT_CLASS_FIRMWARE_EFI_HII_DEFAULT_CLASS_FIRMWARE_ 0xc000 UefiInternalFormRepresentation.h 　
11988
 EFI_HII_DEFAULT_CLASS_FIRMWARE_EFI_HII_DEFAULT_CLASS_FIRMWARE_ 0xffff UefiInternalFormRepresentation.h 　
11989
 EFI_IFR_FLAGS_HORIZONTALEFI_IFR_FLAGS_HORIZONTAL 0x01 UefiInternalFormRepresentation.h 　
11990
 EFI_IFR_CHECKBOX_DEFAULTEFI_IFR_CHECKBOX_DEFAULT 0x01 UefiInternalFormRepresentation.h 　
11991
 EFI_IFR_CHECKBOX_DEFAULT_MFGEFI_IFR_CHECKBOX_DEFAULT_MFG 0x02 UefiInternalFormRepresentation.h 　
11992
 EFI_QF_DATE_YEAR_SUPPRESSEFI_QF_DATE_YEAR_SUPPRESS 0x01 UefiInternalFormRepresentation.h 　
11993
 EFI_QF_DATE_MONTH_SUPPRESSEFI_QF_DATE_MONTH_SUPPRESS 0x02 UefiInternalFormRepresentation.h 　
11994
 EFI_QF_DATE_DAY_SUPPRESSEFI_QF_DATE_DAY_SUPPRESS 0x04 UefiInternalFormRepresentation.h 　
11995
 EFI_QF_DATE_STORAGEEFI_QF_DATE_STORAGE 0x30 UefiInternalFormRepresentation.h 　
11996
 QF_DATE_STORAGE_NORMALQF_DATE_STORAGE_NORMAL 0x00 UefiInternalFormRepresentation.h 　
11997
 QF_DATE_STORAGE_TIMEQF_DATE_STORAGE_TIME 0x10 UefiInternalFormRepresentation.h 　
11998
 QF_DATE_STORAGE_WAKEUPQF_DATE_STORAGE_WAKEUP 0x20 UefiInternalFormRepresentation.h 　
11999
 EFI_IFR_NUMERIC_SIZEEFI_IFR_NUMERIC_SIZE 0x03 UefiInternalFormRepresentation.h 　
12000
 EFI_IFR_NUMERIC_SIZE_1EFI_IFR_NUMERIC_SIZE_1 0x00 UefiInternalFormRepresentation.h 　
12001
 EFI_IFR_NUMERIC_SIZE_2EFI_IFR_NUMERIC_SIZE_2 0x01 UefiInternalFormRepresentation.h 　
12002
 EFI_IFR_NUMERIC_SIZE_4EFI_IFR_NUMERIC_SIZE_4 0x02 UefiInternalFormRepresentation.h 　
12003
 EFI_IFR_NUMERIC_SIZE_8EFI_IFR_NUMERIC_SIZE_8 0x03 UefiInternalFormRepresentation.h 　
12004
 EFI_IFR_DISPLAYEFI_IFR_DISPLAY 0x30 UefiInternalFormRepresentation.h 　
12005
 EFI_IFR_DISPLAY_INT_DECEFI_IFR_DISPLAY_INT_DEC 0x00 UefiInternalFormRepresentation.h 　
12006
 EFI_IFR_DISPLAY_UINT_DECEFI_IFR_DISPLAY_UINT_DEC 0x10 UefiInternalFormRepresentation.h 　
12007
 EFI_IFR_DISPLAY_UINT_HEXEFI_IFR_DISPLAY_UINT_HEX 0x20 UefiInternalFormRepresentation.h 　
12008
 EFI_IFR_STRING_MULTI_LINEEFI_IFR_STRING_MULTI_LINE 0x01 UefiInternalFormRepresentation.h 　
12009
 EFI_IFR_UNIQUE_SETEFI_IFR_UNIQUE_SET 0x01 UefiInternalFormRepresentation.h 　
12010
 EFI_IFR_NO_EMPTY_SETEFI_IFR_NO_EMPTY_SET 0x02 UefiInternalFormRepresentation.h 　
12011
 QF_TIME_HOUR_SUPPRESSQF_TIME_HOUR_SUPPRESS 0x01 UefiInternalFormRepresentation.h 　
12012
 QF_TIME_MINUTE_SUPPRESSQF_TIME_MINUTE_SUPPRESS 0x02 UefiInternalFormRepresentation.h 　
12013
 QF_TIME_SECOND_SUPPRESSQF_TIME_SECOND_SUPPRESS 0x04 UefiInternalFormRepresentation.h 　
12014
 QF_TIME_STORAGEQF_TIME_STORAGE 0x30 UefiInternalFormRepresentation.h 　
12015
 QF_TIME_STORAGE_NORMALQF_TIME_STORAGE_NORMAL 0x00 UefiInternalFormRepresentation.h 　
12016
 QF_TIME_STORAGE_TIMEQF_TIME_STORAGE_TIME 0x10 UefiInternalFormRepresentation.h 　
12017
 QF_TIME_STORAGE_WAKEUPQF_TIME_STORAGE_WAKEUP 0x20 UefiInternalFormRepresentation.h 　
12018
 EFI_IFR_TYPE_NUM_SIZE_8EFI_IFR_TYPE_NUM_SIZE_8 0x00 UefiInternalFormRepresentation.h 　
12019
 EFI_IFR_TYPE_NUM_SIZE_16EFI_IFR_TYPE_NUM_SIZE_16 0x01 UefiInternalFormRepresentation.h 　
12020
 EFI_IFR_TYPE_NUM_SIZE_32EFI_IFR_TYPE_NUM_SIZE_32 0x02 UefiInternalFormRepresentation.h 　
12021
 EFI_IFR_TYPE_NUM_SIZE_64EFI_IFR_TYPE_NUM_SIZE_64 0x03 UefiInternalFormRepresentation.h 　
12022
 EFI_IFR_TYPE_BOOLEANEFI_IFR_TYPE_BOOLEAN 0x04 UefiInternalFormRepresentation.h 　
12023
 EFI_IFR_TYPE_TIMEEFI_IFR_TYPE_TIME 0x05 UefiInternalFormRepresentation.h 　
12024
 EFI_IFR_TYPE_DATEEFI_IFR_TYPE_DATE 0x06 UefiInternalFormRepresentation.h 　
12025
 EFI_IFR_TYPE_STRINGEFI_IFR_TYPE_STRING 0x07 UefiInternalFormRepresentation.h 　
12026
 EFI_IFR_TYPE_OTHEREFI_IFR_TYPE_OTHER 0x08 UefiInternalFormRepresentation.h 　
12027
 EFI_IFR_TYPE_UNDEFINEDEFI_IFR_TYPE_UNDEFINED 0x09 UefiInternalFormRepresentation.h 　
12028
 EFI_IFR_TYPE_ACTIONEFI_IFR_TYPE_ACTION 0x0A UefiInternalFormRepresentation.h 　
12029
 EFI_IFR_TYPE_BUFFEREFI_IFR_TYPE_BUFFER 0x0B UefiInternalFormRepresentation.h 　
12030
 EFI_IFR_OPTION_DEFAULTEFI_IFR_OPTION_DEFAULT 0x10 UefiInternalFormRepresentation.h 　
12031
 EFI_IFR_OPTION_DEFAULT_MFGEFI_IFR_OPTION_DEFAULT_MFG 0x20 UefiInternalFormRepresentation.h 　
12032
 EFI_IFR_STRING_UNSIGNED_DECEFI_IFR_STRING_UNSIGNED_DEC 0 UefiInternalFormRepresentation.h 　
12033
 EFI_IFR_STRING_SIGNED_DECEFI_IFR_STRING_SIGNED_DEC 1 UefiInternalFormRepresentation.h 　
12034
 EFI_IFR_STRING_LOWERCASE_HEXEFI_IFR_STRING_LOWERCASE_HEX 2 UefiInternalFormRepresentation.h 　
12035
 EFI_IFR_STRING_UPPERCASE_HEXEFI_IFR_STRING_UPPERCASE_HEX 3 UefiInternalFormRepresentation.h 　
12036
 EFI_IFR_STRING_ASCIIEFI_IFR_STRING_ASCII 0 UefiInternalFormRepresentation.h 　
12037
 EFI_IFR_STRING_UNICODEEFI_IFR_STRING_UNICODE 8 UefiInternalFormRepresentation.h 　
12038
 EFI_IFR_FF_CASE_SENSITIVEEFI_IFR_FF_CASE_SENSITIVE 0x00 UefiInternalFormRepresentation.h 　
12039
 EFI_IFR_FF_CASE_INSENSITIVEEFI_IFR_FF_CASE_INSENSITIVE 0x01 UefiInternalFormRepresentation.h 　
12040
 EFI_IFR_FLAGS_FIRST_MATCHINGEFI_IFR_FLAGS_FIRST_MATCHING 0x00 UefiInternalFormRepresentation.h 　
12041
 EFI_IFR_FLAGS_FIRST_NON_MATCHINEFI_IFR_FLAGS_FIRST_NON_MATCHIN 0x01 UefiInternalFormRepresentation.h 　
12042
 EFI_AFFECTED_BY_STANDARD_SHIFTEFI_AFFECTED_BY_STANDARD_SHIFT 0x0001 UefiInternalFormRepresentation.h 　
12043
 EFI_AFFECTED_BY_CAPS_LOCKEFI_AFFECTED_BY_CAPS_LOCK 0x0002 UefiInternalFormRepresentation.h 　
12044
 EFI_AFFECTED_BY_NUM_LOCKEFI_AFFECTED_BY_NUM_LOCK 0x0004 UefiInternalFormRepresentation.h 　
12045
 EFI_NULL_MODIFIEREFI_NULL_MODIFIER 0x0000 UefiInternalFormRepresentation.h 　
12046
 EFI_LEFT_CONTROL_MODIFIEREFI_LEFT_CONTROL_MODIFIER 0x0001 UefiInternalFormRepresentation.h 　
12047
 EFI_RIGHT_CONTROL_MODIFIEREFI_RIGHT_CONTROL_MODIFIER 0x0002 UefiInternalFormRepresentation.h 　
12048
 EFI_LEFT_ALT_MODIFIEREFI_LEFT_ALT_MODIFIER 0x0003 UefiInternalFormRepresentation.h 　
12049
 EFI_RIGHT_ALT_MODIFIEREFI_RIGHT_ALT_MODIFIER 0x0004 UefiInternalFormRepresentation.h 　
12050
 EFI_ALT_GR_MODIFIEREFI_ALT_GR_MODIFIER 0x0005 UefiInternalFormRepresentation.h 　
12051
 EFI_INSERT_MODIFIEREFI_INSERT_MODIFIER 0x0006 UefiInternalFormRepresentation.h 　
12052
 EFI_DELETE_MODIFIEREFI_DELETE_MODIFIER 0x0007 UefiInternalFormRepresentation.h 　
12053
 EFI_PAGE_DOWN_MODIFIEREFI_PAGE_DOWN_MODIFIER 0x0008 UefiInternalFormRepresentation.h 　
12054
 EFI_PAGE_UP_MODIFIEREFI_PAGE_UP_MODIFIER 0x0009 UefiInternalFormRepresentation.h 　
12055
 EFI_HOME_MODIFIEREFI_HOME_MODIFIER 0x000A UefiInternalFormRepresentation.h 　
12056
 EFI_END_MODIFIEREFI_END_MODIFIER 0x000B UefiInternalFormRepresentation.h 　
12057
 EFI_LEFT_SHIFT_MODIFIEREFI_LEFT_SHIFT_MODIFIER 0x000C UefiInternalFormRepresentation.h 　
12058
 EFI_RIGHT_SHIFT_MODIFIEREFI_RIGHT_SHIFT_MODIFIER 0x000D UefiInternalFormRepresentation.h 　
12059
 EFI_CAPS_LOCK_MODIFIEREFI_CAPS_LOCK_MODIFIER 0x000E UefiInternalFormRepresentation.h 　
12060
 EFI_NUM_LOCK_MODIFIEREFI_NUM_LOCK_MODIFIER 0x000F UefiInternalFormRepresentation.h 　
12061
 EFI_LEFT_ARROW_MODIFIEREFI_LEFT_ARROW_MODIFIER 0x0010 UefiInternalFormRepresentation.h 　
12062
 EFI_RIGHT_ARROW_MODIFIEREFI_RIGHT_ARROW_MODIFIER 0x0011 UefiInternalFormRepresentation.h 　
12063
 EFI_DOWN_ARROW_MODIFIEREFI_DOWN_ARROW_MODIFIER 0x0012 UefiInternalFormRepresentation.h 　
12064
 EFI_UP_ARROW_MODIFIEREFI_UP_ARROW_MODIFIER 0x0013 UefiInternalFormRepresentation.h 　
12065
 EFI_NS_KEY_MODIFIEREFI_NS_KEY_MODIFIER 0x0014 UefiInternalFormRepresentation.h 　
12066
 EFI_NS_KEY_DEPENDENCY_MODIFIEREFI_NS_KEY_DEPENDENCY_MODIFIER 0x0015 UefiInternalFormRepresentation.h 　
12067
 EFI_FUNCTION_KEY_ONE_MODIFIEREFI_FUNCTION_KEY_ONE_MODIFIER 0x0016 UefiInternalFormRepresentation.h 　
12068
 EFI_FUNCTION_KEY_TWO_MODIFIEREFI_FUNCTION_KEY_TWO_MODIFIER 0x0017 UefiInternalFormRepresentation.h 　
12069
 EFI_FUNCTION_KEY_THREE_MODIFIEREFI_FUNCTION_KEY_THREE_MODIFIER 0x0018 UefiInternalFormRepresentation.h 　
12070
 EFI_FUNCTION_KEY_FOUR_MODIFIEREFI_FUNCTION_KEY_FOUR_MODIFIER 0x0019 UefiInternalFormRepresentation.h 　
12071
 EFI_FUNCTION_KEY_FIVE_MODIFIEREFI_FUNCTION_KEY_FIVE_MODIFIER 0x001A UefiInternalFormRepresentation.h 　
12072
 EFI_FUNCTION_KEY_SIX_MODIFIEREFI_FUNCTION_KEY_SIX_MODIFIER 0x001B UefiInternalFormRepresentation.h 　
12073
 EFI_FUNCTION_KEY_SEVEN_MODIFIEREFI_FUNCTION_KEY_SEVEN_MODIFIER 0x001C UefiInternalFormRepresentation.h 　
12074
 EFI_FUNCTION_KEY_EIGHT_MODIFIEREFI_FUNCTION_KEY_EIGHT_MODIFIER 0x001D UefiInternalFormRepresentation.h 　
12075
 EFI_FUNCTION_KEY_NINE_MODIFIEREFI_FUNCTION_KEY_NINE_MODIFIER 0x001E UefiInternalFormRepresentation.h 　
12076
 EFI_FUNCTION_KEY_TEN_MODIFIEREFI_FUNCTION_KEY_TEN_MODIFIER 0x001F UefiInternalFormRepresentation.h 　
12077
 EFI_FUNCTION_KEY_ELEVEN_MODIFIEEFI_FUNCTION_KEY_ELEVEN_MODIFIE 0x0020 UefiInternalFormRepresentation.h 　
12078
 EFI_FUNCTION_KEY_TWELVE_MODIFIEEFI_FUNCTION_KEY_TWELVE_MODIFIE 0x0021 UefiInternalFormRepresentation.h 　
12079
 EFI_PRINT_MODIFIEREFI_PRINT_MODIFIER 0x0022 UefiInternalFormRepresentation.h 　
12080
 EFI_SYS_REQUEST_MODIFIEREFI_SYS_REQUEST_MODIFIER 0x0023 UefiInternalFormRepresentation.h 　
12081
 EFI_SCROLL_LOCK_MODIFIEREFI_SCROLL_LOCK_MODIFIER 0x0024 UefiInternalFormRepresentation.h 　
12082
 EFI_PAUSE_MODIFIEREFI_PAUSE_MODIFIER 0x0025 UefiInternalFormRepresentation.h 　
12083
 EFI_BREAK_MODIFIEREFI_BREAK_MODIFIER 0x0026 UefiInternalFormRepresentation.h 　
12084
 EFI_LEFT_LOGO_MODIFIEREFI_LEFT_LOGO_MODIFIER 0x0027 UefiInternalFormRepresentation.h 　
12085
 EFI_RIGHT_LOGO_MODIFIEREFI_RIGHT_LOGO_MODIFIER 0x0028 UefiInternalFormRepresentation.h 　
12086
 EFI_MENU_MODIFIEREFI_MENU_MODIFIER 0x0029 UefiInternalFormRepresentation.h 　
12087
 EFI_HII_AIBT_ENDEFI_HII_AIBT_END 0x00 UefiInternalFormRepresentation.h 　
12088
 EFI_HII_AIBT_OVERLAY_IMAGESEFI_HII_AIBT_OVERLAY_IMAGES 0x10 UefiInternalFormRepresentation.h 　
12089
 EFI_HII_AIBT_CLEAR_IMAGESEFI_HII_AIBT_CLEAR_IMAGES 0x11 UefiInternalFormRepresentation.h 　
12090
 EFI_HII_AIBT_RESTORE_SCRNEFI_HII_AIBT_RESTORE_SCRN 0x12 UefiInternalFormRepresentation.h 　
12091
 EFI_HII_AIBT_OVERLAY_IMAGES_LOOEFI_HII_AIBT_OVERLAY_IMAGES_LOO 0x18 UefiInternalFormRepresentation.h 　
12092
 EFI_HII_AIBT_CLEAR_IMAGES_LOOPEFI_HII_AIBT_CLEAR_IMAGES_LOOP 0x19 UefiInternalFormRepresentation.h 　
12093
 EFI_HII_AIBT_RESTORE_SCRN_LOOPEFI_HII_AIBT_RESTORE_SCRN_LOOP 0x1A UefiInternalFormRepresentation.h 　
12094
 EFI_HII_AIBT_DUPLICATEEFI_HII_AIBT_DUPLICATE 0x20 UefiInternalFormRepresentation.h 　
12095
 EFI_HII_AIBT_SKIP2EFI_HII_AIBT_SKIP2 0x21 UefiInternalFormRepresentation.h 　
12096
 EFI_HII_AIBT_SKIP1EFI_HII_AIBT_SKIP1 0x22 UefiInternalFormRepresentation.h 　
12097
 EFI_HII_AIBT_EXT1EFI_HII_AIBT_EXT1 0x30 UefiInternalFormRepresentation.h 　
12098
 EFI_HII_AIBT_EXT2EFI_HII_AIBT_EXT2 0x31 UefiInternalFormRepresentation.h 　
12099
 EFI_HII_AIBT_EXT4EFI_HII_AIBT_EXT4 0x32 UefiInternalFormRepresentation.h 　
12100
 EFI_VARIABLE_NON_VOLATILEEFI_VARIABLE_NON_VOLATILE 0x00000001 UefiMultiPhase.h 　
12101
 EFI_VARIABLE_BOOTSERVICE_ACCESSEFI_VARIABLE_BOOTSERVICE_ACCESS 0x00000002 UefiMultiPhase.h 　
12102
 EFI_VARIABLE_RUNTIME_ACCESSEFI_VARIABLE_RUNTIME_ACCESS 0x00000004 UefiMultiPhase.h 　
12103
 EFI_VARIABLE_HARDWARE_ERROR_RECEFI_VARIABLE_HARDWARE_ERROR_REC 0x00000008 UefiMultiPhase.h 　
12104
 EFI_VARIABLE_AUTHENTICATED_WRITEFI_VARIABLE_AUTHENTICATED_WRIT 0x00000010 UefiMultiPhase.h 　
12105
 PXE_BUSTYPE_PXEPXE_BUSTYPE_PXE PXE_BUSTYPE ('!', 'P', 'X', 'E') UefiPxe.h 　
12106
 PXE_BUSTYPE_PCIPXE_BUSTYPE_PCI PXE_BUSTYPE ('P', 'C', 'I', 'R') UefiPxe.h 　
12107
 PXE_BUSTYPE_PC_CARDPXE_BUSTYPE_PC_CARD PXE_BUSTYPE ('P', 'C', 'C', 'R') UefiPxe.h 　
12108
 PXE_BUSTYPE_USBPXE_BUSTYPE_USB PXE_BUSTYPE ('U', 'S', 'B', 'R') UefiPxe.h 　
12109
 PXE_BUSTYPE_1394PXE_BUSTYPE_1394 PXE_BUSTYPE ('1', '3', '9', '4') UefiPxe.h 　
12110
 PXE_CPBSIZE_NOT_USEDPXE_CPBSIZE_NOT_USED 0 UefiPxe.h < zero
12111
 PXE_DBSIZE_NOT_USEDPXE_DBSIZE_NOT_USED 0 UefiPxe.h < zero
12112
 PXE_CPBADDR_NOT_USEDPXE_CPBADDR_NOT_USED (PXE_UINT64) 0 UefiPxe.h < zero
12113
 PXE_DBADDR_NOT_USEDPXE_DBADDR_NOT_USED (PXE_UINT64) 0 UefiPxe.h < zero
12114
 PXE_CONSTPXE_CONST CONST UefiPxe.h 　
12115
 PXE_VOLATILEPXE_VOLATILE volatile UefiPxe.h 　
12116
 PXE_FALSEPXE_FALSE 0 UefiPxe.h < zero
12117
 PXE_TRUEPXE_TRUE (!PXE_FALSE) UefiPxe.h 　
12118
 PXE_OPCODE_GET_STATEPXE_OPCODE_GET_STATE 0x0000 UefiPxe.h 　
12119
 PXE_OPCODE_STARTPXE_OPCODE_START 0x0001 UefiPxe.h 　
12120
 PXE_OPCODE_STOPPXE_OPCODE_STOP 0x0002 UefiPxe.h 　
12121
 PXE_OPCODE_GET_INIT_INFOPXE_OPCODE_GET_INIT_INFO 0x0003 UefiPxe.h 　
12122
 PXE_OPCODE_GET_CONFIG_INFOPXE_OPCODE_GET_CONFIG_INFO 0x0004 UefiPxe.h 　
12123
 PXE_OPCODE_INITIALIZEPXE_OPCODE_INITIALIZE 0x0005 UefiPxe.h 　
12124
 PXE_OPCODE_RESETPXE_OPCODE_RESET 0x0006 UefiPxe.h 　
12125
 PXE_OPCODE_SHUTDOWNPXE_OPCODE_SHUTDOWN 0x0007 UefiPxe.h 　
12126
 PXE_OPCODE_INTERRUPT_ENABLESPXE_OPCODE_INTERRUPT_ENABLES 0x0008 UefiPxe.h 　
12127
 PXE_OPCODE_RECEIVE_FILTERSPXE_OPCODE_RECEIVE_FILTERS 0x0009 UefiPxe.h 　
12128
 PXE_OPCODE_STATION_ADDRESSPXE_OPCODE_STATION_ADDRESS 0x000A UefiPxe.h 　
12129
 PXE_OPCODE_STATISTICSPXE_OPCODE_STATISTICS 0x000B UefiPxe.h 　
12130
 PXE_OPCODE_MCAST_IP_TO_MACPXE_OPCODE_MCAST_IP_TO_MAC 0x000C UefiPxe.h 　
12131
 PXE_OPCODE_NVDATAPXE_OPCODE_NVDATA 0x000D UefiPxe.h 　
12132
 PXE_OPCODE_GET_STATUSPXE_OPCODE_GET_STATUS 0x000E UefiPxe.h 　
12133
 PXE_OPCODE_FILL_HEADERPXE_OPCODE_FILL_HEADER 0x000F UefiPxe.h 　
12134
 PXE_OPCODE_TRANSMITPXE_OPCODE_TRANSMIT 0x0010 UefiPxe.h 　
12135
 PXE_OPCODE_RECEIVEPXE_OPCODE_RECEIVE 0x0011 UefiPxe.h 　
12136
 PXE_OPCODE_LAST_VALIDPXE_OPCODE_LAST_VALID 0x0011 UefiPxe.h 　
12137
 PXE_OPFLAGS_NOT_USEDPXE_OPFLAGS_NOT_USED 0x0000 UefiPxe.h 　
12138
 PXE_OPFLAGS_INITIALIZE_CABLE_DEPXE_OPFLAGS_INITIALIZE_CABLE_DE 0x0001 UefiPxe.h 　
12139
 PXE_OPFLAGS_INITIALIZE_DETECT_CPXE_OPFLAGS_INITIALIZE_DETECT_C 0x0000 UefiPxe.h 　
12140
 PXE_OPFLAGS_INITIALIZE_DO_NOT_DPXE_OPFLAGS_INITIALIZE_DO_NOT_D 0x0001 UefiPxe.h 　
12141
 PXE_OPFLAGS_RESET_DISABLE_INTERPXE_OPFLAGS_RESET_DISABLE_INTER 0x0001 UefiPxe.h 　
12142
 PXE_OPFLAGS_RESET_DISABLE_FILTEPXE_OPFLAGS_RESET_DISABLE_FILTE 0x0002 UefiPxe.h 　
12143
 PXE_OPFLAGS_INTERRUPT_OPMASKPXE_OPFLAGS_INTERRUPT_OPMASK 0xC000 UefiPxe.h 　
12144
 PXE_OPFLAGS_INTERRUPT_ENABLEPXE_OPFLAGS_INTERRUPT_ENABLE 0x8000 UefiPxe.h 　
12145
 PXE_OPFLAGS_INTERRUPT_DISABLEPXE_OPFLAGS_INTERRUPT_DISABLE 0x4000 UefiPxe.h 　
12146
 PXE_OPFLAGS_INTERRUPT_READPXE_OPFLAGS_INTERRUPT_READ 0x0000 UefiPxe.h 　
12147
 PXE_OPFLAGS_INTERRUPT_RECEIVEPXE_OPFLAGS_INTERRUPT_RECEIVE 0x0001 UefiPxe.h 　
12148
 PXE_OPFLAGS_INTERRUPT_TRANSMITPXE_OPFLAGS_INTERRUPT_TRANSMIT 0x0002 UefiPxe.h 　
12149
 PXE_OPFLAGS_INTERRUPT_COMMANDPXE_OPFLAGS_INTERRUPT_COMMAND 0x0004 UefiPxe.h 　
12150
 PXE_OPFLAGS_INTERRUPT_SOFTWAREPXE_OPFLAGS_INTERRUPT_SOFTWARE 0x0008 UefiPxe.h 　
12151
 PXE_OPFLAGS_RECEIVE_FILTER_OPMAPXE_OPFLAGS_RECEIVE_FILTER_OPMA 0xC000 UefiPxe.h 　
12152
 PXE_OPFLAGS_RECEIVE_FILTER_ENABPXE_OPFLAGS_RECEIVE_FILTER_ENAB 0x8000 UefiPxe.h 　
12153
 PXE_OPFLAGS_RECEIVE_FILTER_DISAPXE_OPFLAGS_RECEIVE_FILTER_DISA 0x4000 UefiPxe.h 　
12154
 PXE_OPFLAGS_RECEIVE_FILTER_READPXE_OPFLAGS_RECEIVE_FILTER_READ 0x0000 UefiPxe.h 　
12155
 PXE_OPFLAGS_RECEIVE_FILTER_RESEPXE_OPFLAGS_RECEIVE_FILTER_RESE 0x2000 UefiPxe.h 　
12156
 PXE_OPFLAGS_RECEIVE_FILTER_UNICPXE_OPFLAGS_RECEIVE_FILTER_UNIC 0x0001 UefiPxe.h 　
12157
 PXE_OPFLAGS_RECEIVE_FILTER_BROAPXE_OPFLAGS_RECEIVE_FILTER_BROA 0x0002 UefiPxe.h 　
12158
 PXE_OPFLAGS_RECEIVE_FILTER_FILTPXE_OPFLAGS_RECEIVE_FILTER_FILT 0x0004 UefiPxe.h 　
12159
 PXE_OPFLAGS_RECEIVE_FILTER_PROMPXE_OPFLAGS_RECEIVE_FILTER_PROM 0x0008 UefiPxe.h 　
12160
 PXE_OPFLAGS_RECEIVE_FILTER_ALL_PXE_OPFLAGS_RECEIVE_FILTER_ALL_ 0x0010 UefiPxe.h 　
12161
 PXE_OPFLAGS_STATION_ADDRESS_REAPXE_OPFLAGS_STATION_ADDRESS_REA 0x0000 UefiPxe.h 　
12162
 PXE_OPFLAGS_STATION_ADDRESS_WRIPXE_OPFLAGS_STATION_ADDRESS_WRI 0x0000 UefiPxe.h 　
12163
 PXE_OPFLAGS_STATION_ADDRESS_RESPXE_OPFLAGS_STATION_ADDRESS_RES 0x0001 UefiPxe.h 　
12164
 PXE_OPFLAGS_STATISTICS_READPXE_OPFLAGS_STATISTICS_READ 0x0000 UefiPxe.h 　
12165
 PXE_OPFLAGS_STATISTICS_RESETPXE_OPFLAGS_STATISTICS_RESET 0x0001 UefiPxe.h 　
12166
 PXE_OPFLAGS_MCAST_IP_TO_MAC_OPMPXE_OPFLAGS_MCAST_IP_TO_MAC_OPM 0x0003 UefiPxe.h 　
12167
 PXE_OPFLAGS_MCAST_IPV4_TO_MACPXE_OPFLAGS_MCAST_IPV4_TO_MAC 0x0000 UefiPxe.h 　
12168
 PXE_OPFLAGS_MCAST_IPV6_TO_MACPXE_OPFLAGS_MCAST_IPV6_TO_MAC 0x0001 UefiPxe.h 　
12169
 PXE_OPFLAGS_NVDATA_OPMASKPXE_OPFLAGS_NVDATA_OPMASK 0x0001 UefiPxe.h 　
12170
 PXE_OPFLAGS_NVDATA_READPXE_OPFLAGS_NVDATA_READ 0x0000 UefiPxe.h 　
12171
 PXE_OPFLAGS_NVDATA_WRITEPXE_OPFLAGS_NVDATA_WRITE 0x0001 UefiPxe.h 　
12172
 PXE_OPFLAGS_GET_INTERRUPT_STATUPXE_OPFLAGS_GET_INTERRUPT_STATU 0x0001 UefiPxe.h 　
12173
 PXE_OPFLAGS_GET_TRANSMITTED_BUFPXE_OPFLAGS_GET_TRANSMITTED_BUF 0x0002 UefiPxe.h 　
12174
 PXE_OPFLAGS_GET_MEDIA_STATUSPXE_OPFLAGS_GET_MEDIA_STATUS 0x0004 UefiPxe.h 　
12175
 PXE_OPFLAGS_FILL_HEADER_OPMASKPXE_OPFLAGS_FILL_HEADER_OPMASK 0x0001 UefiPxe.h 　
12176
 PXE_OPFLAGS_FILL_HEADER_FRAGMENPXE_OPFLAGS_FILL_HEADER_FRAGMEN 0x0001 UefiPxe.h 　
12177
 PXE_OPFLAGS_FILL_HEADER_WHOLEPXE_OPFLAGS_FILL_HEADER_WHOLE 0x0000 UefiPxe.h 　
12178
 PXE_OPFLAGS_SWUNDI_TRANSMIT_OPMPXE_OPFLAGS_SWUNDI_TRANSMIT_OPM 0x0001 UefiPxe.h 　
12179
 PXE_OPFLAGS_TRANSMIT_BLOCKPXE_OPFLAGS_TRANSMIT_BLOCK 0x0001 UefiPxe.h 　
12180
 PXE_OPFLAGS_TRANSMIT_DONT_BLOCKPXE_OPFLAGS_TRANSMIT_DONT_BLOCK 0x0000 UefiPxe.h 　
12181
 PXE_OPFLAGS_TRANSMIT_OPMASKPXE_OPFLAGS_TRANSMIT_OPMASK 0x0002 UefiPxe.h 　
12182
 PXE_OPFLAGS_TRANSMIT_FRAGMENTEDPXE_OPFLAGS_TRANSMIT_FRAGMENTED 0x0002 UefiPxe.h 　
12183
 PXE_OPFLAGS_TRANSMIT_WHOLEPXE_OPFLAGS_TRANSMIT_WHOLE 0x0000 UefiPxe.h 　
12184
 PXE_STATFLAGS_INITIALIZEPXE_STATFLAGS_INITIALIZE 0x0000 UefiPxe.h 　
12185
 PXE_STATFLAGS_STATUS_MASKPXE_STATFLAGS_STATUS_MASK 0xC000 UefiPxe.h 　
12186
 PXE_STATFLAGS_COMMAND_COMPLETEPXE_STATFLAGS_COMMAND_COMPLETE 0xC000 UefiPxe.h 　
12187
 PXE_STATFLAGS_COMMAND_FAILEDPXE_STATFLAGS_COMMAND_FAILED 0x8000 UefiPxe.h 　
12188
 PXE_STATFLAGS_COMMAND_QUEUEDPXE_STATFLAGS_COMMAND_QUEUED 0x4000 UefiPxe.h 　
12189
 PXE_STATFLAGS_GET_STATE_MASKPXE_STATFLAGS_GET_STATE_MASK 0x0003 UefiPxe.h 　
12190
 PXE_STATFLAGS_GET_STATE_INITIALPXE_STATFLAGS_GET_STATE_INITIAL 0x0002 UefiPxe.h 　
12191
 PXE_STATFLAGS_GET_STATE_STARTEDPXE_STATFLAGS_GET_STATE_STARTED 0x0001 UefiPxe.h 　
12192
 PXE_STATFLAGS_GET_STATE_STOPPEDPXE_STATFLAGS_GET_STATE_STOPPED 0x0000 UefiPxe.h 　
12193
 PXE_STATFLAGS_CABLE_DETECT_MASKPXE_STATFLAGS_CABLE_DETECT_MASK 0x0001 UefiPxe.h 　
12194
 PXE_STATFLAGS_CABLE_DETECT_NOT_PXE_STATFLAGS_CABLE_DETECT_NOT_ 0x0000 UefiPxe.h 　
12195
 PXE_STATFLAGS_CABLE_DETECT_SUPPPXE_STATFLAGS_CABLE_DETECT_SUPP 0x0001 UefiPxe.h 　
12196
 PXE_STATFLAGS_GET_STATUS_NO_MEDPXE_STATFLAGS_GET_STATUS_NO_MED 0x0002 UefiPxe.h 　
12197
 PXE_STATFLAGS_GET_STATUS_NO_MEDPXE_STATFLAGS_GET_STATUS_NO_MED 0x0000 UefiPxe.h 　
12198
 PXE_STATFLAGS_GET_STATUS_NO_MEDPXE_STATFLAGS_GET_STATUS_NO_MED 0x0002 UefiPxe.h 　
12199
 PXE_STATFLAGS_INITIALIZED_NO_MEPXE_STATFLAGS_INITIALIZED_NO_ME 0x0001 UefiPxe.h 　
12200
 PXE_STATFLAGS_RESET_NO_MEDIAPXE_STATFLAGS_RESET_NO_MEDIA 0x0001 UefiPxe.h 　
12201
 PXE_STATFLAGS_INTERRUPT_RECEIVEPXE_STATFLAGS_INTERRUPT_RECEIVE 0x0001 UefiPxe.h 　
12202
 PXE_STATFLAGS_INTERRUPT_TRANSMIPXE_STATFLAGS_INTERRUPT_TRANSMI 0x0002 UefiPxe.h 　
12203
 PXE_STATFLAGS_INTERRUPT_COMMANDPXE_STATFLAGS_INTERRUPT_COMMAND 0x0004 UefiPxe.h 　
12204
 PXE_STATFLAGS_RECEIVE_FILTER_UNPXE_STATFLAGS_RECEIVE_FILTER_UN 0x0001 UefiPxe.h 　
12205
 PXE_STATFLAGS_RECEIVE_FILTER_BRPXE_STATFLAGS_RECEIVE_FILTER_BR 0x0002 UefiPxe.h 　
12206
 PXE_STATFLAGS_RECEIVE_FILTER_FIPXE_STATFLAGS_RECEIVE_FILTER_FI 0x0004 UefiPxe.h 　
12207
 PXE_STATFLAGS_RECEIVE_FILTER_PRPXE_STATFLAGS_RECEIVE_FILTER_PR 0x0008 UefiPxe.h 　
12208
 PXE_STATFLAGS_RECEIVE_FILTER_ALPXE_STATFLAGS_RECEIVE_FILTER_AL 0x0010 UefiPxe.h 　
12209
 PXE_STATFLAGS_GET_STATUS_INTERRPXE_STATFLAGS_GET_STATUS_INTERR 0x000F UefiPxe.h 　
12210
 PXE_STATFLAGS_GET_STATUS_NO_INTPXE_STATFLAGS_GET_STATUS_NO_INT 0x0000 UefiPxe.h 　
12211
 PXE_STATFLAGS_GET_STATUS_RECEIVPXE_STATFLAGS_GET_STATUS_RECEIV 0x0001 UefiPxe.h 　
12212
 PXE_STATFLAGS_GET_STATUS_TRANSMPXE_STATFLAGS_GET_STATUS_TRANSM 0x0002 UefiPxe.h 　
12213
 PXE_STATFLAGS_GET_STATUS_COMMANPXE_STATFLAGS_GET_STATUS_COMMAN 0x0004 UefiPxe.h 　
12214
 PXE_STATFLAGS_GET_STATUS_SOFTWAPXE_STATFLAGS_GET_STATUS_SOFTWA 0x0008 UefiPxe.h 　
12215
 PXE_STATFLAGS_GET_STATUS_TXBUF_PXE_STATFLAGS_GET_STATUS_TXBUF_ 0x0010 UefiPxe.h 　
12216
 PXE_STATFLAGS_GET_STATUS_NO_TXBPXE_STATFLAGS_GET_STATUS_NO_TXB 0x0020 UefiPxe.h 　
12217
 PXE_STATFLAGS_GET_STATUS_NO_MEDPXE_STATFLAGS_GET_STATUS_NO_MED 0x0040 UefiPxe.h 　
12218
 PXE_STATCODE_INITIALIZEPXE_STATCODE_INITIALIZE 0x0000 UefiPxe.h 　
12219
 PXE_STATCODE_SUCCESSPXE_STATCODE_SUCCESS 0x0000 UefiPxe.h 　
12220
 PXE_STATCODE_INVALID_CDBPXE_STATCODE_INVALID_CDB 0x0001 UefiPxe.h 　
12221
 PXE_STATCODE_INVALID_CPBPXE_STATCODE_INVALID_CPB 0x0002 UefiPxe.h 　
12222
 PXE_STATCODE_BUSYPXE_STATCODE_BUSY 0x0003 UefiPxe.h 　
12223
 PXE_STATCODE_QUEUE_FULLPXE_STATCODE_QUEUE_FULL 0x0004 UefiPxe.h 　
12224
 PXE_STATCODE_ALREADY_STARTEDPXE_STATCODE_ALREADY_STARTED 0x0005 UefiPxe.h 　
12225
 PXE_STATCODE_NOT_STARTEDPXE_STATCODE_NOT_STARTED 0x0006 UefiPxe.h 　
12226
 PXE_STATCODE_NOT_SHUTDOWNPXE_STATCODE_NOT_SHUTDOWN 0x0007 UefiPxe.h 　
12227
 PXE_STATCODE_ALREADY_INITIALIZEPXE_STATCODE_ALREADY_INITIALIZE 0x0008 UefiPxe.h 　
12228
 PXE_STATCODE_NOT_INITIALIZEDPXE_STATCODE_NOT_INITIALIZED 0x0009 UefiPxe.h 　
12229
 PXE_STATCODE_DEVICE_FAILUREPXE_STATCODE_DEVICE_FAILURE 0x000A UefiPxe.h 　
12230
 PXE_STATCODE_NVDATA_FAILUREPXE_STATCODE_NVDATA_FAILURE 0x000B UefiPxe.h 　
12231
 PXE_STATCODE_UNSUPPORTEDPXE_STATCODE_UNSUPPORTED 0x000C UefiPxe.h 　
12232
 PXE_STATCODE_BUFFER_FULLPXE_STATCODE_BUFFER_FULL 0x000D UefiPxe.h 　
12233
 PXE_STATCODE_INVALID_PARAMETERPXE_STATCODE_INVALID_PARAMETER 0x000E UefiPxe.h 　
12234
 PXE_STATCODE_INVALID_UNDIPXE_STATCODE_INVALID_UNDI 0x000F UefiPxe.h 　
12235
 PXE_STATCODE_IPV4_NOT_SUPPORTEDPXE_STATCODE_IPV4_NOT_SUPPORTED 0x0010 UefiPxe.h 　
12236
 PXE_STATCODE_IPV6_NOT_SUPPORTEDPXE_STATCODE_IPV6_NOT_SUPPORTED 0x0011 UefiPxe.h 　
12237
 PXE_STATCODE_NOT_ENOUGH_MEMORYPXE_STATCODE_NOT_ENOUGH_MEMORY 0x0012 UefiPxe.h 　
12238
 PXE_STATCODE_NO_DATAPXE_STATCODE_NO_DATA 0x0013 UefiPxe.h 　
12239
 PXE_IFNUM_STARTPXE_IFNUM_START 0x0000 UefiPxe.h 　
12240
 PXE_IFNUM_INVALIDPXE_IFNUM_INVALID 0x0000 UefiPxe.h 　
12241
 PXE_CONTROL_QUEUE_IF_BUSYPXE_CONTROL_QUEUE_IF_BUSY 0x0002 UefiPxe.h 　
12242
 PXE_CONTROL_LINKPXE_CONTROL_LINK 0x0001 UefiPxe.h 　
12243
 PXE_CONTROL_LAST_CDB_IN_LISTPXE_CONTROL_LAST_CDB_IN_LIST 0x0000 UefiPxe.h 　
12244
 PXE_FRAME_TYPE_NONEPXE_FRAME_TYPE_NONE 0x00 UefiPxe.h 　
12245
 PXE_FRAME_TYPE_UNICASTPXE_FRAME_TYPE_UNICAST 0x01 UefiPxe.h 　
12246
 PXE_FRAME_TYPE_BROADCASTPXE_FRAME_TYPE_BROADCAST 0x02 UefiPxe.h 　
12247
 PXE_FRAME_TYPE_FILTERED_MULTICAPXE_FRAME_TYPE_FILTERED_MULTICA 0x03 UefiPxe.h 　
12248
 PXE_FRAME_TYPE_PROMISCUOUSPXE_FRAME_TYPE_PROMISCUOUS 0x04 UefiPxe.h 　
12249
 PXE_FRAME_TYPE_PROMISCUOUS_MULTPXE_FRAME_TYPE_PROMISCUOUS_MULT 0x05 UefiPxe.h 　
12250
 PXE_FRAME_TYPE_MULTICASTPXE_FRAME_TYPE_MULTICAST PXE_FRAME_TYPE_FILTERED_MULTICAST UefiPxe.h 　
12251
 PXE_MAC_LENGTHPXE_MAC_LENGTH 32 UefiPxe.h 　
12252
 PXE_IFTYPE_ETHERNETPXE_IFTYPE_ETHERNET 0x01 UefiPxe.h 　
12253
 PXE_IFTYPE_TOKENRINGPXE_IFTYPE_TOKENRING 0x04 UefiPxe.h 　
12254
 PXE_IFTYPE_FIBRE_CHANNELPXE_IFTYPE_FIBRE_CHANNEL 0x12 UefiPxe.h 　
12255
 PXE_HWSTAT_STATE_MASKPXE_HWSTAT_STATE_MASK 0xC0000000 UefiPxe.h 　
12256
 PXE_HWSTAT_BUSYPXE_HWSTAT_BUSY 0xC0000000 UefiPxe.h 　
12257
 PXE_HWSTAT_INITIALIZEDPXE_HWSTAT_INITIALIZED 0x80000000 UefiPxe.h 　
12258
 PXE_HWSTAT_STARTEDPXE_HWSTAT_STARTED 0x40000000 UefiPxe.h 　
12259
 PXE_HWSTAT_STOPPEDPXE_HWSTAT_STOPPED 0x00000000 UefiPxe.h 　
12260
 PXE_HWSTAT_COMMAND_FAILEDPXE_HWSTAT_COMMAND_FAILED 0x20000000 UefiPxe.h 　
12261
 PXE_HWSTAT_PROMISCUOUS_MULTICASPXE_HWSTAT_PROMISCUOUS_MULTICAS 0x00001000 UefiPxe.h 　
12262
 PXE_HWSTAT_PROMISCUOUS_RX_ENABLPXE_HWSTAT_PROMISCUOUS_RX_ENABL 0x00000800 UefiPxe.h 　
12263
 PXE_HWSTAT_BROADCAST_RX_ENABLEDPXE_HWSTAT_BROADCAST_RX_ENABLED 0x00000400 UefiPxe.h 　
12264
 PXE_HWSTAT_MULTICAST_RX_ENABLEDPXE_HWSTAT_MULTICAST_RX_ENABLED 0x00000200 UefiPxe.h 　
12265
 PXE_HWSTAT_UNICAST_RX_ENABLEDPXE_HWSTAT_UNICAST_RX_ENABLED 0x00000100 UefiPxe.h 　
12266
 PXE_HWSTAT_SOFTWARE_INT_ENABLEDPXE_HWSTAT_SOFTWARE_INT_ENABLED 0x00000080 UefiPxe.h 　
12267
 PXE_HWSTAT_TX_COMPLETE_INT_ENABPXE_HWSTAT_TX_COMPLETE_INT_ENAB 0x00000040 UefiPxe.h 　
12268
 PXE_HWSTAT_PACKET_RX_INT_ENABLEPXE_HWSTAT_PACKET_RX_INT_ENABLE 0x00000020 UefiPxe.h 　
12269
 PXE_HWSTAT_CMD_COMPLETE_INT_ENAPXE_HWSTAT_CMD_COMPLETE_INT_ENA 0x00000010 UefiPxe.h 　
12270
 PXE_HWSTAT_SOFTWARE_INT_PENDINGPXE_HWSTAT_SOFTWARE_INT_PENDING 0x00000008 UefiPxe.h 　
12271
 PXE_HWSTAT_TX_COMPLETE_INT_PENDPXE_HWSTAT_TX_COMPLETE_INT_PEND 0x00000004 UefiPxe.h 　
12272
 PXE_HWSTAT_PACKET_RX_INT_PENDINPXE_HWSTAT_PACKET_RX_INT_PENDIN 0x00000002 UefiPxe.h 　
12273
 PXE_HWSTAT_CMD_COMPLETE_INT_PENPXE_HWSTAT_CMD_COMPLETE_INT_PEN 0x00000001 UefiPxe.h 　
12274
 PXE_HWCMD_ISSUE_COMMANDPXE_HWCMD_ISSUE_COMMAND 0x80000000 UefiPxe.h 　
12275
 PXE_HWCMD_INTS_AND_FILTSPXE_HWCMD_INTS_AND_FILTS 0x00000000 UefiPxe.h 　
12276
 PXE_HWCMD_PROMISCUOUS_MULTICASTPXE_HWCMD_PROMISCUOUS_MULTICAST 0x00001000 UefiPxe.h 　
12277
 PXE_HWCMD_PROMISCUOUS_RX_ENABLEPXE_HWCMD_PROMISCUOUS_RX_ENABLE 0x00000800 UefiPxe.h 　
12278
 PXE_HWCMD_BROADCAST_RX_ENABLEPXE_HWCMD_BROADCAST_RX_ENABLE 0x00000400 UefiPxe.h 　
12279
 PXE_HWCMD_MULTICAST_RX_ENABLEPXE_HWCMD_MULTICAST_RX_ENABLE 0x00000200 UefiPxe.h 　
12280
 PXE_HWCMD_UNICAST_RX_ENABLEPXE_HWCMD_UNICAST_RX_ENABLE 0x00000100 UefiPxe.h 　
12281
 PXE_HWCMD_SOFTWARE_INT_ENABLEPXE_HWCMD_SOFTWARE_INT_ENABLE 0x00000080 UefiPxe.h 　
12282
 PXE_HWCMD_TX_COMPLETE_INT_ENABLPXE_HWCMD_TX_COMPLETE_INT_ENABL 0x00000040 UefiPxe.h 　
12283
 PXE_HWCMD_PACKET_RX_INT_ENABLEPXE_HWCMD_PACKET_RX_INT_ENABLE 0x00000020 UefiPxe.h 　
12284
 PXE_HWCMD_CMD_COMPLETE_INT_ENABPXE_HWCMD_CMD_COMPLETE_INT_ENAB 0x00000010 UefiPxe.h 　
12285
 PXE_HWCMD_CLEAR_SOFTWARE_INTPXE_HWCMD_CLEAR_SOFTWARE_INT 0x00000008 UefiPxe.h 　
12286
 PXE_HWCMD_CLEAR_TX_COMPLETE_INTPXE_HWCMD_CLEAR_TX_COMPLETE_INT 0x00000004 UefiPxe.h 　
12287
 PXE_HWCMD_CLEAR_PACKET_RX_INTPXE_HWCMD_CLEAR_PACKET_RX_INT 0x00000002 UefiPxe.h 　
12288
 PXE_HWCMD_CLEAR_CMD_COMPLETE_INPXE_HWCMD_CLEAR_CMD_COMPLETE_IN 0x00000001 UefiPxe.h 　
12289
 PXE_ROMID_SIGNATUREPXE_ROMID_SIGNATURE PXE_BUSTYPE ('!', 'P', 'X', 'E') UefiPxe.h 　
12290
 PXE_ROMID_REVPXE_ROMID_REV 0x02 UefiPxe.h 　
12291
 PXE_ROMID_MAJORVERPXE_ROMID_MAJORVER 0x03 UefiPxe.h 　
12292
 PXE_ROMID_MINORVERPXE_ROMID_MINORVER 0x01 UefiPxe.h 　
12293
 PXE_ROMID_IMP_HW_UNDIPXE_ROMID_IMP_HW_UNDI 0x80000000 UefiPxe.h 　
12294
 PXE_ROMID_IMP_SW_VIRT_ADDRPXE_ROMID_IMP_SW_VIRT_ADDR 0x40000000 UefiPxe.h 　
12295
 PXE_ROMID_IMP_64BIT_DEVICEPXE_ROMID_IMP_64BIT_DEVICE 0x00010000 UefiPxe.h 　
12296
 PXE_ROMID_IMP_FRAG_SUPPORTEDPXE_ROMID_IMP_FRAG_SUPPORTED 0x00008000 UefiPxe.h 　
12297
 PXE_ROMID_IMP_CMD_LINK_SUPPORTEPXE_ROMID_IMP_CMD_LINK_SUPPORTE 0x00004000 UefiPxe.h 　
12298
 PXE_ROMID_IMP_CMD_QUEUE_SUPPORTPXE_ROMID_IMP_CMD_QUEUE_SUPPORT 0x00002000 UefiPxe.h 　
12299
 PXE_ROMID_IMP_MULTI_FRAME_SUPPOPXE_ROMID_IMP_MULTI_FRAME_SUPPO 0x00001000 UefiPxe.h 　
12300
 PXE_ROMID_IMP_NVDATA_SUPPORT_MAPXE_ROMID_IMP_NVDATA_SUPPORT_MA 0x00000C00 UefiPxe.h 　
12301
 PXE_ROMID_IMP_NVDATA_BULK_WRITAPXE_ROMID_IMP_NVDATA_BULK_WRITA 0x00000C00 UefiPxe.h 　
12302
 PXE_ROMID_IMP_NVDATA_SPARSE_WRIPXE_ROMID_IMP_NVDATA_SPARSE_WRI 0x00000800 UefiPxe.h 　
12303
 PXE_ROMID_IMP_NVDATA_READ_ONLYPXE_ROMID_IMP_NVDATA_READ_ONLY 0x00000400 UefiPxe.h 　
12304
 PXE_ROMID_IMP_NVDATA_NOT_AVAILAPXE_ROMID_IMP_NVDATA_NOT_AVAILA 0x00000000 UefiPxe.h 　
12305
 PXE_ROMID_IMP_STATISTICS_SUPPORPXE_ROMID_IMP_STATISTICS_SUPPOR 0x00000200 UefiPxe.h 　
12306
 PXE_ROMID_IMP_STATION_ADDR_SETTPXE_ROMID_IMP_STATION_ADDR_SETT 0x00000100 UefiPxe.h 　
12307
 PXE_ROMID_IMP_PROMISCUOUS_MULTIPXE_ROMID_IMP_PROMISCUOUS_MULTI 0x00000080 UefiPxe.h 　
12308
 PXE_ROMID_IMP_PROMISCUOUS_RX_SUPXE_ROMID_IMP_PROMISCUOUS_RX_SU 0x00000040 UefiPxe.h 　
12309
 PXE_ROMID_IMP_BROADCAST_RX_SUPPPXE_ROMID_IMP_BROADCAST_RX_SUPP 0x00000020 UefiPxe.h 　
12310
 PXE_ROMID_IMP_FILTERED_MULTICASPXE_ROMID_IMP_FILTERED_MULTICAS 0x00000010 UefiPxe.h 　
12311
 PXE_ROMID_IMP_SOFTWARE_INT_SUPPPXE_ROMID_IMP_SOFTWARE_INT_SUPP 0x00000008 UefiPxe.h 　
12312
 PXE_ROMID_IMP_TX_COMPLETE_INT_SPXE_ROMID_IMP_TX_COMPLETE_INT_S 0x00000004 UefiPxe.h 　
12313
 PXE_ROMID_IMP_PACKET_RX_INT_SUPPXE_ROMID_IMP_PACKET_RX_INT_SUP 0x00000002 UefiPxe.h 　
12314
 PXE_ROMID_IMP_CMD_COMPLETE_INT_PXE_ROMID_IMP_CMD_COMPLETE_INT_ 0x00000001 UefiPxe.h 　
12315
 MAX_PCI_CONFIG_LENMAX_PCI_CONFIG_LEN 64 UefiPxe.h < # of dwords.
12316
 MAX_EEPROM_LENMAX_EEPROM_LEN 128 UefiPxe.h < # of dwords.
12317
 MAX_XMIT_BUFFERSMAX_XMIT_BUFFERS 32 UefiPxe.h < recycling Q length for xmit_done.
12318
 MAX_MCAST_ADDRESS_CNTMAX_MCAST_ADDRESS_CNT 8 UefiPxe.h 　
12319
 TO_AND_FROM_DEVICETO_AND_FROM_DEVICE 0 UefiPxe.h 　
12320
 FROM_DEVICEFROM_DEVICE 1 UefiPxe.h 　
12321
 TO_DEVICETO_DEVICE 2 UefiPxe.h 　
12322
 PXE_DELAY_MILLISECONDPXE_DELAY_MILLISECOND 1000 UefiPxe.h 　
12323
 PXE_DELAY_SECONDPXE_DELAY_SECOND 1000000 UefiPxe.h 　
12324
 PXE_IO_READPXE_IO_READ 0 UefiPxe.h 　
12325
 PXE_IO_WRITEPXE_IO_WRITE 1 UefiPxe.h 　
12326
 PXE_MEM_READPXE_MEM_READ 2 UefiPxe.h 　
12327
 PXE_MEM_WRITEPXE_MEM_WRITE 4 UefiPxe.h 　
12328
 PXE_MAX_TXRX_UNIT_ETHERPXE_MAX_TXRX_UNIT_ETHER 1500 UefiPxe.h 　
12329
 PXE_HWADDR_LEN_ETHERPXE_HWADDR_LEN_ETHER 0x0006 UefiPxe.h 　
12330
 PXE_MAC_HEADER_LEN_ETHERPXE_MAC_HEADER_LEN_ETHER 0x000E UefiPxe.h 　
12331
 PXE_DUPLEX_ENABLE_FULL_SUPPORTEPXE_DUPLEX_ENABLE_FULL_SUPPORTE 1 UefiPxe.h 　
12332
 PXE_DUPLEX_FORCE_FULL_SUPPORTEDPXE_DUPLEX_FORCE_FULL_SUPPORTED 2 UefiPxe.h 　
12333
 PXE_LOOPBACK_INTERNAL_SUPPORTEDPXE_LOOPBACK_INTERNAL_SUPPORTED 1 UefiPxe.h 　
12334
 PXE_LOOPBACK_EXTERNAL_SUPPORTEDPXE_LOOPBACK_EXTERNAL_SUPPORTED 2 UefiPxe.h 　
12335
 PXE_DUPLEX_DEFAULTPXE_DUPLEX_DEFAULT 0x00 UefiPxe.h 　
12336
 PXE_FORCE_FULL_DUPLEXPXE_FORCE_FULL_DUPLEX 0x01 UefiPxe.h 　
12337
 PXE_ENABLE_FULL_DUPLEXPXE_ENABLE_FULL_DUPLEX 0x02 UefiPxe.h 　
12338
 PXE_FORCE_HALF_DUPLEXPXE_FORCE_HALF_DUPLEX 0x04 UefiPxe.h 　
12339
 PXE_DISABLE_FULL_DUPLEXPXE_DISABLE_FULL_DUPLEX 0x08 UefiPxe.h 　
12340
 LOOPBACK_NORMALLOOPBACK_NORMAL 0 UefiPxe.h 　
12341
 LOOPBACK_INTERNALLOOPBACK_INTERNAL 1 UefiPxe.h 　
12342
 LOOPBACK_EXTERNALLOOPBACK_EXTERNAL 2 UefiPxe.h 　
12343
 PXE_STATISTICS_RX_TOTAL_FRAMESPXE_STATISTICS_RX_TOTAL_FRAMES 0x00 UefiPxe.h 　
12344
 PXE_STATISTICS_RX_GOOD_FRAMESPXE_STATISTICS_RX_GOOD_FRAMES 0x01 UefiPxe.h 　
12345
 PXE_STATISTICS_RX_UNDERSIZE_FRAPXE_STATISTICS_RX_UNDERSIZE_FRA 0x02 UefiPxe.h 　
12346
 PXE_STATISTICS_RX_OVERSIZE_FRAMPXE_STATISTICS_RX_OVERSIZE_FRAM 0x03 UefiPxe.h 　
12347
 PXE_STATISTICS_RX_DROPPED_FRAMEPXE_STATISTICS_RX_DROPPED_FRAME 0x04 UefiPxe.h 　
12348
 PXE_STATISTICS_RX_UNICAST_FRAMEPXE_STATISTICS_RX_UNICAST_FRAME 0x05 UefiPxe.h 　
12349
 PXE_STATISTICS_RX_BROADCAST_FRAPXE_STATISTICS_RX_BROADCAST_FRA 0x06 UefiPxe.h 　
12350
 PXE_STATISTICS_RX_MULTICAST_FRAPXE_STATISTICS_RX_MULTICAST_FRA 0x07 UefiPxe.h 　
12351
 PXE_STATISTICS_RX_CRC_ERROR_FRAPXE_STATISTICS_RX_CRC_ERROR_FRA 0x08 UefiPxe.h 　
12352
 PXE_STATISTICS_RX_TOTAL_BYTESPXE_STATISTICS_RX_TOTAL_BYTES 0x09 UefiPxe.h 　
12353
 PXE_STATISTICS_TX_TOTAL_FRAMESPXE_STATISTICS_TX_TOTAL_FRAMES 0x0A UefiPxe.h 　
12354
 PXE_STATISTICS_TX_GOOD_FRAMESPXE_STATISTICS_TX_GOOD_FRAMES 0x0B UefiPxe.h 　
12355
 PXE_STATISTICS_TX_UNDERSIZE_FRAPXE_STATISTICS_TX_UNDERSIZE_FRA 0x0C UefiPxe.h 　
12356
 PXE_STATISTICS_TX_OVERSIZE_FRAMPXE_STATISTICS_TX_OVERSIZE_FRAM 0x0D UefiPxe.h 　
12357
 PXE_STATISTICS_TX_DROPPED_FRAMEPXE_STATISTICS_TX_DROPPED_FRAME 0x0E UefiPxe.h 　
12358
 PXE_STATISTICS_TX_UNICAST_FRAMEPXE_STATISTICS_TX_UNICAST_FRAME 0x0F UefiPxe.h 　
12359
 PXE_STATISTICS_TX_BROADCAST_FRAPXE_STATISTICS_TX_BROADCAST_FRA 0x10 UefiPxe.h 　
12360
 PXE_STATISTICS_TX_MULTICAST_FRAPXE_STATISTICS_TX_MULTICAST_FRA 0x11 UefiPxe.h 　
12361
 PXE_STATISTICS_TX_CRC_ERROR_FRAPXE_STATISTICS_TX_CRC_ERROR_FRA 0x12 UefiPxe.h 　
12362
 PXE_STATISTICS_TX_TOTAL_BYTESPXE_STATISTICS_TX_TOTAL_BYTES 0x13 UefiPxe.h 　
12363
 PXE_STATISTICS_COLLISIONSPXE_STATISTICS_COLLISIONS 0x14 UefiPxe.h 　
12364
 PXE_STATISTICS_UNSUPPORTED_PROTPXE_STATISTICS_UNSUPPORTED_PROT 0x15 UefiPxe.h 　
12365
 PXE_PROTOCOL_ETHERNET_IPPXE_PROTOCOL_ETHERNET_IP 0x0800 UefiPxe.h 　
12366
 PXE_PROTOCOL_ETHERNET_ARPPXE_PROTOCOL_ETHERNET_ARP 0x0806 UefiPxe.h 　
12367
 MAX_XMIT_FRAGMENTSMAX_XMIT_FRAGMENTS 16 UefiPxe.h 　
12368
 EFI_TIME_ADJUST_DAYLIGHTEFI_TIME_ADJUST_DAYLIGHT 0x01 UefiSpec.h 　
12369
 EFI_TIME_IN_DAYLIGHTEFI_TIME_IN_DAYLIGHT 0x02 UefiSpec.h 　
12370
 EFI_UNSPECIFIED_TIMEZONEEFI_UNSPECIFIED_TIMEZONE 0x07FF UefiSpec.h 　
12371
 EFI_MEMORY_UCEFI_MEMORY_UC 0x0000000000000001ULL UefiSpec.h 　
12372
 EFI_MEMORY_WCEFI_MEMORY_WC 0x0000000000000002ULL UefiSpec.h 　
12373
 EFI_MEMORY_WTEFI_MEMORY_WT 0x0000000000000004ULL UefiSpec.h 　
12374
 EFI_MEMORY_WBEFI_MEMORY_WB 0x0000000000000008ULL UefiSpec.h 　
12375
 EFI_MEMORY_UCEEFI_MEMORY_UCE 0x0000000000000010ULL UefiSpec.h 　
12376
 EFI_MEMORY_WPEFI_MEMORY_WP 0x0000000000001000ULL UefiSpec.h 　
12377
 EFI_MEMORY_RPEFI_MEMORY_RP 0x0000000000002000ULL UefiSpec.h 　
12378
 EFI_MEMORY_XPEFI_MEMORY_XP 0x0000000000004000ULL UefiSpec.h 　
12379
 EFI_MEMORY_RUNTIMEEFI_MEMORY_RUNTIME 0x8000000000000000ULL UefiSpec.h 　
12380
 EFI_MEMORY_DESCRIPTOR_VERSIONEFI_MEMORY_DESCRIPTOR_VERSION 1 UefiSpec.h 　
12381
 EFI_OPTIONAL_PTREFI_OPTIONAL_PTR 0x00000001 UefiSpec.h 　
12382
 EVT_TIMEREVT_TIMER 0x80000000 UefiSpec.h 　
12383
 EVT_RUNTIMEEVT_RUNTIME 0x40000000 UefiSpec.h 　
12384
 EVT_NOTIFY_WAITEVT_NOTIFY_WAIT 0x00000100 UefiSpec.h 　
12385
 EVT_NOTIFY_SIGNALEVT_NOTIFY_SIGNAL 0x00000200 UefiSpec.h 　
12386
 EVT_SIGNAL_EXIT_BOOT_SERVICESEVT_SIGNAL_EXIT_BOOT_SERVICES 0x00000201 UefiSpec.h 　
12387
 EVT_SIGNAL_VIRTUAL_ADDRESS_CHANEVT_SIGNAL_VIRTUAL_ADDRESS_CHAN 0x60000202 UefiSpec.h 　
12388
 EVT_RUNTIME_CONTEXTEVT_RUNTIME_CONTEXT 0x20000000 UefiSpec.h 　
12389
 TPL_APPLICATIONTPL_APPLICATION 4 UefiSpec.h 　
12390
 TPL_CALLBACKTPL_CALLBACK 8 UefiSpec.h 　
12391
 TPL_NOTIFYTPL_NOTIFY 16 UefiSpec.h 　
12392
 TPL_HIGH_LEVELTPL_HIGH_LEVEL 31 UefiSpec.h 　
12393
 EFI_OPEN_PROTOCOL_BY_HANDLE_PROEFI_OPEN_PROTOCOL_BY_HANDLE_PRO 0x00000001 UefiSpec.h 　
12394
 EFI_OPEN_PROTOCOL_GET_PROTOCOLEFI_OPEN_PROTOCOL_GET_PROTOCOL 0x00000002 UefiSpec.h 　
12395
 EFI_OPEN_PROTOCOL_TEST_PROTOCOLEFI_OPEN_PROTOCOL_TEST_PROTOCOL 0x00000004 UefiSpec.h 　
12396
 EFI_OPEN_PROTOCOL_BY_CHILD_CONTEFI_OPEN_PROTOCOL_BY_CHILD_CONT 0x00000008 UefiSpec.h 　
12397
 EFI_OPEN_PROTOCOL_BY_DRIVEREFI_OPEN_PROTOCOL_BY_DRIVER 0x00000010 UefiSpec.h 　
12398
 EFI_OPEN_PROTOCOL_EXCLUSIVEEFI_OPEN_PROTOCOL_EXCLUSIVE 0x00000020 UefiSpec.h 　
12399
 CAPSULE_FLAGS_PERSIST_ACROSS_RECAPSULE_FLAGS_PERSIST_ACROSS_RE 0x00010000 UefiSpec.h 　
12400
 CAPSULE_FLAGS_POPULATE_SYSTEM_TCAPSULE_FLAGS_POPULATE_SYSTEM_T 0x00020000 UefiSpec.h 　
12401
 CAPSULE_FLAGS_INITIATE_RESETCAPSULE_FLAGS_INITIATE_RESET 0x00040000 UefiSpec.h 　
12402
 EFI_SYSTEM_TABLE_SIGNATUREEFI_SYSTEM_TABLE_SIGNATURE SIGNATURE_64 ('I','B','I',' ','S','Y','S','T') UefiSpec.h 　
12403
 EFI_2_30_SYSTEM_TABLE_REVISIONEFI_2_30_SYSTEM_TABLE_REVISION ((2 << 16) | (30)) UefiSpec.h 　
12404
 EFI_2_20_SYSTEM_TABLE_REVISIONEFI_2_20_SYSTEM_TABLE_REVISION ((2 << 16) | (20)) UefiSpec.h 　
12405
 EFI_2_10_SYSTEM_TABLE_REVISIONEFI_2_10_SYSTEM_TABLE_REVISION ((2 << 16) | (10)) UefiSpec.h 　
12406
 EFI_2_00_SYSTEM_TABLE_REVISIONEFI_2_00_SYSTEM_TABLE_REVISION ((2 << 16) | (00)) UefiSpec.h 　
12407
 EFI_1_10_SYSTEM_TABLE_REVISIONEFI_1_10_SYSTEM_TABLE_REVISION ((1 << 16) | (10)) UefiSpec.h 　
12408
 EFI_1_02_SYSTEM_TABLE_REVISIONEFI_1_02_SYSTEM_TABLE_REVISION ((1 << 16) | (02)) UefiSpec.h 　
12409
 EFI_SYSTEM_TABLE_REVISIONEFI_SYSTEM_TABLE_REVISION EFI_2_30_SYSTEM_TABLE_REVISION UefiSpec.h 　
12410
 EFI_RUNTIME_SERVICES_SIGNATUREEFI_RUNTIME_SERVICES_SIGNATURE SIGNATURE_64 ('R','U','N','T','S','E','R','V') UefiSpec.h 　
12411
 EFI_RUNTIME_SERVICES_REVISIONEFI_RUNTIME_SERVICES_REVISION EFI_2_30_SYSTEM_TABLE_REVISION UefiSpec.h 　
12412
 EFI_BOOT_SERVICES_SIGNATUREEFI_BOOT_SERVICES_SIGNATURE SIGNATURE_64 ('B','O','O','T','S','E','R','V') UefiSpec.h 　
12413
 EFI_BOOT_SERVICES_REVISIONEFI_BOOT_SERVICES_REVISION EFI_2_30_SYSTEM_TABLE_REVISION UefiSpec.h 　
12414
 LOAD_OPTION_ACTIVELOAD_OPTION_ACTIVE 0x00000001 UefiSpec.h 　
12415
 LOAD_OPTION_FORCE_RECONNECTLOAD_OPTION_FORCE_RECONNECT 0x00000002 UefiSpec.h 　
12416
 LOAD_OPTION_HIDDENLOAD_OPTION_HIDDEN 0x00000008 UefiSpec.h 　
12417
 LOAD_OPTION_CATEGORYLOAD_OPTION_CATEGORY 0x00001F00 UefiSpec.h 　
12418
 LOAD_OPTION_CATEGORY_BOOTLOAD_OPTION_CATEGORY_BOOT 0x00000000 UefiSpec.h 　
12419
 LOAD_OPTION_CATEGORY_APPLOAD_OPTION_CATEGORY_APP 0x00000100 UefiSpec.h 　
12420
 EFI_BOOT_OPTION_SUPPORT_KEYEFI_BOOT_OPTION_SUPPORT_KEY 0x00000001 UefiSpec.h 　
12421
 EFI_BOOT_OPTION_SUPPORT_APPEFI_BOOT_OPTION_SUPPORT_APP 0x00000002 UefiSpec.h 　
12422
 EFI_BOOT_OPTION_SUPPORT_COUNTEFI_BOOT_OPTION_SUPPORT_COUNT 0x00000300 UefiSpec.h 　
12423
 EFI_REMOVABLE_MEDIA_FILE_NAME_IEFI_REMOVABLE_MEDIA_FILE_NAME_I L"\\EFI\\BOOT\\BOOTIA32.EFI" UefiSpec.h 　
12424
 EFI_REMOVABLE_MEDIA_FILE_NAME_IEFI_REMOVABLE_MEDIA_FILE_NAME_I L"\\EFI\\BOOT\\BOOTIA64.EFI" UefiSpec.h 　
12425
 EFI_REMOVABLE_MEDIA_FILE_NAME_XEFI_REMOVABLE_MEDIA_FILE_NAME_X L"\\EFI\\BOOT\\BOOTX64.EFI" UefiSpec.h 　
12426
 EFI_REMOVABLE_MEDIA_FILE_NAME_AEFI_REMOVABLE_MEDIA_FILE_NAME_A L"\\EFI\\BOOT\\BOOTARM.EFI" UefiSpec.h 　
12427
 EFI_REMOVABLE_MEDIA_FILE_NAMEEFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 UefiSpec.h 　
12428
 EFI_REMOVABLE_MEDIA_FILE_NAMEEFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 UefiSpec.h 　
12429
 EFI_REMOVABLE_MEDIA_FILE_NAMEEFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_X64 UefiSpec.h 　
12430
 EFI_REMOVABLE_MEDIA_FILE_NAMEEFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_ARM UefiSpec.h 　
12431
 MAX_BITMAX_BIT 0x8000000000000000ULL ProcessorBind.h 　
12432
 MAX_2_BITSMAX_2_BITS 0xC000000000000000ULL ProcessorBind.h 　
12433
 MAX_ADDRESSMAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL ProcessorBind.h 　
12434
 CPU_STACK_ALIGNMENTCPU_STACK_ALIGNMENT 16 ProcessorBind.h 　
12435
 EFIAPIEFIAPI __cdecl ProcessorBind.h 　
12436
 ASM_GLOBALASM_GLOBAL .globl ProcessorBind.h 　
12437
 ATTR_BOLDATTR_BOLD 0x08 efi_console.c 　
12438
 ATTR_FCOL_MASKATTR_FCOL_MASK 0x07 efi_console.c 　
12439
 ATTR_FCOL_BLACKATTR_FCOL_BLACK 0x00 efi_console.c 　
12440
 ATTR_FCOL_BLUEATTR_FCOL_BLUE 0x01 efi_console.c 　
12441
 ATTR_FCOL_GREENATTR_FCOL_GREEN 0x02 efi_console.c 　
12442
 ATTR_FCOL_CYANATTR_FCOL_CYAN 0x03 efi_console.c 　
12443
 ATTR_FCOL_REDATTR_FCOL_RED 0x04 efi_console.c 　
12444
 ATTR_FCOL_MAGENTAATTR_FCOL_MAGENTA 0x05 efi_console.c 　
12445
 ATTR_FCOL_YELLOWATTR_FCOL_YELLOW 0x06 efi_console.c 　
12446
 ATTR_FCOL_WHITEATTR_FCOL_WHITE 0x07 efi_console.c 　
12447
 ATTR_BCOL_MASKATTR_BCOL_MASK 0x70 efi_console.c 　
12448
 ATTR_BCOL_BLACKATTR_BCOL_BLACK 0x00 efi_console.c 　
12449
 ATTR_BCOL_BLUEATTR_BCOL_BLUE 0x10 efi_console.c 　
12450
 ATTR_BCOL_GREENATTR_BCOL_GREEN 0x20 efi_console.c 　
12451
 ATTR_BCOL_CYANATTR_BCOL_CYAN 0x30 efi_console.c 　
12452
 ATTR_BCOL_REDATTR_BCOL_RED 0x40 efi_console.c 　
12453
 ATTR_BCOL_MAGENTAATTR_BCOL_MAGENTA 0x50 efi_console.c 　
12454
 ATTR_BCOL_YELLOWATTR_BCOL_YELLOW 0x60 efi_console.c 　
12455
 ATTR_BCOL_WHITEATTR_BCOL_WHITE 0x70 efi_console.c 　
12456
 ATTR_DEFAULTATTR_DEFAULT ATTR_FCOL_WHITE efi_console.c 　
12457
 MAX_PORT_ADDRESSMAX_PORT_ADDRESS 0xffff efi_io.c 　
12458
 EFI_TIMER0_SHIFTEFI_TIMER0_SHIFT 12 efi_timer.c 　
12459
 EFI_CALIBRATE_DELAY_MSEFI_CALIBRATE_DELAY_MS 1 efi_timer.c 　
12460
 UNOWHEREUNOWHERE ( ~UNULL ) efi_umalloc.c 　
12461
 SMBIOS_TAG_MAGICSMBIOS_TAG_MAGIC 0x5B smbios_settings.c "SmBios"
12462
 SMBIOS_EMPTY_TAGSMBIOS_EMPTY_TAG ( SMBIOS_TAG_MAGIC << 24 ) smbios_settings.c 　
12463
 NUM_ARP_ENTRIESNUM_ARP_ENTRIES 4 arp.c 　
12464
 arp_table_endarp_table_end &arp_table[NUM_ARP_ENTRIES] arp.c 　
12465
 EINPROGRESS_INITEINPROGRESS_INIT ( EINPROGRESS | EUNIQ_01 ) infiniband.c 　
12466
 EINPROGRESS_ARMEDEINPROGRESS_ARMED ( EINPROGRESS | EUNIQ_02 ) infiniband.c 　
12467
 NUM_NDP_ENTRIESNUM_NDP_ENTRIES 4 ndp.c 　
12468
 ndp_table_endndp_table_end &ndp_table[NUM_NDP_ENTRIES] ndp.c 　
12469
 EUNKNOWN_LINK_STATUSEUNKNOWN_LINK_STATUS EINPROGRESS netdevice.c 　
12470
 MIN_TIMEOUTMIN_TIMEOUT 7 retry.c 　
12471
 EINVAL_PKT_TOO_SHORTEINVAL_PKT_TOO_SHORT ( EINVAL | EUNIQ_01 ) net80211.c 　
12472
 EINVAL_PKT_VERSIONEINVAL_PKT_VERSION ( EINVAL | EUNIQ_02 ) net80211.c 　
12473
 EINVAL_PKT_NOT_DATAEINVAL_PKT_NOT_DATA ( EINVAL | EUNIQ_03 ) net80211.c 　
12474
 EINVAL_PKT_NOT_FROMDSEINVAL_PKT_NOT_FROMDS ( EINVAL | EUNIQ_04 ) net80211.c 　
12475
 EINVAL_PKT_LLC_HEADEREINVAL_PKT_LLC_HEADER ( EINVAL | EUNIQ_05 ) net80211.c 　
12476
 EINVAL_CRYPTO_REQUESTEINVAL_CRYPTO_REQUEST ( EINVAL | EUNIQ_06 ) net80211.c 　
12477
 EINVAL_ACTIVE_SCANEINVAL_ACTIVE_SCAN ( EINVAL | EUNIQ_07 ) net80211.c 　
12478
 NET80211_PROBE_GATHERNET80211_PROBE_GATHER 1 net80211.c 　
12479
 NET80211_PROBE_GATHER_ALLNET80211_PROBE_GATHER_ALL 2 net80211.c 　
12480
 NET80211_PROBE_TIMEOUTNET80211_PROBE_TIMEOUT 6 net80211.c 　
12481
 ASSOC_TIMEOUTASSOC_TIMEOUT TICKS_PER_SEC net80211.c 　
12482
 ASSOC_RETRIESASSOC_RETRIES 2 net80211.c 　
12483
 LQ_SMOOTHLQ_SMOOTH 7 net80211.c 　
12484
 RC_PKT_OKRC_PKT_OK 0x3 rc80211.c 　
12485
 RC_PKT_RETRIED_ONCERC_PKT_RETRIED_ONCE 0x2 rc80211.c 　
12486
 RC_PKT_RETRIED_MULTIRC_PKT_RETRIED_MULTI 0x1 rc80211.c 　
12487
 RC_PKT_FAILEDRC_PKT_FAILED 0x0 rc80211.c 　
12488
 RC_TX_FACTORRC_TX_FACTOR 4 rc80211.c 　
12489
 RC_TX_EMERG_FAILRC_TX_EMERG_FAIL 3 rc80211.c 　
12490
 RC_GOODNESS_MINRC_GOODNESS_MIN 85 rc80211.c 　
12491
 RC_GOODNESS_MAXRC_GOODNESS_MAX 95 rc80211.c 　
12492
 RC_UNCERTAINTY_THRESHRC_UNCERTAINTY_THRESH 4 rc80211.c 　
12493
 TXTX 0 rc80211.c 　
12494
 RXRX 1 rc80211.c 　
12495
 END_MAGICEND_MAGIC 0xFFFFFFFF sec80211.c 　
12496
 WEP_IV_LENWEP_IV_LEN 3 wep.c 　
12497
 WEP_KID_LENWEP_KID_LEN 1 wep.c 　
12498
 WEP_ICV_LENWEP_ICV_LEN 4 wep.c 　
12499
 WEP_MAX_KEYWEP_MAX_KEY 16 wep.c 　
12500
 WEP_HEADER_LENWEP_HEADER_LEN 4 wep.c 　
12501
 WEP_TRAILER_LENWEP_TRAILER_LEN 4 wep.c 　
12502
 WEP_OVERHEADWEP_OVERHEAD 8 wep.c 　
12503
 CCMP_HEAD_LENCCMP_HEAD_LEN 8 wpa_ccmp.c 　
12504
 CCMP_MIC_LENCCMP_MIC_LEN 8 wpa_ccmp.c 　
12505
 CCMP_NONCE_LENCCMP_NONCE_LEN 13 wpa_ccmp.c 　
12506
 CCMP_AAD_LENCCMP_AAD_LEN 22 wpa_ccmp.c 　
12507
 CCMP_AAD_FC_MASKCCMP_AAD_FC_MASK 0xC38F wpa_ccmp.c 　
12508
 CCMP_AAD_SEQ_MASKCCMP_AAD_SEQ_MASK 0x000F wpa_ccmp.c 　
12509
 PN_MSBPN_MSB 1 wpa_ccmp.c 　
12510
 PN_LSBPN_LSB 0 wpa_ccmp.c 　
12511
 TKIP_HEAD_LENTKIP_HEAD_LEN 8 wpa_tkip.c 　
12512
 TKIP_FOOT_LENTKIP_FOOT_LEN 12 wpa_tkip.c 　
12513
 TKIP_MIC_LENTKIP_MIC_LEN 8 wpa_tkip.c 　
12514
 TKIP_ICV_LENTKIP_ICV_LEN 4 wpa_tkip.c 　
12515
 IB_CMRC_NUM_SEND_WQESIB_CMRC_NUM_SEND_WQES 4 ib_cmrc.c 　
12516
 IB_CMRC_NUM_RECV_WQESIB_CMRC_NUM_RECV_WQES 2 ib_cmrc.c 　
12517
 IB_CMRC_NUM_CQESIB_CMRC_NUM_CQES 8 ib_cmrc.c 　
12518
 IB_MI_NUM_SEND_WQESIB_MI_NUM_SEND_WQES 4 ib_mi.c 　
12519
 IB_MI_NUM_RECV_WQESIB_MI_NUM_RECV_WQES 2 ib_mi.c 　
12520
 IB_MI_NUM_CQESIB_MI_NUM_CQES 8 ib_mi.c 　
12521
 IB_MI_TID_MAGICIB_MI_TID_MAGIC ( ( 'g' << 24 ) | ( 'P' << 16 ) | ( 'X' << 8 ) | 'E' ) ib_mi.c 　
12522
 IB_NUM_CACHED_PATHSIB_NUM_CACHED_PATHS 4 ib_pathrec.c 　
12523
 EINVAL_BYTE_STRING_LENEINVAL_BYTE_STRING_LEN ( EINVAL | EUNIQ_01 ) ib_srp.c 　
12524
 EINVAL_BYTE_STRINGEINVAL_BYTE_STRING ( EINVAL | EUNIQ_02 ) ib_srp.c 　
12525
 EINVAL_INTEGEREINVAL_INTEGER ( EINVAL | EUNIQ_03 ) ib_srp.c 　
12526
 EINVAL_RP_TOO_SHORTEINVAL_RP_TOO_SHORT ( EINVAL | EUNIQ_04 ) ib_srp.c 　
12527
 IB_SRP_NUM_RP_COMPONENTSIB_SRP_NUM_RP_COMPONENTS ( sizeof ( ib_srp_rp_parser ) / sizeof ( ib_srp_rp_parser[0] ) ) ib_srp.c 　
12528
 EACCES_INCORRECT_TARGET_USERNAMEACCES_INCORRECT_TARGET_USERNAM ( EACCES | EUNIQ_01 ) iscsi.c 　
12529
 EACCES_INCORRECT_TARGET_PASSWOREACCES_INCORRECT_TARGET_PASSWOR ( EACCES | EUNIQ_02 ) iscsi.c 　
12530
 ENOTSUP_INITIATOR_STATUSENOTSUP_INITIATOR_STATUS ( ENOTSUP | EUNIQ_01 ) iscsi.c 　
12531
 ENOTSUP_OPCODEENOTSUP_OPCODE ( ENOTSUP | EUNIQ_02 ) iscsi.c 　
12532
 ENOTSUP_DISCOVERYENOTSUP_DISCOVERY ( ENOTSUP | EUNIQ_03 ) iscsi.c 　
12533
 EPERM_INITIATOR_AUTHENTICATIONEPERM_INITIATOR_AUTHENTICATION ( EPERM | EUNIQ_01 ) iscsi.c 　
12534
 EPERM_INITIATOR_AUTHORISATIONEPERM_INITIATOR_AUTHORISATION ( EPERM | EUNIQ_02 ) iscsi.c 　
12535
 EPROTO_INVALID_CHAP_ALGORITHMEPROTO_INVALID_CHAP_ALGORITHM ( EPROTO | EUNIQ_01 ) iscsi.c 　
12536
 EPROTO_INVALID_CHAP_IDENTIFIEREPROTO_INVALID_CHAP_IDENTIFIER ( EPROTO | EUNIQ_02 ) iscsi.c 　
12537
 EPROTO_INVALID_LARGE_BINARYEPROTO_INVALID_LARGE_BINARY ( EPROTO | EUNIQ_03 ) iscsi.c 　
12538
 EPROTO_INVALID_CHAP_RESPONSEEPROTO_INVALID_CHAP_RESPONSE ( EPROTO | EUNIQ_04 ) iscsi.c 　
12539
 DHCP_OFFER_IPDHCP_OFFER_IP 1 dhcp.c 　
12540
 DHCP_OFFER_PXEDHCP_OFFER_PXE 2 dhcp.c 　
12541
 DHCP_MAX_OFFERSDHCP_MAX_OFFERS 6 dhcp.c 　
12542
 SLAM_DEFAULT_PORTSLAM_DEFAULT_PORT 10000 slam.c 　
12543
 SLAM_DEFAULT_MULTICAST_IPSLAM_DEFAULT_MULTICAST_IP ( ( 239 << 24 ) | ( 255 << 16 ) | ( 1 << 8 ) | ( 1 << 0 ) ) slam.c 　
12544
 SLAM_DEFAULT_MULTICAST_PORTSLAM_DEFAULT_MULTICAST_PORT 10000 slam.c 　
12545
 SLAM_MAX_HEADER_LENSLAM_MAX_HEADER_LEN ( 7 + 7 + \ 7 ) slam.c block_size
12546
 SLAM_MAX_BLOCKS_PER_NACKSLAM_MAX_BLOCKS_PER_NACK 4 slam.c 　
12547
 SLAM_MAX_NACK_LENSLAM_MAX_NACK_LEN ( 7 + 7 + 1 ) slam.c block #blocks NUL
12548
 SLAM_SLAVE_TIMEOUTSLAM_SLAVE_TIMEOUT ( 1 * TICKS_PER_SEC ) slam.c 　
12549
 ETFTP_INVALID_BLKSIZEETFTP_INVALID_BLKSIZE EUNIQ_01 tftp.c 　
12550
 ETFTP_INVALID_TSIZEETFTP_INVALID_TSIZE EUNIQ_02 tftp.c 　
12551
 ETFTP_MC_NO_PORTETFTP_MC_NO_PORT EUNIQ_03 tftp.c 　
12552
 ETFTP_MC_NO_MCETFTP_MC_NO_MC EUNIQ_04 tftp.c 　
12553
 ETFTP_MC_INVALID_MCETFTP_MC_INVALID_MC EUNIQ_05 tftp.c 　
12554
 ETFTP_MC_INVALID_IPETFTP_MC_INVALID_IP EUNIQ_06 tftp.c 　
12555
 ETFTP_MC_INVALID_PORTETFTP_MC_INVALID_PORT EUNIQ_07 tftp.c 　
12556
 MTFTP_MAX_TIMEOUTSMTFTP_MAX_TIMEOUTS 3 tftp.c 　
12557
 __regparm__regparm __attribute__ (( regparm(3) )) memcpy_test.c 　
12558
 URI_MAX_LENURI_MAX_LEN 1024 uri_test.c 　
12559
 LINK_WAIT_MSLINK_WAIT_MS 15000 dhcpmgmt.c 　
12560
 NR_CRYPTO_TYPESNR_CRYPTO_TYPES ( sizeof ( crypto_types ) / sizeof ( crypto_types[0] ) ) iwmgmt.c 　
12561
 NR_AUTH_TYPESNR_AUTH_TYPES ( sizeof ( auth_types ) / sizeof ( auth_types[0] ) ) iwmgmt.c 　
12562
 ERRFILEERRFILE ERRFILE_net80211 iwmgmt.c 　
12563
 CPAIR_NORMALCPAIR_NORMAL 1 pxemenu.c 　
12564
 CPAIR_SELECTCPAIR_SELECT 2 pxemenu.c 　
12565
 EFI_FILE_ALIGNEFI_FILE_ALIGN 0x20 elf2efi.c 　
12566
 SNAPLENSNAPLEN 1600 hijack.c 　
12567
 HAVE_PCAP_INJECTHAVE_PCAP_INJECT 0 hijack.c 　
12568
 DEBUGDEBUG 0 iccfix.c 　
12569
 ELF_EHDRELF_EHDR Elf32_Ehdr iccfix.c 　
12570
 ELF_SHDRELF_SHDR Elf32_Shdr iccfix.c 　
12571
 ICCFIXICCFIX iccfix32 iccfix.c 　
12572
 ELF_EHDRELF_EHDR Elf64_Ehdr iccfix.c 　
12573
 ELF_SHDRELF_SHDR Elf64_Shdr iccfix.c 　
12574
 ICCFIXICCFIX iccfix64 iccfix.c 　
12575
 UCLPACK_COMPATUCLPACK_COMPAT 0 nrv2b.c 　
12576
 NDEBUGNDEBUG 1 nrv2b.c 　
12577
 wterrwterr 0 nrv2b.c 　
12578
 ENDIANENDIAN 0 nrv2b.c 　
12579
 BITSIZEBITSIZE 32 nrv2b.c 　
12580
 NN (65536ul) nrv2b.c size of ring buffer
12581
 THRESHOLDTHRESHOLD 1 nrv2b.c lower limit for match length
12582
 FF 2048 nrv2b.c upper limit for match length
12583
 M2_MAX_OFFSETM2_MAX_OFFSET 0xd00 nrv2b.c 　
12584
 UCL_E_OKUCL_E_OK 0 nrv2b.c 　
12585
 UCL_E_INVALID_ARGUMENTUCL_E_INVALID_ARGUMENT 1 nrv2b.c 　
12586
 UCL_E_OUT_OF_MEMORYUCL_E_OUT_OF_MEMORY 2 nrv2b.c 　
12587
 UCL_E_ERRORUCL_E_ERROR 3 nrv2b.c 　
12588
 SWD_HSIZESWD_HSIZE 16384 nrv2b.c 　
12589
 SWD_MAX_CHAINSWD_MAX_CHAIN 2048 nrv2b.c 　
12590
 SWD_BEST_OFFSWD_BEST_OFF 1 nrv2b.c 　
12591
 NIL2NIL2 UINT_MAX nrv2b.c 　
12592
 DEBUGDEBUG 0 zbin.c 　
12593
 BOOTINFO_VERSIONBOOTINFO_VERSION 1 freebsd_loader.c 　
12594
 NODEVNODEV (-1) freebsd_loader.c non-existent device
12595
 PAGE_SHIFTPAGE_SHIFT 12 freebsd_loader.c LOG2(PAGE_SIZE)
12596
 PAGE_SIZEPAGE_SIZE (1<<PAGE_SHIFT) freebsd_loader.c bytes/page
12597
 PAGE_MASKPAGE_MASK (PAGE_SIZE-1) freebsd_loader.c 　
12598
 N_BIOS_GEOMN_BIOS_GEOM 8 freebsd_loader.c 　
12599
 max_alignmax_align ( ( unsigned int ) _max_align ) relocate.c 　
12600
 MAX_ADDRMAX_ADDR (0xfff00000UL) relocate.c 　
12601
 TIMER2_TICKS_PER_SECTIMER2_TICKS_PER_SEC 1193180U timer2.c 　
12602
 PPC_PORTBPPC_PORTB 0x61 timer2.c 　
12603
 PPCB_T2OUTPPCB_T2OUT 0x20 timer2.c Bit 5
12604
 PPCB_SPKRPPCB_SPKR 0x02 timer2.c Bit 1
12605
 PPCB_T2GATEPPCB_T2GATE 0x01 timer2.c Bit 0
12606
 TIMER2_PORTTIMER2_PORT 0x42 timer2.c 　
12607
 TIMER_MODE_PORTTIMER_MODE_PORT 0x43 timer2.c 　
12608
 TIMER0_SELTIMER0_SEL 0x00 timer2.c 　
12609
 TIMER1_SELTIMER1_SEL 0x40 timer2.c 　
12610
 TIMER2_SELTIMER2_SEL 0x80 timer2.c 　
12611
 READBACK_SELREADBACK_SEL 0xC0 timer2.c 　
12612
 LATCH_COUNTLATCH_COUNT 0x00 timer2.c 　
12613
 LOBYTE_ACCESSLOBYTE_ACCESS 0x10 timer2.c 　
12614
 HIBYTE_ACCESSHIBYTE_ACCESS 0x20 timer2.c 　
12615
 WORD_ACCESSWORD_ACCESS 0x30 timer2.c 　
12616
 MODE0MODE0 0x00 timer2.c 　
12617
 MODE1MODE1 0x02 timer2.c 　
12618
 MODE2MODE2 0x04 timer2.c 　
12619
 MODE3MODE3 0x06 timer2.c 　
12620
 MODE4MODE4 0x08 timer2.c 　
12621
 MODE5MODE5 0x0A timer2.c 　
12622
 BINARY_COUNTBINARY_COUNT 0x00 timer2.c 　
12623
 BCD_COUNTBCD_COUNT 0x01 timer2.c 　
12624
 VIDBUFFERVIDBUFFER 0xB8000 video_subr.c 　
12625
 LOAD_DEBUGLOAD_DEBUG 0 wince_loader.c 　
12626
 BOOT_ARG_PTR_LOCATIONBOOT_ARG_PTR_LOCATION 0x001FFFFC wince_loader.c 　
12627
 PSIZEPSIZE (1500) wince_loader.c Max Packet Size
12628
 DSIZEDSIZE (PSIZE+12) wince_loader.c 　
12629
 undi_loaderundi_loader __use_data16 ( undi_loader ) undiload.c 　
12630
 undi_loader_entryundi_loader_entry __use_data16 ( undi_loader_entry ) undiload.c 　
12631
 UNDI_HACK_EB54UNDI_HACK_EB54 0x0001 undinet.c 　
12632
 undiisr_irqundiisr_irq __use_data16 ( undiisr_irq ) undinet.c 　
12633
 undiisr_next_handlerundiisr_next_handler __use_data16 ( undiisr_next_handler ) undinet.c 　
12634
 undiisr_trigger_countundiisr_trigger_count __use_data16 ( undiisr_trigger_count ) undinet.c 　
12635
 undinet_tbdundinet_tbd __use_data16 ( undinet_tbd ) undinet.c 　
12636
 ATTR_BOLDATTR_BOLD 0x08 bios_console.c 　
12637
 ATTR_FCOL_MASKATTR_FCOL_MASK 0x07 bios_console.c 　
12638
 ATTR_FCOL_BLACKATTR_FCOL_BLACK 0x00 bios_console.c 　
12639
 ATTR_FCOL_BLUEATTR_FCOL_BLUE 0x01 bios_console.c 　
12640
 ATTR_FCOL_GREENATTR_FCOL_GREEN 0x02 bios_console.c 　
12641
 ATTR_FCOL_CYANATTR_FCOL_CYAN 0x03 bios_console.c 　
12642
 ATTR_FCOL_REDATTR_FCOL_RED 0x04 bios_console.c 　
12643
 ATTR_FCOL_MAGENTAATTR_FCOL_MAGENTA 0x05 bios_console.c 　
12644
 ATTR_FCOL_YELLOWATTR_FCOL_YELLOW 0x06 bios_console.c 　
12645
 ATTR_FCOL_WHITEATTR_FCOL_WHITE 0x07 bios_console.c 　
12646
 ATTR_BCOL_MASKATTR_BCOL_MASK 0x70 bios_console.c 　
12647
 ATTR_BCOL_BLACKATTR_BCOL_BLACK 0x00 bios_console.c 　
12648
 ATTR_BCOL_BLUEATTR_BCOL_BLUE 0x10 bios_console.c 　
12649
 ATTR_BCOL_GREENATTR_BCOL_GREEN 0x20 bios_console.c 　
12650
 ATTR_BCOL_CYANATTR_BCOL_CYAN 0x30 bios_console.c 　
12651
 ATTR_BCOL_REDATTR_BCOL_RED 0x40 bios_console.c 　
12652
 ATTR_BCOL_MAGENTAATTR_BCOL_MAGENTA 0x50 bios_console.c 　
12653
 ATTR_BCOL_YELLOWATTR_BCOL_YELLOW 0x60 bios_console.c 　
12654
 ATTR_BCOL_WHITEATTR_BCOL_WHITE 0x70 bios_console.c 　
12655
 ATTR_DEFAULTATTR_DEFAULT ATTR_FCOL_WHITE bios_console.c 　
12656
 BIOS_KEY_MINBIOS_KEY_MIN 0x42 bios_console.c 　
12657
 real_int15_vectorreal_int15_vector __use_text16 ( real_int15_vector ) fakee820.c 　
12658
 E820_TYPE_RAME820_TYPE_RAM 1 fakee820.c *< Normal memory
12659
 E820_TYPE_RSVDE820_TYPE_RSVD 2 fakee820.c *< Reserved and unavailable
12660
 E820_TYPE_ACPIE820_TYPE_ACPI 3 fakee820.c *< ACPI reclaim memory
12661
 E820_TYPE_NVSE820_TYPE_NVS 4 fakee820.c *< ACPI NVS memory
12662
 e820mape820map __use_text16 ( e820map ) fakee820.c 　
12663
 K_RDWRK_RDWR 0x60 gateA20.c keyboard data & cmds (read/write)
12664
 K_STATUSK_STATUS 0x64 gateA20.c keyboard status
12665
 K_CMDK_CMD 0x64 gateA20.c keybd ctlr command (write-only)
12666
 K_OBUF_FULK_OBUF_FUL 0x01 gateA20.c output buffer full
12667
 K_IBUF_FULK_IBUF_FUL 0x02 gateA20.c input buffer full
12668
 KC_CMD_WINKC_CMD_WIN 0xd0 gateA20.c read output port
12669
 KC_CMD_WOUTKC_CMD_WOUT 0xd1 gateA20.c write output port
12670
 KC_CMD_NULLKC_CMD_NULL 0xff gateA20.c null command ("pulse nothing")
12671
 KB_SET_A20KB_SET_A20 0xdf gateA20.c enable A20,
12672
 KB_UNSET_A20KB_UNSET_A20 0xdd gateA20.c enable A20,
12673
 SCP_ASCP_A 0x92 gateA20.c System Control Port A
12674
 A20_MAX_RETRIESA20_MAX_RETRIES 32 gateA20.c 　
12675
 A20_INT15_RETRIESA20_INT15_RETRIES 32 gateA20.c 　
12676
 A20_KBC_RETRIESA20_KBC_RETRIES (2^21) gateA20.c 　
12677
 A20_SCPA_RETRIESA20_SCPA_RETRIES (2^21) gateA20.c 　
12678
 FAKE_E820FAKE_E820 0 hidemem.c 　
12679
 ALIGN_HIDDENALIGN_HIDDEN 4096 hidemem.c 4kB page alignment should be enough
12680
 hidemem_basehidemem_base __use_data16 ( hidemem_base ) hidemem.c 　
12681
 hidemem_umallochidemem_umalloc __use_data16 ( hidemem_umalloc ) hidemem.c 　
12682
 hidemem_textdatahidemem_textdata __use_data16 ( hidemem_textdata ) hidemem.c 　
12683
 int15_vectorint15_vector __use_text16 ( int15_vector ) hidemem.c 　
12684
 _text16_memsz_text16_memsz ( ( unsigned int ) _text16_memsz ) hidemem.c 　
12685
 _data16_memsz_data16_memsz ( ( unsigned int ) _data16_memsz ) hidemem.c 　
12686
 SMAPSMAP ( 0x534d4150 ) memmap.c 　
12687
 E820_TYPE_RAME820_TYPE_RAM 1 memmap.c *< Normal memory
12688
 E820_TYPE_RESERVEDE820_TYPE_RESERVED 2 memmap.c *< Reserved and unavailable
12689
 E820_TYPE_ACPIE820_TYPE_ACPI 3 memmap.c *< ACPI reclaim memory
12690
 E820_TYPE_NVSE820_TYPE_NVS 4 memmap.c *< ACPI NVS memory
12691
 E820_ATTR_ENABLEDE820_ATTR_ENABLED 0x00000001UL memmap.c 　
12692
 E820_ATTR_NONVOLATILEE820_ATTR_NONVOLATILE 0x00000002UL memmap.c 　
12693
 E820_ATTR_UNKNOWNE820_ATTR_UNKNOWN 0xfffffffcUL memmap.c 　
12694
 E820_MIN_SIZEE820_MIN_SIZE 20 memmap.c 　
12695
 e820bufe820buf __use_data16 ( e820buf ) memmap.c 　
12696
 PNP_BIOS_SIGNATUREPNP_BIOS_SIGNATURE ( ( '$' << 0 ) + ( 'P' << 8 ) + ( 'n' << 16 ) + ( 'P' << 24 ) ) pnpbios.c 　
12697
 COMBOOT_PSP_CMDLINE_OFFSETCOMBOOT_PSP_CMDLINE_OFFSET 0x81 comboot.c 　
12698
 COMBOOT_MAX_CMDLINE_LENCOMBOOT_MAX_CMDLINE_LEN 125 comboot.c 　
12699
 ISO9660_BLKSIZEISO9660_BLKSIZE 2048 eltorito.c 　
12700
 ELTORITO_VOL_DESC_OFFSETELTORITO_VOL_DESC_OFFSET ( 17 * ISO9660_BLKSIZE ) eltorito.c 　
12701
 ELTORITO_BOOTABLEELTORITO_BOOTABLE 0x88 eltorito.c 　
12702
 MAX_MODULESMAX_MODULES 8 multiboot.c 　
12703
 MB_MAX_CMDLINEMB_MAX_CMDLINE 512 multiboot.c 　
12704
 MB_SUPPORTED_FLAGSMB_SUPPORTED_FLAGS ( MB_FLAG_PGALIGN | MB_FLAG_MEMMAP | \ MB_FLAG_VIDMODE | MB_FLAG_RAW ) multiboot.c 　
12705
 MB_COMPULSORY_FLAGSMB_COMPULSORY_FLAGS 0x0000ffff multiboot.c 　
12706
 MB_OPTIONAL_FLAGSMB_OPTIONAL_FLAGS 0xffff0000 multiboot.c 　
12707
 MB_UNSUPPORTED_FLAGSMB_UNSUPPORTED_FLAGS ( MB_COMPULSORY_FLAGS & ~MB_SUPPORTED_FLAGS ) multiboot.c 　
12708
 mb_cmdlinesmb_cmdlines __use_data16 ( mb_cmdlines ) multiboot.c 　
12709
 mbinfombinfo __use_data16 ( mbinfo ) multiboot.c 　
12710
 mb_bootloader_namemb_bootloader_name __use_data16 ( mb_bootloader_name ) multiboot.c 　
12711
 mbmemmapmbmemmap __use_data16 ( mbmemmap ) multiboot.c 　
12712
 mbmodulesmbmodules __use_data16 ( mbmodules ) multiboot.c 　
12713
 NBI_MAGICNBI_MAGIC 0x1B031336UL nbi.c 　
12714
 NBI_HEADER_LENGTHNBI_HEADER_LENGTH 512 nbi.c 　
12715
 NBI_LOADADDR_ABSNBI_LOADADDR_ABS 0x00 nbi.c 　
12716
 NBI_LOADADDR_AFTERNBI_LOADADDR_AFTER 0x01 nbi.c 　
12717
 NBI_LOADADDR_ENDNBI_LOADADDR_END 0x02 nbi.c 　
12718
 NBI_LOADADDR_BEFORENBI_LOADADDR_BEFORE 0x03 nbi.c 　
12719
 BASEMEM_PACKET_LENBASEMEM_PACKET_LEN 1514 basemem_packet.h 　
12720
 basemem_packetbasemem_packet __use_data16 ( basemem_packet ) basemem_packet.h 　
12721
 BDA_SEGBDA_SEG 0x0040 bios.h 　
12722
 BDA_FBMSBDA_FBMS 0x0013 bios.h 　
12723
 BDA_NUM_DRIVESBDA_NUM_DRIVES 0x0075 bios.h 　
12724
 hooked_bios_interruptshooked_bios_interrupts __use_text16 ( hooked_bios_interrupts ) biosint.h 　
12725
 BIOS_DISK_MAX_NAME_LENBIOS_DISK_MAX_NAME_LEN 6 bios_disks.h 　
12726
 bochsbpbochsbp xchgw %bx, %bx bochs.h 　
12727
 BOCHSBPBOCHSBP bochsbp bochs.h 　
12728
 BZI_HDR_OFFSETBZI_HDR_OFFSET 0x1f1 bzimage.h 　
12729
 BZI_BOOT_FLAGBZI_BOOT_FLAG 0xaa55 bzimage.h 　
12730
 BZI_SIGNATUREBZI_SIGNATURE 0x53726448 bzimage.h 　
12731
 BZI_LOADER_TYPE_ETHERBOOTBZI_LOADER_TYPE_ETHERBOOT 0x40 bzimage.h 　
12732
 BZI_LOADER_TYPE_GPXEBZI_LOADER_TYPE_GPXE ( BZI_LOADER_TYPE_ETHERBOOT | 0x06 ) bzimage.h 　
12733
 BZI_LOAD_HIGHBZI_LOAD_HIGH 0x01 bzimage.h 　
12734
 BZI_LOAD_HIGH_ADDRBZI_LOAD_HIGH_ADDR 0x100000 bzimage.h 　
12735
 BZI_LOAD_LOW_ADDRBZI_LOAD_LOW_ADDR 0x10000 bzimage.h 　
12736
 BZI_CAN_USE_HEAPBZI_CAN_USE_HEAP 0x80 bzimage.h 　
12737
 BZI_VID_MODE_NORMALBZI_VID_MODE_NORMAL 0xffff bzimage.h 　
12738
 BZI_VID_MODE_EXTBZI_VID_MODE_EXT 0xfffe bzimage.h 　
12739
 BZI_VID_MODE_ASKBZI_VID_MODE_ASK 0xfffd bzimage.h 　
12740
 BZI_INITRD_MAXBZI_INITRD_MAX 0x37ffffff bzimage.h 　
12741
 BZI_CMDLINE_OFFSETBZI_CMDLINE_OFFSET 0x20 bzimage.h 　
12742
 BZI_CMDLINE_MAGICBZI_CMDLINE_MAGIC 0xa33f bzimage.h 　
12743
 BZI_ASSUMED_RM_SIZEBZI_ASSUMED_RM_SIZE 0x8000 bzimage.h 　
12744
 BZI_STACK_SIZEBZI_STACK_SIZE 0x1000 bzimage.h 　
12745
 BZI_CMDLINE_SIZEBZI_CMDLINE_SIZE 0x100 bzimage.h 　
12746
 COMBOOT_PSP_SEGCOMBOOT_PSP_SEG 0x07C0 comboot.h 　
12747
 COM32_START_PHYSCOM32_START_PHYS 0x101000 comboot.h 　
12748
 COM32_BOUNCE_SEGCOM32_BOUNCE_SEG 0x07C0 comboot.h 　
12749
 COMBOOT_FILE_BLOCKSZCOMBOOT_FILE_BLOCKSZ 512 comboot.h 　
12750
 COMBOOT_FEATURE_LOCAL_BOOTCOMBOOT_FEATURE_LOCAL_BOOT (1 << 0) comboot.h 　
12751
 COMBOOT_FEATURE_IDLE_LOOPCOMBOOT_FEATURE_IDLE_LOOP (1 << 1) comboot.h 　
12752
 COMBOOT_MAX_SHUFFLE_DESCRIPTORSCOMBOOT_MAX_SHUFFLE_DESCRIPTORS 682 comboot.h 　
12753
 COMBOOT_EXITCOMBOOT_EXIT 1 comboot.h 　
12754
 COMBOOT_EXIT_RUN_KERNELCOMBOOT_EXIT_RUN_KERNEL 2 comboot.h 　
12755
 COMBOOT_EXIT_COMMANDCOMBOOT_EXIT_COMMAND 3 comboot.h 　
12756
 COMBOOT_VIDEO_GRAPHICSCOMBOOT_VIDEO_GRAPHICS 0x01 comboot.h 　
12757
 COMBOOT_VIDEO_NONSTANDARDCOMBOOT_VIDEO_NONSTANDARD 0x02 comboot.h 　
12758
 COMBOOT_VIDEO_VESACOMBOOT_VIDEO_VESA 0x04 comboot.h 　
12759
 COMBOOT_VIDEO_NOTEXTCOMBOOT_VIDEO_NOTEXT 0x08 comboot.h 　
12760
 INT13_RESETINT13_RESET 0x00 int13.h 　
12761
 INT13_GET_LAST_STATUSINT13_GET_LAST_STATUS 0x01 int13.h 　
12762
 INT13_READ_SECTORSINT13_READ_SECTORS 0x02 int13.h 　
12763
 INT13_WRITE_SECTORSINT13_WRITE_SECTORS 0x03 int13.h 　
12764
 INT13_GET_PARAMETERSINT13_GET_PARAMETERS 0x08 int13.h 　
12765
 INT13_GET_DISK_TYPEINT13_GET_DISK_TYPE 0x15 int13.h 　
12766
 INT13_EXTENSION_CHECKINT13_EXTENSION_CHECK 0x41 int13.h 　
12767
 INT13_EXTENDED_READINT13_EXTENDED_READ 0x42 int13.h 　
12768
 INT13_EXTENDED_WRITEINT13_EXTENDED_WRITE 0x43 int13.h 　
12769
 INT13_GET_EXTENDED_PARAMETERSINT13_GET_EXTENDED_PARAMETERS 0x48 int13.h 　
12770
 INT13_CDROM_STATUS_TERMINATEINT13_CDROM_STATUS_TERMINATE 0x4b int13.h 　
12771
 INT13_STATUS_SUCCESSINT13_STATUS_SUCCESS 0x00 int13.h 　
12772
 INT13_STATUS_INVALIDINT13_STATUS_INVALID 0x01 int13.h 　
12773
 INT13_STATUS_READ_ERRORINT13_STATUS_READ_ERROR 0x04 int13.h 　
12774
 INT13_STATUS_WRITE_ERRORINT13_STATUS_WRITE_ERROR 0xcc int13.h 　
12775
 INT13_BLKSIZEINT13_BLKSIZE 512 int13.h 　
12776
 INT13_DISK_TYPE_NONEINT13_DISK_TYPE_NONE 0x00 int13.h 　
12777
 INT13_DISK_TYPE_FDDINT13_DISK_TYPE_FDD 0x01 int13.h 　
12778
 INT13_DISK_TYPE_FDD_CLINT13_DISK_TYPE_FDD_CL 0x02 int13.h 　
12779
 INT13_DISK_TYPE_HDDINT13_DISK_TYPE_HDD 0x03 int13.h 　
12780
 INT13_FL_DMA_TRANSPARENTINT13_FL_DMA_TRANSPARENT 0x01 int13.h 　
12781
 INT13_FL_CHS_VALIDINT13_FL_CHS_VALID 0x02 int13.h 　
12782
 INT13_FL_REMOVABLEINT13_FL_REMOVABLE 0x04 int13.h 　
12783
 INT13_FL_VERIFIABLEINT13_FL_VERIFIABLE 0x08 int13.h 　
12784
 INT13_FL_CHANGE_LINEINT13_FL_CHANGE_LINE 0x10 int13.h 　
12785
 INT13_FL_LOCKABLEINT13_FL_LOCKABLE 0x20 int13.h 　
12786
 INT13_FL_CHS_MAXINT13_FL_CHS_MAX 0x40 int13.h 　
12787
 INT13_EXTENSION_LINEARINT13_EXTENSION_LINEAR 0x01 int13.h 　
12788
 INT13_EXTENSION_REMOVABLEINT13_EXTENSION_REMOVABLE 0x02 int13.h 　
12789
 INT13_EXTENSION_EDDINT13_EXTENSION_EDD 0x04 int13.h 　
12790
 INT13_EXTENSION_VER_1_XINT13_EXTENSION_VER_1_X 0x01 int13.h 　
12791
 INT13_EXTENSION_VER_2_0INT13_EXTENSION_VER_2_0 0x20 int13.h 　
12792
 INT13_EXTENSION_VER_2_1INT13_EXTENSION_VER_2_1 0x21 int13.h 　
12793
 INT13_EXTENSION_VER_3_0INT13_EXTENSION_VER_3_0 0x30 int13.h 　
12794
 code32code32 code16gcc kir.h 　
12795
 rm_csrm_cs ( _rm_cs() ) libkir.h 　
12796
 rm_dsrm_ds ( _rm_ds() ) libkir.h 　
12797
 copy_to_realcopy_to_real copy_to_real_libkir libkir.h 　
12798
 copy_from_realcopy_from_real copy_from_real_libkir libkir.h 　
12799
 put_realput_real put_real_kir libkir.h 　
12800
 get_realget_real get_real_kir libkir.h 　
12801
 VIRTUAL_CSVIRTUAL_CS 0x08 librm.h 　
12802
 VIRTUAL_DSVIRTUAL_DS 0x10 librm.h 　
12803
 PHYSICAL_CSPHYSICAL_CS 0x18 librm.h 　
12804
 PHYSICAL_DSPHYSICAL_DS 0x20 librm.h 　
12805
 REAL_CSREAL_CS 0x28 librm.h 　
12806
 REAL_DSREAL_DS 0x30 librm.h 　
12807
 LONG_CSLONG_CS 0x38 librm.h 　
12808
 LONG_DSLONG_DS 0x40 librm.h 　
12809
 UACCESS_PREFIX_librmUACCESS_PREFIX_librm __librm_ librm.h 　
12810
 rm_csrm_cs __use_data16 ( rm_cs ) librm.h 　
12811
 rm_dsrm_ds __use_text16 ( rm_ds ) librm.h 　
12812
 LIMITS_HLIMITS_H 1 limits.h 　
12813
 CHAR_BITCHAR_BIT 8 limits.h 　
12814
 SCHAR_MINSCHAR_MIN (-128) limits.h 　
12815
 SCHAR_MAXSCHAR_MAX 127 limits.h 　
12816
 UCHAR_MAXUCHAR_MAX 255 limits.h 　
12817
 CHAR_MINCHAR_MIN SCHAR_MIN limits.h 　
12818
 CHAR_MAXCHAR_MAX SCHAR_MAX limits.h 　
12819
 SHRT_MINSHRT_MIN (-32768) limits.h 　
12820
 SHRT_MAXSHRT_MAX 32767 limits.h 　
12821
 USHRT_MAXUSHRT_MAX 65535 limits.h 　
12822
 INT_MININT_MIN (-INT_MAX - 1) limits.h 　
12823
 INT_MAXINT_MAX 2147483647 limits.h 　
12824
 UINT_MAXUINT_MAX 4294967295U limits.h 　
12825
 INT_MAXINT_MAX 2147483647 limits.h 　
12826
 INT_MININT_MIN (-INT_MAX - 1) limits.h 　
12827
 UINT_MAXUINT_MAX 4294967295U limits.h 　
12828
 LONG_MAXLONG_MAX 2147483647 limits.h 　
12829
 LONG_MINLONG_MIN (-LONG_MAX - 1L) limits.h 　
12830
 ULONG_MAXULONG_MAX 4294967295UL limits.h 　
12831
 LLONG_MAXLLONG_MAX 9223372036854775807LL limits.h 　
12832
 LLONG_MINLLONG_MIN (-LONG_MAX - 1LL) limits.h 　
12833
 ULLONG_MAXULLONG_MAX 18446744073709551615ULL limits.h 　
12834
 MULTIBOOT_HEADER_MAGICMULTIBOOT_HEADER_MAGIC 0x1BADB002 multiboot.h 　
12835
 MB_FLAG_PGALIGNMB_FLAG_PGALIGN 0x00000001 multiboot.h 　
12836
 MB_FLAG_MEMMAPMB_FLAG_MEMMAP 0x00000002 multiboot.h 　
12837
 MB_FLAG_VIDMODEMB_FLAG_VIDMODE 0x00000004 multiboot.h 　
12838
 MB_FLAG_RAWMB_FLAG_RAW 0x00010000 multiboot.h 　
12839
 MULTIBOOT_BOOTLOADER_MAGICMULTIBOOT_BOOTLOADER_MAGIC 0x2BADB002 multiboot.h 　
12840
 MBI_FLAG_MEMMBI_FLAG_MEM 0x00000001 multiboot.h 　
12841
 MBI_FLAG_BOOTDEVMBI_FLAG_BOOTDEV 0x00000002 multiboot.h 　
12842
 MBI_FLAG_CMDLINEMBI_FLAG_CMDLINE 0x00000004 multiboot.h 　
12843
 MBI_FLAG_MODSMBI_FLAG_MODS 0x00000008 multiboot.h 　
12844
 MBI_FLAG_AOUTMBI_FLAG_AOUT 0x00000010 multiboot.h 　
12845
 MBI_FLAG_ELFMBI_FLAG_ELF 0x00000020 multiboot.h 　
12846
 MBI_FLAG_MMAPMBI_FLAG_MMAP 0x00000040 multiboot.h 　
12847
 MBI_FLAG_DRIVESMBI_FLAG_DRIVES 0x00000080 multiboot.h 　
12848
 MBI_FLAG_CFGTBLMBI_FLAG_CFGTBL 0x00000100 multiboot.h 　
12849
 MBI_FLAG_LOADERMBI_FLAG_LOADER 0x00000200 multiboot.h 　
12850
 MBI_FLAG_APMMBI_FLAG_APM 0x00000400 multiboot.h 　
12851
 MBI_FLAG_VBEMBI_FLAG_VBE 0x00000800 multiboot.h 　
12852
 MBMEM_RAMMBMEM_RAM 1 multiboot.h 　
12853
 IRQ_PIC_CUTOFFIRQ_PIC_CUTOFF 8 pic8259.h 　
12854
 PIC1_ICW1PIC1_ICW1 0x20 pic8259.h 　
12855
 PIC1_OCW2PIC1_OCW2 0x20 pic8259.h 　
12856
 PIC1_OCW3PIC1_OCW3 0x20 pic8259.h 　
12857
 PIC1_ICRPIC1_ICR 0x20 pic8259.h 　
12858
 PIC1_IRRPIC1_IRR 0x20 pic8259.h 　
12859
 PIC1_ISRPIC1_ISR 0x20 pic8259.h 　
12860
 PIC1_ICW2PIC1_ICW2 0x21 pic8259.h 　
12861
 PIC1_ICW3PIC1_ICW3 0x21 pic8259.h 　
12862
 PIC1_ICW4PIC1_ICW4 0x21 pic8259.h 　
12863
 PIC1_IMRPIC1_IMR 0x21 pic8259.h 　
12864
 PIC2_ICW1PIC2_ICW1 0xa0 pic8259.h 　
12865
 PIC2_OCW2PIC2_OCW2 0xa0 pic8259.h 　
12866
 PIC2_OCW3PIC2_OCW3 0xa0 pic8259.h 　
12867
 PIC2_ICRPIC2_ICR 0xa0 pic8259.h 　
12868
 PIC2_IRRPIC2_IRR 0xa0 pic8259.h 　
12869
 PIC2_ISRPIC2_ISR 0xa0 pic8259.h 　
12870
 PIC2_ICW2PIC2_ICW2 0xa1 pic8259.h 　
12871
 PIC2_ICW3PIC2_ICW3 0xa1 pic8259.h 　
12872
 PIC2_ICW4PIC2_ICW4 0xa1 pic8259.h 　
12873
 PIC2_IMRPIC2_IMR 0xa1 pic8259.h 　
12874
 OCW3_IDOCW3_ID 0x08 pic8259.h 　
12875
 OCW3_READ_IRROCW3_READ_IRR 0x03 pic8259.h 　
12876
 OCW3_READ_ISROCW3_READ_ISR 0x02 pic8259.h 　
12877
 ICR_EOI_NON_SPECIFICICR_EOI_NON_SPECIFIC 0x20 pic8259.h 　
12878
 ICR_EOI_NOPICR_EOI_NOP 0x40 pic8259.h 　
12879
 ICR_EOI_SPECIFICICR_EOI_SPECIFIC 0x60 pic8259.h 　
12880
 ICR_EOI_SET_PRIORITYICR_EOI_SET_PRIORITY 0xc0 pic8259.h 　
12881
 CHAINED_IRQCHAINED_IRQ 2 pic8259.h 　
12882
 IRQ_MAXIRQ_MAX 15 pic8259.h 　
12883
 IRQ_NONEIRQ_NONE -1U pic8259.h 　
12884
 BIOS_SEGBIOS_SEG 0xf000 pnpbios.h 　
12885
 ROM_SIGNATUREROM_SIGNATURE 0xaa55 pxe.h 　
12886
 UNDI_ROM_ID_SIGNATUREUNDI_ROM_ID_SIGNATURE ( ( 'U' << 0 ) + ( 'N' << 8 ) + ( 'D' << 16 ) + ( 'I' << 24 ) ) pxe.h 　
12887
 PCIR_SIGNATUREPCIR_SIGNATURE ( ( 'P' << 0 ) + ( 'C' << 8 ) + ( 'I' << 16 ) + ( 'R' << 24 ) ) pxe.h 　
12888
 PXENV_UNLOAD_STACKPXENV_UNLOAD_STACK 0x0070 pxe_api.h 　
12889
 PXENV_GET_CACHED_INFOPXENV_GET_CACHED_INFO 0x0071 pxe_api.h 　
12890
 PXENV_PACKET_TYPE_DHCP_DISCOVERPXENV_PACKET_TYPE_DHCP_DISCOVER 1 pxe_api.h 　
12891
 PXENV_PACKET_TYPE_DHCP_ACKPXENV_PACKET_TYPE_DHCP_ACK 2 pxe_api.h 　
12892
 PXENV_PACKET_TYPE_CACHED_REPLYPXENV_PACKET_TYPE_CACHED_REPLY 3 pxe_api.h 　
12893
 BOOTP_REQBOOTP_REQ 1 pxe_api.h *< A BOOTP request packet
12894
 BOOTP_REPBOOTP_REP 2 pxe_api.h *< A BOOTP reply packet
12895
 BOOTP_BCASTBOOTP_BCAST 0x8000 pxe_api.h 　
12896
 VM_RFC1048VM_RFC1048 0x63825363L pxe_api.h *< DHCP magic cookie
12897
 BOOTP_DHCPVENDBOOTP_DHCPVEND 1024 pxe_api.h 　
12898
 PXENV_RESTART_TFTPPXENV_RESTART_TFTP 0x0073 pxe_api.h 　
12899
 PXENV_START_UNDIPXENV_START_UNDI 0x0000 pxe_api.h 　
12900
 PXENV_STOP_UNDIPXENV_STOP_UNDI 0x0015 pxe_api.h 　
12901
 PXENV_START_BASEPXENV_START_BASE 0x0075 pxe_api.h 　
12902
 PXENV_STOP_BASEPXENV_STOP_BASE 0x0076 pxe_api.h 　
12903
 PXENV_TFTP_OPENPXENV_TFTP_OPEN 0x0020 pxe_api.h 　
12904
 PXENV_TFTP_CLOSEPXENV_TFTP_CLOSE 0x0021 pxe_api.h 　
12905
 PXENV_TFTP_READPXENV_TFTP_READ 0x0022 pxe_api.h 　
12906
 PXENV_TFTP_READ_FILEPXENV_TFTP_READ_FILE 0x0023 pxe_api.h 　
12907
 PXENV_TFTP_GET_FSIZEPXENV_TFTP_GET_FSIZE 0x0025 pxe_api.h 　
12908
 PXENV_UDP_OPENPXENV_UDP_OPEN 0x0030 pxe_api.h 　
12909
 PXENV_UDP_CLOSEPXENV_UDP_CLOSE 0x0031 pxe_api.h 　
12910
 PXENV_UDP_WRITEPXENV_UDP_WRITE 0x0033 pxe_api.h 　
12911
 PXENV_UDP_READPXENV_UDP_READ 0x0032 pxe_api.h 　
12912
 PXENV_UNDI_STARTUPPXENV_UNDI_STARTUP 0x0001 pxe_api.h 　
12913
 PXENV_BUS_ISAPXENV_BUS_ISA 0 pxe_api.h *< ISA bus type
12914
 PXENV_BUS_EISAPXENV_BUS_EISA 1 pxe_api.h *< EISA bus type
12915
 PXENV_BUS_MCAPXENV_BUS_MCA 2 pxe_api.h *< MCA bus type
12916
 PXENV_BUS_PCIPXENV_BUS_PCI 3 pxe_api.h *< PCI bus type
12917
 PXENV_BUS_VESAPXENV_BUS_VESA 4 pxe_api.h *< VESA bus type
12918
 PXENV_BUS_PCMCIAPXENV_BUS_PCMCIA 5 pxe_api.h *< PCMCIA bus type
12919
 PXENV_UNDI_CLEANUPPXENV_UNDI_CLEANUP 0x0002 pxe_api.h 　
12920
 PXENV_UNDI_INITIALIZEPXENV_UNDI_INITIALIZE 0x0003 pxe_api.h 　
12921
 PXENV_UNDI_RESET_ADAPTERPXENV_UNDI_RESET_ADAPTER 0x0004 pxe_api.h 　
12922
 MAXNUM_MCADDRMAXNUM_MCADDR 8 pxe_api.h 　
12923
 PXENV_UNDI_SHUTDOWNPXENV_UNDI_SHUTDOWN 0x0005 pxe_api.h 　
12924
 PXENV_UNDI_OPENPXENV_UNDI_OPEN 0x0006 pxe_api.h 　
12925
 FLTR_DIRECTEDFLTR_DIRECTED 0x0001 pxe_api.h 　
12926
 FLTR_BRDCSTFLTR_BRDCST 0x0002 pxe_api.h 　
12927
 FLTR_PRMSCSFLTR_PRMSCS 0x0004 pxe_api.h 　
12928
 FLTR_SRC_RTGFLTR_SRC_RTG 0x0008 pxe_api.h 　
12929
 PXENV_UNDI_CLOSEPXENV_UNDI_CLOSE 0x0007 pxe_api.h 　
12930
 PXENV_UNDI_TRANSMITPXENV_UNDI_TRANSMIT 0x0008 pxe_api.h 　
12931
 P_UNKNOWNP_UNKNOWN 0 pxe_api.h *< Media header already filled in
12932
 P_IPP_IP 1 pxe_api.h *< IP protocol
12933
 P_ARPP_ARP 2 pxe_api.h *< ARP protocol
12934
 P_RARPP_RARP 3 pxe_api.h *< RARP protocol
12935
 P_OTHERP_OTHER 4 pxe_api.h *< Other protocol
12936
 XMT_DESTADDRXMT_DESTADDR 0x0000 pxe_api.h *< Unicast packet
12937
 XMT_BROADCASTXMT_BROADCAST 0x0001 pxe_api.h *< Broadcast packet
12938
 MAX_DATA_BLKSMAX_DATA_BLKS 8 pxe_api.h 　
12939
 PXENV_UNDI_SET_MCAST_ADDRESSPXENV_UNDI_SET_MCAST_ADDRESS 0x0009 pxe_api.h 　
12940
 PXENV_UNDI_SET_STATION_ADDRESSPXENV_UNDI_SET_STATION_ADDRESS 0x000a pxe_api.h 　
12941
 PXENV_UNDI_SET_PACKET_FILTERPXENV_UNDI_SET_PACKET_FILTER 0x000b pxe_api.h 　
12942
 PXENV_UNDI_GET_INFORMATIONPXENV_UNDI_GET_INFORMATION 0x000c pxe_api.h 　
12943
 ETHER_TYPEETHER_TYPE 1 pxe_api.h *< Ethernet (10Mb)
12944
 EXP_ETHER_TYPEEXP_ETHER_TYPE 2 pxe_api.h *< Experimental Ethernet (3Mb)
12945
 AX25_TYPEAX25_TYPE 3 pxe_api.h *< Amateur Radio AX.25
12946
 TOKEN_RING_TYPETOKEN_RING_TYPE 4 pxe_api.h *< Proteon ProNET Token Ring
12947
 CHAOS_TYPECHAOS_TYPE 5 pxe_api.h *< Chaos
12948
 IEEE_TYPEIEEE_TYPE 6 pxe_api.h *< IEEE 802 Networks
12949
 ARCNET_TYPEARCNET_TYPE 7 pxe_api.h *< ARCNET
12950
 PXENV_UNDI_GET_STATISTICSPXENV_UNDI_GET_STATISTICS 0x000d pxe_api.h 　
12951
 PXENV_UNDI_CLEAR_STATISTICSPXENV_UNDI_CLEAR_STATISTICS 0x000e pxe_api.h 　
12952
 PXENV_UNDI_INITIATE_DIAGSPXENV_UNDI_INITIATE_DIAGS 0x000f pxe_api.h 　
12953
 PXENV_UNDI_FORCE_INTERRUPTPXENV_UNDI_FORCE_INTERRUPT 0x0010 pxe_api.h 　
12954
 PXENV_UNDI_GET_MCAST_ADDRESSPXENV_UNDI_GET_MCAST_ADDRESS 0x0011 pxe_api.h 　
12955
 PXENV_UNDI_GET_NIC_TYPEPXENV_UNDI_GET_NIC_TYPE 0x0012 pxe_api.h 　
12956
 PCI_NICPCI_NIC 2 pxe_api.h *< PCI network card
12957
 PnP_NICPnP_NIC 3 pxe_api.h *< ISAPnP network card
12958
 CardBus_NICCardBus_NIC 4 pxe_api.h *< CardBus network card
12959
 PXENV_UNDI_GET_IFACE_INFOPXENV_UNDI_GET_IFACE_INFO 0x0013 pxe_api.h 　
12960
 SUPPORTED_BROADCASTSUPPORTED_BROADCAST 0x0001 pxe_api.h 　
12961
 SUPPORTED_MULTICASTSUPPORTED_MULTICAST 0x0002 pxe_api.h 　
12962
 SUPPORTED_GROUPSUPPORTED_GROUP 0x0004 pxe_api.h 　
12963
 SUPPORTED_PROMISCUOUSSUPPORTED_PROMISCUOUS 0x0008 pxe_api.h 　
12964
 SUPPORTED_SET_STATION_ADDRESSSUPPORTED_SET_STATION_ADDRESS 0x0010 pxe_api.h 　
12965
 SUPPORTED_DIAGNOSTICSSUPPORTED_DIAGNOSTICS 0x0040 pxe_api.h 　
12966
 SUPPORTED_RESETSUPPORTED_RESET 0x0400 pxe_api.h 　
12967
 SUPPORTED_OPEN_CLOSESUPPORTED_OPEN_CLOSE 0x0800 pxe_api.h 　
12968
 SUPPORTED_IRQSUPPORTED_IRQ 0x1000 pxe_api.h 　
12969
 PXENV_UNDI_GET_STATEPXENV_UNDI_GET_STATE 0x0015 pxe_api.h 　
12970
 PXE_UNDI_GET_STATE_STARTEDPXE_UNDI_GET_STATE_STARTED 1 pxe_api.h 　
12971
 PXE_UNDI_GET_STATE_INITIALIZEDPXE_UNDI_GET_STATE_INITIALIZED 2 pxe_api.h 　
12972
 PXE_UNDI_GET_STATE_OPENEDPXE_UNDI_GET_STATE_OPENED 3 pxe_api.h 　
12973
 PXENV_UNDI_ISRPXENV_UNDI_ISR 0x0014 pxe_api.h 　
12974
 PXENV_UNDI_ISR_IN_STARTPXENV_UNDI_ISR_IN_START 1 pxe_api.h 　
12975
 PXENV_UNDI_ISR_IN_PROCESSPXENV_UNDI_ISR_IN_PROCESS 2 pxe_api.h 　
12976
 PXENV_UNDI_ISR_IN_GET_NEXTPXENV_UNDI_ISR_IN_GET_NEXT 3 pxe_api.h 　
12977
 PXENV_UNDI_ISR_OUT_OURSPXENV_UNDI_ISR_OUT_OURS 0 pxe_api.h 　
12978
 PXENV_UNDI_ISR_OUT_NOT_OURSPXENV_UNDI_ISR_OUT_NOT_OURS 1 pxe_api.h 　
12979
 PXENV_UNDI_ISR_OUT_DONEPXENV_UNDI_ISR_OUT_DONE 0 pxe_api.h 　
12980
 PXENV_UNDI_ISR_OUT_TRANSMITPXENV_UNDI_ISR_OUT_TRANSMIT 2 pxe_api.h 　
12981
 PXENV_UNDI_ISR_OUT_RECEIVEPXENV_UNDI_ISR_OUT_RECEIVE 3 pxe_api.h 　
12982
 PXENV_UNDI_ISR_OUT_BUSYPXENV_UNDI_ISR_OUT_BUSY 4 pxe_api.h 　
12983
 P_DIRECTEDP_DIRECTED 0 pxe_api.h 　
12984
 P_BROADCASTP_BROADCAST 1 pxe_api.h 　
12985
 P_MULTICASTP_MULTICAST 2 pxe_api.h 　
12986
 PXENV_FILE_OPENPXENV_FILE_OPEN 0x00e0 pxe_api.h 　
12987
 PXENV_FILE_CLOSEPXENV_FILE_CLOSE 0x00e1 pxe_api.h 　
12988
 PXENV_FILE_SELECTPXENV_FILE_SELECT 0x00e2 pxe_api.h 　
12989
 RDY_READRDY_READ 0x0001 pxe_api.h 　
12990
 PXENV_FILE_READPXENV_FILE_READ 0x00e3 pxe_api.h 　
12991
 PXENV_GET_FILE_SIZEPXENV_GET_FILE_SIZE 0x00e4 pxe_api.h 　
12992
 PXENV_FILE_EXECPXENV_FILE_EXEC 0x00e5 pxe_api.h 　
12993
 PXENV_FILE_API_CHECKPXENV_FILE_API_CHECK 0x00e6 pxe_api.h 　
12994
 PXENV_FILE_EXIT_HOOKPXENV_FILE_EXIT_HOOK 0x00e7 pxe_api.h 　
12995
 PXE_LOAD_SEGMENTPXE_LOAD_SEGMENT 0 pxe_call.h 　
12996
 PXE_LOAD_OFFSETPXE_LOAD_OFFSET 0x7c00 pxe_call.h 　
12997
 PXE_LOAD_PHYSPXE_LOAD_PHYS ( ( PXE_LOAD_SEGMENT << 4 ) + PXE_LOAD_OFFSET ) pxe_call.h 　
12998
 ppxeppxe __use_text16 ( ppxe ) pxe_call.h 　
12999
 pxenvpxenv __use_text16 ( pxenv ) pxe_call.h 　
13000
 PXENV_EXIT_SUCCESSPXENV_EXIT_SUCCESS 0x0000 pxe_types.h *< No error occurred
13001
 PXENV_EXIT_FAILUREPXENV_EXIT_FAILURE 0x0001 pxe_types.h *< An error occurred
13002
 MAC_ADDR_LENMAC_ADDR_LEN 16 pxe_types.h 　
13003
 CFCF ( 1 << 0 ) registers.h 　
13004
 PFPF ( 1 << 2 ) registers.h 　
13005
 AFAF ( 1 << 4 ) registers.h 　
13006
 ZFZF ( 1 << 6 ) registers.h 　
13007
 SFSF ( 1 << 7 ) registers.h 　
13008
 OFOF ( 1 << 11 ) registers.h 　
13009
 UNDI_NO_PCI_BUSDEVFNUNDI_NO_PCI_BUSDEVFN 0xffff undi.h 　
13010
 UNDI_NO_ISAPNP_CSNUNDI_NO_ISAPNP_CSN 0xffff undi.h 　
13011
 UNDI_NO_ISAPNP_READ_PORTUNDI_NO_ISAPNP_READ_PORT 0xffff undi.h 　
13012
 UNDI_FL_STARTEDUNDI_FL_STARTED 0x0001 undi.h 　
13013
 UNDI_FL_INITIALIZEDUNDI_FL_INITIALIZED 0x0002 undi.h 　
13014
 UNDI_FL_KEEP_ALLUNDI_FL_KEEP_ALL 0x0004 undi.h 　
13015
 preloaded_undipreloaded_undi __use_data16 ( preloaded_undi ) undipreload.h 　
13016
 VGA_H_INCLVGA_H_INCL 1 vga.h 　
13017
 u8u8 unsigned char vga.h 　
13018
 u16u16 unsigned short vga.h 　
13019
 u32u32 unsigned int vga.h 　
13020
 __u32__u32 u32 vga.h 　
13021
 VERRORVERROR -1 vga.h 　
13022
 CHAR_HEIGHTCHAR_HEIGHT 16 vga.h 　
13023
 LINESLINES 25 vga.h 　
13024
 COLSCOLS 80 vga.h 　
13025
 SYNC_HOR_HIGH_ACTSYNC_HOR_HIGH_ACT 1 vga.h horizontal sync high active
13026
 SYNC_VERT_HIGH_ACTSYNC_VERT_HIGH_ACT 2 vga.h vertical sync high active
13027
 SYNC_EXTSYNC_EXT 4 vga.h external sync
13028
 SYNC_COMP_HIGH_ACTSYNC_COMP_HIGH_ACT 8 vga.h composite sync high active
13029
 SYNC_BROADCASTSYNC_BROADCAST 16 vga.h broadcast video timings
13030
 SYNC_ON_GREENSYNC_ON_GREEN 32 vga.h sync on green
13031
 VMODE_NONINTERLACEDVMODE_NONINTERLACED 0 vga.h non interlaced
13032
 VMODE_INTERLACEDVMODE_INTERLACED 1 vga.h interlaced
13033
 VMODE_DOUBLEVMODE_DOUBLE 2 vga.h double scan
13034
 VMODE_MASKVMODE_MASK 255 vga.h 　
13035
 VMODE_YWRAPVMODE_YWRAP 256 vga.h ywrap instead of panning
13036
 VMODE_SMOOTH_XPANVMODE_SMOOTH_XPAN 512 vga.h smooth xpan possible (internally used)
13037
 VMODE_CONUPDATEVMODE_CONUPDATE 512 vga.h don't update x/yoffset
13038
 CRT_DCCRT_DC 0x3D5 vga.h CRT Controller Data Register - color emulation
13039
 CRT_DMCRT_DM 0x3B5 vga.h CRT Controller Data Register - mono emulation
13040
 ATT_RATT_R 0x3C1 vga.h Attribute Controller Data Read Register
13041
 GRA_DGRA_D 0x3CF vga.h Graphics Controller Data Register
13042
 SEQ_DSEQ_D 0x3C5 vga.h Sequencer Data Register
13043
 MIS_RMIS_R 0x3CC vga.h Misc Output Read Register
13044
 MIS_WMIS_W 0x3C2 vga.h Misc Output Write Register
13045
 IS1_RCIS1_RC 0x3DA vga.h Input Status Register 1 - color emulation
13046
 IS1_RMIS1_RM 0x3BA vga.h Input Status Register 1 - mono emulation
13047
 PEL_DPEL_D 0x3C9 vga.h PEL Data Register
13048
 PEL_MSKPEL_MSK 0x3C6 vga.h PEL mask register
13049
 GRA_E0GRA_E0 0x3CC vga.h Graphics enable processor 0
13050
 GRA_E1GRA_E1 0x3CA vga.h Graphics enable processor 1
13051
 CRT_ICCRT_IC 0x3D4 vga.h CRT Controller Index - color emulation
13052
 CRT_IMCRT_IM 0x3B4 vga.h CRT Controller Index - mono emulation
13053
 ATT_IWATT_IW 0x3C0 vga.h Attribute Controller Index & Data Write Register
13054
 GRA_IGRA_I 0x3CE vga.h Graphics Controller Index
13055
 SEQ_ISEQ_I 0x3C4 vga.h Sequencer Index
13056
 PEL_IWPEL_IW 0x3C8 vga.h PEL Write Index
13057
 PEL_IRPEL_IR 0x3C7 vga.h PEL Read Index
13058
 CRTC_CCRTC_C 25 vga.h 25 CRT Controller Registers sequentially set
13059
 ATT_CATT_C 21 vga.h 21 Attribute Controller Registers
13060
 GRA_CGRA_C 9 vga.h 9 Graphics Controller Registers
13061
 SEQ_CSEQ_C 5 vga.h 5 Sequencer Registers
13062
 MIS_CMIS_C 1 vga.h 1 Misc Output Register
13063
 CRTC_H_TOTALCRTC_H_TOTAL 0 vga.h 　
13064
 CRTC_H_DISPCRTC_H_DISP 1 vga.h 　
13065
 CRTC_H_BLANK_STARTCRTC_H_BLANK_START 2 vga.h 　
13066
 CRTC_H_BLANK_ENDCRTC_H_BLANK_END 3 vga.h 　
13067
 CRTC_H_SYNC_STARTCRTC_H_SYNC_START 4 vga.h 　
13068
 CRTC_H_SYNC_ENDCRTC_H_SYNC_END 5 vga.h 　
13069
 CRTC_V_TOTALCRTC_V_TOTAL 6 vga.h 　
13070
 CRTC_OVERFLOWCRTC_OVERFLOW 7 vga.h 　
13071
 CRTC_PRESET_ROWCRTC_PRESET_ROW 8 vga.h 　
13072
 CRTC_MAX_SCANCRTC_MAX_SCAN 9 vga.h 　
13073
 CRTC_CURSOR_STARTCRTC_CURSOR_START 0x0A vga.h 　
13074
 CRTC_CURSOR_ENDCRTC_CURSOR_END 0x0B vga.h 　
13075
 CRTC_START_HICRTC_START_HI 0x0C vga.h 　
13076
 CRTC_START_LOCRTC_START_LO 0x0D vga.h 　
13077
 CRTC_CURSOR_HICRTC_CURSOR_HI 0x0E vga.h 　
13078
 CRTC_CURSOR_LOCRTC_CURSOR_LO 0x0F vga.h 　
13079
 CRTC_V_SYNC_STARTCRTC_V_SYNC_START 0x10 vga.h 　
13080
 CRTC_V_SYNC_ENDCRTC_V_SYNC_END 0x11 vga.h 　
13081
 CRTC_V_DISP_ENDCRTC_V_DISP_END 0x12 vga.h 　
13082
 CRTC_OFFSETCRTC_OFFSET 0x13 vga.h 　
13083
 CRTC_UNDERLINECRTC_UNDERLINE 0x14 vga.h 　
13084
 CRTC_V_BLANK_STARTCRTC_V_BLANK_START 0x15 vga.h 　
13085
 CRTC_V_BLANK_ENDCRTC_V_BLANK_END 0x16 vga.h 　
13086
 CRTC_MODECRTC_MODE 0x17 vga.h 　
13087
 CRTC_LINE_COMPARECRTC_LINE_COMPARE 0x18 vga.h 　
13088
 ATC_MODEATC_MODE 0x10 vga.h 　
13089
 ATC_OVERSCANATC_OVERSCAN 0x11 vga.h 　
13090
 ATC_PLANE_ENABLEATC_PLANE_ENABLE 0x12 vga.h 　
13091
 ATC_PELATC_PEL 0x13 vga.h 　
13092
 ATC_COLOR_PAGEATC_COLOR_PAGE 0x14 vga.h 　
13093
 SEQ_CLOCK_MODESEQ_CLOCK_MODE 0x01 vga.h 　
13094
 SEQ_PLANE_WRITESEQ_PLANE_WRITE 0x02 vga.h 　
13095
 SEQ_CHARACTER_MAPSEQ_CHARACTER_MAP 0x03 vga.h 　
13096
 SEQ_MEMORY_MODESEQ_MEMORY_MODE 0x04 vga.h 　
13097
 GDC_SR_VALUEGDC_SR_VALUE 0x00 vga.h 　
13098
 GDC_SR_ENABLEGDC_SR_ENABLE 0x01 vga.h 　
13099
 GDC_COMPARE_VALUEGDC_COMPARE_VALUE 0x02 vga.h 　
13100
 GDC_DATA_ROTATEGDC_DATA_ROTATE 0x03 vga.h 　
13101
 GDC_PLANE_READGDC_PLANE_READ 0x04 vga.h 　
13102
 GDC_MODEGDC_MODE 0x05 vga.h 　
13103
 GDC_MISCGDC_MISC 0x06 vga.h 　
13104
 GDC_COMPARE_MASKGDC_COMPARE_MASK 0x07 vga.h 　
13105
 GDC_BIT_MASKGDC_BIT_MASK 0x08 vga.h 　
13106
 VGA_ATTR_CLR_REDVGA_ATTR_CLR_RED 0x4 vga.h 　
13107
 VGA_ATTR_CLR_GRNVGA_ATTR_CLR_GRN 0x2 vga.h 　
13108
 VGA_ATTR_CLR_BLUVGA_ATTR_CLR_BLU 0x1 vga.h 　
13109
 VGA_ATTR_CLR_YELVGA_ATTR_CLR_YEL (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN) vga.h 　
13110
 VGA_ATTR_CLR_CYNVGA_ATTR_CLR_CYN (VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) vga.h 　
13111
 VGA_ATTR_CLR_MAGVGA_ATTR_CLR_MAG (VGA_ATTR_CLR_BLU | VGA_ATTR_CLR_RED) vga.h 　
13112
 VGA_ATTR_CLR_BLKVGA_ATTR_CLR_BLK 0 vga.h 　
13113
 VGA_ATTR_CLR_WHTVGA_ATTR_CLR_WHT (VGA_ATTR_CLR_RED | VGA_ATTR_CLR_GRN | VGA_ATTR_CLR_BLU) vga.h 　
13114
 VGA_ATTR_BNKVGA_ATTR_BNK 0x80 vga.h 　
13115
 VGA_ATTR_ITNVGA_ATTR_ITN 0x08 vga.h 　
13116
 __asmcall__asmcall __attribute__ (( cdecl, regparm(0) )) compiler.h 　
13117
 __libgcc__libgcc __attribute__ (( cdecl )) compiler.h 　
13118
 X86_FEATURE_FPUX86_FEATURE_FPU 0 cpu.h Onboard FPU
13119
 X86_FEATURE_VMEX86_FEATURE_VME 1 cpu.h Virtual Mode Extensions
13120
 X86_FEATURE_DEX86_FEATURE_DE 2 cpu.h Debugging Extensions
13121
 X86_FEATURE_PSEX86_FEATURE_PSE 3 cpu.h Page Size Extensions
13122
 X86_FEATURE_TSCX86_FEATURE_TSC 4 cpu.h Time Stamp Counter
13123
 X86_FEATURE_MSRX86_FEATURE_MSR 5 cpu.h Model-Specific Registers, RDMSR, WRMSR
13124
 X86_FEATURE_PAEX86_FEATURE_PAE 6 cpu.h Physical Address Extensions
13125
 X86_FEATURE_MCEX86_FEATURE_MCE 7 cpu.h Machine Check Architecture
13126
 X86_FEATURE_CX8X86_FEATURE_CX8 8 cpu.h CMPXCHG8 instruction
13127
 X86_FEATURE_APICX86_FEATURE_APIC 9 cpu.h Onboard APIC
13128
 X86_FEATURE_SEPX86_FEATURE_SEP 11 cpu.h SYSENTER/SYSEXIT
13129
 X86_FEATURE_MTRRX86_FEATURE_MTRR 12 cpu.h Memory Type Range Registers
13130
 X86_FEATURE_PGEX86_FEATURE_PGE 13 cpu.h Page Global Enable
13131
 X86_FEATURE_MCAX86_FEATURE_MCA 14 cpu.h Machine Check Architecture
13132
 X86_FEATURE_CMOVX86_FEATURE_CMOV 15 cpu.h CMOV instruction (FCMOVCC and FCOMI too if FPU present)
13133
 X86_FEATURE_PATX86_FEATURE_PAT 16 cpu.h Page Attribute Table
13134
 X86_FEATURE_PSE36X86_FEATURE_PSE36 17 cpu.h 36-bit PSEs
13135
 X86_FEATURE_PNX86_FEATURE_PN 18 cpu.h Processor serial number
13136
 X86_FEATURE_CLFLSHX86_FEATURE_CLFLSH 19 cpu.h Supports the CLFLUSH instruction
13137
 X86_FEATURE_DTESX86_FEATURE_DTES 21 cpu.h Debug Trace Store
13138
 X86_FEATURE_ACPIX86_FEATURE_ACPI 22 cpu.h ACPI via MSR
13139
 X86_FEATURE_MMXX86_FEATURE_MMX 23 cpu.h Multimedia Extensions
13140
 X86_FEATURE_FXSRX86_FEATURE_FXSR 24 cpu.h FXSAVE and FXRSTOR instructions (fast save and restore
13141
 X86_FEATURE_XMMX86_FEATURE_XMM 25 cpu.h Streaming SIMD Extensions
13142
 X86_FEATURE_XMM2X86_FEATURE_XMM2 26 cpu.h Streaming SIMD Extensions-2
13143
 X86_FEATURE_SELFSNOOPX86_FEATURE_SELFSNOOP 27 cpu.h CPU self snoop
13144
 X86_FEATURE_HTX86_FEATURE_HT 28 cpu.h Hyper-Threading
13145
 X86_FEATURE_ACCX86_FEATURE_ACC 29 cpu.h Automatic clock control
13146
 X86_FEATURE_IA64X86_FEATURE_IA64 30 cpu.h IA-64 processor
13147
 X86_FEATURE_SYSCALLX86_FEATURE_SYSCALL 11 cpu.h SYSCALL/SYSRET
13148
 X86_FEATURE_MMXEXTX86_FEATURE_MMXEXT 22 cpu.h AMD MMX extensions
13149
 X86_FEATURE_LMX86_FEATURE_LM 29 cpu.h Long Mode (x86-64)
13150
 X86_FEATURE_3DNOWEXTX86_FEATURE_3DNOWEXT 30 cpu.h AMD 3DNow! extensions
13151
 X86_FEATURE_3DNOWX86_FEATURE_3DNOW 31 cpu.h 3DNow!
13152
 X86_EFLAGS_CFX86_EFLAGS_CF 0x00000001 cpu.h Carry Flag
13153
 X86_EFLAGS_PFX86_EFLAGS_PF 0x00000004 cpu.h Parity Flag
13154
 X86_EFLAGS_AFX86_EFLAGS_AF 0x00000010 cpu.h Auxillary carry Flag
13155
 X86_EFLAGS_ZFX86_EFLAGS_ZF 0x00000040 cpu.h Zero Flag
13156
 X86_EFLAGS_SFX86_EFLAGS_SF 0x00000080 cpu.h Sign Flag
13157
 X86_EFLAGS_TFX86_EFLAGS_TF 0x00000100 cpu.h Trap Flag
13158
 X86_EFLAGS_IFX86_EFLAGS_IF 0x00000200 cpu.h Interrupt Flag
13159
 X86_EFLAGS_DFX86_EFLAGS_DF 0x00000400 cpu.h Direction Flag
13160
 X86_EFLAGS_OFX86_EFLAGS_OF 0x00000800 cpu.h Overflow Flag
13161
 X86_EFLAGS_IOPLX86_EFLAGS_IOPL 0x00003000 cpu.h IOPL mask
13162
 X86_EFLAGS_NTX86_EFLAGS_NT 0x00004000 cpu.h Nested Task
13163
 X86_EFLAGS_RFX86_EFLAGS_RF 0x00010000 cpu.h Resume Flag
13164
 X86_EFLAGS_VMX86_EFLAGS_VM 0x00020000 cpu.h Virtual Mode
13165
 X86_EFLAGS_ACX86_EFLAGS_AC 0x00040000 cpu.h Alignment Check
13166
 X86_EFLAGS_VIFX86_EFLAGS_VIF 0x00080000 cpu.h Virtual Interrupt Flag
13167
 X86_EFLAGS_VIPX86_EFLAGS_VIP 0x00100000 cpu.h Virtual Interrupt Pending
13168
 X86_EFLAGS_IDX86_EFLAGS_ID 0x00200000 cpu.h CPUID detection flag
13169
 ELTORITO_PLATFORMELTORITO_PLATFORM ELTORITO_PLATFORM_X86 eltorito.h 　
13170
 __BYTE_ORDER__BYTE_ORDER __LITTLE_ENDIAN endian.h 　
13171
 ERRFILE_memtop_umallocERRFILE_memtop_umalloc ( ERRFILE_ARCH | ERRFILE_CORE | 0x00000000 ) errfile.h 　
13172
 ERRFILE_memmapERRFILE_memmap ( ERRFILE_ARCH | ERRFILE_CORE | 0x00010000 ) errfile.h 　
13173
 ERRFILE_pnpbiosERRFILE_pnpbios ( ERRFILE_ARCH | ERRFILE_CORE | 0x00020000 ) errfile.h 　
13174
 ERRFILE_bios_smbiosERRFILE_bios_smbios ( ERRFILE_ARCH | ERRFILE_CORE | 0x00030000 ) errfile.h 　
13175
 ERRFILE_biosintERRFILE_biosint ( ERRFILE_ARCH | ERRFILE_CORE | 0x00040000 ) errfile.h 　
13176
 ERRFILE_int13ERRFILE_int13 ( ERRFILE_ARCH | ERRFILE_CORE | 0x00050000 ) errfile.h 　
13177
 ERRFILE_pxeparentERRFILE_pxeparent ( ERRFILE_ARCH | ERRFILE_CORE | 0x00060000 ) errfile.h 　
13178
 ERRFILE_bootsectorERRFILE_bootsector ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00000000 ) errfile.h 　
13179
 ERRFILE_bzimageERRFILE_bzimage ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00010000 ) errfile.h 　
13180
 ERRFILE_eltoritoERRFILE_eltorito ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00020000 ) errfile.h 　
13181
 ERRFILE_multibootERRFILE_multiboot ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00030000 ) errfile.h 　
13182
 ERRFILE_nbiERRFILE_nbi ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00040000 ) errfile.h 　
13183
 ERRFILE_pxe_imageERRFILE_pxe_image ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00050000 ) errfile.h 　
13184
 ERRFILE_elfbootERRFILE_elfboot ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00060000 ) errfile.h 　
13185
 ERRFILE_combootERRFILE_comboot ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00070000 ) errfile.h 　
13186
 ERRFILE_com32ERRFILE_com32 ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00080000 ) errfile.h 　
13187
 ERRFILE_comboot_resolvERRFILE_comboot_resolv ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x00090000 ) errfile.h 　
13188
 ERRFILE_comboot_callERRFILE_comboot_call ( ERRFILE_ARCH | ERRFILE_IMAGE | 0x000a0000 ) errfile.h 　
13189
 ERRFILE_undiERRFILE_undi ( ERRFILE_ARCH | ERRFILE_NET | 0x00000000 ) errfile.h 　
13190
 ERRFILE_undiloadERRFILE_undiload ( ERRFILE_ARCH | ERRFILE_NET | 0x00010000 ) errfile.h 　
13191
 ERRFILE_undinetERRFILE_undinet ( ERRFILE_ARCH | ERRFILE_NET | 0x00020000 ) errfile.h 　
13192
 ERRFILE_undionlyERRFILE_undionly ( ERRFILE_ARCH | ERRFILE_NET | 0x00030000 ) errfile.h 　
13193
 ERRFILE_undiromERRFILE_undirom ( ERRFILE_ARCH | ERRFILE_NET | 0x00040000 ) errfile.h 　
13194
 ERRFILE_timer_rdtscERRFILE_timer_rdtsc ( ERRFILE_ARCH | ERRFILE_DRIVER | 0x00000000 ) errfile.h 　
13195
 ERRFILE_timer_biosERRFILE_timer_bios ( ERRFILE_ARCH | ERRFILE_DRIVER | 0x00010000 ) errfile.h 　
13196
 DHCP_ARCH_VENDOR_CLASS_IDDHCP_ARCH_VENDOR_CLASS_ID DHCP_STRING ( 'P', 'X', 'E', 'C', 'l', 'i', 'e', 'n', 't', ':', \ 'A', 'r', 'c', 'h', ':', '0', '0', '0', '0', '6', ':', dhcp_arch.h 　
13197
 DHCP_ARCH_CLIENT_ARCHITECTUREDHCP_ARCH_CLIENT_ARCHITECTURE DHCP_WORD ( 6 ) dhcp_arch.h 　
13198
 DHCP_ARCH_CLIENT_NDIDHCP_ARCH_CLIENT_NDI DHCP_OPTION ( 1 , 3, 10 ) dhcp_arch.h UNDI v3.10
13199
 ABFT_SIGABFT_SIG "aBFT" abft.h 　
13200
 NAP_PREFIX_pcbiosNAP_PREFIX_pcbios __pcbios_ bios_nap.h 　
13201
 SMBIOS_PREFIX_pcbiosSMBIOS_PREFIX_pcbios __pcbios_ bios_smbios.h 　
13202
 TIMER_PREFIX_pcbiosTIMER_PREFIX_pcbios __pcbios_ bios_timer.h 　
13203
 IBFT_SIGIBFT_SIG "iBFT" ibft.h 　
13204
 IBFT_STRUCTURE_ID_CONTROLIBFT_STRUCTURE_ID_CONTROL 0x01 ibft.h 　
13205
 IBFT_FL_CONTROL_SINGLE_LOGIN_ONIBFT_FL_CONTROL_SINGLE_LOGIN_ON 0x01 ibft.h 　
13206
 IBFT_STRUCTURE_ID_INITIATORIBFT_STRUCTURE_ID_INITIATOR 0x02 ibft.h 　
13207
 IBFT_FL_INITIATOR_BLOCK_VALIDIBFT_FL_INITIATOR_BLOCK_VALID 0x01 ibft.h 　
13208
 IBFT_FL_INITIATOR_FIRMWARE_BOOTIBFT_FL_INITIATOR_FIRMWARE_BOOT 0x02 ibft.h 　
13209
 IBFT_STRUCTURE_ID_NICIBFT_STRUCTURE_ID_NIC 0x03 ibft.h 　
13210
 IBFT_FL_NIC_BLOCK_VALIDIBFT_FL_NIC_BLOCK_VALID 0x01 ibft.h 　
13211
 IBFT_FL_NIC_FIRMWARE_BOOT_SELECIBFT_FL_NIC_FIRMWARE_BOOT_SELEC 0x02 ibft.h 　
13212
 IBFT_FL_NIC_GLOBALIBFT_FL_NIC_GLOBAL 0x04 ibft.h 　
13213
 IBFT_STRUCTURE_ID_TARGETIBFT_STRUCTURE_ID_TARGET 0x04 ibft.h 　
13214
 IBFT_FL_TARGET_BLOCK_VALIDIBFT_FL_TARGET_BLOCK_VALID 0x01 ibft.h 　
13215
 IBFT_FL_TARGET_FIRMWARE_BOOT_SEIBFT_FL_TARGET_FIRMWARE_BOOT_SE 0x02 ibft.h 　
13216
 IBFT_FL_TARGET_USE_CHAPIBFT_FL_TARGET_USE_CHAP 0x04 ibft.h 　
13217
 IBFT_FL_TARGET_USE_RCHAPIBFT_FL_TARGET_USE_RCHAP 0x08 ibft.h 　
13218
 IBFT_CHAP_NONEIBFT_CHAP_NONE 0 ibft.h *< No CHAP authentication
13219
 IBFT_CHAP_ONE_WAYIBFT_CHAP_ONE_WAY 1 ibft.h *< One-way CHAP
13220
 IBFT_CHAP_MUTUALIBFT_CHAP_MUTUAL 2 ibft.h *< Mutual CHAP
13221
 IBFT_STRINGS_SIZEIBFT_STRINGS_SIZE 384 ibft.h 　
13222
 UMALLOC_PREFIX_memtopUMALLOC_PREFIX_memtop __memtop_ memtop_umalloc.h 　
13223
 TIMER_PREFIX_rdtscTIMER_PREFIX_rdtsc __rdtsc_ rdtsc_timer.h 　
13224
 TSC_SHIFTTSC_SHIFT 8 rdtsc_timer.h 　
13225
 SBFT_SIGSBFT_SIG "sBFT" sbft.h 　
13226
 IOAPI_PREFIX_x86IOAPI_PREFIX_x86 __x86_ x86_io.h 　
13227
 DHCP_ARCH_VENDOR_CLASS_IDDHCP_ARCH_VENDOR_CLASS_ID DHCP_STRING ( 'P', 'X', 'E', 'C', 'l', 'i', 'e', 'n', 't', ':', \ 'A', 'r', 'c', 'h', ':', '0', '0', '0', '0', '0', ':', dhcp_arch.h 　
13228
 DHCP_ARCH_CLIENT_ARCHITECTUREDHCP_ARCH_CLIENT_ARCHITECTURE DHCP_WORD ( 0 ) dhcp_arch.h 　
13229
 DHCP_ARCH_CLIENT_NDIDHCP_ARCH_CLIENT_NDI DHCP_OPTION ( 1 , 2, 1 ) dhcp_arch.h UNDI v2.1
13230
 abftababftab __use_data16 ( abftab ) abft.c 　
13231
 ibftabibftab __use_data16 ( ibftab ) ibft.c 　
13232
 int13_vectorint13_vector __use_text16 ( int13_vector ) int13.c 　
13233
 EM_ALIGNEM_ALIGN ( 4 * 1024 ) memtop_umalloc.c 　
13234
 UNOWHEREUNOWHERE ( ~UNULL ) memtop_umalloc.c 　
13235
 sbftabsbftab __use_data16 ( sbftab ) sbft.c 　
13236
 pxe_int_1a_vectorpxe_int_1a_vector __use_text16 ( pxe_int_1a_vector ) pxe_call.c 　
13237
 pxe_exit_hookpxe_exit_hook __use_data16 ( pxe_exit_hook ) pxe_file.c 　
13238
 cached_infocached_info __use_data16 ( cached_info ) pxe_preboot.c 　
13239
 PXE_TFTP_URI_LENPXE_TFTP_URI_LEN 256 pxe_tftp.c 　
13240
 pxeparent_paramspxeparent_params __use_data16 ( pxeparent_params ) pxeparent.c 　
13241
 pxeparent_entry_pointpxeparent_entry_point __use_data16 ( pxeparent_entry_point ) pxeparent.c 　
13242
 com32_regscom32_regs __use_data16 ( com32_regs ) com32_call.c 　
13243
 com32_int_vectorcom32_int_vector __use_data16 ( com32_int_vector ) com32_call.c 　
13244
 com32_farcall_proccom32_farcall_proc __use_data16 ( com32_farcall_proc ) com32_call.c 　
13245
 syslinux_versionsyslinux_version __use_data16 ( syslinux_version ) comboot_call.c 　
13246
 syslinux_copyrightsyslinux_copyright __use_data16 ( syslinux_copyright ) comboot_call.c 　
13247
 syslinux_configuration_filesyslinux_configuration_file __use_data16 ( syslinux_configuration_file ) comboot_call.c 　
13248
 comboot_feature_flagscomboot_feature_flags __use_data16 ( comboot_feature_flags ) comboot_call.c 　
13249
 comboot_initial_regscomboot_initial_regs __use_text16 ( comboot_initial_regs ) comboot_call.c 　
13250
 int20_vectorint20_vector __use_text16 ( int20_vector ) comboot_call.c 　
13251
 int21_vectorint21_vector __use_text16 ( int21_vector ) comboot_call.c 　
13252
 int22_vectorint22_vector __use_text16 ( int22_vector ) comboot_call.c 　
13253
 PCIAPI_PREFIX_pcbiosPCIAPI_PREFIX_pcbios __pcbios_ pcibios.h 　
13254
 PCIBIOS_INSTALLATION_CHECKPCIBIOS_INSTALLATION_CHECK 0xb1010000 pcibios.h 　
13255
 PCIBIOS_READ_CONFIG_BYTEPCIBIOS_READ_CONFIG_BYTE 0xb1080000 pcibios.h 　
13256
 PCIBIOS_READ_CONFIG_WORDPCIBIOS_READ_CONFIG_WORD 0xb1090000 pcibios.h 　
13257
 PCIBIOS_READ_CONFIG_DWORDPCIBIOS_READ_CONFIG_DWORD 0xb10a0000 pcibios.h 　
13258
 PCIBIOS_WRITE_CONFIG_BYTEPCIBIOS_WRITE_CONFIG_BYTE 0xb10b0000 pcibios.h 　
13259
 PCIBIOS_WRITE_CONFIG_WORDPCIBIOS_WRITE_CONFIG_WORD 0xb10c0000 pcibios.h 　
13260
 PCIBIOS_WRITE_CONFIG_DWORDPCIBIOS_WRITE_CONFIG_DWORD 0xb10d0000 pcibios.h 　
13261
 PCIAPI_PREFIX_directPCIAPI_PREFIX_direct __direct_ pcidirect.h 　
13262
 PCIDIRECT_CONFIG_ADDRESSPCIDIRECT_CONFIG_ADDRESS 0xcf8 pcidirect.h 　
13263
 PCIDIRECT_CONFIG_DATAPCIDIRECT_CONFIG_DATA 0xcfc pcidirect.h 　
13264
 NAP_PREFIX_efix86NAP_PREFIX_efix86 __efix86_ efix86_nap.h 　
13265
 LIMITS_HLIMITS_H 1 limits.h 　
13266
 CHAR_BITCHAR_BIT 8 limits.h 　
13267
 SCHAR_MINSCHAR_MIN (-128) limits.h 　
13268
 SCHAR_MAXSCHAR_MAX 127 limits.h 　
13269
 UCHAR_MAXUCHAR_MAX 255 limits.h 　
13270
 CHAR_MINCHAR_MIN SCHAR_MIN limits.h 　
13271
 CHAR_MAXCHAR_MAX SCHAR_MAX limits.h 　
13272
 SHRT_MINSHRT_MIN (-32768) limits.h 　
13273
 SHRT_MAXSHRT_MAX 32767 limits.h 　
13274
 USHRT_MAXUSHRT_MAX 65535 limits.h 　
13275
 INT_MININT_MIN (-INT_MAX - 1) limits.h 　
13276
 INT_MAXINT_MAX 2147483647 limits.h 　
13277
 UINT_MAXUINT_MAX 4294967295U limits.h 　
13278
 INT_MAXINT_MAX 2147483647 limits.h 　
13279
 INT_MININT_MIN (-INT_MAX - 1) limits.h 　
13280
 UINT_MAXUINT_MAX 4294967295U limits.h 　
13281
 LONG_MAXLONG_MAX 9223372036854775807L limits.h 　
13282
 LONG_MINLONG_MIN (-LONG_MAX - 1L) limits.h 　
13283
 ULONG_MAXULONG_MAX 18446744073709551615UL limits.h 　
13284
 LLONG_MAXLLONG_MAX 9223372036854775807LL limits.h 　
13285
 LLONG_MINLLONG_MIN (-LONG_MAX - 1LL) limits.h 　
13286
 ULLONG_MAXULLONG_MAX 18446744073709551615ULL limits.h 　
13287
 __asmcall__asmcall __attribute__ (( regparm(0) )) compiler.h 　
13288
 __BYTE_ORDER__BYTE_ORDER __LITTLE_ENDIAN endian.h 　
13289
 DHCP_ARCH_VENDOR_CLASS_IDDHCP_ARCH_VENDOR_CLASS_ID DHCP_STRING ( 'P', 'X', 'E', 'C', 'l', 'i', 'e', 'n', 't', ':', \ 'A', 'r', 'c', 'h', ':', '0', '0', '0', '0', '7', ':', dhcp_arch.h 　
13290
 DHCP_ARCH_CLIENT_ARCHITECTUREDHCP_ARCH_CLIENT_ARCHITECTURE DHCP_WORD ( 7 ) dhcp_arch.h 　
13291
 DHCP_ARCH_CLIENT_NDIDHCP_ARCH_CLIENT_NDI DHCP_OPTION ( 1 , 3, 10 ) dhcp_arch.h UNDI v3.10
13292
 BUILD_SERIAL_STRBUILD_SERIAL_STR " #" XSTR(BUILD_SERIAL_NUM) config.c 　
13293
 BUILD_SERIAL_STRBUILD_SERIAL_STR "" config.c 　
13294
 BUILD_ID_STRBUILD_ID_STR " " BUILD_ID config.c 　
13295
 BUILD_ID_STRBUILD_ID_STR "" config.c 　
13296
 BUILD_STRINGBUILD_STRING " [build" BUILD_ID_STR BUILD_SERIAL_STR "]" config.c 　
13297
 BUILD_STRINGBUILD_STRING "" config.c 　
13298
 PRODUCT_NAMEPRODUCT_NAME "" general.h 　
13299
 PRODUCT_SHORT_NAMEPRODUCT_SHORT_NAME "gPXE" general.h 　
13300
 BANNER_TIMEOUTBANNER_TIMEOUT 20 general.h Tenths of a second for which the shell
13301
 COM1COM1 0x3f8 serial.h 　
13302
 COM2COM2 0x2f8 serial.h 　
13303
 COM3COM3 0x3e8 serial.h 　
13304
 COM4COM4 0x2e8 serial.h 　
13305
 COMCONSOLECOMCONSOLE COM1 serial.h I/O port address
13306
 COMSPEEDCOMSPEED 115200 serial.h Baud rate
13307
 COMDATACOMDATA 8 serial.h Data bits
13308
 COMPARITYCOMPARITY 0 serial.h Parity: 0=None, 1=Odd, 2=Even
13309
 COMSTOPCOMSTOP 1 serial.h Stop bits
13310
 CHAR_256CHAR_256 0 btext.c 　
13311
 cmapszcmapsz (16*256) btext.c 　
13312
 cmapszcmapsz (16*96) btext.c 　
13313
 GUARD_SYMBOLGUARD_SYMBOL ( ( 'M' << 24 ) | ( 'I' << 16 ) | ( 'N' << 8 ) | 'E' ) debug.c 　
13314
 NUM_AUTO_COLOURSNUM_AUTO_COLOURS 6 debug.c 　
13315
 GETKEY_TIMEOUTGETKEY_TIMEOUT ( TICKS_PER_SEC / 4 ) getkey.c 　
13316
 IS_VADEMIS_VADEM 0x0001 i82365.c 　
13317
 IS_CIRRUSIS_CIRRUS 0x0002 i82365.c 　
13318
 IS_TIIS_TI 0x0004 i82365.c 　
13319
 IS_O2MICROIS_O2MICRO 0x0008 i82365.c 　
13320
 IS_VIAIS_VIA 0x0010 i82365.c 　
13321
 IS_TOPICIS_TOPIC 0x0020 i82365.c 　
13322
 IS_RICOHIS_RICOH 0x0040 i82365.c 　
13323
 IS_UNKNOWNIS_UNKNOWN 0x0400 i82365.c 　
13324
 IS_VG_PWRIS_VG_PWR 0x0800 i82365.c 　
13325
 IS_DF_PWRIS_DF_PWR 0x1000 i82365.c 　
13326
 IS_PCIIS_PCI 0x2000 i82365.c 　
13327
 IS_ALIVEIS_ALIVE 0x8000 i82365.c 　
13328
 NORMALNORMAL "\033[0m" main.c 　
13329
 BOLDBOLD "\033[1m" main.c 　
13330
 CYANCYAN "\033[36m" main.c 　
13331
 MIN_MEMBLOCK_SIZEMIN_MEMBLOCK_SIZE ( ( size_t ) ( 1 << ( fls ( sizeof ( struct memory_block ) - 1 ) ) ) ) malloc.c 　
13332
 NOWHERENOWHERE ( ( void * ) ~( ( intptr_t ) 0 ) ) malloc.c 　
13333
 HEAP_SIZEHEAP_SIZE ( 128 * 1024 ) malloc.c 　
13334
 CODE_STATUSCODE_STATUS "alpha" pcmcia.c 　
13335
 CODE_VERSIONCODE_VERSION "0.1.3" pcmcia.c 　
13336
 NUM_DRIVERSNUM_DRIVERS (sizeof(driver)/(sizeof(struct driver_interact_t))) pcmcia.c 　
13337
 SHIFTSHIFT 1 pc_kbd.c 　
13338
 CONTROLCONTROL 2 pc_kbd.c 　
13339
 CAPSCAPS 4 pc_kbd.c 　
13340
 LACP_DEBUGLACP_DEBUG 0 proto_eth_slow.c 　
13341
 SLOW_DST_MACSLOW_DST_MAC "\x01\x80\xc2\x00\x00\x02" proto_eth_slow.c 　
13342
 SLOW_SUBTYPE_LACPSLOW_SUBTYPE_LACP 1 proto_eth_slow.c 　
13343
 SLOW_SUBTYPE_MARKERSLOW_SUBTYPE_MARKER 2 proto_eth_slow.c 　
13344
 LACP_CMP_LENLACP_CMP_LEN (2 + 6 + 2 + 2 + 2) proto_eth_slow.c 　
13345
 LACP_CP_LENLACP_CP_LEN (2 + 6 + 2 + 2 + 2 + 1) proto_eth_slow.c 　
13346
 FAST_PERIODIC_TIMEFAST_PERIODIC_TIME (1*TICKS_PER_SEC) proto_eth_slow.c 　
13347
 SLOW_PERIODIC_TIMESLOW_PERIODIC_TIME (30*TICKS_PER_SEC) proto_eth_slow.c 　
13348
 SHORT_TIMEOUT_TIMESHORT_TIMEOUT_TIME (3*FAST_PERIODIC_TIME) proto_eth_slow.c 　
13349
 LONG_TIMEOUT_TIMELONG_TIMEOUT_TIME (3*SLOW_PERIODIC_TIME) proto_eth_slow.c 　
13350
 CHURN_DETECTION_TIMECHURN_DETECTION_TIME (60*TICKS_PER_SEC) proto_eth_slow.c 　
13351
 AGGREGATE_WAIT_TIMEAGGREGATE_WAIT_TIME (2*TICKS_PER_SEC) proto_eth_slow.c 　
13352
 LACP_ACTIVITYLACP_ACTIVITY (1 << 0) proto_eth_slow.c 　
13353
 LACP_TIMEOUTLACP_TIMEOUT (1 << 1) proto_eth_slow.c 　
13354
 LACP_AGGREGATIONLACP_AGGREGATION (1 << 2) proto_eth_slow.c 　
13355
 LACP_SYNCHRONIZATIONLACP_SYNCHRONIZATION (1 << 3) proto_eth_slow.c 　
13356
 LACP_COLLECTINGLACP_COLLECTING (1 << 4) proto_eth_slow.c 　
13357
 LACP_DISTRIBUTINGLACP_DISTRIBUTING (1 << 5) proto_eth_slow.c 　
13358
 LACP_DEFAULTEDLACP_DEFAULTED (1 << 6) proto_eth_slow.c 　
13359
 LACP_EXPIREDLACP_EXPIRED (1 << 7) proto_eth_slow.c 　
13360
 UNSELECTEDUNSELECTED 0 proto_eth_slow.c 　
13361
 STANDBYSTANDBY 1 proto_eth_slow.c 　
13362
 SELECTEDSELECTED 2 proto_eth_slow.c 　
13363
 LACP_NTT_MASKLACP_NTT_MASK (LACP_ACTIVITY | LACP_TIMEOUT | \ LACP_SYNCHRONIZATION | LACP_AGGREGATION) proto_eth_slow.c 　
13364
 COMCONSOLECOMCONSOLE 0x3f8 serial.c 　
13365
 COMSPEEDCOMSPEED 9600 serial.c 　
13366
 COMDATACOMDATA 8 serial.c 　
13367
 COMPARITYCOMPARITY 0 serial.c 　
13368
 COMSTOPCOMSTOP 1 serial.c 　
13369
 UART_BASEUART_BASE ( COMCONSOLE ) serial.c 　
13370
 UART_BAUDUART_BAUD ( COMSPEED ) serial.c 　
13371
 COMBRDCOMBRD (115200/UART_BAUD) serial.c 　
13372
 UART_LCSUART_LCS ( ( ( (COMDATA) - 5 ) << 0 ) | \ ( ( (COMPARITY) ) << 3 ) | \ ( ( (COMSTOP) - 1 ) << 2 ) ) serial.c 　
13373
 UART_RBRUART_RBR 0x00 serial.c 　
13374
 UART_TBRUART_TBR 0x00 serial.c 　
13375
 UART_IERUART_IER 0x01 serial.c 　
13376
 UART_IIRUART_IIR 0x02 serial.c 　
13377
 UART_FCRUART_FCR 0x02 serial.c 　
13378
 UART_LCRUART_LCR 0x03 serial.c 　
13379
 UART_MCRUART_MCR 0x04 serial.c 　
13380
 UART_DLLUART_DLL 0x00 serial.c 　
13381
 UART_DLMUART_DLM 0x01 serial.c 　
13382
 UART_LSRUART_LSR 0x05 serial.c 　
13383
 UART_LSR_TEMPTUART_LSR_TEMPT 0x40 serial.c Transmitter empty
13384
 UART_LSR_THREUART_LSR_THRE 0x20 serial.c Transmit-hold-register empty
13385
 UART_LSR_BIUART_LSR_BI 0x10 serial.c Break interrupt indicator
13386
 UART_LSR_FEUART_LSR_FE 0x08 serial.c Frame error indicator
13387
 UART_LSR_PEUART_LSR_PE 0x04 serial.c Parity error indicator
13388
 UART_LSR_OEUART_LSR_OE 0x02 serial.c Overrun error indicator
13389
 UART_LSR_DRUART_LSR_DR 0x01 serial.c Receiver data ready
13390
 UART_MSRUART_MSR 0x06 serial.c 　
13391
 UART_SCRUART_SCR 0x07 serial.c 　
13392
 settings_rootsettings_root generic_settings_root.settings settings.c 　
13393
 CHAR_LENCHAR_LEN 0 vsprintf.c *< "hh" length modifier
13394
 SHORT_LENSHORT_LEN 1 vsprintf.c *< "h" length modifier
13395
 INT_LENINT_LEN 2 vsprintf.c *< no length modifier
13396
 LONG_LENLONG_LEN 3 vsprintf.c *< "l" length modifier
13397
 LONGLONG_LENLONGLONG_LEN 4 vsprintf.c *< "ll" length modifier
13398
 SIZE_T_LENSIZE_T_LEN 5 vsprintf.c *< "z" length modifier
13399
 LCASELCASE 0x20 vsprintf.c 　
13400
 ALT_FORMALT_FORM 0x02 vsprintf.c 　
13401
 CRCPOLYCRCPOLY 0xedb88320 crc32.c 　
13402
 mtmt 0x80808080 aes.c 　
13403
 mlml 0x7f7f7f7f aes.c 　
13404
 mhmh 0xfefefefe aes.c 　
13405
 mmmm 0x1b1b1b1b aes.c 　
13406
 BIGINT_M_OFFSETBIGINT_M_OFFSET 0 bigint_impl.h *< Normal modulo offset.
13407
 BIGINT_P_OFFSETBIGINT_P_OFFSET 1 bigint_impl.h *< p modulo offset.
13408
 BIGINT_Q_OFFSETBIGINT_Q_OFFSET 2 bigint_impl.h *< q module offset.
13409
 BIGINT_NUM_MODSBIGINT_NUM_MODS 3 bigint_impl.h *< The number of modulus constants used.
13410
 BIGINT_NUM_MODSBIGINT_NUM_MODS 1 bigint_impl.h 　
13411
 COMP_RADIXCOMP_RADIX 4294967296i64 bigint_impl.h 　
13412
 COMP_BIG_MSBCOMP_BIG_MSB 0x8000000000000000i64 bigint_impl.h 　
13413
 COMP_RADIXCOMP_RADIX 4294967296ULL bigint_impl.h *< Max component + 1
13414
 COMP_BIG_MSBCOMP_BIG_MSB 0x8000000000000000ULL bigint_impl.h *< (Max dbl comp + 1)/ 2
13415
 COMP_BIT_SIZECOMP_BIT_SIZE 32 bigint_impl.h *< Number of bits in a component.
13416
 COMP_BYTE_SIZECOMP_BYTE_SIZE 4 bigint_impl.h *< Number of bytes in a component.
13417
 COMP_NUM_NIBBLESCOMP_NUM_NIBBLES 8 bigint_impl.h *< Used For diagnostics only.
13418
 PERMANENTPERMANENT 0x7FFF55AA bigint_impl.h *< A magic number for permanents.
13419
 V1V1 v->comps[v->size-1] bigint_impl.h *< v1 for division
13420
 V2V2 v->comps[v->size-2] bigint_impl.h *< v2 for division
13421
 CONFIG_SSL_CERT_VERIFICATIONCONFIG_SSL_CERT_VERIFICATION 1 os_port.h 　
13422
 CONFIG_SSL_MAX_CERTSCONFIG_SSL_MAX_CERTS 1 os_port.h 　
13423
 CONFIG_X509_MAX_CA_CERTSCONFIG_X509_MAX_CA_CERTS 1 os_port.h 　
13424
 CONFIG_SSL_EXPIRY_TIMECONFIG_SSL_EXPIRY_TIME 24 os_port.h 　
13425
 CONFIG_SSL_ENABLE_CLIENTCONFIG_SSL_ENABLE_CLIENT 1 os_port.h 　
13426
 CONFIG_BIGINT_CLASSICALCONFIG_BIGINT_CLASSICAL 1 os_port.h 　
13427
 SELECT_SLAVESELECT_SLAVE 0 spi_bit.c 　
13428
 DESELECT_SLAVEDESELECT_SLAVE SPI_MODE_SSPOL spi_bit.c 　
13429
 SCSI_MAX_DUMMY_READ_CAPSCSI_MAX_DUMMY_READ_CAP 10 scsi.c 　
13430
 ISA_EXTRA_PROBE_ADDR_COUNTISA_EXTRA_PROBE_ADDR_COUNT ( sizeof ( isa_extra_probe_addrs ) / sizeof ( isa_extra_probe_addrs[0] ) ) isa.c 　
13431
 ISAPNP_CARD_ID_FMTISAPNP_CARD_ID_FMT "ID %04x:%04x (\"%s\") serial %x" isapnp.c 　
13432
 ISAPNP_DEV_ID_FMTISAPNP_DEV_ID_FMT "ID %04x:%04x (\"%s\")" isapnp.c 　
13433
 LINDA_SEND_BUF_TOGGLELINDA_SEND_BUF_TOGGLE 0x80 linda.c 　
13434
 LINDA_EPB_ALL_CHANNELSLINDA_EPB_ALL_CHANNELS 31 linda.c 　
13435
 LINDA_SERDES_PARAM_ENDLINDA_SERDES_PARAM_END { 0, 0, 0 } linda.c 　
13436
 ARBEL_NUM_PORTSARBEL_NUM_PORTS 2 arbel.h 　
13437
 ARBEL_PORT_BASEARBEL_PORT_BASE 1 arbel.h 　
13438
 ARBEL_PCI_CONFIG_BARARBEL_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0 arbel.h 　
13439
 ARBEL_PCI_CONFIG_BAR_SIZEARBEL_PCI_CONFIG_BAR_SIZE 0x100000 arbel.h 　
13440
 ARBEL_PCI_UAR_BARARBEL_PCI_UAR_BAR PCI_BASE_ADDRESS_2 arbel.h 　
13441
 ARBEL_PCI_UAR_IDXARBEL_PCI_UAR_IDX 1 arbel.h 　
13442
 ARBEL_PCI_UAR_SIZEARBEL_PCI_UAR_SIZE 0x1000 arbel.h 　
13443
 ARBEL_UAR_RES_NONEARBEL_UAR_RES_NONE 0x00 arbel.h 　
13444
 ARBEL_UAR_RES_CQ_CIARBEL_UAR_RES_CQ_CI 0x01 arbel.h 　
13445
 ARBEL_UAR_RES_CQ_ARMARBEL_UAR_RES_CQ_ARM 0x02 arbel.h 　
13446
 ARBEL_UAR_RES_SQARBEL_UAR_RES_SQ 0x03 arbel.h 　
13447
 ARBEL_UAR_RES_RQARBEL_UAR_RES_RQ 0x04 arbel.h 　
13448
 ARBEL_UAR_RES_GROUP_SEPARBEL_UAR_RES_GROUP_SEP 0x07 arbel.h 　
13449
 ARBEL_OPCODE_SENDARBEL_OPCODE_SEND 0x0a arbel.h 　
13450
 ARBEL_OPCODE_RECV_ERRORARBEL_OPCODE_RECV_ERROR 0xfe arbel.h 　
13451
 ARBEL_OPCODE_SEND_ERRORARBEL_OPCODE_SEND_ERROR 0xff arbel.h 　
13452
 ARBEL_HCR_QUERY_DEV_LIMARBEL_HCR_QUERY_DEV_LIM 0x0003 arbel.h 　
13453
 ARBEL_HCR_QUERY_FWARBEL_HCR_QUERY_FW 0x0004 arbel.h 　
13454
 ARBEL_HCR_INIT_HCAARBEL_HCR_INIT_HCA 0x0007 arbel.h 　
13455
 ARBEL_HCR_CLOSE_HCAARBEL_HCR_CLOSE_HCA 0x0008 arbel.h 　
13456
 ARBEL_HCR_INIT_IBARBEL_HCR_INIT_IB 0x0009 arbel.h 　
13457
 ARBEL_HCR_CLOSE_IBARBEL_HCR_CLOSE_IB 0x000a arbel.h 　
13458
 ARBEL_HCR_SW2HW_MPTARBEL_HCR_SW2HW_MPT 0x000d arbel.h 　
13459
 ARBEL_HCR_MAP_EQARBEL_HCR_MAP_EQ 0x0012 arbel.h 　
13460
 ARBEL_HCR_SW2HW_EQARBEL_HCR_SW2HW_EQ 0x0013 arbel.h 　
13461
 ARBEL_HCR_HW2SW_EQARBEL_HCR_HW2SW_EQ 0x0014 arbel.h 　
13462
 ARBEL_HCR_SW2HW_CQARBEL_HCR_SW2HW_CQ 0x0016 arbel.h 　
13463
 ARBEL_HCR_HW2SW_CQARBEL_HCR_HW2SW_CQ 0x0017 arbel.h 　
13464
 ARBEL_HCR_RST2INIT_QPEEARBEL_HCR_RST2INIT_QPEE 0x0019 arbel.h 　
13465
 ARBEL_HCR_INIT2RTR_QPEEARBEL_HCR_INIT2RTR_QPEE 0x001a arbel.h 　
13466
 ARBEL_HCR_RTR2RTS_QPEEARBEL_HCR_RTR2RTS_QPEE 0x001b arbel.h 　
13467
 ARBEL_HCR_RTS2RTS_QPEEARBEL_HCR_RTS2RTS_QPEE 0x001c arbel.h 　
13468
 ARBEL_HCR_2RST_QPEEARBEL_HCR_2RST_QPEE 0x0021 arbel.h 　
13469
 ARBEL_HCR_MAD_IFCARBEL_HCR_MAD_IFC 0x0024 arbel.h 　
13470
 ARBEL_HCR_READ_MGMARBEL_HCR_READ_MGM 0x0025 arbel.h 　
13471
 ARBEL_HCR_WRITE_MGMARBEL_HCR_WRITE_MGM 0x0026 arbel.h 　
13472
 ARBEL_HCR_MGID_HASHARBEL_HCR_MGID_HASH 0x0027 arbel.h 　
13473
 ARBEL_HCR_RUN_FWARBEL_HCR_RUN_FW 0x0ff6 arbel.h 　
13474
 ARBEL_HCR_DISABLE_LAMARBEL_HCR_DISABLE_LAM 0x0ff7 arbel.h 　
13475
 ARBEL_HCR_ENABLE_LAMARBEL_HCR_ENABLE_LAM 0x0ff8 arbel.h 　
13476
 ARBEL_HCR_UNMAP_ICMARBEL_HCR_UNMAP_ICM 0x0ff9 arbel.h 　
13477
 ARBEL_HCR_MAP_ICMARBEL_HCR_MAP_ICM 0x0ffa arbel.h 　
13478
 ARBEL_HCR_UNMAP_ICM_AUXARBEL_HCR_UNMAP_ICM_AUX 0x0ffb arbel.h 　
13479
 ARBEL_HCR_MAP_ICM_AUXARBEL_HCR_MAP_ICM_AUX 0x0ffc arbel.h 　
13480
 ARBEL_HCR_SET_ICM_SIZEARBEL_HCR_SET_ICM_SIZE 0x0ffd arbel.h 　
13481
 ARBEL_HCR_UNMAP_FAARBEL_HCR_UNMAP_FA 0x0ffe arbel.h 　
13482
 ARBEL_HCR_MAP_FAARBEL_HCR_MAP_FA 0x0fff arbel.h 　
13483
 ARBEL_ST_UDARBEL_ST_UD 0x03 arbel.h 　
13484
 ARBEL_MTU_2048ARBEL_MTU_2048 0x04 arbel.h 　
13485
 ARBEL_NO_EQARBEL_NO_EQ 64 arbel.h 　
13486
 ARBEL_INVALID_LKEYARBEL_INVALID_LKEY 0x00000100UL arbel.h 　
13487
 ARBEL_PAGE_SIZEARBEL_PAGE_SIZE 4096 arbel.h 　
13488
 ARBEL_DB_POST_SND_OFFSETARBEL_DB_POST_SND_OFFSET 0x10 arbel.h 　
13489
 ARBEL_QPEE_OPT_PARAM_QKEYARBEL_QPEE_OPT_PARAM_QKEY 0x00000020UL arbel.h 　
13490
 ARBEL_MAP_EQARBEL_MAP_EQ ( 0UL << 31 ) arbel.h 　
13491
 ARBEL_UNMAP_EQARBEL_UNMAP_EQ ( 1UL << 31 ) arbel.h 　
13492
 ARBEL_EV_PORT_STATE_CHANGEARBEL_EV_PORT_STATE_CHANGE 0x09 arbel.h 　
13493
 ARBEL_MAX_GATHERARBEL_MAX_GATHER 1 arbel.h 　
13494
 ARBEL_MAX_SCATTERARBEL_MAX_SCATTER 1 arbel.h 　
13495
 ARBEL_SEND_WQE_ALIGNARBEL_SEND_WQE_ALIGN 128 arbel.h 　
13496
 ARBEL_RECV_WQE_ALIGNARBEL_RECV_WQE_ALIGN 64 arbel.h 　
13497
 ARBEL_MAX_QPSARBEL_MAX_QPS 8 arbel.h 　
13498
 ARBEL_QPN_BASEARBEL_QPN_BASE 0x550000 arbel.h 　
13499
 ARBEL_MAX_CQSARBEL_MAX_CQS 8 arbel.h 　
13500
 ARBEL_MAX_EQSARBEL_MAX_EQS 64 arbel.h 　
13501
 ARBEL_NUM_EQESARBEL_NUM_EQES 4 arbel.h 　
13502
 ARBEL_GLOBAL_PDARBEL_GLOBAL_PD 0x123456 arbel.h 　
13503
 ARBEL_MKEY_PREFIXARBEL_MKEY_PREFIX 0x77000000UL arbel.h 　
13504
 ARBEL_HCR_BASEARBEL_HCR_BASE 0x80680 arbel.h 　
13505
 ARBEL_HCR_MAX_WAIT_MSARBEL_HCR_MAX_WAIT_MS 2000 arbel.h 　
13506
 ARBEL_MBOX_ALIGNARBEL_MBOX_ALIGN 4096 arbel.h 　
13507
 ARBEL_MBOX_SIZEARBEL_MBOX_SIZE 512 arbel.h 　
13508
 ARBEL_HCR_IN_MBOXARBEL_HCR_IN_MBOX 0x00001000UL arbel.h 　
13509
 ARBEL_HCR_OUT_MBOXARBEL_HCR_OUT_MBOX 0x00002000UL arbel.h 　
13510
 ARBEL_MAX_DOORBELL_RECORDSARBEL_MAX_DOORBELL_RECORDS 512 arbel.h 　
13511
 ARBEL_GROUP_SEPARATOR_DOORBELLARBEL_GROUP_SEPARATOR_DOORBELL ( ARBEL_MAX_CQS + ARBEL_MAX_QPS ) arbel.h 　
13512
 HERMON_MAX_PORTSHERMON_MAX_PORTS 2 hermon.h 　
13513
 HERMON_PORT_BASEHERMON_PORT_BASE 1 hermon.h 　
13514
 HERMON_PCI_CONFIG_BARHERMON_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0 hermon.h 　
13515
 HERMON_PCI_CONFIG_BAR_SIZEHERMON_PCI_CONFIG_BAR_SIZE 0x100000 hermon.h 　
13516
 HERMON_PCI_UAR_BARHERMON_PCI_UAR_BAR PCI_BASE_ADDRESS_2 hermon.h 　
13517
 HERMON_RESET_OFFSETHERMON_RESET_OFFSET 0x0f0010 hermon.h 　
13518
 HERMON_RESET_MAGICHERMON_RESET_MAGIC 0x01000000UL hermon.h 　
13519
 HERMON_RESET_WAIT_TIME_MSHERMON_RESET_WAIT_TIME_MS 1000 hermon.h 　
13520
 HERMON_OPCODE_NOPHERMON_OPCODE_NOP 0x00 hermon.h 　
13521
 HERMON_OPCODE_SENDHERMON_OPCODE_SEND 0x0a hermon.h 　
13522
 HERMON_OPCODE_RECV_ERRORHERMON_OPCODE_RECV_ERROR 0xfe hermon.h 　
13523
 HERMON_OPCODE_SEND_ERRORHERMON_OPCODE_SEND_ERROR 0xff hermon.h 　
13524
 HERMON_HCR_QUERY_DEV_CAPHERMON_HCR_QUERY_DEV_CAP 0x0003 hermon.h 　
13525
 HERMON_HCR_QUERY_FWHERMON_HCR_QUERY_FW 0x0004 hermon.h 　
13526
 HERMON_HCR_INIT_HCAHERMON_HCR_INIT_HCA 0x0007 hermon.h 　
13527
 HERMON_HCR_CLOSE_HCAHERMON_HCR_CLOSE_HCA 0x0008 hermon.h 　
13528
 HERMON_HCR_INIT_PORTHERMON_HCR_INIT_PORT 0x0009 hermon.h 　
13529
 HERMON_HCR_CLOSE_PORTHERMON_HCR_CLOSE_PORT 0x000a hermon.h 　
13530
 HERMON_HCR_SW2HW_MPTHERMON_HCR_SW2HW_MPT 0x000d hermon.h 　
13531
 HERMON_HCR_WRITE_MTTHERMON_HCR_WRITE_MTT 0x0011 hermon.h 　
13532
 HERMON_HCR_MAP_EQHERMON_HCR_MAP_EQ 0x0012 hermon.h 　
13533
 HERMON_HCR_SW2HW_EQHERMON_HCR_SW2HW_EQ 0x0013 hermon.h 　
13534
 HERMON_HCR_HW2SW_EQHERMON_HCR_HW2SW_EQ 0x0014 hermon.h 　
13535
 HERMON_HCR_QUERY_EQHERMON_HCR_QUERY_EQ 0x0015 hermon.h 　
13536
 HERMON_HCR_SW2HW_CQHERMON_HCR_SW2HW_CQ 0x0016 hermon.h 　
13537
 HERMON_HCR_HW2SW_CQHERMON_HCR_HW2SW_CQ 0x0017 hermon.h 　
13538
 HERMON_HCR_RST2INIT_QPHERMON_HCR_RST2INIT_QP 0x0019 hermon.h 　
13539
 HERMON_HCR_INIT2RTR_QPHERMON_HCR_INIT2RTR_QP 0x001a hermon.h 　
13540
 HERMON_HCR_RTR2RTS_QPHERMON_HCR_RTR2RTS_QP 0x001b hermon.h 　
13541
 HERMON_HCR_RTS2RTS_QPHERMON_HCR_RTS2RTS_QP 0x001c hermon.h 　
13542
 HERMON_HCR_2RST_QPHERMON_HCR_2RST_QP 0x0021 hermon.h 　
13543
 HERMON_HCR_QUERY_QPHERMON_HCR_QUERY_QP 0x0022 hermon.h 　
13544
 HERMON_HCR_CONF_SPECIAL_QPHERMON_HCR_CONF_SPECIAL_QP 0x0023 hermon.h 　
13545
 HERMON_HCR_MAD_IFCHERMON_HCR_MAD_IFC 0x0024 hermon.h 　
13546
 HERMON_HCR_READ_MCGHERMON_HCR_READ_MCG 0x0025 hermon.h 　
13547
 HERMON_HCR_WRITE_MCGHERMON_HCR_WRITE_MCG 0x0026 hermon.h 　
13548
 HERMON_HCR_MGID_HASHHERMON_HCR_MGID_HASH 0x0027 hermon.h 　
13549
 HERMON_HCR_SENSE_PORTHERMON_HCR_SENSE_PORT 0x004d hermon.h 　
13550
 HERMON_HCR_RUN_FWHERMON_HCR_RUN_FW 0x0ff6 hermon.h 　
13551
 HERMON_HCR_DISABLE_LAMHERMON_HCR_DISABLE_LAM 0x0ff7 hermon.h 　
13552
 HERMON_HCR_ENABLE_LAMHERMON_HCR_ENABLE_LAM 0x0ff8 hermon.h 　
13553
 HERMON_HCR_UNMAP_ICMHERMON_HCR_UNMAP_ICM 0x0ff9 hermon.h 　
13554
 HERMON_HCR_MAP_ICMHERMON_HCR_MAP_ICM 0x0ffa hermon.h 　
13555
 HERMON_HCR_UNMAP_ICM_AUXHERMON_HCR_UNMAP_ICM_AUX 0x0ffb hermon.h 　
13556
 HERMON_HCR_MAP_ICM_AUXHERMON_HCR_MAP_ICM_AUX 0x0ffc hermon.h 　
13557
 HERMON_HCR_SET_ICM_SIZEHERMON_HCR_SET_ICM_SIZE 0x0ffd hermon.h 　
13558
 HERMON_HCR_UNMAP_FAHERMON_HCR_UNMAP_FA 0x0ffe hermon.h 　
13559
 HERMON_HCR_MAP_FAHERMON_HCR_MAP_FA 0x0fff hermon.h 　
13560
 HERMON_ST_RCHERMON_ST_RC 0x00 hermon.h 　
13561
 HERMON_ST_UDHERMON_ST_UD 0x03 hermon.h 　
13562
 HERMON_ST_MLXHERMON_ST_MLX 0x07 hermon.h 　
13563
 HERMON_MTU_2048HERMON_MTU_2048 0x04 hermon.h 　
13564
 HERMON_INVALID_LKEYHERMON_INVALID_LKEY 0x00000100UL hermon.h 　
13565
 HERMON_PAGE_SIZEHERMON_PAGE_SIZE 4096 hermon.h 　
13566
 HERMON_DB_POST_SND_OFFSETHERMON_DB_POST_SND_OFFSET 0x14 hermon.h 　
13567
 HERMON_QP_OPT_PARAM_PM_STATEHERMON_QP_OPT_PARAM_PM_STATE 0x00000400UL hermon.h 　
13568
 HERMON_QP_OPT_PARAM_QKEYHERMON_QP_OPT_PARAM_QKEY 0x00000020UL hermon.h 　
13569
 HERMON_QP_OPT_PARAM_ALT_PATHHERMON_QP_OPT_PARAM_ALT_PATH 0x00000001UL hermon.h 　
13570
 HERMON_MAP_EQHERMON_MAP_EQ ( 0UL << 31 ) hermon.h 　
13571
 HERMON_UNMAP_EQHERMON_UNMAP_EQ ( 1UL << 31 ) hermon.h 　
13572
 HERMON_EV_PORT_STATE_CHANGEHERMON_EV_PORT_STATE_CHANGE 0x09 hermon.h 　
13573
 HERMON_SCHED_QP0HERMON_SCHED_QP0 0x3f hermon.h 　
13574
 HERMON_SCHED_DEFAULTHERMON_SCHED_DEFAULT 0x83 hermon.h 　
13575
 HERMON_PM_STATE_ARMEDHERMON_PM_STATE_ARMED 0x00 hermon.h 　
13576
 HERMON_PM_STATE_REARMHERMON_PM_STATE_REARM 0x01 hermon.h 　
13577
 HERMON_PM_STATE_MIGRATEDHERMON_PM_STATE_MIGRATED 0x03 hermon.h 　
13578
 HERMON_RETRY_MAXHERMON_RETRY_MAX 0x07 hermon.h 　
13579
 HERMON_PORT_TYPE_IBHERMON_PORT_TYPE_IB 1 hermon.h 　
13580
 HERMON_MAX_GATHERHERMON_MAX_GATHER 2 hermon.h 　
13581
 HERMON_MAX_SCATTERHERMON_MAX_SCATTER 1 hermon.h 　
13582
 HERMON_CMPT_MAX_ENTRIESHERMON_CMPT_MAX_ENTRIES ( 1 << 24 ) hermon.h 　
13583
 HERMON_UAR_NON_EQ_PAGEHERMON_UAR_NON_EQ_PAGE 128 hermon.h 　
13584
 HERMON_MAX_MTTSHERMON_MAX_MTTS 64 hermon.h 　
13585
 HERMON_SEND_WQE_ALIGNHERMON_SEND_WQE_ALIGN 128 hermon.h 　
13586
 HERMON_RECV_WQE_ALIGNHERMON_RECV_WQE_ALIGN 16 hermon.h 　
13587
 HERMON_NUM_SPECIAL_QPSHERMON_NUM_SPECIAL_QPS 8 hermon.h 　
13588
 HERMON_RSVD_SPECIAL_QPSHERMON_RSVD_SPECIAL_QPS ( ( HERMON_NUM_SPECIAL_QPS << 1 ) - 1 ) hermon.h 　
13589
 HERMON_MAX_QPSHERMON_MAX_QPS 8 hermon.h 　
13590
 HERMON_QPN_RANDOM_MASKHERMON_QPN_RANDOM_MASK 0xfff000 hermon.h 　
13591
 HERMON_MAX_CQSHERMON_MAX_CQS 8 hermon.h 　
13592
 HERMON_MAX_EQSHERMON_MAX_EQS 8 hermon.h 　
13593
 HERMON_NUM_EQESHERMON_NUM_EQES 4 hermon.h 　
13594
 HERMON_GLOBAL_PDHERMON_GLOBAL_PD 0x123456 hermon.h 　
13595
 HERMON_MKEY_PREFIXHERMON_MKEY_PREFIX 0x77000000UL hermon.h 　
13596
 HERMON_HCR_BASEHERMON_HCR_BASE 0x80680 hermon.h 　
13597
 HERMON_HCR_MAX_WAIT_MSHERMON_HCR_MAX_WAIT_MS 2000 hermon.h 　
13598
 HERMON_MBOX_ALIGNHERMON_MBOX_ALIGN 4096 hermon.h 　
13599
 HERMON_MBOX_SIZEHERMON_MBOX_SIZE 512 hermon.h 　
13600
 HERMON_HCR_IN_MBOXHERMON_HCR_IN_MBOX 0x00001000UL hermon.h 　
13601
 HERMON_HCR_OUT_MBOXHERMON_HCR_OUT_MBOX 0x00002000UL hermon.h 　
13602
 LINDA_SENDBUFAVAIL_ALIGNLINDA_SENDBUFAVAIL_ALIGN 64 linda.h 　
13603
 LINDA_BAR0_SIZELINDA_BAR0_SIZE 0x400000 linda.h 　
13604
 LINDA_GPIO_SCLLINDA_GPIO_SCL 0 linda.h 　
13605
 LINDA_GPIO_SDALINDA_GPIO_SDA 1 linda.h 　
13606
 LINDA_EEPROM_GUID_OFFSETLINDA_EEPROM_GUID_OFFSET 3 linda.h 　
13607
 LINDA_EEPROM_GUID_SIZELINDA_EEPROM_GUID_SIZE 8 linda.h 　
13608
 LINDA_EEPROM_SERIAL_OFFSETLINDA_EEPROM_SERIAL_OFFSET 12 linda.h 　
13609
 LINDA_EEPROM_SERIAL_SIZELINDA_EEPROM_SERIAL_SIZE 12 linda.h 　
13610
 LINDA_MAX_SEND_BUFSLINDA_MAX_SEND_BUFS 32 linda.h 　
13611
 LINDA_SEND_BUF_SIZELINDA_SEND_BUF_SIZE 4096 linda.h 　
13612
 LINDA_NUM_CONTEXTSLINDA_NUM_CONTEXTS 5 linda.h 　
13613
 LINDA_EAGER_ARRAY_SIZE_5CTX_0LINDA_EAGER_ARRAY_SIZE_5CTX_0 2048 linda.h 　
13614
 LINDA_EAGER_ARRAY_SIZE_5CTX_OTHLINDA_EAGER_ARRAY_SIZE_5CTX_OTH 4096 linda.h 　
13615
 LINDA_EAGER_ARRAY_SIZE_9CTX_0LINDA_EAGER_ARRAY_SIZE_9CTX_0 2048 linda.h 　
13616
 LINDA_EAGER_ARRAY_SIZE_9CTX_OTHLINDA_EAGER_ARRAY_SIZE_9CTX_OTH 2048 linda.h 　
13617
 LINDA_EAGER_ARRAY_SIZE_17CTX_0LINDA_EAGER_ARRAY_SIZE_17CTX_0 2048 linda.h 　
13618
 LINDA_EAGER_ARRAY_SIZE_17CTX_OTLINDA_EAGER_ARRAY_SIZE_17CTX_OT 1024 linda.h 　
13619
 LINDA_EAGER_BUFFER_ALIGNLINDA_EAGER_BUFFER_ALIGN 2048 linda.h 　
13620
 LINDA_RECV_HEADER_COUNTLINDA_RECV_HEADER_COUNT 8 linda.h 　
13621
 LINDA_RECV_HEADER_SIZELINDA_RECV_HEADER_SIZE 96 linda.h 　
13622
 LINDA_RECV_HEADERS_SIZELINDA_RECV_HEADERS_SIZE ( LINDA_RECV_HEADER_SIZE * LINDA_RECV_HEADER_COUNT ) linda.h 　
13623
 LINDA_RECV_HEADERS_ALIGNLINDA_RECV_HEADERS_ALIGN 64 linda.h 　
13624
 LINDA_RECV_PAYLOAD_SIZELINDA_RECV_PAYLOAD_SIZE 2048 linda.h 　
13625
 LINDA_QP_IDETHLINDA_QP_IDETH 0xdead0 linda.h 　
13626
 LINDA_EPB_REQUEST_MAX_WAIT_USLINDA_EPB_REQUEST_MAX_WAIT_US 500 linda.h 　
13627
 LINDA_EPB_XACT_MAX_WAIT_USLINDA_EPB_XACT_MAX_WAIT_US 500 linda.h 　
13628
 LINDA_EPB_CS_SERDESLINDA_EPB_CS_SERDES 1 linda.h 　
13629
 LINDA_EPB_CS_UCLINDA_EPB_CS_UC 2 linda.h 　
13630
 LINDA_EPB_WRITELINDA_EPB_WRITE 0 linda.h 　
13631
 LINDA_EPB_READLINDA_EPB_READ 1 linda.h 　
13632
 LINDA_EPB_UC_CHANNELLINDA_EPB_UC_CHANNEL 6 linda.h 　
13633
 LINDA_EPB_UC_CTLLINDA_EPB_UC_CTL LINDA_EPB_UC_LOC ( 0 ) linda.h 　
13634
 LINDA_EPB_UC_CTL_WRITELINDA_EPB_UC_CTL_WRITE 1 linda.h 　
13635
 LINDA_EPB_UC_CTL_READLINDA_EPB_UC_CTL_READ 2 linda.h 　
13636
 LINDA_EPB_UC_ADDR_LOLINDA_EPB_UC_ADDR_LO LINDA_EPB_UC_LOC ( 2 ) linda.h 　
13637
 LINDA_EPB_UC_ADDR_HILINDA_EPB_UC_ADDR_HI LINDA_EPB_UC_LOC ( 3 ) linda.h 　
13638
 LINDA_EPB_UC_DATALINDA_EPB_UC_DATA LINDA_EPB_UC_LOC ( 4 ) linda.h 　
13639
 LINDA_EPB_UC_CHUNK_SIZELINDA_EPB_UC_CHUNK_SIZE 64 linda.h 　
13640
 LINDA_TRIM_DONE_MAX_WAIT_MSLINDA_TRIM_DONE_MAX_WAIT_MS 1000 linda.h 　
13641
 LINDA_LINK_STATE_MAX_WAIT_USLINDA_LINK_STATE_MAX_WAIT_US 20 linda.h 　
13642
 QIB_7220_Revision_offsetQIB_7220_Revision_offset 0x00000000UL qib_7220_regs.h 　
13643
 QIB_7220_Control_offsetQIB_7220_Control_offset 0x00000008UL qib_7220_regs.h 　
13644
 QIB_7220_PageAlign_offsetQIB_7220_PageAlign_offset 0x00000010UL qib_7220_regs.h 　
13645
 QIB_7220_PortCnt_offsetQIB_7220_PortCnt_offset 0x00000018UL qib_7220_regs.h 　
13646
 QIB_7220_DbgPortSel_offsetQIB_7220_DbgPortSel_offset 0x00000020UL qib_7220_regs.h 　
13647
 QIB_7220_DebugSigsIntSel_offsetQIB_7220_DebugSigsIntSel_offset 0x00000028UL qib_7220_regs.h 　
13648
 QIB_7220_SendRegBase_offsetQIB_7220_SendRegBase_offset 0x00000030UL qib_7220_regs.h 　
13649
 QIB_7220_UserRegBase_offsetQIB_7220_UserRegBase_offset 0x00000038UL qib_7220_regs.h 　
13650
 QIB_7220_CntrRegBase_offsetQIB_7220_CntrRegBase_offset 0x00000040UL qib_7220_regs.h 　
13651
 QIB_7220_Scratch_offsetQIB_7220_Scratch_offset 0x00000048UL qib_7220_regs.h 　
13652
 QIB_7220_REG_000050_offsetQIB_7220_REG_000050_offset 0x00000050UL qib_7220_regs.h 　
13653
 QIB_7220_IntBlocked_offsetQIB_7220_IntBlocked_offset 0x00000060UL qib_7220_regs.h 　
13654
 QIB_7220_IntMask_offsetQIB_7220_IntMask_offset 0x00000068UL qib_7220_regs.h 　
13655
 QIB_7220_IntStatus_offsetQIB_7220_IntStatus_offset 0x00000070UL qib_7220_regs.h 　
13656
 QIB_7220_IntClear_offsetQIB_7220_IntClear_offset 0x00000078UL qib_7220_regs.h 　
13657
 QIB_7220_ErrMask_offsetQIB_7220_ErrMask_offset 0x00000080UL qib_7220_regs.h 　
13658
 QIB_7220_ErrStatus_offsetQIB_7220_ErrStatus_offset 0x00000088UL qib_7220_regs.h 　
13659
 QIB_7220_ErrClear_offsetQIB_7220_ErrClear_offset 0x00000090UL qib_7220_regs.h 　
13660
 QIB_7220_HwErrMask_offsetQIB_7220_HwErrMask_offset 0x00000098UL qib_7220_regs.h 　
13661
 QIB_7220_HwErrStatus_offsetQIB_7220_HwErrStatus_offset 0x000000a0UL qib_7220_regs.h 　
13662
 QIB_7220_HwErrClear_offsetQIB_7220_HwErrClear_offset 0x000000a8UL qib_7220_regs.h 　
13663
 QIB_7220_HwDiagCtrl_offsetQIB_7220_HwDiagCtrl_offset 0x000000b0UL qib_7220_regs.h 　
13664
 QIB_7220_REG_0000B8_offsetQIB_7220_REG_0000B8_offset 0x000000b8UL qib_7220_regs.h 　
13665
 QIB_7220_IBCStatus_offsetQIB_7220_IBCStatus_offset 0x000000c0UL qib_7220_regs.h 　
13666
 QIB_7220_IBCCtrl_offsetQIB_7220_IBCCtrl_offset 0x000000c8UL qib_7220_regs.h 　
13667
 QIB_7220_EXTStatus_offsetQIB_7220_EXTStatus_offset 0x000000d0UL qib_7220_regs.h 　
13668
 QIB_7220_EXTCtrl_offsetQIB_7220_EXTCtrl_offset 0x000000d8UL qib_7220_regs.h 　
13669
 QIB_7220_GPIOOut_offsetQIB_7220_GPIOOut_offset 0x000000e0UL qib_7220_regs.h 　
13670
 QIB_7220_GPIOMask_offsetQIB_7220_GPIOMask_offset 0x000000e8UL qib_7220_regs.h 　
13671
 QIB_7220_GPIOStatus_offsetQIB_7220_GPIOStatus_offset 0x000000f0UL qib_7220_regs.h 　
13672
 QIB_7220_GPIOClear_offsetQIB_7220_GPIOClear_offset 0x000000f8UL qib_7220_regs.h 　
13673
 QIB_7220_RcvCtrl_offsetQIB_7220_RcvCtrl_offset 0x00000100UL qib_7220_regs.h 　
13674
 QIB_7220_RcvBTHQP_offsetQIB_7220_RcvBTHQP_offset 0x00000108UL qib_7220_regs.h 　
13675
 QIB_7220_RcvHdrSize_offsetQIB_7220_RcvHdrSize_offset 0x00000110UL qib_7220_regs.h 　
13676
 QIB_7220_RcvHdrCnt_offsetQIB_7220_RcvHdrCnt_offset 0x00000118UL qib_7220_regs.h 　
13677
 QIB_7220_RcvHdrEntSize_offsetQIB_7220_RcvHdrEntSize_offset 0x00000120UL qib_7220_regs.h 　
13678
 QIB_7220_RcvTIDBase_offsetQIB_7220_RcvTIDBase_offset 0x00000128UL qib_7220_regs.h 　
13679
 QIB_7220_RcvTIDCnt_offsetQIB_7220_RcvTIDCnt_offset 0x00000130UL qib_7220_regs.h 　
13680
 QIB_7220_RcvEgrBase_offsetQIB_7220_RcvEgrBase_offset 0x00000138UL qib_7220_regs.h 　
13681
 QIB_7220_RcvEgrCnt_offsetQIB_7220_RcvEgrCnt_offset 0x00000140UL qib_7220_regs.h 　
13682
 QIB_7220_RcvBufBase_offsetQIB_7220_RcvBufBase_offset 0x00000148UL qib_7220_regs.h 　
13683
 QIB_7220_RcvBufSize_offsetQIB_7220_RcvBufSize_offset 0x00000150UL qib_7220_regs.h 　
13684
 QIB_7220_RxIntMemBase_offsetQIB_7220_RxIntMemBase_offset 0x00000158UL qib_7220_regs.h 　
13685
 QIB_7220_RxIntMemSize_offsetQIB_7220_RxIntMemSize_offset 0x00000160UL qib_7220_regs.h 　
13686
 QIB_7220_RcvPartitionKey_offsetQIB_7220_RcvPartitionKey_offset 0x00000168UL qib_7220_regs.h 　
13687
 QIB_7220_RcvQPMulticastPort_offQIB_7220_RcvQPMulticastPort_off 0x00000170UL qib_7220_regs.h 　
13688
 QIB_7220_RcvPktLEDCnt_offsetQIB_7220_RcvPktLEDCnt_offset 0x00000178UL qib_7220_regs.h 　
13689
 QIB_7220_IBCDDRCtrl_offsetQIB_7220_IBCDDRCtrl_offset 0x00000180UL qib_7220_regs.h 　
13690
 QIB_7220_HRTBT_GUID_offsetQIB_7220_HRTBT_GUID_offset 0x00000188UL qib_7220_regs.h 　
13691
 QIB_7220_IB_SDTEST_IF_TX_offsetQIB_7220_IB_SDTEST_IF_TX_offset 0x00000190UL qib_7220_regs.h 　
13692
 QIB_7220_IB_SDTEST_IF_RX_offsetQIB_7220_IB_SDTEST_IF_RX_offset 0x00000198UL qib_7220_regs.h 　
13693
 QIB_7220_IBCDDRCtrl2_offsetQIB_7220_IBCDDRCtrl2_offset 0x000001a0UL qib_7220_regs.h 　
13694
 QIB_7220_IBCDDRStatus_offsetQIB_7220_IBCDDRStatus_offset 0x000001a8UL qib_7220_regs.h 　
13695
 QIB_7220_JIntReload_offsetQIB_7220_JIntReload_offset 0x000001b0UL qib_7220_regs.h 　
13696
 QIB_7220_IBNCModeCtrl_offsetQIB_7220_IBNCModeCtrl_offset 0x000001b8UL qib_7220_regs.h 　
13697
 QIB_7220_SendCtrl_offsetQIB_7220_SendCtrl_offset 0x000001c0UL qib_7220_regs.h 　
13698
 QIB_7220_SendBufBase_offsetQIB_7220_SendBufBase_offset 0x000001c8UL qib_7220_regs.h 　
13699
 QIB_7220_SendBufSize_offsetQIB_7220_SendBufSize_offset 0x000001d0UL qib_7220_regs.h 　
13700
 QIB_7220_SendBufCnt_offsetQIB_7220_SendBufCnt_offset 0x000001d8UL qib_7220_regs.h 　
13701
 QIB_7220_SendBufAvailAddr_offseQIB_7220_SendBufAvailAddr_offse 0x000001e0UL qib_7220_regs.h 　
13702
 QIB_7220_TxIntMemBase_offsetQIB_7220_TxIntMemBase_offset 0x000001e8UL qib_7220_regs.h 　
13703
 QIB_7220_TxIntMemSize_offsetQIB_7220_TxIntMemSize_offset 0x000001f0UL qib_7220_regs.h 　
13704
 QIB_7220_SendDmaBase_offsetQIB_7220_SendDmaBase_offset 0x000001f8UL qib_7220_regs.h 　
13705
 QIB_7220_SendDmaLenGen_offsetQIB_7220_SendDmaLenGen_offset 0x00000200UL qib_7220_regs.h 　
13706
 QIB_7220_SendDmaTail_offsetQIB_7220_SendDmaTail_offset 0x00000208UL qib_7220_regs.h 　
13707
 QIB_7220_SendDmaHead_offsetQIB_7220_SendDmaHead_offset 0x00000210UL qib_7220_regs.h 　
13708
 QIB_7220_SendDmaHeadAddr_offsetQIB_7220_SendDmaHeadAddr_offset 0x00000218UL qib_7220_regs.h 　
13709
 QIB_7220_SendDmaBufMask0_offsetQIB_7220_SendDmaBufMask0_offset 0x00000220UL qib_7220_regs.h 　
13710
 QIB_7220_SendDmaStatus_offsetQIB_7220_SendDmaStatus_offset 0x00000238UL qib_7220_regs.h 　
13711
 QIB_7220_SendBufErr0_offsetQIB_7220_SendBufErr0_offset 0x00000240UL qib_7220_regs.h 　
13712
 QIB_7220_REG_000258_offsetQIB_7220_REG_000258_offset 0x00000258UL qib_7220_regs.h 　
13713
 QIB_7220_AvailUpdCount_offsetQIB_7220_AvailUpdCount_offset 0x00000268UL qib_7220_regs.h 　
13714
 QIB_7220_RcvHdrAddr0_offsetQIB_7220_RcvHdrAddr0_offset 0x00000270UL qib_7220_regs.h 　
13715
 QIB_7220_REG_0002F8_offsetQIB_7220_REG_0002F8_offset 0x000002f8UL qib_7220_regs.h 　
13716
 QIB_7220_RcvHdrTailAddr0_offsetQIB_7220_RcvHdrTailAddr0_offset 0x00000300UL qib_7220_regs.h 　
13717
 QIB_7220_REG_000388_offsetQIB_7220_REG_000388_offset 0x00000388UL qib_7220_regs.h 　
13718
 QIB_7220_ibsd_epb_access_ctrl_oQIB_7220_ibsd_epb_access_ctrl_o 0x000003c0UL qib_7220_regs.h 　
13719
 QIB_7220_ibsd_epb_transaction_rQIB_7220_ibsd_epb_transaction_r 0x000003c8UL qib_7220_regs.h 　
13720
 QIB_7220_REG_0003D0_offsetQIB_7220_REG_0003D0_offset 0x000003d0UL qib_7220_regs.h 　
13721
 QIB_7220_XGXSCfg_offsetQIB_7220_XGXSCfg_offset 0x000003d8UL qib_7220_regs.h 　
13722
 QIB_7220_IBSerDesCtrl_offsetQIB_7220_IBSerDesCtrl_offset 0x000003e0UL qib_7220_regs.h 　
13723
 QIB_7220_EEPCtlStat_offsetQIB_7220_EEPCtlStat_offset 0x000003e8UL qib_7220_regs.h 　
13724
 QIB_7220_EEPAddrCmd_offsetQIB_7220_EEPAddrCmd_offset 0x000003f0UL qib_7220_regs.h 　
13725
 QIB_7220_EEPData_offsetQIB_7220_EEPData_offset 0x000003f8UL qib_7220_regs.h 　
13726
 QIB_7220_pciesd_epb_access_ctrlQIB_7220_pciesd_epb_access_ctrl 0x00000400UL qib_7220_regs.h 　
13727
 QIB_7220_pciesd_epb_transactionQIB_7220_pciesd_epb_transaction 0x00000408UL qib_7220_regs.h 　
13728
 QIB_7220_efuse_control_reg_offsQIB_7220_efuse_control_reg_offs 0x00000410UL qib_7220_regs.h 　
13729
 QIB_7220_efuse_rddata0_reg_offsQIB_7220_efuse_rddata0_reg_offs 0x00000418UL qib_7220_regs.h 　
13730
 QIB_7220_procmon_register_offseQIB_7220_procmon_register_offse 0x00000438UL qib_7220_regs.h 　
13731
 QIB_7220_PcieRbufTestReg0_offseQIB_7220_PcieRbufTestReg0_offse 0x00000440UL qib_7220_regs.h 　
13732
 QIB_7220_PcieRBufTestReg1_offseQIB_7220_PcieRBufTestReg1_offse 0x00000448UL qib_7220_regs.h 　
13733
 QIB_7220_SPC_JTAG_ACCESS_REG_ofQIB_7220_SPC_JTAG_ACCESS_REG_of 0x00000460UL qib_7220_regs.h 　
13734
 QIB_7220_LAControlReg_offsetQIB_7220_LAControlReg_offset 0x00000468UL qib_7220_regs.h 　
13735
 QIB_7220_GPIODebugSelReg_offsetQIB_7220_GPIODebugSelReg_offset 0x00000470UL qib_7220_regs.h 　
13736
 QIB_7220_DebugPortValueReg_offsQIB_7220_DebugPortValueReg_offs 0x00000478UL qib_7220_regs.h 　
13737
 QIB_7220_SendDmaBufUsed0_offsetQIB_7220_SendDmaBufUsed0_offset 0x00000480UL qib_7220_regs.h 　
13738
 QIB_7220_SendDmaReqTagUsed_offsQIB_7220_SendDmaReqTagUsed_offs 0x00000498UL qib_7220_regs.h 　
13739
 QIB_7220_efuse_pgm_data0_offsetQIB_7220_efuse_pgm_data0_offset 0x000004a0UL qib_7220_regs.h 　
13740
 QIB_7220_MEM_0004B0_offsetQIB_7220_MEM_0004B0_offset 0x000004b0UL qib_7220_regs.h 　
13741
 QIB_7220_SerDes_DDSRXEQ0_offsetQIB_7220_SerDes_DDSRXEQ0_offset 0x00000500UL qib_7220_regs.h 　
13742
 QIB_7220_MEM_0005F0_offsetQIB_7220_MEM_0005F0_offset 0x000005f0UL qib_7220_regs.h 　
13743
 QIB_7220_LAMemory_offsetQIB_7220_LAMemory_offset 0x00000600UL qib_7220_regs.h 　
13744
 QIB_7220_MEM_0007F0_offsetQIB_7220_MEM_0007F0_offset 0x000007f0UL qib_7220_regs.h 　
13745
 QIB_7220_SendBufAvail0_offsetQIB_7220_SendBufAvail0_offset 0x00001000UL qib_7220_regs.h 　
13746
 QIB_7220_MEM_001028_offsetQIB_7220_MEM_001028_offset 0x00001028UL qib_7220_regs.h 　
13747
 QIB_7220_LBIntCnt_offsetQIB_7220_LBIntCnt_offset 0x00013000UL qib_7220_regs.h 　
13748
 QIB_7220_LBFlowStallCnt_offsetQIB_7220_LBFlowStallCnt_offset 0x00013008UL qib_7220_regs.h 　
13749
 QIB_7220_TxSDmaDescCnt_offsetQIB_7220_TxSDmaDescCnt_offset 0x00013010UL qib_7220_regs.h 　
13750
 QIB_7220_TxUnsupVLErrCnt_offsetQIB_7220_TxUnsupVLErrCnt_offset 0x00013018UL qib_7220_regs.h 　
13751
 QIB_7220_TxDataPktCnt_offsetQIB_7220_TxDataPktCnt_offset 0x00013020UL qib_7220_regs.h 　
13752
 QIB_7220_TxFlowPktCnt_offsetQIB_7220_TxFlowPktCnt_offset 0x00013028UL qib_7220_regs.h 　
13753
 QIB_7220_TxDwordCnt_offsetQIB_7220_TxDwordCnt_offset 0x00013030UL qib_7220_regs.h 　
13754
 QIB_7220_TxLenErrCnt_offsetQIB_7220_TxLenErrCnt_offset 0x00013038UL qib_7220_regs.h 　
13755
 QIB_7220_TxMaxMinLenErrCnt_offsQIB_7220_TxMaxMinLenErrCnt_offs 0x00013040UL qib_7220_regs.h 　
13756
 QIB_7220_TxUnderrunCnt_offsetQIB_7220_TxUnderrunCnt_offset 0x00013048UL qib_7220_regs.h 　
13757
 QIB_7220_TxFlowStallCnt_offsetQIB_7220_TxFlowStallCnt_offset 0x00013050UL qib_7220_regs.h 　
13758
 QIB_7220_TxDroppedPktCnt_offsetQIB_7220_TxDroppedPktCnt_offset 0x00013058UL qib_7220_regs.h 　
13759
 QIB_7220_RxDroppedPktCnt_offsetQIB_7220_RxDroppedPktCnt_offset 0x00013060UL qib_7220_regs.h 　
13760
 QIB_7220_RxDataPktCnt_offsetQIB_7220_RxDataPktCnt_offset 0x00013068UL qib_7220_regs.h 　
13761
 QIB_7220_RxFlowPktCnt_offsetQIB_7220_RxFlowPktCnt_offset 0x00013070UL qib_7220_regs.h 　
13762
 QIB_7220_RxDwordCnt_offsetQIB_7220_RxDwordCnt_offset 0x00013078UL qib_7220_regs.h 　
13763
 QIB_7220_RxLenErrCnt_offsetQIB_7220_RxLenErrCnt_offset 0x00013080UL qib_7220_regs.h 　
13764
 QIB_7220_RxMaxMinLenErrCnt_offsQIB_7220_RxMaxMinLenErrCnt_offs 0x00013088UL qib_7220_regs.h 　
13765
 QIB_7220_RxICRCErrCnt_offsetQIB_7220_RxICRCErrCnt_offset 0x00013090UL qib_7220_regs.h 　
13766
 QIB_7220_RxVCRCErrCnt_offsetQIB_7220_RxVCRCErrCnt_offset 0x00013098UL qib_7220_regs.h 　
13767
 QIB_7220_RxFlowCtrlViolCnt_offsQIB_7220_RxFlowCtrlViolCnt_offs 0x000130a0UL qib_7220_regs.h 　
13768
 QIB_7220_RxVersionErrCnt_offsetQIB_7220_RxVersionErrCnt_offset 0x000130a8UL qib_7220_regs.h 　
13769
 QIB_7220_RxLinkMalformCnt_offseQIB_7220_RxLinkMalformCnt_offse 0x000130b0UL qib_7220_regs.h 　
13770
 QIB_7220_RxEBPCnt_offsetQIB_7220_RxEBPCnt_offset 0x000130b8UL qib_7220_regs.h 　
13771
 QIB_7220_RxLPCRCErrCnt_offsetQIB_7220_RxLPCRCErrCnt_offset 0x000130c0UL qib_7220_regs.h 　
13772
 QIB_7220_RxBufOvflCnt_offsetQIB_7220_RxBufOvflCnt_offset 0x000130c8UL qib_7220_regs.h 　
13773
 QIB_7220_RxTIDFullErrCnt_offsetQIB_7220_RxTIDFullErrCnt_offset 0x000130d0UL qib_7220_regs.h 　
13774
 QIB_7220_RxTIDValidErrCnt_offseQIB_7220_RxTIDValidErrCnt_offse 0x000130d8UL qib_7220_regs.h 　
13775
 QIB_7220_RxPKeyMismatchCnt_offsQIB_7220_RxPKeyMismatchCnt_offs 0x000130e0UL qib_7220_regs.h 　
13776
 QIB_7220_RxP0HdrEgrOvflCnt_offsQIB_7220_RxP0HdrEgrOvflCnt_offs 0x000130e8UL qib_7220_regs.h 　
13777
 QIB_7220_IBStatusChangeCnt_offsQIB_7220_IBStatusChangeCnt_offs 0x00013170UL qib_7220_regs.h 　
13778
 QIB_7220_IBLinkErrRecoveryCnt_oQIB_7220_IBLinkErrRecoveryCnt_o 0x00013178UL qib_7220_regs.h 　
13779
 QIB_7220_IBLinkDownedCnt_offsetQIB_7220_IBLinkDownedCnt_offset 0x00013180UL qib_7220_regs.h 　
13780
 QIB_7220_IBSymbolErrCnt_offsetQIB_7220_IBSymbolErrCnt_offset 0x00013188UL qib_7220_regs.h 　
13781
 QIB_7220_RxVL15DroppedPktCnt_ofQIB_7220_RxVL15DroppedPktCnt_of 0x00013190UL qib_7220_regs.h 　
13782
 QIB_7220_RxOtherLocalPhyErrCnt_QIB_7220_RxOtherLocalPhyErrCnt_ 0x00013198UL qib_7220_regs.h 　
13783
 QIB_7220_PcieRetryBufDiagQwordCQIB_7220_PcieRetryBufDiagQwordC 0x000131a0UL qib_7220_regs.h 　
13784
 QIB_7220_ExcessBufferOvflCnt_ofQIB_7220_ExcessBufferOvflCnt_of 0x000131a8UL qib_7220_regs.h 　
13785
 QIB_7220_LocalLinkIntegrityErrCQIB_7220_LocalLinkIntegrityErrC 0x000131b0UL qib_7220_regs.h 　
13786
 QIB_7220_RxVlErrCnt_offsetQIB_7220_RxVlErrCnt_offset 0x000131b8UL qib_7220_regs.h 　
13787
 QIB_7220_RxDlidFltrCnt_offsetQIB_7220_RxDlidFltrCnt_offset 0x000131c0UL qib_7220_regs.h 　
13788
 QIB_7220_CNT_0131C8_offsetQIB_7220_CNT_0131C8_offset 0x000131c8UL qib_7220_regs.h 　
13789
 QIB_7220_PSStat_offsetQIB_7220_PSStat_offset 0x00013200UL qib_7220_regs.h 　
13790
 QIB_7220_PSStart_offsetQIB_7220_PSStart_offset 0x00013208UL qib_7220_regs.h 　
13791
 QIB_7220_PSInterval_offsetQIB_7220_PSInterval_offset 0x00013210UL qib_7220_regs.h 　
13792
 QIB_7220_PSRcvDataCount_offsetQIB_7220_PSRcvDataCount_offset 0x00013218UL qib_7220_regs.h 　
13793
 QIB_7220_PSRcvPktsCount_offsetQIB_7220_PSRcvPktsCount_offset 0x00013220UL qib_7220_regs.h 　
13794
 QIB_7220_PSXmitDataCount_offsetQIB_7220_PSXmitDataCount_offset 0x00013228UL qib_7220_regs.h 　
13795
 QIB_7220_PSXmitPktsCount_offsetQIB_7220_PSXmitPktsCount_offset 0x00013230UL qib_7220_regs.h 　
13796
 QIB_7220_PSXmitWaitCount_offsetQIB_7220_PSXmitWaitCount_offset 0x00013238UL qib_7220_regs.h 　
13797
 QIB_7220_CNT_013240_offsetQIB_7220_CNT_013240_offset 0x00013240UL qib_7220_regs.h 　
13798
 QIB_7220_RcvEgrArray_offsetQIB_7220_RcvEgrArray_offset 0x00014000UL qib_7220_regs.h 　
13799
 QIB_7220_MEM_038000_offsetQIB_7220_MEM_038000_offset 0x00038000UL qib_7220_regs.h 　
13800
 QIB_7220_RcvTIDArray0_offsetQIB_7220_RcvTIDArray0_offset 0x00053000UL qib_7220_regs.h 　
13801
 QIB_7220_PIOLaunchFIFO_offsetQIB_7220_PIOLaunchFIFO_offset 0x00064000UL qib_7220_regs.h 　
13802
 QIB_7220_MEM_064480_offsetQIB_7220_MEM_064480_offset 0x00064480UL qib_7220_regs.h 　
13803
 QIB_7220_SendPIOpbcCache_offsetQIB_7220_SendPIOpbcCache_offset 0x00064800UL qib_7220_regs.h 　
13804
 QIB_7220_MEM_064C80_offsetQIB_7220_MEM_064C80_offset 0x00064c80UL qib_7220_regs.h 　
13805
 QIB_7220_PreLaunchFIFO_offsetQIB_7220_PreLaunchFIFO_offset 0x00065000UL qib_7220_regs.h 　
13806
 QIB_7220_MEM_065080_offsetQIB_7220_MEM_065080_offset 0x00065080UL qib_7220_regs.h 　
13807
 QIB_7220_ScoreBoard_offsetQIB_7220_ScoreBoard_offset 0x00065400UL qib_7220_regs.h 　
13808
 QIB_7220_MEM_065440_offsetQIB_7220_MEM_065440_offset 0x00065440UL qib_7220_regs.h 　
13809
 QIB_7220_DescriptorFIFO_offsetQIB_7220_DescriptorFIFO_offset 0x00065800UL qib_7220_regs.h 　
13810
 QIB_7220_MEM_065880_offsetQIB_7220_MEM_065880_offset 0x00065880UL qib_7220_regs.h 　
13811
 QIB_7220_RcvBuf1_offsetQIB_7220_RcvBuf1_offset 0x00072000UL qib_7220_regs.h 　
13812
 QIB_7220_MEM_074800_offsetQIB_7220_MEM_074800_offset 0x00074800UL qib_7220_regs.h 　
13813
 QIB_7220_RcvBuf2_offsetQIB_7220_RcvBuf2_offset 0x00075000UL qib_7220_regs.h 　
13814
 QIB_7220_MEM_076400_offsetQIB_7220_MEM_076400_offset 0x00076400UL qib_7220_regs.h 　
13815
 QIB_7220_RcvFlags_offsetQIB_7220_RcvFlags_offset 0x00077000UL qib_7220_regs.h 　
13816
 QIB_7220_MEM_078400_offsetQIB_7220_MEM_078400_offset 0x00078400UL qib_7220_regs.h 　
13817
 QIB_7220_RcvLookupBuf1_offsetQIB_7220_RcvLookupBuf1_offset 0x00079000UL qib_7220_regs.h 　
13818
 QIB_7220_MEM_07A400_offsetQIB_7220_MEM_07A400_offset 0x0007a400UL qib_7220_regs.h 　
13819
 QIB_7220_RcvDMADatBuf_offsetQIB_7220_RcvDMADatBuf_offset 0x0007b000UL qib_7220_regs.h 　
13820
 QIB_7220_RcvDMAHdrBuf_offsetQIB_7220_RcvDMAHdrBuf_offset 0x0007b800UL qib_7220_regs.h 　
13821
 QIB_7220_MiscRXEIntMem_offsetQIB_7220_MiscRXEIntMem_offset 0x0007c000UL qib_7220_regs.h 　
13822
 QIB_7220_MEM_07D400_offsetQIB_7220_MEM_07D400_offset 0x0007d400UL qib_7220_regs.h 　
13823
 QIB_7220_PCIERcvBuf_offsetQIB_7220_PCIERcvBuf_offset 0x00080000UL qib_7220_regs.h 　
13824
 QIB_7220_PCIERetryBuf_offsetQIB_7220_PCIERetryBuf_offset 0x00084000UL qib_7220_regs.h 　
13825
 QIB_7220_PCIERcvBufRdToWrAddr_oQIB_7220_PCIERcvBufRdToWrAddr_o 0x00088000UL qib_7220_regs.h 　
13826
 QIB_7220_PCIECplBuf_offsetQIB_7220_PCIECplBuf_offset 0x00090000UL qib_7220_regs.h 　
13827
 QIB_7220_IBSerDesMappTable_offsQIB_7220_IBSerDesMappTable_offs 0x00094000UL qib_7220_regs.h 　
13828
 QIB_7220_MEM_095000_offsetQIB_7220_MEM_095000_offset 0x00095000UL qib_7220_regs.h 　
13829
 QIB_7220_SendBuf0_MA_offsetQIB_7220_SendBuf0_MA_offset 0x00100000UL qib_7220_regs.h 　
13830
 QIB_7220_MEM_1A0000_offsetQIB_7220_MEM_1A0000_offset 0x001a0000UL qib_7220_regs.h 　
13831
 QIB_7220_RcvHdrTail0_offsetQIB_7220_RcvHdrTail0_offset 0x00200000UL qib_7220_regs.h 　
13832
 QIB_7220_RcvHdrHead0_offsetQIB_7220_RcvHdrHead0_offset 0x00200008UL qib_7220_regs.h 　
13833
 QIB_7220_RcvEgrIndexTail0_offseQIB_7220_RcvEgrIndexTail0_offse 0x00200010UL qib_7220_regs.h 　
13834
 QIB_7220_RcvEgrIndexHead0_offseQIB_7220_RcvEgrIndexHead0_offse 0x00200018UL qib_7220_regs.h 　
13835
 QIB_7220_MEM_200020_offsetQIB_7220_MEM_200020_offset 0x00200020UL qib_7220_regs.h 　
13836
 QIB_7220_RcvHdrTail1_offsetQIB_7220_RcvHdrTail1_offset 0x00210000UL qib_7220_regs.h 　
13837
 QIB_7220_RcvHdrHead1_offsetQIB_7220_RcvHdrHead1_offset 0x00210008UL qib_7220_regs.h 　
13838
 QIB_7220_RcvEgrIndexTail1_offseQIB_7220_RcvEgrIndexTail1_offse 0x00210010UL qib_7220_regs.h 　
13839
 QIB_7220_RcvEgrIndexHead1_offseQIB_7220_RcvEgrIndexHead1_offse 0x00210018UL qib_7220_regs.h 　
13840
 QIB_7220_MEM_210020_offsetQIB_7220_MEM_210020_offset 0x00210020UL qib_7220_regs.h 　
13841
 QIB_7220_RcvHdrTail2_offsetQIB_7220_RcvHdrTail2_offset 0x00220000UL qib_7220_regs.h 　
13842
 QIB_7220_RcvHdrHead2_offsetQIB_7220_RcvHdrHead2_offset 0x00220008UL qib_7220_regs.h 　
13843
 QIB_7220_RcvEgrIndexTail2_offseQIB_7220_RcvEgrIndexTail2_offse 0x00220010UL qib_7220_regs.h 　
13844
 QIB_7220_RcvEgrIndexHead2_offseQIB_7220_RcvEgrIndexHead2_offse 0x00220018UL qib_7220_regs.h 　
13845
 QIB_7220_MEM_220020_offsetQIB_7220_MEM_220020_offset 0x00220020UL qib_7220_regs.h 　
13846
 QIB_7220_RcvHdrTail3_offsetQIB_7220_RcvHdrTail3_offset 0x00230000UL qib_7220_regs.h 　
13847
 QIB_7220_RcvHdrHead3_offsetQIB_7220_RcvHdrHead3_offset 0x00230008UL qib_7220_regs.h 　
13848
 QIB_7220_RcvEgrIndexTail3_offseQIB_7220_RcvEgrIndexTail3_offse 0x00230010UL qib_7220_regs.h 　
13849
 QIB_7220_RcvEgrIndexHead3_offseQIB_7220_RcvEgrIndexHead3_offse 0x00230018UL qib_7220_regs.h 　
13850
 QIB_7220_MEM_230020_offsetQIB_7220_MEM_230020_offset 0x00230020UL qib_7220_regs.h 　
13851
 QIB_7220_RcvHdrTail4_offsetQIB_7220_RcvHdrTail4_offset 0x00240000UL qib_7220_regs.h 　
13852
 QIB_7220_RcvHdrHead4_offsetQIB_7220_RcvHdrHead4_offset 0x00240008UL qib_7220_regs.h 　
13853
 QIB_7220_RcvEgrIndexTail4_offseQIB_7220_RcvEgrIndexTail4_offse 0x00240010UL qib_7220_regs.h 　
13854
 QIB_7220_RcvEgrIndexHead4_offseQIB_7220_RcvEgrIndexHead4_offse 0x00240018UL qib_7220_regs.h 　
13855
 QIB_7220_MEM_240020_offsetQIB_7220_MEM_240020_offset 0x00240020UL qib_7220_regs.h 　
13856
 QIB_7220_RcvHdrTail5_offsetQIB_7220_RcvHdrTail5_offset 0x00250000UL qib_7220_regs.h 　
13857
 QIB_7220_RcvHdrHead5_offsetQIB_7220_RcvHdrHead5_offset 0x00250008UL qib_7220_regs.h 　
13858
 QIB_7220_RcvEgrIndexTail5_offseQIB_7220_RcvEgrIndexTail5_offse 0x00250010UL qib_7220_regs.h 　
13859
 QIB_7220_RcvEgrIndexHead5_offseQIB_7220_RcvEgrIndexHead5_offse 0x00250018UL qib_7220_regs.h 　
13860
 QIB_7220_MEM_250020_offsetQIB_7220_MEM_250020_offset 0x00250020UL qib_7220_regs.h 　
13861
 QIB_7220_RcvHdrTail6_offsetQIB_7220_RcvHdrTail6_offset 0x00260000UL qib_7220_regs.h 　
13862
 QIB_7220_RcvHdrHead6_offsetQIB_7220_RcvHdrHead6_offset 0x00260008UL qib_7220_regs.h 　
13863
 QIB_7220_RcvEgrIndexTail6_offseQIB_7220_RcvEgrIndexTail6_offse 0x00260010UL qib_7220_regs.h 　
13864
 QIB_7220_RcvEgrIndexHead6_offseQIB_7220_RcvEgrIndexHead6_offse 0x00260018UL qib_7220_regs.h 　
13865
 QIB_7220_MEM_260020_offsetQIB_7220_MEM_260020_offset 0x00260020UL qib_7220_regs.h 　
13866
 QIB_7220_RcvHdrTail7_offsetQIB_7220_RcvHdrTail7_offset 0x00270000UL qib_7220_regs.h 　
13867
 QIB_7220_RcvHdrHead7_offsetQIB_7220_RcvHdrHead7_offset 0x00270008UL qib_7220_regs.h 　
13868
 QIB_7220_RcvEgrIndexTail7_offseQIB_7220_RcvEgrIndexTail7_offse 0x00270010UL qib_7220_regs.h 　
13869
 QIB_7220_RcvEgrIndexHead7_offseQIB_7220_RcvEgrIndexHead7_offse 0x00270018UL qib_7220_regs.h 　
13870
 QIB_7220_MEM_270020_offsetQIB_7220_MEM_270020_offset 0x00270020UL qib_7220_regs.h 　
13871
 QIB_7220_RcvHdrTail8_offsetQIB_7220_RcvHdrTail8_offset 0x00280000UL qib_7220_regs.h 　
13872
 QIB_7220_RcvHdrHead8_offsetQIB_7220_RcvHdrHead8_offset 0x00280008UL qib_7220_regs.h 　
13873
 QIB_7220_RcvEgrIndexTail8_offseQIB_7220_RcvEgrIndexTail8_offse 0x00280010UL qib_7220_regs.h 　
13874
 QIB_7220_RcvEgrIndexHead8_offseQIB_7220_RcvEgrIndexHead8_offse 0x00280018UL qib_7220_regs.h 　
13875
 QIB_7220_MEM_280020_offsetQIB_7220_MEM_280020_offset 0x00280020UL qib_7220_regs.h 　
13876
 QIB_7220_RcvHdrTail9_offsetQIB_7220_RcvHdrTail9_offset 0x00290000UL qib_7220_regs.h 　
13877
 QIB_7220_RcvHdrHead9_offsetQIB_7220_RcvHdrHead9_offset 0x00290008UL qib_7220_regs.h 　
13878
 QIB_7220_RcvEgrIndexTail9_offseQIB_7220_RcvEgrIndexTail9_offse 0x00290010UL qib_7220_regs.h 　
13879
 QIB_7220_RcvEgrIndexHead9_offseQIB_7220_RcvEgrIndexHead9_offse 0x00290018UL qib_7220_regs.h 　
13880
 QIB_7220_MEM_290020_offsetQIB_7220_MEM_290020_offset 0x00290020UL qib_7220_regs.h 　
13881
 QIB_7220_RcvHdrTail10_offsetQIB_7220_RcvHdrTail10_offset 0x002a0000UL qib_7220_regs.h 　
13882
 QIB_7220_RcvHdrHead10_offsetQIB_7220_RcvHdrHead10_offset 0x002a0008UL qib_7220_regs.h 　
13883
 QIB_7220_RcvEgrIndexTail10_offsQIB_7220_RcvEgrIndexTail10_offs 0x002a0010UL qib_7220_regs.h 　
13884
 QIB_7220_RcvEgrIndexHead10_offsQIB_7220_RcvEgrIndexHead10_offs 0x002a0018UL qib_7220_regs.h 　
13885
 QIB_7220_MEM_2A0020_offsetQIB_7220_MEM_2A0020_offset 0x002a0020UL qib_7220_regs.h 　
13886
 QIB_7220_RcvHdrTail11_offsetQIB_7220_RcvHdrTail11_offset 0x002b0000UL qib_7220_regs.h 　
13887
 QIB_7220_RcvHdrHead11_offsetQIB_7220_RcvHdrHead11_offset 0x002b0008UL qib_7220_regs.h 　
13888
 QIB_7220_RcvEgrIndexTail11_offsQIB_7220_RcvEgrIndexTail11_offs 0x002b0010UL qib_7220_regs.h 　
13889
 QIB_7220_RcvEgrIndexHead11_offsQIB_7220_RcvEgrIndexHead11_offs 0x002b0018UL qib_7220_regs.h 　
13890
 QIB_7220_MEM_2B0020_offsetQIB_7220_MEM_2B0020_offset 0x002b0020UL qib_7220_regs.h 　
13891
 QIB_7220_RcvHdrTail12_offsetQIB_7220_RcvHdrTail12_offset 0x002c0000UL qib_7220_regs.h 　
13892
 QIB_7220_RcvHdrHead12_offsetQIB_7220_RcvHdrHead12_offset 0x002c0008UL qib_7220_regs.h 　
13893
 QIB_7220_RcvEgrIndexTail12_offsQIB_7220_RcvEgrIndexTail12_offs 0x002c0010UL qib_7220_regs.h 　
13894
 QIB_7220_RcvEgrIndexHead12_offsQIB_7220_RcvEgrIndexHead12_offs 0x002c0018UL qib_7220_regs.h 　
13895
 QIB_7220_MEM_2C0020_offsetQIB_7220_MEM_2C0020_offset 0x002c0020UL qib_7220_regs.h 　
13896
 QIB_7220_RcvHdrTail13_offsetQIB_7220_RcvHdrTail13_offset 0x002d0000UL qib_7220_regs.h 　
13897
 QIB_7220_RcvHdrHead13_offsetQIB_7220_RcvHdrHead13_offset 0x002d0008UL qib_7220_regs.h 　
13898
 QIB_7220_RcvEgrIndexTail13_offsQIB_7220_RcvEgrIndexTail13_offs 0x002d0010UL qib_7220_regs.h 　
13899
 QIB_7220_RcvEgrIndexHead13_offsQIB_7220_RcvEgrIndexHead13_offs 0x002d0018UL qib_7220_regs.h 　
13900
 QIB_7220_MEM_2D0020_offsetQIB_7220_MEM_2D0020_offset 0x002d0020UL qib_7220_regs.h 　
13901
 QIB_7220_RcvHdrTail14_offsetQIB_7220_RcvHdrTail14_offset 0x002e0000UL qib_7220_regs.h 　
13902
 QIB_7220_RcvHdrHead14_offsetQIB_7220_RcvHdrHead14_offset 0x002e0008UL qib_7220_regs.h 　
13903
 QIB_7220_RcvEgrIndexTail14_offsQIB_7220_RcvEgrIndexTail14_offs 0x002e0010UL qib_7220_regs.h 　
13904
 QIB_7220_RcvEgrIndexHead14_offsQIB_7220_RcvEgrIndexHead14_offs 0x002e0018UL qib_7220_regs.h 　
13905
 QIB_7220_MEM_2E0020_offsetQIB_7220_MEM_2E0020_offset 0x002e0020UL qib_7220_regs.h 　
13906
 QIB_7220_RcvHdrTail15_offsetQIB_7220_RcvHdrTail15_offset 0x002f0000UL qib_7220_regs.h 　
13907
 QIB_7220_RcvHdrHead15_offsetQIB_7220_RcvHdrHead15_offset 0x002f0008UL qib_7220_regs.h 　
13908
 QIB_7220_RcvEgrIndexTail15_offsQIB_7220_RcvEgrIndexTail15_offs 0x002f0010UL qib_7220_regs.h 　
13909
 QIB_7220_RcvEgrIndexHead15_offsQIB_7220_RcvEgrIndexHead15_offs 0x002f0018UL qib_7220_regs.h 　
13910
 QIB_7220_MEM_2F0020_offsetQIB_7220_MEM_2F0020_offset 0x002f0020UL qib_7220_regs.h 　
13911
 QIB_7220_RcvHdrTail16_offsetQIB_7220_RcvHdrTail16_offset 0x00300000UL qib_7220_regs.h 　
13912
 QIB_7220_RcvHdrHead16_offsetQIB_7220_RcvHdrHead16_offset 0x00300008UL qib_7220_regs.h 　
13913
 QIB_7220_RcvEgrIndexTail16_offsQIB_7220_RcvEgrIndexTail16_offs 0x00300010UL qib_7220_regs.h 　
13914
 QIB_7220_RcvEgrIndexHead16_offsQIB_7220_RcvEgrIndexHead16_offs 0x00300018UL qib_7220_regs.h 　
13915
 QIB_7220_MEM_300020_offsetQIB_7220_MEM_300020_offset 0x00300020UL qib_7220_regs.h 　
13916
 HZHZ 100 3c515.c 　
13917
 CORKSCREWCORKSCREW 1 3c515.c 　
13918
 AUTOMEDIAAUTOMEDIA 1 3c515.c 　
13919
 TX_RING_SIZETX_RING_SIZE 16 3c515.c 　
13920
 RX_RING_SIZERX_RING_SIZE 16 3c515.c 　
13921
 PKT_BUF_SZPKT_BUF_SZ 1536 3c515.c Size of each temporary Rx buffer.
13922
 DRIVER_DEBUGDRIVER_DEBUG 1 3c515.c 　
13923
 CORKSCREW_IDCORKSCREW_ID 10 3c515.c 　
13924
 EL3_CMDEL3_CMD 0x0e 3c515.c 　
13925
 EL3_STATUSEL3_STATUS 0x0e 3c515.c 　
13926
 RX_BYTES_MASKRX_BYTES_MASK (unsigned short) (0x07ff) 3c515.c 　
13927
 NUM_TX_SLOTSNUM_TX_SLOTS 2 amd8111e.c 　
13928
 NUM_RX_SLOTSNUM_RX_SLOTS 4 amd8111e.c 　
13929
 TX_SLOTS_MASKTX_SLOTS_MASK 1 amd8111e.c 　
13930
 RX_SLOTS_MASKRX_SLOTS_MASK 3 amd8111e.c 　
13931
 TX_BUF_LENTX_BUF_LEN 1536 amd8111e.c 　
13932
 RX_BUF_LENRX_BUF_LEN 1536 amd8111e.c 　
13933
 TX_PKT_LEN_MAXTX_PKT_LEN_MAX (ETH_FRAME_LEN - ETH_HLEN) amd8111e.c 　
13934
 RX_PKT_LEN_MINRX_PKT_LEN_MIN 60 amd8111e.c 　
13935
 RX_PKT_LEN_MAXRX_PKT_LEN_MAX ETH_FRAME_LEN amd8111e.c 　
13936
 TX_TIMEOUTTX_TIMEOUT 3000 amd8111e.c 　
13937
 TX_PROCESS_TIMETX_PROCESS_TIME 10 amd8111e.c 　
13938
 TX_RETRYTX_RETRY (TX_TIMEOUT / TX_PROCESS_TIME) amd8111e.c 　
13939
 PHY_RW_RETRYPHY_RW_RETRY 10 amd8111e.c 　
13940
 TX_DESC_COUNTTX_DESC_COUNT 32 atl1e.c TX descriptors, minimum 32
13941
 RX_MEM_SIZERX_MEM_SIZE 8192 atl1e.c RX area size, minimum 8kb
13942
 MAX_FRAME_SIZEMAX_FRAME_SIZE 1500 atl1e.c Maximum MTU supported, minimum 1500
13943
 PREAMBLE_LENPREAMBLE_LEN 7 atl1e.c 　
13944
 RX_JUMBO_THRESHRX_JUMBO_THRESH ((MAX_FRAME_SIZE + ETH_HLEN + \ VLAN_HLEN + ETH_FCS_LEN + 7) >> 3) atl1e.c 　
13945
 IMT_VALIMT_VAL 100 atl1e.c interrupt moderator timer, us
13946
 ICT_VALICT_VAL 50000 atl1e.c interrupt clear timer, us
13947
 SMB_TIMERSMB_TIMER 200000 atl1e.c 　
13948
 RRD_THRESHRRD_THRESH 1 atl1e.c packets to queue before interrupt
13949
 TPD_BURSTTPD_BURST 5 atl1e.c 　
13950
 TPD_THRESHTPD_THRESH (TX_DESC_COUNT / 2) atl1e.c 　
13951
 RX_COUNT_DOWNRX_COUNT_DOWN 4 atl1e.c 　
13952
 TX_COUNT_DOWNTX_COUNT_DOWN (IMT_VAL * 4 / 3) atl1e.c 　
13953
 DMAR_DLY_CNTDMAR_DLY_CNT 15 atl1e.c 　
13954
 DMAW_DLY_CNTDMAW_DLY_CNT 4 atl1e.c 　
13955
 PCI_DEVICE_ID_ATTANSIC_L1EPCI_DEVICE_ID_ATTANSIC_L1E 0x1026 atl1e.c 　
13956
 EBUSYEBUSY 1 bnx2.c 　
13957
 ENODEVENODEV 2 bnx2.c 　
13958
 EINVALEINVAL 3 bnx2.c 　
13959
 ENOMEMENOMEM 4 bnx2.c 　
13960
 EIOEIO 5 bnx2.c 　
13961
 ETHTOOL_ALL_FIBRE_SPEEDETHTOOL_ALL_FIBRE_SPEED (ADVERTISED_1000baseT_Full) bnx2.c 　
13962
 ETHTOOL_ALL_COPPER_SPEEDETHTOOL_ALL_COPPER_SPEED (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \ ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \ ADVERTISED_1 bnx2.c 　
13963
 PHY_ALL_10_100_SPEEDPHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \ ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA) bnx2.c 　
13964
 PHY_ALL_1000_SPEEDPHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL) bnx2.c 　
13965
 TX_TIME_OUTTX_TIME_OUT 2*TICKS_PER_SEC davicom.c 　
13966
 EEPROM_ADDRLENEEPROM_ADDRLEN 6 davicom.c 　
13967
 EEPROM_SIZEEEPROM_SIZE 32 davicom.c 1 << EEPROM_ADDRLEN
13968
 EE_WRITE_CMDEE_WRITE_CMD (5 << addr_len) davicom.c 　
13969
 EE_READ_CMDEE_READ_CMD (6 << addr_len) davicom.c 　
13970
 EE_ERASE_CMDEE_ERASE_CMD (7 << addr_len) davicom.c 　
13971
 EE_SHIFT_CLKEE_SHIFT_CLK 0x02 davicom.c EEPROM shift clock.
13972
 EE_CSEE_CS 0x01 davicom.c EEPROM chip select.
13973
 EE_DATA_WRITEEE_DATA_WRITE 0x04 davicom.c EEPROM chip data in.
13974
 EE_WRITE_0EE_WRITE_0 0x01 davicom.c 　
13975
 EE_WRITE_1EE_WRITE_1 0x05 davicom.c 　
13976
 EE_DATA_READEE_DATA_READ 0x08 davicom.c EEPROM chip data out.
13977
 EE_ENBEE_ENB (0x4800 | EE_CS) davicom.c 　
13978
 PHY_DATA_0PHY_DATA_0 0x0 davicom.c 　
13979
 PHY_DATA_1PHY_DATA_1 0x20000 davicom.c 　
13980
 MDCLKHMDCLKH 0x10000 davicom.c 　
13981
 BUFLENBUFLEN 1536 davicom.c 　
13982
 NTXDNTXD 2 davicom.c 　
13983
 NRXDNRXD 4 davicom.c 　
13984
 txdtxd davicom_bufs.txd davicom.c 　
13985
 txbtxb davicom_bufs.txb davicom.c 　
13986
 rxdrxd davicom_bufs.rxd davicom.c 　
13987
 rxbrxb davicom_bufs.rxb davicom.c 　
13988
 DEPCA_NICSRDEPCA_NICSR 0x00 depca.c Network interface CSR
13989
 DEPCA_RBIDEPCA_RBI 0x02 depca.c RAM buffer index (2k buffer mode)
13990
 DEPCA_DATADEPCA_DATA 0x04 depca.c LANCE registers' data port
13991
 DEPCA_ADDRDEPCA_ADDR 0x06 depca.c LANCE registers' address port
13992
 DEPCA_HBASEDEPCA_HBASE 0x08 depca.c EISA high memory base address reg.
13993
 DEPCA_PROMDEPCA_PROM 0x0c depca.c Ethernet address ROM data port
13994
 DEPCA_CNFGDEPCA_CNFG 0x0c depca.c EISA Configuration port
13995
 DEPCA_RBSADEPCA_RBSA 0x0e depca.c RAM buffer starting address (2k buff.)
13996
 CSR0CSR0 0 depca.c 　
13997
 CSR1CSR1 1 depca.c 　
13998
 CSR2CSR2 2 depca.c 　
13999
 CSR3CSR3 3 depca.c 　
14000
 TOTO 0x0100 depca.c Time Out for remote boot
14001
 SHESHE 0x0080 depca.c SHadow memory Enable
14002
 BSBS 0x0040 depca.c Bank Select
14003
 BUFBUF 0x0020 depca.c BUFfer size (1->32k, 0->64k)
14004
 RBERBE 0x0010 depca.c Remote Boot Enable (1->net boot)
14005
 AACAAC 0x0008 depca.c Address ROM Address Counter (1->enable)
14006
 _128KB_128KB 0x0008 depca.c 128kB Network RAM (1->enable)
14007
 IMIM 0x0004 depca.c Interrupt Mask (1->mask)
14008
 IENIEN 0x0002 depca.c Interrupt tristate ENable (1->enable)
14009
 LEDLED 0x0001 depca.c LED control
14010
 ERRERR 0x8000 depca.c Error summary
14011
 BABLBABL 0x4000 depca.c Babble transmitter timeout error
14012
 CERRCERR 0x2000 depca.c Collision Error
14013
 MISSMISS 0x1000 depca.c Missed packet
14014
 MERRMERR 0x0800 depca.c Memory Error
14015
 RINTRINT 0x0400 depca.c Receiver Interrupt
14016
 TINTTINT 0x0200 depca.c Transmit Interrupt
14017
 IDONIDON 0x0100 depca.c Initialization Done
14018
 INTRINTR 0x0080 depca.c Interrupt Flag
14019
 INEAINEA 0x0040 depca.c Interrupt Enable
14020
 RXONRXON 0x0020 depca.c Receiver on
14021
 TXONTXON 0x0010 depca.c Transmitter on
14022
 TDMDTDMD 0x0008 depca.c Transmit Demand
14023
 STOPSTOP 0x0004 depca.c Stop
14024
 STRTSTRT 0x0002 depca.c Start
14025
 INITINIT 0x0001 depca.c Initialize
14026
 INTMINTM 0xff00 depca.c Interrupt Mask
14027
 INTEINTE 0xfff0 depca.c Interrupt Enable
14028
 BSWPBSWP 0x0004 depca.c Byte SWaP
14029
 ACONACON 0x0002 depca.c ALE control
14030
 BCONBCON 0x0001 depca.c Byte CONtrol
14031
 PROMPROM 0x8000 depca.c Promiscuous Mode
14032
 EMBAEMBA 0x0080 depca.c Enable Modified Back-off Algorithm
14033
 INTLINTL 0x0040 depca.c Internal Loopback
14034
 DRTYDRTY 0x0020 depca.c Disable Retry
14035
 COLLCOLL 0x0010 depca.c Force Collision
14036
 DTCRDTCR 0x0008 depca.c Disable Transmit CRC
14037
 LOOPLOOP 0x0004 depca.c Loopback
14038
 DTXDTX 0x0002 depca.c Disable the Transmitter
14039
 DRXDRX 0x0001 depca.c Disable the Receiver
14040
 R_OWNR_OWN 0x80000000 depca.c Owner bit 0 = host, 1 = lance
14041
 R_ERRR_ERR 0x4000 depca.c Error Summary
14042
 R_FRAMR_FRAM 0x2000 depca.c Framing Error
14043
 R_OFLOR_OFLO 0x1000 depca.c Overflow Error
14044
 R_CRCR_CRC 0x0800 depca.c CRC Error
14045
 R_BUFFR_BUFF 0x0400 depca.c Buffer Error
14046
 R_STPR_STP 0x0200 depca.c Start of Packet
14047
 R_ENPR_ENP 0x0100 depca.c End of Packet
14048
 T_OWNT_OWN 0x80000000 depca.c Owner bit 0 = host, 1 = lance
14049
 T_ERRT_ERR 0x4000 depca.c Error Summary
14050
 T_ADD_FCST_ADD_FCS 0x2000 depca.c More the 1 retry needed to Xmit
14051
 T_MORET_MORE 0x1000 depca.c >1 retry to transmit packet
14052
 T_ONET_ONE 0x0800 depca.c 1 try needed to transmit the packet
14053
 T_DEFT_DEF 0x0400 depca.c Deferred
14054
 T_STPT_STP 0x02000000 depca.c Start of Packet
14055
 T_ENPT_ENP 0x01000000 depca.c End of Packet
14056
 T_FLAGST_FLAGS 0xff000000 depca.c TX Flags Field
14057
 TMD3_BUFFTMD3_BUFF 0x8000 depca.c BUFFer error
14058
 TMD3_UFLOTMD3_UFLO 0x4000 depca.c UnderFLOw error
14059
 TMD3_RESTMD3_RES 0x2000 depca.c REServed
14060
 TMD3_LCOLTMD3_LCOL 0x1000 depca.c Late COLlision
14061
 TMD3_LCARTMD3_LCAR 0x0800 depca.c Loss of CARrier
14062
 TMD3_RTRYTMD3_RTRY 0x0400 depca.c ReTRY error
14063
 PROBE_LENGTHPROBE_LENGTH 32 depca.c 　
14064
 NUM_RX_DESCNUM_RX_DESC 2 depca.c Number of RX descriptors
14065
 NUM_TX_DESCNUM_TX_DESC 2 depca.c Number of TX descriptors
14066
 RX_BUFF_SZRX_BUFF_SZ 1536 depca.c Buffer size for each Rx buffer
14067
 TX_BUFF_SZTX_BUFF_SZ 1536 depca.c Buffer size for each Tx buffer
14068
 DEPCA_MODELDEPCA_MODEL DEPCA depca.c 　
14069
 DEPCA_RAM_BASEDEPCA_RAM_BASE 0xd0000 depca.c 　
14070
 ALIGN4ALIGN4 ((u32)4 - 1) depca.c 1 longword align
14071
 ALIGN8ALIGN8 ((u32)8 - 1) depca.c 2 longword (quadword) align
14072
 ALIGNALIGN ALIGN8 depca.c Keep the LANCE happy...
14073
 LA_MASKLA_MASK 0x0000ffff depca.c LANCE address mask for mapping network RAM
14074
 PCI_DM9132_IDPCI_DM9132_ID 0x91321282 dmfe.c Davicom DM9132 ID
14075
 PCI_DM9102_IDPCI_DM9102_ID 0x91021282 dmfe.c Davicom DM9102 ID
14076
 PCI_DM9100_IDPCI_DM9100_ID 0x91001282 dmfe.c Davicom DM9100 ID
14077
 PCI_DM9009_IDPCI_DM9009_ID 0x90091282 dmfe.c Davicom DM9009 ID
14078
 DM9102_IO_SIZEDM9102_IO_SIZE 0x80 dmfe.c 　
14079
 DM9102A_IO_SIZEDM9102A_IO_SIZE 0x100 dmfe.c 　
14080
 TX_MAX_SEND_CNTTX_MAX_SEND_CNT 0x1 dmfe.c Maximum tx packet per time
14081
 TX_DESC_CNTTX_DESC_CNT 0x10 dmfe.c Allocated Tx descriptors
14082
 RX_DESC_CNTRX_DESC_CNT 0x20 dmfe.c Allocated Rx descriptors
14083
 TX_FREE_DESC_CNTTX_FREE_DESC_CNT (TX_DESC_CNT - 2) dmfe.c Max TX packet count
14084
 TX_WAKE_DESC_CNTTX_WAKE_DESC_CNT (TX_DESC_CNT - 3) dmfe.c TX wakeup count
14085
 DESC_ALL_CNTDESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT) dmfe.c 　
14086
 TX_BUF_ALLOCTX_BUF_ALLOC 0x600 dmfe.c 　
14087
 RX_ALLOC_SIZERX_ALLOC_SIZE 0x620 dmfe.c 　
14088
 DM910X_RESETDM910X_RESET 1 dmfe.c 　
14089
 CR0_DEFAULTCR0_DEFAULT 0x00E00000 dmfe.c TX & RX burst mode
14090
 CR6_DEFAULTCR6_DEFAULT 0x00080000 dmfe.c HD
14091
 CR7_DEFAULTCR7_DEFAULT 0x180c1 dmfe.c 　
14092
 CR15_DEFAULTCR15_DEFAULT 0x06 dmfe.c TxJabber RxWatchdog
14093
 TDES0_ERR_MASKTDES0_ERR_MASK 0x4302 dmfe.c TXJT, LC, EC, FUE
14094
 MAX_PACKET_SIZEMAX_PACKET_SIZE 1514 dmfe.c 　
14095
 DMFE_MAX_MULTICASTDMFE_MAX_MULTICAST 14 dmfe.c 　
14096
 RX_COPY_SIZERX_COPY_SIZE 100 dmfe.c 　
14097
 MAX_CHECK_PACKETMAX_CHECK_PACKET 0x8000 dmfe.c 　
14098
 DM9801_NOISE_FLOORDM9801_NOISE_FLOOR 8 dmfe.c 　
14099
 DM9802_NOISE_FLOORDM9802_NOISE_FLOOR 5 dmfe.c 　
14100
 DMFE_10MHFDMFE_10MHF 0 dmfe.c 　
14101
 DMFE_100MHFDMFE_100MHF 1 dmfe.c 　
14102
 DMFE_10MFDDMFE_10MFD 4 dmfe.c 　
14103
 DMFE_100MFDDMFE_100MFD 5 dmfe.c 　
14104
 DMFE_AUTODMFE_AUTO 8 dmfe.c 　
14105
 DMFE_1M_HPNADMFE_1M_HPNA 0x10 dmfe.c 　
14106
 DMFE_TXTH_72DMFE_TXTH_72 0x400000 dmfe.c TX TH 72 byte
14107
 DMFE_TXTH_96DMFE_TXTH_96 0x404000 dmfe.c TX TH 96 byte
14108
 DMFE_TXTH_128DMFE_TXTH_128 0x0000 dmfe.c TX TH 128 byte
14109
 DMFE_TXTH_256DMFE_TXTH_256 0x4000 dmfe.c TX TH 256 byte
14110
 DMFE_TXTH_512DMFE_TXTH_512 0x8000 dmfe.c TX TH 512 byte
14111
 DMFE_TXTH_1KDMFE_TXTH_1K 0xC000 dmfe.c TX TH 1K byte
14112
 DMFE_TIMER_WUTDMFE_TIMER_WUT (jiffies + HZ * 1) dmfe.c timer wakeup time : 1 second
14113
 DMFE_TX_TIMEOUTDMFE_TX_TIMEOUT ((3*HZ)/2) dmfe.c tx packet time-out time 1.5 s"
14114
 DMFE_TX_KICKDMFE_TX_KICK (HZ/2) dmfe.c tx packet Kick-out time 0.5 s"
14115
 CR9_SROM_READCR9_SROM_READ 0x4800 dmfe.c 　
14116
 CR9_SRCSCR9_SRCS 0x1 dmfe.c 　
14117
 CR9_SRCLKCR9_SRCLK 0x2 dmfe.c 　
14118
 CR9_CRDOUTCR9_CRDOUT 0x8 dmfe.c 　
14119
 SROM_DATA_0SROM_DATA_0 0x0 dmfe.c 　
14120
 SROM_DATA_1SROM_DATA_1 0x4 dmfe.c 　
14121
 PHY_DATA_1PHY_DATA_1 0x20000 dmfe.c 　
14122
 PHY_DATA_0PHY_DATA_0 0x00000 dmfe.c 　
14123
 MDCLKHMDCLKH 0x10000 dmfe.c 　
14124
 PHY_POWER_DOWNPHY_POWER_DOWN 0x800 dmfe.c 　
14125
 SROM_V41_CODESROM_V41_CODE 0x14 dmfe.c 　
14126
 DEVICEDEVICE net_device dmfe.c 　
14127
 txdtxd dmfe_bufs.txd dmfe.c 　
14128
 txbtxb dmfe_bufs.txb dmfe.c 　
14129
 rxdrxd dmfe_bufs.rxd dmfe.c 　
14130
 rxbrxb dmfe_bufs.rxb dmfe.c 　
14131
 board_foundboard_found 1 dmfe.c 　
14132
 valid_linkvalid_link 0 dmfe.c 　
14133
 LAN595LAN595 0 eepro.c 　
14134
 LAN595TXLAN595TX 1 eepro.c 　
14135
 LAN595FXLAN595FX 2 eepro.c 　
14136
 LAN595FX_10ISALAN595FX_10ISA 3 eepro.c 　
14137
 SLOW_DOWNSLOW_DOWN inb(0x80); eepro.c 　
14138
 SA_ADDR0SA_ADDR0 0x00 eepro.c Etherexpress Pro/10
14139
 SA_ADDR1SA_ADDR1 0xaa eepro.c 　
14140
 SA_ADDR2SA_ADDR2 0x00 eepro.c 　
14141
 ee_PnPee_PnP 0 eepro.c Plug 'n Play enable bit
14142
 ee_Word1ee_Word1 1 eepro.c Word 1?
14143
 ee_BusWidthee_BusWidth 2 eepro.c 8/16 bit
14144
 ee_FlashAddree_FlashAddr 3 eepro.c Flash Address
14145
 ee_FlashMaskee_FlashMask 0x7 eepro.c Mask
14146
 ee_AutoIOee_AutoIO 6 eepro.c 　
14147
 ee_reserved0ee_reserved0 7 eepro.c =0!
14148
 ee_Flashee_Flash 8 eepro.c Flash there?
14149
 ee_AutoNegee_AutoNeg 9 eepro.c Auto Negotiation enabled?
14150
 ee_IO0ee_IO0 10 eepro.c IO Address LSB
14151
 ee_IO0Maskee_IO0Mask 0x eepro.c ...
14152
 ee_IO1ee_IO1 15 eepro.c IO MSB
14153
 ee_IntSelee_IntSel 0 eepro.c Interrupt
14154
 ee_IntMaskee_IntMask 0x7 eepro.c 　
14155
 ee_LIee_LI 3 eepro.c Link Integrity 0= enabled
14156
 ee_PCee_PC 4 eepro.c Polarity Correction 0= enabled
14157
 ee_TPE_AUIee_TPE_AUI 5 eepro.c PortSelection 1=TPE
14158
 ee_Jabberee_Jabber 6 eepro.c Jabber prevention 0= enabled
14159
 ee_AutoPortee_AutoPort 7 eepro.c Auto Port Selection 1= Disabled
14160
 ee_SMOUTee_SMOUT 8 eepro.c SMout Pin Control 0= Input
14161
 ee_PROMee_PROM 9 eepro.c Flash EPROM / PROM 0=Flash
14162
 ee_reserved1ee_reserved1 10 eepro.c .. 12 =0!
14163
 ee_AltReadyee_AltReady 13 eepro.c Alternate Ready, 0=normal
14164
 ee_reserved2ee_reserved2 14 eepro.c =0!
14165
 ee_Duplexee_Duplex 15 eepro.c 　
14166
 ee_IA5ee_IA5 0 eepro.c bit start for individual Addr Byte 5
14167
 ee_IA4ee_IA4 8 eepro.c bit start for individual Addr Byte 5
14168
 ee_IA3ee_IA3 0 eepro.c bit start for individual Addr Byte 5
14169
 ee_IA2ee_IA2 8 eepro.c bit start for individual Addr Byte 5
14170
 ee_IA1ee_IA1 0 eepro.c bit start for individual Addr Byte 5
14171
 ee_IA0ee_IA0 8 eepro.c bit start for individual Addr Byte 5
14172
 ee_BNC_TPEee_BNC_TPE 0 eepro.c 0=TPE
14173
 ee_BootTypeee_BootType 1 eepro.c 00=None, 01=IPX, 10=ODI, 11=NDIS
14174
 ee_BootTypeMaskee_BootTypeMask 0x3 eepro.c 　
14175
 ee_NumConnee_NumConn 3 eepro.c Number of Connections 0= One or Two
14176
 ee_FlashSockee_FlashSock 4 eepro.c Presence of Flash Socket 0= Present
14177
 ee_PortTPEee_PortTPE 5 eepro.c 　
14178
 ee_PortBNCee_PortBNC 6 eepro.c 　
14179
 ee_PortAUIee_PortAUI 7 eepro.c 　
14180
 ee_PowerMgtee_PowerMgt 10 eepro.c 0= disabled
14181
 ee_CPee_CP 13 eepro.c Concurrent Processing
14182
 ee_CPMaskee_CPMask 0x7 eepro.c 　
14183
 ee_Steppingee_Stepping 0 eepro.c Stepping info
14184
 ee_StepMaskee_StepMask 0x0F eepro.c 　
14185
 ee_BoardIDee_BoardID 4 eepro.c Manucaturer Board ID, reserved
14186
 ee_BoardMaskee_BoardMask 0x0FFF eepro.c 　
14187
 ee_INT_TO_IRQee_INT_TO_IRQ 0 eepro.c int to IRQ Mapping = 0x1EB8 for Pro/10+
14188
 ee_FX_INT2IRQee_FX_INT2IRQ 0x1EB8 eepro.c the _only_ mapping allowed for FX chips
14189
 ee_SIZEee_SIZE 0x40 eepro.c total EEprom Size
14190
 ee_Checksumee_Checksum 0xBABA eepro.c initial and final value for adding checksum
14191
 ee_addr_vendoree_addr_vendor 0x10 eepro.c Word offset for EISA Vendor ID
14192
 ee_addr_idee_addr_id 0x11 eepro.c Word offset for Card ID
14193
 ee_addr_SNee_addr_SN 0x12 eepro.c Serial Number
14194
 ee_addr_CRC_8ee_addr_CRC_8 0x14 eepro.c CRC over last thee Bytes
14195
 ee_vendor_intel0ee_vendor_intel0 0x25 eepro.c Vendor ID Intel
14196
 ee_vendor_intel1ee_vendor_intel1 0xD4 eepro.c 　
14197
 ee_id_eepro10p0ee_id_eepro10p0 0x10 eepro.c ID for eepro/10+
14198
 ee_id_eepro10p1ee_id_eepro10p1 0x31 eepro.c 　
14199
 RAM_SIZERAM_SIZE 0x8000 eepro.c 　
14200
 RCV_HEADERRCV_HEADER 8 eepro.c 　
14201
 RCV_DEFAULT_RAMRCV_DEFAULT_RAM 0x6000 eepro.c 　
14202
 RCV_RAMRCV_RAM rcv_ram eepro.c 　
14203
 XMT_HEADERXMT_HEADER 8 eepro.c 　
14204
 XMT_RAMXMT_RAM (RAM_SIZE - RCV_RAM) eepro.c 　
14205
 XMT_STARTXMT_START ((rcv_start + RCV_RAM) % RAM_SIZE) eepro.c 　
14206
 RCV_LOWER_LIMITRCV_LOWER_LIMIT (rcv_start >> 8) eepro.c 　
14207
 RCV_UPPER_LIMITRCV_UPPER_LIMIT (((rcv_start + RCV_RAM) - 2) >> 8) eepro.c 　
14208
 XMT_LOWER_LIMITXMT_LOWER_LIMIT (XMT_START >> 8) eepro.c 　
14209
 XMT_UPPER_LIMITXMT_UPPER_LIMIT (((XMT_START + XMT_RAM) - 2) >> 8) eepro.c 　
14210
 RCV_START_PRORCV_START_PRO 0x00 eepro.c 　
14211
 RCV_START_10RCV_START_10 XMT_RAM eepro.c 　
14212
 RCV_DONERCV_DONE 0x0008 eepro.c 　
14213
 RX_OKRX_OK 0x2000 eepro.c 　
14214
 RX_ERRORRX_ERROR 0x0d81 eepro.c 　
14215
 TX_DONE_BITTX_DONE_BIT 0x0080 eepro.c 　
14216
 CHAIN_BITCHAIN_BIT 0x8000 eepro.c 　
14217
 XMT_STATUSXMT_STATUS 0x02 eepro.c 　
14218
 XMT_CHAINXMT_CHAIN 0x04 eepro.c 　
14219
 XMT_COUNTXMT_COUNT 0x06 eepro.c 　
14220
 BANK0_SELECTBANK0_SELECT 0x00 eepro.c 　
14221
 BANK1_SELECTBANK1_SELECT 0x40 eepro.c 　
14222
 BANK2_SELECTBANK2_SELECT 0x80 eepro.c 　
14223
 COMMAND_REGCOMMAND_REG 0x00 eepro.c Register 0
14224
 MC_SETUPMC_SETUP 0x03 eepro.c 　
14225
 XMT_CMDXMT_CMD 0x04 eepro.c 　
14226
 DIAGNOSE_CMDDIAGNOSE_CMD 0x07 eepro.c 　
14227
 RCV_ENABLE_CMDRCV_ENABLE_CMD 0x08 eepro.c 　
14228
 RCV_DISABLE_CMDRCV_DISABLE_CMD 0x0a eepro.c 　
14229
 STOP_RCV_CMDSTOP_RCV_CMD 0x0b eepro.c 　
14230
 RESET_CMDRESET_CMD 0x0e eepro.c 　
14231
 POWER_DOWN_CMDPOWER_DOWN_CMD 0x18 eepro.c 　
14232
 RESUME_XMT_CMDRESUME_XMT_CMD 0x1c eepro.c 　
14233
 SEL_RESET_CMDSEL_RESET_CMD 0x1e eepro.c 　
14234
 STATUS_REGSTATUS_REG 0x01 eepro.c Register 1
14235
 RX_INTRX_INT 0x02 eepro.c 　
14236
 TX_INTTX_INT 0x04 eepro.c 　
14237
 EXEC_STATUSEXEC_STATUS 0x30 eepro.c 　
14238
 ID_REGID_REG 0x02 eepro.c Register 2
14239
 R_ROBIN_BITSR_ROBIN_BITS 0xc0 eepro.c round robin counter
14240
 ID_REG_MASKID_REG_MASK 0x2c eepro.c 　
14241
 ID_REG_SIGID_REG_SIG 0x24 eepro.c 　
14242
 AUTO_ENABLEAUTO_ENABLE 0x10 eepro.c 　
14243
 INT_MASK_REGINT_MASK_REG 0x03 eepro.c Register 3
14244
 RX_STOP_MASKRX_STOP_MASK 0x01 eepro.c 　
14245
 RX_MASKRX_MASK 0x02 eepro.c 　
14246
 TX_MASKTX_MASK 0x04 eepro.c 　
14247
 EXEC_MASKEXEC_MASK 0x08 eepro.c 　
14248
 ALL_MASKALL_MASK 0x0f eepro.c 　
14249
 IO_32_BITIO_32_BIT 0x10 eepro.c 　
14250
 RCV_BARRCV_BAR 0x04 eepro.c The following are word (16-bit) registers
14251
 RCV_STOPRCV_STOP 0x06 eepro.c 　
14252
 XMT_BAR_PROXMT_BAR_PRO 0x0a eepro.c 　
14253
 XMT_BAR_10XMT_BAR_10 0x0b eepro.c 　
14254
 HOST_ADDRESS_REGHOST_ADDRESS_REG 0x0c eepro.c 　
14255
 IO_PORTIO_PORT 0x0e eepro.c 　
14256
 IO_PORT_32_BITIO_PORT_32_BIT 0x0c eepro.c 　
14257
 REG1REG1 0x01 eepro.c 　
14258
 WORD_WIDTHWORD_WIDTH 0x02 eepro.c 　
14259
 INT_ENABLEINT_ENABLE 0x80 eepro.c 　
14260
 INT_NO_REGINT_NO_REG 0x02 eepro.c 　
14261
 RCV_LOWER_LIMIT_REGRCV_LOWER_LIMIT_REG 0x08 eepro.c 　
14262
 RCV_UPPER_LIMIT_REGRCV_UPPER_LIMIT_REG 0x09 eepro.c 　
14263
 XMT_LOWER_LIMIT_REG_PROXMT_LOWER_LIMIT_REG_PRO 0x0a eepro.c 　
14264
 XMT_UPPER_LIMIT_REG_PROXMT_UPPER_LIMIT_REG_PRO 0x0b eepro.c 　
14265
 XMT_LOWER_LIMIT_REG_10XMT_LOWER_LIMIT_REG_10 0x0b eepro.c 　
14266
 XMT_UPPER_LIMIT_REG_10XMT_UPPER_LIMIT_REG_10 0x0a eepro.c 　
14267
 XMT_Chain_IntXMT_Chain_Int 0x20 eepro.c Interrupt at the end of the transmit chain
14268
 XMT_Chain_ErrStopXMT_Chain_ErrStop 0x40 eepro.c Interrupt at the end of the chain even if there are errors
14269
 RCV_Discard_BadFrameRCV_Discard_BadFrame 0x80 eepro.c Throw bad frames away, and continue to receive others
14270
 REG2REG2 0x02 eepro.c 　
14271
 PRMSC_ModePRMSC_Mode 0x01 eepro.c 　
14272
 Multi_IAMulti_IA 0x20 eepro.c 　
14273
 REG3REG3 0x03 eepro.c 　
14274
 TPE_BITTPE_BIT 0x04 eepro.c 　
14275
 BNC_BITBNC_BIT 0x20 eepro.c 　
14276
 REG13REG13 0x0d eepro.c 　
14277
 FDXFDX 0x00 eepro.c 　
14278
 A_N_ENABLEA_N_ENABLE 0x02 eepro.c 　
14279
 I_ADD_REG0I_ADD_REG0 0x04 eepro.c 　
14280
 I_ADD_REG1I_ADD_REG1 0x05 eepro.c 　
14281
 I_ADD_REG2I_ADD_REG2 0x06 eepro.c 　
14282
 I_ADD_REG3I_ADD_REG3 0x07 eepro.c 　
14283
 I_ADD_REG4I_ADD_REG4 0x08 eepro.c 　
14284
 I_ADD_REG5I_ADD_REG5 0x09 eepro.c 　
14285
 EEPROM_REG_PROEEPROM_REG_PRO 0x0a eepro.c 　
14286
 EEPROM_REG_10EEPROM_REG_10 0x0b eepro.c 　
14287
 EESKEESK 0x01 eepro.c 　
14288
 EECSEECS 0x02 eepro.c 　
14289
 EEDIEEDI 0x04 eepro.c 　
14290
 EEDOEEDO 0x08 eepro.c 　
14291
 EE_READ_CMDEE_READ_CMD (6 << 6) eepro.c 　
14292
 INTERRUPT_MASKINTERRUPT_MASK ( SCBMaskEarlyRx | SCBMaskFlowCtl ) eepro100.c 　
14293
 RFD_STATUSRFD_STATUS ( RFD_OK | RFDRxCol | RFDRxErr | RFDShort | \ RFDDMAOverrun | RFDNoBufs | RFDCRCError ) eepro100.c 　
14294
 TX_RING_SIZETX_RING_SIZE 2 epic100.c use at least 2 buffers for TX
14295
 RX_RING_SIZERX_RING_SIZE 2 epic100.c 　
14296
 PKT_BUF_SZPKT_BUF_SZ 1536 epic100.c Size of each temporary Tx/Rx buffer.
14297
 EPIC_DEBUGEPIC_DEBUG 0 epic100.c debug level
14298
 TD_STDFLAGSTD_STDFLAGS TD_LASTDESC epic100.c 　
14299
 rx_ringrx_ring epic100_bufs.rx_ring epic100.c 　
14300
 tx_ringtx_ring epic100_bufs.tx_ring epic100.c 　
14301
 rx_packetrx_packet epic100_bufs.rx_packet epic100.c 　
14302
 tx_packettx_packet epic100_bufs.tx_packet epic100.c 　
14303
 EE_SHIFT_CLKEE_SHIFT_CLK 0x04 epic100.c EEPROM shift clock.
14304
 EE_CSEE_CS 0x02 epic100.c EEPROM chip select.
14305
 EE_DATA_WRITEEE_DATA_WRITE 0x08 epic100.c EEPROM chip data in.
14306
 EE_WRITE_0EE_WRITE_0 0x01 epic100.c 　
14307
 EE_WRITE_1EE_WRITE_1 0x09 epic100.c 　
14308
 EE_DATA_READEE_DATA_READ 0x10 epic100.c EEPROM chip data out.
14309
 EE_ENBEE_ENB (0x0001 | EE_CS) epic100.c 　
14310
 EE_WRITE_CMDEE_WRITE_CMD (5 << 6) epic100.c 　
14311
 EE_READ_CMDEE_READ_CMD (6 << 6) epic100.c 　
14312
 EE_ERASE_CMDEE_ERASE_CMD (7 << 6) epic100.c 　
14313
 MII_READOPMII_READOP 1 epic100.c 　
14314
 MII_WRITEOPMII_WRITEOP 2 epic100.c 　
14315
 FALCON_USE_IO_BARFALCON_USE_IO_BAR 0 etherfabric.c 　
14316
 HZHZ 100 etherfabric.c 　
14317
 EFAB_BYTEEFAB_BYTE 1 etherfabric.c 　
14318
 GMII_PSSRGMII_PSSR 0x11 etherfabric.c PHY-specific status register
14319
 LPA_EF_1000FULLLPA_EF_1000FULL 0x00020000 etherfabric.c 　
14320
 LPA_EF_1000HALFLPA_EF_1000HALF 0x00010000 etherfabric.c 　
14321
 LPA_EF_10000FULLLPA_EF_10000FULL 0x00040000 etherfabric.c 　
14322
 LPA_EF_10000HALFLPA_EF_10000HALF 0x00080000 etherfabric.c 　
14323
 LPA_100LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) etherfabric.c 　
14324
 LPA_EF_1000LPA_EF_1000 ( LPA_EF_1000FULL | LPA_EF_1000HALF ) etherfabric.c 　
14325
 LPA_EF_10000LPA_EF_10000 ( LPA_EF_10000FULL | LPA_EF_10000HALF ) etherfabric.c 　
14326
 LPA_EF_DUPLEXLPA_EF_DUPLEX ( LPA_10FULL | LPA_100FULL | LPA_EF_1000FULL | \ LPA_EF_10000FULL ) etherfabric.c 　
14327
 LPA_OTHERLPA_OTHER ~( LPA_10FULL | LPA_10HALF | LPA_100FULL | \ LPA_100HALF | LPA_EF_1000FULL | LPA_EF_1000HALF ) etherfabric.c 　
14328
 PSSR_LSTATUSPSSR_LSTATUS 0x0400 etherfabric.c Bit 10 - link status
14329
 MDIO_MMD_PMAPMDMDIO_MMD_PMAPMD (1) etherfabric.c 　
14330
 MDIO_MMD_WISMDIO_MMD_WIS (2) etherfabric.c 　
14331
 MDIO_MMD_PCSMDIO_MMD_PCS (3) etherfabric.c 　
14332
 MDIO_MMD_PHYXSMDIO_MMD_PHYXS (4) etherfabric.c 　
14333
 MDIO_MMD_DTEXSMDIO_MMD_DTEXS (5) etherfabric.c 　
14334
 MDIO_MMD_TCMDIO_MMD_TC (6) etherfabric.c 　
14335
 MDIO_MMD_ANMDIO_MMD_AN (7) etherfabric.c 　
14336
 MDIO_MMDREG_CTRL1MDIO_MMDREG_CTRL1 (0) etherfabric.c 　
14337
 MDIO_MMDREG_STAT1MDIO_MMDREG_STAT1 (1) etherfabric.c 　
14338
 MDIO_MMDREG_DEVS0MDIO_MMDREG_DEVS0 (5) etherfabric.c 　
14339
 MDIO_MMDREG_STAT2MDIO_MMDREG_STAT2 (8) etherfabric.c 　
14340
 MDIO_MMDREG_CTRL1_RESET_LBNMDIO_MMDREG_CTRL1_RESET_LBN (15) etherfabric.c 　
14341
 MDIO_MMDREG_CTRL1_RESET_WIDTHMDIO_MMDREG_CTRL1_RESET_WIDTH (1) etherfabric.c 　
14342
 MDIO_MMDREG_STAT1_FAULT_LBNMDIO_MMDREG_STAT1_FAULT_LBN (7) etherfabric.c 　
14343
 MDIO_MMDREG_STAT1_FAULT_WIDTHMDIO_MMDREG_STAT1_FAULT_WIDTH (1) etherfabric.c 　
14344
 MDIO_MMDREG_STAT1_LINK_LBNMDIO_MMDREG_STAT1_LINK_LBN (2) etherfabric.c 　
14345
 MDIO_MMDREG_STAT1_LINK_WIDTHMDIO_MMDREG_STAT1_LINK_WIDTH (1) etherfabric.c 　
14346
 MDIO_MMDREG_DEVS0_DTEXSMDIO_MMDREG_DEVS0_DTEXS DEV_PRESENT_BIT(MDIO_MMD_DTEXS) etherfabric.c 　
14347
 MDIO_MMDREG_DEVS0_PHYXSMDIO_MMDREG_DEVS0_PHYXS DEV_PRESENT_BIT(MDIO_MMD_PHYXS) etherfabric.c 　
14348
 MDIO_MMDREG_DEVS0_PCSMDIO_MMDREG_DEVS0_PCS DEV_PRESENT_BIT(MDIO_MMD_PCS) etherfabric.c 　
14349
 MDIO_MMDREG_DEVS0_WISMDIO_MMDREG_DEVS0_WIS DEV_PRESENT_BIT(MDIO_MMD_WIS) etherfabric.c 　
14350
 MDIO_MMDREG_DEVS0_PMAPMDMDIO_MMDREG_DEVS0_PMAPMD DEV_PRESENT_BIT(MDIO_MMD_PMAPMD) etherfabric.c 　
14351
 MDIO_MMDREG_DEVS0_ANMDIO_MMDREG_DEVS0_AN DEV_PRESENT_BIT(MDIO_MMD_AN) etherfabric.c 　
14352
 MDIO_MMDREG_STAT2_PRESENT_VALMDIO_MMDREG_STAT2_PRESENT_VAL (2) etherfabric.c 　
14353
 MDIO_MMDREG_STAT2_PRESENT_LBNMDIO_MMDREG_STAT2_PRESENT_LBN (14) etherfabric.c 　
14354
 MDIO_MMDREG_STAT2_PRESENT_WIDTHMDIO_MMDREG_STAT2_PRESENT_WIDTH (2) etherfabric.c 　
14355
 MDIO_PHYXS_LANE_STATEMDIO_PHYXS_LANE_STATE (0x18) etherfabric.c 　
14356
 MDIO_PHYXS_LANE_ALIGNED_LBNMDIO_PHYXS_LANE_ALIGNED_LBN (12) etherfabric.c 　
14357
 MDIO_PHYXS_LANE_SYNC0_LBNMDIO_PHYXS_LANE_SYNC0_LBN (0) etherfabric.c 　
14358
 MDIO_PHYXS_LANE_SYNC1_LBNMDIO_PHYXS_LANE_SYNC1_LBN (1) etherfabric.c 　
14359
 MDIO_PHYXS_LANE_SYNC2_LBNMDIO_PHYXS_LANE_SYNC2_LBN (2) etherfabric.c 　
14360
 MDIO_PHYXS_LANE_SYNC3_LBNMDIO_PHYXS_LANE_SYNC3_LBN (3) etherfabric.c 　
14361
 MDIO45_RESET_TRIESMDIO45_RESET_TRIES 100 etherfabric.c 　
14362
 MDIO45_RESET_SPINTIMEMDIO45_RESET_SPINTIME 10 etherfabric.c 　
14363
 FCN_IOM_IND_ADR_REGFCN_IOM_IND_ADR_REG 0x0 etherfabric.c 　
14364
 FCN_IOM_IND_DAT_REGFCN_IOM_IND_DAT_REG 0x4 etherfabric.c 　
14365
 FCN_ADR_REGION_REG_KERFCN_ADR_REGION_REG_KER 0x00 etherfabric.c 　
14366
 FCN_ADR_REGION0_LBNFCN_ADR_REGION0_LBN 0 etherfabric.c 　
14367
 FCN_ADR_REGION0_WIDTHFCN_ADR_REGION0_WIDTH 18 etherfabric.c 　
14368
 FCN_ADR_REGION1_LBNFCN_ADR_REGION1_LBN 32 etherfabric.c 　
14369
 FCN_ADR_REGION1_WIDTHFCN_ADR_REGION1_WIDTH 18 etherfabric.c 　
14370
 FCN_ADR_REGION2_LBNFCN_ADR_REGION2_LBN 64 etherfabric.c 　
14371
 FCN_ADR_REGION2_WIDTHFCN_ADR_REGION2_WIDTH 18 etherfabric.c 　
14372
 FCN_ADR_REGION3_LBNFCN_ADR_REGION3_LBN 96 etherfabric.c 　
14373
 FCN_ADR_REGION3_WIDTHFCN_ADR_REGION3_WIDTH 18 etherfabric.c 　
14374
 FCN_INT_EN_REG_KERFCN_INT_EN_REG_KER 0x0010 etherfabric.c 　
14375
 FCN_MEM_PERR_INT_EN_KER_LBNFCN_MEM_PERR_INT_EN_KER_LBN 5 etherfabric.c 　
14376
 FCN_MEM_PERR_INT_EN_KER_WIDTHFCN_MEM_PERR_INT_EN_KER_WIDTH 1 etherfabric.c 　
14377
 FCN_KER_INT_CHAR_LBNFCN_KER_INT_CHAR_LBN 4 etherfabric.c 　
14378
 FCN_KER_INT_CHAR_WIDTHFCN_KER_INT_CHAR_WIDTH 1 etherfabric.c 　
14379
 FCN_KER_INT_KER_LBNFCN_KER_INT_KER_LBN 3 etherfabric.c 　
14380
 FCN_KER_INT_KER_WIDTHFCN_KER_INT_KER_WIDTH 1 etherfabric.c 　
14381
 FCN_ILL_ADR_ERR_INT_EN_KER_LBNFCN_ILL_ADR_ERR_INT_EN_KER_LBN 2 etherfabric.c 　
14382
 FCN_ILL_ADR_ERR_INT_EN_KER_WIDTFCN_ILL_ADR_ERR_INT_EN_KER_WIDT 1 etherfabric.c 　
14383
 FCN_SRM_PERR_INT_EN_KER_LBNFCN_SRM_PERR_INT_EN_KER_LBN 1 etherfabric.c 　
14384
 FCN_SRM_PERR_INT_EN_KER_WIDTHFCN_SRM_PERR_INT_EN_KER_WIDTH 1 etherfabric.c 　
14385
 FCN_DRV_INT_EN_KER_LBNFCN_DRV_INT_EN_KER_LBN 0 etherfabric.c 　
14386
 FCN_DRV_INT_EN_KER_WIDTHFCN_DRV_INT_EN_KER_WIDTH 1 etherfabric.c 　
14387
 FCN_INT_ADR_REG_KERFCN_INT_ADR_REG_KER 0x0030 etherfabric.c 　
14388
 FCN_INT_ADR_KER_LBNFCN_INT_ADR_KER_LBN 0 etherfabric.c 　
14389
 FCN_INT_ADR_KER_WIDTHFCN_INT_ADR_KER_WIDTH EFAB_DMA_TYPE_WIDTH ( 64 ) etherfabric.c 　
14390
 INT_ISR0_B0INT_ISR0_B0 0x90 etherfabric.c 　
14391
 INT_ISR1_B0INT_ISR1_B0 0xA0 etherfabric.c 　
14392
 FCN_INT_ACK_KER_REG_A1FCN_INT_ACK_KER_REG_A1 0x0050 etherfabric.c 　
14393
 INT_ACK_DUMMY_DATA_LBNINT_ACK_DUMMY_DATA_LBN 0 etherfabric.c 　
14394
 INT_ACK_DUMMY_DATA_WIDTHINT_ACK_DUMMY_DATA_WIDTH 32 etherfabric.c 　
14395
 WORK_AROUND_BROKEN_PCI_READS_REWORK_AROUND_BROKEN_PCI_READS_RE 0x0070 etherfabric.c 　
14396
 FCN_HW_INIT_REG_KERFCN_HW_INIT_REG_KER 0x00c0 etherfabric.c 　
14397
 FCN_BCSR_TARGET_MASK_LBNFCN_BCSR_TARGET_MASK_LBN 101 etherfabric.c 　
14398
 FCN_BCSR_TARGET_MASK_WIDTHFCN_BCSR_TARGET_MASK_WIDTH 4 etherfabric.c 　
14399
 FCN_EE_SPI_HCMD_REGFCN_EE_SPI_HCMD_REG 0x0100 etherfabric.c 　
14400
 FCN_EE_SPI_HCMD_CMD_EN_LBNFCN_EE_SPI_HCMD_CMD_EN_LBN 31 etherfabric.c 　
14401
 FCN_EE_SPI_HCMD_CMD_EN_WIDTHFCN_EE_SPI_HCMD_CMD_EN_WIDTH 1 etherfabric.c 　
14402
 FCN_EE_WR_TIMER_ACTIVE_LBNFCN_EE_WR_TIMER_ACTIVE_LBN 28 etherfabric.c 　
14403
 FCN_EE_WR_TIMER_ACTIVE_WIDTHFCN_EE_WR_TIMER_ACTIVE_WIDTH 1 etherfabric.c 　
14404
 FCN_EE_SPI_HCMD_SF_SEL_LBNFCN_EE_SPI_HCMD_SF_SEL_LBN 24 etherfabric.c 　
14405
 FCN_EE_SPI_HCMD_SF_SEL_WIDTHFCN_EE_SPI_HCMD_SF_SEL_WIDTH 1 etherfabric.c 　
14406
 FCN_EE_SPI_EEPROMFCN_EE_SPI_EEPROM 0 etherfabric.c 　
14407
 FCN_EE_SPI_FLASHFCN_EE_SPI_FLASH 1 etherfabric.c 　
14408
 FCN_EE_SPI_HCMD_DABCNT_LBNFCN_EE_SPI_HCMD_DABCNT_LBN 16 etherfabric.c 　
14409
 FCN_EE_SPI_HCMD_DABCNT_WIDTHFCN_EE_SPI_HCMD_DABCNT_WIDTH 5 etherfabric.c 　
14410
 FCN_EE_SPI_HCMD_READ_LBNFCN_EE_SPI_HCMD_READ_LBN 15 etherfabric.c 　
14411
 FCN_EE_SPI_HCMD_READ_WIDTHFCN_EE_SPI_HCMD_READ_WIDTH 1 etherfabric.c 　
14412
 FCN_EE_SPI_READFCN_EE_SPI_READ 1 etherfabric.c 　
14413
 FCN_EE_SPI_WRITEFCN_EE_SPI_WRITE 0 etherfabric.c 　
14414
 FCN_EE_SPI_HCMD_DUBCNT_LBNFCN_EE_SPI_HCMD_DUBCNT_LBN 12 etherfabric.c 　
14415
 FCN_EE_SPI_HCMD_DUBCNT_WIDTHFCN_EE_SPI_HCMD_DUBCNT_WIDTH 2 etherfabric.c 　
14416
 FCN_EE_SPI_HCMD_ADBCNT_LBNFCN_EE_SPI_HCMD_ADBCNT_LBN 8 etherfabric.c 　
14417
 FCN_EE_SPI_HCMD_ADBCNT_WIDTHFCN_EE_SPI_HCMD_ADBCNT_WIDTH 2 etherfabric.c 　
14418
 FCN_EE_SPI_HCMD_ENC_LBNFCN_EE_SPI_HCMD_ENC_LBN 0 etherfabric.c 　
14419
 FCN_EE_SPI_HCMD_ENC_WIDTHFCN_EE_SPI_HCMD_ENC_WIDTH 8 etherfabric.c 　
14420
 FCN_EE_SPI_HADR_REGFCN_EE_SPI_HADR_REG 0x0110 etherfabric.c 　
14421
 FCN_EE_SPI_HADR_DUBYTE_LBNFCN_EE_SPI_HADR_DUBYTE_LBN 24 etherfabric.c 　
14422
 FCN_EE_SPI_HADR_DUBYTE_WIDTHFCN_EE_SPI_HADR_DUBYTE_WIDTH 8 etherfabric.c 　
14423
 FCN_EE_SPI_HADR_ADR_LBNFCN_EE_SPI_HADR_ADR_LBN 0 etherfabric.c 　
14424
 FCN_EE_SPI_HADR_ADR_WIDTHFCN_EE_SPI_HADR_ADR_WIDTH 24 etherfabric.c 　
14425
 FCN_EE_SPI_HDATA_REGFCN_EE_SPI_HDATA_REG 0x0120 etherfabric.c 　
14426
 FCN_EE_SPI_HDATA3_LBNFCN_EE_SPI_HDATA3_LBN 96 etherfabric.c 　
14427
 FCN_EE_SPI_HDATA3_WIDTHFCN_EE_SPI_HDATA3_WIDTH 32 etherfabric.c 　
14428
 FCN_EE_SPI_HDATA2_LBNFCN_EE_SPI_HDATA2_LBN 64 etherfabric.c 　
14429
 FCN_EE_SPI_HDATA2_WIDTHFCN_EE_SPI_HDATA2_WIDTH 32 etherfabric.c 　
14430
 FCN_EE_SPI_HDATA1_LBNFCN_EE_SPI_HDATA1_LBN 32 etherfabric.c 　
14431
 FCN_EE_SPI_HDATA1_WIDTHFCN_EE_SPI_HDATA1_WIDTH 32 etherfabric.c 　
14432
 FCN_EE_SPI_HDATA0_LBNFCN_EE_SPI_HDATA0_LBN 0 etherfabric.c 　
14433
 FCN_EE_SPI_HDATA0_WIDTHFCN_EE_SPI_HDATA0_WIDTH 32 etherfabric.c 　
14434
 FCN_EE_VPD_CFG_REGFCN_EE_VPD_CFG_REG 0x0140 etherfabric.c 　
14435
 FCN_EE_VPD_EN_LBNFCN_EE_VPD_EN_LBN 0 etherfabric.c 　
14436
 FCN_EE_VPD_EN_WIDTHFCN_EE_VPD_EN_WIDTH 1 etherfabric.c 　
14437
 FCN_EE_VPD_EN_AD9_MODE_LBNFCN_EE_VPD_EN_AD9_MODE_LBN 1 etherfabric.c 　
14438
 FCN_EE_VPD_EN_AD9_MODE_WIDTHFCN_EE_VPD_EN_AD9_MODE_WIDTH 1 etherfabric.c 　
14439
 FCN_EE_EE_CLOCK_DIV_LBNFCN_EE_EE_CLOCK_DIV_LBN 112 etherfabric.c 　
14440
 FCN_EE_EE_CLOCK_DIV_WIDTHFCN_EE_EE_CLOCK_DIV_WIDTH 7 etherfabric.c 　
14441
 FCN_EE_SF_CLOCK_DIV_LBNFCN_EE_SF_CLOCK_DIV_LBN 120 etherfabric.c 　
14442
 FCN_EE_SF_CLOCK_DIV_WIDTHFCN_EE_SF_CLOCK_DIV_WIDTH 7 etherfabric.c 　
14443
 FCN_NIC_STAT_REGFCN_NIC_STAT_REG 0x0200 etherfabric.c 　
14444
 FCN_ONCHIP_SRAM_LBNFCN_ONCHIP_SRAM_LBN 16 etherfabric.c 　
14445
 FCN_ONCHIP_SRAM_WIDTHFCN_ONCHIP_SRAM_WIDTH 1 etherfabric.c 　
14446
 FCN_SF_PRST_LBNFCN_SF_PRST_LBN 9 etherfabric.c 　
14447
 FCN_SF_PRST_WIDTHFCN_SF_PRST_WIDTH 1 etherfabric.c 　
14448
 FCN_EE_PRST_LBNFCN_EE_PRST_LBN 8 etherfabric.c 　
14449
 FCN_EE_PRST_WIDTHFCN_EE_PRST_WIDTH 1 etherfabric.c 　
14450
 FCN_EE_STRAP_LBNFCN_EE_STRAP_LBN 7 etherfabric.c 　
14451
 FCN_EE_STRAP_WIDTHFCN_EE_STRAP_WIDTH 1 etherfabric.c 　
14452
 FCN_PCI_PCIX_MODE_LBNFCN_PCI_PCIX_MODE_LBN 4 etherfabric.c 　
14453
 FCN_PCI_PCIX_MODE_WIDTHFCN_PCI_PCIX_MODE_WIDTH 3 etherfabric.c 　
14454
 FCN_PCI_PCIX_MODE_PCI33_DECODEFCN_PCI_PCIX_MODE_PCI33_DECODE 0 etherfabric.c 　
14455
 FCN_PCI_PCIX_MODE_PCI66_DECODEFCN_PCI_PCIX_MODE_PCI66_DECODE 1 etherfabric.c 　
14456
 FCN_PCI_PCIX_MODE_PCIX66_DECODEFCN_PCI_PCIX_MODE_PCIX66_DECODE 5 etherfabric.c 　
14457
 FCN_PCI_PCIX_MODE_PCIX100_DECODFCN_PCI_PCIX_MODE_PCIX100_DECOD 6 etherfabric.c 　
14458
 FCN_PCI_PCIX_MODE_PCIX133_DECODFCN_PCI_PCIX_MODE_PCIX133_DECOD 7 etherfabric.c 　
14459
 FCN_STRAP_ISCSI_EN_LBNFCN_STRAP_ISCSI_EN_LBN 3 etherfabric.c 　
14460
 FCN_STRAP_ISCSI_EN_WIDTHFCN_STRAP_ISCSI_EN_WIDTH 1 etherfabric.c 　
14461
 FCN_STRAP_PINS_LBNFCN_STRAP_PINS_LBN 0 etherfabric.c 　
14462
 FCN_STRAP_PINS_WIDTHFCN_STRAP_PINS_WIDTH 3 etherfabric.c 　
14463
 FCN_STRAP_10G_LBNFCN_STRAP_10G_LBN 2 etherfabric.c 　
14464
 FCN_STRAP_10G_WIDTHFCN_STRAP_10G_WIDTH 1 etherfabric.c 　
14465
 FCN_STRAP_DUAL_PORT_LBNFCN_STRAP_DUAL_PORT_LBN 1 etherfabric.c 　
14466
 FCN_STRAP_DUAL_PORT_WIDTHFCN_STRAP_DUAL_PORT_WIDTH 1 etherfabric.c 　
14467
 FCN_STRAP_PCIE_LBNFCN_STRAP_PCIE_LBN 0 etherfabric.c 　
14468
 FCN_STRAP_PCIE_WIDTHFCN_STRAP_PCIE_WIDTH 1 etherfabric.c 　
14469
 FALCON_REV_A0FALCON_REV_A0 0 etherfabric.c 　
14470
 FALCON_REV_A1FALCON_REV_A1 1 etherfabric.c 　
14471
 FALCON_REV_B0FALCON_REV_B0 2 etherfabric.c 　
14472
 FCN_GPIO_CTL_REG_KERFCN_GPIO_CTL_REG_KER 0x0210 etherfabric.c 　
14473
 FCN_GPIO_CTL_REG_KERFCN_GPIO_CTL_REG_KER 0x0210 etherfabric.c 　
14474
 FCN_GPIO3_OEN_LBNFCN_GPIO3_OEN_LBN 27 etherfabric.c 　
14475
 FCN_GPIO3_OEN_WIDTHFCN_GPIO3_OEN_WIDTH 1 etherfabric.c 　
14476
 FCN_GPIO2_OEN_LBNFCN_GPIO2_OEN_LBN 26 etherfabric.c 　
14477
 FCN_GPIO2_OEN_WIDTHFCN_GPIO2_OEN_WIDTH 1 etherfabric.c 　
14478
 FCN_GPIO1_OEN_LBNFCN_GPIO1_OEN_LBN 25 etherfabric.c 　
14479
 FCN_GPIO1_OEN_WIDTHFCN_GPIO1_OEN_WIDTH 1 etherfabric.c 　
14480
 FCN_GPIO0_OEN_LBNFCN_GPIO0_OEN_LBN 24 etherfabric.c 　
14481
 FCN_GPIO0_OEN_WIDTHFCN_GPIO0_OEN_WIDTH 1 etherfabric.c 　
14482
 FCN_GPIO3_OUT_LBNFCN_GPIO3_OUT_LBN 19 etherfabric.c 　
14483
 FCN_GPIO3_OUT_WIDTHFCN_GPIO3_OUT_WIDTH 1 etherfabric.c 　
14484
 FCN_GPIO2_OUT_LBNFCN_GPIO2_OUT_LBN 18 etherfabric.c 　
14485
 FCN_GPIO2_OUT_WIDTHFCN_GPIO2_OUT_WIDTH 1 etherfabric.c 　
14486
 FCN_GPIO1_OUT_LBNFCN_GPIO1_OUT_LBN 17 etherfabric.c 　
14487
 FCN_GPIO1_OUT_WIDTHFCN_GPIO1_OUT_WIDTH 1 etherfabric.c 　
14488
 FCN_GPIO0_OUT_LBNFCN_GPIO0_OUT_LBN 16 etherfabric.c 　
14489
 FCN_GPIO0_OUT_WIDTHFCN_GPIO0_OUT_WIDTH 1 etherfabric.c 　
14490
 FCN_GPIO3_IN_LBNFCN_GPIO3_IN_LBN 11 etherfabric.c 　
14491
 FCN_GPIO3_IN_WIDTHFCN_GPIO3_IN_WIDTH 1 etherfabric.c 　
14492
 FCN_GPIO2_IN_LBNFCN_GPIO2_IN_LBN 10 etherfabric.c 　
14493
 FCN_GPIO2_IN_WIDTHFCN_GPIO2_IN_WIDTH 1 etherfabric.c 　
14494
 FCN_GPIO1_IN_LBNFCN_GPIO1_IN_LBN 9 etherfabric.c 　
14495
 FCN_GPIO1_IN_WIDTHFCN_GPIO1_IN_WIDTH 1 etherfabric.c 　
14496
 FCN_GPIO0_IN_LBNFCN_GPIO0_IN_LBN 8 etherfabric.c 　
14497
 FCN_GPIO0_IN_WIDTHFCN_GPIO0_IN_WIDTH 1 etherfabric.c 　
14498
 FCN_FLASH_PRESENT_LBNFCN_FLASH_PRESENT_LBN 7 etherfabric.c 　
14499
 FCN_FLASH_PRESENT_WIDTHFCN_FLASH_PRESENT_WIDTH 1 etherfabric.c 　
14500
 FCN_EEPROM_PRESENT_LBNFCN_EEPROM_PRESENT_LBN 6 etherfabric.c 　
14501
 FCN_EEPROM_PRESENT_WIDTHFCN_EEPROM_PRESENT_WIDTH 1 etherfabric.c 　
14502
 FCN_BOOTED_USING_NVDEVICE_LBNFCN_BOOTED_USING_NVDEVICE_LBN 3 etherfabric.c 　
14503
 FCN_BOOTED_USING_NVDEVICE_WIDTHFCN_BOOTED_USING_NVDEVICE_WIDTH 1 etherfabric.c 　
14504
 FCN_NV_MAGIC_NUMBERFCN_NV_MAGIC_NUMBER 0xFA1C etherfabric.c 　
14505
 FCN_GLB_CTL_REG_KERFCN_GLB_CTL_REG_KER 0x0220 etherfabric.c 　
14506
 FCN_EXT_PHY_RST_CTL_LBNFCN_EXT_PHY_RST_CTL_LBN 63 etherfabric.c 　
14507
 FCN_EXT_PHY_RST_CTL_WIDTHFCN_EXT_PHY_RST_CTL_WIDTH 1 etherfabric.c 　
14508
 FCN_PCIE_SD_RST_CTL_LBNFCN_PCIE_SD_RST_CTL_LBN 61 etherfabric.c 　
14509
 FCN_PCIE_SD_RST_CTL_WIDTHFCN_PCIE_SD_RST_CTL_WIDTH 1 etherfabric.c 　
14510
 FCN_PCIE_STCK_RST_CTL_LBNFCN_PCIE_STCK_RST_CTL_LBN 59 etherfabric.c 　
14511
 FCN_PCIE_STCK_RST_CTL_WIDTHFCN_PCIE_STCK_RST_CTL_WIDTH 1 etherfabric.c 　
14512
 FCN_PCIE_NSTCK_RST_CTL_LBNFCN_PCIE_NSTCK_RST_CTL_LBN 58 etherfabric.c 　
14513
 FCN_PCIE_NSTCK_RST_CTL_WIDTHFCN_PCIE_NSTCK_RST_CTL_WIDTH 1 etherfabric.c 　
14514
 FCN_PCIE_CORE_RST_CTL_LBNFCN_PCIE_CORE_RST_CTL_LBN 57 etherfabric.c 　
14515
 FCN_PCIE_CORE_RST_CTL_WIDTHFCN_PCIE_CORE_RST_CTL_WIDTH 1 etherfabric.c 　
14516
 FCN_EE_RST_CTL_LBNFCN_EE_RST_CTL_LBN 49 etherfabric.c 　
14517
 FCN_EE_RST_CTL_WIDTHFCN_EE_RST_CTL_WIDTH 1 etherfabric.c 　
14518
 FCN_RST_EXT_PHY_LBNFCN_RST_EXT_PHY_LBN 31 etherfabric.c 　
14519
 FCN_RST_EXT_PHY_WIDTHFCN_RST_EXT_PHY_WIDTH 1 etherfabric.c 　
14520
 FCN_EXT_PHY_RST_DUR_LBNFCN_EXT_PHY_RST_DUR_LBN 1 etherfabric.c 　
14521
 FCN_EXT_PHY_RST_DUR_WIDTHFCN_EXT_PHY_RST_DUR_WIDTH 3 etherfabric.c 　
14522
 FCN_SWRST_LBNFCN_SWRST_LBN 0 etherfabric.c 　
14523
 FCN_SWRST_WIDTHFCN_SWRST_WIDTH 1 etherfabric.c 　
14524
 INCLUDE_IN_RESETINCLUDE_IN_RESET 0 etherfabric.c 　
14525
 EXCLUDE_FROM_RESETEXCLUDE_FROM_RESET 1 etherfabric.c 　
14526
 FCN_ALTERA_BUILD_REG_KERFCN_ALTERA_BUILD_REG_KER 0x0300 etherfabric.c 　
14527
 FCN_VER_MAJOR_LBNFCN_VER_MAJOR_LBN 24 etherfabric.c 　
14528
 FCN_VER_MAJOR_WIDTHFCN_VER_MAJOR_WIDTH 8 etherfabric.c 　
14529
 FCN_VER_MINOR_LBNFCN_VER_MINOR_LBN 16 etherfabric.c 　
14530
 FCN_VER_MINOR_WIDTHFCN_VER_MINOR_WIDTH 8 etherfabric.c 　
14531
 FCN_VER_BUILD_LBNFCN_VER_BUILD_LBN 0 etherfabric.c 　
14532
 FCN_VER_BUILD_WIDTHFCN_VER_BUILD_WIDTH 16 etherfabric.c 　
14533
 FCN_VER_ALL_LBNFCN_VER_ALL_LBN 0 etherfabric.c 　
14534
 FCN_VER_ALL_WIDTHFCN_VER_ALL_WIDTH 32 etherfabric.c 　
14535
 FCN_SPARE_REG_KERFCN_SPARE_REG_KER 0x310 etherfabric.c 　
14536
 FCN_MEM_PERR_EN_TX_DATA_LBNFCN_MEM_PERR_EN_TX_DATA_LBN 72 etherfabric.c 　
14537
 FCN_MEM_PERR_EN_TX_DATA_WIDTHFCN_MEM_PERR_EN_TX_DATA_WIDTH 2 etherfabric.c 　
14538
 FCN_TIMER_CMD_REG_KERFCN_TIMER_CMD_REG_KER 0x420 etherfabric.c 　
14539
 FCN_TIMER_MODE_LBNFCN_TIMER_MODE_LBN 12 etherfabric.c 　
14540
 FCN_TIMER_MODE_WIDTHFCN_TIMER_MODE_WIDTH 2 etherfabric.c 　
14541
 FCN_TIMER_MODE_DISFCN_TIMER_MODE_DIS 0 etherfabric.c 　
14542
 FCN_TIMER_MODE_INT_HLDOFFFCN_TIMER_MODE_INT_HLDOFF 1 etherfabric.c 　
14543
 FCN_TIMER_VAL_LBNFCN_TIMER_VAL_LBN 0 etherfabric.c 　
14544
 FCN_TIMER_VAL_WIDTHFCN_TIMER_VAL_WIDTH 12 etherfabric.c 　
14545
 FCN_RX_CFG_REG_KERFCN_RX_CFG_REG_KER 0x800 etherfabric.c 　
14546
 FCN_RX_XOFF_EN_LBNFCN_RX_XOFF_EN_LBN 0 etherfabric.c 　
14547
 FCN_RX_XOFF_EN_WIDTHFCN_RX_XOFF_EN_WIDTH 1 etherfabric.c 　
14548
 FCN_SRM_RX_DC_CFG_REG_KERFCN_SRM_RX_DC_CFG_REG_KER 0x610 etherfabric.c 　
14549
 FCN_SRM_RX_DC_BASE_ADR_LBNFCN_SRM_RX_DC_BASE_ADR_LBN 0 etherfabric.c 　
14550
 FCN_SRM_RX_DC_BASE_ADR_WIDTHFCN_SRM_RX_DC_BASE_ADR_WIDTH 21 etherfabric.c 　
14551
 FCN_SRM_TX_DC_CFG_REG_KERFCN_SRM_TX_DC_CFG_REG_KER 0x620 etherfabric.c 　
14552
 FCN_SRM_TX_DC_BASE_ADR_LBNFCN_SRM_TX_DC_BASE_ADR_LBN 0 etherfabric.c 　
14553
 FCN_SRM_TX_DC_BASE_ADR_WIDTHFCN_SRM_TX_DC_BASE_ADR_WIDTH 21 etherfabric.c 　
14554
 FCN_SRM_CFG_REG_KERFCN_SRM_CFG_REG_KER 0x630 etherfabric.c 　
14555
 FCN_SRAM_OOB_ADR_INTEN_LBNFCN_SRAM_OOB_ADR_INTEN_LBN 5 etherfabric.c 　
14556
 FCN_SRAM_OOB_ADR_INTEN_WIDTHFCN_SRAM_OOB_ADR_INTEN_WIDTH 1 etherfabric.c 　
14557
 FCN_SRAM_OOB_BUF_INTEN_LBNFCN_SRAM_OOB_BUF_INTEN_LBN 4 etherfabric.c 　
14558
 FCN_SRAM_OOB_BUF_INTEN_WIDTHFCN_SRAM_OOB_BUF_INTEN_WIDTH 1 etherfabric.c 　
14559
 FCN_SRAM_OOB_BT_INIT_EN_LBNFCN_SRAM_OOB_BT_INIT_EN_LBN 3 etherfabric.c 　
14560
 FCN_SRAM_OOB_BT_INIT_EN_WIDTHFCN_SRAM_OOB_BT_INIT_EN_WIDTH 1 etherfabric.c 　
14561
 FCN_SRM_NUM_BANK_LBNFCN_SRM_NUM_BANK_LBN 2 etherfabric.c 　
14562
 FCN_SRM_NUM_BANK_WIDTHFCN_SRM_NUM_BANK_WIDTH 1 etherfabric.c 　
14563
 FCN_SRM_BANK_SIZE_LBNFCN_SRM_BANK_SIZE_LBN 0 etherfabric.c 　
14564
 FCN_SRM_BANK_SIZE_WIDTHFCN_SRM_BANK_SIZE_WIDTH 2 etherfabric.c 　
14565
 FCN_SRM_NUM_BANKS_AND_BANK_SIZEFCN_SRM_NUM_BANKS_AND_BANK_SIZE 0 etherfabric.c 　
14566
 FCN_SRM_NUM_BANKS_AND_BANK_SIZEFCN_SRM_NUM_BANKS_AND_BANK_SIZE 3 etherfabric.c 　
14567
 FCN_RX_CFG_REG_KERFCN_RX_CFG_REG_KER 0x800 etherfabric.c 　
14568
 FCN_RX_INGR_EN_B0_LBNFCN_RX_INGR_EN_B0_LBN 47 etherfabric.c 　
14569
 FCN_RX_INGR_EN_B0_WIDTHFCN_RX_INGR_EN_B0_WIDTH 1 etherfabric.c 　
14570
 FCN_RX_USR_BUF_SIZE_B0_LBNFCN_RX_USR_BUF_SIZE_B0_LBN 19 etherfabric.c 　
14571
 FCN_RX_USR_BUF_SIZE_B0_WIDTHFCN_RX_USR_BUF_SIZE_B0_WIDTH 9 etherfabric.c 　
14572
 FCN_RX_XON_MAC_TH_B0_LBNFCN_RX_XON_MAC_TH_B0_LBN 10 etherfabric.c 　
14573
 FCN_RX_XON_MAC_TH_B0_WIDTHFCN_RX_XON_MAC_TH_B0_WIDTH 9 etherfabric.c 　
14574
 FCN_RX_XOFF_MAC_TH_B0_LBNFCN_RX_XOFF_MAC_TH_B0_LBN 1 etherfabric.c 　
14575
 FCN_RX_XOFF_MAC_TH_B0_WIDTHFCN_RX_XOFF_MAC_TH_B0_WIDTH 9 etherfabric.c 　
14576
 FCN_RX_XOFF_MAC_EN_B0_LBNFCN_RX_XOFF_MAC_EN_B0_LBN 0 etherfabric.c 　
14577
 FCN_RX_XOFF_MAC_EN_B0_WIDTHFCN_RX_XOFF_MAC_EN_B0_WIDTH 1 etherfabric.c 　
14578
 FCN_RX_USR_BUF_SIZE_A1_LBNFCN_RX_USR_BUF_SIZE_A1_LBN 11 etherfabric.c 　
14579
 FCN_RX_USR_BUF_SIZE_A1_WIDTHFCN_RX_USR_BUF_SIZE_A1_WIDTH 9 etherfabric.c 　
14580
 FCN_RX_XON_MAC_TH_A1_LBNFCN_RX_XON_MAC_TH_A1_LBN 6 etherfabric.c 　
14581
 FCN_RX_XON_MAC_TH_A1_WIDTHFCN_RX_XON_MAC_TH_A1_WIDTH 5 etherfabric.c 　
14582
 FCN_RX_XOFF_MAC_TH_A1_LBNFCN_RX_XOFF_MAC_TH_A1_LBN 1 etherfabric.c 　
14583
 FCN_RX_XOFF_MAC_TH_A1_WIDTHFCN_RX_XOFF_MAC_TH_A1_WIDTH 5 etherfabric.c 　
14584
 FCN_RX_XOFF_MAC_EN_A1_LBNFCN_RX_XOFF_MAC_EN_A1_LBN 0 etherfabric.c 　
14585
 FCN_RX_XOFF_MAC_EN_A1_WIDTHFCN_RX_XOFF_MAC_EN_A1_WIDTH 1 etherfabric.c 　
14586
 FCN_RX_USR_BUF_SIZE_A1_LBNFCN_RX_USR_BUF_SIZE_A1_LBN 11 etherfabric.c 　
14587
 FCN_RX_USR_BUF_SIZE_A1_WIDTHFCN_RX_USR_BUF_SIZE_A1_WIDTH 9 etherfabric.c 　
14588
 FCN_RX_XOFF_MAC_EN_A1_LBNFCN_RX_XOFF_MAC_EN_A1_LBN 0 etherfabric.c 　
14589
 FCN_RX_XOFF_MAC_EN_A1_WIDTHFCN_RX_XOFF_MAC_EN_A1_WIDTH 1 etherfabric.c 　
14590
 FCN_RX_FILTER_CTL_REG_KERFCN_RX_FILTER_CTL_REG_KER 0x810 etherfabric.c 　
14591
 FCN_UDP_FULL_SRCH_LIMIT_LBNFCN_UDP_FULL_SRCH_LIMIT_LBN 32 etherfabric.c 　
14592
 FCN_UDP_FULL_SRCH_LIMIT_WIDTHFCN_UDP_FULL_SRCH_LIMIT_WIDTH 8 etherfabric.c 　
14593
 FCN_NUM_KER_LBNFCN_NUM_KER_LBN 24 etherfabric.c 　
14594
 FCN_NUM_KER_WIDTHFCN_NUM_KER_WIDTH 2 etherfabric.c 　
14595
 FCN_UDP_WILD_SRCH_LIMIT_LBNFCN_UDP_WILD_SRCH_LIMIT_LBN 16 etherfabric.c 　
14596
 FCN_UDP_WILD_SRCH_LIMIT_WIDTHFCN_UDP_WILD_SRCH_LIMIT_WIDTH 8 etherfabric.c 　
14597
 FCN_TCP_WILD_SRCH_LIMIT_LBNFCN_TCP_WILD_SRCH_LIMIT_LBN 8 etherfabric.c 　
14598
 FCN_TCP_WILD_SRCH_LIMIT_WIDTHFCN_TCP_WILD_SRCH_LIMIT_WIDTH 8 etherfabric.c 　
14599
 FCN_TCP_FULL_SRCH_LIMIT_LBNFCN_TCP_FULL_SRCH_LIMIT_LBN 0 etherfabric.c 　
14600
 FCN_TCP_FULL_SRCH_LIMIT_WIDTHFCN_TCP_FULL_SRCH_LIMIT_WIDTH 8 etherfabric.c 　
14601
 FCN_RX_FLUSH_DESCQ_REG_KERFCN_RX_FLUSH_DESCQ_REG_KER 0x0820 etherfabric.c 　
14602
 FCN_RX_FLUSH_DESCQ_CMD_LBNFCN_RX_FLUSH_DESCQ_CMD_LBN 24 etherfabric.c 　
14603
 FCN_RX_FLUSH_DESCQ_CMD_WIDTHFCN_RX_FLUSH_DESCQ_CMD_WIDTH 1 etherfabric.c 　
14604
 FCN_RX_FLUSH_DESCQ_LBNFCN_RX_FLUSH_DESCQ_LBN 0 etherfabric.c 　
14605
 FCN_RX_FLUSH_DESCQ_WIDTHFCN_RX_FLUSH_DESCQ_WIDTH 12 etherfabric.c 　
14606
 FCN_RX_DESC_UPD_REG_KERFCN_RX_DESC_UPD_REG_KER 0x0830 etherfabric.c 　
14607
 FCN_RX_DESC_WPTR_LBNFCN_RX_DESC_WPTR_LBN 96 etherfabric.c 　
14608
 FCN_RX_DESC_WPTR_WIDTHFCN_RX_DESC_WPTR_WIDTH 12 etherfabric.c 　
14609
 FCN_RX_DESC_UPD_REG_KER_DWORDFCN_RX_DESC_UPD_REG_KER_DWORD ( FCN_RX_DESC_UPD_REG_KER + 12 ) etherfabric.c 　
14610
 FCN_RX_DESC_WPTR_DWORD_LBNFCN_RX_DESC_WPTR_DWORD_LBN 0 etherfabric.c 　
14611
 FCN_RX_DESC_WPTR_DWORD_WIDTHFCN_RX_DESC_WPTR_DWORD_WIDTH 12 etherfabric.c 　
14612
 FCN_RX_DC_CFG_REG_KERFCN_RX_DC_CFG_REG_KER 0x840 etherfabric.c 　
14613
 FCN_RX_DC_SIZE_LBNFCN_RX_DC_SIZE_LBN 0 etherfabric.c 　
14614
 FCN_RX_DC_SIZE_WIDTHFCN_RX_DC_SIZE_WIDTH 2 etherfabric.c 　
14615
 FCN_RX_SELF_RST_REG_KERFCN_RX_SELF_RST_REG_KER 0x890 etherfabric.c 　
14616
 FCN_RX_ISCSI_DIS_LBNFCN_RX_ISCSI_DIS_LBN 17 etherfabric.c 　
14617
 FCN_RX_ISCSI_DIS_WIDTHFCN_RX_ISCSI_DIS_WIDTH 1 etherfabric.c 　
14618
 FCN_RX_NODESC_WAIT_DIS_LBNFCN_RX_NODESC_WAIT_DIS_LBN 9 etherfabric.c 　
14619
 FCN_RX_NODESC_WAIT_DIS_WIDTHFCN_RX_NODESC_WAIT_DIS_WIDTH 1 etherfabric.c 　
14620
 FCN_RX_RECOVERY_EN_LBNFCN_RX_RECOVERY_EN_LBN 8 etherfabric.c 　
14621
 FCN_RX_RECOVERY_EN_WIDTHFCN_RX_RECOVERY_EN_WIDTH 1 etherfabric.c 　
14622
 FCN_TX_FLUSH_DESCQ_REG_KERFCN_TX_FLUSH_DESCQ_REG_KER 0x0a00 etherfabric.c 　
14623
 FCN_TX_FLUSH_DESCQ_CMD_LBNFCN_TX_FLUSH_DESCQ_CMD_LBN 12 etherfabric.c 　
14624
 FCN_TX_FLUSH_DESCQ_CMD_WIDTHFCN_TX_FLUSH_DESCQ_CMD_WIDTH 1 etherfabric.c 　
14625
 FCN_TX_FLUSH_DESCQ_LBNFCN_TX_FLUSH_DESCQ_LBN 0 etherfabric.c 　
14626
 FCN_TX_FLUSH_DESCQ_WIDTHFCN_TX_FLUSH_DESCQ_WIDTH 12 etherfabric.c 　
14627
 FCN_TX_CFG2_REG_KERFCN_TX_CFG2_REG_KER 0xa80 etherfabric.c 　
14628
 FCN_TX_DIS_NON_IP_EV_LBNFCN_TX_DIS_NON_IP_EV_LBN 17 etherfabric.c 　
14629
 FCN_TX_DIS_NON_IP_EV_WIDTHFCN_TX_DIS_NON_IP_EV_WIDTH 1 etherfabric.c 　
14630
 FCN_TX_DESC_UPD_REG_KERFCN_TX_DESC_UPD_REG_KER 0x0a10 etherfabric.c 　
14631
 FCN_TX_DESC_WPTR_LBNFCN_TX_DESC_WPTR_LBN 96 etherfabric.c 　
14632
 FCN_TX_DESC_WPTR_WIDTHFCN_TX_DESC_WPTR_WIDTH 12 etherfabric.c 　
14633
 FCN_TX_DESC_UPD_REG_KER_DWORDFCN_TX_DESC_UPD_REG_KER_DWORD ( FCN_TX_DESC_UPD_REG_KER + 12 ) etherfabric.c 　
14634
 FCN_TX_DESC_WPTR_DWORD_LBNFCN_TX_DESC_WPTR_DWORD_LBN 0 etherfabric.c 　
14635
 FCN_TX_DESC_WPTR_DWORD_WIDTHFCN_TX_DESC_WPTR_DWORD_WIDTH 12 etherfabric.c 　
14636
 FCN_TX_DC_CFG_REG_KERFCN_TX_DC_CFG_REG_KER 0xa20 etherfabric.c 　
14637
 FCN_TX_DC_SIZE_LBNFCN_TX_DC_SIZE_LBN 0 etherfabric.c 　
14638
 FCN_TX_DC_SIZE_WIDTHFCN_TX_DC_SIZE_WIDTH 2 etherfabric.c 　
14639
 FCN_MD_TXD_REG_KERFCN_MD_TXD_REG_KER 0xc00 etherfabric.c 　
14640
 FCN_MD_TXD_LBNFCN_MD_TXD_LBN 0 etherfabric.c 　
14641
 FCN_MD_TXD_WIDTHFCN_MD_TXD_WIDTH 16 etherfabric.c 　
14642
 FCN_MD_RXD_REG_KERFCN_MD_RXD_REG_KER 0xc10 etherfabric.c 　
14643
 FCN_MD_RXD_LBNFCN_MD_RXD_LBN 0 etherfabric.c 　
14644
 FCN_MD_RXD_WIDTHFCN_MD_RXD_WIDTH 16 etherfabric.c 　
14645
 FCN_MD_CS_REG_KERFCN_MD_CS_REG_KER 0xc20 etherfabric.c 　
14646
 FCN_MD_GC_LBNFCN_MD_GC_LBN 4 etherfabric.c 　
14647
 FCN_MD_GC_WIDTHFCN_MD_GC_WIDTH 1 etherfabric.c 　
14648
 FCN_MD_RIC_LBNFCN_MD_RIC_LBN 2 etherfabric.c 　
14649
 FCN_MD_RIC_WIDTHFCN_MD_RIC_WIDTH 1 etherfabric.c 　
14650
 FCN_MD_RDC_LBNFCN_MD_RDC_LBN 1 etherfabric.c 　
14651
 FCN_MD_RDC_WIDTHFCN_MD_RDC_WIDTH 1 etherfabric.c 　
14652
 FCN_MD_WRC_LBNFCN_MD_WRC_LBN 0 etherfabric.c 　
14653
 FCN_MD_WRC_WIDTHFCN_MD_WRC_WIDTH 1 etherfabric.c 　
14654
 FCN_MD_PHY_ADR_REG_KERFCN_MD_PHY_ADR_REG_KER 0xc30 etherfabric.c 　
14655
 FCN_MD_PHY_ADR_LBNFCN_MD_PHY_ADR_LBN 0 etherfabric.c 　
14656
 FCN_MD_PHY_ADR_WIDTHFCN_MD_PHY_ADR_WIDTH 16 etherfabric.c 　
14657
 FCN_MD_ID_REG_KERFCN_MD_ID_REG_KER 0xc40 etherfabric.c 　
14658
 FCN_MD_PRT_ADR_LBNFCN_MD_PRT_ADR_LBN 11 etherfabric.c 　
14659
 FCN_MD_PRT_ADR_WIDTHFCN_MD_PRT_ADR_WIDTH 5 etherfabric.c 　
14660
 FCN_MD_DEV_ADR_LBNFCN_MD_DEV_ADR_LBN 6 etherfabric.c 　
14661
 FCN_MD_DEV_ADR_WIDTHFCN_MD_DEV_ADR_WIDTH 5 etherfabric.c 　
14662
 FCN_MD_STAT_REG_KERFCN_MD_STAT_REG_KER 0xc50 etherfabric.c 　
14663
 FCN_MD_PINT_LBNFCN_MD_PINT_LBN 4 etherfabric.c 　
14664
 FCN_MD_PINT_WIDTHFCN_MD_PINT_WIDTH 1 etherfabric.c 　
14665
 FCN_MD_DONE_LBNFCN_MD_DONE_LBN 3 etherfabric.c 　
14666
 FCN_MD_DONE_WIDTHFCN_MD_DONE_WIDTH 1 etherfabric.c 　
14667
 FCN_MD_BSERR_LBNFCN_MD_BSERR_LBN 2 etherfabric.c 　
14668
 FCN_MD_BSERR_WIDTHFCN_MD_BSERR_WIDTH 1 etherfabric.c 　
14669
 FCN_MD_LNFL_LBNFCN_MD_LNFL_LBN 1 etherfabric.c 　
14670
 FCN_MD_LNFL_WIDTHFCN_MD_LNFL_WIDTH 1 etherfabric.c 　
14671
 FCN_MD_BSY_LBNFCN_MD_BSY_LBN 0 etherfabric.c 　
14672
 FCN_MD_BSY_WIDTHFCN_MD_BSY_WIDTH 1 etherfabric.c 　
14673
 FCN_MAC0_CTRL_REG_KERFCN_MAC0_CTRL_REG_KER 0xc80 etherfabric.c 　
14674
 FCN_MAC1_CTRL_REG_KERFCN_MAC1_CTRL_REG_KER 0xc90 etherfabric.c 　
14675
 FCN_MAC_XOFF_VAL_LBNFCN_MAC_XOFF_VAL_LBN 16 etherfabric.c 　
14676
 FCN_MAC_XOFF_VAL_WIDTHFCN_MAC_XOFF_VAL_WIDTH 16 etherfabric.c 　
14677
 FCN_MAC_BCAD_ACPT_LBNFCN_MAC_BCAD_ACPT_LBN 4 etherfabric.c 　
14678
 FCN_MAC_BCAD_ACPT_WIDTHFCN_MAC_BCAD_ACPT_WIDTH 1 etherfabric.c 　
14679
 FCN_MAC_UC_PROM_LBNFCN_MAC_UC_PROM_LBN 3 etherfabric.c 　
14680
 FCN_MAC_UC_PROM_WIDTHFCN_MAC_UC_PROM_WIDTH 1 etherfabric.c 　
14681
 FCN_MAC_LINK_STATUS_LBNFCN_MAC_LINK_STATUS_LBN 2 etherfabric.c 　
14682
 FCN_MAC_LINK_STATUS_WIDTHFCN_MAC_LINK_STATUS_WIDTH 1 etherfabric.c 　
14683
 FCN_MAC_SPEED_LBNFCN_MAC_SPEED_LBN 0 etherfabric.c 　
14684
 FCN_MAC_SPEED_WIDTHFCN_MAC_SPEED_WIDTH 2 etherfabric.c 　
14685
 XX_TXDRV_DEQ_DEFAULTXX_TXDRV_DEQ_DEFAULT 0xe etherfabric.c deq=.6
14686
 XX_TXDRV_DTX_DEFAULTXX_TXDRV_DTX_DEFAULT 0x5 etherfabric.c 1.25
14687
 XX_SD_CTL_DRV_DEFAULTXX_SD_CTL_DRV_DEFAULT 0 etherfabric.c 20mA
14688
 FALCON_GMAC_REGBANKFALCON_GMAC_REGBANK 0xe00 etherfabric.c 　
14689
 FALCON_GMAC_REGBANK_SIZEFALCON_GMAC_REGBANK_SIZE 0x200 etherfabric.c 　
14690
 FALCON_GMAC_REG_SIZEFALCON_GMAC_REG_SIZE 0x10 etherfabric.c 　
14691
 FALCON_XMAC_REGBANKFALCON_XMAC_REGBANK 0x1200 etherfabric.c 　
14692
 FALCON_XMAC_REGBANK_SIZEFALCON_XMAC_REGBANK_SIZE 0x200 etherfabric.c 　
14693
 FALCON_XMAC_REG_SIZEFALCON_XMAC_REG_SIZE 0x10 etherfabric.c 　
14694
 FCN_XM_ADR_LO_REG_MACFCN_XM_ADR_LO_REG_MAC 0x00 etherfabric.c 　
14695
 FCN_XM_ADR_3_LBNFCN_XM_ADR_3_LBN 24 etherfabric.c 　
14696
 FCN_XM_ADR_3_WIDTHFCN_XM_ADR_3_WIDTH 8 etherfabric.c 　
14697
 FCN_XM_ADR_2_LBNFCN_XM_ADR_2_LBN 16 etherfabric.c 　
14698
 FCN_XM_ADR_2_WIDTHFCN_XM_ADR_2_WIDTH 8 etherfabric.c 　
14699
 FCN_XM_ADR_1_LBNFCN_XM_ADR_1_LBN 8 etherfabric.c 　
14700
 FCN_XM_ADR_1_WIDTHFCN_XM_ADR_1_WIDTH 8 etherfabric.c 　
14701
 FCN_XM_ADR_0_LBNFCN_XM_ADR_0_LBN 0 etherfabric.c 　
14702
 FCN_XM_ADR_0_WIDTHFCN_XM_ADR_0_WIDTH 8 etherfabric.c 　
14703
 FCN_XM_ADR_HI_REG_MACFCN_XM_ADR_HI_REG_MAC 0x01 etherfabric.c 　
14704
 FCN_XM_ADR_5_LBNFCN_XM_ADR_5_LBN 8 etherfabric.c 　
14705
 FCN_XM_ADR_5_WIDTHFCN_XM_ADR_5_WIDTH 8 etherfabric.c 　
14706
 FCN_XM_ADR_4_LBNFCN_XM_ADR_4_LBN 0 etherfabric.c 　
14707
 FCN_XM_ADR_4_WIDTHFCN_XM_ADR_4_WIDTH 8 etherfabric.c 　
14708
 FCN_XM_GLB_CFG_REG_MACFCN_XM_GLB_CFG_REG_MAC 0x02 etherfabric.c 　
14709
 FCN_XM_RX_STAT_EN_LBNFCN_XM_RX_STAT_EN_LBN 11 etherfabric.c 　
14710
 FCN_XM_RX_STAT_EN_WIDTHFCN_XM_RX_STAT_EN_WIDTH 1 etherfabric.c 　
14711
 FCN_XM_TX_STAT_EN_LBNFCN_XM_TX_STAT_EN_LBN 10 etherfabric.c 　
14712
 FCN_XM_TX_STAT_EN_WIDTHFCN_XM_TX_STAT_EN_WIDTH 1 etherfabric.c 　
14713
 FCN_XM_RX_JUMBO_MODE_LBNFCN_XM_RX_JUMBO_MODE_LBN 6 etherfabric.c 　
14714
 FCN_XM_RX_JUMBO_MODE_WIDTHFCN_XM_RX_JUMBO_MODE_WIDTH 1 etherfabric.c 　
14715
 FCN_XM_CORE_RST_LBNFCN_XM_CORE_RST_LBN 0 etherfabric.c 　
14716
 FCN_XM_CORE_RST_WIDTHFCN_XM_CORE_RST_WIDTH 1 etherfabric.c 　
14717
 FCN_XM_TX_CFG_REG_MACFCN_XM_TX_CFG_REG_MAC 0x03 etherfabric.c 　
14718
 FCN_XM_IPG_LBNFCN_XM_IPG_LBN 16 etherfabric.c 　
14719
 FCN_XM_IPG_WIDTHFCN_XM_IPG_WIDTH 4 etherfabric.c 　
14720
 FCN_XM_FCNTL_LBNFCN_XM_FCNTL_LBN 10 etherfabric.c 　
14721
 FCN_XM_FCNTL_WIDTHFCN_XM_FCNTL_WIDTH 1 etherfabric.c 　
14722
 FCN_XM_TXCRC_LBNFCN_XM_TXCRC_LBN 8 etherfabric.c 　
14723
 FCN_XM_TXCRC_WIDTHFCN_XM_TXCRC_WIDTH 1 etherfabric.c 　
14724
 FCN_XM_AUTO_PAD_LBNFCN_XM_AUTO_PAD_LBN 5 etherfabric.c 　
14725
 FCN_XM_AUTO_PAD_WIDTHFCN_XM_AUTO_PAD_WIDTH 1 etherfabric.c 　
14726
 FCN_XM_TX_PRMBL_LBNFCN_XM_TX_PRMBL_LBN 2 etherfabric.c 　
14727
 FCN_XM_TX_PRMBL_WIDTHFCN_XM_TX_PRMBL_WIDTH 1 etherfabric.c 　
14728
 FCN_XM_TXEN_LBNFCN_XM_TXEN_LBN 1 etherfabric.c 　
14729
 FCN_XM_TXEN_WIDTHFCN_XM_TXEN_WIDTH 1 etherfabric.c 　
14730
 FCN_XM_RX_CFG_REG_MACFCN_XM_RX_CFG_REG_MAC 0x04 etherfabric.c 　
14731
 FCN_XM_PASS_CRC_ERR_LBNFCN_XM_PASS_CRC_ERR_LBN 25 etherfabric.c 　
14732
 FCN_XM_PASS_CRC_ERR_WIDTHFCN_XM_PASS_CRC_ERR_WIDTH 1 etherfabric.c 　
14733
 FCN_XM_AUTO_DEPAD_LBNFCN_XM_AUTO_DEPAD_LBN 8 etherfabric.c 　
14734
 FCN_XM_AUTO_DEPAD_WIDTHFCN_XM_AUTO_DEPAD_WIDTH 1 etherfabric.c 　
14735
 FCN_XM_RXEN_LBNFCN_XM_RXEN_LBN 1 etherfabric.c 　
14736
 FCN_XM_RXEN_WIDTHFCN_XM_RXEN_WIDTH 1 etherfabric.c 　
14737
 FCN_XM_MGT_INT_MSK_REG_MAC_B0FCN_XM_MGT_INT_MSK_REG_MAC_B0 0x5 etherfabric.c 　
14738
 FCN_XM_MSK_PRMBLE_ERR_LBNFCN_XM_MSK_PRMBLE_ERR_LBN 2 etherfabric.c 　
14739
 FCN_XM_MSK_PRMBLE_ERR_WIDTHFCN_XM_MSK_PRMBLE_ERR_WIDTH 1 etherfabric.c 　
14740
 FCN_XM_MSK_RMTFLT_LBNFCN_XM_MSK_RMTFLT_LBN 1 etherfabric.c 　
14741
 FCN_XM_MSK_RMTFLT_WIDTHFCN_XM_MSK_RMTFLT_WIDTH 1 etherfabric.c 　
14742
 FCN_XM_MSK_LCLFLT_LBNFCN_XM_MSK_LCLFLT_LBN 0 etherfabric.c 　
14743
 FCN_XM_MSK_LCLFLT_WIDTHFCN_XM_MSK_LCLFLT_WIDTH 1 etherfabric.c 　
14744
 FCN_XM_FC_REG_MACFCN_XM_FC_REG_MAC 0x7 etherfabric.c 　
14745
 FCN_XM_PAUSE_TIME_LBNFCN_XM_PAUSE_TIME_LBN 16 etherfabric.c 　
14746
 FCN_XM_PAUSE_TIME_WIDTHFCN_XM_PAUSE_TIME_WIDTH 16 etherfabric.c 　
14747
 FCN_XM_DIS_FCNTL_LBNFCN_XM_DIS_FCNTL_LBN 0 etherfabric.c 　
14748
 FCN_XM_DIS_FCNTL_WIDTHFCN_XM_DIS_FCNTL_WIDTH 1 etherfabric.c 　
14749
 FCN_XM_TX_PARAM_REG_MACFCN_XM_TX_PARAM_REG_MAC 0x0d etherfabric.c 　
14750
 FCN_XM_TX_JUMBO_MODE_LBNFCN_XM_TX_JUMBO_MODE_LBN 31 etherfabric.c 　
14751
 FCN_XM_TX_JUMBO_MODE_WIDTHFCN_XM_TX_JUMBO_MODE_WIDTH 1 etherfabric.c 　
14752
 FCN_XM_MAX_TX_FRM_SIZE_LBNFCN_XM_MAX_TX_FRM_SIZE_LBN 16 etherfabric.c 　
14753
 FCN_XM_MAX_TX_FRM_SIZE_WIDTHFCN_XM_MAX_TX_FRM_SIZE_WIDTH 14 etherfabric.c 　
14754
 FCN_XM_ACPT_ALL_MCAST_LBNFCN_XM_ACPT_ALL_MCAST_LBN 11 etherfabric.c 　
14755
 FCN_XM_ACPT_ALL_MCAST_WIDTHFCN_XM_ACPT_ALL_MCAST_WIDTH 1 etherfabric.c 　
14756
 FCN_XM_RX_PARAM_REG_MACFCN_XM_RX_PARAM_REG_MAC 0x0e etherfabric.c 　
14757
 FCN_XM_MAX_RX_FRM_SIZE_LBNFCN_XM_MAX_RX_FRM_SIZE_LBN 0 etherfabric.c 　
14758
 FCN_XM_MAX_RX_FRM_SIZE_WIDTHFCN_XM_MAX_RX_FRM_SIZE_WIDTH 14 etherfabric.c 　
14759
 FCN_XM_MGT_INT_REG_MAC_B0FCN_XM_MGT_INT_REG_MAC_B0 0x0f etherfabric.c 　
14760
 FCN_XM_PRMBLE_ERRFCN_XM_PRMBLE_ERR 2 etherfabric.c 　
14761
 FCN_XM_PRMBLE_WIDTHFCN_XM_PRMBLE_WIDTH 1 etherfabric.c 　
14762
 FCN_XM_RMTFLT_LBNFCN_XM_RMTFLT_LBN 1 etherfabric.c 　
14763
 FCN_XM_RMTFLT_WIDTHFCN_XM_RMTFLT_WIDTH 1 etherfabric.c 　
14764
 FCN_XM_LCLFLT_LBNFCN_XM_LCLFLT_LBN 0 etherfabric.c 　
14765
 FCN_XM_LCLFLT_WIDTHFCN_XM_LCLFLT_WIDTH 1 etherfabric.c 　
14766
 FCN_XX_ALIGN_DONE_LBNFCN_XX_ALIGN_DONE_LBN 20 etherfabric.c 　
14767
 FCN_XX_ALIGN_DONE_WIDTHFCN_XX_ALIGN_DONE_WIDTH 1 etherfabric.c 　
14768
 FCN_XX_CORE_STAT_REG_MACFCN_XX_CORE_STAT_REG_MAC 0x16 etherfabric.c 　
14769
 FCN_XX_SYNC_STAT_LBNFCN_XX_SYNC_STAT_LBN 16 etherfabric.c 　
14770
 FCN_XX_SYNC_STAT_WIDTHFCN_XX_SYNC_STAT_WIDTH 4 etherfabric.c 　
14771
 FCN_XX_SYNC_STAT_DECODE_SYNCEDFCN_XX_SYNC_STAT_DECODE_SYNCED 0xf etherfabric.c 　
14772
 FCN_XX_COMMA_DET_LBNFCN_XX_COMMA_DET_LBN 12 etherfabric.c 　
14773
 FCN_XX_COMMA_DET_WIDTHFCN_XX_COMMA_DET_WIDTH 4 etherfabric.c 　
14774
 FCN_XX_COMMA_DET_RESETFCN_XX_COMMA_DET_RESET 0xf etherfabric.c 　
14775
 FCN_XX_CHARERR_LBNFCN_XX_CHARERR_LBN 4 etherfabric.c 　
14776
 FCN_XX_CHARERR_WIDTHFCN_XX_CHARERR_WIDTH 4 etherfabric.c 　
14777
 FCN_XX_CHARERR_RESETFCN_XX_CHARERR_RESET 0xf etherfabric.c 　
14778
 FCN_XX_DISPERR_LBNFCN_XX_DISPERR_LBN 0 etherfabric.c 　
14779
 FCN_XX_DISPERR_WIDTHFCN_XX_DISPERR_WIDTH 4 etherfabric.c 　
14780
 FCN_XX_DISPERR_RESETFCN_XX_DISPERR_RESET 0xf etherfabric.c 　
14781
 FCN_XX_PWR_RST_REG_MACFCN_XX_PWR_RST_REG_MAC 0x10 etherfabric.c 　
14782
 FCN_XX_PWRDND_EN_LBNFCN_XX_PWRDND_EN_LBN 15 etherfabric.c 　
14783
 FCN_XX_PWRDND_EN_WIDTHFCN_XX_PWRDND_EN_WIDTH 1 etherfabric.c 　
14784
 FCN_XX_PWRDNC_EN_LBNFCN_XX_PWRDNC_EN_LBN 14 etherfabric.c 　
14785
 FCN_XX_PWRDNC_EN_WIDTHFCN_XX_PWRDNC_EN_WIDTH 1 etherfabric.c 　
14786
 FCN_XX_PWRDNB_EN_LBNFCN_XX_PWRDNB_EN_LBN 13 etherfabric.c 　
14787
 FCN_XX_PWRDNB_EN_WIDTHFCN_XX_PWRDNB_EN_WIDTH 1 etherfabric.c 　
14788
 FCN_XX_PWRDNA_EN_LBNFCN_XX_PWRDNA_EN_LBN 12 etherfabric.c 　
14789
 FCN_XX_PWRDNA_EN_WIDTHFCN_XX_PWRDNA_EN_WIDTH 1 etherfabric.c 　
14790
 FCN_XX_RSTPLLCD_EN_LBNFCN_XX_RSTPLLCD_EN_LBN 9 etherfabric.c 　
14791
 FCN_XX_RSTPLLCD_EN_WIDTHFCN_XX_RSTPLLCD_EN_WIDTH 1 etherfabric.c 　
14792
 FCN_XX_RSTPLLAB_EN_LBNFCN_XX_RSTPLLAB_EN_LBN 8 etherfabric.c 　
14793
 FCN_XX_RSTPLLAB_EN_WIDTHFCN_XX_RSTPLLAB_EN_WIDTH 1 etherfabric.c 　
14794
 FCN_XX_RESETD_EN_LBNFCN_XX_RESETD_EN_LBN 7 etherfabric.c 　
14795
 FCN_XX_RESETD_EN_WIDTHFCN_XX_RESETD_EN_WIDTH 1 etherfabric.c 　
14796
 FCN_XX_RESETC_EN_LBNFCN_XX_RESETC_EN_LBN 6 etherfabric.c 　
14797
 FCN_XX_RESETC_EN_WIDTHFCN_XX_RESETC_EN_WIDTH 1 etherfabric.c 　
14798
 FCN_XX_RESETB_EN_LBNFCN_XX_RESETB_EN_LBN 5 etherfabric.c 　
14799
 FCN_XX_RESETB_EN_WIDTHFCN_XX_RESETB_EN_WIDTH 1 etherfabric.c 　
14800
 FCN_XX_RESETA_EN_LBNFCN_XX_RESETA_EN_LBN 4 etherfabric.c 　
14801
 FCN_XX_RESETA_EN_WIDTHFCN_XX_RESETA_EN_WIDTH 1 etherfabric.c 　
14802
 FCN_XX_RSTXGXSRX_EN_LBNFCN_XX_RSTXGXSRX_EN_LBN 2 etherfabric.c 　
14803
 FCN_XX_RSTXGXSRX_EN_WIDTHFCN_XX_RSTXGXSRX_EN_WIDTH 1 etherfabric.c 　
14804
 FCN_XX_RSTXGXSTX_EN_LBNFCN_XX_RSTXGXSTX_EN_LBN 1 etherfabric.c 　
14805
 FCN_XX_RSTXGXSTX_EN_WIDTHFCN_XX_RSTXGXSTX_EN_WIDTH 1 etherfabric.c 　
14806
 FCN_XX_RST_XX_EN_LBNFCN_XX_RST_XX_EN_LBN 0 etherfabric.c 　
14807
 FCN_XX_RST_XX_EN_WIDTHFCN_XX_RST_XX_EN_WIDTH 1 etherfabric.c 　
14808
 FCN_XX_SD_CTL_REG_MACFCN_XX_SD_CTL_REG_MAC 0x11 etherfabric.c 　
14809
 FCN_XX_TERMADJ1_LBNFCN_XX_TERMADJ1_LBN 17 etherfabric.c 　
14810
 FCN_XX_TERMADJ1_WIDTHFCN_XX_TERMADJ1_WIDTH 1 etherfabric.c 　
14811
 FCN_XX_TERMADJ0_LBNFCN_XX_TERMADJ0_LBN 16 etherfabric.c 　
14812
 FCN_XX_TERMADJ0_WIDTHFCN_XX_TERMADJ0_WIDTH 1 etherfabric.c 　
14813
 FCN_XX_HIDRVD_LBNFCN_XX_HIDRVD_LBN 15 etherfabric.c 　
14814
 FCN_XX_HIDRVD_WIDTHFCN_XX_HIDRVD_WIDTH 1 etherfabric.c 　
14815
 FCN_XX_LODRVD_LBNFCN_XX_LODRVD_LBN 14 etherfabric.c 　
14816
 FCN_XX_LODRVD_WIDTHFCN_XX_LODRVD_WIDTH 1 etherfabric.c 　
14817
 FCN_XX_HIDRVC_LBNFCN_XX_HIDRVC_LBN 13 etherfabric.c 　
14818
 FCN_XX_HIDRVC_WIDTHFCN_XX_HIDRVC_WIDTH 1 etherfabric.c 　
14819
 FCN_XX_LODRVC_LBNFCN_XX_LODRVC_LBN 12 etherfabric.c 　
14820
 FCN_XX_LODRVC_WIDTHFCN_XX_LODRVC_WIDTH 1 etherfabric.c 　
14821
 FCN_XX_HIDRVB_LBNFCN_XX_HIDRVB_LBN 11 etherfabric.c 　
14822
 FCN_XX_HIDRVB_WIDTHFCN_XX_HIDRVB_WIDTH 1 etherfabric.c 　
14823
 FCN_XX_LODRVB_LBNFCN_XX_LODRVB_LBN 10 etherfabric.c 　
14824
 FCN_XX_LODRVB_WIDTHFCN_XX_LODRVB_WIDTH 1 etherfabric.c 　
14825
 FCN_XX_HIDRVA_LBNFCN_XX_HIDRVA_LBN 9 etherfabric.c 　
14826
 FCN_XX_HIDRVA_WIDTHFCN_XX_HIDRVA_WIDTH 1 etherfabric.c 　
14827
 FCN_XX_LODRVA_LBNFCN_XX_LODRVA_LBN 8 etherfabric.c 　
14828
 FCN_XX_LODRVA_WIDTHFCN_XX_LODRVA_WIDTH 1 etherfabric.c 　
14829
 FCN_XX_LPBKD_LBNFCN_XX_LPBKD_LBN 3 etherfabric.c 　
14830
 FCN_XX_LPBKD_WIDTHFCN_XX_LPBKD_WIDTH 1 etherfabric.c 　
14831
 FCN_XX_LPBKC_LBNFCN_XX_LPBKC_LBN 2 etherfabric.c 　
14832
 FCN_XX_LPBKC_WIDTHFCN_XX_LPBKC_WIDTH 1 etherfabric.c 　
14833
 FCN_XX_LPBKB_LBNFCN_XX_LPBKB_LBN 1 etherfabric.c 　
14834
 FCN_XX_LPBKB_WIDTHFCN_XX_LPBKB_WIDTH 1 etherfabric.c 　
14835
 FCN_XX_LPBKA_LBNFCN_XX_LPBKA_LBN 0 etherfabric.c 　
14836
 FCN_XX_LPBKA_WIDTHFCN_XX_LPBKA_WIDTH 1 etherfabric.c 　
14837
 FCN_XX_TXDRV_CTL_REG_MACFCN_XX_TXDRV_CTL_REG_MAC 0x12 etherfabric.c 　
14838
 FCN_XX_DEQD_LBNFCN_XX_DEQD_LBN 28 etherfabric.c 　
14839
 FCN_XX_DEQD_WIDTHFCN_XX_DEQD_WIDTH 4 etherfabric.c 　
14840
 FCN_XX_DEQC_LBNFCN_XX_DEQC_LBN 24 etherfabric.c 　
14841
 FCN_XX_DEQC_WIDTHFCN_XX_DEQC_WIDTH 4 etherfabric.c 　
14842
 FCN_XX_DEQB_LBNFCN_XX_DEQB_LBN 20 etherfabric.c 　
14843
 FCN_XX_DEQB_WIDTHFCN_XX_DEQB_WIDTH 4 etherfabric.c 　
14844
 FCN_XX_DEQA_LBNFCN_XX_DEQA_LBN 16 etherfabric.c 　
14845
 FCN_XX_DEQA_WIDTHFCN_XX_DEQA_WIDTH 4 etherfabric.c 　
14846
 FCN_XX_DTXD_LBNFCN_XX_DTXD_LBN 12 etherfabric.c 　
14847
 FCN_XX_DTXD_WIDTHFCN_XX_DTXD_WIDTH 4 etherfabric.c 　
14848
 FCN_XX_DTXC_LBNFCN_XX_DTXC_LBN 8 etherfabric.c 　
14849
 FCN_XX_DTXC_WIDTHFCN_XX_DTXC_WIDTH 4 etherfabric.c 　
14850
 FCN_XX_DTXB_LBNFCN_XX_DTXB_LBN 4 etherfabric.c 　
14851
 FCN_XX_DTXB_WIDTHFCN_XX_DTXB_WIDTH 4 etherfabric.c 　
14852
 FCN_XX_DTXA_LBNFCN_XX_DTXA_LBN 0 etherfabric.c 　
14853
 FCN_XX_DTXA_WIDTHFCN_XX_DTXA_WIDTH 4 etherfabric.c 　
14854
 FCN_RX_FILTER_TBL0FCN_RX_FILTER_TBL0 0xF00000 etherfabric.c 　
14855
 FCN_RX_DESC_PTR_TBL_KER_A1FCN_RX_DESC_PTR_TBL_KER_A1 0x11800 etherfabric.c 　
14856
 FCN_RX_DESC_PTR_TBL_KER_B0FCN_RX_DESC_PTR_TBL_KER_B0 0xF40000 etherfabric.c 　
14857
 FCN_RX_ISCSI_DDIG_EN_LBNFCN_RX_ISCSI_DDIG_EN_LBN 88 etherfabric.c 　
14858
 FCN_RX_ISCSI_DDIG_EN_WIDTHFCN_RX_ISCSI_DDIG_EN_WIDTH 1 etherfabric.c 　
14859
 FCN_RX_ISCSI_HDIG_EN_LBNFCN_RX_ISCSI_HDIG_EN_LBN 87 etherfabric.c 　
14860
 FCN_RX_ISCSI_HDIG_EN_WIDTHFCN_RX_ISCSI_HDIG_EN_WIDTH 1 etherfabric.c 　
14861
 FCN_RX_DESCQ_BUF_BASE_ID_LBNFCN_RX_DESCQ_BUF_BASE_ID_LBN 36 etherfabric.c 　
14862
 FCN_RX_DESCQ_BUF_BASE_ID_WIDTHFCN_RX_DESCQ_BUF_BASE_ID_WIDTH 20 etherfabric.c 　
14863
 FCN_RX_DESCQ_EVQ_ID_LBNFCN_RX_DESCQ_EVQ_ID_LBN 24 etherfabric.c 　
14864
 FCN_RX_DESCQ_EVQ_ID_WIDTHFCN_RX_DESCQ_EVQ_ID_WIDTH 12 etherfabric.c 　
14865
 FCN_RX_DESCQ_OWNER_ID_LBNFCN_RX_DESCQ_OWNER_ID_LBN 10 etherfabric.c 　
14866
 FCN_RX_DESCQ_OWNER_ID_WIDTHFCN_RX_DESCQ_OWNER_ID_WIDTH 14 etherfabric.c 　
14867
 FCN_RX_DESCQ_SIZE_LBNFCN_RX_DESCQ_SIZE_LBN 3 etherfabric.c 　
14868
 FCN_RX_DESCQ_SIZE_WIDTHFCN_RX_DESCQ_SIZE_WIDTH 2 etherfabric.c 　
14869
 FCN_RX_DESCQ_SIZE_4KFCN_RX_DESCQ_SIZE_4K 3 etherfabric.c 　
14870
 FCN_RX_DESCQ_SIZE_2KFCN_RX_DESCQ_SIZE_2K 2 etherfabric.c 　
14871
 FCN_RX_DESCQ_SIZE_1KFCN_RX_DESCQ_SIZE_1K 1 etherfabric.c 　
14872
 FCN_RX_DESCQ_SIZE_512FCN_RX_DESCQ_SIZE_512 0 etherfabric.c 　
14873
 FCN_RX_DESCQ_TYPE_LBNFCN_RX_DESCQ_TYPE_LBN 2 etherfabric.c 　
14874
 FCN_RX_DESCQ_TYPE_WIDTHFCN_RX_DESCQ_TYPE_WIDTH 1 etherfabric.c 　
14875
 FCN_RX_DESCQ_JUMBO_LBNFCN_RX_DESCQ_JUMBO_LBN 1 etherfabric.c 　
14876
 FCN_RX_DESCQ_JUMBO_WIDTHFCN_RX_DESCQ_JUMBO_WIDTH 1 etherfabric.c 　
14877
 FCN_RX_DESCQ_EN_LBNFCN_RX_DESCQ_EN_LBN 0 etherfabric.c 　
14878
 FCN_RX_DESCQ_EN_WIDTHFCN_RX_DESCQ_EN_WIDTH 1 etherfabric.c 　
14879
 FCN_TX_DESC_PTR_TBL_KER_A1FCN_TX_DESC_PTR_TBL_KER_A1 0x11900 etherfabric.c 　
14880
 FCN_TX_DESC_PTR_TBL_KER_B0FCN_TX_DESC_PTR_TBL_KER_B0 0xF50000 etherfabric.c 　
14881
 FCN_TX_NON_IP_DROP_DIS_B0_LBNFCN_TX_NON_IP_DROP_DIS_B0_LBN 91 etherfabric.c 　
14882
 FCN_TX_NON_IP_DROP_DIS_B0_WIDTHFCN_TX_NON_IP_DROP_DIS_B0_WIDTH 1 etherfabric.c 　
14883
 FCN_TX_DESCQ_EN_LBNFCN_TX_DESCQ_EN_LBN 88 etherfabric.c 　
14884
 FCN_TX_DESCQ_EN_WIDTHFCN_TX_DESCQ_EN_WIDTH 1 etherfabric.c 　
14885
 FCN_TX_ISCSI_DDIG_EN_LBNFCN_TX_ISCSI_DDIG_EN_LBN 87 etherfabric.c 　
14886
 FCN_TX_ISCSI_DDIG_EN_WIDTHFCN_TX_ISCSI_DDIG_EN_WIDTH 1 etherfabric.c 　
14887
 FCN_TX_ISCSI_HDIG_EN_LBNFCN_TX_ISCSI_HDIG_EN_LBN 86 etherfabric.c 　
14888
 FCN_TX_ISCSI_HDIG_EN_WIDTHFCN_TX_ISCSI_HDIG_EN_WIDTH 1 etherfabric.c 　
14889
 FCN_TX_DESCQ_BUF_BASE_ID_LBNFCN_TX_DESCQ_BUF_BASE_ID_LBN 36 etherfabric.c 　
14890
 FCN_TX_DESCQ_BUF_BASE_ID_WIDTHFCN_TX_DESCQ_BUF_BASE_ID_WIDTH 20 etherfabric.c 　
14891
 FCN_TX_DESCQ_EVQ_ID_LBNFCN_TX_DESCQ_EVQ_ID_LBN 24 etherfabric.c 　
14892
 FCN_TX_DESCQ_EVQ_ID_WIDTHFCN_TX_DESCQ_EVQ_ID_WIDTH 12 etherfabric.c 　
14893
 FCN_TX_DESCQ_OWNER_ID_LBNFCN_TX_DESCQ_OWNER_ID_LBN 10 etherfabric.c 　
14894
 FCN_TX_DESCQ_OWNER_ID_WIDTHFCN_TX_DESCQ_OWNER_ID_WIDTH 14 etherfabric.c 　
14895
 FCN_TX_DESCQ_SIZE_LBNFCN_TX_DESCQ_SIZE_LBN 3 etherfabric.c 　
14896
 FCN_TX_DESCQ_SIZE_WIDTHFCN_TX_DESCQ_SIZE_WIDTH 2 etherfabric.c 　
14897
 FCN_TX_DESCQ_SIZE_4KFCN_TX_DESCQ_SIZE_4K 3 etherfabric.c 　
14898
 FCN_TX_DESCQ_SIZE_2KFCN_TX_DESCQ_SIZE_2K 2 etherfabric.c 　
14899
 FCN_TX_DESCQ_SIZE_1KFCN_TX_DESCQ_SIZE_1K 1 etherfabric.c 　
14900
 FCN_TX_DESCQ_SIZE_512FCN_TX_DESCQ_SIZE_512 0 etherfabric.c 　
14901
 FCN_TX_DESCQ_TYPE_LBNFCN_TX_DESCQ_TYPE_LBN 1 etherfabric.c 　
14902
 FCN_TX_DESCQ_TYPE_WIDTHFCN_TX_DESCQ_TYPE_WIDTH 2 etherfabric.c 　
14903
 FCN_TX_DESCQ_FLUSH_LBNFCN_TX_DESCQ_FLUSH_LBN 0 etherfabric.c 　
14904
 FCN_TX_DESCQ_FLUSH_WIDTHFCN_TX_DESCQ_FLUSH_WIDTH 1 etherfabric.c 　
14905
 FCN_EVQ_PTR_TBL_KER_A1FCN_EVQ_PTR_TBL_KER_A1 0x11a00 etherfabric.c 　
14906
 FCN_EVQ_PTR_TBL_KER_B0FCN_EVQ_PTR_TBL_KER_B0 0xf60000 etherfabric.c 　
14907
 FCN_EVQ_EN_LBNFCN_EVQ_EN_LBN 23 etherfabric.c 　
14908
 FCN_EVQ_EN_WIDTHFCN_EVQ_EN_WIDTH 1 etherfabric.c 　
14909
 FCN_EVQ_SIZE_LBNFCN_EVQ_SIZE_LBN 20 etherfabric.c 　
14910
 FCN_EVQ_SIZE_WIDTHFCN_EVQ_SIZE_WIDTH 3 etherfabric.c 　
14911
 FCN_EVQ_SIZE_32KFCN_EVQ_SIZE_32K 6 etherfabric.c 　
14912
 FCN_EVQ_SIZE_16KFCN_EVQ_SIZE_16K 5 etherfabric.c 　
14913
 FCN_EVQ_SIZE_8KFCN_EVQ_SIZE_8K 4 etherfabric.c 　
14914
 FCN_EVQ_SIZE_4KFCN_EVQ_SIZE_4K 3 etherfabric.c 　
14915
 FCN_EVQ_SIZE_2KFCN_EVQ_SIZE_2K 2 etherfabric.c 　
14916
 FCN_EVQ_SIZE_1KFCN_EVQ_SIZE_1K 1 etherfabric.c 　
14917
 FCN_EVQ_SIZE_512FCN_EVQ_SIZE_512 0 etherfabric.c 　
14918
 FCN_EVQ_BUF_BASE_ID_LBNFCN_EVQ_BUF_BASE_ID_LBN 0 etherfabric.c 　
14919
 FCN_EVQ_BUF_BASE_ID_WIDTHFCN_EVQ_BUF_BASE_ID_WIDTH 20 etherfabric.c 　
14920
 FCN_RX_RSS_INDIR_TBL_B0FCN_RX_RSS_INDIR_TBL_B0 0xFB0000 etherfabric.c 　
14921
 FCN_EVQ_RPTR_REG_KER_A1FCN_EVQ_RPTR_REG_KER_A1 0x11b00 etherfabric.c 　
14922
 FCN_EVQ_RPTR_REG_KER_B0FCN_EVQ_RPTR_REG_KER_B0 0xfa0000 etherfabric.c 　
14923
 FCN_EVQ_RPTR_LBNFCN_EVQ_RPTR_LBN 0 etherfabric.c 　
14924
 FCN_EVQ_RPTR_WIDTHFCN_EVQ_RPTR_WIDTH 14 etherfabric.c 　
14925
 FCN_EVQ_RPTR_REG_KER_DWORD_A1FCN_EVQ_RPTR_REG_KER_DWORD_A1 ( FCN_EVQ_RPTR_REG_KER_A1 + 0 ) etherfabric.c 　
14926
 FCN_EVQ_RPTR_REG_KER_DWORD_B0FCN_EVQ_RPTR_REG_KER_DWORD_B0 ( FCN_EVQ_RPTR_REG_KER_B0 + 0 ) etherfabric.c 　
14927
 FCN_EVQ_RPTR_DWORD_LBNFCN_EVQ_RPTR_DWORD_LBN 0 etherfabric.c 　
14928
 FCN_EVQ_RPTR_DWORD_WIDTHFCN_EVQ_RPTR_DWORD_WIDTH 14 etherfabric.c 　
14929
 FCN_BUF_FULL_TBL_KER_A1FCN_BUF_FULL_TBL_KER_A1 0x18000 etherfabric.c 　
14930
 FCN_BUF_FULL_TBL_KER_B0FCN_BUF_FULL_TBL_KER_B0 0x800000 etherfabric.c 　
14931
 FCN_IP_DAT_BUF_SIZE_LBNFCN_IP_DAT_BUF_SIZE_LBN 50 etherfabric.c 　
14932
 FCN_IP_DAT_BUF_SIZE_WIDTHFCN_IP_DAT_BUF_SIZE_WIDTH 1 etherfabric.c 　
14933
 FCN_IP_DAT_BUF_SIZE_8KFCN_IP_DAT_BUF_SIZE_8K 1 etherfabric.c 　
14934
 FCN_IP_DAT_BUF_SIZE_4KFCN_IP_DAT_BUF_SIZE_4K 0 etherfabric.c 　
14935
 FCN_BUF_ADR_FBUF_LBNFCN_BUF_ADR_FBUF_LBN 14 etherfabric.c 　
14936
 FCN_BUF_ADR_FBUF_WIDTHFCN_BUF_ADR_FBUF_WIDTH 34 etherfabric.c 　
14937
 FCN_BUF_OWNER_ID_FBUF_LBNFCN_BUF_OWNER_ID_FBUF_LBN 0 etherfabric.c 　
14938
 FCN_BUF_OWNER_ID_FBUF_WIDTHFCN_BUF_OWNER_ID_FBUF_WIDTH 14 etherfabric.c 　
14939
 FCN_MAC_DATA_LBNFCN_MAC_DATA_LBN 0 etherfabric.c 　
14940
 FCN_MAC_DATA_WIDTHFCN_MAC_DATA_WIDTH 32 etherfabric.c 　
14941
 FCN_TX_KER_PORT_LBNFCN_TX_KER_PORT_LBN 63 etherfabric.c 　
14942
 FCN_TX_KER_PORT_WIDTHFCN_TX_KER_PORT_WIDTH 1 etherfabric.c 　
14943
 FCN_TX_KER_BYTE_CNT_LBNFCN_TX_KER_BYTE_CNT_LBN 48 etherfabric.c 　
14944
 FCN_TX_KER_BYTE_CNT_WIDTHFCN_TX_KER_BYTE_CNT_WIDTH 14 etherfabric.c 　
14945
 FCN_TX_KER_BUF_ADR_LBNFCN_TX_KER_BUF_ADR_LBN 0 etherfabric.c 　
14946
 FCN_TX_KER_BUF_ADR_WIDTHFCN_TX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 ) etherfabric.c 　
14947
 FCN_RX_KER_BUF_SIZE_LBNFCN_RX_KER_BUF_SIZE_LBN 48 etherfabric.c 　
14948
 FCN_RX_KER_BUF_SIZE_WIDTHFCN_RX_KER_BUF_SIZE_WIDTH 14 etherfabric.c 　
14949
 FCN_RX_KER_BUF_ADR_LBNFCN_RX_KER_BUF_ADR_LBN 0 etherfabric.c 　
14950
 FCN_RX_KER_BUF_ADR_WIDTHFCN_RX_KER_BUF_ADR_WIDTH EFAB_DMA_TYPE_WIDTH ( 46 ) etherfabric.c 　
14951
 FCN_EV_CODE_LBNFCN_EV_CODE_LBN 60 etherfabric.c 　
14952
 FCN_EV_CODE_WIDTHFCN_EV_CODE_WIDTH 4 etherfabric.c 　
14953
 FCN_RX_IP_EV_DECODEFCN_RX_IP_EV_DECODE 0 etherfabric.c 　
14954
 FCN_TX_IP_EV_DECODEFCN_TX_IP_EV_DECODE 2 etherfabric.c 　
14955
 FCN_DRIVER_EV_DECODEFCN_DRIVER_EV_DECODE 5 etherfabric.c 　
14956
 FCN_RX_EV_PKT_OK_LBNFCN_RX_EV_PKT_OK_LBN 56 etherfabric.c 　
14957
 FCN_RX_EV_PKT_OK_WIDTHFCN_RX_EV_PKT_OK_WIDTH 1 etherfabric.c 　
14958
 FCN_RX_PORT_LBNFCN_RX_PORT_LBN 30 etherfabric.c 　
14959
 FCN_RX_PORT_WIDTHFCN_RX_PORT_WIDTH 1 etherfabric.c 　
14960
 FCN_RX_EV_BYTE_CNT_LBNFCN_RX_EV_BYTE_CNT_LBN 16 etherfabric.c 　
14961
 FCN_RX_EV_BYTE_CNT_WIDTHFCN_RX_EV_BYTE_CNT_WIDTH 14 etherfabric.c 　
14962
 FCN_RX_EV_DESC_PTR_LBNFCN_RX_EV_DESC_PTR_LBN 0 etherfabric.c 　
14963
 FCN_RX_EV_DESC_PTR_WIDTHFCN_RX_EV_DESC_PTR_WIDTH 12 etherfabric.c 　
14964
 FCN_TX_EV_DESC_PTR_LBNFCN_TX_EV_DESC_PTR_LBN 0 etherfabric.c 　
14965
 FCN_TX_EV_DESC_PTR_WIDTHFCN_TX_EV_DESC_PTR_WIDTH 12 etherfabric.c 　
14966
 FALCON_SPI_MAX_LENFALCON_SPI_MAX_LEN 16 etherfabric.c 　
14967
 GM_CFG1_REG_MACGM_CFG1_REG_MAC 0x00 etherfabric.c 　
14968
 GM_SW_RST_LBNGM_SW_RST_LBN 31 etherfabric.c 　
14969
 GM_SW_RST_WIDTHGM_SW_RST_WIDTH 1 etherfabric.c 　
14970
 GM_RX_FC_EN_LBNGM_RX_FC_EN_LBN 5 etherfabric.c 　
14971
 GM_RX_FC_EN_WIDTHGM_RX_FC_EN_WIDTH 1 etherfabric.c 　
14972
 GM_TX_FC_EN_LBNGM_TX_FC_EN_LBN 4 etherfabric.c 　
14973
 GM_TX_FC_EN_WIDTHGM_TX_FC_EN_WIDTH 1 etherfabric.c 　
14974
 GM_RX_EN_LBNGM_RX_EN_LBN 2 etherfabric.c 　
14975
 GM_RX_EN_WIDTHGM_RX_EN_WIDTH 1 etherfabric.c 　
14976
 GM_TX_EN_LBNGM_TX_EN_LBN 0 etherfabric.c 　
14977
 GM_TX_EN_WIDTHGM_TX_EN_WIDTH 1 etherfabric.c 　
14978
 GM_CFG2_REG_MACGM_CFG2_REG_MAC 0x01 etherfabric.c 　
14979
 GM_PAMBL_LEN_LBNGM_PAMBL_LEN_LBN 12 etherfabric.c 　
14980
 GM_PAMBL_LEN_WIDTHGM_PAMBL_LEN_WIDTH 4 etherfabric.c 　
14981
 GM_IF_MODE_LBNGM_IF_MODE_LBN 8 etherfabric.c 　
14982
 GM_IF_MODE_WIDTHGM_IF_MODE_WIDTH 2 etherfabric.c 　
14983
 GM_PAD_CRC_EN_LBNGM_PAD_CRC_EN_LBN 2 etherfabric.c 　
14984
 GM_PAD_CRC_EN_WIDTHGM_PAD_CRC_EN_WIDTH 1 etherfabric.c 　
14985
 GM_FD_LBNGM_FD_LBN 0 etherfabric.c 　
14986
 GM_FD_WIDTHGM_FD_WIDTH 1 etherfabric.c 　
14987
 GM_MAX_FLEN_REG_MACGM_MAX_FLEN_REG_MAC 0x04 etherfabric.c 　
14988
 GM_MAX_FLEN_LBNGM_MAX_FLEN_LBN 0 etherfabric.c 　
14989
 GM_MAX_FLEN_WIDTHGM_MAX_FLEN_WIDTH 16 etherfabric.c 　
14990
 GM_MII_MGMT_CFG_REG_MACGM_MII_MGMT_CFG_REG_MAC 0x08 etherfabric.c 　
14991
 GM_MGMT_CLK_SEL_LBNGM_MGMT_CLK_SEL_LBN 0 etherfabric.c 　
14992
 GM_MGMT_CLK_SEL_WIDTHGM_MGMT_CLK_SEL_WIDTH 3 etherfabric.c 　
14993
 GM_MII_MGMT_CMD_REG_MACGM_MII_MGMT_CMD_REG_MAC 0x09 etherfabric.c 　
14994
 GM_MGMT_SCAN_CYC_LBNGM_MGMT_SCAN_CYC_LBN 1 etherfabric.c 　
14995
 GM_MGMT_SCAN_CYC_WIDTHGM_MGMT_SCAN_CYC_WIDTH 1 etherfabric.c 　
14996
 GM_MGMT_RD_CYC_LBNGM_MGMT_RD_CYC_LBN 0 etherfabric.c 　
14997
 GM_MGMT_RD_CYC_WIDTHGM_MGMT_RD_CYC_WIDTH 1 etherfabric.c 　
14998
 GM_MII_MGMT_ADR_REG_MACGM_MII_MGMT_ADR_REG_MAC 0x0a etherfabric.c 　
14999
 GM_MGMT_PHY_ADDR_LBNGM_MGMT_PHY_ADDR_LBN 8 etherfabric.c 　
15000
 GM_MGMT_PHY_ADDR_WIDTHGM_MGMT_PHY_ADDR_WIDTH 5 etherfabric.c 　
15001
 GM_MGMT_REG_ADDR_LBNGM_MGMT_REG_ADDR_LBN 0 etherfabric.c 　
15002
 GM_MGMT_REG_ADDR_WIDTHGM_MGMT_REG_ADDR_WIDTH 5 etherfabric.c 　
15003
 GM_MII_MGMT_CTL_REG_MACGM_MII_MGMT_CTL_REG_MAC 0x0b etherfabric.c 　
15004
 GM_MGMT_CTL_LBNGM_MGMT_CTL_LBN 0 etherfabric.c 　
15005
 GM_MGMT_CTL_WIDTHGM_MGMT_CTL_WIDTH 16 etherfabric.c 　
15006
 GM_MII_MGMT_STAT_REG_MACGM_MII_MGMT_STAT_REG_MAC 0x0c etherfabric.c 　
15007
 GM_MGMT_STAT_LBNGM_MGMT_STAT_LBN 0 etherfabric.c 　
15008
 GM_MGMT_STAT_WIDTHGM_MGMT_STAT_WIDTH 16 etherfabric.c 　
15009
 GM_MII_MGMT_IND_REG_MACGM_MII_MGMT_IND_REG_MAC 0x0d etherfabric.c 　
15010
 GM_MGMT_BUSY_LBNGM_MGMT_BUSY_LBN 0 etherfabric.c 　
15011
 GM_MGMT_BUSY_WIDTHGM_MGMT_BUSY_WIDTH 1 etherfabric.c 　
15012
 GM_ADR1_REG_MACGM_ADR1_REG_MAC 0x10 etherfabric.c 　
15013
 GM_HWADDR_5_LBNGM_HWADDR_5_LBN 24 etherfabric.c 　
15014
 GM_HWADDR_5_WIDTHGM_HWADDR_5_WIDTH 8 etherfabric.c 　
15015
 GM_HWADDR_4_LBNGM_HWADDR_4_LBN 16 etherfabric.c 　
15016
 GM_HWADDR_4_WIDTHGM_HWADDR_4_WIDTH 8 etherfabric.c 　
15017
 GM_HWADDR_3_LBNGM_HWADDR_3_LBN 8 etherfabric.c 　
15018
 GM_HWADDR_3_WIDTHGM_HWADDR_3_WIDTH 8 etherfabric.c 　
15019
 GM_HWADDR_2_LBNGM_HWADDR_2_LBN 0 etherfabric.c 　
15020
 GM_HWADDR_2_WIDTHGM_HWADDR_2_WIDTH 8 etherfabric.c 　
15021
 GM_ADR2_REG_MACGM_ADR2_REG_MAC 0x11 etherfabric.c 　
15022
 GM_HWADDR_1_LBNGM_HWADDR_1_LBN 24 etherfabric.c 　
15023
 GM_HWADDR_1_WIDTHGM_HWADDR_1_WIDTH 8 etherfabric.c 　
15024
 GM_HWADDR_0_LBNGM_HWADDR_0_LBN 16 etherfabric.c 　
15025
 GM_HWADDR_0_WIDTHGM_HWADDR_0_WIDTH 8 etherfabric.c 　
15026
 GMF_CFG0_REG_MACGMF_CFG0_REG_MAC 0x12 etherfabric.c 　
15027
 GMF_FTFENREQ_LBNGMF_FTFENREQ_LBN 12 etherfabric.c 　
15028
 GMF_FTFENREQ_WIDTHGMF_FTFENREQ_WIDTH 1 etherfabric.c 　
15029
 GMF_STFENREQ_LBNGMF_STFENREQ_LBN 11 etherfabric.c 　
15030
 GMF_STFENREQ_WIDTHGMF_STFENREQ_WIDTH 1 etherfabric.c 　
15031
 GMF_FRFENREQ_LBNGMF_FRFENREQ_LBN 10 etherfabric.c 　
15032
 GMF_FRFENREQ_WIDTHGMF_FRFENREQ_WIDTH 1 etherfabric.c 　
15033
 GMF_SRFENREQ_LBNGMF_SRFENREQ_LBN 9 etherfabric.c 　
15034
 GMF_SRFENREQ_WIDTHGMF_SRFENREQ_WIDTH 1 etherfabric.c 　
15035
 GMF_WTMENREQ_LBNGMF_WTMENREQ_LBN 8 etherfabric.c 　
15036
 GMF_WTMENREQ_WIDTHGMF_WTMENREQ_WIDTH 1 etherfabric.c 　
15037
 GMF_CFG1_REG_MACGMF_CFG1_REG_MAC 0x13 etherfabric.c 　
15038
 GMF_CFGFRTH_LBNGMF_CFGFRTH_LBN 16 etherfabric.c 　
15039
 GMF_CFGFRTH_WIDTHGMF_CFGFRTH_WIDTH 5 etherfabric.c 　
15040
 GMF_CFGXOFFRTX_LBNGMF_CFGXOFFRTX_LBN 0 etherfabric.c 　
15041
 GMF_CFGXOFFRTX_WIDTHGMF_CFGXOFFRTX_WIDTH 16 etherfabric.c 　
15042
 GMF_CFG2_REG_MACGMF_CFG2_REG_MAC 0x14 etherfabric.c 　
15043
 GMF_CFGHWM_LBNGMF_CFGHWM_LBN 16 etherfabric.c 　
15044
 GMF_CFGHWM_WIDTHGMF_CFGHWM_WIDTH 6 etherfabric.c 　
15045
 GMF_CFGLWM_LBNGMF_CFGLWM_LBN 0 etherfabric.c 　
15046
 GMF_CFGLWM_WIDTHGMF_CFGLWM_WIDTH 6 etherfabric.c 　
15047
 GMF_CFG3_REG_MACGMF_CFG3_REG_MAC 0x15 etherfabric.c 　
15048
 GMF_CFGHWMFT_LBNGMF_CFGHWMFT_LBN 16 etherfabric.c 　
15049
 GMF_CFGHWMFT_WIDTHGMF_CFGHWMFT_WIDTH 6 etherfabric.c 　
15050
 GMF_CFGFTTH_LBNGMF_CFGFTTH_LBN 0 etherfabric.c 　
15051
 GMF_CFGFTTH_WIDTHGMF_CFGFTTH_WIDTH 6 etherfabric.c 　
15052
 GMF_CFG4_REG_MACGMF_CFG4_REG_MAC 0x16 etherfabric.c 　
15053
 GMF_HSTFLTRFRM_PAUSE_LBNGMF_HSTFLTRFRM_PAUSE_LBN 12 etherfabric.c 　
15054
 GMF_HSTFLTRFRM_PAUSE_WIDTHGMF_HSTFLTRFRM_PAUSE_WIDTH 12 etherfabric.c 　
15055
 GMF_CFG5_REG_MACGMF_CFG5_REG_MAC 0x17 etherfabric.c 　
15056
 GMF_CFGHDPLX_LBNGMF_CFGHDPLX_LBN 22 etherfabric.c 　
15057
 GMF_CFGHDPLX_WIDTHGMF_CFGHDPLX_WIDTH 1 etherfabric.c 　
15058
 GMF_CFGBYTMODE_LBNGMF_CFGBYTMODE_LBN 19 etherfabric.c 　
15059
 GMF_CFGBYTMODE_WIDTHGMF_CFGBYTMODE_WIDTH 1 etherfabric.c 　
15060
 GMF_HSTDRPLT64_LBNGMF_HSTDRPLT64_LBN 18 etherfabric.c 　
15061
 GMF_HSTDRPLT64_WIDTHGMF_HSTDRPLT64_WIDTH 1 etherfabric.c 　
15062
 GMF_HSTFLTRFRMDC_PAUSE_LBNGMF_HSTFLTRFRMDC_PAUSE_LBN 12 etherfabric.c 　
15063
 GMF_HSTFLTRFRMDC_PAUSE_WIDTHGMF_HSTFLTRFRMDC_PAUSE_WIDTH 1 etherfabric.c 　
15064
 XFP_REQUIRED_DEVSXFP_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \ MDIO_MMDREG_DEVS0_PMAPMD | \ MDIO_MMDREG_DEVS0_PHYXS ) etherfabric.c 　
15065
 TXC_GLRGS_GLCMDTXC_GLRGS_GLCMD (0xc004) etherfabric.c 　
15066
 TXC_GLCMD_LMTSWRST_LBNTXC_GLCMD_LMTSWRST_LBN (14) etherfabric.c 　
15067
 TXC_ALRGS_ATXAMP0TXC_ALRGS_ATXAMP0 (0xc041) etherfabric.c 　
15068
 TXC_ALRGS_ATXAMP1TXC_ALRGS_ATXAMP1 (0xc042) etherfabric.c 　
15069
 TXC_ATXAMP_LANE02_LBNTXC_ATXAMP_LANE02_LBN (3) etherfabric.c 　
15070
 TXC_ATXAMP_LANE13_LBNTXC_ATXAMP_LANE13_LBN (11) etherfabric.c 　
15071
 TXC_ATXAMP_1280_mVTXC_ATXAMP_1280_mV (0) etherfabric.c 　
15072
 TXC_ATXAMP_1200_mVTXC_ATXAMP_1200_mV (8) etherfabric.c 　
15073
 TXC_ATXAMP_1120_mVTXC_ATXAMP_1120_mV (12) etherfabric.c 　
15074
 TXC_ATXAMP_1060_mVTXC_ATXAMP_1060_mV (14) etherfabric.c 　
15075
 TXC_ATXAMP_0820_mVTXC_ATXAMP_0820_mV (25) etherfabric.c 　
15076
 TXC_ATXAMP_0720_mVTXC_ATXAMP_0720_mV (26) etherfabric.c 　
15077
 TXC_ATXAMP_0580_mVTXC_ATXAMP_0580_mV (27) etherfabric.c 　
15078
 TXC_ATXAMP_0440_mVTXC_ATXAMP_0440_mV (28) etherfabric.c 　
15079
 TXC_ATXAMP_0820_BOTHTXC_ATXAMP_0820_BOTH ( (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE02_LBN) | \ (TXC_ATXAMP_0820_mV << TXC_ATXAMP_LANE13_LBN) ) etherfabric.c 　
15080
 TXC_ATXAMP_DEFAULTTXC_ATXAMP_DEFAULT (0x6060) etherfabric.c From databook
15081
 TXC_ALRGS_ATXPRE0TXC_ALRGS_ATXPRE0 (0xc043) etherfabric.c 　
15082
 TXC_ALRGS_ATXPRE1TXC_ALRGS_ATXPRE1 (0xc044) etherfabric.c 　
15083
 TXC_ATXPRE_NONETXC_ATXPRE_NONE (0) etherfabric.c 　
15084
 TXC_ATXPRE_DEFAULTTXC_ATXPRE_DEFAULT (0x1010) etherfabric.c From databook
15085
 TXC_REQUIRED_DEVSTXC_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PCS | \ MDIO_MMDREG_DEVS0_PMAPMD | \ MDIO_MMDREG_DEVS0_PHYXS ) etherfabric.c 　
15086
 TENXPRESS_REQUIRED_DEVSTENXPRESS_REQUIRED_DEVS ( MDIO_MMDREG_DEVS0_PMAPMD | \ MDIO_MMDREG_DEVS0_PCS | \ MDIO_MMDREG_DEVS0_PHYXS ) etherfabric.c 　
15087
 PCS_TEST_SELECT_REGPCS_TEST_SELECT_REG 0xd807 etherfabric.c PRM 10.5.8
15088
 CLK312_EN_LBNCLK312_EN_LBN 3 etherfabric.c 　
15089
 CLK312_EN_WIDTHCLK312_EN_WIDTH 1 etherfabric.c 　
15090
 PCS_CLOCK_CTRL_REGPCS_CLOCK_CTRL_REG 0xd801 etherfabric.c 　
15091
 PLL312_RST_N_LBNPLL312_RST_N_LBN 2 etherfabric.c 　
15092
 PMA_PMD_EXT_CTRL_REGPMA_PMD_EXT_CTRL_REG 49152 etherfabric.c 　
15093
 PMA_PMD_EXT_SSR_LBNPMA_PMD_EXT_SSR_LBN 15 etherfabric.c 　
15094
 PCS_BOOT_STATUS_REGPCS_BOOT_STATUS_REG 0xd000 etherfabric.c 　
15095
 PCS_BOOT_FATAL_ERR_LBNPCS_BOOT_FATAL_ERR_LBN 0 etherfabric.c 　
15096
 PCS_BOOT_PROGRESS_LBNPCS_BOOT_PROGRESS_LBN 1 etherfabric.c 　
15097
 PCS_BOOT_PROGRESS_WIDTHPCS_BOOT_PROGRESS_WIDTH 2 etherfabric.c 　
15098
 PCS_BOOT_COMPLETE_LBNPCS_BOOT_COMPLETE_LBN 3 etherfabric.c 　
15099
 PCS_SOFT_RST2_REGPCS_SOFT_RST2_REG 0xd806 etherfabric.c 　
15100
 SERDES_RST_N_LBNSERDES_RST_N_LBN 13 etherfabric.c 　
15101
 XGXS_RST_N_LBNXGXS_RST_N_LBN 12 etherfabric.c 　
15102
 PM8358_REQUIRED_DEVSPM8358_REQUIRED_DEVS (MDIO_MMDREG_DEVS0_DTEXS) etherfabric.c 　
15103
 PMC_MASTER_REGPMC_MASTER_REG (0xd000) etherfabric.c 　
15104
 PMC_MASTER_ANLG_CTRLPMC_MASTER_ANLG_CTRL (1<< 11) etherfabric.c 　
15105
 PMC_MCONF2_REGPMC_MCONF2_REG (0xd002) etherfabric.c 　
15106
 PMC_MCONF2_TEDGEPMC_MCONF2_TEDGE (1 << 2) etherfabric.c 　
15107
 PMC_MCONF2_REDGEPMC_MCONF2_REDGE (1 << 3) etherfabric.c 　
15108
 PMC_ANALOG_RX_CFG0PMC_ANALOG_RX_CFG0 (0xd025) etherfabric.c 　
15109
 PMC_ANALOG_RX_CFG1PMC_ANALOG_RX_CFG1 (0xd02d) etherfabric.c 　
15110
 PMC_ANALOG_RX_CFG2PMC_ANALOG_RX_CFG2 (0xd035) etherfabric.c 　
15111
 PMC_ANALOG_RX_CFG3PMC_ANALOG_RX_CFG3 (0xd03d) etherfabric.c 　
15112
 PMC_ANALOG_RX_TERMPMC_ANALOG_RX_TERM (1 << 15) etherfabric.c Bit 15 of RX CFG: 0 for 100 ohms float,
15113
 PMC_ANALOG_RX_EQ_MASKPMC_ANALOG_RX_EQ_MASK (3 << 8) etherfabric.c 　
15114
 PMC_ANALOG_RX_EQ_NONEPMC_ANALOG_RX_EQ_NONE (0 << 8) etherfabric.c 　
15115
 PMC_ANALOG_RX_EQ_HALFPMC_ANALOG_RX_EQ_HALF (1 << 8) etherfabric.c 　
15116
 PMC_ANALOG_RX_EQ_FULLPMC_ANALOG_RX_EQ_FULL (2 << 8) etherfabric.c 　
15117
 PMC_ANALOG_RX_EQ_RSVDPMC_ANALOG_RX_EQ_RSVD (3 << 8) etherfabric.c 　
15118
 MAX_TEMP_THRESHMAX_TEMP_THRESH 90 etherfabric.c 　
15119
 PCA9539PCA9539 0x74 etherfabric.c 　
15120
 P0_INP0_IN 0x00 etherfabric.c 　
15121
 P0_OUTP0_OUT 0x02 etherfabric.c 　
15122
 P0_CONFIGP0_CONFIG 0x06 etherfabric.c 　
15123
 P0_EN_1V0X_LBNP0_EN_1V0X_LBN 0 etherfabric.c 　
15124
 P0_EN_1V0X_WIDTHP0_EN_1V0X_WIDTH 1 etherfabric.c 　
15125
 P0_EN_1V2_LBNP0_EN_1V2_LBN 1 etherfabric.c 　
15126
 P0_EN_1V2_WIDTHP0_EN_1V2_WIDTH 1 etherfabric.c 　
15127
 P0_EN_2V5_LBNP0_EN_2V5_LBN 2 etherfabric.c 　
15128
 P0_EN_2V5_WIDTHP0_EN_2V5_WIDTH 1 etherfabric.c 　
15129
 P0_EN_3V3X_LBNP0_EN_3V3X_LBN 3 etherfabric.c 　
15130
 P0_EN_3V3X_WIDTHP0_EN_3V3X_WIDTH 1 etherfabric.c 　
15131
 P0_EN_5V_LBNP0_EN_5V_LBN 4 etherfabric.c 　
15132
 P0_EN_5V_WIDTHP0_EN_5V_WIDTH 1 etherfabric.c 　
15133
 P0_X_TRST_LBNP0_X_TRST_LBN 6 etherfabric.c 　
15134
 P0_X_TRST_WIDTHP0_X_TRST_WIDTH 1 etherfabric.c 　
15135
 P1_INP1_IN 0x01 etherfabric.c 　
15136
 P1_CONFIGP1_CONFIG 0x07 etherfabric.c 　
15137
 P1_AFE_PWD_LBNP1_AFE_PWD_LBN 0 etherfabric.c 　
15138
 P1_AFE_PWD_WIDTHP1_AFE_PWD_WIDTH 1 etherfabric.c 　
15139
 P1_DSP_PWD25_LBNP1_DSP_PWD25_LBN 1 etherfabric.c 　
15140
 P1_DSP_PWD25_WIDTHP1_DSP_PWD25_WIDTH 1 etherfabric.c 　
15141
 P1_SPARE_LBNP1_SPARE_LBN 4 etherfabric.c 　
15142
 P1_SPARE_WIDTHP1_SPARE_WIDTH 4 etherfabric.c 　
15143
 MAX6647MAX6647 0x4e etherfabric.c 　
15144
 RSLRSL 0x02 etherfabric.c 　
15145
 RLHNRLHN 0x05 etherfabric.c 　
15146
 WLHOWLHO 0x0b etherfabric.c 　
15147
 FALCON_MAC_ADDRESS_OFFSETFALCON_MAC_ADDRESS_OFFSET 0x310 etherfabric.c 　
15148
 SF_NV_CONFIG_BASESF_NV_CONFIG_BASE 0x300 etherfabric.c 　
15149
 SF_NV_CONFIG_EXTRASF_NV_CONFIG_EXTRA 0xA0 etherfabric.c 　
15150
 drv_versiondrv_version "v1.2" forcedeth.c 　
15151
 drv_datedrv_date "05-14-2005" forcedeth.c 　
15152
 ETH_DATA_LENETH_DATA_LEN 1500 forcedeth.c 　
15153
 PCI_DEVICE_ID_NVIDIA_NVENET_1PCI_DEVICE_ID_NVIDIA_NVENET_1 0x01c3 forcedeth.c 　
15154
 PCI_DEVICE_ID_NVIDIA_NVENET_2PCI_DEVICE_ID_NVIDIA_NVENET_2 0x0066 forcedeth.c 　
15155
 PCI_DEVICE_ID_NVIDIA_NVENET_4PCI_DEVICE_ID_NVIDIA_NVENET_4 0x0086 forcedeth.c 　
15156
 PCI_DEVICE_ID_NVIDIA_NVENET_5PCI_DEVICE_ID_NVIDIA_NVENET_5 0x008c forcedeth.c 　
15157
 PCI_DEVICE_ID_NVIDIA_NVENET_3PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6 forcedeth.c 　
15158
 PCI_DEVICE_ID_NVIDIA_NVENET_7PCI_DEVICE_ID_NVIDIA_NVENET_7 0x00df forcedeth.c 　
15159
 PCI_DEVICE_ID_NVIDIA_NVENET_6PCI_DEVICE_ID_NVIDIA_NVENET_6 0x00e6 forcedeth.c 　
15160
 PCI_DEVICE_ID_NVIDIA_NVENET_8PCI_DEVICE_ID_NVIDIA_NVENET_8 0x0056 forcedeth.c 　
15161
 PCI_DEVICE_ID_NVIDIA_NVENET_9PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057 forcedeth.c 　
15162
 PCI_DEVICE_ID_NVIDIA_NVENET_10PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037 forcedeth.c 　
15163
 PCI_DEVICE_ID_NVIDIA_NVENET_11PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038 forcedeth.c 　
15164
 PCI_DEVICE_ID_NVIDIA_NVENET_15PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373 forcedeth.c 　
15165
 DEV_NEED_LASTPACKET1DEV_NEED_LASTPACKET1 0x0001 forcedeth.c set LASTPACKET1 in tx flags
15166
 DEV_IRQMASK_1DEV_IRQMASK_1 0x0002 forcedeth.c use NVREG_IRQMASK_WANTED_1 for irq mask
15167
 DEV_IRQMASK_2DEV_IRQMASK_2 0x0004 forcedeth.c use NVREG_IRQMASK_WANTED_2 for irq mask
15168
 DEV_NEED_TIMERIRQDEV_NEED_TIMERIRQ 0x0008 forcedeth.c set the timer irq flag in the irq mask
15169
 DEV_NEED_LINKTIMERDEV_NEED_LINKTIMER 0x0010 forcedeth.c poll link settings. Relies on the timer irq
15170
 FLAG_MASK_V1FLAG_MASK_V1 0xffff0000 forcedeth.c 　
15171
 FLAG_MASK_V2FLAG_MASK_V2 0xffffc000 forcedeth.c 　
15172
 LEN_MASK_V1LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1) forcedeth.c 　
15173
 LEN_MASK_V2LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2) forcedeth.c 　
15174
 NV_TX_LASTPACKETNV_TX_LASTPACKET (1<<16) forcedeth.c 　
15175
 NV_TX_RETRYERRORNV_TX_RETRYERROR (1<<19) forcedeth.c 　
15176
 NV_TX_LASTPACKET1NV_TX_LASTPACKET1 (1<<24) forcedeth.c 　
15177
 NV_TX_DEFERREDNV_TX_DEFERRED (1<<26) forcedeth.c 　
15178
 NV_TX_CARRIERLOSTNV_TX_CARRIERLOST (1<<27) forcedeth.c 　
15179
 NV_TX_LATECOLLISIONNV_TX_LATECOLLISION (1<<28) forcedeth.c 　
15180
 NV_TX_UNDERFLOWNV_TX_UNDERFLOW (1<<29) forcedeth.c 　
15181
 NV_TX_ERRORNV_TX_ERROR (1<<30) forcedeth.c 　
15182
 NV_TX_VALIDNV_TX_VALID (1<<31) forcedeth.c 　
15183
 NV_TX2_LASTPACKETNV_TX2_LASTPACKET (1<<29) forcedeth.c 　
15184
 NV_TX2_RETRYERRORNV_TX2_RETRYERROR (1<<18) forcedeth.c 　
15185
 NV_TX2_LASTPACKET1NV_TX2_LASTPACKET1 (1<<23) forcedeth.c 　
15186
 NV_TX2_DEFERREDNV_TX2_DEFERRED (1<<25) forcedeth.c 　
15187
 NV_TX2_CARRIERLOSTNV_TX2_CARRIERLOST (1<<26) forcedeth.c 　
15188
 NV_TX2_LATECOLLISIONNV_TX2_LATECOLLISION (1<<27) forcedeth.c 　
15189
 NV_TX2_UNDERFLOWNV_TX2_UNDERFLOW (1<<28) forcedeth.c 　
15190
 NV_TX2_ERRORNV_TX2_ERROR (1<<30) forcedeth.c 　
15191
 NV_TX2_VALIDNV_TX2_VALID (1<<31) forcedeth.c 　
15192
 NV_RX_DESCRIPTORVALIDNV_RX_DESCRIPTORVALID (1<<16) forcedeth.c 　
15193
 NV_RX_MISSEDFRAMENV_RX_MISSEDFRAME (1<<17) forcedeth.c 　
15194
 NV_RX_SUBSTRACT1NV_RX_SUBSTRACT1 (1<<18) forcedeth.c 　
15195
 NV_RX_ERROR1NV_RX_ERROR1 (1<<23) forcedeth.c 　
15196
 NV_RX_ERROR2NV_RX_ERROR2 (1<<24) forcedeth.c 　
15197
 NV_RX_ERROR3NV_RX_ERROR3 (1<<25) forcedeth.c 　
15198
 NV_RX_ERROR4NV_RX_ERROR4 (1<<26) forcedeth.c 　
15199
 NV_RX_CRCERRNV_RX_CRCERR (1<<27) forcedeth.c 　
15200
 NV_RX_OVERFLOWNV_RX_OVERFLOW (1<<28) forcedeth.c 　
15201
 NV_RX_FRAMINGERRNV_RX_FRAMINGERR (1<<29) forcedeth.c 　
15202
 NV_RX_ERRORNV_RX_ERROR (1<<30) forcedeth.c 　
15203
 NV_RX_AVAILNV_RX_AVAIL (1<<31) forcedeth.c 　
15204
 NV_RX2_CHECKSUMMASKNV_RX2_CHECKSUMMASK (0x1C000000) forcedeth.c 　
15205
 NV_RX2_CHECKSUMOK1NV_RX2_CHECKSUMOK1 (0x10000000) forcedeth.c 　
15206
 NV_RX2_CHECKSUMOK2NV_RX2_CHECKSUMOK2 (0x14000000) forcedeth.c 　
15207
 NV_RX2_CHECKSUMOK3NV_RX2_CHECKSUMOK3 (0x18000000) forcedeth.c 　
15208
 NV_RX2_DESCRIPTORVALIDNV_RX2_DESCRIPTORVALID (1<<29) forcedeth.c 　
15209
 NV_RX2_SUBSTRACT1NV_RX2_SUBSTRACT1 (1<<25) forcedeth.c 　
15210
 NV_RX2_ERROR1NV_RX2_ERROR1 (1<<18) forcedeth.c 　
15211
 NV_RX2_ERROR2NV_RX2_ERROR2 (1<<19) forcedeth.c 　
15212
 NV_RX2_ERROR3NV_RX2_ERROR3 (1<<20) forcedeth.c 　
15213
 NV_RX2_ERROR4NV_RX2_ERROR4 (1<<21) forcedeth.c 　
15214
 NV_RX2_CRCERRNV_RX2_CRCERR (1<<22) forcedeth.c 　
15215
 NV_RX2_OVERFLOWNV_RX2_OVERFLOW (1<<23) forcedeth.c 　
15216
 NV_RX2_FRAMINGERRNV_RX2_FRAMINGERR (1<<24) forcedeth.c 　
15217
 NV_RX2_ERRORNV_RX2_ERROR (1<<30) forcedeth.c 　
15218
 NV_RX2_AVAILNV_RX2_AVAIL (1<<31) forcedeth.c 　
15219
 NV_PCI_REGSZNV_PCI_REGSZ 0x270 forcedeth.c 　
15220
 NV_TXRX_RESET_DELAYNV_TXRX_RESET_DELAY 4 forcedeth.c 　
15221
 NV_TXSTOP_DELAY1NV_TXSTOP_DELAY1 10 forcedeth.c 　
15222
 NV_TXSTOP_DELAY1MAXNV_TXSTOP_DELAY1MAX 500000 forcedeth.c 　
15223
 NV_TXSTOP_DELAY2NV_TXSTOP_DELAY2 100 forcedeth.c 　
15224
 NV_RXSTOP_DELAY1NV_RXSTOP_DELAY1 10 forcedeth.c 　
15225
 NV_RXSTOP_DELAY1MAXNV_RXSTOP_DELAY1MAX 500000 forcedeth.c 　
15226
 NV_RXSTOP_DELAY2NV_RXSTOP_DELAY2 100 forcedeth.c 　
15227
 NV_SETUP5_DELAYNV_SETUP5_DELAY 5 forcedeth.c 　
15228
 NV_SETUP5_DELAYMAXNV_SETUP5_DELAYMAX 50000 forcedeth.c 　
15229
 NV_POWERUP_DELAYNV_POWERUP_DELAY 5 forcedeth.c 　
15230
 NV_POWERUP_DELAYMAXNV_POWERUP_DELAYMAX 5000 forcedeth.c 　
15231
 NV_MIIBUSY_DELAYNV_MIIBUSY_DELAY 50 forcedeth.c 　
15232
 NV_MIIPHY_DELAYNV_MIIPHY_DELAY 10 forcedeth.c 　
15233
 NV_MIIPHY_DELAYMAXNV_MIIPHY_DELAYMAX 10000 forcedeth.c 　
15234
 NV_WAKEUPPATTERNSNV_WAKEUPPATTERNS 5 forcedeth.c 　
15235
 NV_WAKEUPMASKENTRIESNV_WAKEUPMASKENTRIES 4 forcedeth.c 　
15236
 NV_WATCHDOG_TIMEONV_WATCHDOG_TIMEO (5*HZ) forcedeth.c 　
15237
 RX_RINGRX_RING 4 forcedeth.c 　
15238
 TX_RINGTX_RING 2 forcedeth.c 　
15239
 TX_LIMIT_STOPTX_LIMIT_STOP 63 forcedeth.c 　
15240
 TX_LIMIT_STARTTX_LIMIT_START 62 forcedeth.c 　
15241
 RX_NIC_BUFSIZERX_NIC_BUFSIZE (ETH_DATA_LEN + 64) forcedeth.c 　
15242
 RX_ALLOC_BUFSIZERX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128) forcedeth.c 　
15243
 OOM_REFILLOOM_REFILL (1+HZ/20) forcedeth.c 　
15244
 POLL_WAITPOLL_WAIT (1+HZ/100) forcedeth.c 　
15245
 LINK_TIMEOUTLINK_TIMEOUT (3*HZ) forcedeth.c 　
15246
 DESC_VER_1DESC_VER_1 0x0 forcedeth.c 　
15247
 DESC_VER_2DESC_VER_2 (0x02100|NVREG_TXRXCTL_RXCHECK) forcedeth.c 　
15248
 PHY_OUI_MARVELLPHY_OUI_MARVELL 0x5043 forcedeth.c 　
15249
 PHY_OUI_CICADAPHY_OUI_CICADA 0x03f1 forcedeth.c 　
15250
 PHYID1_OUI_MASKPHYID1_OUI_MASK 0x03ff forcedeth.c 　
15251
 PHYID1_OUI_SHFTPHYID1_OUI_SHFT 6 forcedeth.c 　
15252
 PHYID2_OUI_MASKPHYID2_OUI_MASK 0xfc00 forcedeth.c 　
15253
 PHYID2_OUI_SHFTPHYID2_OUI_SHFT 10 forcedeth.c 　
15254
 PHY_INIT1PHY_INIT1 0x0f000 forcedeth.c 　
15255
 PHY_INIT2PHY_INIT2 0x0e00 forcedeth.c 　
15256
 PHY_INIT3PHY_INIT3 0x01000 forcedeth.c 　
15257
 PHY_INIT4PHY_INIT4 0x0200 forcedeth.c 　
15258
 PHY_INIT5PHY_INIT5 0x0004 forcedeth.c 　
15259
 PHY_INIT6PHY_INIT6 0x02000 forcedeth.c 　
15260
 PHY_GIGABITPHY_GIGABIT 0x0100 forcedeth.c 　
15261
 PHY_TIMEOUTPHY_TIMEOUT 0x1 forcedeth.c 　
15262
 PHY_ERRORPHY_ERROR 0x2 forcedeth.c 　
15263
 PHY_100PHY_100 0x1 forcedeth.c 　
15264
 PHY_1000PHY_1000 0x2 forcedeth.c 　
15265
 PHY_HALFPHY_HALF 0x100 forcedeth.c 　
15266
 MAC_ADDR_CORRECTMAC_ADDR_CORRECT 0x01 forcedeth.c 　
15267
 tx_ringtx_ring forcedeth_bufs.tx_ring forcedeth.c 　
15268
 rx_ringrx_ring forcedeth_bufs.rx_ring forcedeth.c 　
15269
 txbtxb forcedeth_bufs.txb forcedeth.c 　
15270
 rxbrxb forcedeth_bufs.rxb forcedeth.c 　
15271
 MII_READMII_READ (-1) forcedeth.c 　
15272
 IORESOURCE_MEMIORESOURCE_MEM 0x00000200 forcedeth.c 　
15273
 board_foundboard_found 1 forcedeth.c 　
15274
 valid_linkvalid_link 0 forcedeth.c 　
15275
 IPOIB_NUM_SEND_WQESIPOIB_NUM_SEND_WQES 2 ipoib.c 　
15276
 IPOIB_NUM_RECV_WQESIPOIB_NUM_RECV_WQES 4 ipoib.c 　
15277
 IPOIB_NUM_CQESIPOIB_NUM_CQES 8 ipoib.c 　
15278
 EINPROGRESS_JOININGEINPROGRESS_JOINING ( EINPROGRESS | EUNIQ_01 ) ipoib.c 　
15279
 IPOIB_NUM_CACHED_PEERSIPOIB_NUM_CACHED_PEERS 4 ipoib.c 　
15280
 TX_RING_SIZETX_RING_SIZE 2 mtd80x.c 　
15281
 TX_QUEUE_LENTX_QUEUE_LEN 10 mtd80x.c Limit ring entries actually used.
15282
 RX_RING_SIZERX_RING_SIZE 4 mtd80x.c 　
15283
 HZHZ 100 mtd80x.c 　
15284
 TX_TIME_OUTTX_TIME_OUT (6*HZ) mtd80x.c 　
15285
 PKT_BUF_SZPKT_BUF_SZ 1536 mtd80x.c 　
15286
 MASK_MIIR_MII_READMASK_MIIR_MII_READ 0x00000000 mtd80x.c 　
15287
 MASK_MIIR_MII_WRITEMASK_MIIR_MII_WRITE 0x00000008 mtd80x.c 　
15288
 MASK_MIIR_MII_MDOMASK_MIIR_MII_MDO 0x00000004 mtd80x.c 　
15289
 MASK_MIIR_MII_MDIMASK_MIIR_MII_MDI 0x00000002 mtd80x.c 　
15290
 MASK_MIIR_MII_MDCMASK_MIIR_MII_MDC 0x00000001 mtd80x.c 　
15291
 OP_READOP_READ 0x6000 mtd80x.c ST:01+OP:10+PHYAD+REGAD+TA:Z0
15292
 OP_WRITEOP_WRITE 0x5002 mtd80x.c ST:01+OP:01+PHYAD+REGAD+TA:10
15293
 MysonPHYIDMysonPHYID 0xd0000302 mtd80x.c 　
15294
 MysonPHYID0MysonPHYID0 0x0302 mtd80x.c 　
15295
 StatusRegisterStatusRegister 18 mtd80x.c 　
15296
 SPEED100SPEED100 0x0400 mtd80x.c bit10
15297
 FULLMODEFULLMODE 0x0800 mtd80x.c bit11
15298
 SeeqPHYID0SeeqPHYID0 0x0016 mtd80x.c 　
15299
 MIIRegister18MIIRegister18 18 mtd80x.c 　
15300
 SPD_DET_100SPD_DET_100 0x80 mtd80x.c 　
15301
 DPLX_DET_FULLDPLX_DET_FULL 0x40 mtd80x.c 　
15302
 AhdocPHYID0AhdocPHYID0 0x0022 mtd80x.c 　
15303
 DiagnosticRegDiagnosticReg 18 mtd80x.c 　
15304
 DPLX_FULLDPLX_FULL 0x0800 mtd80x.c 　
15305
 Speed_100Speed_100 0x0400 mtd80x.c 　
15306
 MarvellPHYID0MarvellPHYID0 0x0141 mtd80x.c 　
15307
 LevelOnePHYID0LevelOnePHYID0 0x0013 mtd80x.c 　
15308
 MII1000BaseTControlRegMII1000BaseTControlReg 9 mtd80x.c 　
15309
 MII1000BaseTStatusRegMII1000BaseTStatusReg 10 mtd80x.c 　
15310
 SpecificRegSpecificReg 17 mtd80x.c 　
15311
 PHYAbletoPerform1000FullDuplexPHYAbletoPerform1000FullDuplex 0x0200 mtd80x.c 　
15312
 PHYAbletoPerform1000HalfDuplexPHYAbletoPerform1000HalfDuplex 0x0100 mtd80x.c 　
15313
 PHY1000AbilityMaskPHY1000AbilityMask 0x300 mtd80x.c 　
15314
 SpeedMaskSpeedMask 0x0c000 mtd80x.c 　
15315
 Speed_1000MSpeed_1000M 0x08000 mtd80x.c 　
15316
 Speed_100MSpeed_100M 0x4000 mtd80x.c 　
15317
 Speed_10MSpeed_10M 0 mtd80x.c 　
15318
 Full_DuplexFull_Duplex 0x2000 mtd80x.c 　
15319
 LXT1000_100MLXT1000_100M 0x08000 mtd80x.c 　
15320
 LXT1000_1000MLXT1000_1000M 0x0c000 mtd80x.c 　
15321
 LXT1000_FullLXT1000_Full 0x200 mtd80x.c 　
15322
 PS10PS10 0x00080000 mtd80x.c 　
15323
 FDFD 0x00100000 mtd80x.c 　
15324
 PS1000PS1000 0x00010000 mtd80x.c 　
15325
 LinkIsUpLinkIsUp 0x0004 mtd80x.c 　
15326
 LinkIsUp2LinkIsUp2 0x00040000 mtd80x.c 　
15327
 txbtxb mtd80x_bufs.txb mtd80x.c 　
15328
 rxbrxb mtd80x_bufs.rxb mtd80x.c 　
15329
 MYRI10GE_TRANSMIT_WRAPMYRI10GE_TRANSMIT_WRAP 1U myri10ge.c 　
15330
 MYRI10GE_RECEIVE_WRAPMYRI10GE_RECEIVE_WRAP 7U myri10ge.c 　
15331
 MYRI10GE_RECEIVE_COMPLETION_WRAMYRI10GE_RECEIVE_COMPLETION_WRA 31U myri10ge.c 　
15332
 VS_ADDRVS_ADDR ( vs + 0x18 ) myri10ge.c 　
15333
 VS_DATAVS_DATA ( vs + 0x14 ) myri10ge.c 　
15334
 VS_MODEVS_MODE ( vs + 0x10 ) myri10ge.c 　
15335
 VS_MODE_READ32VS_MODE_READ32 0x3 myri10ge.c 　
15336
 VS_MODE_LOCATEVS_MODE_LOCATE 0x8 myri10ge.c 　
15337
 VS_LOCATE_STRING_SPECSVS_LOCATE_STRING_SPECS 0x3 myri10ge.c 　
15338
 INCLUDE_NEINCLUDE_NE 1 ne.c 　
15339
 NE_SCANNE_SCAN 0x300,0x280,0x320,0x340,0x380 ne.c 　
15340
 ASIC_PIOASIC_PIO NE_DATA ne2k_isa.c 　
15341
 HZHZ 100 ns83820.c 　
15342
 USE_64BIT_ADDRUSE_64BIT_ADDR "+" ns83820.c 　
15343
 TRY_DACTRY_DAC 1 ns83820.c 　
15344
 TRY_DACTRY_DAC 0 ns83820.c 　
15345
 RX_BUF_SIZERX_BUF_SIZE 1500 ns83820.c 8192
15346
 NR_RX_DESCNR_RX_DESC 64 ns83820.c 　
15347
 NR_TX_DESCNR_TX_DESC 1 ns83820.c 　
15348
 REAL_RX_BUF_SIZEREAL_RX_BUF_SIZE (RX_BUF_SIZE + 14 + 6) ns83820.c rx/tx mac addr + type
15349
 MIN_TX_DESC_FREEMIN_TX_DESC_FREE 8 ns83820.c 　
15350
 CFGCSCFGCS 0x04 ns83820.c 　
15351
 CR_TXECR_TXE 0x00000001 ns83820.c 　
15352
 CR_TXDCR_TXD 0x00000002 ns83820.c 　
15353
 CR_RXECR_RXE 0x00000004 ns83820.c 　
15354
 CR_RXDCR_RXD 0x00000008 ns83820.c 　
15355
 CR_TXRCR_TXR 0x00000010 ns83820.c 　
15356
 CR_RXRCR_RXR 0x00000020 ns83820.c 　
15357
 CR_SWICR_SWI 0x00000080 ns83820.c 　
15358
 CR_RSTCR_RST 0x00000100 ns83820.c 　
15359
 PTSCR_EEBIST_FAILPTSCR_EEBIST_FAIL 0x00000001 ns83820.c 　
15360
 PTSCR_EEBIST_ENPTSCR_EEBIST_EN 0x00000002 ns83820.c 　
15361
 PTSCR_EELOAD_ENPTSCR_EELOAD_EN 0x00000004 ns83820.c 　
15362
 PTSCR_RBIST_FAILPTSCR_RBIST_FAIL 0x000001b8 ns83820.c 　
15363
 PTSCR_RBIST_DONEPTSCR_RBIST_DONE 0x00000200 ns83820.c 　
15364
 PTSCR_RBIST_ENPTSCR_RBIST_EN 0x00000400 ns83820.c 　
15365
 PTSCR_RBIST_RSTPTSCR_RBIST_RST 0x00002000 ns83820.c 　
15366
 MEAR_EEDIMEAR_EEDI 0x00000001 ns83820.c 　
15367
 MEAR_EEDOMEAR_EEDO 0x00000002 ns83820.c 　
15368
 MEAR_EECLKMEAR_EECLK 0x00000004 ns83820.c 　
15369
 MEAR_EESELMEAR_EESEL 0x00000008 ns83820.c 　
15370
 MEAR_MDIOMEAR_MDIO 0x00000010 ns83820.c 　
15371
 MEAR_MDDIRMEAR_MDDIR 0x00000020 ns83820.c 　
15372
 MEAR_MDCMEAR_MDC 0x00000040 ns83820.c 　
15373
 ISR_TXDESC3ISR_TXDESC3 0x40000000 ns83820.c 　
15374
 ISR_TXDESC2ISR_TXDESC2 0x20000000 ns83820.c 　
15375
 ISR_TXDESC1ISR_TXDESC1 0x10000000 ns83820.c 　
15376
 ISR_TXDESC0ISR_TXDESC0 0x08000000 ns83820.c 　
15377
 ISR_RXDESC3ISR_RXDESC3 0x04000000 ns83820.c 　
15378
 ISR_RXDESC2ISR_RXDESC2 0x02000000 ns83820.c 　
15379
 ISR_RXDESC1ISR_RXDESC1 0x01000000 ns83820.c 　
15380
 ISR_RXDESC0ISR_RXDESC0 0x00800000 ns83820.c 　
15381
 ISR_TXRCMPISR_TXRCMP 0x00400000 ns83820.c 　
15382
 ISR_RXRCMPISR_RXRCMP 0x00200000 ns83820.c 　
15383
 ISR_DPERRISR_DPERR 0x00100000 ns83820.c 　
15384
 ISR_SSERRISR_SSERR 0x00080000 ns83820.c 　
15385
 ISR_RMABTISR_RMABT 0x00040000 ns83820.c 　
15386
 ISR_RTABTISR_RTABT 0x00020000 ns83820.c 　
15387
 ISR_RXSOVRISR_RXSOVR 0x00010000 ns83820.c 　
15388
 ISR_HIBINTISR_HIBINT 0x00008000 ns83820.c 　
15389
 ISR_PHYISR_PHY 0x00004000 ns83820.c 　
15390
 ISR_PMEISR_PME 0x00002000 ns83820.c 　
15391
 ISR_SWIISR_SWI 0x00001000 ns83820.c 　
15392
 ISR_MIBISR_MIB 0x00000800 ns83820.c 　
15393
 ISR_TXURNISR_TXURN 0x00000400 ns83820.c 　
15394
 ISR_TXIDLEISR_TXIDLE 0x00000200 ns83820.c 　
15395
 ISR_TXERRISR_TXERR 0x00000100 ns83820.c 　
15396
 ISR_TXDESCISR_TXDESC 0x00000080 ns83820.c 　
15397
 ISR_TXOKISR_TXOK 0x00000040 ns83820.c 　
15398
 ISR_RXORNISR_RXORN 0x00000020 ns83820.c 　
15399
 ISR_RXIDLEISR_RXIDLE 0x00000010 ns83820.c 　
15400
 ISR_RXEARLYISR_RXEARLY 0x00000008 ns83820.c 　
15401
 ISR_RXERRISR_RXERR 0x00000004 ns83820.c 　
15402
 ISR_RXDESCISR_RXDESC 0x00000002 ns83820.c 　
15403
 ISR_RXOKISR_RXOK 0x00000001 ns83820.c 　
15404
 TXCFG_CSITXCFG_CSI 0x80000000 ns83820.c 　
15405
 TXCFG_HBITXCFG_HBI 0x40000000 ns83820.c 　
15406
 TXCFG_MLBTXCFG_MLB 0x20000000 ns83820.c 　
15407
 TXCFG_ATPTXCFG_ATP 0x10000000 ns83820.c 　
15408
 TXCFG_ECRETRYTXCFG_ECRETRY 0x00800000 ns83820.c 　
15409
 TXCFG_BRST_DISTXCFG_BRST_DIS 0x00080000 ns83820.c 　
15410
 TXCFG_MXDMA1024TXCFG_MXDMA1024 0x00000000 ns83820.c 　
15411
 TXCFG_MXDMA512TXCFG_MXDMA512 0x00700000 ns83820.c 　
15412
 TXCFG_MXDMA256TXCFG_MXDMA256 0x00600000 ns83820.c 　
15413
 TXCFG_MXDMA128TXCFG_MXDMA128 0x00500000 ns83820.c 　
15414
 TXCFG_MXDMA64TXCFG_MXDMA64 0x00400000 ns83820.c 　
15415
 TXCFG_MXDMA32TXCFG_MXDMA32 0x00300000 ns83820.c 　
15416
 TXCFG_MXDMA16TXCFG_MXDMA16 0x00200000 ns83820.c 　
15417
 TXCFG_MXDMA8TXCFG_MXDMA8 0x00100000 ns83820.c 　
15418
 CFG_LNKSTSCFG_LNKSTS 0x80000000 ns83820.c 　
15419
 CFG_SPDSTSCFG_SPDSTS 0x60000000 ns83820.c 　
15420
 CFG_SPDSTS1CFG_SPDSTS1 0x40000000 ns83820.c 　
15421
 CFG_SPDSTS0CFG_SPDSTS0 0x20000000 ns83820.c 　
15422
 CFG_DUPSTSCFG_DUPSTS 0x10000000 ns83820.c 　
15423
 CFG_TBI_ENCFG_TBI_EN 0x01000000 ns83820.c 　
15424
 CFG_MODE_1000CFG_MODE_1000 0x00400000 ns83820.c 　
15425
 CFG_AUTO_1000CFG_AUTO_1000 0x00200000 ns83820.c 　
15426
 CFG_PINT_CTLCFG_PINT_CTL 0x001c0000 ns83820.c 　
15427
 CFG_PINT_DUPSTSCFG_PINT_DUPSTS 0x00100000 ns83820.c 　
15428
 CFG_PINT_LNKSTSCFG_PINT_LNKSTS 0x00080000 ns83820.c 　
15429
 CFG_PINT_SPDSTSCFG_PINT_SPDSTS 0x00040000 ns83820.c 　
15430
 CFG_TMRTESTCFG_TMRTEST 0x00020000 ns83820.c 　
15431
 CFG_MRM_DISCFG_MRM_DIS 0x00010000 ns83820.c 　
15432
 CFG_MWI_DISCFG_MWI_DIS 0x00008000 ns83820.c 　
15433
 CFG_T64ADDRCFG_T64ADDR 0x00004000 ns83820.c 　
15434
 CFG_PCI64_DETCFG_PCI64_DET 0x00002000 ns83820.c 　
15435
 CFG_DATA64_ENCFG_DATA64_EN 0x00001000 ns83820.c 　
15436
 CFG_M64ADDRCFG_M64ADDR 0x00000800 ns83820.c 　
15437
 CFG_PHY_RSTCFG_PHY_RST 0x00000400 ns83820.c 　
15438
 CFG_PHY_DISCFG_PHY_DIS 0x00000200 ns83820.c 　
15439
 CFG_EXTSTS_ENCFG_EXTSTS_EN 0x00000100 ns83820.c 　
15440
 CFG_REQALGCFG_REQALG 0x00000080 ns83820.c 　
15441
 CFG_SBCFG_SB 0x00000040 ns83820.c 　
15442
 CFG_POWCFG_POW 0x00000020 ns83820.c 　
15443
 CFG_EXDCFG_EXD 0x00000010 ns83820.c 　
15444
 CFG_PESELCFG_PESEL 0x00000008 ns83820.c 　
15445
 CFG_BROM_DISCFG_BROM_DIS 0x00000004 ns83820.c 　
15446
 CFG_EXT_125CFG_EXT_125 0x00000002 ns83820.c 　
15447
 CFG_BEMCFG_BEM 0x00000001 ns83820.c 　
15448
 EXTSTS_UDPPKTEXTSTS_UDPPKT 0x00200000 ns83820.c 　
15449
 EXTSTS_TCPPKTEXTSTS_TCPPKT 0x00080000 ns83820.c 　
15450
 EXTSTS_IPPKTEXTSTS_IPPKT 0x00020000 ns83820.c 　
15451
 SPDSTS_POLARITYSPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) ns83820.c 　
15452
 MIBC_MIBSMIBC_MIBS 0x00000008 ns83820.c 　
15453
 MIBC_ACLRMIBC_ACLR 0x00000004 ns83820.c 　
15454
 MIBC_FRZMIBC_FRZ 0x00000002 ns83820.c 　
15455
 MIBC_WRNMIBC_WRN 0x00000001 ns83820.c 　
15456
 PCR_PSENPCR_PSEN (1 << 31) ns83820.c 　
15457
 PCR_PS_MCASTPCR_PS_MCAST (1 << 30) ns83820.c 　
15458
 PCR_PS_DAPCR_PS_DA (1 << 29) ns83820.c 　
15459
 PCR_STHI_8PCR_STHI_8 (3 << 23) ns83820.c 　
15460
 PCR_STLO_4PCR_STLO_4 (1 << 23) ns83820.c 　
15461
 PCR_FFHI_8KPCR_FFHI_8K (3 << 21) ns83820.c 　
15462
 PCR_FFLO_4KPCR_FFLO_4K (1 << 21) ns83820.c 　
15463
 PCR_PAUSE_CNTPCR_PAUSE_CNT 0xFFFE ns83820.c 　
15464
 RXCFG_AEPRXCFG_AEP 0x80000000 ns83820.c 　
15465
 RXCFG_ARPRXCFG_ARP 0x40000000 ns83820.c 　
15466
 RXCFG_STRIPCRCRXCFG_STRIPCRC 0x20000000 ns83820.c 　
15467
 RXCFG_RX_FDRXCFG_RX_FD 0x10000000 ns83820.c 　
15468
 RXCFG_ALPRXCFG_ALP 0x08000000 ns83820.c 　
15469
 RXCFG_AIRLRXCFG_AIRL 0x04000000 ns83820.c 　
15470
 RXCFG_MXDMA512RXCFG_MXDMA512 0x00700000 ns83820.c 　
15471
 RXCFG_DRTHRXCFG_DRTH 0x0000003e ns83820.c 　
15472
 RXCFG_DRTH0RXCFG_DRTH0 0x00000002 ns83820.c 　
15473
 RFCR_RFENRFCR_RFEN 0x80000000 ns83820.c 　
15474
 RFCR_AABRFCR_AAB 0x40000000 ns83820.c 　
15475
 RFCR_AAMRFCR_AAM 0x20000000 ns83820.c 　
15476
 RFCR_AAURFCR_AAU 0x10000000 ns83820.c 　
15477
 RFCR_APMRFCR_APM 0x08000000 ns83820.c 　
15478
 RFCR_APATRFCR_APAT 0x07800000 ns83820.c 　
15479
 RFCR_APAT3RFCR_APAT3 0x04000000 ns83820.c 　
15480
 RFCR_APAT2RFCR_APAT2 0x02000000 ns83820.c 　
15481
 RFCR_APAT1RFCR_APAT1 0x01000000 ns83820.c 　
15482
 RFCR_APAT0RFCR_APAT0 0x00800000 ns83820.c 　
15483
 RFCR_AARPRFCR_AARP 0x00400000 ns83820.c 　
15484
 RFCR_MHENRFCR_MHEN 0x00200000 ns83820.c 　
15485
 RFCR_UHENRFCR_UHEN 0x00100000 ns83820.c 　
15486
 RFCR_ULMRFCR_ULM 0x00080000 ns83820.c 　
15487
 VRCR_RUDPEVRCR_RUDPE 0x00000080 ns83820.c 　
15488
 VRCR_RTCPEVRCR_RTCPE 0x00000040 ns83820.c 　
15489
 VRCR_RIPEVRCR_RIPE 0x00000020 ns83820.c 　
15490
 VRCR_IPENVRCR_IPEN 0x00000010 ns83820.c 　
15491
 VRCR_DUTFVRCR_DUTF 0x00000008 ns83820.c 　
15492
 VRCR_DVTFVRCR_DVTF 0x00000004 ns83820.c 　
15493
 VRCR_VTRENVRCR_VTREN 0x00000002 ns83820.c 　
15494
 VRCR_VTDENVRCR_VTDEN 0x00000001 ns83820.c 　
15495
 VTCR_PPCHKVTCR_PPCHK 0x00000008 ns83820.c 　
15496
 VTCR_GCHKVTCR_GCHK 0x00000004 ns83820.c 　
15497
 VTCR_VPPTIVTCR_VPPTI 0x00000002 ns83820.c 　
15498
 VTCR_VGTIVTCR_VGTI 0x00000001 ns83820.c 　
15499
 CRCR 0x00 ns83820.c 　
15500
 CFGCFG 0x04 ns83820.c 　
15501
 MEARMEAR 0x08 ns83820.c 　
15502
 PTSCRPTSCR 0x0c ns83820.c 　
15503
 ISRISR 0x10 ns83820.c 　
15504
 IMRIMR 0x14 ns83820.c 　
15505
 IERIER 0x18 ns83820.c 　
15506
 IHRIHR 0x1c ns83820.c 　
15507
 TXDPTXDP 0x20 ns83820.c 　
15508
 TXDP_HITXDP_HI 0x24 ns83820.c 　
15509
 TXCFGTXCFG 0x28 ns83820.c 　
15510
 GPIORGPIOR 0x2c ns83820.c 　
15511
 RXDPRXDP 0x30 ns83820.c 　
15512
 RXDP_HIRXDP_HI 0x34 ns83820.c 　
15513
 RXCFGRXCFG 0x38 ns83820.c 　
15514
 PQCRPQCR 0x3c ns83820.c 　
15515
 WCSRWCSR 0x40 ns83820.c 　
15516
 PCRPCR 0x44 ns83820.c 　
15517
 RFCRRFCR 0x48 ns83820.c 　
15518
 RFDRRFDR 0x4c ns83820.c 　
15519
 SRRSRR 0x58 ns83820.c 　
15520
 VRCRVRCR 0xbc ns83820.c 　
15521
 VTCRVTCR 0xc0 ns83820.c 　
15522
 VDRVDR 0xc4 ns83820.c 　
15523
 CCSRCCSR 0xcc ns83820.c 　
15524
 TBICRTBICR 0xe0 ns83820.c 　
15525
 TBISRTBISR 0xe4 ns83820.c 　
15526
 TANARTANAR 0xe8 ns83820.c 　
15527
 TANLPARTANLPAR 0xec ns83820.c 　
15528
 TANERTANER 0xf0 ns83820.c 　
15529
 TESRTESR 0xf4 ns83820.c 　
15530
 TBICR_MR_AN_ENABLETBICR_MR_AN_ENABLE 0x00001000 ns83820.c 　
15531
 TBICR_MR_RESTART_ANTBICR_MR_RESTART_AN 0x00000200 ns83820.c 　
15532
 TBISR_MR_LINK_STATUSTBISR_MR_LINK_STATUS 0x00000020 ns83820.c 　
15533
 TBISR_MR_AN_COMPLETETBISR_MR_AN_COMPLETE 0x00000004 ns83820.c 　
15534
 TANAR_PS2TANAR_PS2 0x00000100 ns83820.c 　
15535
 TANAR_PS1TANAR_PS1 0x00000080 ns83820.c 　
15536
 TANAR_HALF_DUPTANAR_HALF_DUP 0x00000040 ns83820.c 　
15537
 TANAR_FULL_DUPTANAR_FULL_DUP 0x00000020 ns83820.c 　
15538
 GPIOR_GP5_OEGPIOR_GP5_OE 0x00000200 ns83820.c 　
15539
 GPIOR_GP4_OEGPIOR_GP4_OE 0x00000100 ns83820.c 　
15540
 GPIOR_GP3_OEGPIOR_GP3_OE 0x00000080 ns83820.c 　
15541
 GPIOR_GP2_OEGPIOR_GP2_OE 0x00000040 ns83820.c 　
15542
 GPIOR_GP1_OEGPIOR_GP1_OE 0x00000020 ns83820.c 　
15543
 GPIOR_GP3_OUTGPIOR_GP3_OUT 0x00000004 ns83820.c 　
15544
 GPIOR_GP1_OUTGPIOR_GP1_OUT 0x00000001 ns83820.c 　
15545
 LINK_AUTONEGOTIATELINK_AUTONEGOTIATE 0x01 ns83820.c 　
15546
 LINK_DOWNLINK_DOWN 0x02 ns83820.c 　
15547
 LINK_UPLINK_UP 0x04 ns83820.c 　
15548
 HW_ADDR_LENHW_ADDR_LEN 8 ns83820.c 　
15549
 HW_ADDR_LENHW_ADDR_LEN 4 ns83820.c 　
15550
 CMDSTS_OWNCMDSTS_OWN 0x80000000 ns83820.c 　
15551
 CMDSTS_MORECMDSTS_MORE 0x40000000 ns83820.c 　
15552
 CMDSTS_INTRCMDSTS_INTR 0x20000000 ns83820.c 　
15553
 CMDSTS_ERRCMDSTS_ERR 0x10000000 ns83820.c 　
15554
 CMDSTS_OKCMDSTS_OK 0x08000000 ns83820.c 　
15555
 CMDSTS_LEN_MASKCMDSTS_LEN_MASK 0x0000ffff ns83820.c 　
15556
 CMDSTS_DEST_MASKCMDSTS_DEST_MASK 0x01800000 ns83820.c 　
15557
 CMDSTS_DEST_SELFCMDSTS_DEST_SELF 0x00800000 ns83820.c 　
15558
 CMDSTS_DEST_MULTICMDSTS_DEST_MULTI 0x01000000 ns83820.c 　
15559
 DESC_SIZEDESC_SIZE 8 ns83820.c Should be cache line sized
15560
 tx_ringtx_ring ns83820_bufs.tx_ring ns83820.c 　
15561
 rx_ringrx_ring ns83820_bufs.rx_ring ns83820.c 　
15562
 txbtxb ns83820_bufs.txb ns83820.c 　
15563
 rxbrxb ns83820_bufs.rxb ns83820.c 　
15564
 board_foundboard_found 1 ns83820.c 　
15565
 valid_linkvalid_link 0 ns83820.c 　
15566
 ASIC_PIOASIC_PIO WD_IAR ns8390.c 　
15567
 eth_probeeth_probe wd_probe ns8390.c 　
15568
 MAX_JOIN_INFO_COUNTMAX_JOIN_INFO_COUNT 2 prism2.c 　
15569
 WLAN_HOSTIFWLAN_HOSTIF WLAN_PLX prism2.c 　
15570
 BAP_TIMEOUTBAP_TIMEOUT ( 5000 ) prism2.c 　
15571
 PLX_LOCAL_CONFIG_REGISTER_BASEPLX_LOCAL_CONFIG_REGISTER_BASE ( PCI_BASE_ADDRESS_1 ) prism2.c 　
15572
 PLX_LOCAL_ADDRESS_SPACE_0_BASEPLX_LOCAL_ADDRESS_SPACE_0_BASE ( PCI_BASE_ADDRESS_2 ) prism2.c 　
15573
 PLX_LOCAL_ADDRESS_SPACE_1_BASEPLX_LOCAL_ADDRESS_SPACE_1_BASE ( PCI_BASE_ADDRESS_3 ) prism2.c 　
15574
 PLX_LOCAL_ADDRESS_SPACE_2_BASEPLX_LOCAL_ADDRESS_SPACE_2_BASE ( PCI_BASE_ADDRESS_4 ) prism2.c 　
15575
 PLX_LOCAL_ADDRESS_SPACE_3_BASEPLX_LOCAL_ADDRESS_SPACE_3_BASE ( PCI_BASE_ADDRESS_5 ) prism2.c 　
15576
 PRISM2_PLX_ATTR_MEM_BASEPRISM2_PLX_ATTR_MEM_BASE ( PLX_LOCAL_ADDRESS_SPACE_0_BASE ) prism2.c 　
15577
 PRISM2_PLX_IO_BASEPRISM2_PLX_IO_BASE ( PLX_LOCAL_ADDRESS_SPACE_1_BASE ) prism2.c 　
15578
 PRISM2_PCI_MEM_BASEPRISM2_PCI_MEM_BASE ( PCI_BASE_ADDRESS_0 ) prism2.c 　
15579
 CISTPL_VERS_1CISTPL_VERS_1 ( 0x15 ) prism2.c 　
15580
 CISTPL_ENDCISTPL_END ( 0xff ) prism2.c 　
15581
 CIS_STEPCIS_STEP ( 2 ) prism2.c 　
15582
 CISTPL_HEADER_LENCISTPL_HEADER_LEN ( 2 * CIS_STEP ) prism2.c 　
15583
 CISTPL_LEN_OFFCISTPL_LEN_OFF ( 1 * CIS_STEP ) prism2.c 　
15584
 CISTPL_VERS_1_STR_OFFCISTPL_VERS_1_STR_OFF ( 4 * CIS_STEP ) prism2.c 　
15585
 COR_OFFSETCOR_OFFSET ( 0x3e0 ) prism2.c COR attribute offset of Prism2 PC card
15586
 COR_VALUECOR_VALUE ( 0x41 ) prism2.c Enable PC card with irq in level trigger (but interrupts disabled)
15587
 WLAN_IEEE_OUI_LENWLAN_IEEE_OUI_LEN 3 prism2.c 　
15588
 WLAN_HOSTIFWLAN_HOSTIF WLAN_PCI prism2_pci.c 　
15589
 WLAN_HOSTIFWLAN_HOSTIF WLAN_PLX prism2_plx.c 　
15590
 R8168_CPCMD_QUIRK_MASKR8168_CPCMD_QUIRK_MASK (\ EnableBist | \ Mac_dbgo_oe | \ Force_half_dup | \ Force_rxflow_en | \ Force_txflow_en | \ Cxpl_dbg_sel | \ ASF | \ PktCntrDi r8169.c 　
15591
 R810X_CPCMD_QUIRK_MASKR810X_CPCMD_QUIRK_MASK (\ EnableBist | \ Mac_dbgo_oe | \ Force_half_dup | \ Force_half_dup | \ Force_txflow_en | \ Cxpl_dbg_sel | \ ASF | \ PktCntrDis r8169.c 　
15592
 TX_RING_SIZETX_RING_SIZE 4 rtl8139.c 　
15593
 TX_FIFO_THRESHTX_FIFO_THRESH 256 rtl8139.c In bytes, rounded down to 32 byte units.
15594
 RX_FIFO_THRESHRX_FIFO_THRESH 4 rtl8139.c Rx buffer level before first PCI xfer.
15595
 RX_DMA_BURSTRX_DMA_BURST 4 rtl8139.c Maximum PCI burst, '4' is 256 bytes
15596
 TX_DMA_BURSTTX_DMA_BURST 4 rtl8139.c Calculate as 16<<val.
15597
 TX_IPGTX_IPG 3 rtl8139.c This is the only valid value
15598
 RX_BUF_LEN_IDXRX_BUF_LEN_IDX 0 rtl8139.c 0, 1, 2 is allowed - 8,16,32K rx buffer
15599
 RX_BUF_LENRX_BUF_LEN ( (8192 << RX_BUF_LEN_IDX) ) rtl8139.c 　
15600
 RX_BUF_PADRX_BUF_PAD 4 rtl8139.c 　
15601
 EE_M1EE_M1 0x80 rtl8139.c Mode select bit 1
15602
 EE_M0EE_M0 0x40 rtl8139.c Mode select bit 0
15603
 EE_CSEE_CS 0x08 rtl8139.c EEPROM chip select
15604
 EE_SKEE_SK 0x04 rtl8139.c EEPROM shift clock
15605
 EE_DIEE_DI 0x02 rtl8139.c Data in
15606
 EE_DOEE_DO 0x01 rtl8139.c Data out
15607
 EE_MACEE_MAC 7 rtl8139.c 　
15608
 txdtxd sis900_bufs.txd sis900.c 　
15609
 rxdrxd sis900_bufs.rxd sis900.c 　
15610
 txbtxb sis900_bufs.txb sis900.c 　
15611
 rxbrxb sis900_bufs.rxb sis900.c 　
15612
 DRV_NAMEDRV_NAME "sky2" sky2.c 　
15613
 DRV_VERSIONDRV_VERSION "1.22" sky2.c 　
15614
 PFXPFX DRV_NAME " " sky2.c 　
15615
 RX_LE_SIZERX_LE_SIZE 128 sky2.c 　
15616
 RX_LE_BYTESRX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) sky2.c 　
15617
 RX_RING_ALIGNRX_RING_ALIGN 4096 sky2.c 　
15618
 RX_PENDINGRX_PENDING (RX_LE_SIZE/6 - 2) sky2.c 　
15619
 TX_RING_SIZETX_RING_SIZE 128 sky2.c 　
15620
 TX_PENDINGTX_PENDING (TX_RING_SIZE - 1) sky2.c 　
15621
 TX_RING_ALIGNTX_RING_ALIGN 4096 sky2.c 　
15622
 MAX_SKB_TX_LEMAX_SKB_TX_LE 4 sky2.c 　
15623
 STATUS_RING_SIZESTATUS_RING_SIZE 512 sky2.c 2 ports * (TX + RX)
15624
 STATUS_LE_BYTESSTATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) sky2.c 　
15625
 STATUS_RING_ALIGNSTATUS_RING_ALIGN 4096 sky2.c 　
15626
 PHY_RETRIESPHY_RETRIES 1000 sky2.c 　
15627
 SKY2_EEPROM_MAGICSKY2_EEPROM_MAGIC 0x9955aabb sky2.c 　
15628
 LINUX_OUT_MACROSLINUX_OUT_MACROS 1 smc9000.c 　
15629
 SMC9000_DEBUGSMC9000_DEBUG 0 smc9000.c 　
15630
 PRINTK2PRINTK2 printf smc9000.c 　
15631
 _outb_outb outb smc9000.c 　
15632
 _outw_outw outw smc9000.c 　
15633
 drv_versiondrv_version "v1.12" sundance.c 　
15634
 drv_datedrv_date "2004-03-21" sundance.c 　
15635
 HZHZ 100 sundance.c 　
15636
 TX_RING_SIZETX_RING_SIZE 2 sundance.c 　
15637
 TX_QUEUE_LENTX_QUEUE_LEN 10 sundance.c Limit ring entries actually used.
15638
 RX_RING_SIZERX_RING_SIZE 4 sundance.c 　
15639
 TX_TIME_OUTTX_TIME_OUT (4*HZ) sundance.c 　
15640
 PKT_BUF_SZPKT_BUF_SZ 1536 sundance.c 　
15641
 rxbrxb rx_tx_buf.rxb sundance.c 　
15642
 txbtxb rx_tx_buf.txb sundance.c 　
15643
 EEPROM_SIZEEEPROM_SIZE 128 sundance.c 　
15644
 PCI_IOTYPEPCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0) sundance.c 　
15645
 MII_CNTMII_CNT 4 sundance.c 　
15646
 EEPROM_SA_OFFSETEEPROM_SA_OFFSET 0x10 sundance.c 　
15647
 DEFAULT_INTRDEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \ IntrDrvRqst | IntrTxDone | StatsMax | \ LinkChange) sundance.c 　
15648
 MDIO_EnbInMDIO_EnbIn (0) sundance.c 　
15649
 MDIO_WRITE0MDIO_WRITE0 (MDIO_EnbOutput) sundance.c 　
15650
 MDIO_WRITE1MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput) sundance.c 　
15651
 SUPPORT_COPPER_PHYSUPPORT_COPPER_PHY 1 tg3.c 　
15652
 SUPPORT_FIBER_PHYSUPPORT_FIBER_PHY 1 tg3.c 　
15653
 SUPPORT_LINK_REPORTSUPPORT_LINK_REPORT 1 tg3.c 　
15654
 SUPPORT_PARTNO_STRSUPPORT_PARTNO_STR 1 tg3.c 　
15655
 SUPPORT_PHY_STRSUPPORT_PHY_STR 1 tg3.c 　
15656
 TG3_RX_RING_SIZETG3_RX_RING_SIZE 512 tg3.c 　
15657
 TG3_DEF_RX_RING_PENDINGTG3_DEF_RX_RING_PENDING 20 tg3.c RX_RING_PENDING seems to be o.k. at 20 and 200
15658
 TG3_RX_RCB_RING_SIZETG3_RX_RCB_RING_SIZE 1024 tg3.c 　
15659
 TG3_TX_RING_SIZETG3_TX_RING_SIZE 512 tg3.c 　
15660
 TG3_DEF_TX_RING_PENDINGTG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1) tg3.c 　
15661
 TG3_RX_RING_BYTESTG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE) tg3.c 　
15662
 TG3_RX_RCB_RING_BYTESTG3_RX_RCB_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE) tg3.c 　
15663
 TG3_TX_RING_BYTESTG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE) tg3.c 　
15664
 RX_PKT_BUF_SZRX_PKT_BUF_SZ (1536 + 2 + 64) tg3.c 　
15665
 PHY_BUSY_LOOPSPHY_BUSY_LOOPS 5000 tg3.c 　
15666
 ANEG_OKANEG_OK 0 tg3.c 　
15667
 ANEG_DONEANEG_DONE 1 tg3.c 　
15668
 ANEG_TIMER_ENABANEG_TIMER_ENAB 2 tg3.c 　
15669
 ANEG_FAILEDANEG_FAILED -1 tg3.c 　
15670
 ANEG_STATE_SETTLE_TIMEANEG_STATE_SETTLE_TIME 10000 tg3.c 　
15671
 MAX_WAIT_CNTMAX_WAIT_CNT 1000 tg3.c 　
15672
 drv_versiondrv_version "v1.4" tlan.c 　
15673
 drv_datedrv_date "01-17-2004" tlan.c 　
15674
 HZHZ 100 tlan.c 　
15675
 TX_TIME_OUTTX_TIME_OUT (6*HZ) tlan.c 　
15676
 tx_ringtx_ring tlan_buffers.tx_ring tlan.c 　
15677
 txbtxb tlan_buffers.txb tlan.c 　
15678
 rx_ringrx_ring tlan_buffers.rx_ring tlan.c 　
15679
 rxbrxb tlan_buffers.rxb tlan.c 　
15680
 board_foundboard_found 1 tlan.c 　
15681
 valid_linkvalid_link 0 tlan.c 　
15682
 TX_TIME_OUTTX_TIME_OUT 2*TICKS_PER_SEC tulip.c 　
15683
 TULIP_IOTYPETULIP_IOTYPE PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0 tulip.c 　
15684
 TULIP_SIZETULIP_SIZE 0x80 tulip.c 　
15685
 FULL_DUPLEX_MAGICFULL_DUPLEX_MAGIC 0x6969 tulip.c 　
15686
 MEDIA_MASKMEDIA_MASK 31 tulip.c 　
15687
 EEPROM_ADDRLENEEPROM_ADDRLEN 6 tulip.c 　
15688
 EEPROM_SIZEEEPROM_SIZE 128 tulip.c 2 << EEPROM_ADDRLEN
15689
 EE_WRITE_CMDEE_WRITE_CMD (5 << addr_len) tulip.c 　
15690
 EE_READ_CMDEE_READ_CMD (6 << addr_len) tulip.c 　
15691
 EE_ERASE_CMDEE_ERASE_CMD (7 << addr_len) tulip.c 　
15692
 EE_SHIFT_CLKEE_SHIFT_CLK 0x02 tulip.c EEPROM shift clock.
15693
 EE_CSEE_CS 0x01 tulip.c EEPROM chip select.
15694
 EE_DATA_WRITEEE_DATA_WRITE 0x04 tulip.c EEPROM chip data in.
15695
 EE_WRITE_0EE_WRITE_0 0x01 tulip.c 　
15696
 EE_WRITE_1EE_WRITE_1 0x05 tulip.c 　
15697
 EE_DATA_READEE_DATA_READ 0x08 tulip.c EEPROM chip data out.
15698
 EE_ENBEE_ENB (0x4800 | EE_CS) tulip.c 　
15699
 BUFLENBUFLEN 1536 tulip.c 　
15700
 DESC_RING_WRAPDESC_RING_WRAP 0x02000000 tulip.c 　
15701
 TX_RING_SIZETX_RING_SIZE 2 tulip.c 　
15702
 RX_RING_SIZERX_RING_SIZE 4 tulip.c 　
15703
 tx_ringtx_ring tulip_bss.tx_ring tulip.c 　
15704
 txbtxb tulip_bss.txb tulip.c 　
15705
 rx_ringrx_ring tulip_bss.rx_ring tulip.c 　
15706
 rxbrxb tulip_bss.rxb tulip.c 　
15707
 MDIO_SHIFT_CLKMDIO_SHIFT_CLK 0x10000 tulip.c 　
15708
 MDIO_DATA_WRITE0MDIO_DATA_WRITE0 0x00000 tulip.c 　
15709
 MDIO_DATA_WRITE1MDIO_DATA_WRITE1 0x20000 tulip.c 　
15710
 MDIO_ENBMDIO_ENB 0x00000 tulip.c Ignore the 0x02000 databook setting.
15711
 MDIO_ENB_INMDIO_ENB_IN 0x40000 tulip.c 　
15712
 MDIO_DATA_READMDIO_DATA_READ 0x80000 tulip.c 　
15713
 W_MAX_TIMEOUTW_MAX_TIMEOUT 0x0FFFU via-rhine.c 　
15714
 RX_BUF_LEN_IDXRX_BUF_LEN_IDX 3 via-rhine.c 0==8K, 1==16K, 2==32K, 3==64K
15715
 RX_BUF_LENRX_BUF_LEN (8192 << RX_BUF_LEN_IDX) via-rhine.c 　
15716
 TX_BUF_SIZETX_BUF_SIZE 1536 via-rhine.c 　
15717
 RX_BUF_SIZERX_BUF_SIZE 1536 via-rhine.c 　
15718
 TX_FIFO_THRESHTX_FIFO_THRESH 256 via-rhine.c In bytes, rounded down to 32 byte units.
15719
 RX_FIFO_THRESHRX_FIFO_THRESH 4 via-rhine.c Rx buffer level before first PCI xfer.
15720
 RX_DMA_BURSTRX_DMA_BURST 4 via-rhine.c Maximum PCI burst, '4' is 256 bytes
15721
 TX_DMA_BURSTTX_DMA_BURST 4 via-rhine.c 　
15722
 TX_TIMEOUTTX_TIMEOUT ((2000*HZ)/1000) via-rhine.c 　
15723
 byPAR0byPAR0 ioaddr via-rhine.c 　
15724
 byRCRbyRCR ioaddr + 6 via-rhine.c 　
15725
 byTCRbyTCR ioaddr + 7 via-rhine.c 　
15726
 byCR0byCR0 ioaddr + 8 via-rhine.c 　
15727
 byCR1byCR1 ioaddr + 9 via-rhine.c 　
15728
 byISR0byISR0 ioaddr + 0x0c via-rhine.c 　
15729
 byISR1byISR1 ioaddr + 0x0d via-rhine.c 　
15730
 byIMR0byIMR0 ioaddr + 0x0e via-rhine.c 　
15731
 byIMR1byIMR1 ioaddr + 0x0f via-rhine.c 　
15732
 byMAR0byMAR0 ioaddr + 0x10 via-rhine.c 　
15733
 byMAR1byMAR1 ioaddr + 0x11 via-rhine.c 　
15734
 byMAR2byMAR2 ioaddr + 0x12 via-rhine.c 　
15735
 byMAR3byMAR3 ioaddr + 0x13 via-rhine.c 　
15736
 byMAR4byMAR4 ioaddr + 0x14 via-rhine.c 　
15737
 byMAR5byMAR5 ioaddr + 0x15 via-rhine.c 　
15738
 byMAR6byMAR6 ioaddr + 0x16 via-rhine.c 　
15739
 byMAR7byMAR7 ioaddr + 0x17 via-rhine.c 　
15740
 dwCurrentRxDescAddrdwCurrentRxDescAddr ioaddr + 0x18 via-rhine.c 　
15741
 dwCurrentTxDescAddrdwCurrentTxDescAddr ioaddr + 0x1c via-rhine.c 　
15742
 dwCurrentRDSE0dwCurrentRDSE0 ioaddr + 0x20 via-rhine.c 　
15743
 dwCurrentRDSE1dwCurrentRDSE1 ioaddr + 0x24 via-rhine.c 　
15744
 dwCurrentRDSE2dwCurrentRDSE2 ioaddr + 0x28 via-rhine.c 　
15745
 dwCurrentRDSE3dwCurrentRDSE3 ioaddr + 0x2c via-rhine.c 　
15746
 dwNextRDSE0dwNextRDSE0 ioaddr + 0x30 via-rhine.c 　
15747
 dwNextRDSE1dwNextRDSE1 ioaddr + 0x34 via-rhine.c 　
15748
 dwNextRDSE2dwNextRDSE2 ioaddr + 0x38 via-rhine.c 　
15749
 dwNextRDSE3dwNextRDSE3 ioaddr + 0x3c via-rhine.c 　
15750
 dwCurrentTDSE0dwCurrentTDSE0 ioaddr + 0x40 via-rhine.c 　
15751
 dwCurrentTDSE1dwCurrentTDSE1 ioaddr + 0x44 via-rhine.c 　
15752
 dwCurrentTDSE2dwCurrentTDSE2 ioaddr + 0x48 via-rhine.c 　
15753
 dwCurrentTDSE3dwCurrentTDSE3 ioaddr + 0x4c via-rhine.c 　
15754
 dwNextTDSE0dwNextTDSE0 ioaddr + 0x50 via-rhine.c 　
15755
 dwNextTDSE1dwNextTDSE1 ioaddr + 0x54 via-rhine.c 　
15756
 dwNextTDSE2dwNextTDSE2 ioaddr + 0x58 via-rhine.c 　
15757
 dwNextTDSE3dwNextTDSE3 ioaddr + 0x5c via-rhine.c 　
15758
 dwCurrRxDMAPtrdwCurrRxDMAPtr ioaddr + 0x60 via-rhine.c 　
15759
 dwCurrTxDMAPtrdwCurrTxDMAPtr ioaddr + 0x64 via-rhine.c 　
15760
 byMPHYbyMPHY ioaddr + 0x6c via-rhine.c 　
15761
 byMIISRbyMIISR ioaddr + 0x6d via-rhine.c 　
15762
 byBCR0byBCR0 ioaddr + 0x6e via-rhine.c 　
15763
 byBCR1byBCR1 ioaddr + 0x6f via-rhine.c 　
15764
 byMIICRbyMIICR ioaddr + 0x70 via-rhine.c 　
15765
 byMIIADbyMIIAD ioaddr + 0x71 via-rhine.c 　
15766
 wMIIDATAwMIIDATA ioaddr + 0x72 via-rhine.c 　
15767
 byEECSRbyEECSR ioaddr + 0x74 via-rhine.c 　
15768
 byTESTbyTEST ioaddr + 0x75 via-rhine.c 　
15769
 byGPIObyGPIO ioaddr + 0x76 via-rhine.c 　
15770
 byCFGAbyCFGA ioaddr + 0x78 via-rhine.c 　
15771
 byCFGBbyCFGB ioaddr + 0x79 via-rhine.c 　
15772
 byCFGCbyCFGC ioaddr + 0x7a via-rhine.c 　
15773
 byCFGDbyCFGD ioaddr + 0x7b via-rhine.c 　
15774
 wTallyCntMPAwTallyCntMPA ioaddr + 0x7c via-rhine.c 　
15775
 wTallyCntCRCwTallyCntCRC ioaddr + 0x7d via-rhine.c 　
15776
 bySTICKHWbySTICKHW ioaddr + 0x83 via-rhine.c 　
15777
 byWOLcrClrbyWOLcrClr ioaddr + 0xA4 via-rhine.c 　
15778
 byWOLcgClrbyWOLcgClr ioaddr + 0xA7 via-rhine.c 　
15779
 byPwrcsrClrbyPwrcsrClr ioaddr + 0xAC via-rhine.c 　
15780
 RCR_RRFT2RCR_RRFT2 0x80 via-rhine.c 　
15781
 RCR_RRFT1RCR_RRFT1 0x40 via-rhine.c 　
15782
 RCR_RRFT0RCR_RRFT0 0x20 via-rhine.c 　
15783
 RCR_PROMRCR_PROM 0x10 via-rhine.c 　
15784
 RCR_ABRCR_AB 0x08 via-rhine.c 　
15785
 RCR_AMRCR_AM 0x04 via-rhine.c 　
15786
 RCR_ARRCR_AR 0x02 via-rhine.c 　
15787
 RCR_SEPRCR_SEP 0x01 via-rhine.c 　
15788
 TCR_RTSFTCR_RTSF 0x80 via-rhine.c 　
15789
 TCR_RTFT1TCR_RTFT1 0x40 via-rhine.c 　
15790
 TCR_RTFT0TCR_RTFT0 0x20 via-rhine.c 　
15791
 TCR_OFSETTCR_OFSET 0x08 via-rhine.c 　
15792
 TCR_LB1TCR_LB1 0x04 via-rhine.c loopback[1]
15793
 TCR_LB0TCR_LB0 0x02 via-rhine.c loopback[0]
15794
 CR0_RDMDCR0_RDMD 0x40 via-rhine.c rx descriptor polling demand
15795
 CR0_TDMDCR0_TDMD 0x20 via-rhine.c tx descriptor polling demand
15796
 CR0_TXONCR0_TXON 0x10 via-rhine.c 　
15797
 CR0_RXONCR0_RXON 0x08 via-rhine.c 　
15798
 CR0_STOPCR0_STOP 0x04 via-rhine.c stop NIC, default = 1
15799
 CR0_STRTCR0_STRT 0x02 via-rhine.c start NIC
15800
 CR0_INITCR0_INIT 0x01 via-rhine.c start init process
15801
 CR1_SFRSTCR1_SFRST 0x80 via-rhine.c software reset
15802
 CR1_RDMD1CR1_RDMD1 0x40 via-rhine.c RDMD1
15803
 CR1_TDMD1CR1_TDMD1 0x20 via-rhine.c TDMD1
15804
 CR1_KEYPAGCR1_KEYPAG 0x10 via-rhine.c turn on par/key
15805
 CR1_DPOLLCR1_DPOLL 0x08 via-rhine.c disable rx/tx auto polling
15806
 CR1_FDXCR1_FDX 0x04 via-rhine.c full duplex mode
15807
 CR1_ETENCR1_ETEN 0x02 via-rhine.c early tx mode
15808
 CR1_ERENCR1_EREN 0x01 via-rhine.c early rx mode
15809
 CR_RDMDCR_RDMD 0x0040 via-rhine.c rx descriptor polling demand
15810
 CR_TDMDCR_TDMD 0x0020 via-rhine.c tx descriptor polling demand
15811
 CR_TXONCR_TXON 0x0010 via-rhine.c 　
15812
 CR_RXONCR_RXON 0x0008 via-rhine.c 　
15813
 CR_STOPCR_STOP 0x0004 via-rhine.c stop NIC, default = 1
15814
 CR_STRTCR_STRT 0x0002 via-rhine.c start NIC
15815
 CR_INITCR_INIT 0x0001 via-rhine.c start init process
15816
 CR_SFRSTCR_SFRST 0x8000 via-rhine.c software reset
15817
 CR_RDMD1CR_RDMD1 0x4000 via-rhine.c RDMD1
15818
 CR_TDMD1CR_TDMD1 0x2000 via-rhine.c TDMD1
15819
 CR_KEYPAGCR_KEYPAG 0x1000 via-rhine.c turn on par/key
15820
 CR_DPOLLCR_DPOLL 0x0800 via-rhine.c disable rx/tx auto polling
15821
 CR_FDXCR_FDX 0x0400 via-rhine.c full duplex mode
15822
 CR_ETENCR_ETEN 0x0200 via-rhine.c early tx mode
15823
 CR_ERENCR_EREN 0x0100 via-rhine.c early rx mode
15824
 IMR0_CNTMIMR0_CNTM 0x80 via-rhine.c 　
15825
 IMR0_BEMIMR0_BEM 0x40 via-rhine.c 　
15826
 IMR0_RUMIMR0_RUM 0x20 via-rhine.c 　
15827
 IMR0_TUMIMR0_TUM 0x10 via-rhine.c 　
15828
 IMR0_TXEMIMR0_TXEM 0x08 via-rhine.c 　
15829
 IMR0_RXEMIMR0_RXEM 0x04 via-rhine.c 　
15830
 IMR0_PTXMIMR0_PTXM 0x02 via-rhine.c 　
15831
 IMR0_PRXMIMR0_PRXM 0x01 via-rhine.c 　
15832
 IMRShadowIMRShadow 0x5AFF via-rhine.c 　
15833
 IMR1_INITMIMR1_INITM 0x80 via-rhine.c 　
15834
 IMR1_SRCMIMR1_SRCM 0x40 via-rhine.c 　
15835
 IMR1_NBFMIMR1_NBFM 0x10 via-rhine.c 　
15836
 IMR1_PRAIMIMR1_PRAIM 0x08 via-rhine.c 　
15837
 IMR1_RES0MIMR1_RES0M 0x04 via-rhine.c 　
15838
 IMR1_ETMIMR1_ETM 0x02 via-rhine.c 　
15839
 IMR1_ERMIMR1_ERM 0x01 via-rhine.c 　
15840
 ISR_INITIISR_INITI 0x8000 via-rhine.c 　
15841
 ISR_SRCIISR_SRCI 0x4000 via-rhine.c 　
15842
 ISR_ABTIISR_ABTI 0x2000 via-rhine.c 　
15843
 ISR_NORBFISR_NORBF 0x1000 via-rhine.c 　
15844
 ISR_PKTRAISR_PKTRA 0x0800 via-rhine.c 　
15845
 ISR_RES0ISR_RES0 0x0400 via-rhine.c 　
15846
 ISR_ETIISR_ETI 0x0200 via-rhine.c 　
15847
 ISR_ERIISR_ERI 0x0100 via-rhine.c 　
15848
 ISR_CNTISR_CNT 0x0080 via-rhine.c 　
15849
 ISR_BEISR_BE 0x0040 via-rhine.c 　
15850
 ISR_RUISR_RU 0x0020 via-rhine.c 　
15851
 ISR_TUISR_TU 0x0010 via-rhine.c 　
15852
 ISR_TXEISR_TXE 0x0008 via-rhine.c 　
15853
 ISR_RXEISR_RXE 0x0004 via-rhine.c 　
15854
 ISR_PTXISR_PTX 0x0002 via-rhine.c 　
15855
 ISR_PRXISR_PRX 0x0001 via-rhine.c 　
15856
 ISR0_CNTISR0_CNT 0x80 via-rhine.c 　
15857
 ISR0_BEISR0_BE 0x40 via-rhine.c 　
15858
 ISR0_RUISR0_RU 0x20 via-rhine.c 　
15859
 ISR0_TUISR0_TU 0x10 via-rhine.c 　
15860
 ISR0_TXEISR0_TXE 0x08 via-rhine.c 　
15861
 ISR0_RXEISR0_RXE 0x04 via-rhine.c 　
15862
 ISR0_PTXISR0_PTX 0x02 via-rhine.c 　
15863
 ISR0_PRXISR0_PRX 0x01 via-rhine.c 　
15864
 ISR1_INITIISR1_INITI 0x80 via-rhine.c 　
15865
 ISR1_SRCIISR1_SRCI 0x40 via-rhine.c 　
15866
 ISR1_NORBFISR1_NORBF 0x10 via-rhine.c 　
15867
 ISR1_PKTRAISR1_PKTRA 0x08 via-rhine.c 　
15868
 ISR1_ETIISR1_ETI 0x02 via-rhine.c 　
15869
 ISR1_ERIISR1_ERI 0x01 via-rhine.c 　
15870
 ISR_ABNORMALISR_ABNORMAL ISR_BE+ISR_RU+ISR_TU+ISR_CNT+ISR_NORBF+ISR_PKTRA via-rhine.c 　
15871
 MIISR_MIIERRMIISR_MIIERR 0x08 via-rhine.c 　
15872
 MIISR_MRERRMIISR_MRERR 0x04 via-rhine.c 　
15873
 MIISR_LNKFLMIISR_LNKFL 0x02 via-rhine.c 　
15874
 MIISR_SPEEDMIISR_SPEED 0x01 via-rhine.c 　
15875
 MIICR_MAUTOMIICR_MAUTO 0x80 via-rhine.c 　
15876
 MIICR_RCMDMIICR_RCMD 0x40 via-rhine.c 　
15877
 MIICR_WCMDMIICR_WCMD 0x20 via-rhine.c 　
15878
 MIICR_MDPMMIICR_MDPM 0x10 via-rhine.c 　
15879
 MIICR_MOUTMIICR_MOUT 0x08 via-rhine.c 　
15880
 MIICR_MDOMIICR_MDO 0x04 via-rhine.c 　
15881
 MIICR_MDIMIICR_MDI 0x02 via-rhine.c 　
15882
 MIICR_MDCMIICR_MDC 0x01 via-rhine.c 　
15883
 EECSR_EEPREECSR_EEPR 0x80 via-rhine.c eeprom programed status, 73h means programed
15884
 EECSR_EMBPEECSR_EMBP 0x40 via-rhine.c eeprom embeded programming
15885
 EECSR_AUTOLDEECSR_AUTOLD 0x20 via-rhine.c eeprom content reload
15886
 EECSR_DPMEECSR_DPM 0x10 via-rhine.c eeprom direct programming
15887
 EECSR_CSEECSR_CS 0x08 via-rhine.c eeprom CS pin
15888
 EECSR_SKEECSR_SK 0x04 via-rhine.c eeprom SK pin
15889
 EECSR_DIEECSR_DI 0x02 via-rhine.c eeprom DI pin
15890
 EECSR_DOEECSR_DO 0x01 via-rhine.c eeprom DO pin
15891
 BCR0_CRFT2BCR0_CRFT2 0x20 via-rhine.c 　
15892
 BCR0_CRFT1BCR0_CRFT1 0x10 via-rhine.c 　
15893
 BCR0_CRFT0BCR0_CRFT0 0x08 via-rhine.c 　
15894
 BCR0_DMAL2BCR0_DMAL2 0x04 via-rhine.c 　
15895
 BCR0_DMAL1BCR0_DMAL1 0x02 via-rhine.c 　
15896
 BCR0_DMAL0BCR0_DMAL0 0x01 via-rhine.c 　
15897
 BCR1_CTSFBCR1_CTSF 0x20 via-rhine.c 　
15898
 BCR1_CTFT1BCR1_CTFT1 0x10 via-rhine.c 　
15899
 BCR1_CTFT0BCR1_CTFT0 0x08 via-rhine.c 　
15900
 BCR1_POT2BCR1_POT2 0x04 via-rhine.c 　
15901
 BCR1_POT1BCR1_POT1 0x02 via-rhine.c 　
15902
 BCR1_POT0BCR1_POT0 0x01 via-rhine.c 　
15903
 CFGA_EELOADCFGA_EELOAD 0x80 via-rhine.c enable eeprom embeded and direct programming
15904
 CFGA_JUMPERCFGA_JUMPER 0x40 via-rhine.c 　
15905
 CFGA_MTGPIOCFGA_MTGPIO 0x08 via-rhine.c 　
15906
 CFGA_T10ENCFGA_T10EN 0x02 via-rhine.c 　
15907
 CFGA_AUTOCFGA_AUTO 0x01 via-rhine.c 　
15908
 CFGB_PDCFGB_PD 0x80 via-rhine.c 　
15909
 CFGB_POLENCFGB_POLEN 0x02 via-rhine.c 　
15910
 CFGB_LNKENCFGB_LNKEN 0x01 via-rhine.c 　
15911
 CFGC_M10TIOCFGC_M10TIO 0x80 via-rhine.c 　
15912
 CFGC_M10POLCFGC_M10POL 0x40 via-rhine.c 　
15913
 CFGC_PHY1CFGC_PHY1 0x20 via-rhine.c 　
15914
 CFGC_PHY0CFGC_PHY0 0x10 via-rhine.c 　
15915
 CFGC_BTSELCFGC_BTSEL 0x08 via-rhine.c 　
15916
 CFGC_BPS2CFGC_BPS2 0x04 via-rhine.c bootrom select[2]
15917
 CFGC_BPS1CFGC_BPS1 0x02 via-rhine.c bootrom select[1]
15918
 CFGC_BPS0CFGC_BPS0 0x01 via-rhine.c bootrom select[0]
15919
 CFGD_GPIOENCFGD_GPIOEN 0x80 via-rhine.c 　
15920
 CFGD_DIAGCFGD_DIAG 0x40 via-rhine.c 　
15921
 CFGD_MAGICCFGD_MAGIC 0x10 via-rhine.c 　
15922
 CFGD_RANDOMCFGD_RANDOM 0x08 via-rhine.c 　
15923
 CFGD_CFDXCFGD_CFDX 0x04 via-rhine.c 　
15924
 CFGD_CERENCFGD_CEREN 0x02 via-rhine.c 　
15925
 CFGD_CETENCFGD_CETEN 0x01 via-rhine.c 　
15926
 RSR_RERRRSR_RERR 0x00000001 via-rhine.c 　
15927
 RSR_CRCRSR_CRC 0x00000002 via-rhine.c 　
15928
 RSR_FAERSR_FAE 0x00000004 via-rhine.c 　
15929
 RSR_FOVRSR_FOV 0x00000008 via-rhine.c 　
15930
 RSR_LONGRSR_LONG 0x00000010 via-rhine.c 　
15931
 RSR_RUNTRSR_RUNT 0x00000020 via-rhine.c 　
15932
 RSR_SERRRSR_SERR 0x00000040 via-rhine.c 　
15933
 RSR_BUFFRSR_BUFF 0x00000080 via-rhine.c 　
15934
 RSR_EDPRSR_EDP 0x00000100 via-rhine.c 　
15935
 RSR_STPRSR_STP 0x00000200 via-rhine.c 　
15936
 RSR_CHNRSR_CHN 0x00000400 via-rhine.c 　
15937
 RSR_PHYRSR_PHY 0x00000800 via-rhine.c 　
15938
 RSR_BARRSR_BAR 0x00001000 via-rhine.c 　
15939
 RSR_MARRSR_MAR 0x00002000 via-rhine.c 　
15940
 RSR_RXOKRSR_RXOK 0x00008000 via-rhine.c 　
15941
 RSR_ABNORMALRSR_ABNORMAL RSR_RERR+RSR_LONG+RSR_RUNT via-rhine.c 　
15942
 TSR_NCR0TSR_NCR0 0x00000001 via-rhine.c 　
15943
 TSR_NCR1TSR_NCR1 0x00000002 via-rhine.c 　
15944
 TSR_NCR2TSR_NCR2 0x00000004 via-rhine.c 　
15945
 TSR_NCR3TSR_NCR3 0x00000008 via-rhine.c 　
15946
 TSR_COLSTSR_COLS 0x00000010 via-rhine.c 　
15947
 TSR_CDHTSR_CDH 0x00000080 via-rhine.c 　
15948
 TSR_ABTTSR_ABT 0x00000100 via-rhine.c 　
15949
 TSR_OWCTSR_OWC 0x00000200 via-rhine.c 　
15950
 TSR_CRSTSR_CRS 0x00000400 via-rhine.c 　
15951
 TSR_UDFTSR_UDF 0x00000800 via-rhine.c 　
15952
 TSR_TBUFFTSR_TBUFF 0x00001000 via-rhine.c 　
15953
 TSR_SERRTSR_SERR 0x00002000 via-rhine.c 　
15954
 TSR_JABTSR_JAB 0x00004000 via-rhine.c 　
15955
 TSR_TERRTSR_TERR 0x00008000 via-rhine.c 　
15956
 TSR_ABNORMALTSR_ABNORMAL TSR_TERR+TSR_OWC+TSR_ABT+TSR_JAB+TSR_CRS via-rhine.c 　
15957
 TSR_OWN_BITTSR_OWN_BIT 0x80000000 via-rhine.c 　
15958
 CB_DELAY_LOOP_WAITCB_DELAY_LOOP_WAIT 10 via-rhine.c 10ms
15959
 W_IMR_MASK_VALUEW_IMR_MASK_VALUE 0x1BFF via-rhine.c initial value of IMR
15960
 PKT_TYPE_DIRECTEDPKT_TYPE_DIRECTED 0x0001 via-rhine.c obsolete, directed address is always accepted
15961
 PKT_TYPE_MULTICASTPKT_TYPE_MULTICAST 0x0002 via-rhine.c 　
15962
 PKT_TYPE_ALL_MULTICASTPKT_TYPE_ALL_MULTICAST 0x0004 via-rhine.c 　
15963
 PKT_TYPE_BROADCASTPKT_TYPE_BROADCAST 0x0008 via-rhine.c 　
15964
 PKT_TYPE_PROMISCUOUSPKT_TYPE_PROMISCUOUS 0x0020 via-rhine.c 　
15965
 PKT_TYPE_LONGPKT_TYPE_LONG 0x2000 via-rhine.c 　
15966
 PKT_TYPE_RUNTPKT_TYPE_RUNT 0x4000 via-rhine.c 　
15967
 PKT_TYPE_ERRORPKT_TYPE_ERROR 0x8000 via-rhine.c accept error packets, e.g. CRC error
15968
 NIC_LB_NONENIC_LB_NONE 0x00 via-rhine.c 　
15969
 NIC_LB_INTERNALNIC_LB_INTERNAL 0x01 via-rhine.c 　
15970
 NIC_LB_PHYNIC_LB_PHY 0x02 via-rhine.c MII or Internal-10BaseT loopback
15971
 TX_RING_SIZETX_RING_SIZE 2 via-rhine.c 　
15972
 RX_RING_SIZERX_RING_SIZE 2 via-rhine.c 　
15973
 PKT_BUF_SZPKT_BUF_SZ 1536 via-rhine.c Size of each temporary Rx buffer.
15974
 PCI_REG_MODE3PCI_REG_MODE3 0x53 via-rhine.c 　
15975
 MODE3_MIIONMODE3_MIION 0x04 via-rhine.c in PCI_REG_MOD3 OF PCI space
15976
 rhine_TOTAL_SIZErhine_TOTAL_SIZE 0x80 via-rhine.c 　
15977
 NUM_TX_DESCNUM_TX_DESC 2 via-rhine.c Number of Tx descriptor registers.
15978
 DEFAULT_INTRDEFAULT_INTR (IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow | \ IntrRxDropped | IntrRxNoBuf) via-rhine.c 　
15979
 IOSYNCIOSYNC do { inb(nic->ioaddr + StationAddr); } while (0) via-rhine.c 　
15980
 PCI_D0PCI_D0 ((int) 0) via-velocity.c 　
15981
 PCI_D1PCI_D1 ((int) 1) via-velocity.c 　
15982
 PCI_D2PCI_D2 ((int) 2) via-velocity.c 　
15983
 PCI_D3hotPCI_D3hot ((int) 3) via-velocity.c 　
15984
 PCI_D3coldPCI_D3cold ((int) 4) via-velocity.c 　
15985
 PCI_POWER_ERRORPCI_POWER_ERROR ((int) -1) via-velocity.c 　
15986
 VLAN_ID_MINVLAN_ID_MIN 0 via-velocity.c 　
15987
 VLAN_ID_MAXVLAN_ID_MAX 4095 via-velocity.c 　
15988
 VLAN_ID_DEFVLAN_ID_DEF 0 via-velocity.c 　
15989
 RX_THRESH_MINRX_THRESH_MIN 0 via-velocity.c 　
15990
 RX_THRESH_MAXRX_THRESH_MAX 3 via-velocity.c 　
15991
 RX_THRESH_DEFRX_THRESH_DEF 0 via-velocity.c 　
15992
 DMA_LENGTH_MINDMA_LENGTH_MIN 0 via-velocity.c 　
15993
 DMA_LENGTH_MAXDMA_LENGTH_MAX 7 via-velocity.c 　
15994
 DMA_LENGTH_DEFDMA_LENGTH_DEF 0 via-velocity.c 　
15995
 TAGGING_DEFTAGGING_DEF 0 via-velocity.c 　
15996
 IP_ALIG_DEFIP_ALIG_DEF 0 via-velocity.c 　
15997
 TX_CSUM_DEFTX_CSUM_DEF 1 via-velocity.c 　
15998
 FLOW_CNTL_DEFFLOW_CNTL_DEF 1 via-velocity.c 　
15999
 FLOW_CNTL_MINFLOW_CNTL_MIN 1 via-velocity.c 　
16000
 FLOW_CNTL_MAXFLOW_CNTL_MAX 5 via-velocity.c 　
16001
 MED_LNK_DEFMED_LNK_DEF 0 via-velocity.c 　
16002
 MED_LNK_MINMED_LNK_MIN 0 via-velocity.c 　
16003
 MED_LNK_MAXMED_LNK_MAX 4 via-velocity.c 　
16004
 VAL_PKT_LEN_DEFVAL_PKT_LEN_DEF 0 via-velocity.c 　
16005
 WOL_OPT_DEFWOL_OPT_DEF 0 via-velocity.c 　
16006
 WOL_OPT_MINWOL_OPT_MIN 0 via-velocity.c 　
16007
 WOL_OPT_MAXWOL_OPT_MAX 7 via-velocity.c 　
16008
 INT_WORKS_DEFINT_WORKS_DEF 20 via-velocity.c 　
16009
 INT_WORKS_MININT_WORKS_MIN 10 via-velocity.c 　
16010
 INT_WORKS_MAXINT_WORKS_MAX 64 via-velocity.c 　
16011
 TX_TIMEOUTTX_TIMEOUT (1000); via-velocity.c 　
16012
 IORESOURCE_IOIORESOURCE_IO 0x00000100 via-velocity.c Resource type
16013
 IORESOURCE_PREFETCHIORESOURCE_PREFETCH 0x00001000 via-velocity.c No side effects
16014
 IORESOURCE_MEMIORESOURCE_MEM 0x00000200 via-velocity.c 　
16015
 BAR_0BAR_0 0 via-velocity.c 　
16016
 BAR_1BAR_1 1 via-velocity.c 　
16017
 BAR_5BAR_5 5 via-velocity.c 　
16018
 PCI_BASE_ADDRESS_SPACEPCI_BASE_ADDRESS_SPACE 0x01 via-velocity.c 0 = memory, 1 = I/O
16019
 PCI_BASE_ADDRESS_SPACE_IOPCI_BASE_ADDRESS_SPACE_IO 0x01 via-velocity.c 　
16020
 PCI_BASE_ADDRESS_SPACE_MEMORYPCI_BASE_ADDRESS_SPACE_MEMORY 0x00 via-velocity.c 　
16021
 PCI_BASE_ADDRESS_MEM_TYPE_MASKPCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 via-velocity.c 　
16022
 PCI_BASE_ADDRESS_MEM_TYPE_32PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 via-velocity.c 32 bit address
16023
 PCI_BASE_ADDRESS_MEM_TYPE_1MPCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 via-velocity.c Below 1M [obsolete]
16024
 PCI_BASE_ADDRESS_MEM_TYPE_64PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 via-velocity.c 64 bit address
16025
 PCI_BASE_ADDRESS_MEM_PREFETCHPCI_BASE_ADDRESS_MEM_PREFETCH 0x08 via-velocity.c prefetchable?
16026
 PCI_REG_COMMANDPCI_REG_COMMAND 0x04 via-velocity.c 　
16027
 PCI_REG_MODE0PCI_REG_MODE0 0x60 via-velocity.c 　
16028
 PCI_REG_MODE1PCI_REG_MODE1 0x61 via-velocity.c 　
16029
 PCI_REG_MODE2PCI_REG_MODE2 0x62 via-velocity.c 　
16030
 PCI_REG_MODE3PCI_REG_MODE3 0x63 via-velocity.c 　
16031
 PCI_REG_DELAY_TIMERPCI_REG_DELAY_TIMER 0x64 via-velocity.c 　
16032
 MODE2_PCEROPTMODE2_PCEROPT 0x80 via-velocity.c take PCI bus ERror as a fatal and shutdown from software control
16033
 MODE2_TXQ16MODE2_TXQ16 0x40 via-velocity.c TX write-back Queue control. 0->32 entries available in Tx write-back queue, 1->16 entries
16034
 MODE2_TXPOSTMODE2_TXPOST 0x08 via-velocity.c (Not support in VT3119)
16035
 MODE2_AUTOOPTMODE2_AUTOOPT 0x04 via-velocity.c (VT3119 GHCI without such behavior)
16036
 MODE2_MODE10TMODE2_MODE10T 0x02 via-velocity.c used to control tx Threshold for 10M case
16037
 MODE2_TCPLSOPTMODE2_TCPLSOPT 0x01 via-velocity.c TCP large send field update disable, hardware will not update related fields, leave it to software.
16038
 MODE3_MIIONMODE3_MIION 0x04 via-velocity.c MII symbol codine error detect enable ??
16039
 COMMAND_BUSMCOMMAND_BUSM 0x04 via-velocity.c 　
16040
 COMMAND_WAITCOMMAND_WAIT 0x80 via-velocity.c 　
16041
 RX_BUF_NBRX_BUF_NB 6 virtio-net.c 　
16042
 TX_RING_SIZETX_RING_SIZE 2 w89c840.c 　
16043
 RX_RING_SIZERX_RING_SIZE 2 w89c840.c 　
16044
 TX_FIFO_SIZETX_FIFO_SIZE (2048) w89c840.c 　
16045
 TX_BUG_FIFO_LIMITTX_BUG_FIFO_LIMIT (TX_FIFO_SIZE-1514-16) w89c840.c 　
16046
 TX_TIMEOUTTX_TIMEOUT (10*1000) w89c840.c 　
16047
 PKT_BUF_SZPKT_BUF_SZ 1536 w89c840.c Size of each temporary Rx buffer.
16048
 W840_FLAGSW840_FLAGS (PCI_USES_IO | PCI_ADDR0 | PCI_USES_MASTER) w89c840.c 　
16049
 W840_FLAGSW840_FLAGS (PCI_USES_MEM | PCI_ADDR1 | PCI_USES_MASTER) w89c840.c 　
16050
 readbreadb inb w89c840.c 　
16051
 readwreadw inw w89c840.c 　
16052
 readlreadl inl w89c840.c 　
16053
 writebwriteb outb w89c840.c 　
16054
 writewwritew outw w89c840.c 　
16055
 writelwritel outl w89c840.c 　
16056
 PRIV_ALIGNPRIV_ALIGN 15 w89c840.c Required alignment mask
16057
 PRIV_ALIGN_BYTESPRIV_ALIGN_BYTES 32 w89c840.c 　
16058
 MDIO_WRITE0MDIO_WRITE0 (MDIO_EnbOutput) w89c840.c 　
16059
 MDIO_WRITE1MDIO_WRITE1 (MDIO_DataOut | MDIO_EnbOutput) w89c840.c 　
16060
 WD_DEFAULT_MEMWD_DEFAULT_MEM 0xCC000 wd.c 　
16061
 TX_INIT_RATETX_INIT_RATE 16 3c509.h 　
16062
 TX_INIT_MAX_RATETX_INIT_MAX_RATE 64 3c509.h 　
16063
 RX_INIT_LATENCYRX_INIT_LATENCY 64 3c509.h 　
16064
 RX_INIT_EARLY_THRESHRX_INIT_EARLY_THRESH 64 3c509.h 　
16065
 MIN_RX_EARLY_THRESHFMIN_RX_EARLY_THRESHF 16 3c509.h not less than ether_header
16066
 MIN_RX_EARLY_THRESHLMIN_RX_EARLY_THRESHL 4 3c509.h 　
16067
 EEPROMSIZEEEPROMSIZE 0x40 3c509.h 　
16068
 MAX_EEPROMBUSYMAX_EEPROMBUSY 1000 3c509.h 　
16069
 EP_ID_PORT_STARTEP_ID_PORT_START 0x110 3c509.h avoid 0x100 to avoid conflict with SB16
16070
 EP_ID_PORT_INCEP_ID_PORT_INC 0x10 3c509.h 　
16071
 EP_ID_PORT_ENDEP_ID_PORT_END 0x200 3c509.h 　
16072
 EP_TAG_MAXEP_TAG_MAX 0x7 3c509.h must be 2^n - 1
16073
 EEPROM_CMD_RDEEPROM_CMD_RD 0x0080 3c509.h Read: Address required (5 bits)
16074
 EEPROM_CMD_WREEPROM_CMD_WR 0x0040 3c509.h Write: Address required (5 bits)
16075
 EEPROM_CMD_ERASEEEPROM_CMD_ERASE 0x00c0 3c509.h Erase: Address required (5 bits)
16076
 EEPROM_CMD_EWENEEPROM_CMD_EWEN 0x0030 3c509.h Erase/Write Enable: No data required
16077
 EEPROM_BUSYEEPROM_BUSY (1<<15) 3c509.h 　
16078
 EEPROM_TST_MODEEEPROM_TST_MODE (1<<14) 3c509.h 　
16079
 EEPROM_NODE_ADDR_0EEPROM_NODE_ADDR_0 0x0 3c509.h Word
16080
 EEPROM_NODE_ADDR_1EEPROM_NODE_ADDR_1 0x1 3c509.h Word
16081
 EEPROM_NODE_ADDR_2EEPROM_NODE_ADDR_2 0x2 3c509.h Word
16082
 EEPROM_PROD_IDEEPROM_PROD_ID 0x3 3c509.h 0x9[0-f]50
16083
 EEPROM_MFG_IDEEPROM_MFG_ID 0x7 3c509.h 0x6d50
16084
 EEPROM_ADDR_CFGEEPROM_ADDR_CFG 0x8 3c509.h Base addr
16085
 EEPROM_RESOURCE_CFGEEPROM_RESOURCE_CFG 0x9 3c509.h IRQ. Bits 12-15
16086
 EP_COMMANDEP_COMMAND 0x0e 3c509.h Write. BASE+0x0e is always a
16087
 EP_STATUSEP_STATUS 0x0e 3c509.h Read. BASE+0x0e is always status
16088
 EP_WINDOWEP_WINDOW 0x0f 3c509.h Read. BASE+0x0f is always window
16089
 EP_W0_EEPROM_DATAEP_W0_EEPROM_DATA 0x0c 3c509.h 　
16090
 EP_W0_EEPROM_COMMANDEP_W0_EEPROM_COMMAND 0x0a 3c509.h 　
16091
 EP_W0_RESOURCE_CFGEP_W0_RESOURCE_CFG 0x08 3c509.h 　
16092
 EP_W0_ADDRESS_CFGEP_W0_ADDRESS_CFG 0x06 3c509.h 　
16093
 EP_W0_CONFIG_CTRLEP_W0_CONFIG_CTRL 0x04 3c509.h 　
16094
 EP_W0_PRODUCT_IDEP_W0_PRODUCT_ID 0x02 3c509.h 　
16095
 EP_W0_MFG_IDEP_W0_MFG_ID 0x00 3c509.h 　
16096
 EP_W1_TX_PIO_WR_2EP_W1_TX_PIO_WR_2 0x02 3c509.h 　
16097
 EP_W1_TX_PIO_WR_1EP_W1_TX_PIO_WR_1 0x00 3c509.h 　
16098
 EP_W1_FREE_TXEP_W1_FREE_TX 0x0c 3c509.h 　
16099
 EP_W1_TX_STATUSEP_W1_TX_STATUS 0x0b 3c509.h byte
16100
 EP_W1_TIMEREP_W1_TIMER 0x0a 3c509.h byte
16101
 EP_W1_RX_STATUSEP_W1_RX_STATUS 0x08 3c509.h 　
16102
 EP_W1_RX_PIO_RD_2EP_W1_RX_PIO_RD_2 0x02 3c509.h 　
16103
 EP_W1_RX_PIO_RD_1EP_W1_RX_PIO_RD_1 0x00 3c509.h 　
16104
 EP_W2_ADDR_5EP_W2_ADDR_5 0x05 3c509.h 　
16105
 EP_W2_ADDR_4EP_W2_ADDR_4 0x04 3c509.h 　
16106
 EP_W2_ADDR_3EP_W2_ADDR_3 0x03 3c509.h 　
16107
 EP_W2_ADDR_2EP_W2_ADDR_2 0x02 3c509.h 　
16108
 EP_W2_ADDR_1EP_W2_ADDR_1 0x01 3c509.h 　
16109
 EP_W2_ADDR_0EP_W2_ADDR_0 0x00 3c509.h 　
16110
 EP_W3_FREE_TXEP_W3_FREE_TX 0x0c 3c509.h 　
16111
 EP_W3_FREE_RXEP_W3_FREE_RX 0x0a 3c509.h 　
16112
 EP_W4_MEDIA_TYPEEP_W4_MEDIA_TYPE 0x0a 3c509.h 　
16113
 EP_W4_CTRLR_STATUSEP_W4_CTRLR_STATUS 0x08 3c509.h 　
16114
 EP_W4_NET_DIAGEP_W4_NET_DIAG 0x06 3c509.h 　
16115
 EP_W4_FIFO_DIAGEP_W4_FIFO_DIAG 0x04 3c509.h 　
16116
 EP_W4_HOST_DIAGEP_W4_HOST_DIAG 0x02 3c509.h 　
16117
 EP_W4_TX_DIAGEP_W4_TX_DIAG 0x00 3c509.h 　
16118
 EP_W5_READ_0_MASKEP_W5_READ_0_MASK 0x0c 3c509.h 　
16119
 EP_W5_INTR_MASKEP_W5_INTR_MASK 0x0a 3c509.h 　
16120
 EP_W5_RX_FILTEREP_W5_RX_FILTER 0x08 3c509.h 　
16121
 EP_W5_RX_EARLY_THRESHEP_W5_RX_EARLY_THRESH 0x06 3c509.h 　
16122
 EP_W5_TX_AVAIL_THRESHEP_W5_TX_AVAIL_THRESH 0x02 3c509.h 　
16123
 EP_W5_TX_START_THRESHEP_W5_TX_START_THRESH 0x00 3c509.h 　
16124
 TX_TOTAL_OKTX_TOTAL_OK 0x0c 3c509.h 　
16125
 RX_TOTAL_OKRX_TOTAL_OK 0x0a 3c509.h 　
16126
 TX_DEFERRALSTX_DEFERRALS 0x08 3c509.h 　
16127
 RX_FRAMES_OKRX_FRAMES_OK 0x07 3c509.h 　
16128
 TX_FRAMES_OKTX_FRAMES_OK 0x06 3c509.h 　
16129
 RX_OVERRUNSRX_OVERRUNS 0x05 3c509.h 　
16130
 TX_COLLISIONSTX_COLLISIONS 0x04 3c509.h 　
16131
 TX_AFTER_1_COLLISIONTX_AFTER_1_COLLISION 0x03 3c509.h 　
16132
 TX_AFTER_X_COLLISIONSTX_AFTER_X_COLLISIONS 0x02 3c509.h 　
16133
 TX_NO_SQETX_NO_SQE 0x01 3c509.h 　
16134
 TX_CD_LOSTTX_CD_LOST 0x00 3c509.h 　
16135
 GLOBAL_RESETGLOBAL_RESET (unsigned short) 0x0000 3c509.h Wait at least 1ms
16136
 WINDOW_SELECTWINDOW_SELECT (unsigned short) (0x1<<11) 3c509.h 　
16137
 START_TRANSCEIVERSTART_TRANSCEIVER (unsigned short) (0x2<<11) 3c509.h Read ADDR_CFG reg to
16138
 RX_DISABLERX_DISABLE (unsigned short) (0x3<<11) 3c509.h state disabled on
16139
 RX_ENABLERX_ENABLE (unsigned short) (0x4<<11) 3c509.h 　
16140
 RX_RESETRX_RESET (unsigned short) (0x5<<11) 3c509.h 　
16141
 RX_DISCARD_TOP_PACKRX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) 3c509.h 　
16142
 TX_ENABLETX_ENABLE (unsigned short) (0x9<<11) 3c509.h 　
16143
 TX_DISABLETX_DISABLE (unsigned short) (0xa<<11) 3c509.h 　
16144
 TX_RESETTX_RESET (unsigned short) (0xb<<11) 3c509.h 　
16145
 REQ_INTRREQ_INTR (unsigned short) (0xc<<11) 3c509.h 　
16146
 SET_INTR_MASKSET_INTR_MASK (unsigned short) (0xe<<11) 3c509.h 　
16147
 SET_RD_0_MASKSET_RD_0_MASK (unsigned short) (0xf<<11) 3c509.h 　
16148
 SET_RX_FILTERSET_RX_FILTER (unsigned short) (0x10<<11) 3c509.h 　
16149
 FIL_INDIVIDUALFIL_INDIVIDUAL (unsigned short) (0x1) 3c509.h 　
16150
 FIL_GROUPFIL_GROUP (unsigned short) (0x2) 3c509.h 　
16151
 FIL_BRDCSTFIL_BRDCST (unsigned short) (0x4) 3c509.h 　
16152
 FIL_ALLFIL_ALL (unsigned short) (0x8) 3c509.h 　
16153
 SET_RX_EARLY_THRESHSET_RX_EARLY_THRESH (unsigned short) (0x11<<11) 3c509.h 　
16154
 SET_TX_AVAIL_THRESHSET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) 3c509.h 　
16155
 SET_TX_START_THRESHSET_TX_START_THRESH (unsigned short) (0x13<<11) 3c509.h 　
16156
 STATS_ENABLESTATS_ENABLE (unsigned short) (0x15<<11) 3c509.h 　
16157
 STATS_DISABLESTATS_DISABLE (unsigned short) (0x16<<11) 3c509.h 　
16158
 STOP_TRANSCEIVERSTOP_TRANSCEIVER (unsigned short) (0x17<<11) 3c509.h 　
16159
 ACK_INTRACK_INTR (unsigned short) (0x6800) 3c509.h 　
16160
 C_INTR_LATCHC_INTR_LATCH (unsigned short) (ACK_INTR|0x1) 3c509.h 　
16161
 C_CARD_FAILUREC_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) 3c509.h 　
16162
 C_TX_COMPLETEC_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) 3c509.h 　
16163
 C_TX_AVAILC_TX_AVAIL (unsigned short) (ACK_INTR|0x8) 3c509.h 　
16164
 C_RX_COMPLETEC_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) 3c509.h 　
16165
 C_RX_EARLYC_RX_EARLY (unsigned short) (ACK_INTR|0x20) 3c509.h 　
16166
 C_INT_RQDC_INT_RQD (unsigned short) (ACK_INTR|0x40) 3c509.h 　
16167
 C_UPD_STATSC_UPD_STATS (unsigned short) (ACK_INTR|0x80) 3c509.h 　
16168
 S_INTR_LATCHS_INTR_LATCH (unsigned short) (0x1) 3c509.h 　
16169
 S_CARD_FAILURES_CARD_FAILURE (unsigned short) (0x2) 3c509.h 　
16170
 S_TX_COMPLETES_TX_COMPLETE (unsigned short) (0x4) 3c509.h 　
16171
 S_TX_AVAILS_TX_AVAIL (unsigned short) (0x8) 3c509.h 　
16172
 S_RX_COMPLETES_RX_COMPLETE (unsigned short) (0x10) 3c509.h 　
16173
 S_RX_EARLYS_RX_EARLY (unsigned short) (0x20) 3c509.h 　
16174
 S_INT_RQDS_INT_RQD (unsigned short) (0x40) 3c509.h 　
16175
 S_UPD_STATSS_UPD_STATS (unsigned short) (0x80) 3c509.h 　
16176
 S_5_INTSS_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\ S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY) 3c509.h 　
16177
 S_COMMAND_IN_PROGRESSS_COMMAND_IN_PROGRESS (unsigned short) (0x1000) 3c509.h 　
16178
 ERR_RX_INCOMPLETEERR_RX_INCOMPLETE (unsigned short) (0x1<<15) 3c509.h 　
16179
 ERR_RXERR_RX (unsigned short) (0x1<<14) 3c509.h 　
16180
 ERR_RX_OVERRUNERR_RX_OVERRUN (unsigned short) (0x8<<11) 3c509.h 　
16181
 ERR_RX_RUN_PKTERR_RX_RUN_PKT (unsigned short) (0xb<<11) 3c509.h 　
16182
 ERR_RX_ALIGNERR_RX_ALIGN (unsigned short) (0xc<<11) 3c509.h 　
16183
 ERR_RX_CRCERR_RX_CRC (unsigned short) (0xd<<11) 3c509.h 　
16184
 ERR_RX_OVERSIZEERR_RX_OVERSIZE (unsigned short) (0x9<<11) 3c509.h 　
16185
 ERR_RX_DRIBBLEERR_RX_DRIBBLE (unsigned short) (0x2<<11) 3c509.h 　
16186
 TXS_COMPLETETXS_COMPLETE 0x80 3c509.h 　
16187
 TXS_SUCCES_INTR_REQTXS_SUCCES_INTR_REQ 0x40 3c509.h 　
16188
 TXS_JABBERTXS_JABBER 0x20 3c509.h 　
16189
 TXS_UNDERRUNTXS_UNDERRUN 0x10 3c509.h 　
16190
 TXS_MAX_COLLISIONTXS_MAX_COLLISION 0x8 3c509.h 　
16191
 TXS_STATUS_OVERFLOWTXS_STATUS_OVERFLOW 0x4 3c509.h 　
16192
 IS_AUIIS_AUI (1<<13) 3c509.h 　
16193
 IS_BNCIS_BNC (1<<12) 3c509.h 　
16194
 IS_UTPIS_UTP (1<<9) 3c509.h 　
16195
 ENABLE_DRQ_IRQENABLE_DRQ_IRQ 0x0001 3c509.h 　
16196
 W0_P4_CMD_RESET_ADAPTERW0_P4_CMD_RESET_ADAPTER 0x4 3c509.h 　
16197
 W0_P4_CMD_ENABLE_ADAPTERW0_P4_CMD_ENABLE_ADAPTER 0x1 3c509.h 　
16198
 ENABLE_UTPENABLE_UTP 0xc0 3c509.h 　
16199
 DISABLE_UTPDISABLE_UTP 0x0 3c509.h 　
16200
 RX_BYTES_MASKRX_BYTES_MASK (unsigned short) (0x07ff) 3c509.h 　
16201
 RX_ERRORRX_ERROR 0x4000 3c509.h 　
16202
 RX_INCOMPLETERX_INCOMPLETE 0x8000 3c509.h 　
16203
 MFG_IDMFG_ID 0x6d50 3c509.h in EEPROM and W0 ADDR_CONFIG
16204
 PROD_IDPROD_ID 0x9150 3c509.h 　
16205
 AUIAUI 0x1 3c509.h 　
16206
 BNCBNC 0x2 3c509.h 　
16207
 UTPUTP 0x4 3c509.h 　
16208
 RX_BYTES_MASKRX_BYTES_MASK (unsigned short) (0x07ff) 3c509.h 　
16209
 TX_INIT_RATETX_INIT_RATE 16 3c595.h 　
16210
 TX_INIT_MAX_RATETX_INIT_MAX_RATE 64 3c595.h 　
16211
 RX_INIT_LATENCYRX_INIT_LATENCY 64 3c595.h 　
16212
 RX_INIT_EARLY_THRESHRX_INIT_EARLY_THRESH 64 3c595.h 　
16213
 MIN_RX_EARLY_THRESHFMIN_RX_EARLY_THRESHF 16 3c595.h not less than ether_header
16214
 MIN_RX_EARLY_THRESHLMIN_RX_EARLY_THRESHL 4 3c595.h 　
16215
 EEPROMSIZEEEPROMSIZE 0x40 3c595.h 　
16216
 MAX_EEPROMBUSYMAX_EEPROMBUSY 1000 3c595.h 　
16217
 VX_LAST_TAGVX_LAST_TAG 0xd7 3c595.h 　
16218
 VX_MAX_BOARDSVX_MAX_BOARDS 16 3c595.h 　
16219
 VX_ID_PORTVX_ID_PORT 0x100 3c595.h 　
16220
 BASEBASE (eth_nic_base) 3c595.h 　
16221
 EEPROM_CMD_RDEEPROM_CMD_RD 0x0080 3c595.h Read: Address required (5 bits)
16222
 EEPROM_CMD_WREEPROM_CMD_WR 0x0040 3c595.h Write: Address required (5 bits)
16223
 EEPROM_CMD_ERASEEEPROM_CMD_ERASE 0x00c0 3c595.h Erase: Address required (5 bits)
16224
 EEPROM_CMD_EWENEEPROM_CMD_EWEN 0x0030 3c595.h Erase/Write Enable: No data required
16225
 EEPROM_BUSYEEPROM_BUSY (1<<15) 3c595.h 　
16226
 EEPROM_NODE_ADDR_0EEPROM_NODE_ADDR_0 0x0 3c595.h Word
16227
 EEPROM_NODE_ADDR_1EEPROM_NODE_ADDR_1 0x1 3c595.h Word
16228
 EEPROM_NODE_ADDR_2EEPROM_NODE_ADDR_2 0x2 3c595.h Word
16229
 EEPROM_PROD_IDEEPROM_PROD_ID 0x3 3c595.h 0x9[0-f]50
16230
 EEPROM_MFG_IDEEPROM_MFG_ID 0x7 3c595.h 0x6d50
16231
 EEPROM_ADDR_CFGEEPROM_ADDR_CFG 0x8 3c595.h Base addr
16232
 EEPROM_RESOURCE_CFGEEPROM_RESOURCE_CFG 0x9 3c595.h IRQ. Bits 12-15
16233
 EEPROM_OEM_ADDR_0EEPROM_OEM_ADDR_0 0xa 3c595.h Word
16234
 EEPROM_OEM_ADDR_1EEPROM_OEM_ADDR_1 0xb 3c595.h Word
16235
 EEPROM_OEM_ADDR_2EEPROM_OEM_ADDR_2 0xc 3c595.h Word
16236
 EEPROM_SOFT_INFO_2EEPROM_SOFT_INFO_2 0xf 3c595.h Software information 2
16237
 NO_RX_OVN_ANOMALYNO_RX_OVN_ANOMALY (1<<5) 3c595.h 　
16238
 VX_COMMANDVX_COMMAND 0x0e 3c595.h Write. BASE+0x0e is always a
16239
 VX_STATUSVX_STATUS 0x0e 3c595.h Read. BASE+0x0e is always status
16240
 VX_WINDOWVX_WINDOW 0x0f 3c595.h Read. BASE+0x0f is always window
16241
 VX_W0_EEPROM_DATAVX_W0_EEPROM_DATA 0x0c 3c595.h 　
16242
 VX_W0_EEPROM_COMMANDVX_W0_EEPROM_COMMAND 0x0a 3c595.h 　
16243
 VX_W0_RESOURCE_CFGVX_W0_RESOURCE_CFG 0x08 3c595.h 　
16244
 VX_W0_ADDRESS_CFGVX_W0_ADDRESS_CFG 0x06 3c595.h 　
16245
 VX_W0_CONFIG_CTRLVX_W0_CONFIG_CTRL 0x04 3c595.h 　
16246
 VX_W0_PRODUCT_IDVX_W0_PRODUCT_ID 0x02 3c595.h 　
16247
 VX_W0_MFG_IDVX_W0_MFG_ID 0x00 3c595.h 　
16248
 VX_W1_TX_PIO_WR_2VX_W1_TX_PIO_WR_2 0x02 3c595.h 　
16249
 VX_W1_TX_PIO_WR_1VX_W1_TX_PIO_WR_1 0x00 3c595.h 　
16250
 VX_W1_FREE_TXVX_W1_FREE_TX 0x0c 3c595.h 　
16251
 VX_W1_TX_STATUSVX_W1_TX_STATUS 0x0b 3c595.h byte
16252
 VX_W1_TIMERVX_W1_TIMER 0x0a 3c595.h byte
16253
 VX_W1_RX_STATUSVX_W1_RX_STATUS 0x08 3c595.h 　
16254
 VX_W1_RX_PIO_RD_2VX_W1_RX_PIO_RD_2 0x02 3c595.h 　
16255
 VX_W1_RX_PIO_RD_1VX_W1_RX_PIO_RD_1 0x00 3c595.h 　
16256
 VX_W2_ADDR_5VX_W2_ADDR_5 0x05 3c595.h 　
16257
 VX_W2_ADDR_4VX_W2_ADDR_4 0x04 3c595.h 　
16258
 VX_W2_ADDR_3VX_W2_ADDR_3 0x03 3c595.h 　
16259
 VX_W2_ADDR_2VX_W2_ADDR_2 0x02 3c595.h 　
16260
 VX_W2_ADDR_1VX_W2_ADDR_1 0x01 3c595.h 　
16261
 VX_W2_ADDR_0VX_W2_ADDR_0 0x00 3c595.h 　
16262
 VX_W3_INTERNAL_CFGVX_W3_INTERNAL_CFG 0x00 3c595.h 　
16263
 VX_W3_RESET_OPTVX_W3_RESET_OPT 0x08 3c595.h 　
16264
 VX_W3_FREE_TXVX_W3_FREE_TX 0x0c 3c595.h 　
16265
 VX_W3_FREE_RXVX_W3_FREE_RX 0x0a 3c595.h 　
16266
 VX_W4_MEDIA_TYPEVX_W4_MEDIA_TYPE 0x0a 3c595.h 　
16267
 VX_W4_CTRLR_STATUSVX_W4_CTRLR_STATUS 0x08 3c595.h 　
16268
 VX_W4_NET_DIAGVX_W4_NET_DIAG 0x06 3c595.h 　
16269
 VX_W4_FIFO_DIAGVX_W4_FIFO_DIAG 0x04 3c595.h 　
16270
 VX_W4_HOST_DIAGVX_W4_HOST_DIAG 0x02 3c595.h 　
16271
 VX_W4_TX_DIAGVX_W4_TX_DIAG 0x00 3c595.h 　
16272
 VX_W5_READ_0_MASKVX_W5_READ_0_MASK 0x0c 3c595.h 　
16273
 VX_W5_INTR_MASKVX_W5_INTR_MASK 0x0a 3c595.h 　
16274
 VX_W5_RX_FILTERVX_W5_RX_FILTER 0x08 3c595.h 　
16275
 VX_W5_RX_EARLY_THRESHVX_W5_RX_EARLY_THRESH 0x06 3c595.h 　
16276
 VX_W5_TX_AVAIL_THRESHVX_W5_TX_AVAIL_THRESH 0x02 3c595.h 　
16277
 VX_W5_TX_START_THRESHVX_W5_TX_START_THRESH 0x00 3c595.h 　
16278
 TX_TOTAL_OKTX_TOTAL_OK 0x0c 3c595.h 　
16279
 RX_TOTAL_OKRX_TOTAL_OK 0x0a 3c595.h 　
16280
 TX_DEFERRALSTX_DEFERRALS 0x08 3c595.h 　
16281
 RX_FRAMES_OKRX_FRAMES_OK 0x07 3c595.h 　
16282
 TX_FRAMES_OKTX_FRAMES_OK 0x06 3c595.h 　
16283
 RX_OVERRUNSRX_OVERRUNS 0x05 3c595.h 　
16284
 TX_COLLISIONSTX_COLLISIONS 0x04 3c595.h 　
16285
 TX_AFTER_1_COLLISIONTX_AFTER_1_COLLISION 0x03 3c595.h 　
16286
 TX_AFTER_X_COLLISIONSTX_AFTER_X_COLLISIONS 0x02 3c595.h 　
16287
 TX_NO_SQETX_NO_SQE 0x01 3c595.h 　
16288
 TX_CD_LOSTTX_CD_LOST 0x00 3c595.h 　
16289
 GLOBAL_RESETGLOBAL_RESET (unsigned short) 0x0000 3c595.h Wait at least 1ms
16290
 WINDOW_SELECTWINDOW_SELECT (unsigned short) (0x1<<11) 3c595.h 　
16291
 START_TRANSCEIVERSTART_TRANSCEIVER (unsigned short) (0x2<<11) 3c595.h Read ADDR_CFG reg to
16292
 RX_DISABLERX_DISABLE (unsigned short) (0x3<<11) 3c595.h state disabled on
16293
 RX_ENABLERX_ENABLE (unsigned short) (0x4<<11) 3c595.h 　
16294
 RX_RESETRX_RESET (unsigned short) (0x5<<11) 3c595.h 　
16295
 RX_DISCARD_TOP_PACKRX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) 3c595.h 　
16296
 TX_ENABLETX_ENABLE (unsigned short) (0x9<<11) 3c595.h 　
16297
 TX_DISABLETX_DISABLE (unsigned short) (0xa<<11) 3c595.h 　
16298
 TX_RESETTX_RESET (unsigned short) (0xb<<11) 3c595.h 　
16299
 REQ_INTRREQ_INTR (unsigned short) (0xc<<11) 3c595.h 　
16300
 ACK_INTRACK_INTR (unsigned short) (0x6800) 3c595.h 　
16301
 C_INTR_LATCHC_INTR_LATCH (unsigned short) (ACK_INTR|0x1) 3c595.h 　
16302
 C_CARD_FAILUREC_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) 3c595.h 　
16303
 C_TX_COMPLETEC_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) 3c595.h 　
16304
 C_TX_AVAILC_TX_AVAIL (unsigned short) (ACK_INTR|0x8) 3c595.h 　
16305
 C_RX_COMPLETEC_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) 3c595.h 　
16306
 C_RX_EARLYC_RX_EARLY (unsigned short) (ACK_INTR|0x20) 3c595.h 　
16307
 C_INT_RQDC_INT_RQD (unsigned short) (ACK_INTR|0x40) 3c595.h 　
16308
 C_UPD_STATSC_UPD_STATS (unsigned short) (ACK_INTR|0x80) 3c595.h 　
16309
 SET_INTR_MASKSET_INTR_MASK (unsigned short) (0xe<<11) 3c595.h 　
16310
 SET_RD_0_MASKSET_RD_0_MASK (unsigned short) (0xf<<11) 3c595.h 　
16311
 SET_RX_FILTERSET_RX_FILTER (unsigned short) (0x10<<11) 3c595.h 　
16312
 FIL_INDIVIDUALFIL_INDIVIDUAL (unsigned short) (0x1) 3c595.h 　
16313
 FIL_MULTICASTFIL_MULTICAST (unsigned short) (0x02) 3c595.h 　
16314
 FIL_BRDCSTFIL_BRDCST (unsigned short) (0x04) 3c595.h 　
16315
 FIL_PROMISCFIL_PROMISC (unsigned short) (0x08) 3c595.h 　
16316
 SET_RX_EARLY_THRESHSET_RX_EARLY_THRESH (unsigned short) (0x11<<11) 3c595.h 　
16317
 SET_TX_AVAIL_THRESHSET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) 3c595.h 　
16318
 SET_TX_START_THRESHSET_TX_START_THRESH (unsigned short) (0x13<<11) 3c595.h 　
16319
 STATS_ENABLESTATS_ENABLE (unsigned short) (0x15<<11) 3c595.h 　
16320
 STATS_DISABLESTATS_DISABLE (unsigned short) (0x16<<11) 3c595.h 　
16321
 STOP_TRANSCEIVERSTOP_TRANSCEIVER (unsigned short) (0x17<<11) 3c595.h 　
16322
 S_INTR_LATCHS_INTR_LATCH (unsigned short) (0x1) 3c595.h 　
16323
 S_CARD_FAILURES_CARD_FAILURE (unsigned short) (0x2) 3c595.h 　
16324
 S_TX_COMPLETES_TX_COMPLETE (unsigned short) (0x4) 3c595.h 　
16325
 S_TX_AVAILS_TX_AVAIL (unsigned short) (0x8) 3c595.h 　
16326
 S_RX_COMPLETES_RX_COMPLETE (unsigned short) (0x10) 3c595.h 　
16327
 S_RX_EARLYS_RX_EARLY (unsigned short) (0x20) 3c595.h 　
16328
 S_INT_RQDS_INT_RQD (unsigned short) (0x40) 3c595.h 　
16329
 S_UPD_STATSS_UPD_STATS (unsigned short) (0x80) 3c595.h 　
16330
 S_COMMAND_IN_PROGRESSS_COMMAND_IN_PROGRESS (unsigned short) (0x1000) 3c595.h 　
16331
 VX_BUSY_WAITVX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) 3c595.h 　
16332
 ACF_CONNECTOR_BITSACF_CONNECTOR_BITS 14 3c595.h 　
16333
 ACF_CONNECTOR_UTPACF_CONNECTOR_UTP 0 3c595.h 　
16334
 ACF_CONNECTOR_AUIACF_CONNECTOR_AUI 1 3c595.h 　
16335
 ACF_CONNECTOR_BNCACF_CONNECTOR_BNC 3 3c595.h 　
16336
 INTERNAL_CONNECTOR_BITSINTERNAL_CONNECTOR_BITS 20 3c595.h 　
16337
 INTERNAL_CONNECTOR_MASKINTERNAL_CONNECTOR_MASK 0x01700000 3c595.h 　
16338
 ERR_INCOMPLETEERR_INCOMPLETE (unsigned short) (0x8000) 3c595.h 　
16339
 ERR_RXERR_RX (unsigned short) (0x4000) 3c595.h 　
16340
 ERR_MASKERR_MASK (unsigned short) (0x7800) 3c595.h 　
16341
 ERR_OVERRUNERR_OVERRUN (unsigned short) (0x4000) 3c595.h 　
16342
 ERR_RUNTERR_RUNT (unsigned short) (0x5800) 3c595.h 　
16343
 ERR_ALIGNMENTERR_ALIGNMENT (unsigned short) (0x6000) 3c595.h 　
16344
 ERR_CRCERR_CRC (unsigned short) (0x6800) 3c595.h 　
16345
 ERR_OVERSIZEERR_OVERSIZE (unsigned short) (0x4800) 3c595.h 　
16346
 ERR_DRIBBLEERR_DRIBBLE (unsigned short) (0x1000) 3c595.h 　
16347
 TXS_COMPLETETXS_COMPLETE 0x80 3c595.h 　
16348
 TXS_INTR_REQTXS_INTR_REQ 0x40 3c595.h 　
16349
 TXS_JABBERTXS_JABBER 0x20 3c595.h 　
16350
 TXS_UNDERRUNTXS_UNDERRUN 0x10 3c595.h 　
16351
 TXS_MAX_COLLISIONTXS_MAX_COLLISION 0x8 3c595.h 　
16352
 TXS_STATUS_OVERFLOWTXS_STATUS_OVERFLOW 0x4 3c595.h 　
16353
 RS_AUIRS_AUI (1<<5) 3c595.h 　
16354
 RS_BNCRS_BNC (1<<4) 3c595.h 　
16355
 RS_UTPRS_UTP (1<<3) 3c595.h 　
16356
 RS_T4RS_T4 (1<<0) 3c595.h 　
16357
 RS_TXRS_TX (1<<1) 3c595.h 　
16358
 RS_FXRS_FX (1<<2) 3c595.h 　
16359
 RS_MIIRS_MII (1<<6) 3c595.h 　
16360
 FIFOS_RX_RECEIVINGFIFOS_RX_RECEIVING (unsigned short) 0x8000 3c595.h 　
16361
 FIFOS_RX_UNDERRUNFIFOS_RX_UNDERRUN (unsigned short) 0x2000 3c595.h 　
16362
 FIFOS_RX_STATUS_OVERRUNFIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000 3c595.h 　
16363
 FIFOS_RX_OVERRUNFIFOS_RX_OVERRUN (unsigned short) 0x0800 3c595.h 　
16364
 FIFOS_TX_OVERRUNFIFOS_TX_OVERRUN (unsigned short) 0x0400 3c595.h 　
16365
 TAG_ADAPTERTAG_ADAPTER 0xd0 3c595.h 　
16366
 ACTIVATE_ADAPTER_TO_CONFIGACTIVATE_ADAPTER_TO_CONFIG 0xff 3c595.h 　
16367
 ENABLE_DRQ_IRQENABLE_DRQ_IRQ 0x0001 3c595.h 　
16368
 MFG_IDMFG_ID 0x506d 3c595.h `TCM'
16369
 PROD_IDPROD_ID 0x5090 3c595.h 　
16370
 JABBER_GUARD_ENABLEJABBER_GUARD_ENABLE 0x40 3c595.h 　
16371
 LINKBEAT_ENABLELINKBEAT_ENABLE 0x80 3c595.h 　
16372
 ENABLE_UTPENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) 3c595.h 　
16373
 DISABLE_UTPDISABLE_UTP 0x0 3c595.h 　
16374
 RX_BYTES_MASKRX_BYTES_MASK (unsigned short) (0x07ff) 3c595.h 　
16375
 RX_ERRORRX_ERROR 0x4000 3c595.h 　
16376
 RX_INCOMPLETERX_INCOMPLETE 0x8000 3c595.h 　
16377
 TX_INDICATETX_INDICATE 1<<15 3c595.h 　
16378
 VX_IOSIZEVX_IOSIZE 0x20 3c595.h 　
16379
 VX_CONNECTORSVX_CONNECTORS 8 3c595.h 　
16380
 XCVR_MAGICXCVR_MAGIC (0x5A00) 3c90x.h 　
16381
 INT_INTERRUPTLATCHINT_INTERRUPTLATCH (1<<0) 3c90x.h 　
16382
 INT_HOSTERRORINT_HOSTERROR (1<<1) 3c90x.h 　
16383
 INT_TXCOMPLETEINT_TXCOMPLETE (1<<2) 3c90x.h 　
16384
 INT_RXCOMPLETEINT_RXCOMPLETE (1<<4) 3c90x.h 　
16385
 INT_RXEARLYINT_RXEARLY (1<<5) 3c90x.h 　
16386
 INT_INTREQUESTEDINT_INTREQUESTED (1<<6) 3c90x.h 　
16387
 INT_UPDATESTATSINT_UPDATESTATS (1<<7) 3c90x.h 　
16388
 INT_LINKEVENTINT_LINKEVENT (1<<8) 3c90x.h 　
16389
 INT_DNCOMPLETEINT_DNCOMPLETE (1<<9) 3c90x.h 　
16390
 INT_UPCOMPLETEINT_UPCOMPLETE (1<<10) 3c90x.h 　
16391
 INT_CMDINPROGRESSINT_CMDINPROGRESS (1<<12) 3c90x.h 　
16392
 INT_WINDOWNUMBERINT_WINDOWNUMBER (7<<13) 3c90x.h 　
16393
 TX_RING_SIZETX_RING_SIZE 8 3c90x.h 　
16394
 RX_RING_SIZERX_RING_SIZE 8 3c90x.h 　
16395
 TX_RING_ALIGNTX_RING_ALIGN 16 3c90x.h 　
16396
 RX_RING_ALIGNRX_RING_ALIGN 16 3c90x.h 　
16397
 RX_BUF_SIZERX_BUF_SIZE 1536 3c90x.h 　
16398
 EEPROM_TIMEOUTEEPROM_TIMEOUT 1 * 1000 * 1000 3c90x.h 　
16399
 ASF_STATASF_STAT 0x00 amd8111e.h ASF status register
16400
 CHIPIDCHIPID 0x04 amd8111e.h Chip ID regsiter
16401
 MIB_DATAMIB_DATA 0x10 amd8111e.h MIB data register
16402
 MIB_ADDRMIB_ADDR 0x14 amd8111e.h MIB address register
16403
 STAT0STAT0 0x30 amd8111e.h Status0 register
16404
 INT0INT0 0x38 amd8111e.h Interrupt0 register
16405
 INTEN0INTEN0 0x40 amd8111e.h Interrupt0 enable register
16406
 CMD0CMD0 0x48 amd8111e.h Command0 register
16407
 CMD2CMD2 0x50 amd8111e.h Command2 register
16408
 CMD3CMD3 0x54 amd8111e.h Command3 resiter
16409
 CMD7CMD7 0x64 amd8111e.h Command7 register
16410
 CTRL1CTRL1 0x6C amd8111e.h Control1 register
16411
 CTRL2CTRL2 0x70 amd8111e.h Control2 register
16412
 XMT_RING_LIMITXMT_RING_LIMIT 0x7C amd8111e.h Transmit ring limit register
16413
 AUTOPOLL0AUTOPOLL0 0x88 amd8111e.h Auto-poll0 register
16414
 AUTOPOLL1AUTOPOLL1 0x8A amd8111e.h Auto-poll1 register
16415
 AUTOPOLL2AUTOPOLL2 0x8C amd8111e.h Auto-poll2 register
16416
 AUTOPOLL3AUTOPOLL3 0x8E amd8111e.h Auto-poll3 register
16417
 AUTOPOLL4AUTOPOLL4 0x90 amd8111e.h Auto-poll4 register
16418
 AUTOPOLL5AUTOPOLL5 0x92 amd8111e.h Auto-poll5 register
16419
 AP_VALUEAP_VALUE 0x98 amd8111e.h Auto-poll value register
16420
 DLY_INT_ADLY_INT_A 0xA8 amd8111e.h Group A delayed interrupt register
16421
 DLY_INT_BDLY_INT_B 0xAC amd8111e.h Group B delayed interrupt register
16422
 FLOW_CONTROLFLOW_CONTROL 0xC8 amd8111e.h Flow control register
16423
 PHY_ACCESSPHY_ACCESS 0xD0 amd8111e.h PHY access register
16424
 STVALSTVAL 0xD8 amd8111e.h Software timer value register
16425
 XMT_RING_BASE_ADDR0XMT_RING_BASE_ADDR0 0x100 amd8111e.h Transmit ring0 base addr register
16426
 XMT_RING_BASE_ADDR1XMT_RING_BASE_ADDR1 0x108 amd8111e.h Transmit ring1 base addr register
16427
 XMT_RING_BASE_ADDR2XMT_RING_BASE_ADDR2 0x110 amd8111e.h Transmit ring2 base addr register
16428
 XMT_RING_BASE_ADDR3XMT_RING_BASE_ADDR3 0x118 amd8111e.h Transmit ring2 base addr register
16429
 RCV_RING_BASE_ADDR0RCV_RING_BASE_ADDR0 0x120 amd8111e.h Transmit ring0 base addr register
16430
 PMAT0PMAT0 0x190 amd8111e.h OnNow pattern register0
16431
 PMAT1PMAT1 0x194 amd8111e.h OnNow pattern register1
16432
 XMT_RING_LEN0XMT_RING_LEN0 0x140 amd8111e.h Transmit Ring0 length register
16433
 XMT_RING_LEN1XMT_RING_LEN1 0x144 amd8111e.h Transmit Ring1 length register
16434
 XMT_RING_LEN2XMT_RING_LEN2 0x148 amd8111e.h Transmit Ring2 length register
16435
 XMT_RING_LEN3XMT_RING_LEN3 0x14C amd8111e.h Transmit Ring3 length register
16436
 RCV_RING_LEN0RCV_RING_LEN0 0x150 amd8111e.h Receive Ring0 length register
16437
 SRAM_SIZESRAM_SIZE 0x178 amd8111e.h SRAM size register
16438
 SRAM_BOUNDARYSRAM_BOUNDARY 0x17A amd8111e.h SRAM boundary register
16439
 PADRPADR 0x160 amd8111e.h Physical address register
16440
 IFS1IFS1 0x18C amd8111e.h Inter-frame spacing Part1 register
16441
 IFSIFS 0x18D amd8111e.h Inter-frame spacing register
16442
 IPGIPG 0x18E amd8111e.h Inter-frame gap register
16443
 LADRFLADRF 0x168 amd8111e.h Logical address filter register
16444
 PHY_SPEED_10PHY_SPEED_10 0x2 amd8111e.h 　
16445
 PHY_SPEED_100PHY_SPEED_100 0x3 amd8111e.h 　
16446
 rcv_miss_pktsrcv_miss_pkts 0x00 amd8111e.h 　
16447
 rcv_octetsrcv_octets 0x01 amd8111e.h 　
16448
 rcv_broadcast_pktsrcv_broadcast_pkts 0x02 amd8111e.h 　
16449
 rcv_multicast_pktsrcv_multicast_pkts 0x03 amd8111e.h 　
16450
 rcv_undersize_pktsrcv_undersize_pkts 0x04 amd8111e.h 　
16451
 rcv_oversize_pktsrcv_oversize_pkts 0x05 amd8111e.h 　
16452
 rcv_fragmentsrcv_fragments 0x06 amd8111e.h 　
16453
 rcv_jabbersrcv_jabbers 0x07 amd8111e.h 　
16454
 rcv_unicast_pktsrcv_unicast_pkts 0x08 amd8111e.h 　
16455
 rcv_alignment_errorsrcv_alignment_errors 0x09 amd8111e.h 　
16456
 rcv_fcs_errorsrcv_fcs_errors 0x0A amd8111e.h 　
16457
 rcv_good_octetsrcv_good_octets 0x0B amd8111e.h 　
16458
 rcv_mac_ctrlrcv_mac_ctrl 0x0C amd8111e.h 　
16459
 rcv_flow_ctrlrcv_flow_ctrl 0x0D amd8111e.h 　
16460
 rcv_pkts_64_octetsrcv_pkts_64_octets 0x0E amd8111e.h 　
16461
 rcv_pkts_65to127_octetsrcv_pkts_65to127_octets 0x0F amd8111e.h 　
16462
 rcv_pkts_128to255_octetsrcv_pkts_128to255_octets 0x10 amd8111e.h 　
16463
 rcv_pkts_256to511_octetsrcv_pkts_256to511_octets 0x11 amd8111e.h 　
16464
 rcv_pkts_512to1023_octetsrcv_pkts_512to1023_octets 0x12 amd8111e.h 　
16465
 rcv_pkts_1024to1518_octetsrcv_pkts_1024to1518_octets 0x13 amd8111e.h 　
16466
 rcv_unsupported_opcodercv_unsupported_opcode 0x14 amd8111e.h 　
16467
 rcv_symbol_errorsrcv_symbol_errors 0x15 amd8111e.h 　
16468
 rcv_drop_pkts_ring1rcv_drop_pkts_ring1 0x16 amd8111e.h 　
16469
 rcv_drop_pkts_ring2rcv_drop_pkts_ring2 0x17 amd8111e.h 　
16470
 rcv_drop_pkts_ring3rcv_drop_pkts_ring3 0x18 amd8111e.h 　
16471
 rcv_drop_pkts_ring4rcv_drop_pkts_ring4 0x19 amd8111e.h 　
16472
 rcv_jumbo_pktsrcv_jumbo_pkts 0x1A amd8111e.h 　
16473
 xmt_underrun_pktsxmt_underrun_pkts 0x20 amd8111e.h 　
16474
 xmt_octetsxmt_octets 0x21 amd8111e.h 　
16475
 xmt_packetsxmt_packets 0x22 amd8111e.h 　
16476
 xmt_broadcast_pktsxmt_broadcast_pkts 0x23 amd8111e.h 　
16477
 xmt_multicast_pktsxmt_multicast_pkts 0x24 amd8111e.h 　
16478
 xmt_collisionsxmt_collisions 0x25 amd8111e.h 　
16479
 xmt_unicast_pktsxmt_unicast_pkts 0x26 amd8111e.h 　
16480
 xmt_one_collisionxmt_one_collision 0x27 amd8111e.h 　
16481
 xmt_multiple_collisionxmt_multiple_collision 0x28 amd8111e.h 　
16482
 xmt_deferred_transmitxmt_deferred_transmit 0x29 amd8111e.h 　
16483
 xmt_late_collisionxmt_late_collision 0x2A amd8111e.h 　
16484
 xmt_excessive_deferxmt_excessive_defer 0x2B amd8111e.h 　
16485
 xmt_loss_carrierxmt_loss_carrier 0x2C amd8111e.h 　
16486
 xmt_excessive_collisionxmt_excessive_collision 0x2D amd8111e.h 　
16487
 xmt_back_pressurexmt_back_pressure 0x2E amd8111e.h 　
16488
 xmt_flow_ctrlxmt_flow_ctrl 0x2F amd8111e.h 　
16489
 xmt_pkts_64_octetsxmt_pkts_64_octets 0x30 amd8111e.h 　
16490
 xmt_pkts_65to127_octetsxmt_pkts_65to127_octets 0x31 amd8111e.h 　
16491
 xmt_pkts_128to255_octetsxmt_pkts_128to255_octets 0x32 amd8111e.h 　
16492
 xmt_pkts_256to511_octetsxmt_pkts_256to511_octets 0x33 amd8111e.h 　
16493
 xmt_pkts_512to1023_octetsxmt_pkts_512to1023_octets 0x34 amd8111e.h 　
16494
 xmt_pkts_1024to1518_octetxmt_pkts_1024to1518_octet 0x35 amd8111e.h 　
16495
 xmt_oversize_pktsxmt_oversize_pkts 0x36 amd8111e.h 　
16496
 xmt_jumbo_pktsxmt_jumbo_pkts 0x37 amd8111e.h 　
16497
 DEFAULT_IPGDEFAULT_IPG 0x60 amd8111e.h 　
16498
 IFS1_DELTAIFS1_DELTA 36 amd8111e.h 　
16499
 IPG_CONVERGE_JIFFIESIPG_CONVERGE_JIFFIES (HZ/2) amd8111e.h 　
16500
 IPG_STABLE_TIMEIPG_STABLE_TIME 5 amd8111e.h 　
16501
 MIN_IPGMIN_IPG 96 amd8111e.h 　
16502
 MAX_IPGMAX_IPG 255 amd8111e.h 　
16503
 IPG_STEPIPG_STEP 16 amd8111e.h 　
16504
 CSTATECSTATE 1 amd8111e.h 　
16505
 SSTATESSTATE 2 amd8111e.h 　
16506
 RESET_RX_FLAGSRESET_RX_FLAGS 0x0000 amd8111e.h 　
16507
 TT_MASKTT_MASK 0x000c amd8111e.h 　
16508
 TCC_MASKTCC_MASK 0x0003 amd8111e.h 　
16509
 AMD8111E_REG_DUMP_LENAMD8111E_REG_DUMP_LEN 13*sizeof(u32) amd8111e.h 　
16510
 CRC32CRC32 0xedb88320 amd8111e.h 　
16511
 INITCRCINITCRC 0xFFFFFFFF amd8111e.h 　
16512
 ETH_FCS_LENETH_FCS_LEN 4 atl1e.h 　
16513
 VLAN_HLENVLAN_HLEN 4 atl1e.h 　
16514
 NET_IP_ALIGNNET_IP_ALIGN 2 atl1e.h 　
16515
 SPEED_0SPEED_0 0xffff atl1e.h 　
16516
 SPEED_10SPEED_10 10 atl1e.h 　
16517
 SPEED_100SPEED_100 100 atl1e.h 　
16518
 SPEED_1000SPEED_1000 1000 atl1e.h 　
16519
 HALF_DUPLEXHALF_DUPLEX 1 atl1e.h 　
16520
 FULL_DUPLEXFULL_DUPLEX 2 atl1e.h 　
16521
 AT_ERR_EEPROMAT_ERR_EEPROM 1 atl1e.h 　
16522
 AT_ERR_PHYAT_ERR_PHY 2 atl1e.h 　
16523
 AT_ERR_CONFIGAT_ERR_CONFIG 3 atl1e.h 　
16524
 AT_ERR_PARAMAT_ERR_PARAM 4 atl1e.h 　
16525
 AT_ERR_MAC_TYPEAT_ERR_MAC_TYPE 5 atl1e.h 　
16526
 AT_ERR_PHY_TYPEAT_ERR_PHY_TYPE 6 atl1e.h 　
16527
 AT_ERR_PHY_SPEEDAT_ERR_PHY_SPEED 7 atl1e.h 　
16528
 AT_ERR_PHY_RESAT_ERR_PHY_RES 8 atl1e.h 　
16529
 AT_ERR_TIMEOUTAT_ERR_TIMEOUT 9 atl1e.h 　
16530
 AT_MAX_RECEIVE_QUEUEAT_MAX_RECEIVE_QUEUE 4 atl1e.h 　
16531
 AT_PAGE_NUM_PER_QUEUEAT_PAGE_NUM_PER_QUEUE 2 atl1e.h 　
16532
 AT_TWSI_EEPROM_TIMEOUTAT_TWSI_EEPROM_TIMEOUT 100 atl1e.h 　
16533
 AT_HW_MAX_IDLE_DELAYAT_HW_MAX_IDLE_DELAY 10 atl1e.h 　
16534
 AT_REGS_LENAT_REGS_LEN 75 atl1e.h 　
16535
 AT_EEPROM_LENAT_EEPROM_LEN 512 atl1e.h 　
16536
 TPD_BUFLEN_MASKTPD_BUFLEN_MASK 0x3FFF atl1e.h 　
16537
 TPD_BUFLEN_SHIFTTPD_BUFLEN_SHIFT 0 atl1e.h 　
16538
 TPD_EOP_MASKTPD_EOP_MASK 0x0001 atl1e.h 　
16539
 TPD_EOP_SHIFTTPD_EOP_SHIFT 0 atl1e.h 　
16540
 MAX_TX_BUF_LENMAX_TX_BUF_LEN 0x2000 atl1e.h 　
16541
 MAX_TX_BUF_SHIFTMAX_TX_BUF_SHIFT 13 atl1e.h 　
16542
 RRS_RX_CSUM_MASKRRS_RX_CSUM_MASK 0xFFFF atl1e.h 　
16543
 RRS_RX_CSUM_SHIFTRRS_RX_CSUM_SHIFT 0 atl1e.h 　
16544
 RRS_PKT_SIZE_MASKRRS_PKT_SIZE_MASK 0x3FFF atl1e.h 　
16545
 RRS_PKT_SIZE_SHIFTRRS_PKT_SIZE_SHIFT 16 atl1e.h 　
16546
 RRS_CPU_NUM_MASKRRS_CPU_NUM_MASK 0x0003 atl1e.h 　
16547
 RRS_CPU_NUM_SHIFTRRS_CPU_NUM_SHIFT 30 atl1e.h 　
16548
 RRS_IS_RSS_IPV4RRS_IS_RSS_IPV4 0x0001 atl1e.h 　
16549
 RRS_IS_RSS_IPV4_TCPRRS_IS_RSS_IPV4_TCP 0x0002 atl1e.h 　
16550
 RRS_IS_RSS_IPV6RRS_IS_RSS_IPV6 0x0004 atl1e.h 　
16551
 RRS_IS_RSS_IPV6_TCPRRS_IS_RSS_IPV6_TCP 0x0008 atl1e.h 　
16552
 RRS_IS_IPV6RRS_IS_IPV6 0x0010 atl1e.h 　
16553
 RRS_IS_IP_FRAGRRS_IS_IP_FRAG 0x0020 atl1e.h 　
16554
 RRS_IS_IP_DFRRS_IS_IP_DF 0x0040 atl1e.h 　
16555
 RRS_IS_802_3RRS_IS_802_3 0x0080 atl1e.h 　
16556
 RRS_IS_VLAN_TAGRRS_IS_VLAN_TAG 0x0100 atl1e.h 　
16557
 RRS_IS_ERR_FRAMERRS_IS_ERR_FRAME 0x0200 atl1e.h 　
16558
 RRS_IS_IPV4RRS_IS_IPV4 0x0400 atl1e.h 　
16559
 RRS_IS_UDPRRS_IS_UDP 0x0800 atl1e.h 　
16560
 RRS_IS_TCPRRS_IS_TCP 0x1000 atl1e.h 　
16561
 RRS_IS_BCASTRRS_IS_BCAST 0x2000 atl1e.h 　
16562
 RRS_IS_MCASTRRS_IS_MCAST 0x4000 atl1e.h 　
16563
 RRS_IS_PAUSERRS_IS_PAUSE 0x8000 atl1e.h 　
16564
 RRS_ERR_BAD_CRCRRS_ERR_BAD_CRC 0x0001 atl1e.h 　
16565
 RRS_ERR_CODERRS_ERR_CODE 0x0002 atl1e.h 　
16566
 RRS_ERR_DRIBBLERRS_ERR_DRIBBLE 0x0004 atl1e.h 　
16567
 RRS_ERR_RUNTRRS_ERR_RUNT 0x0008 atl1e.h 　
16568
 RRS_ERR_RX_OVERFLOWRRS_ERR_RX_OVERFLOW 0x0010 atl1e.h 　
16569
 RRS_ERR_TRUNCRRS_ERR_TRUNC 0x0020 atl1e.h 　
16570
 RRS_ERR_IP_CSUMRRS_ERR_IP_CSUM 0x0040 atl1e.h 　
16571
 RRS_ERR_L4_CSUMRRS_ERR_L4_CSUM 0x0080 atl1e.h 　
16572
 RRS_ERR_LENGTHRRS_ERR_LENGTH 0x0100 atl1e.h 　
16573
 RRS_ERR_DES_ADDRRRS_ERR_DES_ADDR 0x0200 atl1e.h 　
16574
 REG_PM_CTRLSTATREG_PM_CTRLSTAT 0x44 atl1e.h 　
16575
 REG_PCIE_CAP_LISTREG_PCIE_CAP_LIST 0x58 atl1e.h 　
16576
 REG_DEVICE_CAPREG_DEVICE_CAP 0x5C atl1e.h 　
16577
 DEVICE_CAP_MAX_PAYLOAD_MASKDEVICE_CAP_MAX_PAYLOAD_MASK 0x7 atl1e.h 　
16578
 DEVICE_CAP_MAX_PAYLOAD_SHIFTDEVICE_CAP_MAX_PAYLOAD_SHIFT 0 atl1e.h 　
16579
 REG_DEVICE_CTRLREG_DEVICE_CTRL 0x60 atl1e.h 　
16580
 DEVICE_CTRL_MAX_PAYLOAD_MASKDEVICE_CTRL_MAX_PAYLOAD_MASK 0x7 atl1e.h 　
16581
 DEVICE_CTRL_MAX_PAYLOAD_SHIFTDEVICE_CTRL_MAX_PAYLOAD_SHIFT 5 atl1e.h 　
16582
 DEVICE_CTRL_MAX_RREQ_SZ_MASKDEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7 atl1e.h 　
16583
 DEVICE_CTRL_MAX_RREQ_SZ_SHIFTDEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12 atl1e.h 　
16584
 REG_VPD_CAPREG_VPD_CAP 0x6C atl1e.h 　
16585
 VPD_CAP_ID_MASKVPD_CAP_ID_MASK 0xff atl1e.h 　
16586
 VPD_CAP_ID_SHIFTVPD_CAP_ID_SHIFT 0 atl1e.h 　
16587
 VPD_CAP_NEXT_PTR_MASKVPD_CAP_NEXT_PTR_MASK 0xFF atl1e.h 　
16588
 VPD_CAP_NEXT_PTR_SHIFTVPD_CAP_NEXT_PTR_SHIFT 8 atl1e.h 　
16589
 VPD_CAP_VPD_ADDR_MASKVPD_CAP_VPD_ADDR_MASK 0x7FFF atl1e.h 　
16590
 VPD_CAP_VPD_ADDR_SHIFTVPD_CAP_VPD_ADDR_SHIFT 16 atl1e.h 　
16591
 VPD_CAP_VPD_FLAGVPD_CAP_VPD_FLAG 0x80000000 atl1e.h 　
16592
 REG_VPD_DATAREG_VPD_DATA 0x70 atl1e.h 　
16593
 REG_SPI_FLASH_CTRLREG_SPI_FLASH_CTRL 0x200 atl1e.h 　
16594
 SPI_FLASH_CTRL_STS_NON_RDYSPI_FLASH_CTRL_STS_NON_RDY 0x1 atl1e.h 　
16595
 SPI_FLASH_CTRL_STS_WENSPI_FLASH_CTRL_STS_WEN 0x2 atl1e.h 　
16596
 SPI_FLASH_CTRL_STS_WPENSPI_FLASH_CTRL_STS_WPEN 0x80 atl1e.h 　
16597
 SPI_FLASH_CTRL_DEV_STS_MASKSPI_FLASH_CTRL_DEV_STS_MASK 0xFF atl1e.h 　
16598
 SPI_FLASH_CTRL_DEV_STS_SHIFTSPI_FLASH_CTRL_DEV_STS_SHIFT 0 atl1e.h 　
16599
 SPI_FLASH_CTRL_INS_MASKSPI_FLASH_CTRL_INS_MASK 0x7 atl1e.h 　
16600
 SPI_FLASH_CTRL_INS_SHIFTSPI_FLASH_CTRL_INS_SHIFT 8 atl1e.h 　
16601
 SPI_FLASH_CTRL_STARTSPI_FLASH_CTRL_START 0x800 atl1e.h 　
16602
 SPI_FLASH_CTRL_EN_VPDSPI_FLASH_CTRL_EN_VPD 0x2000 atl1e.h 　
16603
 SPI_FLASH_CTRL_LDSTARTSPI_FLASH_CTRL_LDSTART 0x8000 atl1e.h 　
16604
 SPI_FLASH_CTRL_CS_HI_MASKSPI_FLASH_CTRL_CS_HI_MASK 0x3 atl1e.h 　
16605
 SPI_FLASH_CTRL_CS_HI_SHIFTSPI_FLASH_CTRL_CS_HI_SHIFT 16 atl1e.h 　
16606
 SPI_FLASH_CTRL_CS_HOLD_MASKSPI_FLASH_CTRL_CS_HOLD_MASK 0x3 atl1e.h 　
16607
 SPI_FLASH_CTRL_CS_HOLD_SHIFTSPI_FLASH_CTRL_CS_HOLD_SHIFT 18 atl1e.h 　
16608
 SPI_FLASH_CTRL_CLK_LO_MASKSPI_FLASH_CTRL_CLK_LO_MASK 0x3 atl1e.h 　
16609
 SPI_FLASH_CTRL_CLK_LO_SHIFTSPI_FLASH_CTRL_CLK_LO_SHIFT 20 atl1e.h 　
16610
 SPI_FLASH_CTRL_CLK_HI_MASKSPI_FLASH_CTRL_CLK_HI_MASK 0x3 atl1e.h 　
16611
 SPI_FLASH_CTRL_CLK_HI_SHIFTSPI_FLASH_CTRL_CLK_HI_SHIFT 22 atl1e.h 　
16612
 SPI_FLASH_CTRL_CS_SETUP_MASKSPI_FLASH_CTRL_CS_SETUP_MASK 0x3 atl1e.h 　
16613
 SPI_FLASH_CTRL_CS_SETUP_SHIFTSPI_FLASH_CTRL_CS_SETUP_SHIFT 24 atl1e.h 　
16614
 SPI_FLASH_CTRL_EROM_PGSZ_MASKSPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3 atl1e.h 　
16615
 SPI_FLASH_CTRL_EROM_PGSZ_SHIFTSPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26 atl1e.h 　
16616
 SPI_FLASH_CTRL_WAIT_READYSPI_FLASH_CTRL_WAIT_READY 0x10000000 atl1e.h 　
16617
 REG_SPI_ADDRREG_SPI_ADDR 0x204 atl1e.h 　
16618
 REG_SPI_DATAREG_SPI_DATA 0x208 atl1e.h 　
16619
 REG_SPI_FLASH_CONFIGREG_SPI_FLASH_CONFIG 0x20C atl1e.h 　
16620
 SPI_FLASH_CONFIG_LD_ADDR_MASKSPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF atl1e.h 　
16621
 SPI_FLASH_CONFIG_LD_ADDR_SHIFTSPI_FLASH_CONFIG_LD_ADDR_SHIFT 0 atl1e.h 　
16622
 SPI_FLASH_CONFIG_VPD_ADDR_MASKSPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3 atl1e.h 　
16623
 SPI_FLASH_CONFIG_VPD_ADDR_SHIFTSPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24 atl1e.h 　
16624
 SPI_FLASH_CONFIG_LD_EXISTSPI_FLASH_CONFIG_LD_EXIST 0x4000000 atl1e.h 　
16625
 REG_SPI_FLASH_OP_PROGRAMREG_SPI_FLASH_OP_PROGRAM 0x210 atl1e.h 　
16626
 REG_SPI_FLASH_OP_SC_ERASEREG_SPI_FLASH_OP_SC_ERASE 0x211 atl1e.h 　
16627
 REG_SPI_FLASH_OP_CHIP_ERASEREG_SPI_FLASH_OP_CHIP_ERASE 0x212 atl1e.h 　
16628
 REG_SPI_FLASH_OP_RDIDREG_SPI_FLASH_OP_RDID 0x213 atl1e.h 　
16629
 REG_SPI_FLASH_OP_WRENREG_SPI_FLASH_OP_WREN 0x214 atl1e.h 　
16630
 REG_SPI_FLASH_OP_RDSRREG_SPI_FLASH_OP_RDSR 0x215 atl1e.h 　
16631
 REG_SPI_FLASH_OP_WRSRREG_SPI_FLASH_OP_WRSR 0x216 atl1e.h 　
16632
 REG_SPI_FLASH_OP_READREG_SPI_FLASH_OP_READ 0x217 atl1e.h 　
16633
 REG_TWSI_CTRLREG_TWSI_CTRL 0x218 atl1e.h 　
16634
 TWSI_CTRL_LD_OFFSET_MASKTWSI_CTRL_LD_OFFSET_MASK 0xFF atl1e.h 　
16635
 TWSI_CTRL_LD_OFFSET_SHIFTTWSI_CTRL_LD_OFFSET_SHIFT 0 atl1e.h 　
16636
 TWSI_CTRL_LD_SLV_ADDR_MASKTWSI_CTRL_LD_SLV_ADDR_MASK 0x7 atl1e.h 　
16637
 TWSI_CTRL_LD_SLV_ADDR_SHIFTTWSI_CTRL_LD_SLV_ADDR_SHIFT 8 atl1e.h 　
16638
 TWSI_CTRL_SW_LDSTARTTWSI_CTRL_SW_LDSTART 0x800 atl1e.h 　
16639
 TWSI_CTRL_HW_LDSTARTTWSI_CTRL_HW_LDSTART 0x1000 atl1e.h 　
16640
 TWSI_CTRL_SMB_SLV_ADDR_MASKTWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F atl1e.h 　
16641
 TWSI_CTRL_SMB_SLV_ADDR_SHIFTTWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 atl1e.h 　
16642
 TWSI_CTRL_LD_EXISTTWSI_CTRL_LD_EXIST 0x400000 atl1e.h 　
16643
 TWSI_CTRL_READ_FREQ_SEL_MASKTWSI_CTRL_READ_FREQ_SEL_MASK 0x3 atl1e.h 　
16644
 TWSI_CTRL_READ_FREQ_SEL_SHIFTTWSI_CTRL_READ_FREQ_SEL_SHIFT 23 atl1e.h 　
16645
 TWSI_CTRL_FREQ_SEL_100KTWSI_CTRL_FREQ_SEL_100K 0 atl1e.h 　
16646
 TWSI_CTRL_FREQ_SEL_200KTWSI_CTRL_FREQ_SEL_200K 1 atl1e.h 　
16647
 TWSI_CTRL_FREQ_SEL_300KTWSI_CTRL_FREQ_SEL_300K 2 atl1e.h 　
16648
 TWSI_CTRL_FREQ_SEL_400KTWSI_CTRL_FREQ_SEL_400K 3 atl1e.h 　
16649
 TWSI_CTRL_WRITE_FREQ_SEL_MASKTWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 atl1e.h 　
16650
 TWSI_CTRL_WRITE_FREQ_SEL_SHIFTTWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 atl1e.h 　
16651
 REG_PCIE_DEV_MISC_CTRLREG_PCIE_DEV_MISC_CTRL 0x21C atl1e.h 　
16652
 PCIE_DEV_MISC_CTRL_EXT_PIPEPCIE_DEV_MISC_CTRL_EXT_PIPE 0x2 atl1e.h 　
16653
 PCIE_DEV_MISC_CTRL_RETRY_BUFDISPCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1 atl1e.h 　
16654
 PCIE_DEV_MISC_CTRL_SPIROM_EXISTPCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4 atl1e.h 　
16655
 PCIE_DEV_MISC_CTRL_SERDES_ENDIAPCIE_DEV_MISC_CTRL_SERDES_ENDIA 0x8 atl1e.h 　
16656
 PCIE_DEV_MISC_CTRL_SERDES_SEL_DPCIE_DEV_MISC_CTRL_SERDES_SEL_D 0x10 atl1e.h 　
16657
 REG_PCIE_PHYMISCREG_PCIE_PHYMISC 0x1000 atl1e.h 　
16658
 PCIE_PHYMISC_FORCE_RCV_DETPCIE_PHYMISC_FORCE_RCV_DET 0x4 atl1e.h 　
16659
 REG_LTSSM_TEST_MODEREG_LTSSM_TEST_MODE 0x12FC atl1e.h 　
16660
 LTSSM_TEST_MODE_DEFLTSSM_TEST_MODE_DEF 0xE000 atl1e.h 　
16661
 REG_MASTER_CTRLREG_MASTER_CTRL 0x1400 atl1e.h 　
16662
 MASTER_CTRL_SOFT_RSTMASTER_CTRL_SOFT_RST 0x1 atl1e.h 　
16663
 MASTER_CTRL_MTIMER_ENMASTER_CTRL_MTIMER_EN 0x2 atl1e.h 　
16664
 MASTER_CTRL_ITIMER_ENMASTER_CTRL_ITIMER_EN 0x4 atl1e.h 　
16665
 MASTER_CTRL_MANUAL_INTMASTER_CTRL_MANUAL_INT 0x8 atl1e.h 　
16666
 MASTER_CTRL_ITIMER2_ENMASTER_CTRL_ITIMER2_EN 0x20 atl1e.h 　
16667
 MASTER_CTRL_INT_RDCLRMASTER_CTRL_INT_RDCLR 0x40 atl1e.h 　
16668
 MASTER_CTRL_LED_MODEMASTER_CTRL_LED_MODE 0x200 atl1e.h 　
16669
 MASTER_CTRL_REV_NUM_SHIFTMASTER_CTRL_REV_NUM_SHIFT 16 atl1e.h 　
16670
 MASTER_CTRL_REV_NUM_MASKMASTER_CTRL_REV_NUM_MASK 0xff atl1e.h 　
16671
 MASTER_CTRL_DEV_ID_SHIFTMASTER_CTRL_DEV_ID_SHIFT 24 atl1e.h 　
16672
 MASTER_CTRL_DEV_ID_MASKMASTER_CTRL_DEV_ID_MASK 0xff atl1e.h 　
16673
 REG_MANUAL_TIMER_INITREG_MANUAL_TIMER_INIT 0x1404 atl1e.h 　
16674
 REG_IRQ_MODU_TIMER_INITREG_IRQ_MODU_TIMER_INIT 0x1408 atl1e.h w
16675
 REG_IRQ_MODU_TIMER2_INITREG_IRQ_MODU_TIMER2_INIT 0x140A atl1e.h w
16676
 REG_GPHY_CTRLREG_GPHY_CTRL 0x140C atl1e.h 　
16677
 GPHY_CTRL_EXT_RESETGPHY_CTRL_EXT_RESET 1 atl1e.h 　
16678
 GPHY_CTRL_PIPE_MODGPHY_CTRL_PIPE_MOD 2 atl1e.h 　
16679
 GPHY_CTRL_TEST_MODE_MASKGPHY_CTRL_TEST_MODE_MASK 3 atl1e.h 　
16680
 GPHY_CTRL_TEST_MODE_SHIFTGPHY_CTRL_TEST_MODE_SHIFT 2 atl1e.h 　
16681
 GPHY_CTRL_BERT_STARTGPHY_CTRL_BERT_START 0x10 atl1e.h 　
16682
 GPHY_CTRL_GATE_25M_ENGPHY_CTRL_GATE_25M_EN 0x20 atl1e.h 　
16683
 GPHY_CTRL_LPW_EXITGPHY_CTRL_LPW_EXIT 0x40 atl1e.h 　
16684
 GPHY_CTRL_PHY_IDDQGPHY_CTRL_PHY_IDDQ 0x80 atl1e.h 　
16685
 GPHY_CTRL_PHY_IDDQ_DISGPHY_CTRL_PHY_IDDQ_DIS 0x100 atl1e.h 　
16686
 GPHY_CTRL_PCLK_SEL_DISGPHY_CTRL_PCLK_SEL_DIS 0x200 atl1e.h 　
16687
 GPHY_CTRL_HIB_ENGPHY_CTRL_HIB_EN 0x400 atl1e.h 　
16688
 GPHY_CTRL_HIB_PULSEGPHY_CTRL_HIB_PULSE 0x800 atl1e.h 　
16689
 GPHY_CTRL_SEL_ANA_RSTGPHY_CTRL_SEL_ANA_RST 0x1000 atl1e.h 　
16690
 GPHY_CTRL_PHY_PLL_ONGPHY_CTRL_PHY_PLL_ON 0x2000 atl1e.h 　
16691
 GPHY_CTRL_PWDOWN_HWGPHY_CTRL_PWDOWN_HW 0x4000 atl1e.h 　
16692
 GPHY_CTRL_DEFAULTGPHY_CTRL_DEFAULT (\ GPHY_CTRL_PHY_PLL_ON |\ GPHY_CTRL_SEL_ANA_RST |\ GPHY_CTRL_HIB_PULSE |\ GPHY_CTRL_HIB_EN) atl1e.h 　
16693
 GPHY_CTRL_PW_WOL_DISGPHY_CTRL_PW_WOL_DIS (\ GPHY_CTRL_PHY_PLL_ON |\ GPHY_CTRL_SEL_ANA_RST |\ GPHY_CTRL_HIB_PULSE |\ GPHY_CTRL_HIB_EN |\ GPHY_CTRL_PWDOWN_HW |\ GPHY_CTRL atl1e.h 　
16694
 REG_CMBDISDMA_TIMERREG_CMBDISDMA_TIMER 0x140E atl1e.h 　
16695
 REG_IDLE_STATUSREG_IDLE_STATUS 0x1410 atl1e.h 　
16696
 IDLE_STATUS_RXMACIDLE_STATUS_RXMAC 1 atl1e.h 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling
16697
 IDLE_STATUS_TXMACIDLE_STATUS_TXMAC 2 atl1e.h 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling
16698
 IDLE_STATUS_RXQIDLE_STATUS_RXQ 4 atl1e.h 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling
16699
 IDLE_STATUS_TXQIDLE_STATUS_TXQ 8 atl1e.h 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling
16700
 IDLE_STATUS_DMARIDLE_STATUS_DMAR 0x10 atl1e.h 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling
16701
 IDLE_STATUS_DMAWIDLE_STATUS_DMAW 0x20 atl1e.h 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling
16702
 IDLE_STATUS_SMBIDLE_STATUS_SMB 0x40 atl1e.h 1: SMB state machine is in non-IDLE state. 0: SMB is idling
16703
 IDLE_STATUS_CMBIDLE_STATUS_CMB 0x80 atl1e.h 1: CMB state machine is in non-IDLE state. 0: CMB is idling
16704
 REG_MDIO_CTRLREG_MDIO_CTRL 0x1414 atl1e.h 　
16705
 MDIO_DATA_MASKMDIO_DATA_MASK 0xffff atl1e.h On MDIO write, the 16-bit control data to write to PHY MII management register
16706
 MDIO_DATA_SHIFTMDIO_DATA_SHIFT 0 atl1e.h On MDIO read, the 16-bit status data that was read from the PHY MII management register
16707
 MDIO_REG_ADDR_MASKMDIO_REG_ADDR_MASK 0x1f atl1e.h MDIO register address
16708
 MDIO_REG_ADDR_SHIFTMDIO_REG_ADDR_SHIFT 16 atl1e.h 　
16709
 MDIO_RWMDIO_RW 0x200000 atl1e.h 1: read, 0: write
16710
 MDIO_SUP_PREAMBLEMDIO_SUP_PREAMBLE 0x400000 atl1e.h Suppress preamble
16711
 MDIO_STARTMDIO_START 0x800000 atl1e.h Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle
16712
 MDIO_CLK_SEL_SHIFTMDIO_CLK_SEL_SHIFT 24 atl1e.h 　
16713
 MDIO_CLK_25_4MDIO_CLK_25_4 0 atl1e.h 　
16714
 MDIO_CLK_25_6MDIO_CLK_25_6 2 atl1e.h 　
16715
 MDIO_CLK_25_8MDIO_CLK_25_8 3 atl1e.h 　
16716
 MDIO_CLK_25_10MDIO_CLK_25_10 4 atl1e.h 　
16717
 MDIO_CLK_25_14MDIO_CLK_25_14 5 atl1e.h 　
16718
 MDIO_CLK_25_20MDIO_CLK_25_20 6 atl1e.h 　
16719
 MDIO_CLK_25_28MDIO_CLK_25_28 7 atl1e.h 　
16720
 MDIO_BUSYMDIO_BUSY 0x8000000 atl1e.h 　
16721
 MDIO_AP_ENMDIO_AP_EN 0x10000000 atl1e.h 　
16722
 MDIO_WAIT_TIMESMDIO_WAIT_TIMES 10 atl1e.h 　
16723
 REG_PHY_STATUSREG_PHY_STATUS 0x1418 atl1e.h 　
16724
 PHY_STATUS_100MPHY_STATUS_100M 0x20000 atl1e.h 　
16725
 PHY_STATUS_EMI_CAPHY_STATUS_EMI_CA 0x40000 atl1e.h 　
16726
 REG_BIST0_CTRLREG_BIST0_CTRL 0x141c atl1e.h 　
16727
 BIST0_NOWBIST0_NOW 0x1 atl1e.h 1: To trigger BIST0 logic. This bit stays high during the
16728
 BIST0_SRAM_FAILBIST0_SRAM_FAIL 0x2 atl1e.h 1: The SRAM failure is un-repairable because it has address
16729
 BIST0_FUSE_FLAGBIST0_FUSE_FLAG 0x4 atl1e.h 1: Indicating one cell has been fixed
16730
 REG_BIST1_CTRLREG_BIST1_CTRL 0x1420 atl1e.h 　
16731
 BIST1_NOWBIST1_NOW 0x1 atl1e.h 1: To trigger BIST0 logic. This bit stays high during the
16732
 BIST1_SRAM_FAILBIST1_SRAM_FAIL 0x2 atl1e.h 1: The SRAM failure is un-repairable because it has address
16733
 BIST1_FUSE_FLAGBIST1_FUSE_FLAG 0x4 atl1e.h 　
16734
 REG_SERDES_LOCKREG_SERDES_LOCK 0x1424 atl1e.h 　
16735
 SERDES_LOCK_DETECTSERDES_LOCK_DETECT 1 atl1e.h 1: SerDes lock detected . This signal comes from Analog SerDes
16736
 SERDES_LOCK_DETECT_ENSERDES_LOCK_DETECT_EN 2 atl1e.h 1: Enable SerDes Lock detect function
16737
 REG_MAC_CTRLREG_MAC_CTRL 0x1480 atl1e.h 　
16738
 MAC_CTRL_TX_ENMAC_CTRL_TX_EN 1 atl1e.h 1: Transmit Enable
16739
 MAC_CTRL_RX_ENMAC_CTRL_RX_EN 2 atl1e.h 1: Receive Enable
16740
 MAC_CTRL_TX_FLOWMAC_CTRL_TX_FLOW 4 atl1e.h 1: Transmit Flow Control Enable
16741
 MAC_CTRL_RX_FLOWMAC_CTRL_RX_FLOW 8 atl1e.h 1: Receive Flow Control Enable
16742
 MAC_CTRL_LOOPBACKMAC_CTRL_LOOPBACK 0x10 atl1e.h 1: Loop back at G/MII Interface
16743
 MAC_CTRL_DUPLXMAC_CTRL_DUPLX 0x20 atl1e.h 1: Full-duplex mode 0: Half-duplex mode
16744
 MAC_CTRL_ADD_CRCMAC_CTRL_ADD_CRC 0x40 atl1e.h 1: Instruct MAC to attach CRC on all egress Ethernet frames
16745
 MAC_CTRL_PADMAC_CTRL_PAD 0x80 atl1e.h 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN
16746
 MAC_CTRL_LENCHKMAC_CTRL_LENCHK 0x100 atl1e.h 1: Instruct MAC to check if length field matches the real packet length
16747
 MAC_CTRL_HUGE_ENMAC_CTRL_HUGE_EN 0x200 atl1e.h 1: receive Jumbo frame enable
16748
 MAC_CTRL_PRMLEN_SHIFTMAC_CTRL_PRMLEN_SHIFT 10 atl1e.h Preamble length
16749
 MAC_CTRL_PRMLEN_MASKMAC_CTRL_PRMLEN_MASK 0xf atl1e.h 　
16750
 MAC_CTRL_RMV_VLANMAC_CTRL_RMV_VLAN 0x4000 atl1e.h 1: to remove VLAN Tag automatically from all receive packets
16751
 MAC_CTRL_PROMIS_ENMAC_CTRL_PROMIS_EN 0x8000 atl1e.h 1: Promiscuous Mode Enable
16752
 MAC_CTRL_TX_PAUSEMAC_CTRL_TX_PAUSE 0x10000 atl1e.h 1: transmit test pause
16753
 MAC_CTRL_SCNTMAC_CTRL_SCNT 0x20000 atl1e.h 1: shortcut slot time counter
16754
 MAC_CTRL_SRST_TXMAC_CTRL_SRST_TX 0x40000 atl1e.h 1: synchronized reset Transmit MAC module
16755
 MAC_CTRL_TX_SIMURSTMAC_CTRL_TX_SIMURST 0x80000 atl1e.h 1: transmit simulation reset
16756
 MAC_CTRL_SPEED_SHIFTMAC_CTRL_SPEED_SHIFT 20 atl1e.h 10: gigabit 01:10M/100M
16757
 MAC_CTRL_SPEED_MASKMAC_CTRL_SPEED_MASK 0x300000 atl1e.h 　
16758
 MAC_CTRL_SPEED_1000MAC_CTRL_SPEED_1000 2 atl1e.h 　
16759
 MAC_CTRL_SPEED_10_100MAC_CTRL_SPEED_10_100 1 atl1e.h 　
16760
 MAC_CTRL_DBG_TX_BKPRESUREMAC_CTRL_DBG_TX_BKPRESURE 0x400000 atl1e.h 1: transmit maximum backoff (half-duplex test bit)
16761
 MAC_CTRL_TX_HUGEMAC_CTRL_TX_HUGE 0x800000 atl1e.h 1: transmit huge enable
16762
 MAC_CTRL_RX_CHKSUM_ENMAC_CTRL_RX_CHKSUM_EN 0x1000000 atl1e.h 1: RX checksum enable
16763
 MAC_CTRL_MC_ALL_ENMAC_CTRL_MC_ALL_EN 0x2000000 atl1e.h 1: upload all multicast frame without error to system
16764
 MAC_CTRL_BC_ENMAC_CTRL_BC_EN 0x4000000 atl1e.h 1: upload all broadcast frame without error to system
16765
 MAC_CTRL_DBGMAC_CTRL_DBG 0x8000000 atl1e.h 1: upload all received frame to system (Debug Mode)
16766
 REG_MAC_IPG_IFGREG_MAC_IPG_IFG 0x1484 atl1e.h 　
16767
 MAC_IPG_IFG_IPGT_SHIFTMAC_IPG_IFG_IPGT_SHIFT 0 atl1e.h Desired back to back inter-packet gap. The default is 96-bit time
16768
 MAC_IPG_IFG_IPGT_MASKMAC_IPG_IFG_IPGT_MASK 0x7f atl1e.h 　
16769
 MAC_IPG_IFG_MIFG_SHIFTMAC_IPG_IFG_MIFG_SHIFT 8 atl1e.h Minimum number of IFG to enforce in between RX frames
16770
 MAC_IPG_IFG_MIFG_MASKMAC_IPG_IFG_MIFG_MASK 0xff atl1e.h Frame gap below such IFP is dropped
16771
 MAC_IPG_IFG_IPGR1_SHIFTMAC_IPG_IFG_IPGR1_SHIFT 16 atl1e.h 64bit Carrier-Sense window
16772
 MAC_IPG_IFG_IPGR1_MASKMAC_IPG_IFG_IPGR1_MASK 0x7f atl1e.h 　
16773
 MAC_IPG_IFG_IPGR2_SHIFTMAC_IPG_IFG_IPGR2_SHIFT 24 atl1e.h 96-bit IPG window
16774
 MAC_IPG_IFG_IPGR2_MASKMAC_IPG_IFG_IPGR2_MASK 0x7f atl1e.h 　
16775
 REG_MAC_STA_ADDRREG_MAC_STA_ADDR 0x1488 atl1e.h 　
16776
 REG_RX_HASH_TABLEREG_RX_HASH_TABLE 0x1490 atl1e.h 　
16777
 REG_MAC_HALF_DUPLX_CTRLREG_MAC_HALF_DUPLX_CTRL 0x1498 atl1e.h 　
16778
 MAC_HALF_DUPLX_CTRL_LCOL_SHIFTMAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 atl1e.h Collision Window
16779
 MAC_HALF_DUPLX_CTRL_LCOL_MASKMAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff atl1e.h 　
16780
 MAC_HALF_DUPLX_CTRL_RETRY_SHIFTMAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 atl1e.h Retransmission maximum, afterwards the packet will be discarded
16781
 MAC_HALF_DUPLX_CTRL_RETRY_MASKMAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf atl1e.h 　
16782
 MAC_HALF_DUPLX_CTRL_EXC_DEF_ENMAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 atl1e.h 1: Allow the transmission of a packet which has been excessively deferred
16783
 MAC_HALF_DUPLX_CTRL_NO_BACK_CMAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 atl1e.h 1: No back-off on collision, immediately start the retransmission
16784
 MAC_HALF_DUPLX_CTRL_NO_BACK_PMAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 atl1e.h 1: No back-off on backpressure, immediately start the transmission after back pressure
16785
 MAC_HALF_DUPLX_CTRL_ABEBEMAC_HALF_DUPLX_CTRL_ABEBE 0x80000 atl1e.h 1: Alternative Binary Exponential Back-off Enabled
16786
 MAC_HALF_DUPLX_CTRL_ABEBT_SHIFTMAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 atl1e.h Maximum binary exponential number
16787
 MAC_HALF_DUPLX_CTRL_ABEBT_MASKMAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf atl1e.h 　
16788
 MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFMAC_HALF_DUPLX_CTRL_JAMIPG_SHIF 24 atl1e.h IPG to start JAM for collision based flow control in half-duplex
16789
 MAC_HALF_DUPLX_CTRL_JAMIPG_MASKMAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf atl1e.h mode. In unit of 8-bit time
16790
 REG_MTUREG_MTU 0x149c atl1e.h 　
16791
 REG_WOL_CTRLREG_WOL_CTRL 0x14a0 atl1e.h 　
16792
 WOL_PATTERN_ENWOL_PATTERN_EN 0x00000001 atl1e.h 　
16793
 WOL_PATTERN_PME_ENWOL_PATTERN_PME_EN 0x00000002 atl1e.h 　
16794
 WOL_MAGIC_ENWOL_MAGIC_EN 0x00000004 atl1e.h 　
16795
 WOL_MAGIC_PME_ENWOL_MAGIC_PME_EN 0x00000008 atl1e.h 　
16796
 WOL_LINK_CHG_ENWOL_LINK_CHG_EN 0x00000010 atl1e.h 　
16797
 WOL_LINK_CHG_PME_ENWOL_LINK_CHG_PME_EN 0x00000020 atl1e.h 　
16798
 WOL_PATTERN_STWOL_PATTERN_ST 0x00000100 atl1e.h 　
16799
 WOL_MAGIC_STWOL_MAGIC_ST 0x00000200 atl1e.h 　
16800
 WOL_LINKCHG_STWOL_LINKCHG_ST 0x00000400 atl1e.h 　
16801
 WOL_CLK_SWITCH_ENWOL_CLK_SWITCH_EN 0x00008000 atl1e.h 　
16802
 WOL_PT0_ENWOL_PT0_EN 0x00010000 atl1e.h 　
16803
 WOL_PT1_ENWOL_PT1_EN 0x00020000 atl1e.h 　
16804
 WOL_PT2_ENWOL_PT2_EN 0x00040000 atl1e.h 　
16805
 WOL_PT3_ENWOL_PT3_EN 0x00080000 atl1e.h 　
16806
 WOL_PT4_ENWOL_PT4_EN 0x00100000 atl1e.h 　
16807
 WOL_PT5_ENWOL_PT5_EN 0x00200000 atl1e.h 　
16808
 WOL_PT6_ENWOL_PT6_EN 0x00400000 atl1e.h 　
16809
 REG_WOL_PATTERN_LENREG_WOL_PATTERN_LEN 0x14a4 atl1e.h 　
16810
 WOL_PT_LEN_MASKWOL_PT_LEN_MASK 0x7f atl1e.h 　
16811
 WOL_PT0_LEN_SHIFTWOL_PT0_LEN_SHIFT 0 atl1e.h 　
16812
 WOL_PT1_LEN_SHIFTWOL_PT1_LEN_SHIFT 8 atl1e.h 　
16813
 WOL_PT2_LEN_SHIFTWOL_PT2_LEN_SHIFT 16 atl1e.h 　
16814
 WOL_PT3_LEN_SHIFTWOL_PT3_LEN_SHIFT 24 atl1e.h 　
16815
 WOL_PT4_LEN_SHIFTWOL_PT4_LEN_SHIFT 0 atl1e.h 　
16816
 WOL_PT5_LEN_SHIFTWOL_PT5_LEN_SHIFT 8 atl1e.h 　
16817
 WOL_PT6_LEN_SHIFTWOL_PT6_LEN_SHIFT 16 atl1e.h 　
16818
 REG_SRAM_TRD_ADDRREG_SRAM_TRD_ADDR 0x1518 atl1e.h 　
16819
 REG_SRAM_TRD_LENREG_SRAM_TRD_LEN 0x151C atl1e.h 　
16820
 REG_SRAM_RXF_ADDRREG_SRAM_RXF_ADDR 0x1520 atl1e.h 　
16821
 REG_SRAM_RXF_LENREG_SRAM_RXF_LEN 0x1524 atl1e.h 　
16822
 REG_SRAM_TXF_ADDRREG_SRAM_TXF_ADDR 0x1528 atl1e.h 　
16823
 REG_SRAM_TXF_LENREG_SRAM_TXF_LEN 0x152C atl1e.h 　
16824
 REG_SRAM_TCPH_ADDRREG_SRAM_TCPH_ADDR 0x1530 atl1e.h 　
16825
 REG_SRAM_PKTH_ADDRREG_SRAM_PKTH_ADDR 0x1532 atl1e.h 　
16826
 REG_LOAD_PTRREG_LOAD_PTR 0x1534 atl1e.h Software sets this bit after the initialization of the head and tail
16827
 REG_RXF3_BASE_ADDR_HIREG_RXF3_BASE_ADDR_HI 0x153C atl1e.h 　
16828
 REG_DESC_BASE_ADDR_HIREG_DESC_BASE_ADDR_HI 0x1540 atl1e.h 　
16829
 REG_RXF0_BASE_ADDR_HIREG_RXF0_BASE_ADDR_HI 0x1540 atl1e.h share with DESC BASE ADDR HI
16830
 REG_HOST_RXF0_PAGE0_LOREG_HOST_RXF0_PAGE0_LO 0x1544 atl1e.h 　
16831
 REG_HOST_RXF0_PAGE1_LOREG_HOST_RXF0_PAGE1_LO 0x1548 atl1e.h 　
16832
 REG_TPD_BASE_ADDR_LOREG_TPD_BASE_ADDR_LO 0x154C atl1e.h 　
16833
 REG_RXF1_BASE_ADDR_HIREG_RXF1_BASE_ADDR_HI 0x1550 atl1e.h 　
16834
 REG_RXF2_BASE_ADDR_HIREG_RXF2_BASE_ADDR_HI 0x1554 atl1e.h 　
16835
 REG_HOST_RXFPAGE_SIZEREG_HOST_RXFPAGE_SIZE 0x1558 atl1e.h 　
16836
 REG_TPD_RING_SIZEREG_TPD_RING_SIZE 0x155C atl1e.h 　
16837
 REG_RSS_KEY0REG_RSS_KEY0 0x14B0 atl1e.h 　
16838
 REG_RSS_KEY1REG_RSS_KEY1 0x14B4 atl1e.h 　
16839
 REG_RSS_KEY2REG_RSS_KEY2 0x14B8 atl1e.h 　
16840
 REG_RSS_KEY3REG_RSS_KEY3 0x14BC atl1e.h 　
16841
 REG_RSS_KEY4REG_RSS_KEY4 0x14C0 atl1e.h 　
16842
 REG_RSS_KEY5REG_RSS_KEY5 0x14C4 atl1e.h 　
16843
 REG_RSS_KEY6REG_RSS_KEY6 0x14C8 atl1e.h 　
16844
 REG_RSS_KEY7REG_RSS_KEY7 0x14CC atl1e.h 　
16845
 REG_RSS_KEY8REG_RSS_KEY8 0x14D0 atl1e.h 　
16846
 REG_RSS_KEY9REG_RSS_KEY9 0x14D4 atl1e.h 　
16847
 REG_IDT_TABLE4REG_IDT_TABLE4 0x14E0 atl1e.h 　
16848
 REG_IDT_TABLE5REG_IDT_TABLE5 0x14E4 atl1e.h 　
16849
 REG_IDT_TABLE6REG_IDT_TABLE6 0x14E8 atl1e.h 　
16850
 REG_IDT_TABLE7REG_IDT_TABLE7 0x14EC atl1e.h 　
16851
 REG_IDT_TABLE0REG_IDT_TABLE0 0x1560 atl1e.h 　
16852
 REG_IDT_TABLE1REG_IDT_TABLE1 0x1564 atl1e.h 　
16853
 REG_IDT_TABLE2REG_IDT_TABLE2 0x1568 atl1e.h 　
16854
 REG_IDT_TABLE3REG_IDT_TABLE3 0x156C atl1e.h 　
16855
 REG_IDT_TABLEREG_IDT_TABLE REG_IDT_TABLE0 atl1e.h 　
16856
 REG_RSS_HASH_VALUEREG_RSS_HASH_VALUE 0x1570 atl1e.h 　
16857
 REG_RSS_HASH_FLAGREG_RSS_HASH_FLAG 0x1574 atl1e.h 　
16858
 REG_BASE_CPU_NUMBERREG_BASE_CPU_NUMBER 0x157C atl1e.h 　
16859
 REG_TXQ_CTRLREG_TXQ_CTRL 0x1580 atl1e.h 　
16860
 TXQ_CTRL_NUM_TPD_BURST_MASKTXQ_CTRL_NUM_TPD_BURST_MASK 0xF atl1e.h 　
16861
 TXQ_CTRL_NUM_TPD_BURST_SHIFTTXQ_CTRL_NUM_TPD_BURST_SHIFT 0 atl1e.h 　
16862
 TXQ_CTRL_ENTXQ_CTRL_EN 0x20 atl1e.h 1: Enable TXQ
16863
 TXQ_CTRL_ENH_MODETXQ_CTRL_ENH_MODE 0x40 atl1e.h Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched.
16864
 TXQ_CTRL_TXF_BURST_NUM_SHIFTTXQ_CTRL_TXF_BURST_NUM_SHIFT 16 atl1e.h Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length.
16865
 TXQ_CTRL_TXF_BURST_NUM_MASKTXQ_CTRL_TXF_BURST_NUM_MASK 0xffff atl1e.h 　
16866
 REG_TX_EARLY_THREG_TX_EARLY_TH 0x1584 atl1e.h Jumbo frame threshold in QWORD unit. Packet greater than
16867
 TX_TX_EARLY_TH_MASKTX_TX_EARLY_TH_MASK 0x7ff atl1e.h 　
16868
 TX_TX_EARLY_TH_SHIFTTX_TX_EARLY_TH_SHIFT 0 atl1e.h 　
16869
 REG_RXQ_CTRLREG_RXQ_CTRL 0x15A0 atl1e.h 　
16870
 RXQ_CTRL_PBA_ALIGN_32RXQ_CTRL_PBA_ALIGN_32 0 atl1e.h rx-packet alignment
16871
 RXQ_CTRL_PBA_ALIGN_64RXQ_CTRL_PBA_ALIGN_64 1 atl1e.h 　
16872
 RXQ_CTRL_PBA_ALIGN_128RXQ_CTRL_PBA_ALIGN_128 2 atl1e.h 　
16873
 RXQ_CTRL_PBA_ALIGN_256RXQ_CTRL_PBA_ALIGN_256 3 atl1e.h 　
16874
 RXQ_CTRL_Q1_ENRXQ_CTRL_Q1_EN 0x10 atl1e.h 　
16875
 RXQ_CTRL_Q2_ENRXQ_CTRL_Q2_EN 0x20 atl1e.h 　
16876
 RXQ_CTRL_Q3_ENRXQ_CTRL_Q3_EN 0x40 atl1e.h 　
16877
 RXQ_CTRL_IPV6_XSUM_VERIFY_ENRXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80 atl1e.h 　
16878
 RXQ_CTRL_HASH_TLEN_SHIFTRXQ_CTRL_HASH_TLEN_SHIFT 8 atl1e.h 　
16879
 RXQ_CTRL_HASH_TLEN_MASKRXQ_CTRL_HASH_TLEN_MASK 0xFF atl1e.h 　
16880
 RXQ_CTRL_HASH_TYPE_IPV4RXQ_CTRL_HASH_TYPE_IPV4 0x10000 atl1e.h 　
16881
 RXQ_CTRL_HASH_TYPE_IPV4_TCPRXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000 atl1e.h 　
16882
 RXQ_CTRL_HASH_TYPE_IPV6RXQ_CTRL_HASH_TYPE_IPV6 0x40000 atl1e.h 　
16883
 RXQ_CTRL_HASH_TYPE_IPV6_TCPRXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000 atl1e.h 　
16884
 RXQ_CTRL_RSS_MODE_DISABLERXQ_CTRL_RSS_MODE_DISABLE 0 atl1e.h 　
16885
 RXQ_CTRL_RSS_MODE_SQSINTRXQ_CTRL_RSS_MODE_SQSINT 0x4000000 atl1e.h 　
16886
 RXQ_CTRL_RSS_MODE_MQUESINTRXQ_CTRL_RSS_MODE_MQUESINT 0x8000000 atl1e.h 　
16887
 RXQ_CTRL_RSS_MODE_MQUEMINTRXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000 atl1e.h 　
16888
 RXQ_CTRL_NIP_QUEUE_SEL_TBLRXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000 atl1e.h 　
16889
 RXQ_CTRL_HASH_ENABLERXQ_CTRL_HASH_ENABLE 0x20000000 atl1e.h 　
16890
 RXQ_CTRL_CUT_THRU_ENRXQ_CTRL_CUT_THRU_EN 0x40000000 atl1e.h 　
16891
 RXQ_CTRL_ENRXQ_CTRL_EN 0x80000000 atl1e.h 　
16892
 REG_RXQ_JMBOSZ_RRDTIMREG_RXQ_JMBOSZ_RRDTIM 0x15A4 atl1e.h 　
16893
 RXQ_JMBOSZ_TH_MASKRXQ_JMBOSZ_TH_MASK 0x7ff atl1e.h 　
16894
 RXQ_JMBOSZ_TH_SHIFTRXQ_JMBOSZ_TH_SHIFT 0 atl1e.h RRD retirement timer. Decrement by 1 after every 512ns passes
16895
 RXQ_JMBO_LKAH_MASKRXQ_JMBO_LKAH_MASK 0xf atl1e.h 　
16896
 RXQ_JMBO_LKAH_SHIFTRXQ_JMBO_LKAH_SHIFT 11 atl1e.h 　
16897
 REG_RXQ_RXF_PAUSE_THRESHREG_RXQ_RXF_PAUSE_THRESH 0x15A8 atl1e.h 　
16898
 RXQ_RXF_PAUSE_TH_HI_SHIFTRXQ_RXF_PAUSE_TH_HI_SHIFT 0 atl1e.h 　
16899
 RXQ_RXF_PAUSE_TH_HI_MASKRXQ_RXF_PAUSE_TH_HI_MASK 0xfff atl1e.h 　
16900
 RXQ_RXF_PAUSE_TH_LO_SHIFTRXQ_RXF_PAUSE_TH_LO_SHIFT 16 atl1e.h 　
16901
 RXQ_RXF_PAUSE_TH_LO_MASKRXQ_RXF_PAUSE_TH_LO_MASK 0xfff atl1e.h 　
16902
 REG_DMA_CTRLREG_DMA_CTRL 0x15C0 atl1e.h 　
16903
 DMA_CTRL_DMAR_IN_ORDERDMA_CTRL_DMAR_IN_ORDER 0x1 atl1e.h 　
16904
 DMA_CTRL_DMAR_ENH_ORDERDMA_CTRL_DMAR_ENH_ORDER 0x2 atl1e.h 　
16905
 DMA_CTRL_DMAR_OUT_ORDERDMA_CTRL_DMAR_OUT_ORDER 0x4 atl1e.h 　
16906
 DMA_CTRL_RCB_VALUEDMA_CTRL_RCB_VALUE 0x8 atl1e.h 　
16907
 DMA_CTRL_DMAR_BURST_LEN_SHIFTDMA_CTRL_DMAR_BURST_LEN_SHIFT 4 atl1e.h 　
16908
 DMA_CTRL_DMAR_BURST_LEN_MASKDMA_CTRL_DMAR_BURST_LEN_MASK 7 atl1e.h 　
16909
 DMA_CTRL_DMAW_BURST_LEN_SHIFTDMA_CTRL_DMAW_BURST_LEN_SHIFT 7 atl1e.h 　
16910
 DMA_CTRL_DMAW_BURST_LEN_MASKDMA_CTRL_DMAW_BURST_LEN_MASK 7 atl1e.h 　
16911
 DMA_CTRL_DMAR_REQ_PRIDMA_CTRL_DMAR_REQ_PRI 0x400 atl1e.h 　
16912
 DMA_CTRL_DMAR_DLY_CNT_MASKDMA_CTRL_DMAR_DLY_CNT_MASK 0x1F atl1e.h 　
16913
 DMA_CTRL_DMAR_DLY_CNT_SHIFTDMA_CTRL_DMAR_DLY_CNT_SHIFT 11 atl1e.h 　
16914
 DMA_CTRL_DMAW_DLY_CNT_MASKDMA_CTRL_DMAW_DLY_CNT_MASK 0xF atl1e.h 　
16915
 DMA_CTRL_DMAW_DLY_CNT_SHIFTDMA_CTRL_DMAW_DLY_CNT_SHIFT 16 atl1e.h 　
16916
 DMA_CTRL_TXCMB_ENDMA_CTRL_TXCMB_EN 0x100000 atl1e.h 　
16917
 DMA_CTRL_RXCMB_ENDMA_CTRL_RXCMB_EN 0x200000 atl1e.h 　
16918
 REG_SMB_STAT_TIMERREG_SMB_STAT_TIMER 0x15C4 atl1e.h 　
16919
 REG_TRIG_RRD_THRESHREG_TRIG_RRD_THRESH 0x15CA atl1e.h 　
16920
 REG_TRIG_TPD_THRESHREG_TRIG_TPD_THRESH 0x15C8 atl1e.h 　
16921
 REG_TRIG_TXTIMERREG_TRIG_TXTIMER 0x15CC atl1e.h 　
16922
 REG_TRIG_RXTIMERREG_TRIG_RXTIMER 0x15CE atl1e.h 　
16923
 REG_HOST_RXF1_PAGE0_LOREG_HOST_RXF1_PAGE0_LO 0x15D0 atl1e.h 　
16924
 REG_HOST_RXF1_PAGE1_LOREG_HOST_RXF1_PAGE1_LO 0x15D4 atl1e.h 　
16925
 REG_HOST_RXF2_PAGE0_LOREG_HOST_RXF2_PAGE0_LO 0x15D8 atl1e.h 　
16926
 REG_HOST_RXF2_PAGE1_LOREG_HOST_RXF2_PAGE1_LO 0x15DC atl1e.h 　
16927
 REG_HOST_RXF3_PAGE0_LOREG_HOST_RXF3_PAGE0_LO 0x15E0 atl1e.h 　
16928
 REG_HOST_RXF3_PAGE1_LOREG_HOST_RXF3_PAGE1_LO 0x15E4 atl1e.h 　
16929
 REG_MB_RXF1_RADDRREG_MB_RXF1_RADDR 0x15B4 atl1e.h 　
16930
 REG_MB_RXF2_RADDRREG_MB_RXF2_RADDR 0x15B8 atl1e.h 　
16931
 REG_MB_RXF3_RADDRREG_MB_RXF3_RADDR 0x15BC atl1e.h 　
16932
 REG_MB_TPD_PROD_IDXREG_MB_TPD_PROD_IDX 0x15F0 atl1e.h 　
16933
 REG_HOST_RXF0_PAGE0_VLDREG_HOST_RXF0_PAGE0_VLD 0x15F4 atl1e.h 　
16934
 HOST_RXF_VALIDHOST_RXF_VALID 1 atl1e.h 　
16935
 HOST_RXF_PAGENO_SHIFTHOST_RXF_PAGENO_SHIFT 1 atl1e.h 　
16936
 HOST_RXF_PAGENO_MASKHOST_RXF_PAGENO_MASK 0x7F atl1e.h 　
16937
 REG_HOST_RXF0_PAGE1_VLDREG_HOST_RXF0_PAGE1_VLD 0x15F5 atl1e.h 　
16938
 REG_HOST_RXF1_PAGE0_VLDREG_HOST_RXF1_PAGE0_VLD 0x15F6 atl1e.h 　
16939
 REG_HOST_RXF1_PAGE1_VLDREG_HOST_RXF1_PAGE1_VLD 0x15F7 atl1e.h 　
16940
 REG_HOST_RXF2_PAGE0_VLDREG_HOST_RXF2_PAGE0_VLD 0x15F8 atl1e.h 　
16941
 REG_HOST_RXF2_PAGE1_VLDREG_HOST_RXF2_PAGE1_VLD 0x15F9 atl1e.h 　
16942
 REG_HOST_RXF3_PAGE0_VLDREG_HOST_RXF3_PAGE0_VLD 0x15FA atl1e.h 　
16943
 REG_HOST_RXF3_PAGE1_VLDREG_HOST_RXF3_PAGE1_VLD 0x15FB atl1e.h 　
16944
 REG_ISRREG_ISR 0x1600 atl1e.h 　
16945
 ISR_SMBISR_SMB 1 atl1e.h 　
16946
 ISR_TIMERISR_TIMER 2 atl1e.h Interrupt when Timer is counted down to zero
16947
 ISR_MANUALISR_MANUAL 4 atl1e.h 　
16948
 ISR_HW_RXF_OVISR_HW_RXF_OV 8 atl1e.h RXF overflow interrupt
16949
 ISR_HOST_RXF0_OVISR_HOST_RXF0_OV 0x10 atl1e.h 　
16950
 ISR_HOST_RXF1_OVISR_HOST_RXF1_OV 0x20 atl1e.h 　
16951
 ISR_HOST_RXF2_OVISR_HOST_RXF2_OV 0x40 atl1e.h 　
16952
 ISR_HOST_RXF3_OVISR_HOST_RXF3_OV 0x80 atl1e.h 　
16953
 ISR_TXF_UNISR_TXF_UN 0x100 atl1e.h 　
16954
 ISR_RX0_PAGE_FULLISR_RX0_PAGE_FULL 0x200 atl1e.h 　
16955
 ISR_DMAR_TO_RSTISR_DMAR_TO_RST 0x400 atl1e.h 　
16956
 ISR_DMAW_TO_RSTISR_DMAW_TO_RST 0x800 atl1e.h 　
16957
 ISR_GPHYISR_GPHY 0x1000 atl1e.h 　
16958
 ISR_TX_CREDITISR_TX_CREDIT 0x2000 atl1e.h 　
16959
 ISR_GPHY_LPWISR_GPHY_LPW 0x4000 atl1e.h GPHY low power state interrupt
16960
 ISR_RX_PKTISR_RX_PKT 0x10000 atl1e.h One packet received, triggered by RFD
16961
 ISR_TX_PKTISR_TX_PKT 0x20000 atl1e.h One packet transmitted, triggered by TPD
16962
 ISR_TX_DMAISR_TX_DMA 0x40000 atl1e.h 　
16963
 ISR_RX_PKT_1ISR_RX_PKT_1 0x80000 atl1e.h 　
16964
 ISR_RX_PKT_2ISR_RX_PKT_2 0x100000 atl1e.h 　
16965
 ISR_RX_PKT_3ISR_RX_PKT_3 0x200000 atl1e.h 　
16966
 ISR_MAC_RXISR_MAC_RX 0x400000 atl1e.h 　
16967
 ISR_MAC_TXISR_MAC_TX 0x800000 atl1e.h 　
16968
 ISR_UR_DETECTEDISR_UR_DETECTED 0x1000000 atl1e.h 　
16969
 ISR_FERR_DETECTEDISR_FERR_DETECTED 0x2000000 atl1e.h 　
16970
 ISR_NFERR_DETECTEDISR_NFERR_DETECTED 0x4000000 atl1e.h 　
16971
 ISR_CERR_DETECTEDISR_CERR_DETECTED 0x8000000 atl1e.h 　
16972
 ISR_PHY_LINKDOWNISR_PHY_LINKDOWN 0x10000000 atl1e.h 　
16973
 ISR_DIS_INTISR_DIS_INT 0x80000000 atl1e.h 　
16974
 REG_IMRREG_IMR 0x1604 atl1e.h 　
16975
 IMR_NORMAL_MASKIMR_NORMAL_MASK (\ ISR_SMB |\ ISR_TXF_UN |\ ISR_HW_RXF_OV |\ ISR_HOST_RXF0_OV|\ ISR_MANUAL |\ ISR_GPHY |\ ISR_GPHY_L atl1e.h 　
16976
 ISR_TX_EVENTISR_TX_EVENT (ISR_TXF_UN | ISR_TX_PKT) atl1e.h 　
16977
 ISR_RX_EVENTISR_RX_EVENT (ISR_HOST_RXF0_OV | ISR_HW_RXF_OV | ISR_RX_PKT) atl1e.h 　
16978
 REG_MAC_RX_STATUS_BINREG_MAC_RX_STATUS_BIN 0x1700 atl1e.h 　
16979
 REG_MAC_RX_STATUS_ENDREG_MAC_RX_STATUS_END 0x175c atl1e.h 　
16980
 REG_MAC_TX_STATUS_BINREG_MAC_TX_STATUS_BIN 0x1760 atl1e.h 　
16981
 REG_MAC_TX_STATUS_ENDREG_MAC_TX_STATUS_END 0x17c0 atl1e.h 　
16982
 REG_HOST_RXF0_PAGEOFFREG_HOST_RXF0_PAGEOFF 0x1800 atl1e.h 　
16983
 REG_TPD_CONS_IDXREG_TPD_CONS_IDX 0x1804 atl1e.h 　
16984
 REG_HOST_RXF1_PAGEOFFREG_HOST_RXF1_PAGEOFF 0x1808 atl1e.h 　
16985
 REG_HOST_RXF2_PAGEOFFREG_HOST_RXF2_PAGEOFF 0x180C atl1e.h 　
16986
 REG_HOST_RXF3_PAGEOFFREG_HOST_RXF3_PAGEOFF 0x1810 atl1e.h 　
16987
 REG_HOST_RXF0_MB0_LOREG_HOST_RXF0_MB0_LO 0x1820 atl1e.h 　
16988
 REG_HOST_RXF0_MB1_LOREG_HOST_RXF0_MB1_LO 0x1824 atl1e.h 　
16989
 REG_HOST_RXF1_MB0_LOREG_HOST_RXF1_MB0_LO 0x1828 atl1e.h 　
16990
 REG_HOST_RXF1_MB1_LOREG_HOST_RXF1_MB1_LO 0x182C atl1e.h 　
16991
 REG_HOST_RXF2_MB0_LOREG_HOST_RXF2_MB0_LO 0x1830 atl1e.h 　
16992
 REG_HOST_RXF2_MB1_LOREG_HOST_RXF2_MB1_LO 0x1834 atl1e.h 　
16993
 REG_HOST_RXF3_MB0_LOREG_HOST_RXF3_MB0_LO 0x1838 atl1e.h 　
16994
 REG_HOST_RXF3_MB1_LOREG_HOST_RXF3_MB1_LO 0x183C atl1e.h 　
16995
 REG_HOST_TX_CMB_LOREG_HOST_TX_CMB_LO 0x1840 atl1e.h 　
16996
 REG_HOST_SMB_ADDR_LOREG_HOST_SMB_ADDR_LO 0x1844 atl1e.h 　
16997
 REG_DEBUG_DATA0REG_DEBUG_DATA0 0x1900 atl1e.h 　
16998
 REG_DEBUG_DATA1REG_DEBUG_DATA1 0x1904 atl1e.h 　
16999
 MII_BMCRMII_BMCR 0x00 atl1e.h 　
17000
 MII_BMSRMII_BMSR 0x01 atl1e.h 　
17001
 MII_PHYSID1MII_PHYSID1 0x02 atl1e.h 　
17002
 MII_PHYSID2MII_PHYSID2 0x03 atl1e.h 　
17003
 MII_ADVERTISEMII_ADVERTISE 0x04 atl1e.h 　
17004
 MII_LPAMII_LPA 0x05 atl1e.h 　
17005
 MII_EXPANSIONMII_EXPANSION 0x06 atl1e.h 　
17006
 MII_AT001_CRMII_AT001_CR 0x09 atl1e.h 　
17007
 MII_AT001_SRMII_AT001_SR 0x0A atl1e.h 　
17008
 MII_AT001_ESRMII_AT001_ESR 0x0F atl1e.h 　
17009
 MII_AT001_PSCRMII_AT001_PSCR 0x10 atl1e.h 　
17010
 MII_AT001_PSSRMII_AT001_PSSR 0x11 atl1e.h 　
17011
 MII_INT_CTRLMII_INT_CTRL 0x12 atl1e.h 　
17012
 MII_INT_STATUSMII_INT_STATUS 0x13 atl1e.h 　
17013
 MII_SMARTSPEEDMII_SMARTSPEED 0x14 atl1e.h 　
17014
 MII_RERRCOUNTERMII_RERRCOUNTER 0x15 atl1e.h 　
17015
 MII_SREVISIONMII_SREVISION 0x16 atl1e.h 　
17016
 MII_RESV1MII_RESV1 0x17 atl1e.h 　
17017
 MII_LBRERRORMII_LBRERROR 0x18 atl1e.h 　
17018
 MII_PHYADDRMII_PHYADDR 0x19 atl1e.h 　
17019
 MII_RESV2MII_RESV2 0x1a atl1e.h 　
17020
 MII_TPISTATUSMII_TPISTATUS 0x1b atl1e.h 　
17021
 MII_NCONFIGMII_NCONFIG 0x1c atl1e.h 　
17022
 MII_DBG_ADDRMII_DBG_ADDR 0x1D atl1e.h 　
17023
 MII_DBG_DATAMII_DBG_DATA 0x1E atl1e.h 　
17024
 MII_CR_SPEED_SELECT_MSBMII_CR_SPEED_SELECT_MSB 0x0040 atl1e.h bits 6,13: 10=1000, 01=100, 00=10
17025
 MII_CR_COLL_TEST_ENABLEMII_CR_COLL_TEST_ENABLE 0x0080 atl1e.h Collision test enable
17026
 MII_CR_FULL_DUPLEXMII_CR_FULL_DUPLEX 0x0100 atl1e.h FDX =1, half duplex =0
17027
 MII_CR_RESTART_AUTO_NEGMII_CR_RESTART_AUTO_NEG 0x0200 atl1e.h Restart auto negotiation
17028
 MII_CR_ISOLATEMII_CR_ISOLATE 0x0400 atl1e.h Isolate PHY from MII
17029
 MII_CR_POWER_DOWNMII_CR_POWER_DOWN 0x0800 atl1e.h Power down
17030
 MII_CR_AUTO_NEG_ENMII_CR_AUTO_NEG_EN 0x1000 atl1e.h Auto Neg Enable
17031
 MII_CR_SPEED_SELECT_LSBMII_CR_SPEED_SELECT_LSB 0x2000 atl1e.h bits 6,13: 10=1000, 01=100, 00=10
17032
 MII_CR_LOOPBACKMII_CR_LOOPBACK 0x4000 atl1e.h 0 = normal, 1 = loopback
17033
 MII_CR_RESETMII_CR_RESET 0x8000 atl1e.h 0 = normal, 1 = PHY reset
17034
 MII_CR_SPEED_MASKMII_CR_SPEED_MASK 0x2040 atl1e.h 　
17035
 MII_CR_SPEED_1000MII_CR_SPEED_1000 0x0040 atl1e.h 　
17036
 MII_CR_SPEED_100MII_CR_SPEED_100 0x2000 atl1e.h 　
17037
 MII_CR_SPEED_10MII_CR_SPEED_10 0x0000 atl1e.h 　
17038
 MII_SR_EXTENDED_CAPSMII_SR_EXTENDED_CAPS 0x0001 atl1e.h Extended register capabilities
17039
 MII_SR_JABBER_DETECTMII_SR_JABBER_DETECT 0x0002 atl1e.h Jabber Detected
17040
 MII_SR_LINK_STATUSMII_SR_LINK_STATUS 0x0004 atl1e.h Link Status 1 = link
17041
 MII_SR_AUTONEG_CAPSMII_SR_AUTONEG_CAPS 0x0008 atl1e.h Auto Neg Capable
17042
 MII_SR_REMOTE_FAULTMII_SR_REMOTE_FAULT 0x0010 atl1e.h Remote Fault Detect
17043
 MII_SR_AUTONEG_COMPLETEMII_SR_AUTONEG_COMPLETE 0x0020 atl1e.h Auto Neg Complete
17044
 MII_SR_PREAMBLE_SUPPRESSMII_SR_PREAMBLE_SUPPRESS 0x0040 atl1e.h Preamble may be suppressed
17045
 MII_SR_EXTENDED_STATUSMII_SR_EXTENDED_STATUS 0x0100 atl1e.h Ext. status info in Reg 0x0F
17046
 MII_SR_100T2_HD_CAPSMII_SR_100T2_HD_CAPS 0x0200 atl1e.h 100T2 Half Duplex Capable
17047
 MII_SR_100T2_FD_CAPSMII_SR_100T2_FD_CAPS 0x0400 atl1e.h 100T2 Full Duplex Capable
17048
 MII_SR_10T_HD_CAPSMII_SR_10T_HD_CAPS 0x0800 atl1e.h 10T Half Duplex Capable
17049
 MII_SR_10T_FD_CAPSMII_SR_10T_FD_CAPS 0x1000 atl1e.h 10T Full Duplex Capable
17050
 MII_SR_100X_HD_CAPSMII_SR_100X_HD_CAPS 0x2000 atl1e.h 100X Half Duplex Capable
17051
 MII_SR_100X_FD_CAPSMII_SR_100X_FD_CAPS 0x4000 atl1e.h 100X Full Duplex Capable
17052
 MII_SR_100T4_CAPSMII_SR_100T4_CAPS 0x8000 atl1e.h 100T4 Capable
17053
 MII_LPA_SLCTMII_LPA_SLCT 0x001f atl1e.h Same as advertise selector
17054
 MII_LPA_10HALFMII_LPA_10HALF 0x0020 atl1e.h Can do 10mbps half-duplex
17055
 MII_LPA_10FULLMII_LPA_10FULL 0x0040 atl1e.h Can do 10mbps full-duplex
17056
 MII_LPA_100HALFMII_LPA_100HALF 0x0080 atl1e.h Can do 100mbps half-duplex
17057
 MII_LPA_100FULLMII_LPA_100FULL 0x0100 atl1e.h Can do 100mbps full-duplex
17058
 MII_LPA_100BASE4MII_LPA_100BASE4 0x0200 atl1e.h 100BASE-T4
17059
 MII_LPA_PAUSEMII_LPA_PAUSE 0x0400 atl1e.h PAUSE
17060
 MII_LPA_ASYPAUSEMII_LPA_ASYPAUSE 0x0800 atl1e.h Asymmetrical PAUSE
17061
 MII_LPA_RFAULTMII_LPA_RFAULT 0x2000 atl1e.h Link partner faulted
17062
 MII_LPA_LPACKMII_LPA_LPACK 0x4000 atl1e.h Link partner acked us
17063
 MII_LPA_NPAGEMII_LPA_NPAGE 0x8000 atl1e.h Next page bit
17064
 MII_AR_SELECTOR_FIELDMII_AR_SELECTOR_FIELD 0x0001 atl1e.h indicates IEEE 802.3 CSMA/CD
17065
 MII_AR_10T_HD_CAPSMII_AR_10T_HD_CAPS 0x0020 atl1e.h 10T Half Duplex Capable
17066
 MII_AR_10T_FD_CAPSMII_AR_10T_FD_CAPS 0x0040 atl1e.h 10T Full Duplex Capable
17067
 MII_AR_100TX_HD_CAPSMII_AR_100TX_HD_CAPS 0x0080 atl1e.h 100TX Half Duplex Capable
17068
 MII_AR_100TX_FD_CAPSMII_AR_100TX_FD_CAPS 0x0100 atl1e.h 100TX Full Duplex Capable
17069
 MII_AR_100T4_CAPSMII_AR_100T4_CAPS 0x0200 atl1e.h 100T4 Capable
17070
 MII_AR_PAUSEMII_AR_PAUSE 0x0400 atl1e.h Pause operation desired
17071
 MII_AR_ASM_DIRMII_AR_ASM_DIR 0x0800 atl1e.h Asymmetric Pause Direction bit
17072
 MII_AR_REMOTE_FAULTMII_AR_REMOTE_FAULT 0x2000 atl1e.h Remote Fault detected
17073
 MII_AR_NEXT_PAGEMII_AR_NEXT_PAGE 0x8000 atl1e.h Next Page ability supported
17074
 MII_AR_SPEED_MASKMII_AR_SPEED_MASK 0x01E0 atl1e.h 　
17075
 MII_AR_DEFAULT_CAP_MASKMII_AR_DEFAULT_CAP_MASK 0x0DE0 atl1e.h 　
17076
 MII_AT001_CR_1000T_HD_CAPSMII_AT001_CR_1000T_HD_CAPS 0x0100 atl1e.h Advertise 1000T HD capability
17077
 MII_AT001_CR_1000T_FD_CAPSMII_AT001_CR_1000T_FD_CAPS 0x0200 atl1e.h Advertise 1000T FD capability
17078
 MII_AT001_CR_1000T_REPEATER_DTEMII_AT001_CR_1000T_REPEATER_DTE 0x0400 atl1e.h 1=Repeater/switch device port
17079
 MII_AT001_CR_1000T_MS_VALUEMII_AT001_CR_1000T_MS_VALUE 0x0800 atl1e.h 1=Configure PHY as Master
17080
 MII_AT001_CR_1000T_MS_ENABLEMII_AT001_CR_1000T_MS_ENABLE 0x1000 atl1e.h 1=Master/Slave manual config value
17081
 MII_AT001_CR_1000T_TEST_MODE_NOMII_AT001_CR_1000T_TEST_MODE_NO 0x0000 atl1e.h Normal Operation
17082
 MII_AT001_CR_1000T_TEST_MODE_1MII_AT001_CR_1000T_TEST_MODE_1 0x2000 atl1e.h Transmit Waveform test
17083
 MII_AT001_CR_1000T_TEST_MODE_2MII_AT001_CR_1000T_TEST_MODE_2 0x4000 atl1e.h Master Transmit Jitter test
17084
 MII_AT001_CR_1000T_TEST_MODE_3MII_AT001_CR_1000T_TEST_MODE_3 0x6000 atl1e.h Slave Transmit Jitter test
17085
 MII_AT001_CR_1000T_TEST_MODE_4MII_AT001_CR_1000T_TEST_MODE_4 0x8000 atl1e.h Transmitter Distortion test
17086
 MII_AT001_CR_1000T_SPEED_MASKMII_AT001_CR_1000T_SPEED_MASK 0x0300 atl1e.h 　
17087
 MII_AT001_CR_1000T_DEFAULT_CAP_MII_AT001_CR_1000T_DEFAULT_CAP_ 0x0300 atl1e.h 　
17088
 MII_AT001_SR_1000T_LP_HD_CAPSMII_AT001_SR_1000T_LP_HD_CAPS 0x0400 atl1e.h LP is 1000T HD capable
17089
 MII_AT001_SR_1000T_LP_FD_CAPSMII_AT001_SR_1000T_LP_FD_CAPS 0x0800 atl1e.h LP is 1000T FD capable
17090
 MII_AT001_SR_1000T_REMOTE_RX_STMII_AT001_SR_1000T_REMOTE_RX_ST 0x1000 atl1e.h Remote receiver OK
17091
 MII_AT001_SR_1000T_LOCAL_RX_STAMII_AT001_SR_1000T_LOCAL_RX_STA 0x2000 atl1e.h Local receiver OK
17092
 MII_AT001_SR_1000T_MS_CONFIG_REMII_AT001_SR_1000T_MS_CONFIG_RE 0x4000 atl1e.h 1=Local TX is Master, 0=Slave
17093
 MII_AT001_SR_1000T_MS_CONFIG_FAMII_AT001_SR_1000T_MS_CONFIG_FA 0x8000 atl1e.h Master/Slave config fault
17094
 MII_AT001_SR_1000T_REMOTE_RX_STMII_AT001_SR_1000T_REMOTE_RX_ST 12 atl1e.h 　
17095
 MII_AT001_SR_1000T_LOCAL_RX_STAMII_AT001_SR_1000T_LOCAL_RX_STA 13 atl1e.h 　
17096
 MII_AT001_ESR_1000T_HD_CAPSMII_AT001_ESR_1000T_HD_CAPS 0x1000 atl1e.h 1000T HD capable
17097
 MII_AT001_ESR_1000T_FD_CAPSMII_AT001_ESR_1000T_FD_CAPS 0x2000 atl1e.h 1000T FD capable
17098
 MII_AT001_ESR_1000X_HD_CAPSMII_AT001_ESR_1000X_HD_CAPS 0x4000 atl1e.h 1000X HD capable
17099
 MII_AT001_ESR_1000X_FD_CAPSMII_AT001_ESR_1000X_FD_CAPS 0x8000 atl1e.h 1000X FD capable
17100
 MII_AT001_PSCR_JABBER_DISABLEMII_AT001_PSCR_JABBER_DISABLE 0x0001 atl1e.h 1=Jabber Function disabled
17101
 MII_AT001_PSCR_POLARITY_REVERSAMII_AT001_PSCR_POLARITY_REVERSA 0x0002 atl1e.h 1=Polarity Reversal enabled
17102
 MII_AT001_PSCR_SQE_TESTMII_AT001_PSCR_SQE_TEST 0x0004 atl1e.h 1=SQE Test enabled
17103
 MII_AT001_PSCR_MAC_POWERDOWNMII_AT001_PSCR_MAC_POWERDOWN 0x0008 atl1e.h 　
17104
 MII_AT001_PSCR_CLK125_DISABLEMII_AT001_PSCR_CLK125_DISABLE 0x0010 atl1e.h 1=CLK125 low,
17105
 MII_AT001_PSCR_MDI_MANUAL_MODEMII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 atl1e.h MDI Crossover Mode bits 6:5
17106
 MII_AT001_PSCR_MDIX_MANUAL_MODEMII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 atl1e.h Manual MDIX configuration
17107
 MII_AT001_PSCR_AUTO_X_1000TMII_AT001_PSCR_AUTO_X_1000T 0x0040 atl1e.h 1000BASE-T: Auto crossover,
17108
 MII_AT001_PSCR_AUTO_X_MODEMII_AT001_PSCR_AUTO_X_MODE 0x0060 atl1e.h Auto crossover enabled
17109
 MII_AT001_PSCR_10BT_EXT_DIST_ENMII_AT001_PSCR_10BT_EXT_DIST_EN 0x0080 atl1e.h 　
17110
 MII_AT001_PSCR_MII_5BIT_ENABLEMII_AT001_PSCR_MII_5BIT_ENABLE 0x0100 atl1e.h 　
17111
 MII_AT001_PSCR_SCRAMBLER_DISABLMII_AT001_PSCR_SCRAMBLER_DISABL 0x0200 atl1e.h 1=Scrambler disable
17112
 MII_AT001_PSCR_FORCE_LINK_GOODMII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 atl1e.h 1=Force link good
17113
 MII_AT001_PSCR_ASSERT_CRS_ON_TXMII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 atl1e.h 1=Assert CRS on Transmit
17114
 MII_AT001_PSCR_POLARITY_REVERSAMII_AT001_PSCR_POLARITY_REVERSA 1 atl1e.h 　
17115
 MII_AT001_PSCR_AUTO_X_MODE_SHIFMII_AT001_PSCR_AUTO_X_MODE_SHIF 5 atl1e.h 　
17116
 MII_AT001_PSCR_10BT_EXT_DIST_ENMII_AT001_PSCR_10BT_EXT_DIST_EN 7 atl1e.h 　
17117
 MII_AT001_PSSR_SPD_DPLX_RESOLVEMII_AT001_PSSR_SPD_DPLX_RESOLVE 0x0800 atl1e.h 1=Speed & Duplex resolved
17118
 MII_AT001_PSSR_DPLXMII_AT001_PSSR_DPLX 0x2000 atl1e.h 1=Duplex 0=Half Duplex
17119
 MII_AT001_PSSR_SPEEDMII_AT001_PSSR_SPEED 0xC000 atl1e.h Speed, bits 14:15
17120
 MII_AT001_PSSR_10MBSMII_AT001_PSSR_10MBS 0x0000 atl1e.h 00=10Mbs
17121
 MII_AT001_PSSR_100MBSMII_AT001_PSSR_100MBS 0x4000 atl1e.h 01=100Mbs
17122
 MII_AT001_PSSR_1000MBSMII_AT001_PSSR_1000MBS 0x8000 atl1e.h 10=1000Mbs
17123
 B44_DEVCTRLB44_DEVCTRL 0x0000UL b44.h Device Control
17124
 DEVCTRL_MPMDEVCTRL_MPM 0x00000040 b44.h MP PME Enable (B0 only)
17125
 DEVCTRL_PFEDEVCTRL_PFE 0x00000080 b44.h Pattern Filtering Enable
17126
 DEVCTRL_IPPDEVCTRL_IPP 0x00000400 b44.h Internal EPHY Present
17127
 DEVCTRL_EPRDEVCTRL_EPR 0x00008000 b44.h EPHY Reset
17128
 DEVCTRL_PMEDEVCTRL_PME 0x00001000 b44.h PHY Mode Enable
17129
 DEVCTRL_PMCEDEVCTRL_PMCE 0x00002000 b44.h PHY Mode Clocks Enable
17130
 DEVCTRL_PADDRDEVCTRL_PADDR 0x0007c000 b44.h PHY Address
17131
 DEVCTRL_PADDR_SHIFTDEVCTRL_PADDR_SHIFT 18 b44.h 　
17132
 B44_BIST_STATB44_BIST_STAT 0x000CUL b44.h Built-In Self-Test Status
17133
 B44_WKUP_LENB44_WKUP_LEN 0x0010UL b44.h Wakeup Length
17134
 WKUP_LEN_P0_MASKWKUP_LEN_P0_MASK 0x0000007f b44.h Pattern 0
17135
 WKUP_LEN_D0WKUP_LEN_D0 0x00000080 b44.h 　
17136
 WKUP_LEN_P1_MASKWKUP_LEN_P1_MASK 0x00007f00 b44.h Pattern 1
17137
 WKUP_LEN_P1_SHIFTWKUP_LEN_P1_SHIFT 8 b44.h 　
17138
 WKUP_LEN_D1WKUP_LEN_D1 0x00008000 b44.h 　
17139
 WKUP_LEN_P2_MASKWKUP_LEN_P2_MASK 0x007f0000 b44.h Pattern 2
17140
 WKUP_LEN_P2_SHIFTWKUP_LEN_P2_SHIFT 16 b44.h 　
17141
 WKUP_LEN_D2WKUP_LEN_D2 0x00000000 b44.h 　
17142
 WKUP_LEN_P3_MASKWKUP_LEN_P3_MASK 0x7f000000 b44.h Pattern 3
17143
 WKUP_LEN_P3_SHIFTWKUP_LEN_P3_SHIFT 24 b44.h 　
17144
 WKUP_LEN_D3WKUP_LEN_D3 0x80000000 b44.h 　
17145
 WKUP_LEN_DISABLEWKUP_LEN_DISABLE 0x80808080 b44.h 　
17146
 WKUP_LEN_ENABLE_TWOWKUP_LEN_ENABLE_TWO 0x80800000 b44.h 　
17147
 WKUP_LEN_ENABLE_THREEWKUP_LEN_ENABLE_THREE 0x80000000 b44.h 　
17148
 B44_ISTATB44_ISTAT 0x0020UL b44.h Interrupt Status
17149
 ISTAT_LSISTAT_LS 0x00000020 b44.h Link Change (B0 only)
17150
 ISTAT_PMEISTAT_PME 0x00000040 b44.h Power Management Event
17151
 ISTAT_TOISTAT_TO 0x00000080 b44.h General Purpose Timeout
17152
 ISTAT_DSCEISTAT_DSCE 0x00000400 b44.h Descriptor Error
17153
 ISTAT_DATAEISTAT_DATAE 0x00000800 b44.h Data Error
17154
 ISTAT_DPEISTAT_DPE 0x00001000 b44.h Descr. Protocol Error
17155
 ISTAT_RDUISTAT_RDU 0x00002000 b44.h Receive Descr. Underflow
17156
 ISTAT_RFOISTAT_RFO 0x00004000 b44.h Receive FIFO Overflow
17157
 ISTAT_TFUISTAT_TFU 0x00008000 b44.h Transmit FIFO Underflow
17158
 ISTAT_RXISTAT_RX 0x00010000 b44.h RX Interrupt
17159
 ISTAT_TXISTAT_TX 0x01000000 b44.h TX Interrupt
17160
 ISTAT_EMACISTAT_EMAC 0x04000000 b44.h EMAC Interrupt
17161
 ISTAT_MII_WRITEISTAT_MII_WRITE 0x08000000 b44.h MII Write Interrupt
17162
 ISTAT_MII_READISTAT_MII_READ 0x10000000 b44.h MII Read Interrupt
17163
 ISTAT_ERRORSISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|\ ISTAT_RDU|ISTAT_RFO|ISTAT_TFU) b44.h 　
17164
 B44_IMASKB44_IMASK 0x0024UL b44.h Interrupt Mask
17165
 IMASK_DEFIMASK_DEF (ISTAT_ERRORS | ISTAT_RX | ISTAT_TX) b44.h 　
17166
 IMASK_DISABLEIMASK_DISABLE 0 b44.h 　
17167
 B44_GPTIMERB44_GPTIMER 0x0028UL b44.h General Purpose Timer
17168
 B44_ADDR_LOB44_ADDR_LO 0x0088UL b44.h ENET Address Lo (B0 only)
17169
 B44_ADDR_HIB44_ADDR_HI 0x008CUL b44.h ENET Address Hi (B0 only)
17170
 B44_FILT_ADDRB44_FILT_ADDR 0x0090UL b44.h ENET Filter Address
17171
 B44_FILT_DATAB44_FILT_DATA 0x0094UL b44.h ENET Filter Data
17172
 B44_TXBURSTB44_TXBURST 0x00A0UL b44.h TX Max Burst Length
17173
 B44_RXBURSTB44_RXBURST 0x00A4UL b44.h RX Max Burst Length
17174
 B44_MAC_CTRLB44_MAC_CTRL 0x00A8UL b44.h MAC Control
17175
 MAC_CTRL_CRC32_ENABMAC_CTRL_CRC32_ENAB 0x00000001 b44.h CRC32 Generation Enable
17176
 MAC_CTRL_PHY_PDOWNMAC_CTRL_PHY_PDOWN 0x00000004 b44.h Onchip EPHY Powerdown
17177
 MAC_CTRL_PHY_EDETMAC_CTRL_PHY_EDET 0x00000008 b44.h Onchip EPHY Energy Detected
17178
 MAC_CTRL_PHY_LEDCTRLMAC_CTRL_PHY_LEDCTRL 0x000000e0 b44.h Onchip EPHY LED Control
17179
 MAC_CTRL_PHY_LEDCTRL_SHIFTMAC_CTRL_PHY_LEDCTRL_SHIFT 5 b44.h 　
17180
 B44_MAC_FLOWB44_MAC_FLOW 0x00ACUL b44.h MAC Flow Control
17181
 MAC_FLOW_RX_HI_WATERMAC_FLOW_RX_HI_WATER 0x000000ff b44.h Receive FIFO HI Water Mark
17182
 MAC_FLOW_PAUSE_ENABMAC_FLOW_PAUSE_ENAB 0x00008000 b44.h Enbl Pause Frm Generation
17183
 B44_RCV_LAZYB44_RCV_LAZY 0x0100UL b44.h Lazy Interrupt Control
17184
 RCV_LAZY_TO_MASKRCV_LAZY_TO_MASK 0x00ffffff b44.h Timeout
17185
 RCV_LAZY_FC_MASKRCV_LAZY_FC_MASK 0xff000000 b44.h Frame Count
17186
 RCV_LAZY_FC_SHIFTRCV_LAZY_FC_SHIFT 24 b44.h 　
17187
 B44_DMATX_CTRLB44_DMATX_CTRL 0x0200UL b44.h DMA TX Control
17188
 DMATX_CTRL_ENABLEDMATX_CTRL_ENABLE 0x00000001 b44.h Enable
17189
 DMATX_CTRL_SUSPENDDMATX_CTRL_SUSPEND 0x00000002 b44.h Suepend Request
17190
 DMATX_CTRL_LPBACKDMATX_CTRL_LPBACK 0x00000004 b44.h Loopback Enable
17191
 DMATX_CTRL_FAIRPRIORDMATX_CTRL_FAIRPRIOR 0x00000008 b44.h Fair Priority
17192
 DMATX_CTRL_FLUSHDMATX_CTRL_FLUSH 0x00000010 b44.h Flush Request
17193
 B44_DMATX_ADDRB44_DMATX_ADDR 0x0204UL b44.h DMA TX Descriptor Ring Addr
17194
 B44_DMATX_PTRB44_DMATX_PTR 0x0208UL b44.h DMA TX Last Posted Desc.
17195
 B44_DMATX_STATB44_DMATX_STAT 0x020CUL b44.h DMA TX Cur Actve Desc. + Sts
17196
 DMATX_STAT_CDMASKDMATX_STAT_CDMASK 0x00000fff b44.h Current Descriptor Mask
17197
 DMATX_STAT_SMASKDMATX_STAT_SMASK 0x0000f000 b44.h State Mask
17198
 DMATX_STAT_SDISABLEDDMATX_STAT_SDISABLED 0x00000000 b44.h State Disabled
17199
 DMATX_STAT_SACTIVEDMATX_STAT_SACTIVE 0x00001000 b44.h State Active
17200
 DMATX_STAT_SIDLEDMATX_STAT_SIDLE 0x00002000 b44.h State Idle Wait
17201
 DMATX_STAT_SSTOPPEDDMATX_STAT_SSTOPPED 0x00003000 b44.h State Stopped
17202
 DMATX_STAT_SSUSPDMATX_STAT_SSUSP 0x00004000 b44.h State Suspend Pending
17203
 DMATX_STAT_EMASKDMATX_STAT_EMASK 0x000f0000 b44.h Error Mask
17204
 DMATX_STAT_ENONEDMATX_STAT_ENONE 0x00000000 b44.h Error None
17205
 DMATX_STAT_EDPEDMATX_STAT_EDPE 0x00010000 b44.h Error Desc. Protocol Error
17206
 DMATX_STAT_EDFUDMATX_STAT_EDFU 0x00020000 b44.h Error Data FIFO Underrun
17207
 DMATX_STAT_EBEBRDMATX_STAT_EBEBR 0x00030000 b44.h Bus Error on Buffer Read
17208
 DMATX_STAT_EBEDADMATX_STAT_EBEDA 0x00040000 b44.h Bus Error on Desc. Access
17209
 DMATX_STAT_FLUSHEDDMATX_STAT_FLUSHED 0x00100000 b44.h Flushed
17210
 B44_DMARX_CTRLB44_DMARX_CTRL 0x0210UL b44.h DMA RX Control
17211
 DMARX_CTRL_ENABLEDMARX_CTRL_ENABLE 0x00000001 b44.h Enable
17212
 DMARX_CTRL_ROMASKDMARX_CTRL_ROMASK 0x000000fe b44.h Receive Offset Mask
17213
 DMARX_CTRL_ROSHIFTDMARX_CTRL_ROSHIFT 1 b44.h Receive Offset Shift
17214
 B44_DMARX_ADDRB44_DMARX_ADDR 0x0214UL b44.h DMA RX Descriptor Ring Addr
17215
 B44_DMARX_PTRB44_DMARX_PTR 0x0218UL b44.h DMA RX Last Posted Desc
17216
 B44_DMARX_STATB44_DMARX_STAT 0x021CUL b44.h Cur Active Desc. + Status
17217
 DMARX_STAT_CDMASKDMARX_STAT_CDMASK 0x00000fff b44.h Current Descriptor Mask
17218
 DMARX_STAT_SMASKDMARX_STAT_SMASK 0x0000f000 b44.h State Mask
17219
 DMARX_STAT_SDISABLEDDMARX_STAT_SDISABLED 0x00000000 b44.h State Disbaled
17220
 DMARX_STAT_SACTIVEDMARX_STAT_SACTIVE 0x00001000 b44.h State Active
17221
 DMARX_STAT_SIDLEDMARX_STAT_SIDLE 0x00002000 b44.h State Idle Wait
17222
 DMARX_STAT_SSTOPPEDDMARX_STAT_SSTOPPED 0x00003000 b44.h State Stopped
17223
 DMARX_STAT_EMASKDMARX_STAT_EMASK 0x000f0000 b44.h Error Mask
17224
 DMARX_STAT_ENONEDMARX_STAT_ENONE 0x00000000 b44.h Error None
17225
 DMARX_STAT_EDPEDMARX_STAT_EDPE 0x00010000 b44.h Error Desc. Protocol Error
17226
 DMARX_STAT_EDFODMARX_STAT_EDFO 0x00020000 b44.h Error Data FIFO Overflow
17227
 DMARX_STAT_EBEBWDMARX_STAT_EBEBW 0x00030000 b44.h Error on Buffer Write
17228
 DMARX_STAT_EBEDADMARX_STAT_EBEDA 0x00040000 b44.h Bus Error on Desc. Access
17229
 B44_DMAFIFO_ADB44_DMAFIFO_AD 0x0220UL b44.h DMA FIFO Diag Address
17230
 DMAFIFO_AD_OMASKDMAFIFO_AD_OMASK 0x0000ffff b44.h Offset Mask
17231
 DMAFIFO_AD_SMASKDMAFIFO_AD_SMASK 0x000f0000 b44.h Select Mask
17232
 DMAFIFO_AD_SXDDDMAFIFO_AD_SXDD 0x00000000 b44.h Select Transmit DMA Data
17233
 DMAFIFO_AD_SXDPDMAFIFO_AD_SXDP 0x00010000 b44.h Sel Transmit DMA Pointers
17234
 DMAFIFO_AD_SRDDDMAFIFO_AD_SRDD 0x00040000 b44.h Select Receive DMA Data
17235
 DMAFIFO_AD_SRDPDMAFIFO_AD_SRDP 0x00050000 b44.h Sel Receive DMA Pointers
17236
 DMAFIFO_AD_SXFDDMAFIFO_AD_SXFD 0x00080000 b44.h Select Transmit FIFO Data
17237
 DMAFIFO_AD_SXFPDMAFIFO_AD_SXFP 0x00090000 b44.h Sel Transmit FIFO Pointers
17238
 DMAFIFO_AD_SRFDDMAFIFO_AD_SRFD 0x000c0000 b44.h Select Receive FIFO Data
17239
 DMAFIFO_AD_SRFPDMAFIFO_AD_SRFP 0x000c0000 b44.h Sel Receive FIFO Pointers
17240
 B44_DMAFIFO_LOB44_DMAFIFO_LO 0x0224UL b44.h DMA FIFO Diag Low Data
17241
 B44_DMAFIFO_HIB44_DMAFIFO_HI 0x0228UL b44.h DMA FIFO Diag High Data
17242
 B44_RXCONFIGB44_RXCONFIG 0x0400UL b44.h EMAC RX Config
17243
 RXCONFIG_DBCASTRXCONFIG_DBCAST 0x00000001 b44.h Disable Broadcast
17244
 RXCONFIG_ALLMULTIRXCONFIG_ALLMULTI 0x00000002 b44.h Accept All Multicast
17245
 RXCONFIG_NORX_WHILE_TXRXCONFIG_NORX_WHILE_TX 0x00000004 b44.h Rcv Disble While TX
17246
 RXCONFIG_PROMISCRXCONFIG_PROMISC 0x00000008 b44.h Promiscuous Enable
17247
 RXCONFIG_LPBACKRXCONFIG_LPBACK 0x00000010 b44.h Loopback Enable
17248
 RXCONFIG_FLOWRXCONFIG_FLOW 0x00000020 b44.h Flow Control Enable
17249
 RXCONFIG_FLOW_ACCEPTRXCONFIG_FLOW_ACCEPT 0x00000040 b44.h Accept UFC Frame
17250
 RXCONFIG_RFILTRXCONFIG_RFILT 0x00000080 b44.h Reject Filter
17251
 B44_RXMAXLENB44_RXMAXLEN 0x0404UL b44.h EMAC RX Max Packet Length
17252
 B44_TXMAXLENB44_TXMAXLEN 0x0408UL b44.h EMAC TX Max Packet Length
17253
 B44_MDIO_CTRLB44_MDIO_CTRL 0x0410UL b44.h EMAC MDIO Control
17254
 MDIO_CTRL_MAXF_MASKMDIO_CTRL_MAXF_MASK 0x0000007f b44.h MDC Frequency
17255
 MDIO_CTRL_PREAMBLEMDIO_CTRL_PREAMBLE 0x00000080 b44.h MII Preamble Enable
17256
 B44_MDIO_DATAB44_MDIO_DATA 0x0414UL b44.h EMAC MDIO Data
17257
 MDIO_DATA_DATAMDIO_DATA_DATA 0x0000ffff b44.h R/W Data
17258
 MDIO_DATA_TA_MASKMDIO_DATA_TA_MASK 0x00030000 b44.h Turnaround Value
17259
 MDIO_DATA_TA_SHIFTMDIO_DATA_TA_SHIFT 16 b44.h 　
17260
 MDIO_TA_VALIDMDIO_TA_VALID 2 b44.h 　
17261
 MDIO_DATA_RA_MASKMDIO_DATA_RA_MASK 0x007c0000 b44.h Register Address
17262
 MDIO_DATA_RA_SHIFTMDIO_DATA_RA_SHIFT 18 b44.h 　
17263
 MDIO_DATA_PMD_MASKMDIO_DATA_PMD_MASK 0x0f800000 b44.h Physical Media Device
17264
 MDIO_DATA_PMD_SHIFTMDIO_DATA_PMD_SHIFT 23 b44.h 　
17265
 MDIO_DATA_OP_MASKMDIO_DATA_OP_MASK 0x30000000 b44.h Opcode
17266
 MDIO_DATA_OP_SHIFTMDIO_DATA_OP_SHIFT 28 b44.h 　
17267
 MDIO_OP_WRITEMDIO_OP_WRITE 1 b44.h 　
17268
 MDIO_OP_READMDIO_OP_READ 2 b44.h 　
17269
 MDIO_DATA_SB_MASKMDIO_DATA_SB_MASK 0xc0000000 b44.h Start Bits
17270
 MDIO_DATA_SB_SHIFTMDIO_DATA_SB_SHIFT 30 b44.h 　
17271
 MDIO_DATA_SB_STARTMDIO_DATA_SB_START 0x40000000 b44.h Start Of Frame
17272
 B44_EMAC_IMASKB44_EMAC_IMASK 0x0418UL b44.h EMAC Interrupt Mask
17273
 B44_EMAC_ISTATB44_EMAC_ISTAT 0x041CUL b44.h EMAC Interrupt Status
17274
 EMAC_INT_MIIEMAC_INT_MII 0x00000001 b44.h MII MDIO Interrupt
17275
 EMAC_INT_MIBEMAC_INT_MIB 0x00000002 b44.h MIB Interrupt
17276
 EMAC_INT_FLOWEMAC_INT_FLOW 0x00000003 b44.h Flow Control Interrupt
17277
 B44_CAM_DATA_LOB44_CAM_DATA_LO 0x0420UL b44.h EMAC CAM Data Low
17278
 B44_CAM_DATA_HIB44_CAM_DATA_HI 0x0424UL b44.h EMAC CAM Data High
17279
 CAM_DATA_HI_VALIDCAM_DATA_HI_VALID 0x00010000 b44.h Valid Bit
17280
 B44_CAM_CTRLB44_CAM_CTRL 0x0428UL b44.h EMAC CAM Control
17281
 CAM_CTRL_ENABLECAM_CTRL_ENABLE 0x00000001 b44.h CAM Enable
17282
 CAM_CTRL_MSELCAM_CTRL_MSEL 0x00000002 b44.h Mask Select
17283
 CAM_CTRL_READCAM_CTRL_READ 0x00000004 b44.h Read
17284
 CAM_CTRL_WRITECAM_CTRL_WRITE 0x00000008 b44.h Read
17285
 CAM_CTRL_INDEX_MASKCAM_CTRL_INDEX_MASK 0x003f0000 b44.h Index Mask
17286
 CAM_CTRL_INDEX_SHIFTCAM_CTRL_INDEX_SHIFT 16 b44.h 　
17287
 CAM_CTRL_BUSYCAM_CTRL_BUSY 0x80000000 b44.h CAM Busy
17288
 B44_ENET_CTRLB44_ENET_CTRL 0x042CUL b44.h EMAC ENET Control
17289
 ENET_CTRL_ENABLEENET_CTRL_ENABLE 0x00000001 b44.h EMAC Enable
17290
 ENET_CTRL_DISABLEENET_CTRL_DISABLE 0x00000002 b44.h EMAC Disable
17291
 ENET_CTRL_SRSTENET_CTRL_SRST 0x00000004 b44.h EMAC Soft Reset
17292
 ENET_CTRL_EPSELENET_CTRL_EPSEL 0x00000008 b44.h External PHY Select
17293
 B44_TX_CTRLB44_TX_CTRL 0x0430UL b44.h EMAC TX Control
17294
 TX_CTRL_DUPLEXTX_CTRL_DUPLEX 0x00000001 b44.h Full Duplex
17295
 TX_CTRL_FMODETX_CTRL_FMODE 0x00000002 b44.h Flow Mode
17296
 TX_CTRL_SBENABTX_CTRL_SBENAB 0x00000004 b44.h Single Backoff Enable
17297
 TX_CTRL_SMALL_SLOTTX_CTRL_SMALL_SLOT 0x00000008 b44.h Small Slottime
17298
 B44_TX_HIWMARKB44_TX_HIWMARK 0x0434UL b44.h EMAC TX High Watermark
17299
 TX_HIWMARK_DEFLTTX_HIWMARK_DEFLT 56 b44.h Default used in all drivers
17300
 B44_MIB_CTRLB44_MIB_CTRL 0x0438UL b44.h EMAC MIB Control
17301
 MIB_CTRL_CLR_ON_READMIB_CTRL_CLR_ON_READ 0x00000001 b44.h Autoclear on Read
17302
 B44_TX_GOOD_OB44_TX_GOOD_O 0x0500UL b44.h MIB TX Good Octets
17303
 B44_TX_GOOD_PB44_TX_GOOD_P 0x0504UL b44.h MIB TX Good Packets
17304
 B44_TX_OB44_TX_O 0x0508UL b44.h MIB TX Octets
17305
 B44_TX_PB44_TX_P 0x050CUL b44.h MIB TX Packets
17306
 B44_TX_BCASTB44_TX_BCAST 0x0510UL b44.h MIB TX Broadcast Packets
17307
 B44_TX_MCASTB44_TX_MCAST 0x0514UL b44.h MIB TX Multicast Packets
17308
 B44_TX_64B44_TX_64 0x0518UL b44.h MIB TX <= 64 byte Packets
17309
 B44_TX_65_127B44_TX_65_127 0x051CUL b44.h MIB TX 65 to 127 byte Pkts
17310
 B44_TX_128_255B44_TX_128_255 0x0520UL b44.h MIB TX 128 to 255 byte Pkts
17311
 B44_TX_256_511B44_TX_256_511 0x0524UL b44.h MIB TX 256 to 511 byte Pkts
17312
 B44_TX_512_1023B44_TX_512_1023 0x0528UL b44.h MIB TX 512 to 1023 byte Pkts
17313
 B44_TX_1024_MAXB44_TX_1024_MAX 0x052CUL b44.h MIB TX 1024 to max byte Pkts
17314
 B44_TX_JABBERB44_TX_JABBER 0x0530UL b44.h MIB TX Jabber Packets
17315
 B44_TX_OSIZEB44_TX_OSIZE 0x0534UL b44.h MIB TX Oversize Packets
17316
 B44_TX_FRAGB44_TX_FRAG 0x0538UL b44.h MIB TX Fragment Packets
17317
 B44_TX_URUNSB44_TX_URUNS 0x053CUL b44.h MIB TX Underruns
17318
 B44_TX_TCOLSB44_TX_TCOLS 0x0540UL b44.h MIB TX Total Collisions
17319
 B44_TX_SCOLSB44_TX_SCOLS 0x0544UL b44.h MIB TX Single Collisions
17320
 B44_TX_MCOLSB44_TX_MCOLS 0x0548UL b44.h MIB TX Multiple Collisions
17321
 B44_TX_ECOLSB44_TX_ECOLS 0x054CUL b44.h MIB TX Excessive Collisions
17322
 B44_TX_LCOLSB44_TX_LCOLS 0x0550UL b44.h MIB TX Late Collisions
17323
 B44_TX_DEFEREDB44_TX_DEFERED 0x0554UL b44.h MIB TX Defered Packets
17324
 B44_TX_CLOSTB44_TX_CLOST 0x0558UL b44.h MIB TX Carrier Lost
17325
 B44_TX_PAUSEB44_TX_PAUSE 0x055CUL b44.h MIB TX Pause Packets
17326
 B44_RX_GOOD_OB44_RX_GOOD_O 0x0580UL b44.h MIB RX Good Octets
17327
 B44_RX_GOOD_PB44_RX_GOOD_P 0x0584UL b44.h MIB RX Good Packets
17328
 B44_RX_OB44_RX_O 0x0588UL b44.h MIB RX Octets
17329
 B44_RX_PB44_RX_P 0x058CUL b44.h MIB RX Packets
17330
 B44_RX_BCASTB44_RX_BCAST 0x0590UL b44.h MIB RX Broadcast Packets
17331
 B44_RX_MCASTB44_RX_MCAST 0x0594UL b44.h MIB RX Multicast Packets
17332
 B44_RX_64B44_RX_64 0x0598UL b44.h MIB RX <= 64 byte Packets
17333
 B44_RX_65_127B44_RX_65_127 0x059CUL b44.h MIB RX 65 to 127 byte Pkts
17334
 B44_RX_128_255B44_RX_128_255 0x05A0UL b44.h MIB RX 128 to 255 byte Pkts
17335
 B44_RX_256_511B44_RX_256_511 0x05A4UL b44.h MIB RX 256 to 511 byte Pkts
17336
 B44_RX_512_1023B44_RX_512_1023 0x05A8UL b44.h MIB RX 512 to 1023 byte Pkts
17337
 B44_RX_1024_MAXB44_RX_1024_MAX 0x05ACUL b44.h MIB RX 1024 to max byte Pkts
17338
 B44_RX_JABBERB44_RX_JABBER 0x05B0UL b44.h MIB RX Jabber Packets
17339
 B44_RX_OSIZEB44_RX_OSIZE 0x05B4UL b44.h MIB RX Oversize Packets
17340
 B44_RX_FRAGB44_RX_FRAG 0x05B8UL b44.h MIB RX Fragment Packets
17341
 B44_RX_MISSB44_RX_MISS 0x05BCUL b44.h MIB RX Missed Packets
17342
 B44_RX_CRCAB44_RX_CRCA 0x05C0UL b44.h MIB RX CRC Align Errors
17343
 B44_RX_USIZEB44_RX_USIZE 0x05C4UL b44.h MIB RX Undersize Packets
17344
 B44_RX_CRCB44_RX_CRC 0x05C8UL b44.h MIB RX CRC Errors
17345
 B44_RX_ALIGNB44_RX_ALIGN 0x05CCUL b44.h MIB RX Align Errors
17346
 B44_RX_SYMB44_RX_SYM 0x05D0UL b44.h MIB RX Symbol Errors
17347
 B44_RX_PAUSEB44_RX_PAUSE 0x05D4UL b44.h MIB RX Pause Packets
17348
 B44_RX_NPAUSEB44_RX_NPAUSE 0x05D8UL b44.h MIB RX Non-Pause Packets
17349
 B44_SBIMSTATEB44_SBIMSTATE 0x0F90UL b44.h SB Initiator Agent State
17350
 SBIMSTATE_PCSBIMSTATE_PC 0x0000000f b44.h Pipe Count
17351
 SBIMSTATE_AP_MASKSBIMSTATE_AP_MASK 0x00000030 b44.h Arbitration Priority
17352
 SBIMSTATE_AP_BOTHSBIMSTATE_AP_BOTH 0x00000000 b44.h both timeslices and token
17353
 SBIMSTATE_AP_TSSBIMSTATE_AP_TS 0x00000010 b44.h Use timeslices only
17354
 SBIMSTATE_AP_TKSBIMSTATE_AP_TK 0x00000020 b44.h Use token only
17355
 SBIMSTATE_AP_RSVSBIMSTATE_AP_RSV 0x00000030 b44.h Reserved
17356
 SBIMSTATE_IBESBIMSTATE_IBE 0x00020000 b44.h In Band Error
17357
 SBIMSTATE_TOSBIMSTATE_TO 0x00040000 b44.h Timeout
17358
 SBIMSTATE_BADSBIMSTATE_BAD ( SBIMSTATE_IBE | SBIMSTATE_TO ) b44.h 　
17359
 B44_SBINTVECB44_SBINTVEC 0x0F94UL b44.h SB Interrupt Mask
17360
 SBINTVEC_PCISBINTVEC_PCI 0x00000001 b44.h Enable interrupts for PCI
17361
 SBINTVEC_ENET0SBINTVEC_ENET0 0x00000002 b44.h Enable ints for enet 0
17362
 SBINTVEC_ILINE20SBINTVEC_ILINE20 0x00000004 b44.h Enable ints for iline20
17363
 SBINTVEC_CODECSBINTVEC_CODEC 0x00000008 b44.h Enable ints for v90 codec
17364
 SBINTVEC_USBSBINTVEC_USB 0x00000010 b44.h Enable intts for usb
17365
 SBINTVEC_EXTIFSBINTVEC_EXTIF 0x00000020 b44.h Enable ints for ext i/f
17366
 SBINTVEC_ENET1SBINTVEC_ENET1 0x00000040 b44.h Enable ints for enet 1
17367
 B44_SBTMSLOWB44_SBTMSLOW 0x0F98UL b44.h SB Target State Low
17368
 SBTMSLOW_RESETSBTMSLOW_RESET 0x00000001 b44.h Reset
17369
 SBTMSLOW_REJECTSBTMSLOW_REJECT 0x00000002 b44.h Reject
17370
 SBTMSLOW_CLOCKSBTMSLOW_CLOCK 0x00010000 b44.h Clock Enable
17371
 SBTMSLOW_FGCSBTMSLOW_FGC 0x00020000 b44.h Force Gated Clocks On
17372
 SBTMSLOW_PESBTMSLOW_PE 0x40000000 b44.h Power Management Enable
17373
 SBTMSLOW_BESBTMSLOW_BE 0x80000000 b44.h BIST Enable
17374
 B44_SBTMSHIGHB44_SBTMSHIGH 0x0F9CUL b44.h SB Target State High
17375
 SBTMSHIGH_SERRSBTMSHIGH_SERR 0x00000001 b44.h S-error
17376
 SBTMSHIGH_INTSBTMSHIGH_INT 0x00000002 b44.h Interrupt
17377
 SBTMSHIGH_BUSYSBTMSHIGH_BUSY 0x00000004 b44.h Busy
17378
 SBTMSHIGH_GCRSBTMSHIGH_GCR 0x20000000 b44.h Gated Clock Request
17379
 SBTMSHIGH_BISTFSBTMSHIGH_BISTF 0x40000000 b44.h BIST Failed
17380
 SBTMSHIGH_BISTDSBTMSHIGH_BISTD 0x80000000 b44.h BIST Done
17381
 B44_SBIDHIGHB44_SBIDHIGH 0x0FFCUL b44.h SB Identification High
17382
 SBIDHIGH_RC_MASKSBIDHIGH_RC_MASK 0x0000000f b44.h Revision Code
17383
 SBIDHIGH_CC_MASKSBIDHIGH_CC_MASK 0x0000fff0 b44.h Core Code
17384
 SBIDHIGH_CC_SHIFTSBIDHIGH_CC_SHIFT 4 b44.h 　
17385
 SBIDHIGH_VC_MASKSBIDHIGH_VC_MASK 0xffff0000 b44.h Vendor Code
17386
 SBIDHIGH_VC_SHIFTSBIDHIGH_VC_SHIFT 16 b44.h 　
17387
 SSB_PMCSRSSB_PMCSR 0x44 b44.h 　
17388
 SSB_PESSB_PE 0x100 b44.h 　
17389
 SSB_BAR0_WINSSB_BAR0_WIN 0x80 b44.h 　
17390
 SSB_BAR1_WINSSB_BAR1_WIN 0x84 b44.h 　
17391
 SSB_SPROM_CONTROLSSB_SPROM_CONTROL 0x88 b44.h 　
17392
 SSB_BAR1_CONTROLSSB_BAR1_CONTROL 0x8c b44.h 　
17393
 SSB_CONTROLSSB_CONTROL 0x0000UL b44.h 　
17394
 SSB_ARBCONTROLSSB_ARBCONTROL 0x0010UL b44.h 　
17395
 SSB_ISTATSSB_ISTAT 0x0020UL b44.h 　
17396
 SSB_IMASKSSB_IMASK 0x0024UL b44.h 　
17397
 SSB_MBOXSSB_MBOX 0x0028UL b44.h 　
17398
 SSB_BCAST_ADDRSSB_BCAST_ADDR 0x0050UL b44.h 　
17399
 SSB_BCAST_DATASSB_BCAST_DATA 0x0054UL b44.h 　
17400
 SSB_PCI_TRANS_0SSB_PCI_TRANS_0 0x0100UL b44.h 　
17401
 SSB_PCI_TRANS_1SSB_PCI_TRANS_1 0x0104UL b44.h 　
17402
 SSB_PCI_TRANS_2SSB_PCI_TRANS_2 0x0108UL b44.h 　
17403
 SSB_SPROMSSB_SPROM 0x0800UL b44.h 　
17404
 SSB_PCI_MEMSSB_PCI_MEM 0x00000000 b44.h 　
17405
 SSB_PCI_IOSSB_PCI_IO 0x00000001 b44.h 　
17406
 SSB_PCI_CFG0SSB_PCI_CFG0 0x00000002 b44.h 　
17407
 SSB_PCI_CFG1SSB_PCI_CFG1 0x00000003 b44.h 　
17408
 SSB_PCI_PREFSSB_PCI_PREF 0x00000004 b44.h 　
17409
 SSB_PCI_BURSTSSB_PCI_BURST 0x00000008 b44.h 　
17410
 SSB_PCI_MASK0SSB_PCI_MASK0 0xfc000000 b44.h 　
17411
 SSB_PCI_MASK1SSB_PCI_MASK1 0xfc000000 b44.h 　
17412
 SSB_PCI_MASK2SSB_PCI_MASK2 0xc0000000 b44.h 　
17413
 B44_MII_AUXCTRLB44_MII_AUXCTRL 24 b44.h Auxiliary Control
17414
 MII_AUXCTRL_DUPLEXMII_AUXCTRL_DUPLEX 0x0001 b44.h Full Duplex
17415
 MII_AUXCTRL_SPEEDMII_AUXCTRL_SPEED 0x0002 b44.h 1=100Mbps, 0=10Mbps
17416
 MII_AUXCTRL_FORCEDMII_AUXCTRL_FORCED 0x0004 b44.h Forced 10/100
17417
 B44_MII_ALEDCTRLB44_MII_ALEDCTRL 26 b44.h Activity LED
17418
 MII_ALEDCTRL_ALLMSKMII_ALEDCTRL_ALLMSK 0x7fff b44.h 　
17419
 B44_MII_TLEDCTRLB44_MII_TLEDCTRL 27 b44.h Traffic Meter LED
17420
 MII_TLEDCTRL_ENABLEMII_TLEDCTRL_ENABLE 0x0040 b44.h 　
17421
 B44_DMA_ALIGNMENTB44_DMA_ALIGNMENT 4096 b44.h 　
17422
 B44_30BIT_DMA_MASKB44_30BIT_DMA_MASK 0x3fffffff b44.h 　
17423
 DESC_CTRL_LENDESC_CTRL_LEN 0x00001fff b44.h 　
17424
 DESC_CTRL_CMASKDESC_CTRL_CMASK 0x0ff00000 b44.h Core specific bits
17425
 DESC_CTRL_EOTDESC_CTRL_EOT 0x10000000 b44.h End of Table
17426
 DESC_CTRL_IOCDESC_CTRL_IOC 0x20000000 b44.h Interrupt On Completion
17427
 DESC_CTRL_EOFDESC_CTRL_EOF 0x40000000 b44.h End of Frame
17428
 DESC_CTRL_SOFDESC_CTRL_SOF 0x80000000 b44.h Start of Frame
17429
 RX_HEADER_LENRX_HEADER_LEN 28 b44.h 　
17430
 RX_FLAG_OFIFORX_FLAG_OFIFO 0x00000001 b44.h FIFO Overflow
17431
 RX_FLAG_CRCERRRX_FLAG_CRCERR 0x00000002 b44.h CRC Error
17432
 RX_FLAG_SERRRX_FLAG_SERR 0x00000004 b44.h Receive Symbol Error
17433
 RX_FLAG_ODDRX_FLAG_ODD 0x00000008 b44.h Frame has odd number of nibbles
17434
 RX_FLAG_LARGERX_FLAG_LARGE 0x00000010 b44.h Frame is > RX MAX Length
17435
 RX_FLAG_MCASTRX_FLAG_MCAST 0x00000020 b44.h Dest is Multicast Address
17436
 RX_FLAG_BCASTRX_FLAG_BCAST 0x00000040 b44.h Dest is Broadcast Address
17437
 RX_FLAG_MISSRX_FLAG_MISS 0x00000080 b44.h Received due to promisc mode
17438
 RX_FLAG_LASTRX_FLAG_LAST 0x00000800 b44.h Last buffer in frame
17439
 RX_FLAG_ERRORSRX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR |\ RX_FLAG_CRCERR | RX_FLAG_OFIFO) b44.h 　
17440
 SB_PCI_DMASB_PCI_DMA 0x40000000 b44.h 　
17441
 BCM4400_PCI_CORE_ADDRBCM4400_PCI_CORE_ADDR 0x18002000 b44.h 　
17442
 B44_MIN_MTUB44_MIN_MTU 60 b44.h 　
17443
 B44_MAX_MTUB44_MAX_MTU 1500 b44.h 　
17444
 B44_RING_SIZEB44_RING_SIZE 8 b44.h 　
17445
 B44_RING_LASTB44_RING_LAST ( B44_RING_SIZE - 1 ) b44.h 　
17446
 B44_RX_RING_LEN_BYTESB44_RX_RING_LEN_BYTES ( sizeof bp->rx[0] * B44_RING_SIZE ) b44.h 　
17447
 B44_TX_RING_LEN_BYTESB44_TX_RING_LEN_BYTES ( sizeof bp->tx[0] * B44_RING_SIZE ) b44.h 　
17448
 RX_PKT_OFFSETRX_PKT_OFFSET 30 b44.h 　
17449
 RX_PKT_BUF_SZRX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET + 64) b44.h 　
17450
 B44_FULL_RESETB44_FULL_RESET 1 b44.h 　
17451
 B44_FULL_RESET_SKIP_PHYB44_FULL_RESET_SKIP_PHY 2 b44.h 　
17452
 B44_PARTIAL_RESETB44_PARTIAL_RESET 3 b44.h 　
17453
 B44_CHIP_RESET_FULLB44_CHIP_RESET_FULL 4 b44.h 　
17454
 B44_CHIP_RESET_PARTIALB44_CHIP_RESET_PARTIAL 5 b44.h 　
17455
 SSB_CORE_DOWNSSB_CORE_DOWN ( SBTMSLOW_RESET | SBTMSLOW_REJECT ) b44.h 　
17456
 B44_REGS_SIZEB44_REGS_SIZE 8192 b44.h 　
17457
 L1_CACHE_BYTESL1_CACHE_BYTES 128 bnx2.h Rough approximaition of the cache line size
17458
 PCI_D0PCI_D0 ((pci_power_t) 0) bnx2.h 　
17459
 PCI_D1PCI_D1 ((pci_power_t) 1) bnx2.h 　
17460
 PCI_D2PCI_D2 ((pci_power_t) 2) bnx2.h 　
17461
 PCI_D3hotPCI_D3hot ((pci_power_t) 3) bnx2.h 　
17462
 PCI_D3coldPCI_D3cold ((pci_power_t) 4) bnx2.h 　
17463
 PCI_UNKNOWNPCI_UNKNOWN ((pci_power_t) 5) bnx2.h 　
17464
 PCI_POWER_ERRORPCI_POWER_ERROR ((pci_power_t) -1) bnx2.h 　
17465
 PCI_CAP_ID_PCIXPCI_CAP_ID_PCIX 0x07 bnx2.h PCI-X
17466
 PCI_X_CMDPCI_X_CMD 2 bnx2.h Modes & Features
17467
 PCI_X_CMD_EROPCI_X_CMD_ERO 0x0002 bnx2.h Enable Relaxed Ordering
17468
 ADVERTISED_10baseT_HalfADVERTISED_10baseT_Half (1 << 0) bnx2.h 　
17469
 ADVERTISED_10baseT_FullADVERTISED_10baseT_Full (1 << 1) bnx2.h 　
17470
 ADVERTISED_100baseT_HalfADVERTISED_100baseT_Half (1 << 2) bnx2.h 　
17471
 ADVERTISED_100baseT_FullADVERTISED_100baseT_Full (1 << 3) bnx2.h 　
17472
 ADVERTISED_1000baseT_HalfADVERTISED_1000baseT_Half (1 << 4) bnx2.h 　
17473
 ADVERTISED_1000baseT_FullADVERTISED_1000baseT_Full (1 << 5) bnx2.h 　
17474
 ADVERTISED_AutonegADVERTISED_Autoneg (1 << 6) bnx2.h 　
17475
 ADVERTISED_TPADVERTISED_TP (1 << 7) bnx2.h 　
17476
 ADVERTISED_AUIADVERTISED_AUI (1 << 8) bnx2.h 　
17477
 ADVERTISED_MIIADVERTISED_MII (1 << 9) bnx2.h 　
17478
 ADVERTISED_FIBREADVERTISED_FIBRE (1 << 10) bnx2.h 　
17479
 ADVERTISED_BNCADVERTISED_BNC (1 << 11) bnx2.h 　
17480
 DUPLEX_HALFDUPLEX_HALF 0x00 bnx2.h 　
17481
 DUPLEX_FULLDUPLEX_FULL 0x01 bnx2.h 　
17482
 DUPLEX_INVALIDDUPLEX_INVALID 0x02 bnx2.h 　
17483
 PORT_TPPORT_TP 0x00 bnx2.h 　
17484
 PORT_AUIPORT_AUI 0x01 bnx2.h 　
17485
 PORT_MIIPORT_MII 0x02 bnx2.h 　
17486
 PORT_FIBREPORT_FIBRE 0x03 bnx2.h 　
17487
 PORT_BNCPORT_BNC 0x04 bnx2.h 　
17488
 XCVR_INTERNALXCVR_INTERNAL 0x00 bnx2.h 　
17489
 XCVR_EXTERNALXCVR_EXTERNAL 0x01 bnx2.h 　
17490
 XCVR_DUMMY1XCVR_DUMMY1 0x02 bnx2.h 　
17491
 XCVR_DUMMY2XCVR_DUMMY2 0x03 bnx2.h 　
17492
 XCVR_DUMMY3XCVR_DUMMY3 0x04 bnx2.h 　
17493
 AUTONEG_DISABLEAUTONEG_DISABLE 0x00 bnx2.h 　
17494
 AUTONEG_ENABLEAUTONEG_ENABLE 0x01 bnx2.h 　
17495
 WAKE_PHYWAKE_PHY (1 << 0) bnx2.h 　
17496
 WAKE_UCASTWAKE_UCAST (1 << 1) bnx2.h 　
17497
 WAKE_MCASTWAKE_MCAST (1 << 2) bnx2.h 　
17498
 WAKE_BCASTWAKE_BCAST (1 << 3) bnx2.h 　
17499
 WAKE_ARPWAKE_ARP (1 << 4) bnx2.h 　
17500
 WAKE_MAGICWAKE_MAGIC (1 << 5) bnx2.h 　
17501
 WAKE_MAGICSECUREWAKE_MAGICSECURE (1 << 6) bnx2.h only meaningful if WAKE_MAGIC
17502
 SPEED_10SPEED_10 10 bnx2.h 　
17503
 SPEED_100SPEED_100 100 bnx2.h 　
17504
 SPEED_1000SPEED_1000 1000 bnx2.h 　
17505
 SPEED_2500SPEED_2500 2500 bnx2.h 　
17506
 SPEED_INVALIDSPEED_INVALID 0 bnx2.h XXX was 3
17507
 DUPLEX_HALFDUPLEX_HALF 0x00 bnx2.h 　
17508
 DUPLEX_FULLDUPLEX_FULL 0x01 bnx2.h 　
17509
 DUPLEX_INVALIDDUPLEX_INVALID 0x02 bnx2.h 　
17510
 PORT_TPPORT_TP 0x00 bnx2.h 　
17511
 PORT_AUIPORT_AUI 0x01 bnx2.h 　
17512
 PORT_MIIPORT_MII 0x02 bnx2.h 　
17513
 PORT_FIBREPORT_FIBRE 0x03 bnx2.h 　
17514
 PORT_BNCPORT_BNC 0x04 bnx2.h 　
17515
 XCVR_INTERNALXCVR_INTERNAL 0x00 bnx2.h 　
17516
 XCVR_EXTERNALXCVR_EXTERNAL 0x01 bnx2.h 　
17517
 XCVR_DUMMY1XCVR_DUMMY1 0x02 bnx2.h 　
17518
 XCVR_DUMMY2XCVR_DUMMY2 0x03 bnx2.h 　
17519
 XCVR_DUMMY3XCVR_DUMMY3 0x04 bnx2.h 　
17520
 AUTONEG_DISABLEAUTONEG_DISABLE 0x00 bnx2.h 　
17521
 AUTONEG_ENABLEAUTONEG_ENABLE 0x01 bnx2.h 　
17522
 WAKE_PHYWAKE_PHY (1 << 0) bnx2.h 　
17523
 WAKE_UCASTWAKE_UCAST (1 << 1) bnx2.h 　
17524
 WAKE_MCASTWAKE_MCAST (1 << 2) bnx2.h 　
17525
 WAKE_BCASTWAKE_BCAST (1 << 3) bnx2.h 　
17526
 WAKE_ARPWAKE_ARP (1 << 4) bnx2.h 　
17527
 WAKE_MAGICWAKE_MAGIC (1 << 5) bnx2.h 　
17528
 WAKE_MAGICSECUREWAKE_MAGICSECURE (1 << 6) bnx2.h only meaningful if WAKE_MAGIC
17529
 BNX2_L2CTX_TYPEBNX2_L2CTX_TYPE 0x00000000 bnx2.h 　
17530
 BNX2_L2CTX_TYPE_SIZE_L2BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16) bnx2.h 　
17531
 BNX2_L2CTX_TYPE_TYPEBNX2_L2CTX_TYPE_TYPE (0xf<<28) bnx2.h 　
17532
 BNX2_L2CTX_TYPE_TYPE_EMPTYBNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28) bnx2.h 　
17533
 BNX2_L2CTX_TYPE_TYPE_L2BNX2_L2CTX_TYPE_TYPE_L2 (1<<28) bnx2.h 　
17534
 BNX2_L2CTX_TX_HOST_BIDXBNX2_L2CTX_TX_HOST_BIDX 0x00000088 bnx2.h 　
17535
 BNX2_L2CTX_EST_NBDBNX2_L2CTX_EST_NBD 0x00000088 bnx2.h 　
17536
 BNX2_L2CTX_CMD_TYPEBNX2_L2CTX_CMD_TYPE 0x00000088 bnx2.h 　
17537
 BNX2_L2CTX_CMD_TYPE_TYPEBNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24) bnx2.h 　
17538
 BNX2_L2CTX_CMD_TYPE_TYPE_L2BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24) bnx2.h 　
17539
 BNX2_L2CTX_CMD_TYPE_TYPE_TCPBNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24) bnx2.h 　
17540
 BNX2_L2CTX_TX_HOST_BSEQBNX2_L2CTX_TX_HOST_BSEQ 0x00000090 bnx2.h 　
17541
 BNX2_L2CTX_TSCH_BSEQBNX2_L2CTX_TSCH_BSEQ 0x00000094 bnx2.h 　
17542
 BNX2_L2CTX_TBDR_BSEQBNX2_L2CTX_TBDR_BSEQ 0x00000098 bnx2.h 　
17543
 BNX2_L2CTX_TBDR_BOFFBNX2_L2CTX_TBDR_BOFF 0x0000009c bnx2.h 　
17544
 BNX2_L2CTX_TBDR_BIDXBNX2_L2CTX_TBDR_BIDX 0x0000009c bnx2.h 　
17545
 BNX2_L2CTX_TBDR_BHADDR_HIBNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0 bnx2.h 　
17546
 BNX2_L2CTX_TBDR_BHADDR_LOBNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4 bnx2.h 　
17547
 BNX2_L2CTX_TXP_BOFFBNX2_L2CTX_TXP_BOFF 0x000000a8 bnx2.h 　
17548
 BNX2_L2CTX_TXP_BIDXBNX2_L2CTX_TXP_BIDX 0x000000a8 bnx2.h 　
17549
 BNX2_L2CTX_TXP_BSEQBNX2_L2CTX_TXP_BSEQ 0x000000ac bnx2.h 　
17550
 BNX2_L2CTX_BD_PRE_READBNX2_L2CTX_BD_PRE_READ 0x00000000 bnx2.h 　
17551
 BNX2_L2CTX_CTX_SIZEBNX2_L2CTX_CTX_SIZE 0x00000000 bnx2.h 　
17552
 BNX2_L2CTX_CTX_TYPEBNX2_L2CTX_CTX_TYPE 0x00000000 bnx2.h 　
17553
 BNX2_L2CTX_CTX_TYPE_SIZE_L2BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16) bnx2.h 　
17554
 BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_ (0xf<<28) bnx2.h 　
17555
 BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_ (0<<28) bnx2.h 　
17556
 BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_ (1<<28) bnx2.h 　
17557
 BNX2_L2CTX_HOST_BDIDXBNX2_L2CTX_HOST_BDIDX 0x00000004 bnx2.h 　
17558
 BNX2_L2CTX_HOST_BSEQBNX2_L2CTX_HOST_BSEQ 0x00000008 bnx2.h 　
17559
 BNX2_L2CTX_NX_BSEQBNX2_L2CTX_NX_BSEQ 0x0000000c bnx2.h 　
17560
 BNX2_L2CTX_NX_BDHADDR_HIBNX2_L2CTX_NX_BDHADDR_HI 0x00000010 bnx2.h 　
17561
 BNX2_L2CTX_NX_BDHADDR_LOBNX2_L2CTX_NX_BDHADDR_LO 0x00000014 bnx2.h 　
17562
 BNX2_L2CTX_NX_BDIDXBNX2_L2CTX_NX_BDIDX 0x00000018 bnx2.h 　
17563
 BNX2_PCICFG_MISC_CONFIGBNX2_PCICFG_MISC_CONFIG 0x00000068 bnx2.h 　
17564
 BNX2_PCICFG_MISC_CONFIG_TARGET_BNX2_PCICFG_MISC_CONFIG_TARGET_ (1L<<2) bnx2.h 　
17565
 BNX2_PCICFG_MISC_CONFIG_TARGET_BNX2_PCICFG_MISC_CONFIG_TARGET_ (1L<<3) bnx2.h 　
17566
 BNX2_PCICFG_MISC_CONFIG_CLOCK_CBNX2_PCICFG_MISC_CONFIG_CLOCK_C (1L<<5) bnx2.h 　
17567
 BNX2_PCICFG_MISC_CONFIG_TARGET_BNX2_PCICFG_MISC_CONFIG_TARGET_ (1L<<6) bnx2.h 　
17568
 BNX2_PCICFG_MISC_CONFIG_REG_WINBNX2_PCICFG_MISC_CONFIG_REG_WIN (1L<<7) bnx2.h 　
17569
 BNX2_PCICFG_MISC_CONFIG_CORE_RSBNX2_PCICFG_MISC_CONFIG_CORE_RS (1L<<8) bnx2.h 　
17570
 BNX2_PCICFG_MISC_CONFIG_CORE_RSBNX2_PCICFG_MISC_CONFIG_CORE_RS (1L<<9) bnx2.h 　
17571
 BNX2_PCICFG_MISC_CONFIG_ASIC_MEBNX2_PCICFG_MISC_CONFIG_ASIC_ME (0xffL<<16) bnx2.h 　
17572
 BNX2_PCICFG_MISC_CONFIG_ASIC_BABNX2_PCICFG_MISC_CONFIG_ASIC_BA (0xfL<<24) bnx2.h 　
17573
 BNX2_PCICFG_MISC_CONFIG_ASIC_IDBNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28) bnx2.h 　
17574
 BNX2_PCICFG_MISC_STATUSBNX2_PCICFG_MISC_STATUS 0x0000006c bnx2.h 　
17575
 BNX2_PCICFG_MISC_STATUS_INTA_VABNX2_PCICFG_MISC_STATUS_INTA_VA (1L<<0) bnx2.h 　
17576
 BNX2_PCICFG_MISC_STATUS_32BIT_DBNX2_PCICFG_MISC_STATUS_32BIT_D (1L<<1) bnx2.h 　
17577
 BNX2_PCICFG_MISC_STATUS_M66ENBNX2_PCICFG_MISC_STATUS_M66EN (1L<<2) bnx2.h 　
17578
 BNX2_PCICFG_MISC_STATUS_PCIX_DEBNX2_PCICFG_MISC_STATUS_PCIX_DE (1L<<3) bnx2.h 　
17579
 BNX2_PCICFG_MISC_STATUS_PCIX_SPBNX2_PCICFG_MISC_STATUS_PCIX_SP (0x3L<<4) bnx2.h 　
17580
 BNX2_PCICFG_MISC_STATUS_PCIX_SPBNX2_PCICFG_MISC_STATUS_PCIX_SP (0L<<4) bnx2.h 　
17581
 BNX2_PCICFG_MISC_STATUS_PCIX_SPBNX2_PCICFG_MISC_STATUS_PCIX_SP (1L<<4) bnx2.h 　
17582
 BNX2_PCICFG_MISC_STATUS_PCIX_SPBNX2_PCICFG_MISC_STATUS_PCIX_SP (2L<<4) bnx2.h 　
17583
 BNX2_PCICFG_MISC_STATUS_PCIX_SPBNX2_PCICFG_MISC_STATUS_PCIX_SP (3L<<4) bnx2.h 　
17584
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B 0x00000070 bnx2.h 　
17585
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (0xfL<<0) bnx2.h 　
17586
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (0L<<0) bnx2.h 　
17587
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<0) bnx2.h 　
17588
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (2L<<0) bnx2.h 　
17589
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (3L<<0) bnx2.h 　
17590
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (4L<<0) bnx2.h 　
17591
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (5L<<0) bnx2.h 　
17592
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (6L<<0) bnx2.h 　
17593
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (7L<<0) bnx2.h 　
17594
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (0xfL<<0) bnx2.h 　
17595
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<6) bnx2.h 　
17596
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<7) bnx2.h 　
17597
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (0x7L<<8) bnx2.h 　
17598
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (0L<<8) bnx2.h 　
17599
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<8) bnx2.h 　
17600
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (2L<<8) bnx2.h 　
17601
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (4L<<8) bnx2.h 　
17602
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<11) bnx2.h 　
17603
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (0xfL<<12) bnx2.h 　
17604
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (0L<<12) bnx2.h 　
17605
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<12) bnx2.h 　
17606
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (2L<<12) bnx2.h 　
17607
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (4L<<12) bnx2.h 　
17608
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (8L<<12) bnx2.h 　
17609
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<16) bnx2.h 　
17610
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<17) bnx2.h 　
17611
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<18) bnx2.h 　
17612
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (1L<<19) bnx2.h 　
17613
 BNX2_PCICFG_PCI_CLOCK_CONTROL_BBNX2_PCICFG_PCI_CLOCK_CONTROL_B (0xfffL<<20) bnx2.h 　
17614
 BNX2_PCICFG_REG_WINDOW_ADDRESSBNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078 bnx2.h 　
17615
 BNX2_PCICFG_REG_WINDOWBNX2_PCICFG_REG_WINDOW 0x00000080 bnx2.h 　
17616
 BNX2_PCICFG_INT_ACK_CMDBNX2_PCICFG_INT_ACK_CMD 0x00000084 bnx2.h 　
17617
 BNX2_PCICFG_INT_ACK_CMD_INDEXBNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0) bnx2.h 　
17618
 BNX2_PCICFG_INT_ACK_CMD_INDEX_VBNX2_PCICFG_INT_ACK_CMD_INDEX_V (1L<<16) bnx2.h 　
17619
 BNX2_PCICFG_INT_ACK_CMD_USE_INTBNX2_PCICFG_INT_ACK_CMD_USE_INT (1L<<17) bnx2.h 　
17620
 BNX2_PCICFG_INT_ACK_CMD_MASK_INBNX2_PCICFG_INT_ACK_CMD_MASK_IN (1L<<18) bnx2.h 　
17621
 BNX2_PCICFG_STATUS_BIT_SET_CMDBNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088 bnx2.h 　
17622
 BNX2_PCICFG_STATUS_BIT_CLEAR_CMBNX2_PCICFG_STATUS_BIT_CLEAR_CM 0x0000008c bnx2.h 　
17623
 BNX2_PCICFG_MAILBOX_QUEUE_ADDRBNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090 bnx2.h 　
17624
 BNX2_PCICFG_MAILBOX_QUEUE_DATABNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094 bnx2.h 　
17625
 BNX2_PCI_GRC_WINDOW_ADDRBNX2_PCI_GRC_WINDOW_ADDR 0x00000400 bnx2.h 　
17626
 BNX2_PCI_GRC_WINDOW_ADDR_PCI_GRBNX2_PCI_GRC_WINDOW_ADDR_PCI_GR (0x3ffffL<<8) bnx2.h 　
17627
 BNX2_PCI_CONFIG_1BNX2_PCI_CONFIG_1 0x00000404 bnx2.h 　
17628
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8) bnx2.h 　
17629
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (0L<<8) bnx2.h 　
17630
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (1L<<8) bnx2.h 　
17631
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (2L<<8) bnx2.h 　
17632
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (3L<<8) bnx2.h 　
17633
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (4L<<8) bnx2.h 　
17634
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (5L<<8) bnx2.h 　
17635
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (6L<<8) bnx2.h 　
17636
 BNX2_PCI_CONFIG_1_READ_BOUNDARYBNX2_PCI_CONFIG_1_READ_BOUNDARY (7L<<8) bnx2.h 　
17637
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (0x7L<<11) bnx2.h 　
17638
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (0L<<11) bnx2.h 　
17639
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (1L<<11) bnx2.h 　
17640
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (2L<<11) bnx2.h 　
17641
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (3L<<11) bnx2.h 　
17642
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (4L<<11) bnx2.h 　
17643
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (5L<<11) bnx2.h 　
17644
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (6L<<11) bnx2.h 　
17645
 BNX2_PCI_CONFIG_1_WRITE_BOUNDARBNX2_PCI_CONFIG_1_WRITE_BOUNDAR (7L<<11) bnx2.h 　
17646
 BNX2_PCI_CONFIG_2BNX2_PCI_CONFIG_2 0x00000408 bnx2.h 　
17647
 BNX2_PCI_CONFIG_2_BAR1_SIZEBNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0) bnx2.h 　
17648
 BNX2_PCI_CONFIG_2_BAR1_SIZE_DISBNX2_PCI_CONFIG_2_BAR1_SIZE_DIS (0L<<0) bnx2.h 　
17649
 BNX2_PCI_CONFIG_2_BAR1_SIZE_64KBNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0) bnx2.h 　
17650
 BNX2_PCI_CONFIG_2_BAR1_SIZE_128BNX2_PCI_CONFIG_2_BAR1_SIZE_128 (2L<<0) bnx2.h 　
17651
 BNX2_PCI_CONFIG_2_BAR1_SIZE_256BNX2_PCI_CONFIG_2_BAR1_SIZE_256 (3L<<0) bnx2.h 　
17652
 BNX2_PCI_CONFIG_2_BAR1_SIZE_512BNX2_PCI_CONFIG_2_BAR1_SIZE_512 (4L<<0) bnx2.h 　
17653
 BNX2_PCI_CONFIG_2_BAR1_SIZE_1MBNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0) bnx2.h 　
17654
 BNX2_PCI_CONFIG_2_BAR1_SIZE_2MBNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0) bnx2.h 　
17655
 BNX2_PCI_CONFIG_2_BAR1_SIZE_4MBNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0) bnx2.h 　
17656
 BNX2_PCI_CONFIG_2_BAR1_SIZE_8MBNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0) bnx2.h 　
17657
 BNX2_PCI_CONFIG_2_BAR1_SIZE_16MBNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0) bnx2.h 　
17658
 BNX2_PCI_CONFIG_2_BAR1_SIZE_32MBNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0) bnx2.h 　
17659
 BNX2_PCI_CONFIG_2_BAR1_SIZE_64MBNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0) bnx2.h 　
17660
 BNX2_PCI_CONFIG_2_BAR1_SIZE_128BNX2_PCI_CONFIG_2_BAR1_SIZE_128 (12L<<0) bnx2.h 　
17661
 BNX2_PCI_CONFIG_2_BAR1_SIZE_256BNX2_PCI_CONFIG_2_BAR1_SIZE_256 (13L<<0) bnx2.h 　
17662
 BNX2_PCI_CONFIG_2_BAR1_SIZE_512BNX2_PCI_CONFIG_2_BAR1_SIZE_512 (14L<<0) bnx2.h 　
17663
 BNX2_PCI_CONFIG_2_BAR1_SIZE_1GBNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0) bnx2.h 　
17664
 BNX2_PCI_CONFIG_2_BAR1_64ENABNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4) bnx2.h 　
17665
 BNX2_PCI_CONFIG_2_EXP_ROM_RETRYBNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5) bnx2.h 　
17666
 BNX2_PCI_CONFIG_2_CFG_CYCLE_RETBNX2_PCI_CONFIG_2_CFG_CYCLE_RET (1L<<6) bnx2.h 　
17667
 BNX2_PCI_CONFIG_2_FIRST_CFG_DONBNX2_PCI_CONFIG_2_FIRST_CFG_DON (1L<<7) bnx2.h 　
17668
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZEBNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8) bnx2.h 　
17669
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (0L<<8) bnx2.h 　
17670
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (1L<<8) bnx2.h 　
17671
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (2L<<8) bnx2.h 　
17672
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (3L<<8) bnx2.h 　
17673
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (4L<<8) bnx2.h 　
17674
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (5L<<8) bnx2.h 　
17675
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (6L<<8) bnx2.h 　
17676
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (7L<<8) bnx2.h 　
17677
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (8L<<8) bnx2.h 　
17678
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (9L<<8) bnx2.h 　
17679
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (10L<<8) bnx2.h 　
17680
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (11L<<8) bnx2.h 　
17681
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (12L<<8) bnx2.h 　
17682
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (13L<<8) bnx2.h 　
17683
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (14L<<8) bnx2.h 　
17684
 BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_ (15L<<8) bnx2.h 　
17685
 BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMBNX2_PCI_CONFIG_2_MAX_SPLIT_LIM (0x1fL<<16) bnx2.h 　
17686
 BNX2_PCI_CONFIG_2_MAX_READ_LIMIBNX2_PCI_CONFIG_2_MAX_READ_LIMI (0x3L<<21) bnx2.h 　
17687
 BNX2_PCI_CONFIG_2_MAX_READ_LIMIBNX2_PCI_CONFIG_2_MAX_READ_LIMI (0L<<21) bnx2.h 　
17688
 BNX2_PCI_CONFIG_2_MAX_READ_LIMIBNX2_PCI_CONFIG_2_MAX_READ_LIMI (1L<<21) bnx2.h 　
17689
 BNX2_PCI_CONFIG_2_MAX_READ_LIMIBNX2_PCI_CONFIG_2_MAX_READ_LIMI (2L<<21) bnx2.h 　
17690
 BNX2_PCI_CONFIG_2_MAX_READ_LIMIBNX2_PCI_CONFIG_2_MAX_READ_LIMI (3L<<21) bnx2.h 　
17691
 BNX2_PCI_CONFIG_2_FORCE_32_BIT_BNX2_PCI_CONFIG_2_FORCE_32_BIT_ (1L<<23) bnx2.h 　
17692
 BNX2_PCI_CONFIG_2_FORCE_32_BIT_BNX2_PCI_CONFIG_2_FORCE_32_BIT_ (1L<<24) bnx2.h 　
17693
 BNX2_PCI_CONFIG_2_KEEP_REQ_ASSEBNX2_PCI_CONFIG_2_KEEP_REQ_ASSE (1L<<25) bnx2.h 　
17694
 BNX2_PCI_CONFIG_3BNX2_PCI_CONFIG_3 0x0000040c bnx2.h 　
17695
 BNX2_PCI_CONFIG_3_STICKY_BYTEBNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0) bnx2.h 　
17696
 BNX2_PCI_CONFIG_3_FORCE_PMEBNX2_PCI_CONFIG_3_FORCE_PME (1L<<24) bnx2.h 　
17697
 BNX2_PCI_CONFIG_3_PME_STATUSBNX2_PCI_CONFIG_3_PME_STATUS (1L<<25) bnx2.h 　
17698
 BNX2_PCI_CONFIG_3_PME_ENABLEBNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26) bnx2.h 　
17699
 BNX2_PCI_CONFIG_3_PM_STATEBNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27) bnx2.h 　
17700
 BNX2_PCI_CONFIG_3_VAUX_PRESETBNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30) bnx2.h 　
17701
 BNX2_PCI_CONFIG_3_PCI_POWERBNX2_PCI_CONFIG_3_PCI_POWER (1L<<31) bnx2.h 　
17702
 BNX2_PCI_PM_DATA_ABNX2_PCI_PM_DATA_A 0x00000410 bnx2.h 　
17703
 BNX2_PCI_PM_DATA_A_PM_DATA_0_PRBNX2_PCI_PM_DATA_A_PM_DATA_0_PR (0xffL<<0) bnx2.h 　
17704
 BNX2_PCI_PM_DATA_A_PM_DATA_1_PRBNX2_PCI_PM_DATA_A_PM_DATA_1_PR (0xffL<<8) bnx2.h 　
17705
 BNX2_PCI_PM_DATA_A_PM_DATA_2_PRBNX2_PCI_PM_DATA_A_PM_DATA_2_PR (0xffL<<16) bnx2.h 　
17706
 BNX2_PCI_PM_DATA_A_PM_DATA_3_PRBNX2_PCI_PM_DATA_A_PM_DATA_3_PR (0xffL<<24) bnx2.h 　
17707
 BNX2_PCI_PM_DATA_BBNX2_PCI_PM_DATA_B 0x00000414 bnx2.h 　
17708
 BNX2_PCI_PM_DATA_B_PM_DATA_4_PRBNX2_PCI_PM_DATA_B_PM_DATA_4_PR (0xffL<<0) bnx2.h 　
17709
 BNX2_PCI_PM_DATA_B_PM_DATA_5_PRBNX2_PCI_PM_DATA_B_PM_DATA_5_PR (0xffL<<8) bnx2.h 　
17710
 BNX2_PCI_PM_DATA_B_PM_DATA_6_PRBNX2_PCI_PM_DATA_B_PM_DATA_6_PR (0xffL<<16) bnx2.h 　
17711
 BNX2_PCI_PM_DATA_B_PM_DATA_7_PRBNX2_PCI_PM_DATA_B_PM_DATA_7_PR (0xffL<<24) bnx2.h 　
17712
 BNX2_PCI_SWAP_DIAG0BNX2_PCI_SWAP_DIAG0 0x00000418 bnx2.h 　
17713
 BNX2_PCI_SWAP_DIAG1BNX2_PCI_SWAP_DIAG1 0x0000041c bnx2.h 　
17714
 BNX2_PCI_EXP_ROM_ADDRBNX2_PCI_EXP_ROM_ADDR 0x00000420 bnx2.h 　
17715
 BNX2_PCI_EXP_ROM_ADDR_ADDRESSBNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2) bnx2.h 　
17716
 BNX2_PCI_EXP_ROM_ADDR_REQBNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31) bnx2.h 　
17717
 BNX2_PCI_EXP_ROM_DATABNX2_PCI_EXP_ROM_DATA 0x00000424 bnx2.h 　
17718
 BNX2_PCI_VPD_INTFBNX2_PCI_VPD_INTF 0x00000428 bnx2.h 　
17719
 BNX2_PCI_VPD_INTF_INTF_REQBNX2_PCI_VPD_INTF_INTF_REQ (1L<<0) bnx2.h 　
17720
 BNX2_PCI_VPD_ADDR_FLAGBNX2_PCI_VPD_ADDR_FLAG 0x0000042c bnx2.h 　
17721
 BNX2_PCI_VPD_ADDR_FLAG_ADDRESSBNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fff<<2) bnx2.h 　
17722
 BNX2_PCI_VPD_ADDR_FLAG_WRBNX2_PCI_VPD_ADDR_FLAG_WR (1<<15) bnx2.h 　
17723
 BNX2_PCI_VPD_DATABNX2_PCI_VPD_DATA 0x00000430 bnx2.h 　
17724
 BNX2_PCI_ID_VAL1BNX2_PCI_ID_VAL1 0x00000434 bnx2.h 　
17725
 BNX2_PCI_ID_VAL1_DEVICE_IDBNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0) bnx2.h 　
17726
 BNX2_PCI_ID_VAL1_VENDOR_IDBNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16) bnx2.h 　
17727
 BNX2_PCI_ID_VAL2BNX2_PCI_ID_VAL2 0x00000438 bnx2.h 　
17728
 BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDBNX2_PCI_ID_VAL2_SUBSYSTEM_VEND (0xffffL<<0) bnx2.h 　
17729
 BNX2_PCI_ID_VAL2_SUBSYSTEM_IDBNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16) bnx2.h 　
17730
 BNX2_PCI_ID_VAL3BNX2_PCI_ID_VAL3 0x0000043c bnx2.h 　
17731
 BNX2_PCI_ID_VAL3_CLASS_CODEBNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0) bnx2.h 　
17732
 BNX2_PCI_ID_VAL3_REVISION_IDBNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24) bnx2.h 　
17733
 BNX2_PCI_ID_VAL4BNX2_PCI_ID_VAL4 0x00000440 bnx2.h 　
17734
 BNX2_PCI_ID_VAL4_CAP_ENABNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0) bnx2.h 　
17735
 BNX2_PCI_ID_VAL4_CAP_ENA_0BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0) bnx2.h 　
17736
 BNX2_PCI_ID_VAL4_CAP_ENA_1BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0) bnx2.h 　
17737
 BNX2_PCI_ID_VAL4_CAP_ENA_2BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0) bnx2.h 　
17738
 BNX2_PCI_ID_VAL4_CAP_ENA_3BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0) bnx2.h 　
17739
 BNX2_PCI_ID_VAL4_CAP_ENA_4BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0) bnx2.h 　
17740
 BNX2_PCI_ID_VAL4_CAP_ENA_5BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0) bnx2.h 　
17741
 BNX2_PCI_ID_VAL4_CAP_ENA_6BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0) bnx2.h 　
17742
 BNX2_PCI_ID_VAL4_CAP_ENA_7BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0) bnx2.h 　
17743
 BNX2_PCI_ID_VAL4_CAP_ENA_8BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0) bnx2.h 　
17744
 BNX2_PCI_ID_VAL4_CAP_ENA_9BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0) bnx2.h 　
17745
 BNX2_PCI_ID_VAL4_CAP_ENA_10BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0) bnx2.h 　
17746
 BNX2_PCI_ID_VAL4_CAP_ENA_11BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0) bnx2.h 　
17747
 BNX2_PCI_ID_VAL4_CAP_ENA_12BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0) bnx2.h 　
17748
 BNX2_PCI_ID_VAL4_CAP_ENA_13BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0) bnx2.h 　
17749
 BNX2_PCI_ID_VAL4_CAP_ENA_14BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0) bnx2.h 　
17750
 BNX2_PCI_ID_VAL4_CAP_ENA_15BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0) bnx2.h 　
17751
 BNX2_PCI_ID_VAL4_PM_SCALE_PRGBNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6) bnx2.h 　
17752
 BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6) bnx2.h 　
17753
 BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6) bnx2.h 　
17754
 BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6) bnx2.h 　
17755
 BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6) bnx2.h 　
17756
 BNX2_PCI_ID_VAL4_MSI_LIMITBNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9) bnx2.h 　
17757
 BNX2_PCI_ID_VAL4_MSI_ADVERTIZEBNX2_PCI_ID_VAL4_MSI_ADVERTIZE (0x7L<<12) bnx2.h 　
17758
 BNX2_PCI_ID_VAL4_MSI_ENABLEBNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15) bnx2.h 　
17759
 BNX2_PCI_ID_VAL4_MAX_64_ADVERTIBNX2_PCI_ID_VAL4_MAX_64_ADVERTI (1L<<16) bnx2.h 　
17760
 BNX2_PCI_ID_VAL4_MAX_133_ADVERTBNX2_PCI_ID_VAL4_MAX_133_ADVERT (1L<<17) bnx2.h 　
17761
 BNX2_PCI_ID_VAL4_MAX_MEM_READ_SBNX2_PCI_ID_VAL4_MAX_MEM_READ_S (0x3L<<21) bnx2.h 　
17762
 BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZEBNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE (0x7L<<23) bnx2.h 　
17763
 BNX2_PCI_ID_VAL4_MAX_CUMULATIVEBNX2_PCI_ID_VAL4_MAX_CUMULATIVE (0x7L<<26) bnx2.h 　
17764
 BNX2_PCI_ID_VAL5BNX2_PCI_ID_VAL5 0x00000444 bnx2.h 　
17765
 BNX2_PCI_ID_VAL5_D1_SUPPORTBNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0) bnx2.h 　
17766
 BNX2_PCI_ID_VAL5_D2_SUPPORTBNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1) bnx2.h 　
17767
 BNX2_PCI_ID_VAL5_PME_IN_D0BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2) bnx2.h 　
17768
 BNX2_PCI_ID_VAL5_PME_IN_D1BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3) bnx2.h 　
17769
 BNX2_PCI_ID_VAL5_PME_IN_D2BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4) bnx2.h 　
17770
 BNX2_PCI_ID_VAL5_PME_IN_D3_HOTBNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5) bnx2.h 　
17771
 BNX2_PCI_PCIX_EXTENDED_STATUSBNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448 bnx2.h 　
17772
 BNX2_PCI_PCIX_EXTENDED_STATUS_NBNX2_PCI_PCIX_EXTENDED_STATUS_N (1L<<8) bnx2.h 　
17773
 BNX2_PCI_PCIX_EXTENDED_STATUS_LBNX2_PCI_PCIX_EXTENDED_STATUS_L (1L<<9) bnx2.h 　
17774
 BNX2_PCI_PCIX_EXTENDED_STATUS_SBNX2_PCI_PCIX_EXTENDED_STATUS_S (0xfL<<16) bnx2.h 　
17775
 BNX2_PCI_PCIX_EXTENDED_STATUS_SBNX2_PCI_PCIX_EXTENDED_STATUS_S (0xffL<<24) bnx2.h 　
17776
 BNX2_PCI_ID_VAL6BNX2_PCI_ID_VAL6 0x0000044c bnx2.h 　
17777
 BNX2_PCI_ID_VAL6_MAX_LATBNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0) bnx2.h 　
17778
 BNX2_PCI_ID_VAL6_MIN_GNTBNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8) bnx2.h 　
17779
 BNX2_PCI_ID_VAL6_BISTBNX2_PCI_ID_VAL6_BIST (0xffL<<16) bnx2.h 　
17780
 BNX2_PCI_MSI_DATABNX2_PCI_MSI_DATA 0x00000450 bnx2.h 　
17781
 BNX2_PCI_MSI_DATA_PCI_MSI_DATABNX2_PCI_MSI_DATA_PCI_MSI_DATA (0xffffL<<0) bnx2.h 　
17782
 BNX2_PCI_MSI_ADDR_HBNX2_PCI_MSI_ADDR_H 0x00000454 bnx2.h 　
17783
 BNX2_PCI_MSI_ADDR_LBNX2_PCI_MSI_ADDR_L 0x00000458 bnx2.h 　
17784
 BNX2_MISC_COMMANDBNX2_MISC_COMMAND 0x00000800 bnx2.h 　
17785
 BNX2_MISC_COMMAND_ENABLE_ALLBNX2_MISC_COMMAND_ENABLE_ALL (1L<<0) bnx2.h 　
17786
 BNX2_MISC_COMMAND_DISABLE_ALLBNX2_MISC_COMMAND_DISABLE_ALL (1L<<1) bnx2.h 　
17787
 BNX2_MISC_COMMAND_CORE_RESETBNX2_MISC_COMMAND_CORE_RESET (1L<<4) bnx2.h 　
17788
 BNX2_MISC_COMMAND_HARD_RESETBNX2_MISC_COMMAND_HARD_RESET (1L<<5) bnx2.h 　
17789
 BNX2_MISC_COMMAND_PAR_ERRORBNX2_MISC_COMMAND_PAR_ERROR (1L<<8) bnx2.h 　
17790
 BNX2_MISC_COMMAND_PAR_ERR_RAMBNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16) bnx2.h 　
17791
 BNX2_MISC_CFGBNX2_MISC_CFG 0x00000804 bnx2.h 　
17792
 BNX2_MISC_CFG_PCI_GRC_TMOUTBNX2_MISC_CFG_PCI_GRC_TMOUT (1L<<0) bnx2.h 　
17793
 BNX2_MISC_CFG_NVM_WR_ENBNX2_MISC_CFG_NVM_WR_EN (0x3L<<1) bnx2.h 　
17794
 BNX2_MISC_CFG_NVM_WR_EN_PROTECTBNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1) bnx2.h 　
17795
 BNX2_MISC_CFG_NVM_WR_EN_PCIBNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1) bnx2.h 　
17796
 BNX2_MISC_CFG_NVM_WR_EN_ALLOWBNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1) bnx2.h 　
17797
 BNX2_MISC_CFG_NVM_WR_EN_ALLOW2BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1) bnx2.h 　
17798
 BNX2_MISC_CFG_BIST_ENBNX2_MISC_CFG_BIST_EN (1L<<3) bnx2.h 　
17799
 BNX2_MISC_CFG_CK25_OUT_ALT_SRCBNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4) bnx2.h 　
17800
 BNX2_MISC_CFG_BYPASS_BSCANBNX2_MISC_CFG_BYPASS_BSCAN (1L<<5) bnx2.h 　
17801
 BNX2_MISC_CFG_BYPASS_EJTAGBNX2_MISC_CFG_BYPASS_EJTAG (1L<<6) bnx2.h 　
17802
 BNX2_MISC_CFG_CLK_CTL_OVERRIDEBNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7) bnx2.h 　
17803
 BNX2_MISC_CFG_LEDMODEBNX2_MISC_CFG_LEDMODE (0x3L<<8) bnx2.h 　
17804
 BNX2_MISC_CFG_LEDMODE_MACBNX2_MISC_CFG_LEDMODE_MAC (0L<<8) bnx2.h 　
17805
 BNX2_MISC_CFG_LEDMODE_GPHY1BNX2_MISC_CFG_LEDMODE_GPHY1 (1L<<8) bnx2.h 　
17806
 BNX2_MISC_CFG_LEDMODE_GPHY2BNX2_MISC_CFG_LEDMODE_GPHY2 (2L<<8) bnx2.h 　
17807
 BNX2_MISC_IDBNX2_MISC_ID 0x00000808 bnx2.h 　
17808
 BNX2_MISC_ID_BOND_IDBNX2_MISC_ID_BOND_ID (0xfL<<0) bnx2.h 　
17809
 BNX2_MISC_ID_CHIP_METALBNX2_MISC_ID_CHIP_METAL (0xffL<<4) bnx2.h 　
17810
 BNX2_MISC_ID_CHIP_REVBNX2_MISC_ID_CHIP_REV (0xfL<<12) bnx2.h 　
17811
 BNX2_MISC_ID_CHIP_NUMBNX2_MISC_ID_CHIP_NUM (0xffffL<<16) bnx2.h 　
17812
 BNX2_MISC_ENABLE_STATUS_BITSBNX2_MISC_ENABLE_STATUS_BITS 0x0000080c bnx2.h 　
17813
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<0) bnx2.h 　
17814
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<1) bnx2.h 　
17815
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<2) bnx2.h 　
17816
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<3) bnx2.h 　
17817
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<4) bnx2.h 　
17818
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<5) bnx2.h 　
17819
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<6) bnx2.h 　
17820
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<7) bnx2.h 　
17821
 BNX2_MISC_ENABLE_STATUS_BITS_TXBNX2_MISC_ENABLE_STATUS_BITS_TX (1L<<8) bnx2.h 　
17822
 BNX2_MISC_ENABLE_STATUS_BITS_EMBNX2_MISC_ENABLE_STATUS_BITS_EM (1L<<9) bnx2.h 　
17823
 BNX2_MISC_ENABLE_STATUS_BITS_RXBNX2_MISC_ENABLE_STATUS_BITS_RX (1L<<10) bnx2.h 　
17824
 BNX2_MISC_ENABLE_STATUS_BITS_RXBNX2_MISC_ENABLE_STATUS_BITS_RX (1L<<11) bnx2.h 　
17825
 BNX2_MISC_ENABLE_STATUS_BITS_RXBNX2_MISC_ENABLE_STATUS_BITS_RX (1L<<12) bnx2.h 　
17826
 BNX2_MISC_ENABLE_STATUS_BITS_RXBNX2_MISC_ENABLE_STATUS_BITS_RX (1L<<13) bnx2.h 　
17827
 BNX2_MISC_ENABLE_STATUS_BITS_RXBNX2_MISC_ENABLE_STATUS_BITS_RX (1L<<14) bnx2.h 　
17828
 BNX2_MISC_ENABLE_STATUS_BITS_RXBNX2_MISC_ENABLE_STATUS_BITS_RX (1L<<15) bnx2.h 　
17829
 BNX2_MISC_ENABLE_STATUS_BITS_RXBNX2_MISC_ENABLE_STATUS_BITS_RX (1L<<16) bnx2.h 　
17830
 BNX2_MISC_ENABLE_STATUS_BITS_RXBNX2_MISC_ENABLE_STATUS_BITS_RX (1L<<17) bnx2.h 　
17831
 BNX2_MISC_ENABLE_STATUS_BITS_COBNX2_MISC_ENABLE_STATUS_BITS_CO (1L<<18) bnx2.h 　
17832
 BNX2_MISC_ENABLE_STATUS_BITS_HOBNX2_MISC_ENABLE_STATUS_BITS_HO (1L<<19) bnx2.h 　
17833
 BNX2_MISC_ENABLE_STATUS_BITS_MABNX2_MISC_ENABLE_STATUS_BITS_MA (1L<<20) bnx2.h 　
17834
 BNX2_MISC_ENABLE_STATUS_BITS_COBNX2_MISC_ENABLE_STATUS_BITS_CO (1L<<21) bnx2.h 　
17835
 BNX2_MISC_ENABLE_STATUS_BITS_CMBNX2_MISC_ENABLE_STATUS_BITS_CM (1L<<22) bnx2.h 　
17836
 BNX2_MISC_ENABLE_STATUS_BITS_CMBNX2_MISC_ENABLE_STATUS_BITS_CM (1L<<23) bnx2.h 　
17837
 BNX2_MISC_ENABLE_STATUS_BITS_MGBNX2_MISC_ENABLE_STATUS_BITS_MG (1L<<24) bnx2.h 　
17838
 BNX2_MISC_ENABLE_STATUS_BITS_TIBNX2_MISC_ENABLE_STATUS_BITS_TI (1L<<25) bnx2.h 　
17839
 BNX2_MISC_ENABLE_STATUS_BITS_DMBNX2_MISC_ENABLE_STATUS_BITS_DM (1L<<26) bnx2.h 　
17840
 BNX2_MISC_ENABLE_STATUS_BITS_UMBNX2_MISC_ENABLE_STATUS_BITS_UM (1L<<27) bnx2.h 　
17841
 BNX2_MISC_ENABLE_SET_BITSBNX2_MISC_ENABLE_SET_BITS 0x00000810 bnx2.h 　
17842
 BNX2_MISC_ENABLE_SET_BITS_TX_SCBNX2_MISC_ENABLE_SET_BITS_TX_SC (1L<<0) bnx2.h 　
17843
 BNX2_MISC_ENABLE_SET_BITS_TX_BDBNX2_MISC_ENABLE_SET_BITS_TX_BD (1L<<1) bnx2.h 　
17844
 BNX2_MISC_ENABLE_SET_BITS_TX_BDBNX2_MISC_ENABLE_SET_BITS_TX_BD (1L<<2) bnx2.h 　
17845
 BNX2_MISC_ENABLE_SET_BITS_TX_PRBNX2_MISC_ENABLE_SET_BITS_TX_PR (1L<<3) bnx2.h 　
17846
 BNX2_MISC_ENABLE_SET_BITS_TX_DMBNX2_MISC_ENABLE_SET_BITS_TX_DM (1L<<4) bnx2.h 　
17847
 BNX2_MISC_ENABLE_SET_BITS_TX_PABNX2_MISC_ENABLE_SET_BITS_TX_PA (1L<<5) bnx2.h 　
17848
 BNX2_MISC_ENABLE_SET_BITS_TX_PABNX2_MISC_ENABLE_SET_BITS_TX_PA (1L<<6) bnx2.h 　
17849
 BNX2_MISC_ENABLE_SET_BITS_TX_HEBNX2_MISC_ENABLE_SET_BITS_TX_HE (1L<<7) bnx2.h 　
17850
 BNX2_MISC_ENABLE_SET_BITS_TX_ASBNX2_MISC_ENABLE_SET_BITS_TX_AS (1L<<8) bnx2.h 　
17851
 BNX2_MISC_ENABLE_SET_BITS_EMAC_BNX2_MISC_ENABLE_SET_BITS_EMAC_ (1L<<9) bnx2.h 　
17852
 BNX2_MISC_ENABLE_SET_BITS_RX_PABNX2_MISC_ENABLE_SET_BITS_RX_PA (1L<<10) bnx2.h 　
17853
 BNX2_MISC_ENABLE_SET_BITS_RX_PABNX2_MISC_ENABLE_SET_BITS_RX_PA (1L<<11) bnx2.h 　
17854
 BNX2_MISC_ENABLE_SET_BITS_RX_MBBNX2_MISC_ENABLE_SET_BITS_RX_MB (1L<<12) bnx2.h 　
17855
 BNX2_MISC_ENABLE_SET_BITS_RX_LOBNX2_MISC_ENABLE_SET_BITS_RX_LO (1L<<13) bnx2.h 　
17856
 BNX2_MISC_ENABLE_SET_BITS_RX_PRBNX2_MISC_ENABLE_SET_BITS_RX_PR (1L<<14) bnx2.h 　
17857
 BNX2_MISC_ENABLE_SET_BITS_RX_V2BNX2_MISC_ENABLE_SET_BITS_RX_V2 (1L<<15) bnx2.h 　
17858
 BNX2_MISC_ENABLE_SET_BITS_RX_BDBNX2_MISC_ENABLE_SET_BITS_RX_BD (1L<<16) bnx2.h 　
17859
 BNX2_MISC_ENABLE_SET_BITS_RX_DMBNX2_MISC_ENABLE_SET_BITS_RX_DM (1L<<17) bnx2.h 　
17860
 BNX2_MISC_ENABLE_SET_BITS_COMPLBNX2_MISC_ENABLE_SET_BITS_COMPL (1L<<18) bnx2.h 　
17861
 BNX2_MISC_ENABLE_SET_BITS_HOST_BNX2_MISC_ENABLE_SET_BITS_HOST_ (1L<<19) bnx2.h 　
17862
 BNX2_MISC_ENABLE_SET_BITS_MAILBBNX2_MISC_ENABLE_SET_BITS_MAILB (1L<<20) bnx2.h 　
17863
 BNX2_MISC_ENABLE_SET_BITS_CONTEBNX2_MISC_ENABLE_SET_BITS_CONTE (1L<<21) bnx2.h 　
17864
 BNX2_MISC_ENABLE_SET_BITS_CMD_SBNX2_MISC_ENABLE_SET_BITS_CMD_S (1L<<22) bnx2.h 　
17865
 BNX2_MISC_ENABLE_SET_BITS_CMD_PBNX2_MISC_ENABLE_SET_BITS_CMD_P (1L<<23) bnx2.h 　
17866
 BNX2_MISC_ENABLE_SET_BITS_MGMT_BNX2_MISC_ENABLE_SET_BITS_MGMT_ (1L<<24) bnx2.h 　
17867
 BNX2_MISC_ENABLE_SET_BITS_TIMERBNX2_MISC_ENABLE_SET_BITS_TIMER (1L<<25) bnx2.h 　
17868
 BNX2_MISC_ENABLE_SET_BITS_DMA_EBNX2_MISC_ENABLE_SET_BITS_DMA_E (1L<<26) bnx2.h 　
17869
 BNX2_MISC_ENABLE_SET_BITS_UMP_EBNX2_MISC_ENABLE_SET_BITS_UMP_E (1L<<27) bnx2.h 　
17870
 BNX2_MISC_ENABLE_CLR_BITSBNX2_MISC_ENABLE_CLR_BITS 0x00000814 bnx2.h 　
17871
 BNX2_MISC_ENABLE_CLR_BITS_TX_SCBNX2_MISC_ENABLE_CLR_BITS_TX_SC (1L<<0) bnx2.h 　
17872
 BNX2_MISC_ENABLE_CLR_BITS_TX_BDBNX2_MISC_ENABLE_CLR_BITS_TX_BD (1L<<1) bnx2.h 　
17873
 BNX2_MISC_ENABLE_CLR_BITS_TX_BDBNX2_MISC_ENABLE_CLR_BITS_TX_BD (1L<<2) bnx2.h 　
17874
 BNX2_MISC_ENABLE_CLR_BITS_TX_PRBNX2_MISC_ENABLE_CLR_BITS_TX_PR (1L<<3) bnx2.h 　
17875
 BNX2_MISC_ENABLE_CLR_BITS_TX_DMBNX2_MISC_ENABLE_CLR_BITS_TX_DM (1L<<4) bnx2.h 　
17876
 BNX2_MISC_ENABLE_CLR_BITS_TX_PABNX2_MISC_ENABLE_CLR_BITS_TX_PA (1L<<5) bnx2.h 　
17877
 BNX2_MISC_ENABLE_CLR_BITS_TX_PABNX2_MISC_ENABLE_CLR_BITS_TX_PA (1L<<6) bnx2.h 　
17878
 BNX2_MISC_ENABLE_CLR_BITS_TX_HEBNX2_MISC_ENABLE_CLR_BITS_TX_HE (1L<<7) bnx2.h 　
17879
 BNX2_MISC_ENABLE_CLR_BITS_TX_ASBNX2_MISC_ENABLE_CLR_BITS_TX_AS (1L<<8) bnx2.h 　
17880
 BNX2_MISC_ENABLE_CLR_BITS_EMAC_BNX2_MISC_ENABLE_CLR_BITS_EMAC_ (1L<<9) bnx2.h 　
17881
 BNX2_MISC_ENABLE_CLR_BITS_RX_PABNX2_MISC_ENABLE_CLR_BITS_RX_PA (1L<<10) bnx2.h 　
17882
 BNX2_MISC_ENABLE_CLR_BITS_RX_PABNX2_MISC_ENABLE_CLR_BITS_RX_PA (1L<<11) bnx2.h 　
17883
 BNX2_MISC_ENABLE_CLR_BITS_RX_MBBNX2_MISC_ENABLE_CLR_BITS_RX_MB (1L<<12) bnx2.h 　
17884
 BNX2_MISC_ENABLE_CLR_BITS_RX_LOBNX2_MISC_ENABLE_CLR_BITS_RX_LO (1L<<13) bnx2.h 　
17885
 BNX2_MISC_ENABLE_CLR_BITS_RX_PRBNX2_MISC_ENABLE_CLR_BITS_RX_PR (1L<<14) bnx2.h 　
17886
 BNX2_MISC_ENABLE_CLR_BITS_RX_V2BNX2_MISC_ENABLE_CLR_BITS_RX_V2 (1L<<15) bnx2.h 　
17887
 BNX2_MISC_ENABLE_CLR_BITS_RX_BDBNX2_MISC_ENABLE_CLR_BITS_RX_BD (1L<<16) bnx2.h 　
17888
 BNX2_MISC_ENABLE_CLR_BITS_RX_DMBNX2_MISC_ENABLE_CLR_BITS_RX_DM (1L<<17) bnx2.h 　
17889
 BNX2_MISC_ENABLE_CLR_BITS_COMPLBNX2_MISC_ENABLE_CLR_BITS_COMPL (1L<<18) bnx2.h 　
17890
 BNX2_MISC_ENABLE_CLR_BITS_HOST_BNX2_MISC_ENABLE_CLR_BITS_HOST_ (1L<<19) bnx2.h 　
17891
 BNX2_MISC_ENABLE_CLR_BITS_MAILBBNX2_MISC_ENABLE_CLR_BITS_MAILB (1L<<20) bnx2.h 　
17892
 BNX2_MISC_ENABLE_CLR_BITS_CONTEBNX2_MISC_ENABLE_CLR_BITS_CONTE (1L<<21) bnx2.h 　
17893
 BNX2_MISC_ENABLE_CLR_BITS_CMD_SBNX2_MISC_ENABLE_CLR_BITS_CMD_S (1L<<22) bnx2.h 　
17894
 BNX2_MISC_ENABLE_CLR_BITS_CMD_PBNX2_MISC_ENABLE_CLR_BITS_CMD_P (1L<<23) bnx2.h 　
17895
 BNX2_MISC_ENABLE_CLR_BITS_MGMT_BNX2_MISC_ENABLE_CLR_BITS_MGMT_ (1L<<24) bnx2.h 　
17896
 BNX2_MISC_ENABLE_CLR_BITS_TIMERBNX2_MISC_ENABLE_CLR_BITS_TIMER (1L<<25) bnx2.h 　
17897
 BNX2_MISC_ENABLE_CLR_BITS_DMA_EBNX2_MISC_ENABLE_CLR_BITS_DMA_E (1L<<26) bnx2.h 　
17898
 BNX2_MISC_ENABLE_CLR_BITS_UMP_EBNX2_MISC_ENABLE_CLR_BITS_UMP_E (1L<<27) bnx2.h 　
17899
 BNX2_MISC_CLOCK_CONTROL_BITSBNX2_MISC_CLOCK_CONTROL_BITS 0x00000818 bnx2.h 　
17900
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (0xfL<<0) bnx2.h 　
17901
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (0L<<0) bnx2.h 　
17902
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (1L<<0) bnx2.h 　
17903
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (2L<<0) bnx2.h 　
17904
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (3L<<0) bnx2.h 　
17905
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (4L<<0) bnx2.h 　
17906
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (5L<<0) bnx2.h 　
17907
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (6L<<0) bnx2.h 　
17908
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (7L<<0) bnx2.h 　
17909
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (0xfL<<0) bnx2.h 　
17910
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (1L<<6) bnx2.h 　
17911
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (1L<<7) bnx2.h 　
17912
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (0x7L<<8) bnx2.h 　
17913
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (0L<<8) bnx2.h 　
17914
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (1L<<8) bnx2.h 　
17915
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (2L<<8) bnx2.h 　
17916
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (4L<<8) bnx2.h 　
17917
 BNX2_MISC_CLOCK_CONTROL_BITS_PLBNX2_MISC_CLOCK_CONTROL_BITS_PL (1L<<11) bnx2.h 　
17918
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (0xfL<<12) bnx2.h 　
17919
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (0L<<12) bnx2.h 　
17920
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (1L<<12) bnx2.h 　
17921
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (2L<<12) bnx2.h 　
17922
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (4L<<12) bnx2.h 　
17923
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (8L<<12) bnx2.h 　
17924
 BNX2_MISC_CLOCK_CONTROL_BITS_COBNX2_MISC_CLOCK_CONTROL_BITS_CO (1L<<16) bnx2.h 　
17925
 BNX2_MISC_CLOCK_CONTROL_BITS_PCBNX2_MISC_CLOCK_CONTROL_BITS_PC (1L<<17) bnx2.h 　
17926
 BNX2_MISC_CLOCK_CONTROL_BITS_REBNX2_MISC_CLOCK_CONTROL_BITS_RE (1L<<18) bnx2.h 　
17927
 BNX2_MISC_CLOCK_CONTROL_BITS_USBNX2_MISC_CLOCK_CONTROL_BITS_US (1L<<19) bnx2.h 　
17928
 BNX2_MISC_CLOCK_CONTROL_BITS_REBNX2_MISC_CLOCK_CONTROL_BITS_RE (0xfffL<<20) bnx2.h 　
17929
 BNX2_MISC_GPIOBNX2_MISC_GPIO 0x0000081c bnx2.h 　
17930
 BNX2_MISC_GPIO_VALUEBNX2_MISC_GPIO_VALUE (0xffL<<0) bnx2.h 　
17931
 BNX2_MISC_GPIO_SETBNX2_MISC_GPIO_SET (0xffL<<8) bnx2.h 　
17932
 BNX2_MISC_GPIO_CLRBNX2_MISC_GPIO_CLR (0xffL<<16) bnx2.h 　
17933
 BNX2_MISC_GPIO_FLOATBNX2_MISC_GPIO_FLOAT (0xffL<<24) bnx2.h 　
17934
 BNX2_MISC_GPIO_INTBNX2_MISC_GPIO_INT 0x00000820 bnx2.h 　
17935
 BNX2_MISC_GPIO_INT_INT_STATEBNX2_MISC_GPIO_INT_INT_STATE (0xfL<<0) bnx2.h 　
17936
 BNX2_MISC_GPIO_INT_OLD_VALUEBNX2_MISC_GPIO_INT_OLD_VALUE (0xfL<<8) bnx2.h 　
17937
 BNX2_MISC_GPIO_INT_OLD_SETBNX2_MISC_GPIO_INT_OLD_SET (0xfL<<16) bnx2.h 　
17938
 BNX2_MISC_GPIO_INT_OLD_CLRBNX2_MISC_GPIO_INT_OLD_CLR (0xfL<<24) bnx2.h 　
17939
 BNX2_MISC_CONFIG_LFSRBNX2_MISC_CONFIG_LFSR 0x00000824 bnx2.h 　
17940
 BNX2_MISC_CONFIG_LFSR_DIVBNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0) bnx2.h 　
17941
 BNX2_MISC_LFSR_MASK_BITSBNX2_MISC_LFSR_MASK_BITS 0x00000828 bnx2.h 　
17942
 BNX2_MISC_LFSR_MASK_BITS_TX_SCHBNX2_MISC_LFSR_MASK_BITS_TX_SCH (1L<<0) bnx2.h 　
17943
 BNX2_MISC_LFSR_MASK_BITS_TX_BD_BNX2_MISC_LFSR_MASK_BITS_TX_BD_ (1L<<1) bnx2.h 　
17944
 BNX2_MISC_LFSR_MASK_BITS_TX_BD_BNX2_MISC_LFSR_MASK_BITS_TX_BD_ (1L<<2) bnx2.h 　
17945
 BNX2_MISC_LFSR_MASK_BITS_TX_PROBNX2_MISC_LFSR_MASK_BITS_TX_PRO (1L<<3) bnx2.h 　
17946
 BNX2_MISC_LFSR_MASK_BITS_TX_DMABNX2_MISC_LFSR_MASK_BITS_TX_DMA (1L<<4) bnx2.h 　
17947
 BNX2_MISC_LFSR_MASK_BITS_TX_PATBNX2_MISC_LFSR_MASK_BITS_TX_PAT (1L<<5) bnx2.h 　
17948
 BNX2_MISC_LFSR_MASK_BITS_TX_PAYBNX2_MISC_LFSR_MASK_BITS_TX_PAY (1L<<6) bnx2.h 　
17949
 BNX2_MISC_LFSR_MASK_BITS_TX_HEABNX2_MISC_LFSR_MASK_BITS_TX_HEA (1L<<7) bnx2.h 　
17950
 BNX2_MISC_LFSR_MASK_BITS_TX_ASSBNX2_MISC_LFSR_MASK_BITS_TX_ASS (1L<<8) bnx2.h 　
17951
 BNX2_MISC_LFSR_MASK_BITS_EMAC_EBNX2_MISC_LFSR_MASK_BITS_EMAC_E (1L<<9) bnx2.h 　
17952
 BNX2_MISC_LFSR_MASK_BITS_RX_PARBNX2_MISC_LFSR_MASK_BITS_RX_PAR (1L<<10) bnx2.h 　
17953
 BNX2_MISC_LFSR_MASK_BITS_RX_PARBNX2_MISC_LFSR_MASK_BITS_RX_PAR (1L<<11) bnx2.h 　
17954
 BNX2_MISC_LFSR_MASK_BITS_RX_MBUBNX2_MISC_LFSR_MASK_BITS_RX_MBU (1L<<12) bnx2.h 　
17955
 BNX2_MISC_LFSR_MASK_BITS_RX_LOOBNX2_MISC_LFSR_MASK_BITS_RX_LOO (1L<<13) bnx2.h 　
17956
 BNX2_MISC_LFSR_MASK_BITS_RX_PROBNX2_MISC_LFSR_MASK_BITS_RX_PRO (1L<<14) bnx2.h 　
17957
 BNX2_MISC_LFSR_MASK_BITS_RX_V2PBNX2_MISC_LFSR_MASK_BITS_RX_V2P (1L<<15) bnx2.h 　
17958
 BNX2_MISC_LFSR_MASK_BITS_RX_BD_BNX2_MISC_LFSR_MASK_BITS_RX_BD_ (1L<<16) bnx2.h 　
17959
 BNX2_MISC_LFSR_MASK_BITS_RX_DMABNX2_MISC_LFSR_MASK_BITS_RX_DMA (1L<<17) bnx2.h 　
17960
 BNX2_MISC_LFSR_MASK_BITS_COMPLEBNX2_MISC_LFSR_MASK_BITS_COMPLE (1L<<18) bnx2.h 　
17961
 BNX2_MISC_LFSR_MASK_BITS_HOST_CBNX2_MISC_LFSR_MASK_BITS_HOST_C (1L<<19) bnx2.h 　
17962
 BNX2_MISC_LFSR_MASK_BITS_MAILBOBNX2_MISC_LFSR_MASK_BITS_MAILBO (1L<<20) bnx2.h 　
17963
 BNX2_MISC_LFSR_MASK_BITS_CONTEXBNX2_MISC_LFSR_MASK_BITS_CONTEX (1L<<21) bnx2.h 　
17964
 BNX2_MISC_LFSR_MASK_BITS_CMD_SCBNX2_MISC_LFSR_MASK_BITS_CMD_SC (1L<<22) bnx2.h 　
17965
 BNX2_MISC_LFSR_MASK_BITS_CMD_PRBNX2_MISC_LFSR_MASK_BITS_CMD_PR (1L<<23) bnx2.h 　
17966
 BNX2_MISC_LFSR_MASK_BITS_MGMT_PBNX2_MISC_LFSR_MASK_BITS_MGMT_P (1L<<24) bnx2.h 　
17967
 BNX2_MISC_LFSR_MASK_BITS_TIMER_BNX2_MISC_LFSR_MASK_BITS_TIMER_ (1L<<25) bnx2.h 　
17968
 BNX2_MISC_LFSR_MASK_BITS_DMA_ENBNX2_MISC_LFSR_MASK_BITS_DMA_EN (1L<<26) bnx2.h 　
17969
 BNX2_MISC_LFSR_MASK_BITS_UMP_ENBNX2_MISC_LFSR_MASK_BITS_UMP_EN (1L<<27) bnx2.h 　
17970
 BNX2_MISC_ARB_REQ0BNX2_MISC_ARB_REQ0 0x0000082c bnx2.h 　
17971
 BNX2_MISC_ARB_REQ1BNX2_MISC_ARB_REQ1 0x00000830 bnx2.h 　
17972
 BNX2_MISC_ARB_REQ2BNX2_MISC_ARB_REQ2 0x00000834 bnx2.h 　
17973
 BNX2_MISC_ARB_REQ3BNX2_MISC_ARB_REQ3 0x00000838 bnx2.h 　
17974
 BNX2_MISC_ARB_REQ4BNX2_MISC_ARB_REQ4 0x0000083c bnx2.h 　
17975
 BNX2_MISC_ARB_FREE0BNX2_MISC_ARB_FREE0 0x00000840 bnx2.h 　
17976
 BNX2_MISC_ARB_FREE1BNX2_MISC_ARB_FREE1 0x00000844 bnx2.h 　
17977
 BNX2_MISC_ARB_FREE2BNX2_MISC_ARB_FREE2 0x00000848 bnx2.h 　
17978
 BNX2_MISC_ARB_FREE3BNX2_MISC_ARB_FREE3 0x0000084c bnx2.h 　
17979
 BNX2_MISC_ARB_FREE4BNX2_MISC_ARB_FREE4 0x00000850 bnx2.h 　
17980
 BNX2_MISC_ARB_REQ_STATUS0BNX2_MISC_ARB_REQ_STATUS0 0x00000854 bnx2.h 　
17981
 BNX2_MISC_ARB_REQ_STATUS1BNX2_MISC_ARB_REQ_STATUS1 0x00000858 bnx2.h 　
17982
 BNX2_MISC_ARB_REQ_STATUS2BNX2_MISC_ARB_REQ_STATUS2 0x0000085c bnx2.h 　
17983
 BNX2_MISC_ARB_REQ_STATUS3BNX2_MISC_ARB_REQ_STATUS3 0x00000860 bnx2.h 　
17984
 BNX2_MISC_ARB_REQ_STATUS4BNX2_MISC_ARB_REQ_STATUS4 0x00000864 bnx2.h 　
17985
 BNX2_MISC_ARB_GNT0BNX2_MISC_ARB_GNT0 0x00000868 bnx2.h 　
17986
 BNX2_MISC_ARB_GNT0_0BNX2_MISC_ARB_GNT0_0 (0x7L<<0) bnx2.h 　
17987
 BNX2_MISC_ARB_GNT0_1BNX2_MISC_ARB_GNT0_1 (0x7L<<4) bnx2.h 　
17988
 BNX2_MISC_ARB_GNT0_2BNX2_MISC_ARB_GNT0_2 (0x7L<<8) bnx2.h 　
17989
 BNX2_MISC_ARB_GNT0_3BNX2_MISC_ARB_GNT0_3 (0x7L<<12) bnx2.h 　
17990
 BNX2_MISC_ARB_GNT0_4BNX2_MISC_ARB_GNT0_4 (0x7L<<16) bnx2.h 　
17991
 BNX2_MISC_ARB_GNT0_5BNX2_MISC_ARB_GNT0_5 (0x7L<<20) bnx2.h 　
17992
 BNX2_MISC_ARB_GNT0_6BNX2_MISC_ARB_GNT0_6 (0x7L<<24) bnx2.h 　
17993
 BNX2_MISC_ARB_GNT0_7BNX2_MISC_ARB_GNT0_7 (0x7L<<28) bnx2.h 　
17994
 BNX2_MISC_ARB_GNT1BNX2_MISC_ARB_GNT1 0x0000086c bnx2.h 　
17995
 BNX2_MISC_ARB_GNT1_8BNX2_MISC_ARB_GNT1_8 (0x7L<<0) bnx2.h 　
17996
 BNX2_MISC_ARB_GNT1_9BNX2_MISC_ARB_GNT1_9 (0x7L<<4) bnx2.h 　
17997
 BNX2_MISC_ARB_GNT1_10BNX2_MISC_ARB_GNT1_10 (0x7L<<8) bnx2.h 　
17998
 BNX2_MISC_ARB_GNT1_11BNX2_MISC_ARB_GNT1_11 (0x7L<<12) bnx2.h 　
17999
 BNX2_MISC_ARB_GNT1_12BNX2_MISC_ARB_GNT1_12 (0x7L<<16) bnx2.h 　
18000
 BNX2_MISC_ARB_GNT1_13BNX2_MISC_ARB_GNT1_13 (0x7L<<20) bnx2.h 　
18001
 BNX2_MISC_ARB_GNT1_14BNX2_MISC_ARB_GNT1_14 (0x7L<<24) bnx2.h 　
18002
 BNX2_MISC_ARB_GNT1_15BNX2_MISC_ARB_GNT1_15 (0x7L<<28) bnx2.h 　
18003
 BNX2_MISC_ARB_GNT2BNX2_MISC_ARB_GNT2 0x00000870 bnx2.h 　
18004
 BNX2_MISC_ARB_GNT2_16BNX2_MISC_ARB_GNT2_16 (0x7L<<0) bnx2.h 　
18005
 BNX2_MISC_ARB_GNT2_17BNX2_MISC_ARB_GNT2_17 (0x7L<<4) bnx2.h 　
18006
 BNX2_MISC_ARB_GNT2_18BNX2_MISC_ARB_GNT2_18 (0x7L<<8) bnx2.h 　
18007
 BNX2_MISC_ARB_GNT2_19BNX2_MISC_ARB_GNT2_19 (0x7L<<12) bnx2.h 　
18008
 BNX2_MISC_ARB_GNT2_20BNX2_MISC_ARB_GNT2_20 (0x7L<<16) bnx2.h 　
18009
 BNX2_MISC_ARB_GNT2_21BNX2_MISC_ARB_GNT2_21 (0x7L<<20) bnx2.h 　
18010
 BNX2_MISC_ARB_GNT2_22BNX2_MISC_ARB_GNT2_22 (0x7L<<24) bnx2.h 　
18011
 BNX2_MISC_ARB_GNT2_23BNX2_MISC_ARB_GNT2_23 (0x7L<<28) bnx2.h 　
18012
 BNX2_MISC_ARB_GNT3BNX2_MISC_ARB_GNT3 0x00000874 bnx2.h 　
18013
 BNX2_MISC_ARB_GNT3_24BNX2_MISC_ARB_GNT3_24 (0x7L<<0) bnx2.h 　
18014
 BNX2_MISC_ARB_GNT3_25BNX2_MISC_ARB_GNT3_25 (0x7L<<4) bnx2.h 　
18015
 BNX2_MISC_ARB_GNT3_26BNX2_MISC_ARB_GNT3_26 (0x7L<<8) bnx2.h 　
18016
 BNX2_MISC_ARB_GNT3_27BNX2_MISC_ARB_GNT3_27 (0x7L<<12) bnx2.h 　
18017
 BNX2_MISC_ARB_GNT3_28BNX2_MISC_ARB_GNT3_28 (0x7L<<16) bnx2.h 　
18018
 BNX2_MISC_ARB_GNT3_29BNX2_MISC_ARB_GNT3_29 (0x7L<<20) bnx2.h 　
18019
 BNX2_MISC_ARB_GNT3_30BNX2_MISC_ARB_GNT3_30 (0x7L<<24) bnx2.h 　
18020
 BNX2_MISC_ARB_GNT3_31BNX2_MISC_ARB_GNT3_31 (0x7L<<28) bnx2.h 　
18021
 BNX2_MISC_PRBS_CONTROLBNX2_MISC_PRBS_CONTROL 0x00000878 bnx2.h 　
18022
 BNX2_MISC_PRBS_CONTROL_ENBNX2_MISC_PRBS_CONTROL_EN (1L<<0) bnx2.h 　
18023
 BNX2_MISC_PRBS_CONTROL_RSTBBNX2_MISC_PRBS_CONTROL_RSTB (1L<<1) bnx2.h 　
18024
 BNX2_MISC_PRBS_CONTROL_INVBNX2_MISC_PRBS_CONTROL_INV (1L<<2) bnx2.h 　
18025
 BNX2_MISC_PRBS_CONTROL_ERR_CLRBNX2_MISC_PRBS_CONTROL_ERR_CLR (1L<<3) bnx2.h 　
18026
 BNX2_MISC_PRBS_CONTROL_ORDERBNX2_MISC_PRBS_CONTROL_ORDER (0x3L<<4) bnx2.h 　
18027
 BNX2_MISC_PRBS_CONTROL_ORDER_7TBNX2_MISC_PRBS_CONTROL_ORDER_7T (0L<<4) bnx2.h 　
18028
 BNX2_MISC_PRBS_CONTROL_ORDER_15BNX2_MISC_PRBS_CONTROL_ORDER_15 (1L<<4) bnx2.h 　
18029
 BNX2_MISC_PRBS_CONTROL_ORDER_23BNX2_MISC_PRBS_CONTROL_ORDER_23 (2L<<4) bnx2.h 　
18030
 BNX2_MISC_PRBS_CONTROL_ORDER_31BNX2_MISC_PRBS_CONTROL_ORDER_31 (3L<<4) bnx2.h 　
18031
 BNX2_MISC_PRBS_STATUSBNX2_MISC_PRBS_STATUS 0x0000087c bnx2.h 　
18032
 BNX2_MISC_PRBS_STATUS_LOCKBNX2_MISC_PRBS_STATUS_LOCK (1L<<0) bnx2.h 　
18033
 BNX2_MISC_PRBS_STATUS_STKYBNX2_MISC_PRBS_STATUS_STKY (1L<<1) bnx2.h 　
18034
 BNX2_MISC_PRBS_STATUS_ERRORSBNX2_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2) bnx2.h 　
18035
 BNX2_MISC_PRBS_STATUS_STATEBNX2_MISC_PRBS_STATUS_STATE (0xfL<<16) bnx2.h 　
18036
 BNX2_MISC_SM_ASF_CONTROLBNX2_MISC_SM_ASF_CONTROL 0x00000880 bnx2.h 　
18037
 BNX2_MISC_SM_ASF_CONTROL_ASF_RSBNX2_MISC_SM_ASF_CONTROL_ASF_RS (1L<<0) bnx2.h 　
18038
 BNX2_MISC_SM_ASF_CONTROL_TSC_ENBNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1) bnx2.h 　
18039
 BNX2_MISC_SM_ASF_CONTROL_WG_TOBNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2) bnx2.h 　
18040
 BNX2_MISC_SM_ASF_CONTROL_HB_TOBNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3) bnx2.h 　
18041
 BNX2_MISC_SM_ASF_CONTROL_PA_TOBNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4) bnx2.h 　
18042
 BNX2_MISC_SM_ASF_CONTROL_PL_TOBNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5) bnx2.h 　
18043
 BNX2_MISC_SM_ASF_CONTROL_RT_TOBNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6) bnx2.h 　
18044
 BNX2_MISC_SM_ASF_CONTROL_SMB_EVBNX2_MISC_SM_ASF_CONTROL_SMB_EV (1L<<7) bnx2.h 　
18045
 BNX2_MISC_SM_ASF_CONTROL_RESBNX2_MISC_SM_ASF_CONTROL_RES (0xfL<<8) bnx2.h 　
18046
 BNX2_MISC_SM_ASF_CONTROL_SMB_ENBNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12) bnx2.h 　
18047
 BNX2_MISC_SM_ASF_CONTROL_SMB_BBBNX2_MISC_SM_ASF_CONTROL_SMB_BB (1L<<13) bnx2.h 　
18048
 BNX2_MISC_SM_ASF_CONTROL_SMB_NOBNX2_MISC_SM_ASF_CONTROL_SMB_NO (1L<<14) bnx2.h 　
18049
 BNX2_MISC_SM_ASF_CONTROL_SMB_AUBNX2_MISC_SM_ASF_CONTROL_SMB_AU (1L<<15) bnx2.h 　
18050
 BNX2_MISC_SM_ASF_CONTROL_NIC_SMBNX2_MISC_SM_ASF_CONTROL_NIC_SM (0x3fL<<16) bnx2.h 　
18051
 BNX2_MISC_SM_ASF_CONTROL_NIC_SMBNX2_MISC_SM_ASF_CONTROL_NIC_SM (0x3fL<<24) bnx2.h 　
18052
 BNX2_MISC_SM_ASF_CONTROL_EN_NICBNX2_MISC_SM_ASF_CONTROL_EN_NIC (1L<<30) bnx2.h 　
18053
 BNX2_MISC_SM_ASF_CONTROL_SMB_EABNX2_MISC_SM_ASF_CONTROL_SMB_EA (1L<<31) bnx2.h 　
18054
 BNX2_MISC_SMB_INBNX2_MISC_SMB_IN 0x00000884 bnx2.h 　
18055
 BNX2_MISC_SMB_IN_DAT_INBNX2_MISC_SMB_IN_DAT_IN (0xffL<<0) bnx2.h 　
18056
 BNX2_MISC_SMB_IN_RDYBNX2_MISC_SMB_IN_RDY (1L<<8) bnx2.h 　
18057
 BNX2_MISC_SMB_IN_DONEBNX2_MISC_SMB_IN_DONE (1L<<9) bnx2.h 　
18058
 BNX2_MISC_SMB_IN_FIRSTBYTEBNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10) bnx2.h 　
18059
 BNX2_MISC_SMB_IN_STATUSBNX2_MISC_SMB_IN_STATUS (0x7L<<11) bnx2.h 　
18060
 BNX2_MISC_SMB_IN_STATUS_OKBNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11) bnx2.h 　
18061
 BNX2_MISC_SMB_IN_STATUS_PECBNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11) bnx2.h 　
18062
 BNX2_MISC_SMB_IN_STATUS_OFLOWBNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11) bnx2.h 　
18063
 BNX2_MISC_SMB_IN_STATUS_STOPBNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11) bnx2.h 　
18064
 BNX2_MISC_SMB_IN_STATUS_TIMEOUTBNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11) bnx2.h 　
18065
 BNX2_MISC_SMB_OUTBNX2_MISC_SMB_OUT 0x00000888 bnx2.h 　
18066
 BNX2_MISC_SMB_OUT_DAT_OUTBNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0) bnx2.h 　
18067
 BNX2_MISC_SMB_OUT_RDYBNX2_MISC_SMB_OUT_RDY (1L<<8) bnx2.h 　
18068
 BNX2_MISC_SMB_OUT_STARTBNX2_MISC_SMB_OUT_START (1L<<9) bnx2.h 　
18069
 BNX2_MISC_SMB_OUT_LASTBNX2_MISC_SMB_OUT_LAST (1L<<10) bnx2.h 　
18070
 BNX2_MISC_SMB_OUT_ACC_TYPEBNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11) bnx2.h 　
18071
 BNX2_MISC_SMB_OUT_ENB_PECBNX2_MISC_SMB_OUT_ENB_PEC (1L<<12) bnx2.h 　
18072
 BNX2_MISC_SMB_OUT_GET_RX_LENBNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13) bnx2.h 　
18073
 BNX2_MISC_SMB_OUT_SMB_READ_LENBNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14) bnx2.h 　
18074
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (0xfL<<20) bnx2.h 　
18075
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (0L<<20) bnx2.h 　
18076
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (1L<<20) bnx2.h 　
18077
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (9L<<20) bnx2.h 　
18078
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (2L<<20) bnx2.h 　
18079
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (3L<<20) bnx2.h 　
18080
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (4L<<20) bnx2.h 　
18081
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (5L<<20) bnx2.h 　
18082
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (0xdL<<20) bnx2.h 　
18083
 BNX2_MISC_SMB_OUT_SMB_OUT_STATUBNX2_MISC_SMB_OUT_SMB_OUT_STATU (0x6L<<20) bnx2.h 　
18084
 BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEBNX2_MISC_SMB_OUT_SMB_OUT_SLAVE (1L<<24) bnx2.h 　
18085
 BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EBNX2_MISC_SMB_OUT_SMB_OUT_DAT_E (1L<<25) bnx2.h 　
18086
 BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IBNX2_MISC_SMB_OUT_SMB_OUT_DAT_I (1L<<26) bnx2.h 　
18087
 BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EBNX2_MISC_SMB_OUT_SMB_OUT_CLK_E (1L<<27) bnx2.h 　
18088
 BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IBNX2_MISC_SMB_OUT_SMB_OUT_CLK_I (1L<<28) bnx2.h 　
18089
 BNX2_MISC_SMB_WATCHDOGBNX2_MISC_SMB_WATCHDOG 0x0000088c bnx2.h 　
18090
 BNX2_MISC_SMB_WATCHDOG_WATCHDOGBNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0) bnx2.h 　
18091
 BNX2_MISC_SMB_HEARTBEATBNX2_MISC_SMB_HEARTBEAT 0x00000890 bnx2.h 　
18092
 BNX2_MISC_SMB_HEARTBEAT_HEARTBEBNX2_MISC_SMB_HEARTBEAT_HEARTBE (0xffffL<<0) bnx2.h 　
18093
 BNX2_MISC_SMB_POLL_ASFBNX2_MISC_SMB_POLL_ASF 0x00000894 bnx2.h 　
18094
 BNX2_MISC_SMB_POLL_ASF_POLL_ASFBNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0) bnx2.h 　
18095
 BNX2_MISC_SMB_POLL_LEGACYBNX2_MISC_SMB_POLL_LEGACY 0x00000898 bnx2.h 　
18096
 BNX2_MISC_SMB_POLL_LEGACY_POLL_BNX2_MISC_SMB_POLL_LEGACY_POLL_ (0xffffL<<0) bnx2.h 　
18097
 BNX2_MISC_SMB_RETRANBNX2_MISC_SMB_RETRAN 0x0000089c bnx2.h 　
18098
 BNX2_MISC_SMB_RETRAN_RETRANBNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0) bnx2.h 　
18099
 BNX2_MISC_SMB_TIMESTAMPBNX2_MISC_SMB_TIMESTAMP 0x000008a0 bnx2.h 　
18100
 BNX2_MISC_SMB_TIMESTAMP_TIMESTABNX2_MISC_SMB_TIMESTAMP_TIMESTA (0xffffffffL<<0) bnx2.h 　
18101
 BNX2_MISC_PERR_ENA0BNX2_MISC_PERR_ENA0 0x000008a4 bnx2.h 　
18102
 BNX2_MISC_PERR_ENA0_COM_MISC_CTBNX2_MISC_PERR_ENA0_COM_MISC_CT (1L<<0) bnx2.h 　
18103
 BNX2_MISC_PERR_ENA0_COM_MISC_REBNX2_MISC_PERR_ENA0_COM_MISC_RE (1L<<1) bnx2.h 　
18104
 BNX2_MISC_PERR_ENA0_COM_MISC_SCBNX2_MISC_PERR_ENA0_COM_MISC_SC (1L<<2) bnx2.h 　
18105
 BNX2_MISC_PERR_ENA0_CP_MISC_CTXBNX2_MISC_PERR_ENA0_CP_MISC_CTX (1L<<3) bnx2.h 　
18106
 BNX2_MISC_PERR_ENA0_CP_MISC_REGBNX2_MISC_PERR_ENA0_CP_MISC_REG (1L<<4) bnx2.h 　
18107
 BNX2_MISC_PERR_ENA0_CP_MISC_SCPBNX2_MISC_PERR_ENA0_CP_MISC_SCP (1L<<5) bnx2.h 　
18108
 BNX2_MISC_PERR_ENA0_CS_MISC_TMEBNX2_MISC_PERR_ENA0_CS_MISC_TME (1L<<6) bnx2.h 　
18109
 BNX2_MISC_PERR_ENA0_CTX_MISC_ACBNX2_MISC_PERR_ENA0_CTX_MISC_AC (1L<<7) bnx2.h 　
18110
 BNX2_MISC_PERR_ENA0_CTX_MISC_ACBNX2_MISC_PERR_ENA0_CTX_MISC_AC (1L<<8) bnx2.h 　
18111
 BNX2_MISC_PERR_ENA0_CTX_MISC_ACBNX2_MISC_PERR_ENA0_CTX_MISC_AC (1L<<9) bnx2.h 　
18112
 BNX2_MISC_PERR_ENA0_CTX_MISC_ACBNX2_MISC_PERR_ENA0_CTX_MISC_AC (1L<<10) bnx2.h 　
18113
 BNX2_MISC_PERR_ENA0_CTX_MISC_ACBNX2_MISC_PERR_ENA0_CTX_MISC_AC (1L<<11) bnx2.h 　
18114
 BNX2_MISC_PERR_ENA0_CTX_MISC_ACBNX2_MISC_PERR_ENA0_CTX_MISC_AC (1L<<12) bnx2.h 　
18115
 BNX2_MISC_PERR_ENA0_CTX_MISC_PGBNX2_MISC_PERR_ENA0_CTX_MISC_PG (1L<<13) bnx2.h 　
18116
 BNX2_MISC_PERR_ENA0_DMAE_MISC_DBNX2_MISC_PERR_ENA0_DMAE_MISC_D (1L<<14) bnx2.h 　
18117
 BNX2_MISC_PERR_ENA0_DMAE_MISC_DBNX2_MISC_PERR_ENA0_DMAE_MISC_D (1L<<15) bnx2.h 　
18118
 BNX2_MISC_PERR_ENA0_DMAE_MISC_DBNX2_MISC_PERR_ENA0_DMAE_MISC_D (1L<<16) bnx2.h 　
18119
 BNX2_MISC_PERR_ENA0_DMAE_MISC_DBNX2_MISC_PERR_ENA0_DMAE_MISC_D (1L<<17) bnx2.h 　
18120
 BNX2_MISC_PERR_ENA0_DMAE_MISC_DBNX2_MISC_PERR_ENA0_DMAE_MISC_D (1L<<18) bnx2.h 　
18121
 BNX2_MISC_PERR_ENA0_DMAE_MISC_DBNX2_MISC_PERR_ENA0_DMAE_MISC_D (1L<<19) bnx2.h 　
18122
 BNX2_MISC_PERR_ENA0_DMAE_MISC_DBNX2_MISC_PERR_ENA0_DMAE_MISC_D (1L<<20) bnx2.h 　
18123
 BNX2_MISC_PERR_ENA0_DMAE_MISC_DBNX2_MISC_PERR_ENA0_DMAE_MISC_D (1L<<21) bnx2.h 　
18124
 BNX2_MISC_PERR_ENA0_HC_MISC_DMABNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22) bnx2.h 　
18125
 BNX2_MISC_PERR_ENA0_MCP_MISC_REBNX2_MISC_PERR_ENA0_MCP_MISC_RE (1L<<23) bnx2.h 　
18126
 BNX2_MISC_PERR_ENA0_MCP_MISC_SCBNX2_MISC_PERR_ENA0_MCP_MISC_SC (1L<<24) bnx2.h 　
18127
 BNX2_MISC_PERR_ENA0_MQ_MISC_CTXBNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25) bnx2.h 　
18128
 BNX2_MISC_PERR_ENA0_RBDC_MISCBNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26) bnx2.h 　
18129
 BNX2_MISC_PERR_ENA0_RBUF_MISC_MBNX2_MISC_PERR_ENA0_RBUF_MISC_M (1L<<27) bnx2.h 　
18130
 BNX2_MISC_PERR_ENA0_RBUF_MISC_PBNX2_MISC_PERR_ENA0_RBUF_MISC_P (1L<<28) bnx2.h 　
18131
 BNX2_MISC_PERR_ENA0_RDE_MISC_RPBNX2_MISC_PERR_ENA0_RDE_MISC_RP (1L<<29) bnx2.h 　
18132
 BNX2_MISC_PERR_ENA0_RDE_MISC_RPBNX2_MISC_PERR_ENA0_RDE_MISC_RP (1L<<30) bnx2.h 　
18133
 BNX2_MISC_PERR_ENA0_RV2P_MISC_CBNX2_MISC_PERR_ENA0_RV2P_MISC_C (1L<<31) bnx2.h 　
18134
 BNX2_MISC_PERR_ENA1BNX2_MISC_PERR_ENA1 0x000008a8 bnx2.h 　
18135
 BNX2_MISC_PERR_ENA1_RV2P_MISC_CBNX2_MISC_PERR_ENA1_RV2P_MISC_C (1L<<0) bnx2.h 　
18136
 BNX2_MISC_PERR_ENA1_RV2P_MISC_PBNX2_MISC_PERR_ENA1_RV2P_MISC_P (1L<<1) bnx2.h 　
18137
 BNX2_MISC_PERR_ENA1_RV2P_MISC_PBNX2_MISC_PERR_ENA1_RV2P_MISC_P (1L<<2) bnx2.h 　
18138
 BNX2_MISC_PERR_ENA1_RXP_MISC_CTBNX2_MISC_PERR_ENA1_RXP_MISC_CT (1L<<3) bnx2.h 　
18139
 BNX2_MISC_PERR_ENA1_RXP_MISC_REBNX2_MISC_PERR_ENA1_RXP_MISC_RE (1L<<4) bnx2.h 　
18140
 BNX2_MISC_PERR_ENA1_RXP_MISC_SCBNX2_MISC_PERR_ENA1_RXP_MISC_SC (1L<<5) bnx2.h 　
18141
 BNX2_MISC_PERR_ENA1_RXP_MISC_RBBNX2_MISC_PERR_ENA1_RXP_MISC_RB (1L<<6) bnx2.h 　
18142
 BNX2_MISC_PERR_ENA1_TBDC_MISCBNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7) bnx2.h 　
18143
 BNX2_MISC_PERR_ENA1_TDMA_MISCBNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8) bnx2.h 　
18144
 BNX2_MISC_PERR_ENA1_THBUF_MISC_BNX2_MISC_PERR_ENA1_THBUF_MISC_ (1L<<9) bnx2.h 　
18145
 BNX2_MISC_PERR_ENA1_THBUF_MISC_BNX2_MISC_PERR_ENA1_THBUF_MISC_ (1L<<10) bnx2.h 　
18146
 BNX2_MISC_PERR_ENA1_TPAT_MISC_RBNX2_MISC_PERR_ENA1_TPAT_MISC_R (1L<<11) bnx2.h 　
18147
 BNX2_MISC_PERR_ENA1_TPAT_MISC_SBNX2_MISC_PERR_ENA1_TPAT_MISC_S (1L<<12) bnx2.h 　
18148
 BNX2_MISC_PERR_ENA1_TPBUF_MISC_BNX2_MISC_PERR_ENA1_TPBUF_MISC_ (1L<<13) bnx2.h 　
18149
 BNX2_MISC_PERR_ENA1_TSCH_MISC_LBNX2_MISC_PERR_ENA1_TSCH_MISC_L (1L<<14) bnx2.h 　
18150
 BNX2_MISC_PERR_ENA1_TXP_MISC_CTBNX2_MISC_PERR_ENA1_TXP_MISC_CT (1L<<15) bnx2.h 　
18151
 BNX2_MISC_PERR_ENA1_TXP_MISC_REBNX2_MISC_PERR_ENA1_TXP_MISC_RE (1L<<16) bnx2.h 　
18152
 BNX2_MISC_PERR_ENA1_TXP_MISC_SCBNX2_MISC_PERR_ENA1_TXP_MISC_SC (1L<<17) bnx2.h 　
18153
 BNX2_MISC_PERR_ENA1_UMP_MISC_FIBNX2_MISC_PERR_ENA1_UMP_MISC_FI (1L<<18) bnx2.h 　
18154
 BNX2_MISC_PERR_ENA1_UMP_MISC_FIBNX2_MISC_PERR_ENA1_UMP_MISC_FI (1L<<19) bnx2.h 　
18155
 BNX2_MISC_PERR_ENA1_UMP_MISC_RXBNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20) bnx2.h 　
18156
 BNX2_MISC_PERR_ENA1_UMP_MISC_TXBNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21) bnx2.h 　
18157
 BNX2_MISC_PERR_ENA1_RDMAQ_MISCBNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22) bnx2.h 　
18158
 BNX2_MISC_PERR_ENA1_CSQ_MISCBNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23) bnx2.h 　
18159
 BNX2_MISC_PERR_ENA1_CPQ_MISCBNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24) bnx2.h 　
18160
 BNX2_MISC_PERR_ENA1_MCPQ_MISCBNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25) bnx2.h 　
18161
 BNX2_MISC_PERR_ENA1_RV2PMQ_MISCBNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26) bnx2.h 　
18162
 BNX2_MISC_PERR_ENA1_RV2PPQ_MISCBNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27) bnx2.h 　
18163
 BNX2_MISC_PERR_ENA1_RV2PTQ_MISCBNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28) bnx2.h 　
18164
 BNX2_MISC_PERR_ENA1_RXPQ_MISCBNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29) bnx2.h 　
18165
 BNX2_MISC_PERR_ENA1_RXPCQ_MISCBNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30) bnx2.h 　
18166
 BNX2_MISC_PERR_ENA1_RLUPQ_MISCBNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31) bnx2.h 　
18167
 BNX2_MISC_PERR_ENA2BNX2_MISC_PERR_ENA2 0x000008ac bnx2.h 　
18168
 BNX2_MISC_PERR_ENA2_COMQ_MISCBNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0) bnx2.h 　
18169
 BNX2_MISC_PERR_ENA2_COMXQ_MISCBNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1) bnx2.h 　
18170
 BNX2_MISC_PERR_ENA2_COMTQ_MISCBNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2) bnx2.h 　
18171
 BNX2_MISC_PERR_ENA2_TSCHQ_MISCBNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3) bnx2.h 　
18172
 BNX2_MISC_PERR_ENA2_TBDRQ_MISCBNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4) bnx2.h 　
18173
 BNX2_MISC_PERR_ENA2_TXPQ_MISCBNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5) bnx2.h 　
18174
 BNX2_MISC_PERR_ENA2_TDMAQ_MISCBNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6) bnx2.h 　
18175
 BNX2_MISC_PERR_ENA2_TPATQ_MISCBNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7) bnx2.h 　
18176
 BNX2_MISC_PERR_ENA2_TASQ_MISCBNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8) bnx2.h 　
18177
 BNX2_MISC_DEBUG_VECTOR_SELBNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0 bnx2.h 　
18178
 BNX2_MISC_DEBUG_VECTOR_SEL_0BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0) bnx2.h 　
18179
 BNX2_MISC_DEBUG_VECTOR_SEL_1BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12) bnx2.h 　
18180
 BNX2_MISC_VREG_CONTROLBNX2_MISC_VREG_CONTROL 0x000008b4 bnx2.h 　
18181
 BNX2_MISC_VREG_CONTROL_1_2BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0) bnx2.h 　
18182
 BNX2_MISC_VREG_CONTROL_2_5BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4) bnx2.h 　
18183
 BNX2_MISC_FINAL_CLK_CTL_VALBNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8 bnx2.h 　
18184
 BNX2_MISC_FINAL_CLK_CTL_VAL_MISBNX2_MISC_FINAL_CLK_CTL_VAL_MIS (0x3ffffffL<<6) bnx2.h 　
18185
 BNX2_MISC_UNUSED0BNX2_MISC_UNUSED0 0x000008bc bnx2.h 　
18186
 BNX2_NVM_COMMANDBNX2_NVM_COMMAND 0x00006400 bnx2.h 　
18187
 BNX2_NVM_COMMAND_RSTBNX2_NVM_COMMAND_RST (1L<<0) bnx2.h 　
18188
 BNX2_NVM_COMMAND_DONEBNX2_NVM_COMMAND_DONE (1L<<3) bnx2.h 　
18189
 BNX2_NVM_COMMAND_DOITBNX2_NVM_COMMAND_DOIT (1L<<4) bnx2.h 　
18190
 BNX2_NVM_COMMAND_WRBNX2_NVM_COMMAND_WR (1L<<5) bnx2.h 　
18191
 BNX2_NVM_COMMAND_ERASEBNX2_NVM_COMMAND_ERASE (1L<<6) bnx2.h 　
18192
 BNX2_NVM_COMMAND_FIRSTBNX2_NVM_COMMAND_FIRST (1L<<7) bnx2.h 　
18193
 BNX2_NVM_COMMAND_LASTBNX2_NVM_COMMAND_LAST (1L<<8) bnx2.h 　
18194
 BNX2_NVM_COMMAND_WRENBNX2_NVM_COMMAND_WREN (1L<<16) bnx2.h 　
18195
 BNX2_NVM_COMMAND_WRDIBNX2_NVM_COMMAND_WRDI (1L<<17) bnx2.h 　
18196
 BNX2_NVM_COMMAND_EWSRBNX2_NVM_COMMAND_EWSR (1L<<18) bnx2.h 　
18197
 BNX2_NVM_COMMAND_WRSRBNX2_NVM_COMMAND_WRSR (1L<<19) bnx2.h 　
18198
 BNX2_NVM_STATUSBNX2_NVM_STATUS 0x00006404 bnx2.h 　
18199
 BNX2_NVM_STATUS_PI_FSM_STATEBNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0) bnx2.h 　
18200
 BNX2_NVM_STATUS_EE_FSM_STATEBNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4) bnx2.h 　
18201
 BNX2_NVM_STATUS_EQ_FSM_STATEBNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8) bnx2.h 　
18202
 BNX2_NVM_WRITEBNX2_NVM_WRITE 0x00006408 bnx2.h 　
18203
 BNX2_NVM_WRITE_NVM_WRITE_VALUEBNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0) bnx2.h 　
18204
 BNX2_NVM_WRITE_NVM_WRITE_VALUE_BNX2_NVM_WRITE_NVM_WRITE_VALUE_ (0L<<0) bnx2.h 　
18205
 BNX2_NVM_WRITE_NVM_WRITE_VALUE_BNX2_NVM_WRITE_NVM_WRITE_VALUE_ (1L<<0) bnx2.h 　
18206
 BNX2_NVM_WRITE_NVM_WRITE_VALUE_BNX2_NVM_WRITE_NVM_WRITE_VALUE_ (2L<<0) bnx2.h 　
18207
 BNX2_NVM_WRITE_NVM_WRITE_VALUE_BNX2_NVM_WRITE_NVM_WRITE_VALUE_ (4L<<0) bnx2.h 　
18208
 BNX2_NVM_WRITE_NVM_WRITE_VALUE_BNX2_NVM_WRITE_NVM_WRITE_VALUE_ (8L<<0) bnx2.h 　
18209
 BNX2_NVM_WRITE_NVM_WRITE_VALUE_BNX2_NVM_WRITE_NVM_WRITE_VALUE_ (16L<<0) bnx2.h 　
18210
 BNX2_NVM_WRITE_NVM_WRITE_VALUE_BNX2_NVM_WRITE_NVM_WRITE_VALUE_ (32L<<0) bnx2.h 　
18211
 BNX2_NVM_ADDRBNX2_NVM_ADDR 0x0000640c bnx2.h 　
18212
 BNX2_NVM_ADDR_NVM_ADDR_VALUEBNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0) bnx2.h 　
18213
 BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIBNX2_NVM_ADDR_NVM_ADDR_VALUE_BI (0L<<0) bnx2.h 　
18214
 BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEBNX2_NVM_ADDR_NVM_ADDR_VALUE_EE (1L<<0) bnx2.h 　
18215
 BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEBNX2_NVM_ADDR_NVM_ADDR_VALUE_EE (2L<<0) bnx2.h 　
18216
 BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCBNX2_NVM_ADDR_NVM_ADDR_VALUE_SC (4L<<0) bnx2.h 　
18217
 BNX2_NVM_ADDR_NVM_ADDR_VALUE_CSBNX2_NVM_ADDR_NVM_ADDR_VALUE_CS (8L<<0) bnx2.h 　
18218
 BNX2_NVM_ADDR_NVM_ADDR_VALUE_SOBNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0) bnx2.h 　
18219
 BNX2_NVM_ADDR_NVM_ADDR_VALUE_SIBNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0) bnx2.h 　
18220
 BNX2_NVM_READBNX2_NVM_READ 0x00006410 bnx2.h 　
18221
 BNX2_NVM_READ_NVM_READ_VALUEBNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0) bnx2.h 　
18222
 BNX2_NVM_READ_NVM_READ_VALUE_BIBNX2_NVM_READ_NVM_READ_VALUE_BI (0L<<0) bnx2.h 　
18223
 BNX2_NVM_READ_NVM_READ_VALUE_EEBNX2_NVM_READ_NVM_READ_VALUE_EE (1L<<0) bnx2.h 　
18224
 BNX2_NVM_READ_NVM_READ_VALUE_EEBNX2_NVM_READ_NVM_READ_VALUE_EE (2L<<0) bnx2.h 　
18225
 BNX2_NVM_READ_NVM_READ_VALUE_SCBNX2_NVM_READ_NVM_READ_VALUE_SC (4L<<0) bnx2.h 　
18226
 BNX2_NVM_READ_NVM_READ_VALUE_CSBNX2_NVM_READ_NVM_READ_VALUE_CS (8L<<0) bnx2.h 　
18227
 BNX2_NVM_READ_NVM_READ_VALUE_SOBNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0) bnx2.h 　
18228
 BNX2_NVM_READ_NVM_READ_VALUE_SIBNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0) bnx2.h 　
18229
 BNX2_NVM_CFG1BNX2_NVM_CFG1 0x00006414 bnx2.h 　
18230
 BNX2_NVM_CFG1_FLASH_MODEBNX2_NVM_CFG1_FLASH_MODE (1L<<0) bnx2.h 　
18231
 BNX2_NVM_CFG1_BUFFER_MODEBNX2_NVM_CFG1_BUFFER_MODE (1L<<1) bnx2.h 　
18232
 BNX2_NVM_CFG1_PASS_MODEBNX2_NVM_CFG1_PASS_MODE (1L<<2) bnx2.h 　
18233
 BNX2_NVM_CFG1_BITBANG_MODEBNX2_NVM_CFG1_BITBANG_MODE (1L<<3) bnx2.h 　
18234
 BNX2_NVM_CFG1_STATUS_BITBNX2_NVM_CFG1_STATUS_BIT (0x7L<<4) bnx2.h 　
18235
 BNX2_NVM_CFG1_STATUS_BIT_FLASH_BNX2_NVM_CFG1_STATUS_BIT_FLASH_ (0L<<4) bnx2.h 　
18236
 BNX2_NVM_CFG1_STATUS_BIT_BUFFERBNX2_NVM_CFG1_STATUS_BIT_BUFFER (7L<<4) bnx2.h 　
18237
 BNX2_NVM_CFG1_SPI_CLK_DIVBNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7) bnx2.h 　
18238
 BNX2_NVM_CFG1_SEE_CLK_DIVBNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11) bnx2.h 　
18239
 BNX2_NVM_CFG1_PROTECT_MODEBNX2_NVM_CFG1_PROTECT_MODE (1L<<24) bnx2.h 　
18240
 BNX2_NVM_CFG1_FLASH_SIZEBNX2_NVM_CFG1_FLASH_SIZE (1L<<25) bnx2.h 　
18241
 BNX2_NVM_CFG1_COMPAT_BYPASSSBNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31) bnx2.h 　
18242
 BNX2_NVM_CFG2BNX2_NVM_CFG2 0x00006418 bnx2.h 　
18243
 BNX2_NVM_CFG2_ERASE_CMDBNX2_NVM_CFG2_ERASE_CMD (0xffL<<0) bnx2.h 　
18244
 BNX2_NVM_CFG2_DUMMYBNX2_NVM_CFG2_DUMMY (0xffL<<8) bnx2.h 　
18245
 BNX2_NVM_CFG2_STATUS_CMDBNX2_NVM_CFG2_STATUS_CMD (0xffL<<16) bnx2.h 　
18246
 BNX2_NVM_CFG3BNX2_NVM_CFG3 0x0000641c bnx2.h 　
18247
 BNX2_NVM_CFG3_BUFFER_RD_CMDBNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0) bnx2.h 　
18248
 BNX2_NVM_CFG3_WRITE_CMDBNX2_NVM_CFG3_WRITE_CMD (0xffL<<8) bnx2.h 　
18249
 BNX2_NVM_CFG3_BUFFER_WRITE_CMDBNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16) bnx2.h 　
18250
 BNX2_NVM_CFG3_READ_CMDBNX2_NVM_CFG3_READ_CMD (0xffL<<24) bnx2.h 　
18251
 BNX2_NVM_SW_ARBBNX2_NVM_SW_ARB 0x00006420 bnx2.h 　
18252
 BNX2_NVM_SW_ARB_ARB_REQ_SET0BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0) bnx2.h 　
18253
 BNX2_NVM_SW_ARB_ARB_REQ_SET1BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1) bnx2.h 　
18254
 BNX2_NVM_SW_ARB_ARB_REQ_SET2BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2) bnx2.h 　
18255
 BNX2_NVM_SW_ARB_ARB_REQ_SET3BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3) bnx2.h 　
18256
 BNX2_NVM_SW_ARB_ARB_REQ_CLR0BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4) bnx2.h 　
18257
 BNX2_NVM_SW_ARB_ARB_REQ_CLR1BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5) bnx2.h 　
18258
 BNX2_NVM_SW_ARB_ARB_REQ_CLR2BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6) bnx2.h 　
18259
 BNX2_NVM_SW_ARB_ARB_REQ_CLR3BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7) bnx2.h 　
18260
 BNX2_NVM_SW_ARB_ARB_ARB0BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8) bnx2.h 　
18261
 BNX2_NVM_SW_ARB_ARB_ARB1BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9) bnx2.h 　
18262
 BNX2_NVM_SW_ARB_ARB_ARB2BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10) bnx2.h 　
18263
 BNX2_NVM_SW_ARB_ARB_ARB3BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11) bnx2.h 　
18264
 BNX2_NVM_SW_ARB_REQ0BNX2_NVM_SW_ARB_REQ0 (1L<<12) bnx2.h 　
18265
 BNX2_NVM_SW_ARB_REQ1BNX2_NVM_SW_ARB_REQ1 (1L<<13) bnx2.h 　
18266
 BNX2_NVM_SW_ARB_REQ2BNX2_NVM_SW_ARB_REQ2 (1L<<14) bnx2.h 　
18267
 BNX2_NVM_SW_ARB_REQ3BNX2_NVM_SW_ARB_REQ3 (1L<<15) bnx2.h 　
18268
 BNX2_NVM_ACCESS_ENABLEBNX2_NVM_ACCESS_ENABLE 0x00006424 bnx2.h 　
18269
 BNX2_NVM_ACCESS_ENABLE_ENBNX2_NVM_ACCESS_ENABLE_EN (1L<<0) bnx2.h 　
18270
 BNX2_NVM_ACCESS_ENABLE_WR_ENBNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1) bnx2.h 　
18271
 BNX2_NVM_WRITE1BNX2_NVM_WRITE1 0x00006428 bnx2.h 　
18272
 BNX2_NVM_WRITE1_WREN_CMDBNX2_NVM_WRITE1_WREN_CMD (0xffL<<0) bnx2.h 　
18273
 BNX2_NVM_WRITE1_WRDI_CMDBNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8) bnx2.h 　
18274
 BNX2_NVM_WRITE1_SR_DATABNX2_NVM_WRITE1_SR_DATA (0xffL<<16) bnx2.h 　
18275
 BNX2_DMA_COMMANDBNX2_DMA_COMMAND 0x00000c00 bnx2.h 　
18276
 BNX2_DMA_COMMAND_ENABLEBNX2_DMA_COMMAND_ENABLE (1L<<0) bnx2.h 　
18277
 BNX2_DMA_STATUSBNX2_DMA_STATUS 0x00000c04 bnx2.h 　
18278
 BNX2_DMA_STATUS_PAR_ERROR_STATEBNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0) bnx2.h 　
18279
 BNX2_DMA_STATUS_READ_TRANSFERS_BNX2_DMA_STATUS_READ_TRANSFERS_ (1L<<16) bnx2.h 　
18280
 BNX2_DMA_STATUS_READ_DELAY_PCI_BNX2_DMA_STATUS_READ_DELAY_PCI_ (1L<<17) bnx2.h 　
18281
 BNX2_DMA_STATUS_BIG_READ_TRANSFBNX2_DMA_STATUS_BIG_READ_TRANSF (1L<<18) bnx2.h 　
18282
 BNX2_DMA_STATUS_BIG_READ_DELAY_BNX2_DMA_STATUS_BIG_READ_DELAY_ (1L<<19) bnx2.h 　
18283
 BNX2_DMA_STATUS_BIG_READ_RETRY_BNX2_DMA_STATUS_BIG_READ_RETRY_ (1L<<20) bnx2.h 　
18284
 BNX2_DMA_STATUS_WRITE_TRANSFERSBNX2_DMA_STATUS_WRITE_TRANSFERS (1L<<21) bnx2.h 　
18285
 BNX2_DMA_STATUS_WRITE_DELAY_PCIBNX2_DMA_STATUS_WRITE_DELAY_PCI (1L<<22) bnx2.h 　
18286
 BNX2_DMA_STATUS_BIG_WRITE_TRANSBNX2_DMA_STATUS_BIG_WRITE_TRANS (1L<<23) bnx2.h 　
18287
 BNX2_DMA_STATUS_BIG_WRITE_DELAYBNX2_DMA_STATUS_BIG_WRITE_DELAY (1L<<24) bnx2.h 　
18288
 BNX2_DMA_STATUS_BIG_WRITE_RETRYBNX2_DMA_STATUS_BIG_WRITE_RETRY (1L<<25) bnx2.h 　
18289
 BNX2_DMA_CONFIGBNX2_DMA_CONFIG 0x00000c08 bnx2.h 　
18290
 BNX2_DMA_CONFIG_DATA_BYTE_SWAPBNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0) bnx2.h 　
18291
 BNX2_DMA_CONFIG_DATA_WORD_SWAPBNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1) bnx2.h 　
18292
 BNX2_DMA_CONFIG_CNTL_BYTE_SWAPBNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4) bnx2.h 　
18293
 BNX2_DMA_CONFIG_CNTL_WORD_SWAPBNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5) bnx2.h 　
18294
 BNX2_DMA_CONFIG_ONE_DMABNX2_DMA_CONFIG_ONE_DMA (1L<<6) bnx2.h 　
18295
 BNX2_DMA_CONFIG_CNTL_TWO_DMABNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7) bnx2.h 　
18296
 BNX2_DMA_CONFIG_CNTL_FPGA_MODEBNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8) bnx2.h 　
18297
 BNX2_DMA_CONFIG_CNTL_PING_PONG_BNX2_DMA_CONFIG_CNTL_PING_PONG_ (1L<<10) bnx2.h 　
18298
 BNX2_DMA_CONFIG_CNTL_PCI_COMP_DBNX2_DMA_CONFIG_CNTL_PCI_COMP_D (1L<<11) bnx2.h 　
18299
 BNX2_DMA_CONFIG_NO_RCHANS_IN_USBNX2_DMA_CONFIG_NO_RCHANS_IN_US (0xfL<<12) bnx2.h 　
18300
 BNX2_DMA_CONFIG_NO_WCHANS_IN_USBNX2_DMA_CONFIG_NO_WCHANS_IN_US (0xfL<<16) bnx2.h 　
18301
 BNX2_DMA_CONFIG_PCI_CLK_CMP_BITBNX2_DMA_CONFIG_PCI_CLK_CMP_BIT (0x7L<<20) bnx2.h 　
18302
 BNX2_DMA_CONFIG_PCI_FAST_CLK_CMBNX2_DMA_CONFIG_PCI_FAST_CLK_CM (1L<<23) bnx2.h 　
18303
 BNX2_DMA_CONFIG_BIG_SIZEBNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24) bnx2.h 　
18304
 BNX2_DMA_CONFIG_BIG_SIZE_NONEBNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24) bnx2.h 　
18305
 BNX2_DMA_CONFIG_BIG_SIZE_64BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24) bnx2.h 　
18306
 BNX2_DMA_CONFIG_BIG_SIZE_128BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24) bnx2.h 　
18307
 BNX2_DMA_CONFIG_BIG_SIZE_256BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24) bnx2.h 　
18308
 BNX2_DMA_CONFIG_BIG_SIZE_512BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24) bnx2.h 　
18309
 BNX2_DMA_BLACKOUTBNX2_DMA_BLACKOUT 0x00000c0c bnx2.h 　
18310
 BNX2_DMA_BLACKOUT_RD_RETRY_BLACBNX2_DMA_BLACKOUT_RD_RETRY_BLAC (0xffL<<0) bnx2.h 　
18311
 BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BNX2_DMA_BLACKOUT_2ND_RD_RETRY_ (0xffL<<8) bnx2.h 　
18312
 BNX2_DMA_BLACKOUT_WR_RETRY_BLACBNX2_DMA_BLACKOUT_WR_RETRY_BLAC (0xffL<<16) bnx2.h 　
18313
 BNX2_DMA_RCHAN_STATBNX2_DMA_RCHAN_STAT 0x00000c30 bnx2.h 　
18314
 BNX2_DMA_RCHAN_STAT_COMP_CODE_0BNX2_DMA_RCHAN_STAT_COMP_CODE_0 (0x7L<<0) bnx2.h 　
18315
 BNX2_DMA_RCHAN_STAT_PAR_ERR_0BNX2_DMA_RCHAN_STAT_PAR_ERR_0 (1L<<3) bnx2.h 　
18316
 BNX2_DMA_RCHAN_STAT_COMP_CODE_1BNX2_DMA_RCHAN_STAT_COMP_CODE_1 (0x7L<<4) bnx2.h 　
18317
 BNX2_DMA_RCHAN_STAT_PAR_ERR_1BNX2_DMA_RCHAN_STAT_PAR_ERR_1 (1L<<7) bnx2.h 　
18318
 BNX2_DMA_RCHAN_STAT_COMP_CODE_2BNX2_DMA_RCHAN_STAT_COMP_CODE_2 (0x7L<<8) bnx2.h 　
18319
 BNX2_DMA_RCHAN_STAT_PAR_ERR_2BNX2_DMA_RCHAN_STAT_PAR_ERR_2 (1L<<11) bnx2.h 　
18320
 BNX2_DMA_RCHAN_STAT_COMP_CODE_3BNX2_DMA_RCHAN_STAT_COMP_CODE_3 (0x7L<<12) bnx2.h 　
18321
 BNX2_DMA_RCHAN_STAT_PAR_ERR_3BNX2_DMA_RCHAN_STAT_PAR_ERR_3 (1L<<15) bnx2.h 　
18322
 BNX2_DMA_RCHAN_STAT_COMP_CODE_4BNX2_DMA_RCHAN_STAT_COMP_CODE_4 (0x7L<<16) bnx2.h 　
18323
 BNX2_DMA_RCHAN_STAT_PAR_ERR_4BNX2_DMA_RCHAN_STAT_PAR_ERR_4 (1L<<19) bnx2.h 　
18324
 BNX2_DMA_RCHAN_STAT_COMP_CODE_5BNX2_DMA_RCHAN_STAT_COMP_CODE_5 (0x7L<<20) bnx2.h 　
18325
 BNX2_DMA_RCHAN_STAT_PAR_ERR_5BNX2_DMA_RCHAN_STAT_PAR_ERR_5 (1L<<23) bnx2.h 　
18326
 BNX2_DMA_RCHAN_STAT_COMP_CODE_6BNX2_DMA_RCHAN_STAT_COMP_CODE_6 (0x7L<<24) bnx2.h 　
18327
 BNX2_DMA_RCHAN_STAT_PAR_ERR_6BNX2_DMA_RCHAN_STAT_PAR_ERR_6 (1L<<27) bnx2.h 　
18328
 BNX2_DMA_RCHAN_STAT_COMP_CODE_7BNX2_DMA_RCHAN_STAT_COMP_CODE_7 (0x7L<<28) bnx2.h 　
18329
 BNX2_DMA_RCHAN_STAT_PAR_ERR_7BNX2_DMA_RCHAN_STAT_PAR_ERR_7 (1L<<31) bnx2.h 　
18330
 BNX2_DMA_WCHAN_STATBNX2_DMA_WCHAN_STAT 0x00000c34 bnx2.h 　
18331
 BNX2_DMA_WCHAN_STAT_COMP_CODE_0BNX2_DMA_WCHAN_STAT_COMP_CODE_0 (0x7L<<0) bnx2.h 　
18332
 BNX2_DMA_WCHAN_STAT_PAR_ERR_0BNX2_DMA_WCHAN_STAT_PAR_ERR_0 (1L<<3) bnx2.h 　
18333
 BNX2_DMA_WCHAN_STAT_COMP_CODE_1BNX2_DMA_WCHAN_STAT_COMP_CODE_1 (0x7L<<4) bnx2.h 　
18334
 BNX2_DMA_WCHAN_STAT_PAR_ERR_1BNX2_DMA_WCHAN_STAT_PAR_ERR_1 (1L<<7) bnx2.h 　
18335
 BNX2_DMA_WCHAN_STAT_COMP_CODE_2BNX2_DMA_WCHAN_STAT_COMP_CODE_2 (0x7L<<8) bnx2.h 　
18336
 BNX2_DMA_WCHAN_STAT_PAR_ERR_2BNX2_DMA_WCHAN_STAT_PAR_ERR_2 (1L<<11) bnx2.h 　
18337
 BNX2_DMA_WCHAN_STAT_COMP_CODE_3BNX2_DMA_WCHAN_STAT_COMP_CODE_3 (0x7L<<12) bnx2.h 　
18338
 BNX2_DMA_WCHAN_STAT_PAR_ERR_3BNX2_DMA_WCHAN_STAT_PAR_ERR_3 (1L<<15) bnx2.h 　
18339
 BNX2_DMA_WCHAN_STAT_COMP_CODE_4BNX2_DMA_WCHAN_STAT_COMP_CODE_4 (0x7L<<16) bnx2.h 　
18340
 BNX2_DMA_WCHAN_STAT_PAR_ERR_4BNX2_DMA_WCHAN_STAT_PAR_ERR_4 (1L<<19) bnx2.h 　
18341
 BNX2_DMA_WCHAN_STAT_COMP_CODE_5BNX2_DMA_WCHAN_STAT_COMP_CODE_5 (0x7L<<20) bnx2.h 　
18342
 BNX2_DMA_WCHAN_STAT_PAR_ERR_5BNX2_DMA_WCHAN_STAT_PAR_ERR_5 (1L<<23) bnx2.h 　
18343
 BNX2_DMA_WCHAN_STAT_COMP_CODE_6BNX2_DMA_WCHAN_STAT_COMP_CODE_6 (0x7L<<24) bnx2.h 　
18344
 BNX2_DMA_WCHAN_STAT_PAR_ERR_6BNX2_DMA_WCHAN_STAT_PAR_ERR_6 (1L<<27) bnx2.h 　
18345
 BNX2_DMA_WCHAN_STAT_COMP_CODE_7BNX2_DMA_WCHAN_STAT_COMP_CODE_7 (0x7L<<28) bnx2.h 　
18346
 BNX2_DMA_WCHAN_STAT_PAR_ERR_7BNX2_DMA_WCHAN_STAT_PAR_ERR_7 (1L<<31) bnx2.h 　
18347
 BNX2_DMA_RCHAN_ASSIGNMENTBNX2_DMA_RCHAN_ASSIGNMENT 0x00000c38 bnx2.h 　
18348
 BNX2_DMA_RCHAN_ASSIGNMENT_0BNX2_DMA_RCHAN_ASSIGNMENT_0 (0xfL<<0) bnx2.h 　
18349
 BNX2_DMA_RCHAN_ASSIGNMENT_1BNX2_DMA_RCHAN_ASSIGNMENT_1 (0xfL<<4) bnx2.h 　
18350
 BNX2_DMA_RCHAN_ASSIGNMENT_2BNX2_DMA_RCHAN_ASSIGNMENT_2 (0xfL<<8) bnx2.h 　
18351
 BNX2_DMA_RCHAN_ASSIGNMENT_3BNX2_DMA_RCHAN_ASSIGNMENT_3 (0xfL<<12) bnx2.h 　
18352
 BNX2_DMA_RCHAN_ASSIGNMENT_4BNX2_DMA_RCHAN_ASSIGNMENT_4 (0xfL<<16) bnx2.h 　
18353
 BNX2_DMA_RCHAN_ASSIGNMENT_5BNX2_DMA_RCHAN_ASSIGNMENT_5 (0xfL<<20) bnx2.h 　
18354
 BNX2_DMA_RCHAN_ASSIGNMENT_6BNX2_DMA_RCHAN_ASSIGNMENT_6 (0xfL<<24) bnx2.h 　
18355
 BNX2_DMA_RCHAN_ASSIGNMENT_7BNX2_DMA_RCHAN_ASSIGNMENT_7 (0xfL<<28) bnx2.h 　
18356
 BNX2_DMA_WCHAN_ASSIGNMENTBNX2_DMA_WCHAN_ASSIGNMENT 0x00000c3c bnx2.h 　
18357
 BNX2_DMA_WCHAN_ASSIGNMENT_0BNX2_DMA_WCHAN_ASSIGNMENT_0 (0xfL<<0) bnx2.h 　
18358
 BNX2_DMA_WCHAN_ASSIGNMENT_1BNX2_DMA_WCHAN_ASSIGNMENT_1 (0xfL<<4) bnx2.h 　
18359
 BNX2_DMA_WCHAN_ASSIGNMENT_2BNX2_DMA_WCHAN_ASSIGNMENT_2 (0xfL<<8) bnx2.h 　
18360
 BNX2_DMA_WCHAN_ASSIGNMENT_3BNX2_DMA_WCHAN_ASSIGNMENT_3 (0xfL<<12) bnx2.h 　
18361
 BNX2_DMA_WCHAN_ASSIGNMENT_4BNX2_DMA_WCHAN_ASSIGNMENT_4 (0xfL<<16) bnx2.h 　
18362
 BNX2_DMA_WCHAN_ASSIGNMENT_5BNX2_DMA_WCHAN_ASSIGNMENT_5 (0xfL<<20) bnx2.h 　
18363
 BNX2_DMA_WCHAN_ASSIGNMENT_6BNX2_DMA_WCHAN_ASSIGNMENT_6 (0xfL<<24) bnx2.h 　
18364
 BNX2_DMA_WCHAN_ASSIGNMENT_7BNX2_DMA_WCHAN_ASSIGNMENT_7 (0xfL<<28) bnx2.h 　
18365
 BNX2_DMA_RCHAN_STAT_00BNX2_DMA_RCHAN_STAT_00 0x00000c40 bnx2.h 　
18366
 BNX2_DMA_RCHAN_STAT_00_RCHAN_STBNX2_DMA_RCHAN_STAT_00_RCHAN_ST (0xffffffffL<<0) bnx2.h 　
18367
 BNX2_DMA_RCHAN_STAT_01BNX2_DMA_RCHAN_STAT_01 0x00000c44 bnx2.h 　
18368
 BNX2_DMA_RCHAN_STAT_01_RCHAN_STBNX2_DMA_RCHAN_STAT_01_RCHAN_ST (0xffffffffL<<0) bnx2.h 　
18369
 BNX2_DMA_RCHAN_STAT_02BNX2_DMA_RCHAN_STAT_02 0x00000c48 bnx2.h 　
18370
 BNX2_DMA_RCHAN_STAT_02_LENGTHBNX2_DMA_RCHAN_STAT_02_LENGTH (0xffffL<<0) bnx2.h 　
18371
 BNX2_DMA_RCHAN_STAT_02_WORD_SWABNX2_DMA_RCHAN_STAT_02_WORD_SWA (1L<<16) bnx2.h 　
18372
 BNX2_DMA_RCHAN_STAT_02_BYTE_SWABNX2_DMA_RCHAN_STAT_02_BYTE_SWA (1L<<17) bnx2.h 　
18373
 BNX2_DMA_RCHAN_STAT_02_PRIORITYBNX2_DMA_RCHAN_STAT_02_PRIORITY (1L<<18) bnx2.h 　
18374
 BNX2_DMA_RCHAN_STAT_10BNX2_DMA_RCHAN_STAT_10 0x00000c4c bnx2.h 　
18375
 BNX2_DMA_RCHAN_STAT_11BNX2_DMA_RCHAN_STAT_11 0x00000c50 bnx2.h 　
18376
 BNX2_DMA_RCHAN_STAT_12BNX2_DMA_RCHAN_STAT_12 0x00000c54 bnx2.h 　
18377
 BNX2_DMA_RCHAN_STAT_20BNX2_DMA_RCHAN_STAT_20 0x00000c58 bnx2.h 　
18378
 BNX2_DMA_RCHAN_STAT_21BNX2_DMA_RCHAN_STAT_21 0x00000c5c bnx2.h 　
18379
 BNX2_DMA_RCHAN_STAT_22BNX2_DMA_RCHAN_STAT_22 0x00000c60 bnx2.h 　
18380
 BNX2_DMA_RCHAN_STAT_30BNX2_DMA_RCHAN_STAT_30 0x00000c64 bnx2.h 　
18381
 BNX2_DMA_RCHAN_STAT_31BNX2_DMA_RCHAN_STAT_31 0x00000c68 bnx2.h 　
18382
 BNX2_DMA_RCHAN_STAT_32BNX2_DMA_RCHAN_STAT_32 0x00000c6c bnx2.h 　
18383
 BNX2_DMA_RCHAN_STAT_40BNX2_DMA_RCHAN_STAT_40 0x00000c70 bnx2.h 　
18384
 BNX2_DMA_RCHAN_STAT_41BNX2_DMA_RCHAN_STAT_41 0x00000c74 bnx2.h 　
18385
 BNX2_DMA_RCHAN_STAT_42BNX2_DMA_RCHAN_STAT_42 0x00000c78 bnx2.h 　
18386
 BNX2_DMA_RCHAN_STAT_50BNX2_DMA_RCHAN_STAT_50 0x00000c7c bnx2.h 　
18387
 BNX2_DMA_RCHAN_STAT_51BNX2_DMA_RCHAN_STAT_51 0x00000c80 bnx2.h 　
18388
 BNX2_DMA_RCHAN_STAT_52BNX2_DMA_RCHAN_STAT_52 0x00000c84 bnx2.h 　
18389
 BNX2_DMA_RCHAN_STAT_60BNX2_DMA_RCHAN_STAT_60 0x00000c88 bnx2.h 　
18390
 BNX2_DMA_RCHAN_STAT_61BNX2_DMA_RCHAN_STAT_61 0x00000c8c bnx2.h 　
18391
 BNX2_DMA_RCHAN_STAT_62BNX2_DMA_RCHAN_STAT_62 0x00000c90 bnx2.h 　
18392
 BNX2_DMA_RCHAN_STAT_70BNX2_DMA_RCHAN_STAT_70 0x00000c94 bnx2.h 　
18393
 BNX2_DMA_RCHAN_STAT_71BNX2_DMA_RCHAN_STAT_71 0x00000c98 bnx2.h 　
18394
 BNX2_DMA_RCHAN_STAT_72BNX2_DMA_RCHAN_STAT_72 0x00000c9c bnx2.h 　
18395
 BNX2_DMA_WCHAN_STAT_00BNX2_DMA_WCHAN_STAT_00 0x00000ca0 bnx2.h 　
18396
 BNX2_DMA_WCHAN_STAT_00_WCHAN_STBNX2_DMA_WCHAN_STAT_00_WCHAN_ST (0xffffffffL<<0) bnx2.h 　
18397
 BNX2_DMA_WCHAN_STAT_01BNX2_DMA_WCHAN_STAT_01 0x00000ca4 bnx2.h 　
18398
 BNX2_DMA_WCHAN_STAT_01_WCHAN_STBNX2_DMA_WCHAN_STAT_01_WCHAN_ST (0xffffffffL<<0) bnx2.h 　
18399
 BNX2_DMA_WCHAN_STAT_02BNX2_DMA_WCHAN_STAT_02 0x00000ca8 bnx2.h 　
18400
 BNX2_DMA_WCHAN_STAT_02_LENGTHBNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0) bnx2.h 　
18401
 BNX2_DMA_WCHAN_STAT_02_WORD_SWABNX2_DMA_WCHAN_STAT_02_WORD_SWA (1L<<16) bnx2.h 　
18402
 BNX2_DMA_WCHAN_STAT_02_BYTE_SWABNX2_DMA_WCHAN_STAT_02_BYTE_SWA (1L<<17) bnx2.h 　
18403
 BNX2_DMA_WCHAN_STAT_02_PRIORITYBNX2_DMA_WCHAN_STAT_02_PRIORITY (1L<<18) bnx2.h 　
18404
 BNX2_DMA_WCHAN_STAT_10BNX2_DMA_WCHAN_STAT_10 0x00000cac bnx2.h 　
18405
 BNX2_DMA_WCHAN_STAT_11BNX2_DMA_WCHAN_STAT_11 0x00000cb0 bnx2.h 　
18406
 BNX2_DMA_WCHAN_STAT_12BNX2_DMA_WCHAN_STAT_12 0x00000cb4 bnx2.h 　
18407
 BNX2_DMA_WCHAN_STAT_20BNX2_DMA_WCHAN_STAT_20 0x00000cb8 bnx2.h 　
18408
 BNX2_DMA_WCHAN_STAT_21BNX2_DMA_WCHAN_STAT_21 0x00000cbc bnx2.h 　
18409
 BNX2_DMA_WCHAN_STAT_22BNX2_DMA_WCHAN_STAT_22 0x00000cc0 bnx2.h 　
18410
 BNX2_DMA_WCHAN_STAT_30BNX2_DMA_WCHAN_STAT_30 0x00000cc4 bnx2.h 　
18411
 BNX2_DMA_WCHAN_STAT_31BNX2_DMA_WCHAN_STAT_31 0x00000cc8 bnx2.h 　
18412
 BNX2_DMA_WCHAN_STAT_32BNX2_DMA_WCHAN_STAT_32 0x00000ccc bnx2.h 　
18413
 BNX2_DMA_WCHAN_STAT_40BNX2_DMA_WCHAN_STAT_40 0x00000cd0 bnx2.h 　
18414
 BNX2_DMA_WCHAN_STAT_41BNX2_DMA_WCHAN_STAT_41 0x00000cd4 bnx2.h 　
18415
 BNX2_DMA_WCHAN_STAT_42BNX2_DMA_WCHAN_STAT_42 0x00000cd8 bnx2.h 　
18416
 BNX2_DMA_WCHAN_STAT_50BNX2_DMA_WCHAN_STAT_50 0x00000cdc bnx2.h 　
18417
 BNX2_DMA_WCHAN_STAT_51BNX2_DMA_WCHAN_STAT_51 0x00000ce0 bnx2.h 　
18418
 BNX2_DMA_WCHAN_STAT_52BNX2_DMA_WCHAN_STAT_52 0x00000ce4 bnx2.h 　
18419
 BNX2_DMA_WCHAN_STAT_60BNX2_DMA_WCHAN_STAT_60 0x00000ce8 bnx2.h 　
18420
 BNX2_DMA_WCHAN_STAT_61BNX2_DMA_WCHAN_STAT_61 0x00000cec bnx2.h 　
18421
 BNX2_DMA_WCHAN_STAT_62BNX2_DMA_WCHAN_STAT_62 0x00000cf0 bnx2.h 　
18422
 BNX2_DMA_WCHAN_STAT_70BNX2_DMA_WCHAN_STAT_70 0x00000cf4 bnx2.h 　
18423
 BNX2_DMA_WCHAN_STAT_71BNX2_DMA_WCHAN_STAT_71 0x00000cf8 bnx2.h 　
18424
 BNX2_DMA_WCHAN_STAT_72BNX2_DMA_WCHAN_STAT_72 0x00000cfc bnx2.h 　
18425
 BNX2_DMA_ARB_STAT_00BNX2_DMA_ARB_STAT_00 0x00000d00 bnx2.h 　
18426
 BNX2_DMA_ARB_STAT_00_MASTERBNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0) bnx2.h 　
18427
 BNX2_DMA_ARB_STAT_00_MASTER_ENCBNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16) bnx2.h 　
18428
 BNX2_DMA_ARB_STAT_00_CUR_BINMSTBNX2_DMA_ARB_STAT_00_CUR_BINMST (0xffL<<24) bnx2.h 　
18429
 BNX2_DMA_ARB_STAT_01BNX2_DMA_ARB_STAT_01 0x00000d04 bnx2.h 　
18430
 BNX2_DMA_ARB_STAT_01_LPR_RPTRBNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0) bnx2.h 　
18431
 BNX2_DMA_ARB_STAT_01_LPR_WPTRBNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4) bnx2.h 　
18432
 BNX2_DMA_ARB_STAT_01_LPB_RPTRBNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8) bnx2.h 　
18433
 BNX2_DMA_ARB_STAT_01_LPB_WPTRBNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12) bnx2.h 　
18434
 BNX2_DMA_ARB_STAT_01_HPR_RPTRBNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16) bnx2.h 　
18435
 BNX2_DMA_ARB_STAT_01_HPR_WPTRBNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20) bnx2.h 　
18436
 BNX2_DMA_ARB_STAT_01_HPB_RPTRBNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24) bnx2.h 　
18437
 BNX2_DMA_ARB_STAT_01_HPB_WPTRBNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28) bnx2.h 　
18438
 BNX2_DMA_FUSE_CTRL0_CMDBNX2_DMA_FUSE_CTRL0_CMD 0x00000f00 bnx2.h 　
18439
 BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DBNX2_DMA_FUSE_CTRL0_CMD_PWRUP_D (1L<<0) bnx2.h 　
18440
 BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DBNX2_DMA_FUSE_CTRL0_CMD_SHIFT_D (1L<<1) bnx2.h 　
18441
 BNX2_DMA_FUSE_CTRL0_CMD_SHIFTBNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2) bnx2.h 　
18442
 BNX2_DMA_FUSE_CTRL0_CMD_LOADBNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3) bnx2.h 　
18443
 BNX2_DMA_FUSE_CTRL0_CMD_SELBNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8) bnx2.h 　
18444
 BNX2_DMA_FUSE_CTRL0_DATABNX2_DMA_FUSE_CTRL0_DATA 0x00000f04 bnx2.h 　
18445
 BNX2_DMA_FUSE_CTRL1_CMDBNX2_DMA_FUSE_CTRL1_CMD 0x00000f08 bnx2.h 　
18446
 BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DBNX2_DMA_FUSE_CTRL1_CMD_PWRUP_D (1L<<0) bnx2.h 　
18447
 BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DBNX2_DMA_FUSE_CTRL1_CMD_SHIFT_D (1L<<1) bnx2.h 　
18448
 BNX2_DMA_FUSE_CTRL1_CMD_SHIFTBNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2) bnx2.h 　
18449
 BNX2_DMA_FUSE_CTRL1_CMD_LOADBNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3) bnx2.h 　
18450
 BNX2_DMA_FUSE_CTRL1_CMD_SELBNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8) bnx2.h 　
18451
 BNX2_DMA_FUSE_CTRL1_DATABNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c bnx2.h 　
18452
 BNX2_DMA_FUSE_CTRL2_CMDBNX2_DMA_FUSE_CTRL2_CMD 0x00000f10 bnx2.h 　
18453
 BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DBNX2_DMA_FUSE_CTRL2_CMD_PWRUP_D (1L<<0) bnx2.h 　
18454
 BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DBNX2_DMA_FUSE_CTRL2_CMD_SHIFT_D (1L<<1) bnx2.h 　
18455
 BNX2_DMA_FUSE_CTRL2_CMD_SHIFTBNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2) bnx2.h 　
18456
 BNX2_DMA_FUSE_CTRL2_CMD_LOADBNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3) bnx2.h 　
18457
 BNX2_DMA_FUSE_CTRL2_CMD_SELBNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8) bnx2.h 　
18458
 BNX2_DMA_FUSE_CTRL2_DATABNX2_DMA_FUSE_CTRL2_DATA 0x00000f14 bnx2.h 　
18459
 BNX2_CTX_COMMANDBNX2_CTX_COMMAND 0x00001000 bnx2.h 　
18460
 BNX2_CTX_COMMAND_ENABLEDBNX2_CTX_COMMAND_ENABLED (1L<<0) bnx2.h 　
18461
 BNX2_CTX_STATUSBNX2_CTX_STATUS 0x00001004 bnx2.h 　
18462
 BNX2_CTX_STATUS_LOCK_WAITBNX2_CTX_STATUS_LOCK_WAIT (1L<<0) bnx2.h 　
18463
 BNX2_CTX_STATUS_READ_STATBNX2_CTX_STATUS_READ_STAT (1L<<16) bnx2.h 　
18464
 BNX2_CTX_STATUS_WRITE_STATBNX2_CTX_STATUS_WRITE_STAT (1L<<17) bnx2.h 　
18465
 BNX2_CTX_STATUS_ACC_STALL_STATBNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18) bnx2.h 　
18466
 BNX2_CTX_STATUS_LOCK_STALL_STATBNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19) bnx2.h 　
18467
 BNX2_CTX_VIRT_ADDRBNX2_CTX_VIRT_ADDR 0x00001008 bnx2.h 　
18468
 BNX2_CTX_VIRT_ADDR_VIRT_ADDRBNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6) bnx2.h 　
18469
 BNX2_CTX_PAGE_TBLBNX2_CTX_PAGE_TBL 0x0000100c bnx2.h 　
18470
 BNX2_CTX_PAGE_TBL_PAGE_TBLBNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6) bnx2.h 　
18471
 BNX2_CTX_DATA_ADRBNX2_CTX_DATA_ADR 0x00001010 bnx2.h 　
18472
 BNX2_CTX_DATA_ADR_DATA_ADRBNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2) bnx2.h 　
18473
 BNX2_CTX_DATABNX2_CTX_DATA 0x00001014 bnx2.h 　
18474
 BNX2_CTX_LOCKBNX2_CTX_LOCK 0x00001018 bnx2.h 　
18475
 BNX2_CTX_LOCK_TYPEBNX2_CTX_LOCK_TYPE (0x7L<<0) bnx2.h 　
18476
 BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOBNX2_CTX_LOCK_TYPE_LOCK_TYPE_VO (0x0L<<0) bnx2.h 　
18477
 BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COBNX2_CTX_LOCK_TYPE_LOCK_TYPE_CO (0x7L<<0) bnx2.h 　
18478
 BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PRBNX2_CTX_LOCK_TYPE_LOCK_TYPE_PR (0x1L<<0) bnx2.h 　
18479
 BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TXBNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0) bnx2.h 　
18480
 BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIBNX2_CTX_LOCK_TYPE_LOCK_TYPE_TI (0x4L<<0) bnx2.h 　
18481
 BNX2_CTX_LOCK_CID_VALUEBNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7) bnx2.h 　
18482
 BNX2_CTX_LOCK_GRANTEDBNX2_CTX_LOCK_GRANTED (1L<<26) bnx2.h 　
18483
 BNX2_CTX_LOCK_MODEBNX2_CTX_LOCK_MODE (0x7L<<27) bnx2.h 　
18484
 BNX2_CTX_LOCK_MODE_UNLOCKBNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27) bnx2.h 　
18485
 BNX2_CTX_LOCK_MODE_IMMEDIATEBNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27) bnx2.h 　
18486
 BNX2_CTX_LOCK_MODE_SUREBNX2_CTX_LOCK_MODE_SURE (0x2L<<27) bnx2.h 　
18487
 BNX2_CTX_LOCK_STATUSBNX2_CTX_LOCK_STATUS (1L<<30) bnx2.h 　
18488
 BNX2_CTX_LOCK_REQBNX2_CTX_LOCK_REQ (1L<<31) bnx2.h 　
18489
 BNX2_CTX_ACCESS_STATUSBNX2_CTX_ACCESS_STATUS 0x00001040 bnx2.h 　
18490
 BNX2_CTX_ACCESS_STATUS_MASTERENBNX2_CTX_ACCESS_STATUS_MASTEREN (0xfL<<0) bnx2.h 　
18491
 BNX2_CTX_ACCESS_STATUS_ACCESSMEBNX2_CTX_ACCESS_STATUS_ACCESSME (0x3L<<10) bnx2.h 　
18492
 BNX2_CTX_ACCESS_STATUS_PAGETABLBNX2_CTX_ACCESS_STATUS_PAGETABL (0x3L<<12) bnx2.h 　
18493
 BNX2_CTX_ACCESS_STATUS_ACCESSMEBNX2_CTX_ACCESS_STATUS_ACCESSME (0x3L<<14) bnx2.h 　
18494
 BNX2_CTX_ACCESS_STATUS_QUALIFIEBNX2_CTX_ACCESS_STATUS_QUALIFIE (0x7ffL<<17) bnx2.h 　
18495
 BNX2_CTX_DBG_LOCK_STATUSBNX2_CTX_DBG_LOCK_STATUS 0x00001044 bnx2.h 　
18496
 BNX2_CTX_DBG_LOCK_STATUS_SMBNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0) bnx2.h 　
18497
 BNX2_CTX_DBG_LOCK_STATUS_MATCHBNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22) bnx2.h 　
18498
 BNX2_CTX_CHNL_LOCK_STATUS_0BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080 bnx2.h 　
18499
 BNX2_CTX_CHNL_LOCK_STATUS_0_CIDBNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0) bnx2.h 　
18500
 BNX2_CTX_CHNL_LOCK_STATUS_0_TYPBNX2_CTX_CHNL_LOCK_STATUS_0_TYP (0x3L<<14) bnx2.h 　
18501
 BNX2_CTX_CHNL_LOCK_STATUS_0_MODBNX2_CTX_CHNL_LOCK_STATUS_0_MOD (1L<<16) bnx2.h 　
18502
 BNX2_CTX_CHNL_LOCK_STATUS_1BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084 bnx2.h 　
18503
 BNX2_CTX_CHNL_LOCK_STATUS_2BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088 bnx2.h 　
18504
 BNX2_CTX_CHNL_LOCK_STATUS_3BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c bnx2.h 　
18505
 BNX2_CTX_CHNL_LOCK_STATUS_4BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090 bnx2.h 　
18506
 BNX2_CTX_CHNL_LOCK_STATUS_5BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094 bnx2.h 　
18507
 BNX2_CTX_CHNL_LOCK_STATUS_6BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098 bnx2.h 　
18508
 BNX2_CTX_CHNL_LOCK_STATUS_7BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c bnx2.h 　
18509
 BNX2_CTX_CHNL_LOCK_STATUS_8BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0 bnx2.h 　
18510
 BNX2_EMAC_MODEBNX2_EMAC_MODE 0x00001400 bnx2.h 　
18511
 BNX2_EMAC_MODE_RESETBNX2_EMAC_MODE_RESET (1L<<0) bnx2.h 　
18512
 BNX2_EMAC_MODE_HALF_DUPLEXBNX2_EMAC_MODE_HALF_DUPLEX (1L<<1) bnx2.h 　
18513
 BNX2_EMAC_MODE_PORTBNX2_EMAC_MODE_PORT (0x3L<<2) bnx2.h 　
18514
 BNX2_EMAC_MODE_PORT_NONEBNX2_EMAC_MODE_PORT_NONE (0L<<2) bnx2.h 　
18515
 BNX2_EMAC_MODE_PORT_MIIBNX2_EMAC_MODE_PORT_MII (1L<<2) bnx2.h 　
18516
 BNX2_EMAC_MODE_PORT_GMIIBNX2_EMAC_MODE_PORT_GMII (2L<<2) bnx2.h 　
18517
 BNX2_EMAC_MODE_PORT_MII_10BNX2_EMAC_MODE_PORT_MII_10 (3L<<2) bnx2.h 　
18518
 BNX2_EMAC_MODE_MAC_LOOPBNX2_EMAC_MODE_MAC_LOOP (1L<<4) bnx2.h 　
18519
 BNX2_EMAC_MODE_25GBNX2_EMAC_MODE_25G (1L<<5) bnx2.h 　
18520
 BNX2_EMAC_MODE_TAGGED_MAC_CTLBNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7) bnx2.h 　
18521
 BNX2_EMAC_MODE_TX_BURSTBNX2_EMAC_MODE_TX_BURST (1L<<8) bnx2.h 　
18522
 BNX2_EMAC_MODE_MAX_DEFER_DROP_EBNX2_EMAC_MODE_MAX_DEFER_DROP_E (1L<<9) bnx2.h 　
18523
 BNX2_EMAC_MODE_EXT_LINK_POLBNX2_EMAC_MODE_EXT_LINK_POL (1L<<10) bnx2.h 　
18524
 BNX2_EMAC_MODE_FORCE_LINKBNX2_EMAC_MODE_FORCE_LINK (1L<<11) bnx2.h 　
18525
 BNX2_EMAC_MODE_MPKTBNX2_EMAC_MODE_MPKT (1L<<18) bnx2.h 　
18526
 BNX2_EMAC_MODE_MPKT_RCVDBNX2_EMAC_MODE_MPKT_RCVD (1L<<19) bnx2.h 　
18527
 BNX2_EMAC_MODE_ACPI_RCVDBNX2_EMAC_MODE_ACPI_RCVD (1L<<20) bnx2.h 　
18528
 BNX2_EMAC_STATUSBNX2_EMAC_STATUS 0x00001404 bnx2.h 　
18529
 BNX2_EMAC_STATUS_LINKBNX2_EMAC_STATUS_LINK (1L<<11) bnx2.h 　
18530
 BNX2_EMAC_STATUS_LINK_CHANGEBNX2_EMAC_STATUS_LINK_CHANGE (1L<<12) bnx2.h 　
18531
 BNX2_EMAC_STATUS_MI_COMPLETEBNX2_EMAC_STATUS_MI_COMPLETE (1L<<22) bnx2.h 　
18532
 BNX2_EMAC_STATUS_MI_INTBNX2_EMAC_STATUS_MI_INT (1L<<23) bnx2.h 　
18533
 BNX2_EMAC_STATUS_AP_ERRORBNX2_EMAC_STATUS_AP_ERROR (1L<<24) bnx2.h 　
18534
 BNX2_EMAC_STATUS_PARITY_ERROR_SBNX2_EMAC_STATUS_PARITY_ERROR_S (1L<<31) bnx2.h 　
18535
 BNX2_EMAC_ATTENTION_ENABNX2_EMAC_ATTENTION_ENA 0x00001408 bnx2.h 　
18536
 BNX2_EMAC_ATTENTION_ENA_LINKBNX2_EMAC_ATTENTION_ENA_LINK (1L<<11) bnx2.h 　
18537
 BNX2_EMAC_ATTENTION_ENA_MI_COMPBNX2_EMAC_ATTENTION_ENA_MI_COMP (1L<<22) bnx2.h 　
18538
 BNX2_EMAC_ATTENTION_ENA_MI_INTBNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23) bnx2.h 　
18539
 BNX2_EMAC_ATTENTION_ENA_AP_ERROBNX2_EMAC_ATTENTION_ENA_AP_ERRO (1L<<24) bnx2.h 　
18540
 BNX2_EMAC_LEDBNX2_EMAC_LED 0x0000140c bnx2.h 　
18541
 BNX2_EMAC_LED_OVERRIDEBNX2_EMAC_LED_OVERRIDE (1L<<0) bnx2.h 　
18542
 BNX2_EMAC_LED_1000MB_OVERRIDEBNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1) bnx2.h 　
18543
 BNX2_EMAC_LED_100MB_OVERRIDEBNX2_EMAC_LED_100MB_OVERRIDE (1L<<2) bnx2.h 　
18544
 BNX2_EMAC_LED_10MB_OVERRIDEBNX2_EMAC_LED_10MB_OVERRIDE (1L<<3) bnx2.h 　
18545
 BNX2_EMAC_LED_TRAFFIC_OVERRIDEBNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4) bnx2.h 　
18546
 BNX2_EMAC_LED_BLNK_TRAFFICBNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5) bnx2.h 　
18547
 BNX2_EMAC_LED_TRAFFICBNX2_EMAC_LED_TRAFFIC (1L<<6) bnx2.h 　
18548
 BNX2_EMAC_LED_1000MBBNX2_EMAC_LED_1000MB (1L<<7) bnx2.h 　
18549
 BNX2_EMAC_LED_100MBBNX2_EMAC_LED_100MB (1L<<8) bnx2.h 　
18550
 BNX2_EMAC_LED_10MBBNX2_EMAC_LED_10MB (1L<<9) bnx2.h 　
18551
 BNX2_EMAC_LED_TRAFFIC_STATBNX2_EMAC_LED_TRAFFIC_STAT (1L<<10) bnx2.h 　
18552
 BNX2_EMAC_LED_BLNK_RATEBNX2_EMAC_LED_BLNK_RATE (0xfffL<<19) bnx2.h 　
18553
 BNX2_EMAC_LED_BLNK_RATE_ENABNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31) bnx2.h 　
18554
 BNX2_EMAC_MAC_MATCH0BNX2_EMAC_MAC_MATCH0 0x00001410 bnx2.h 　
18555
 BNX2_EMAC_MAC_MATCH1BNX2_EMAC_MAC_MATCH1 0x00001414 bnx2.h 　
18556
 BNX2_EMAC_MAC_MATCH2BNX2_EMAC_MAC_MATCH2 0x00001418 bnx2.h 　
18557
 BNX2_EMAC_MAC_MATCH3BNX2_EMAC_MAC_MATCH3 0x0000141c bnx2.h 　
18558
 BNX2_EMAC_MAC_MATCH4BNX2_EMAC_MAC_MATCH4 0x00001420 bnx2.h 　
18559
 BNX2_EMAC_MAC_MATCH5BNX2_EMAC_MAC_MATCH5 0x00001424 bnx2.h 　
18560
 BNX2_EMAC_MAC_MATCH6BNX2_EMAC_MAC_MATCH6 0x00001428 bnx2.h 　
18561
 BNX2_EMAC_MAC_MATCH7BNX2_EMAC_MAC_MATCH7 0x0000142c bnx2.h 　
18562
 BNX2_EMAC_MAC_MATCH8BNX2_EMAC_MAC_MATCH8 0x00001430 bnx2.h 　
18563
 BNX2_EMAC_MAC_MATCH9BNX2_EMAC_MAC_MATCH9 0x00001434 bnx2.h 　
18564
 BNX2_EMAC_MAC_MATCH10BNX2_EMAC_MAC_MATCH10 0x00001438 bnx2.h 　
18565
 BNX2_EMAC_MAC_MATCH11BNX2_EMAC_MAC_MATCH11 0x0000143c bnx2.h 　
18566
 BNX2_EMAC_MAC_MATCH12BNX2_EMAC_MAC_MATCH12 0x00001440 bnx2.h 　
18567
 BNX2_EMAC_MAC_MATCH13BNX2_EMAC_MAC_MATCH13 0x00001444 bnx2.h 　
18568
 BNX2_EMAC_MAC_MATCH14BNX2_EMAC_MAC_MATCH14 0x00001448 bnx2.h 　
18569
 BNX2_EMAC_MAC_MATCH15BNX2_EMAC_MAC_MATCH15 0x0000144c bnx2.h 　
18570
 BNX2_EMAC_MAC_MATCH16BNX2_EMAC_MAC_MATCH16 0x00001450 bnx2.h 　
18571
 BNX2_EMAC_MAC_MATCH17BNX2_EMAC_MAC_MATCH17 0x00001454 bnx2.h 　
18572
 BNX2_EMAC_MAC_MATCH18BNX2_EMAC_MAC_MATCH18 0x00001458 bnx2.h 　
18573
 BNX2_EMAC_MAC_MATCH19BNX2_EMAC_MAC_MATCH19 0x0000145c bnx2.h 　
18574
 BNX2_EMAC_MAC_MATCH20BNX2_EMAC_MAC_MATCH20 0x00001460 bnx2.h 　
18575
 BNX2_EMAC_MAC_MATCH21BNX2_EMAC_MAC_MATCH21 0x00001464 bnx2.h 　
18576
 BNX2_EMAC_MAC_MATCH22BNX2_EMAC_MAC_MATCH22 0x00001468 bnx2.h 　
18577
 BNX2_EMAC_MAC_MATCH23BNX2_EMAC_MAC_MATCH23 0x0000146c bnx2.h 　
18578
 BNX2_EMAC_MAC_MATCH24BNX2_EMAC_MAC_MATCH24 0x00001470 bnx2.h 　
18579
 BNX2_EMAC_MAC_MATCH25BNX2_EMAC_MAC_MATCH25 0x00001474 bnx2.h 　
18580
 BNX2_EMAC_MAC_MATCH26BNX2_EMAC_MAC_MATCH26 0x00001478 bnx2.h 　
18581
 BNX2_EMAC_MAC_MATCH27BNX2_EMAC_MAC_MATCH27 0x0000147c bnx2.h 　
18582
 BNX2_EMAC_MAC_MATCH28BNX2_EMAC_MAC_MATCH28 0x00001480 bnx2.h 　
18583
 BNX2_EMAC_MAC_MATCH29BNX2_EMAC_MAC_MATCH29 0x00001484 bnx2.h 　
18584
 BNX2_EMAC_MAC_MATCH30BNX2_EMAC_MAC_MATCH30 0x00001488 bnx2.h 　
18585
 BNX2_EMAC_MAC_MATCH31BNX2_EMAC_MAC_MATCH31 0x0000148c bnx2.h 　
18586
 BNX2_EMAC_BACKOFF_SEEDBNX2_EMAC_BACKOFF_SEED 0x00001498 bnx2.h 　
18587
 BNX2_EMAC_BACKOFF_SEED_EMAC_BACBNX2_EMAC_BACKOFF_SEED_EMAC_BAC (0x3ffL<<0) bnx2.h 　
18588
 BNX2_EMAC_RX_MTU_SIZEBNX2_EMAC_RX_MTU_SIZE 0x0000149c bnx2.h 　
18589
 BNX2_EMAC_RX_MTU_SIZE_MTU_SIZEBNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0) bnx2.h 　
18590
 BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENABNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31) bnx2.h 　
18591
 BNX2_EMAC_SERDES_CNTLBNX2_EMAC_SERDES_CNTL 0x000014a4 bnx2.h 　
18592
 BNX2_EMAC_SERDES_CNTL_RXRBNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0) bnx2.h 　
18593
 BNX2_EMAC_SERDES_CNTL_RXGBNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3) bnx2.h 　
18594
 BNX2_EMAC_SERDES_CNTL_RXCKSELBNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6) bnx2.h 　
18595
 BNX2_EMAC_SERDES_CNTL_TXBIASBNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7) bnx2.h 　
18596
 BNX2_EMAC_SERDES_CNTL_BGMAXBNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10) bnx2.h 　
18597
 BNX2_EMAC_SERDES_CNTL_BGMINBNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11) bnx2.h 　
18598
 BNX2_EMAC_SERDES_CNTL_TXMODEBNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12) bnx2.h 　
18599
 BNX2_EMAC_SERDES_CNTL_TXEDGEBNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13) bnx2.h 　
18600
 BNX2_EMAC_SERDES_CNTL_SERDES_MOBNX2_EMAC_SERDES_CNTL_SERDES_MO (1L<<14) bnx2.h 　
18601
 BNX2_EMAC_SERDES_CNTL_PLLTESTBNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15) bnx2.h 　
18602
 BNX2_EMAC_SERDES_CNTL_CDET_ENBNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16) bnx2.h 　
18603
 BNX2_EMAC_SERDES_CNTL_TBI_LBKBNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17) bnx2.h 　
18604
 BNX2_EMAC_SERDES_CNTL_REMOTE_LBBNX2_EMAC_SERDES_CNTL_REMOTE_LB (1L<<18) bnx2.h 　
18605
 BNX2_EMAC_SERDES_CNTL_REV_PHASEBNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19) bnx2.h 　
18606
 BNX2_EMAC_SERDES_CNTL_REGCTL12BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20) bnx2.h 　
18607
 BNX2_EMAC_SERDES_CNTL_REGCTL25BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22) bnx2.h 　
18608
 BNX2_EMAC_SERDES_STATUSBNX2_EMAC_SERDES_STATUS 0x000014a8 bnx2.h 　
18609
 BNX2_EMAC_SERDES_STATUS_RX_STATBNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0) bnx2.h 　
18610
 BNX2_EMAC_SERDES_STATUS_COMMA_DBNX2_EMAC_SERDES_STATUS_COMMA_D (1L<<8) bnx2.h 　
18611
 BNX2_EMAC_MDIO_COMMBNX2_EMAC_MDIO_COMM 0x000014ac bnx2.h 　
18612
 BNX2_EMAC_MDIO_COMM_DATABNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0) bnx2.h 　
18613
 BNX2_EMAC_MDIO_COMM_REG_ADDRBNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16) bnx2.h 　
18614
 BNX2_EMAC_MDIO_COMM_PHY_ADDRBNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21) bnx2.h 　
18615
 BNX2_EMAC_MDIO_COMM_COMMANDBNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26) bnx2.h 　
18616
 BNX2_EMAC_MDIO_COMM_COMMAND_UNDBNX2_EMAC_MDIO_COMM_COMMAND_UND (0L<<26) bnx2.h 　
18617
 BNX2_EMAC_MDIO_COMM_COMMAND_WRIBNX2_EMAC_MDIO_COMM_COMMAND_WRI (1L<<26) bnx2.h 　
18618
 BNX2_EMAC_MDIO_COMM_COMMAND_REABNX2_EMAC_MDIO_COMM_COMMAND_REA (2L<<26) bnx2.h 　
18619
 BNX2_EMAC_MDIO_COMM_COMMAND_UNDBNX2_EMAC_MDIO_COMM_COMMAND_UND (3L<<26) bnx2.h 　
18620
 BNX2_EMAC_MDIO_COMM_FAILBNX2_EMAC_MDIO_COMM_FAIL (1L<<28) bnx2.h 　
18621
 BNX2_EMAC_MDIO_COMM_START_BUSYBNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29) bnx2.h 　
18622
 BNX2_EMAC_MDIO_COMM_DISEXTBNX2_EMAC_MDIO_COMM_DISEXT (1L<<30) bnx2.h 　
18623
 BNX2_EMAC_MDIO_STATUSBNX2_EMAC_MDIO_STATUS 0x000014b0 bnx2.h 　
18624
 BNX2_EMAC_MDIO_STATUS_LINKBNX2_EMAC_MDIO_STATUS_LINK (1L<<0) bnx2.h 　
18625
 BNX2_EMAC_MDIO_STATUS_10MBBNX2_EMAC_MDIO_STATUS_10MB (1L<<1) bnx2.h 　
18626
 BNX2_EMAC_MDIO_MODEBNX2_EMAC_MDIO_MODE 0x000014b4 bnx2.h 　
18627
 BNX2_EMAC_MDIO_MODE_SHORT_PREAMBNX2_EMAC_MDIO_MODE_SHORT_PREAM (1L<<1) bnx2.h 　
18628
 BNX2_EMAC_MDIO_MODE_AUTO_POLLBNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4) bnx2.h 　
18629
 BNX2_EMAC_MDIO_MODE_BIT_BANGBNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8) bnx2.h 　
18630
 BNX2_EMAC_MDIO_MODE_MDIOBNX2_EMAC_MDIO_MODE_MDIO (1L<<9) bnx2.h 　
18631
 BNX2_EMAC_MDIO_MODE_MDIO_OEBNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10) bnx2.h 　
18632
 BNX2_EMAC_MDIO_MODE_MDCBNX2_EMAC_MDIO_MODE_MDC (1L<<11) bnx2.h 　
18633
 BNX2_EMAC_MDIO_MODE_MDINTBNX2_EMAC_MDIO_MODE_MDINT (1L<<12) bnx2.h 　
18634
 BNX2_EMAC_MDIO_MODE_CLOCK_CNTBNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16) bnx2.h 　
18635
 BNX2_EMAC_MDIO_AUTO_STATUSBNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8 bnx2.h 　
18636
 BNX2_EMAC_MDIO_AUTO_STATUS_AUTOBNX2_EMAC_MDIO_AUTO_STATUS_AUTO (1L<<0) bnx2.h 　
18637
 BNX2_EMAC_TX_MODEBNX2_EMAC_TX_MODE 0x000014bc bnx2.h 　
18638
 BNX2_EMAC_TX_MODE_RESETBNX2_EMAC_TX_MODE_RESET (1L<<0) bnx2.h 　
18639
 BNX2_EMAC_TX_MODE_EXT_PAUSE_ENBNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3) bnx2.h 　
18640
 BNX2_EMAC_TX_MODE_FLOW_ENBNX2_EMAC_TX_MODE_FLOW_EN (1L<<4) bnx2.h 　
18641
 BNX2_EMAC_TX_MODE_BIG_BACKOFFBNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5) bnx2.h 　
18642
 BNX2_EMAC_TX_MODE_LONG_PAUSEBNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6) bnx2.h 　
18643
 BNX2_EMAC_TX_MODE_LINK_AWAREBNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7) bnx2.h 　
18644
 BNX2_EMAC_TX_STATUSBNX2_EMAC_TX_STATUS 0x000014c0 bnx2.h 　
18645
 BNX2_EMAC_TX_STATUS_XOFFEDBNX2_EMAC_TX_STATUS_XOFFED (1L<<0) bnx2.h 　
18646
 BNX2_EMAC_TX_STATUS_XOFF_SENTBNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1) bnx2.h 　
18647
 BNX2_EMAC_TX_STATUS_XON_SENTBNX2_EMAC_TX_STATUS_XON_SENT (1L<<2) bnx2.h 　
18648
 BNX2_EMAC_TX_STATUS_LINK_UPBNX2_EMAC_TX_STATUS_LINK_UP (1L<<3) bnx2.h 　
18649
 BNX2_EMAC_TX_STATUS_UNDERRUNBNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4) bnx2.h 　
18650
 BNX2_EMAC_TX_LENGTHSBNX2_EMAC_TX_LENGTHS 0x000014c4 bnx2.h 　
18651
 BNX2_EMAC_TX_LENGTHS_SLOTBNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0) bnx2.h 　
18652
 BNX2_EMAC_TX_LENGTHS_IPGBNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8) bnx2.h 　
18653
 BNX2_EMAC_TX_LENGTHS_IPG_CRSBNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12) bnx2.h 　
18654
 BNX2_EMAC_RX_MODEBNX2_EMAC_RX_MODE 0x000014c8 bnx2.h 　
18655
 BNX2_EMAC_RX_MODE_RESETBNX2_EMAC_RX_MODE_RESET (1L<<0) bnx2.h 　
18656
 BNX2_EMAC_RX_MODE_FLOW_ENBNX2_EMAC_RX_MODE_FLOW_EN (1L<<2) bnx2.h 　
18657
 BNX2_EMAC_RX_MODE_KEEP_MAC_CONTBNX2_EMAC_RX_MODE_KEEP_MAC_CONT (1L<<3) bnx2.h 　
18658
 BNX2_EMAC_RX_MODE_KEEP_PAUSEBNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4) bnx2.h 　
18659
 BNX2_EMAC_RX_MODE_ACCEPT_OVERSIBNX2_EMAC_RX_MODE_ACCEPT_OVERSI (1L<<5) bnx2.h 　
18660
 BNX2_EMAC_RX_MODE_ACCEPT_RUNTSBNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6) bnx2.h 　
18661
 BNX2_EMAC_RX_MODE_LLC_CHKBNX2_EMAC_RX_MODE_LLC_CHK (1L<<7) bnx2.h 　
18662
 BNX2_EMAC_RX_MODE_PROMISCUOUSBNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8) bnx2.h 　
18663
 BNX2_EMAC_RX_MODE_NO_CRC_CHKBNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9) bnx2.h 　
18664
 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAGBNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10) bnx2.h 　
18665
 BNX2_EMAC_RX_MODE_FILT_BROADCASBNX2_EMAC_RX_MODE_FILT_BROADCAS (1L<<11) bnx2.h 　
18666
 BNX2_EMAC_RX_MODE_SORT_MODEBNX2_EMAC_RX_MODE_SORT_MODE (1L<<12) bnx2.h 　
18667
 BNX2_EMAC_RX_STATUSBNX2_EMAC_RX_STATUS 0x000014cc bnx2.h 　
18668
 BNX2_EMAC_RX_STATUS_FFEDBNX2_EMAC_RX_STATUS_FFED (1L<<0) bnx2.h 　
18669
 BNX2_EMAC_RX_STATUS_FF_RECEIVEDBNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1) bnx2.h 　
18670
 BNX2_EMAC_RX_STATUS_N_RECEIVEDBNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2) bnx2.h 　
18671
 BNX2_EMAC_MULTICAST_HASH0BNX2_EMAC_MULTICAST_HASH0 0x000014d0 bnx2.h 　
18672
 BNX2_EMAC_MULTICAST_HASH1BNX2_EMAC_MULTICAST_HASH1 0x000014d4 bnx2.h 　
18673
 BNX2_EMAC_MULTICAST_HASH2BNX2_EMAC_MULTICAST_HASH2 0x000014d8 bnx2.h 　
18674
 BNX2_EMAC_MULTICAST_HASH3BNX2_EMAC_MULTICAST_HASH3 0x000014dc bnx2.h 　
18675
 BNX2_EMAC_MULTICAST_HASH4BNX2_EMAC_MULTICAST_HASH4 0x000014e0 bnx2.h 　
18676
 BNX2_EMAC_MULTICAST_HASH5BNX2_EMAC_MULTICAST_HASH5 0x000014e4 bnx2.h 　
18677
 BNX2_EMAC_MULTICAST_HASH6BNX2_EMAC_MULTICAST_HASH6 0x000014e8 bnx2.h 　
18678
 BNX2_EMAC_MULTICAST_HASH7BNX2_EMAC_MULTICAST_HASH7 0x000014ec bnx2.h 　
18679
 BNX2_EMAC_RX_STAT_IFHCINOCTETSBNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500 bnx2.h 　
18680
 BNX2_EMAC_RX_STAT_IFHCINBADOCTEBNX2_EMAC_RX_STAT_IFHCINBADOCTE 0x00001504 bnx2.h 　
18681
 BNX2_EMAC_RX_STAT_ETHERSTATSFRABNX2_EMAC_RX_STAT_ETHERSTATSFRA 0x00001508 bnx2.h 　
18682
 BNX2_EMAC_RX_STAT_IFHCINUCASTPKBNX2_EMAC_RX_STAT_IFHCINUCASTPK 0x0000150c bnx2.h 　
18683
 BNX2_EMAC_RX_STAT_IFHCINMULTICABNX2_EMAC_RX_STAT_IFHCINMULTICA 0x00001510 bnx2.h 　
18684
 BNX2_EMAC_RX_STAT_IFHCINBROADCABNX2_EMAC_RX_STAT_IFHCINBROADCA 0x00001514 bnx2.h 　
18685
 BNX2_EMAC_RX_STAT_DOT3STATSFCSEBNX2_EMAC_RX_STAT_DOT3STATSFCSE 0x00001518 bnx2.h 　
18686
 BNX2_EMAC_RX_STAT_DOT3STATSALIGBNX2_EMAC_RX_STAT_DOT3STATSALIG 0x0000151c bnx2.h 　
18687
 BNX2_EMAC_RX_STAT_DOT3STATSCARRBNX2_EMAC_RX_STAT_DOT3STATSCARR 0x00001520 bnx2.h 　
18688
 BNX2_EMAC_RX_STAT_XONPAUSEFRAMEBNX2_EMAC_RX_STAT_XONPAUSEFRAME 0x00001524 bnx2.h 　
18689
 BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMBNX2_EMAC_RX_STAT_XOFFPAUSEFRAM 0x00001528 bnx2.h 　
18690
 BNX2_EMAC_RX_STAT_MACCONTROLFRABNX2_EMAC_RX_STAT_MACCONTROLFRA 0x0000152c bnx2.h 　
18691
 BNX2_EMAC_RX_STAT_XOFFSTATEENTEBNX2_EMAC_RX_STAT_XOFFSTATEENTE 0x00001530 bnx2.h 　
18692
 BNX2_EMAC_RX_STAT_DOT3STATSFRAMBNX2_EMAC_RX_STAT_DOT3STATSFRAM 0x00001534 bnx2.h 　
18693
 BNX2_EMAC_RX_STAT_ETHERSTATSJABBNX2_EMAC_RX_STAT_ETHERSTATSJAB 0x00001538 bnx2.h 　
18694
 BNX2_EMAC_RX_STAT_ETHERSTATSUNDBNX2_EMAC_RX_STAT_ETHERSTATSUND 0x0000153c bnx2.h 　
18695
 BNX2_EMAC_RX_STAT_ETHERSTATSPKTBNX2_EMAC_RX_STAT_ETHERSTATSPKT 0x00001540 bnx2.h 　
18696
 BNX2_EMAC_RX_STAT_ETHERSTATSPKTBNX2_EMAC_RX_STAT_ETHERSTATSPKT 0x00001544 bnx2.h 　
18697
 BNX2_EMAC_RX_STAT_ETHERSTATSPKTBNX2_EMAC_RX_STAT_ETHERSTATSPKT 0x00001548 bnx2.h 　
18698
 BNX2_EMAC_RX_STAT_ETHERSTATSPKTBNX2_EMAC_RX_STAT_ETHERSTATSPKT 0x0000154c bnx2.h 　
18699
 BNX2_EMAC_RX_STAT_ETHERSTATSPKTBNX2_EMAC_RX_STAT_ETHERSTATSPKT 0x00001550 bnx2.h 　
18700
 BNX2_EMAC_RX_STAT_ETHERSTATSPKTBNX2_EMAC_RX_STAT_ETHERSTATSPKT 0x00001554 bnx2.h 　
18701
 BNX2_EMAC_RX_STAT_ETHERSTATSPKTBNX2_EMAC_RX_STAT_ETHERSTATSPKT 0x00001558 bnx2.h 　
18702
 BNX2_EMAC_RXMAC_DEBUG0BNX2_EMAC_RXMAC_DEBUG0 0x0000155c bnx2.h 　
18703
 BNX2_EMAC_RXMAC_DEBUG1BNX2_EMAC_RXMAC_DEBUG1 0x00001560 bnx2.h 　
18704
 BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NBNX2_EMAC_RXMAC_DEBUG1_LENGTH_N (1L<<0) bnx2.h 　
18705
 BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OBNX2_EMAC_RXMAC_DEBUG1_LENGTH_O (1L<<1) bnx2.h 　
18706
 BNX2_EMAC_RXMAC_DEBUG1_BAD_CRCBNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2) bnx2.h 　
18707
 BNX2_EMAC_RXMAC_DEBUG1_RX_ERRORBNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3) bnx2.h 　
18708
 BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERBNX2_EMAC_RXMAC_DEBUG1_ALIGN_ER (1L<<4) bnx2.h 　
18709
 BNX2_EMAC_RXMAC_DEBUG1_LAST_DATBNX2_EMAC_RXMAC_DEBUG1_LAST_DAT (1L<<5) bnx2.h 　
18710
 BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTEBNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE (1L<<6) bnx2.h 　
18711
 BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUBNX2_EMAC_RXMAC_DEBUG1_BYTE_COU (0xffffL<<7) bnx2.h 　
18712
 BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIMBNX2_EMAC_RXMAC_DEBUG1_SLOT_TIM (0xffL<<23) bnx2.h 　
18713
 BNX2_EMAC_RXMAC_DEBUG2BNX2_EMAC_RXMAC_DEBUG2 0x00001564 bnx2.h 　
18714
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) bnx2.h 　
18715
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x0L<<0) bnx2.h 　
18716
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x1L<<0) bnx2.h 　
18717
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x2L<<0) bnx2.h 　
18718
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x3L<<0) bnx2.h 　
18719
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x4L<<0) bnx2.h 　
18720
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x5L<<0) bnx2.h 　
18721
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x6L<<0) bnx2.h 　
18722
 BNX2_EMAC_RXMAC_DEBUG2_SM_STATEBNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0) bnx2.h 　
18723
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0xfL<<3) bnx2.h 　
18724
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x0L<<3) bnx2.h 　
18725
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x1L<<3) bnx2.h 　
18726
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x2L<<3) bnx2.h 　
18727
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x3L<<3) bnx2.h 　
18728
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x4L<<3) bnx2.h 　
18729
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x5L<<3) bnx2.h 　
18730
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x6L<<3) bnx2.h 　
18731
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x7L<<3) bnx2.h 　
18732
 BNX2_EMAC_RXMAC_DEBUG2_IDI_STATBNX2_EMAC_RXMAC_DEBUG2_IDI_STAT (0x8L<<3) bnx2.h 　
18733
 BNX2_EMAC_RXMAC_DEBUG2_BYTE_INBNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7) bnx2.h 　
18734
 BNX2_EMAC_RXMAC_DEBUG2_FALSECBNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15) bnx2.h 　
18735
 BNX2_EMAC_RXMAC_DEBUG2_TAGGEDBNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16) bnx2.h 　
18736
 BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STBNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST (1L<<18) bnx2.h 　
18737
 BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STBNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST (0L<<18) bnx2.h 　
18738
 BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STBNX2_EMAC_RXMAC_DEBUG2_PAUSE_ST (1L<<18) bnx2.h 　
18739
 BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTBNX2_EMAC_RXMAC_DEBUG2_SE_COUNT (0xfL<<19) bnx2.h 　
18740
 BNX2_EMAC_RXMAC_DEBUG2_QUANTABNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23) bnx2.h 　
18741
 BNX2_EMAC_RXMAC_DEBUG3BNX2_EMAC_RXMAC_DEBUG3 0x00001568 bnx2.h 　
18742
 BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTBNX2_EMAC_RXMAC_DEBUG3_PAUSE_CT (0xffffL<<0) bnx2.h 　
18743
 BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSBNX2_EMAC_RXMAC_DEBUG3_TMP_PAUS (0xffffL<<16) bnx2.h 　
18744
 BNX2_EMAC_RXMAC_DEBUG4BNX2_EMAC_RXMAC_DEBUG4 0x0000156c bnx2.h 　
18745
 BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIEBNX2_EMAC_RXMAC_DEBUG4_TYPE_FIE (0xffffL<<0) bnx2.h 　
18746
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x3fL<<16) bnx2.h 　
18747
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x0L<<16) bnx2.h 　
18748
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x1L<<16) bnx2.h 　
18749
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x2L<<16) bnx2.h 　
18750
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x3L<<16) bnx2.h 　
18751
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x7L<<16) bnx2.h 　
18752
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x5L<<16) bnx2.h 　
18753
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x6L<<16) bnx2.h 　
18754
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x7L<<16) bnx2.h 　
18755
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x8L<<16) bnx2.h 　
18756
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x9L<<16) bnx2.h 　
18757
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0xaL<<16) bnx2.h 　
18758
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0xeL<<16) bnx2.h 　
18759
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0xfL<<16) bnx2.h 　
18760
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x10L<<16) bnx2.h 　
18761
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x11L<<16) bnx2.h 　
18762
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x12L<<16) bnx2.h 　
18763
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x13L<<16) bnx2.h 　
18764
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x14L<<16) bnx2.h 　
18765
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x15L<<16) bnx2.h 　
18766
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x16L<<16) bnx2.h 　
18767
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x17L<<16) bnx2.h 　
18768
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x18L<<16) bnx2.h 　
18769
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x19L<<16) bnx2.h 　
18770
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x1aL<<16) bnx2.h 　
18771
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x1bL<<16) bnx2.h 　
18772
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x1cL<<16) bnx2.h 　
18773
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x1dL<<16) bnx2.h 　
18774
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x1eL<<16) bnx2.h 　
18775
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x1fL<<16) bnx2.h 　
18776
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x20L<<16) bnx2.h 　
18777
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x21L<<16) bnx2.h 　
18778
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x22L<<16) bnx2.h 　
18779
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x23L<<16) bnx2.h 　
18780
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x24L<<16) bnx2.h 　
18781
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x25L<<16) bnx2.h 　
18782
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x26L<<16) bnx2.h 　
18783
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x27L<<16) bnx2.h 　
18784
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x28L<<16) bnx2.h 　
18785
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x29L<<16) bnx2.h 　
18786
 BNX2_EMAC_RXMAC_DEBUG4_FILT_STABNX2_EMAC_RXMAC_DEBUG4_FILT_STA (0x2aL<<16) bnx2.h 　
18787
 BNX2_EMAC_RXMAC_DEBUG4_DROP_PKTBNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22) bnx2.h 　
18788
 BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILBNX2_EMAC_RXMAC_DEBUG4_SLOT_FIL (1L<<23) bnx2.h 　
18789
 BNX2_EMAC_RXMAC_DEBUG4_FALSE_CABNX2_EMAC_RXMAC_DEBUG4_FALSE_CA (1L<<24) bnx2.h 　
18790
 BNX2_EMAC_RXMAC_DEBUG4_LAST_DATBNX2_EMAC_RXMAC_DEBUG4_LAST_DAT (1L<<25) bnx2.h 　
18791
 BNX2_EMAC_RXMAC_DEBUG4_sfd_FOUNBNX2_EMAC_RXMAC_DEBUG4_sfd_FOUN (1L<<26) bnx2.h 　
18792
 BNX2_EMAC_RXMAC_DEBUG4_ADVANCEBNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27) bnx2.h 　
18793
 BNX2_EMAC_RXMAC_DEBUG4_STARTBNX2_EMAC_RXMAC_DEBUG4_START (1L<<28) bnx2.h 　
18794
 BNX2_EMAC_RXMAC_DEBUG5BNX2_EMAC_RXMAC_DEBUG5 0x00001570 bnx2.h 　
18795
 BNX2_EMAC_RXMAC_DEBUG5_PS_IDISMBNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0) bnx2.h 　
18796
 BNX2_EMAC_RXMAC_DEBUG5_PS_IDISMBNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0L<<0) bnx2.h 　
18797
 BNX2_EMAC_RXMAC_DEBUG5_PS_IDISMBNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (1L<<0) bnx2.h 　
18798
 BNX2_EMAC_RXMAC_DEBUG5_PS_IDISMBNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (2L<<0) bnx2.h 　
18799
 BNX2_EMAC_RXMAC_DEBUG5_PS_IDISMBNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (3L<<0) bnx2.h 　
18800
 BNX2_EMAC_RXMAC_DEBUG5_PS_IDISMBNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (4L<<0) bnx2.h 　
18801
 BNX2_EMAC_RXMAC_DEBUG5_PS_IDISMBNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (5L<<0) bnx2.h 　
18802
 BNX2_EMAC_RXMAC_DEBUG5_PS_IDISMBNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (6L<<0) bnx2.h 　
18803
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x7L<<4) bnx2.h 　
18804
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x0L<<4) bnx2.h 　
18805
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x1L<<4) bnx2.h 　
18806
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x2L<<4) bnx2.h 　
18807
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x3L<<4) bnx2.h 　
18808
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x4L<<4) bnx2.h 　
18809
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x6L<<4) bnx2.h 　
18810
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x7L<<4) bnx2.h 　
18811
 BNX2_EMAC_RXMAC_DEBUG5_EOF_DETEBNX2_EMAC_RXMAC_DEBUG5_EOF_DETE (1L<<7) bnx2.h 　
18812
 BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUBNX2_EMAC_RXMAC_DEBUG5_CCODE_BU (0x7L<<8) bnx2.h 　
18813
 BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_ (1L<<11) bnx2.h 　
18814
 BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCOBNX2_EMAC_RXMAC_DEBUG5_LOAD_CCO (1L<<12) bnx2.h 　
18815
 BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATBNX2_EMAC_RXMAC_DEBUG5_LOAD_DAT (1L<<13) bnx2.h 　
18816
 BNX2_EMAC_RXMAC_DEBUG5_LOAD_STABNX2_EMAC_RXMAC_DEBUG5_LOAD_STA (1L<<14) bnx2.h 　
18817
 BNX2_EMAC_RXMAC_DEBUG5_CLR_STATBNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15) bnx2.h 　
18818
 BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ (0x3L<<16) bnx2.h 　
18819
 BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ (1L<<19) bnx2.h 　
18820
 BNX2_EMAC_RXMAC_DEBUG5_FMLENBNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20) bnx2.h 　
18821
 BNX2_EMAC_RX_STAT_AC0BNX2_EMAC_RX_STAT_AC0 0x00001580 bnx2.h 　
18822
 BNX2_EMAC_RX_STAT_AC1BNX2_EMAC_RX_STAT_AC1 0x00001584 bnx2.h 　
18823
 BNX2_EMAC_RX_STAT_AC2BNX2_EMAC_RX_STAT_AC2 0x00001588 bnx2.h 　
18824
 BNX2_EMAC_RX_STAT_AC3BNX2_EMAC_RX_STAT_AC3 0x0000158c bnx2.h 　
18825
 BNX2_EMAC_RX_STAT_AC4BNX2_EMAC_RX_STAT_AC4 0x00001590 bnx2.h 　
18826
 BNX2_EMAC_RX_STAT_AC5BNX2_EMAC_RX_STAT_AC5 0x00001594 bnx2.h 　
18827
 BNX2_EMAC_RX_STAT_AC6BNX2_EMAC_RX_STAT_AC6 0x00001598 bnx2.h 　
18828
 BNX2_EMAC_RX_STAT_AC7BNX2_EMAC_RX_STAT_AC7 0x0000159c bnx2.h 　
18829
 BNX2_EMAC_RX_STAT_AC8BNX2_EMAC_RX_STAT_AC8 0x000015a0 bnx2.h 　
18830
 BNX2_EMAC_RX_STAT_AC9BNX2_EMAC_RX_STAT_AC9 0x000015a4 bnx2.h 　
18831
 BNX2_EMAC_RX_STAT_AC10BNX2_EMAC_RX_STAT_AC10 0x000015a8 bnx2.h 　
18832
 BNX2_EMAC_RX_STAT_AC11BNX2_EMAC_RX_STAT_AC11 0x000015ac bnx2.h 　
18833
 BNX2_EMAC_RX_STAT_AC12BNX2_EMAC_RX_STAT_AC12 0x000015b0 bnx2.h 　
18834
 BNX2_EMAC_RX_STAT_AC13BNX2_EMAC_RX_STAT_AC13 0x000015b4 bnx2.h 　
18835
 BNX2_EMAC_RX_STAT_AC14BNX2_EMAC_RX_STAT_AC14 0x000015b8 bnx2.h 　
18836
 BNX2_EMAC_RX_STAT_AC15BNX2_EMAC_RX_STAT_AC15 0x000015bc bnx2.h 　
18837
 BNX2_EMAC_RX_STAT_AC16BNX2_EMAC_RX_STAT_AC16 0x000015c0 bnx2.h 　
18838
 BNX2_EMAC_RX_STAT_AC17BNX2_EMAC_RX_STAT_AC17 0x000015c4 bnx2.h 　
18839
 BNX2_EMAC_RX_STAT_AC18BNX2_EMAC_RX_STAT_AC18 0x000015c8 bnx2.h 　
18840
 BNX2_EMAC_RX_STAT_AC19BNX2_EMAC_RX_STAT_AC19 0x000015cc bnx2.h 　
18841
 BNX2_EMAC_RX_STAT_AC20BNX2_EMAC_RX_STAT_AC20 0x000015d0 bnx2.h 　
18842
 BNX2_EMAC_RX_STAT_AC21BNX2_EMAC_RX_STAT_AC21 0x000015d4 bnx2.h 　
18843
 BNX2_EMAC_RX_STAT_AC22BNX2_EMAC_RX_STAT_AC22 0x000015d8 bnx2.h 　
18844
 BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNBNX2_EMAC_RXMAC_SUC_DBG_OVERRUN 0x000015dc bnx2.h 　
18845
 BNX2_EMAC_TX_STAT_IFHCOUTOCTETSBNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600 bnx2.h 　
18846
 BNX2_EMAC_TX_STAT_IFHCOUTBADOCTBNX2_EMAC_TX_STAT_IFHCOUTBADOCT 0x00001604 bnx2.h 　
18847
 BNX2_EMAC_TX_STAT_ETHERSTATSCOLBNX2_EMAC_TX_STAT_ETHERSTATSCOL 0x00001608 bnx2.h 　
18848
 BNX2_EMAC_TX_STAT_OUTXONSENTBNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c bnx2.h 　
18849
 BNX2_EMAC_TX_STAT_OUTXOFFSENTBNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610 bnx2.h 　
18850
 BNX2_EMAC_TX_STAT_FLOWCONTROLDOBNX2_EMAC_TX_STAT_FLOWCONTROLDO 0x00001614 bnx2.h 　
18851
 BNX2_EMAC_TX_STAT_DOT3STATSSINGBNX2_EMAC_TX_STAT_DOT3STATSSING 0x00001618 bnx2.h 　
18852
 BNX2_EMAC_TX_STAT_DOT3STATSMULTBNX2_EMAC_TX_STAT_DOT3STATSMULT 0x0000161c bnx2.h 　
18853
 BNX2_EMAC_TX_STAT_DOT3STATSDEFEBNX2_EMAC_TX_STAT_DOT3STATSDEFE 0x00001620 bnx2.h 　
18854
 BNX2_EMAC_TX_STAT_DOT3STATSEXCEBNX2_EMAC_TX_STAT_DOT3STATSEXCE 0x00001624 bnx2.h 　
18855
 BNX2_EMAC_TX_STAT_DOT3STATSLATEBNX2_EMAC_TX_STAT_DOT3STATSLATE 0x00001628 bnx2.h 　
18856
 BNX2_EMAC_TX_STAT_IFHCOUTUCASTPBNX2_EMAC_TX_STAT_IFHCOUTUCASTP 0x0000162c bnx2.h 　
18857
 BNX2_EMAC_TX_STAT_IFHCOUTMULTICBNX2_EMAC_TX_STAT_IFHCOUTMULTIC 0x00001630 bnx2.h 　
18858
 BNX2_EMAC_TX_STAT_IFHCOUTBROADCBNX2_EMAC_TX_STAT_IFHCOUTBROADC 0x00001634 bnx2.h 　
18859
 BNX2_EMAC_TX_STAT_ETHERSTATSPKTBNX2_EMAC_TX_STAT_ETHERSTATSPKT 0x00001638 bnx2.h 　
18860
 BNX2_EMAC_TX_STAT_ETHERSTATSPKTBNX2_EMAC_TX_STAT_ETHERSTATSPKT 0x0000163c bnx2.h 　
18861
 BNX2_EMAC_TX_STAT_ETHERSTATSPKTBNX2_EMAC_TX_STAT_ETHERSTATSPKT 0x00001640 bnx2.h 　
18862
 BNX2_EMAC_TX_STAT_ETHERSTATSPKTBNX2_EMAC_TX_STAT_ETHERSTATSPKT 0x00001644 bnx2.h 　
18863
 BNX2_EMAC_TX_STAT_ETHERSTATSPKTBNX2_EMAC_TX_STAT_ETHERSTATSPKT 0x00001648 bnx2.h 　
18864
 BNX2_EMAC_TX_STAT_ETHERSTATSPKTBNX2_EMAC_TX_STAT_ETHERSTATSPKT 0x0000164c bnx2.h 　
18865
 BNX2_EMAC_TX_STAT_ETHERSTATSPKTBNX2_EMAC_TX_STAT_ETHERSTATSPKT 0x00001650 bnx2.h 　
18866
 BNX2_EMAC_TX_STAT_DOT3STATSINTEBNX2_EMAC_TX_STAT_DOT3STATSINTE 0x00001654 bnx2.h 　
18867
 BNX2_EMAC_TXMAC_DEBUG0BNX2_EMAC_TXMAC_DEBUG0 0x00001658 bnx2.h 　
18868
 BNX2_EMAC_TXMAC_DEBUG1BNX2_EMAC_TXMAC_DEBUG1 0x0000165c bnx2.h 　
18869
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0xfL<<0) bnx2.h 　
18870
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0x0L<<0) bnx2.h 　
18871
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0x1L<<0) bnx2.h 　
18872
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0x4L<<0) bnx2.h 　
18873
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0x5L<<0) bnx2.h 　
18874
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0x6L<<0) bnx2.h 　
18875
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0x7L<<0) bnx2.h 　
18876
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0x8L<<0) bnx2.h 　
18877
 BNX2_EMAC_TXMAC_DEBUG1_ODI_STATBNX2_EMAC_TXMAC_DEBUG1_ODI_STAT (0x9L<<0) bnx2.h 　
18878
 BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABBNX2_EMAC_TXMAC_DEBUG1_CRS_ENAB (1L<<4) bnx2.h 　
18879
 BNX2_EMAC_TXMAC_DEBUG1_BAD_CRCBNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5) bnx2.h 　
18880
 BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTBNX2_EMAC_TXMAC_DEBUG1_SE_COUNT (0xfL<<6) bnx2.h 　
18881
 BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUBNX2_EMAC_TXMAC_DEBUG1_SEND_PAU (1L<<10) bnx2.h 　
18882
 BNX2_EMAC_TXMAC_DEBUG1_LATE_COLBNX2_EMAC_TXMAC_DEBUG1_LATE_COL (1L<<11) bnx2.h 　
18883
 BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFEBNX2_EMAC_TXMAC_DEBUG1_MAX_DEFE (1L<<12) bnx2.h 　
18884
 BNX2_EMAC_TXMAC_DEBUG1_DEFERREDBNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13) bnx2.h 　
18885
 BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTEBNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14) bnx2.h 　
18886
 BNX2_EMAC_TXMAC_DEBUG1_IPG_TIMEBNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15) bnx2.h 　
18887
 BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIMBNX2_EMAC_TXMAC_DEBUG1_SLOT_TIM (0xffL<<19) bnx2.h 　
18888
 BNX2_EMAC_TXMAC_DEBUG2BNX2_EMAC_TXMAC_DEBUG2 0x00001660 bnx2.h 　
18889
 BNX2_EMAC_TXMAC_DEBUG2_BACK_OFFBNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0) bnx2.h 　
18890
 BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUBNX2_EMAC_TXMAC_DEBUG2_BYTE_COU (0xffffL<<10) bnx2.h 　
18891
 BNX2_EMAC_TXMAC_DEBUG2_COL_COUNBNX2_EMAC_TXMAC_DEBUG2_COL_COUN (0x1fL<<26) bnx2.h 　
18892
 BNX2_EMAC_TXMAC_DEBUG2_COL_BITBNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31) bnx2.h 　
18893
 BNX2_EMAC_TXMAC_DEBUG3BNX2_EMAC_TXMAC_DEBUG3 0x00001664 bnx2.h 　
18894
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0) bnx2.h 　
18895
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x0L<<0) bnx2.h 　
18896
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x1L<<0) bnx2.h 　
18897
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x2L<<0) bnx2.h 　
18898
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x3L<<0) bnx2.h 　
18899
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x4L<<0) bnx2.h 　
18900
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x5L<<0) bnx2.h 　
18901
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x6L<<0) bnx2.h 　
18902
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x7L<<0) bnx2.h 　
18903
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x8L<<0) bnx2.h 　
18904
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0x9L<<0) bnx2.h 　
18905
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xaL<<0) bnx2.h 　
18906
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xbL<<0) bnx2.h 　
18907
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xcL<<0) bnx2.h 　
18908
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xdL<<0) bnx2.h 　
18909
 BNX2_EMAC_TXMAC_DEBUG3_SM_STATEBNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xeL<<0) bnx2.h 　
18910
 BNX2_EMAC_TXMAC_DEBUG3_FILT_STABNX2_EMAC_TXMAC_DEBUG3_FILT_STA (0x7L<<4) bnx2.h 　
18911
 BNX2_EMAC_TXMAC_DEBUG3_FILT_STABNX2_EMAC_TXMAC_DEBUG3_FILT_STA (0x0L<<4) bnx2.h 　
18912
 BNX2_EMAC_TXMAC_DEBUG3_FILT_STABNX2_EMAC_TXMAC_DEBUG3_FILT_STA (0x1L<<4) bnx2.h 　
18913
 BNX2_EMAC_TXMAC_DEBUG3_FILT_STABNX2_EMAC_TXMAC_DEBUG3_FILT_STA (0x2L<<4) bnx2.h 　
18914
 BNX2_EMAC_TXMAC_DEBUG3_FILT_STABNX2_EMAC_TXMAC_DEBUG3_FILT_STA (0x3L<<4) bnx2.h 　
18915
 BNX2_EMAC_TXMAC_DEBUG3_FILT_STABNX2_EMAC_TXMAC_DEBUG3_FILT_STA (0x4L<<4) bnx2.h 　
18916
 BNX2_EMAC_TXMAC_DEBUG3_FILT_STABNX2_EMAC_TXMAC_DEBUG3_FILT_STA (0x5L<<4) bnx2.h 　
18917
 BNX2_EMAC_TXMAC_DEBUG3_FILT_STABNX2_EMAC_TXMAC_DEBUG3_FILT_STA (0x6L<<4) bnx2.h 　
18918
 BNX2_EMAC_TXMAC_DEBUG3_CRS_DONEBNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7) bnx2.h 　
18919
 BNX2_EMAC_TXMAC_DEBUG3_XOFFBNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8) bnx2.h 　
18920
 BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTBNX2_EMAC_TXMAC_DEBUG3_SE_COUNT (0xfL<<9) bnx2.h 　
18921
 BNX2_EMAC_TXMAC_DEBUG3_QUANTA_CBNX2_EMAC_TXMAC_DEBUG3_QUANTA_C (0x1fL<<13) bnx2.h 　
18922
 BNX2_EMAC_TXMAC_DEBUG4BNX2_EMAC_TXMAC_DEBUG4 0x00001668 bnx2.h 　
18923
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COBNX2_EMAC_TXMAC_DEBUG4_PAUSE_CO (0xffffL<<0) bnx2.h 　
18924
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0xfL<<16) bnx2.h 　
18925
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x0L<<16) bnx2.h 　
18926
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x2L<<16) bnx2.h 　
18927
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x3L<<16) bnx2.h 　
18928
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x6L<<16) bnx2.h 　
18929
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x7L<<16) bnx2.h 　
18930
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x5L<<16) bnx2.h 　
18931
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x4L<<16) bnx2.h 　
18932
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0xcL<<16) bnx2.h 　
18933
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0xeL<<16) bnx2.h 　
18934
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0xaL<<16) bnx2.h 　
18935
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x8L<<16) bnx2.h 　
18936
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0x9L<<16) bnx2.h 　
18937
 BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STBNX2_EMAC_TXMAC_DEBUG4_PAUSE_ST (0xdL<<16) bnx2.h 　
18938
 BNX2_EMAC_TXMAC_DEBUG4_STATS0_VBNX2_EMAC_TXMAC_DEBUG4_STATS0_V (1L<<20) bnx2.h 　
18939
 BNX2_EMAC_TXMAC_DEBUG4_APPEND_CBNX2_EMAC_TXMAC_DEBUG4_APPEND_C (1L<<21) bnx2.h 　
18940
 BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILBNX2_EMAC_TXMAC_DEBUG4_SLOT_FIL (1L<<22) bnx2.h 　
18941
 BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFEBNX2_EMAC_TXMAC_DEBUG4_MAX_DEFE (1L<<23) bnx2.h 　
18942
 BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTBNX2_EMAC_TXMAC_DEBUG4_SEND_EXT (1L<<24) bnx2.h 　
18943
 BNX2_EMAC_TXMAC_DEBUG4_SEND_PADBNX2_EMAC_TXMAC_DEBUG4_SEND_PAD (1L<<25) bnx2.h 　
18944
 BNX2_EMAC_TXMAC_DEBUG4_EOF_LOCBNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26) bnx2.h 　
18945
 BNX2_EMAC_TXMAC_DEBUG4_COLLIDINBNX2_EMAC_TXMAC_DEBUG4_COLLIDIN (1L<<27) bnx2.h 　
18946
 BNX2_EMAC_TXMAC_DEBUG4_COL_INBNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28) bnx2.h 　
18947
 BNX2_EMAC_TXMAC_DEBUG4_BURSTINGBNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29) bnx2.h 　
18948
 BNX2_EMAC_TXMAC_DEBUG4_ADVANCEBNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30) bnx2.h 　
18949
 BNX2_EMAC_TXMAC_DEBUG4_GOBNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31) bnx2.h 　
18950
 BNX2_EMAC_TX_STAT_AC0BNX2_EMAC_TX_STAT_AC0 0x00001680 bnx2.h 　
18951
 BNX2_EMAC_TX_STAT_AC1BNX2_EMAC_TX_STAT_AC1 0x00001684 bnx2.h 　
18952
 BNX2_EMAC_TX_STAT_AC2BNX2_EMAC_TX_STAT_AC2 0x00001688 bnx2.h 　
18953
 BNX2_EMAC_TX_STAT_AC3BNX2_EMAC_TX_STAT_AC3 0x0000168c bnx2.h 　
18954
 BNX2_EMAC_TX_STAT_AC4BNX2_EMAC_TX_STAT_AC4 0x00001690 bnx2.h 　
18955
 BNX2_EMAC_TX_STAT_AC5BNX2_EMAC_TX_STAT_AC5 0x00001694 bnx2.h 　
18956
 BNX2_EMAC_TX_STAT_AC6BNX2_EMAC_TX_STAT_AC6 0x00001698 bnx2.h 　
18957
 BNX2_EMAC_TX_STAT_AC7BNX2_EMAC_TX_STAT_AC7 0x0000169c bnx2.h 　
18958
 BNX2_EMAC_TX_STAT_AC8BNX2_EMAC_TX_STAT_AC8 0x000016a0 bnx2.h 　
18959
 BNX2_EMAC_TX_STAT_AC9BNX2_EMAC_TX_STAT_AC9 0x000016a4 bnx2.h 　
18960
 BNX2_EMAC_TX_STAT_AC10BNX2_EMAC_TX_STAT_AC10 0x000016a8 bnx2.h 　
18961
 BNX2_EMAC_TX_STAT_AC11BNX2_EMAC_TX_STAT_AC11 0x000016ac bnx2.h 　
18962
 BNX2_EMAC_TX_STAT_AC12BNX2_EMAC_TX_STAT_AC12 0x000016b0 bnx2.h 　
18963
 BNX2_EMAC_TX_STAT_AC13BNX2_EMAC_TX_STAT_AC13 0x000016b4 bnx2.h 　
18964
 BNX2_EMAC_TX_STAT_AC14BNX2_EMAC_TX_STAT_AC14 0x000016b8 bnx2.h 　
18965
 BNX2_EMAC_TX_STAT_AC15BNX2_EMAC_TX_STAT_AC15 0x000016bc bnx2.h 　
18966
 BNX2_EMAC_TX_STAT_AC16BNX2_EMAC_TX_STAT_AC16 0x000016c0 bnx2.h 　
18967
 BNX2_EMAC_TX_STAT_AC17BNX2_EMAC_TX_STAT_AC17 0x000016c4 bnx2.h 　
18968
 BNX2_EMAC_TX_STAT_AC18BNX2_EMAC_TX_STAT_AC18 0x000016c8 bnx2.h 　
18969
 BNX2_EMAC_TX_STAT_AC19BNX2_EMAC_TX_STAT_AC19 0x000016cc bnx2.h 　
18970
 BNX2_EMAC_TX_STAT_AC20BNX2_EMAC_TX_STAT_AC20 0x000016d0 bnx2.h 　
18971
 BNX2_EMAC_TX_STAT_AC21BNX2_EMAC_TX_STAT_AC21 0x000016d4 bnx2.h 　
18972
 BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNBNX2_EMAC_TXMAC_SUC_DBG_OVERRUN 0x000016d8 bnx2.h 　
18973
 BNX2_RPM_COMMANDBNX2_RPM_COMMAND 0x00001800 bnx2.h 　
18974
 BNX2_RPM_COMMAND_ENABLEDBNX2_RPM_COMMAND_ENABLED (1L<<0) bnx2.h 　
18975
 BNX2_RPM_COMMAND_OVERRUN_ABORTBNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4) bnx2.h 　
18976
 BNX2_RPM_STATUSBNX2_RPM_STATUS 0x00001804 bnx2.h 　
18977
 BNX2_RPM_STATUS_MBUF_WAITBNX2_RPM_STATUS_MBUF_WAIT (1L<<0) bnx2.h 　
18978
 BNX2_RPM_STATUS_FREE_WAITBNX2_RPM_STATUS_FREE_WAIT (1L<<1) bnx2.h 　
18979
 BNX2_RPM_CONFIGBNX2_RPM_CONFIG 0x00001808 bnx2.h 　
18980
 BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUBNX2_RPM_CONFIG_NO_PSD_HDR_CKSU (1L<<0) bnx2.h 　
18981
 BNX2_RPM_CONFIG_ACPI_ENABNX2_RPM_CONFIG_ACPI_ENA (1L<<1) bnx2.h 　
18982
 BNX2_RPM_CONFIG_ACPI_KEEPBNX2_RPM_CONFIG_ACPI_KEEP (1L<<2) bnx2.h 　
18983
 BNX2_RPM_CONFIG_MP_KEEPBNX2_RPM_CONFIG_MP_KEEP (1L<<3) bnx2.h 　
18984
 BNX2_RPM_CONFIG_SORT_VECT_VALBNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4) bnx2.h 　
18985
 BNX2_RPM_CONFIG_IGNORE_VLANBNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31) bnx2.h 　
18986
 BNX2_RPM_VLAN_MATCH0BNX2_RPM_VLAN_MATCH0 0x00001810 bnx2.h 　
18987
 BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MBNX2_RPM_VLAN_MATCH0_RPM_VLAN_M (0xfffL<<0) bnx2.h 　
18988
 BNX2_RPM_VLAN_MATCH1BNX2_RPM_VLAN_MATCH1 0x00001814 bnx2.h 　
18989
 BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MBNX2_RPM_VLAN_MATCH1_RPM_VLAN_M (0xfffL<<0) bnx2.h 　
18990
 BNX2_RPM_VLAN_MATCH2BNX2_RPM_VLAN_MATCH2 0x00001818 bnx2.h 　
18991
 BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MBNX2_RPM_VLAN_MATCH2_RPM_VLAN_M (0xfffL<<0) bnx2.h 　
18992
 BNX2_RPM_VLAN_MATCH3BNX2_RPM_VLAN_MATCH3 0x0000181c bnx2.h 　
18993
 BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MBNX2_RPM_VLAN_MATCH3_RPM_VLAN_M (0xfffL<<0) bnx2.h 　
18994
 BNX2_RPM_SORT_USER0BNX2_RPM_SORT_USER0 0x00001820 bnx2.h 　
18995
 BNX2_RPM_SORT_USER0_PM_ENBNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0) bnx2.h 　
18996
 BNX2_RPM_SORT_USER0_BC_ENBNX2_RPM_SORT_USER0_BC_EN (1L<<16) bnx2.h 　
18997
 BNX2_RPM_SORT_USER0_MC_ENBNX2_RPM_SORT_USER0_MC_EN (1L<<17) bnx2.h 　
18998
 BNX2_RPM_SORT_USER0_MC_HSH_ENBNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18) bnx2.h 　
18999
 BNX2_RPM_SORT_USER0_PROM_ENBNX2_RPM_SORT_USER0_PROM_EN (1L<<19) bnx2.h 　
19000
 BNX2_RPM_SORT_USER0_VLAN_ENBNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20) bnx2.h 　
19001
 BNX2_RPM_SORT_USER0_PROM_VLANBNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24) bnx2.h 　
19002
 BNX2_RPM_SORT_USER0_ENABNX2_RPM_SORT_USER0_ENA (1L<<31) bnx2.h 　
19003
 BNX2_RPM_SORT_USER1BNX2_RPM_SORT_USER1 0x00001824 bnx2.h 　
19004
 BNX2_RPM_SORT_USER1_PM_ENBNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0) bnx2.h 　
19005
 BNX2_RPM_SORT_USER1_BC_ENBNX2_RPM_SORT_USER1_BC_EN (1L<<16) bnx2.h 　
19006
 BNX2_RPM_SORT_USER1_MC_ENBNX2_RPM_SORT_USER1_MC_EN (1L<<17) bnx2.h 　
19007
 BNX2_RPM_SORT_USER1_MC_HSH_ENBNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18) bnx2.h 　
19008
 BNX2_RPM_SORT_USER1_PROM_ENBNX2_RPM_SORT_USER1_PROM_EN (1L<<19) bnx2.h 　
19009
 BNX2_RPM_SORT_USER1_VLAN_ENBNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20) bnx2.h 　
19010
 BNX2_RPM_SORT_USER1_PROM_VLANBNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24) bnx2.h 　
19011
 BNX2_RPM_SORT_USER1_ENABNX2_RPM_SORT_USER1_ENA (1L<<31) bnx2.h 　
19012
 BNX2_RPM_SORT_USER2BNX2_RPM_SORT_USER2 0x00001828 bnx2.h 　
19013
 BNX2_RPM_SORT_USER2_PM_ENBNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0) bnx2.h 　
19014
 BNX2_RPM_SORT_USER2_BC_ENBNX2_RPM_SORT_USER2_BC_EN (1L<<16) bnx2.h 　
19015
 BNX2_RPM_SORT_USER2_MC_ENBNX2_RPM_SORT_USER2_MC_EN (1L<<17) bnx2.h 　
19016
 BNX2_RPM_SORT_USER2_MC_HSH_ENBNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18) bnx2.h 　
19017
 BNX2_RPM_SORT_USER2_PROM_ENBNX2_RPM_SORT_USER2_PROM_EN (1L<<19) bnx2.h 　
19018
 BNX2_RPM_SORT_USER2_VLAN_ENBNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20) bnx2.h 　
19019
 BNX2_RPM_SORT_USER2_PROM_VLANBNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24) bnx2.h 　
19020
 BNX2_RPM_SORT_USER2_ENABNX2_RPM_SORT_USER2_ENA (1L<<31) bnx2.h 　
19021
 BNX2_RPM_SORT_USER3BNX2_RPM_SORT_USER3 0x0000182c bnx2.h 　
19022
 BNX2_RPM_SORT_USER3_PM_ENBNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0) bnx2.h 　
19023
 BNX2_RPM_SORT_USER3_BC_ENBNX2_RPM_SORT_USER3_BC_EN (1L<<16) bnx2.h 　
19024
 BNX2_RPM_SORT_USER3_MC_ENBNX2_RPM_SORT_USER3_MC_EN (1L<<17) bnx2.h 　
19025
 BNX2_RPM_SORT_USER3_MC_HSH_ENBNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18) bnx2.h 　
19026
 BNX2_RPM_SORT_USER3_PROM_ENBNX2_RPM_SORT_USER3_PROM_EN (1L<<19) bnx2.h 　
19027
 BNX2_RPM_SORT_USER3_VLAN_ENBNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20) bnx2.h 　
19028
 BNX2_RPM_SORT_USER3_PROM_VLANBNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24) bnx2.h 　
19029
 BNX2_RPM_SORT_USER3_ENABNX2_RPM_SORT_USER3_ENA (1L<<31) bnx2.h 　
19030
 BNX2_RPM_STAT_L2_FILTER_DISCARDBNX2_RPM_STAT_L2_FILTER_DISCARD 0x00001840 bnx2.h 　
19031
 BNX2_RPM_STAT_RULE_CHECKER_DISCBNX2_RPM_STAT_RULE_CHECKER_DISC 0x00001844 bnx2.h 　
19032
 BNX2_RPM_STAT_IFINFTQDISCARDSBNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848 bnx2.h 　
19033
 BNX2_RPM_STAT_IFINMBUFDISCARDBNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c bnx2.h 　
19034
 BNX2_RPM_STAT_RULE_CHECKER_P4_HBNX2_RPM_STAT_RULE_CHECKER_P4_H 0x00001850 bnx2.h 　
19035
 BNX2_RPM_STAT_AC0BNX2_RPM_STAT_AC0 0x00001880 bnx2.h 　
19036
 BNX2_RPM_STAT_AC1BNX2_RPM_STAT_AC1 0x00001884 bnx2.h 　
19037
 BNX2_RPM_STAT_AC2BNX2_RPM_STAT_AC2 0x00001888 bnx2.h 　
19038
 BNX2_RPM_STAT_AC3BNX2_RPM_STAT_AC3 0x0000188c bnx2.h 　
19039
 BNX2_RPM_STAT_AC4BNX2_RPM_STAT_AC4 0x00001890 bnx2.h 　
19040
 BNX2_RPM_RC_CNTL_0BNX2_RPM_RC_CNTL_0 0x00001900 bnx2.h 　
19041
 BNX2_RPM_RC_CNTL_0_OFFSETBNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0) bnx2.h 　
19042
 BNX2_RPM_RC_CNTL_0_CLASSBNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8) bnx2.h 　
19043
 BNX2_RPM_RC_CNTL_0_PRIORITYBNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11) bnx2.h 　
19044
 BNX2_RPM_RC_CNTL_0_P4BNX2_RPM_RC_CNTL_0_P4 (1L<<12) bnx2.h 　
19045
 BNX2_RPM_RC_CNTL_0_HDR_TYPEBNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13) bnx2.h 　
19046
 BNX2_RPM_RC_CNTL_0_HDR_TYPE_STABNX2_RPM_RC_CNTL_0_HDR_TYPE_STA (0L<<13) bnx2.h 　
19047
 BNX2_RPM_RC_CNTL_0_HDR_TYPE_IPBNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13) bnx2.h 　
19048
 BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCPBNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13) bnx2.h 　
19049
 BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDPBNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13) bnx2.h 　
19050
 BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATBNX2_RPM_RC_CNTL_0_HDR_TYPE_DAT (4L<<13) bnx2.h 　
19051
 BNX2_RPM_RC_CNTL_0_COMPBNX2_RPM_RC_CNTL_0_COMP (0x3L<<16) bnx2.h 　
19052
 BNX2_RPM_RC_CNTL_0_COMP_EQUALBNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16) bnx2.h 　
19053
 BNX2_RPM_RC_CNTL_0_COMP_NEQUALBNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16) bnx2.h 　
19054
 BNX2_RPM_RC_CNTL_0_COMP_GREATERBNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16) bnx2.h 　
19055
 BNX2_RPM_RC_CNTL_0_COMP_LESSBNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16) bnx2.h 　
19056
 BNX2_RPM_RC_CNTL_0_SBITBNX2_RPM_RC_CNTL_0_SBIT (1L<<19) bnx2.h 　
19057
 BNX2_RPM_RC_CNTL_0_CMDSELBNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20) bnx2.h 　
19058
 BNX2_RPM_RC_CNTL_0_MAPBNX2_RPM_RC_CNTL_0_MAP (1L<<24) bnx2.h 　
19059
 BNX2_RPM_RC_CNTL_0_DISCARDBNX2_RPM_RC_CNTL_0_DISCARD (1L<<25) bnx2.h 　
19060
 BNX2_RPM_RC_CNTL_0_MASKBNX2_RPM_RC_CNTL_0_MASK (1L<<26) bnx2.h 　
19061
 BNX2_RPM_RC_CNTL_0_P1BNX2_RPM_RC_CNTL_0_P1 (1L<<27) bnx2.h 　
19062
 BNX2_RPM_RC_CNTL_0_P2BNX2_RPM_RC_CNTL_0_P2 (1L<<28) bnx2.h 　
19063
 BNX2_RPM_RC_CNTL_0_P3BNX2_RPM_RC_CNTL_0_P3 (1L<<29) bnx2.h 　
19064
 BNX2_RPM_RC_CNTL_0_NBITBNX2_RPM_RC_CNTL_0_NBIT (1L<<30) bnx2.h 　
19065
 BNX2_RPM_RC_VALUE_MASK_0BNX2_RPM_RC_VALUE_MASK_0 0x00001904 bnx2.h 　
19066
 BNX2_RPM_RC_VALUE_MASK_0_VALUEBNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0) bnx2.h 　
19067
 BNX2_RPM_RC_VALUE_MASK_0_MASKBNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16) bnx2.h 　
19068
 BNX2_RPM_RC_CNTL_1BNX2_RPM_RC_CNTL_1 0x00001908 bnx2.h 　
19069
 BNX2_RPM_RC_CNTL_1_ABNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0) bnx2.h 　
19070
 BNX2_RPM_RC_CNTL_1_BBNX2_RPM_RC_CNTL_1_B (0xfffL<<19) bnx2.h 　
19071
 BNX2_RPM_RC_VALUE_MASK_1BNX2_RPM_RC_VALUE_MASK_1 0x0000190c bnx2.h 　
19072
 BNX2_RPM_RC_CNTL_2BNX2_RPM_RC_CNTL_2 0x00001910 bnx2.h 　
19073
 BNX2_RPM_RC_CNTL_2_ABNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0) bnx2.h 　
19074
 BNX2_RPM_RC_CNTL_2_BBNX2_RPM_RC_CNTL_2_B (0xfffL<<19) bnx2.h 　
19075
 BNX2_RPM_RC_VALUE_MASK_2BNX2_RPM_RC_VALUE_MASK_2 0x00001914 bnx2.h 　
19076
 BNX2_RPM_RC_CNTL_3BNX2_RPM_RC_CNTL_3 0x00001918 bnx2.h 　
19077
 BNX2_RPM_RC_CNTL_3_ABNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0) bnx2.h 　
19078
 BNX2_RPM_RC_CNTL_3_BBNX2_RPM_RC_CNTL_3_B (0xfffL<<19) bnx2.h 　
19079
 BNX2_RPM_RC_VALUE_MASK_3BNX2_RPM_RC_VALUE_MASK_3 0x0000191c bnx2.h 　
19080
 BNX2_RPM_RC_CNTL_4BNX2_RPM_RC_CNTL_4 0x00001920 bnx2.h 　
19081
 BNX2_RPM_RC_CNTL_4_ABNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0) bnx2.h 　
19082
 BNX2_RPM_RC_CNTL_4_BBNX2_RPM_RC_CNTL_4_B (0xfffL<<19) bnx2.h 　
19083
 BNX2_RPM_RC_VALUE_MASK_4BNX2_RPM_RC_VALUE_MASK_4 0x00001924 bnx2.h 　
19084
 BNX2_RPM_RC_CNTL_5BNX2_RPM_RC_CNTL_5 0x00001928 bnx2.h 　
19085
 BNX2_RPM_RC_CNTL_5_ABNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0) bnx2.h 　
19086
 BNX2_RPM_RC_CNTL_5_BBNX2_RPM_RC_CNTL_5_B (0xfffL<<19) bnx2.h 　
19087
 BNX2_RPM_RC_VALUE_MASK_5BNX2_RPM_RC_VALUE_MASK_5 0x0000192c bnx2.h 　
19088
 BNX2_RPM_RC_CNTL_6BNX2_RPM_RC_CNTL_6 0x00001930 bnx2.h 　
19089
 BNX2_RPM_RC_CNTL_6_ABNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0) bnx2.h 　
19090
 BNX2_RPM_RC_CNTL_6_BBNX2_RPM_RC_CNTL_6_B (0xfffL<<19) bnx2.h 　
19091
 BNX2_RPM_RC_VALUE_MASK_6BNX2_RPM_RC_VALUE_MASK_6 0x00001934 bnx2.h 　
19092
 BNX2_RPM_RC_CNTL_7BNX2_RPM_RC_CNTL_7 0x00001938 bnx2.h 　
19093
 BNX2_RPM_RC_CNTL_7_ABNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0) bnx2.h 　
19094
 BNX2_RPM_RC_CNTL_7_BBNX2_RPM_RC_CNTL_7_B (0xfffL<<19) bnx2.h 　
19095
 BNX2_RPM_RC_VALUE_MASK_7BNX2_RPM_RC_VALUE_MASK_7 0x0000193c bnx2.h 　
19096
 BNX2_RPM_RC_CNTL_8BNX2_RPM_RC_CNTL_8 0x00001940 bnx2.h 　
19097
 BNX2_RPM_RC_CNTL_8_ABNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0) bnx2.h 　
19098
 BNX2_RPM_RC_CNTL_8_BBNX2_RPM_RC_CNTL_8_B (0xfffL<<19) bnx2.h 　
19099
 BNX2_RPM_RC_VALUE_MASK_8BNX2_RPM_RC_VALUE_MASK_8 0x00001944 bnx2.h 　
19100
 BNX2_RPM_RC_CNTL_9BNX2_RPM_RC_CNTL_9 0x00001948 bnx2.h 　
19101
 BNX2_RPM_RC_CNTL_9_ABNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0) bnx2.h 　
19102
 BNX2_RPM_RC_CNTL_9_BBNX2_RPM_RC_CNTL_9_B (0xfffL<<19) bnx2.h 　
19103
 BNX2_RPM_RC_VALUE_MASK_9BNX2_RPM_RC_VALUE_MASK_9 0x0000194c bnx2.h 　
19104
 BNX2_RPM_RC_CNTL_10BNX2_RPM_RC_CNTL_10 0x00001950 bnx2.h 　
19105
 BNX2_RPM_RC_CNTL_10_ABNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0) bnx2.h 　
19106
 BNX2_RPM_RC_CNTL_10_BBNX2_RPM_RC_CNTL_10_B (0xfffL<<19) bnx2.h 　
19107
 BNX2_RPM_RC_VALUE_MASK_10BNX2_RPM_RC_VALUE_MASK_10 0x00001954 bnx2.h 　
19108
 BNX2_RPM_RC_CNTL_11BNX2_RPM_RC_CNTL_11 0x00001958 bnx2.h 　
19109
 BNX2_RPM_RC_CNTL_11_ABNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0) bnx2.h 　
19110
 BNX2_RPM_RC_CNTL_11_BBNX2_RPM_RC_CNTL_11_B (0xfffL<<19) bnx2.h 　
19111
 BNX2_RPM_RC_VALUE_MASK_11BNX2_RPM_RC_VALUE_MASK_11 0x0000195c bnx2.h 　
19112
 BNX2_RPM_RC_CNTL_12BNX2_RPM_RC_CNTL_12 0x00001960 bnx2.h 　
19113
 BNX2_RPM_RC_CNTL_12_ABNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0) bnx2.h 　
19114
 BNX2_RPM_RC_CNTL_12_BBNX2_RPM_RC_CNTL_12_B (0xfffL<<19) bnx2.h 　
19115
 BNX2_RPM_RC_VALUE_MASK_12BNX2_RPM_RC_VALUE_MASK_12 0x00001964 bnx2.h 　
19116
 BNX2_RPM_RC_CNTL_13BNX2_RPM_RC_CNTL_13 0x00001968 bnx2.h 　
19117
 BNX2_RPM_RC_CNTL_13_ABNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0) bnx2.h 　
19118
 BNX2_RPM_RC_CNTL_13_BBNX2_RPM_RC_CNTL_13_B (0xfffL<<19) bnx2.h 　
19119
 BNX2_RPM_RC_VALUE_MASK_13BNX2_RPM_RC_VALUE_MASK_13 0x0000196c bnx2.h 　
19120
 BNX2_RPM_RC_CNTL_14BNX2_RPM_RC_CNTL_14 0x00001970 bnx2.h 　
19121
 BNX2_RPM_RC_CNTL_14_ABNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0) bnx2.h 　
19122
 BNX2_RPM_RC_CNTL_14_BBNX2_RPM_RC_CNTL_14_B (0xfffL<<19) bnx2.h 　
19123
 BNX2_RPM_RC_VALUE_MASK_14BNX2_RPM_RC_VALUE_MASK_14 0x00001974 bnx2.h 　
19124
 BNX2_RPM_RC_CNTL_15BNX2_RPM_RC_CNTL_15 0x00001978 bnx2.h 　
19125
 BNX2_RPM_RC_CNTL_15_ABNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0) bnx2.h 　
19126
 BNX2_RPM_RC_CNTL_15_BBNX2_RPM_RC_CNTL_15_B (0xfffL<<19) bnx2.h 　
19127
 BNX2_RPM_RC_VALUE_MASK_15BNX2_RPM_RC_VALUE_MASK_15 0x0000197c bnx2.h 　
19128
 BNX2_RPM_RC_CONFIGBNX2_RPM_RC_CONFIG 0x00001980 bnx2.h 　
19129
 BNX2_RPM_RC_CONFIG_RULE_ENABLEBNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0) bnx2.h 　
19130
 BNX2_RPM_RC_CONFIG_DEF_CLASSBNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24) bnx2.h 　
19131
 BNX2_RPM_DEBUG0BNX2_RPM_DEBUG0 0x00001984 bnx2.h 　
19132
 BNX2_RPM_DEBUG0_FM_BCNTBNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0) bnx2.h 　
19133
 BNX2_RPM_DEBUG0_T_DATA_OFST_VLDBNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16) bnx2.h 　
19134
 BNX2_RPM_DEBUG0_T_UDP_OFST_VLDBNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17) bnx2.h 　
19135
 BNX2_RPM_DEBUG0_T_TCP_OFST_VLDBNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18) bnx2.h 　
19136
 BNX2_RPM_DEBUG0_T_IP_OFST_VLDBNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19) bnx2.h 　
19137
 BNX2_RPM_DEBUG0_IP_MORE_FRGMTBNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20) bnx2.h 　
19138
 BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDPBNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP (1L<<21) bnx2.h 　
19139
 BNX2_RPM_DEBUG0_LLC_SNAPBNX2_RPM_DEBUG0_LLC_SNAP (1L<<22) bnx2.h 　
19140
 BNX2_RPM_DEBUG0_FM_STARTEDBNX2_RPM_DEBUG0_FM_STARTED (1L<<23) bnx2.h 　
19141
 BNX2_RPM_DEBUG0_DONEBNX2_RPM_DEBUG0_DONE (1L<<24) bnx2.h 　
19142
 BNX2_RPM_DEBUG0_WAIT_4_DONEBNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25) bnx2.h 　
19143
 BNX2_RPM_DEBUG0_USE_TPBUF_CKSUMBNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26) bnx2.h 　
19144
 BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CBNX2_RPM_DEBUG0_RX_NO_PSD_HDR_C (1L<<27) bnx2.h 　
19145
 BNX2_RPM_DEBUG0_IGNORE_VLANBNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28) bnx2.h 　
19146
 BNX2_RPM_DEBUG0_RP_ENA_ACTIVEBNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31) bnx2.h 　
19147
 BNX2_RPM_DEBUG1BNX2_RPM_DEBUG1 0x00001988 bnx2.h 　
19148
 BNX2_RPM_DEBUG1_FSM_CUR_STBNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0) bnx2.h 　
19149
 BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLEBNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0) bnx2.h 　
19150
 BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPBNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP (1L<<0) bnx2.h 　
19151
 BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPBNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP (2L<<0) bnx2.h 　
19152
 BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPBNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP (4L<<0) bnx2.h 　
19153
 BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPBNX2_RPM_DEBUG1_FSM_CUR_ST_ETYP (8L<<0) bnx2.h 　
19154
 BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_SBNX2_RPM_DEBUG1_FSM_CUR_ST_IP_S (16L<<0) bnx2.h 　
19155
 BNX2_RPM_DEBUG1_FSM_CUR_ST_IPBNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0) bnx2.h 　
19156
 BNX2_RPM_DEBUG1_FSM_CUR_ST_TCPBNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0) bnx2.h 　
19157
 BNX2_RPM_DEBUG1_FSM_CUR_ST_UDPBNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0) bnx2.h 　
19158
 BNX2_RPM_DEBUG1_FSM_CUR_ST_AHBNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0) bnx2.h 　
19159
 BNX2_RPM_DEBUG1_FSM_CUR_ST_ESPBNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0) bnx2.h 　
19160
 BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_ (1024L<<0) bnx2.h 　
19161
 BNX2_RPM_DEBUG1_FSM_CUR_ST_DATABNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0) bnx2.h 　
19162
 BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_ (0x2000L<<0) bnx2.h 　
19163
 BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_ (0x4000L<<0) bnx2.h 　
19164
 BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCBNX2_RPM_DEBUG1_FSM_CUR_ST_LATC (0x8000L<<0) bnx2.h 　
19165
 BNX2_RPM_DEBUG1_HDR_BCNTBNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16) bnx2.h 　
19166
 BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_DBNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28) bnx2.h 　
19167
 BNX2_RPM_DEBUG1_VLAN_REMOVED_D2BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29) bnx2.h 　
19168
 BNX2_RPM_DEBUG1_VLAN_REMOVED_D1BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30) bnx2.h 　
19169
 BNX2_RPM_DEBUG1_EOF_0XTRA_WDBNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31) bnx2.h 　
19170
 BNX2_RPM_DEBUG2BNX2_RPM_DEBUG2 0x0000198c bnx2.h 　
19171
 BNX2_RPM_DEBUG2_CMD_HIT_VECBNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0) bnx2.h 　
19172
 BNX2_RPM_DEBUG2_IP_BCNTBNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16) bnx2.h 　
19173
 BNX2_RPM_DEBUG2_THIS_CMD_M4BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24) bnx2.h 　
19174
 BNX2_RPM_DEBUG2_THIS_CMD_M3BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25) bnx2.h 　
19175
 BNX2_RPM_DEBUG2_THIS_CMD_M2BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26) bnx2.h 　
19176
 BNX2_RPM_DEBUG2_THIS_CMD_M1BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27) bnx2.h 　
19177
 BNX2_RPM_DEBUG2_IPIPE_EMPTYBNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28) bnx2.h 　
19178
 BNX2_RPM_DEBUG2_FM_DISCARDBNX2_RPM_DEBUG2_FM_DISCARD (1L<<29) bnx2.h 　
19179
 BNX2_RPM_DEBUG2_LAST_RULE_IN_FMBNX2_RPM_DEBUG2_LAST_RULE_IN_FM (1L<<30) bnx2.h 　
19180
 BNX2_RPM_DEBUG2_LAST_RULE_IN_FMBNX2_RPM_DEBUG2_LAST_RULE_IN_FM (1L<<31) bnx2.h 　
19181
 BNX2_RPM_DEBUG3BNX2_RPM_DEBUG3 0x00001990 bnx2.h 　
19182
 BNX2_RPM_DEBUG3_AVAIL_MBUF_PTRBNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0) bnx2.h 　
19183
 BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REBNX2_RPM_DEBUG3_RDE_RLUPQ_WR_RE (1L<<9) bnx2.h 　
19184
 BNX2_RPM_DEBUG3_RDE_RBUF_WR_LASBNX2_RPM_DEBUG3_RDE_RBUF_WR_LAS (1L<<10) bnx2.h 　
19185
 BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQBNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ (1L<<11) bnx2.h 　
19186
 BNX2_RPM_DEBUG3_RDE_RBUF_FREE_RBNX2_RPM_DEBUG3_RDE_RBUF_FREE_R (1L<<12) bnx2.h 　
19187
 BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_ (1L<<13) bnx2.h 　
19188
 BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVBNX2_RPM_DEBUG3_DFSM_MBUF_NOTAV (1L<<14) bnx2.h 　
19189
 BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DRBNX2_RPM_DEBUG3_RBUF_RDE_SOF_DR (1L<<15) bnx2.h 　
19190
 BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRYBNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY (0xfL<<16) bnx2.h 　
19191
 BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALBNX2_RPM_DEBUG3_RDE_SRC_FIFO_AL (1L<<21) bnx2.h 　
19192
 BNX2_RPM_DEBUG3_DROP_NXT_VLDBNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22) bnx2.h 　
19193
 BNX2_RPM_DEBUG3_DROP_NXTBNX2_RPM_DEBUG3_DROP_NXT (1L<<23) bnx2.h 　
19194
 BNX2_RPM_DEBUG3_FTQ_FSMBNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24) bnx2.h 　
19195
 BNX2_RPM_DEBUG3_FTQ_FSM_IDLEBNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24) bnx2.h 　
19196
 BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACBNX2_RPM_DEBUG3_FTQ_FSM_WAIT_AC (0x1L<<24) bnx2.h 　
19197
 BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FRBNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FR (0x2L<<24) bnx2.h 　
19198
 BNX2_RPM_DEBUG3_MBWRITE_FSMBNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26) bnx2.h 　
19199
 BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIBNX2_RPM_DEBUG3_MBWRITE_FSM_WAI (0x0L<<26) bnx2.h 　
19200
 BNX2_RPM_DEBUG3_MBWRITE_FSM_GETBNX2_RPM_DEBUG3_MBWRITE_FSM_GET (0x1L<<26) bnx2.h 　
19201
 BNX2_RPM_DEBUG3_MBWRITE_FSM_DMABNX2_RPM_DEBUG3_MBWRITE_FSM_DMA (0x2L<<26) bnx2.h 　
19202
 BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIBNX2_RPM_DEBUG3_MBWRITE_FSM_WAI (0x3L<<26) bnx2.h 　
19203
 BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIBNX2_RPM_DEBUG3_MBWRITE_FSM_WAI (0x4L<<26) bnx2.h 　
19204
 BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIBNX2_RPM_DEBUG3_MBWRITE_FSM_WAI (0x5L<<26) bnx2.h 　
19205
 BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIBNX2_RPM_DEBUG3_MBWRITE_FSM_WAI (0x6L<<26) bnx2.h 　
19206
 BNX2_RPM_DEBUG3_MBWRITE_FSM_DONBNX2_RPM_DEBUG3_MBWRITE_FSM_DON (0x7L<<26) bnx2.h 　
19207
 BNX2_RPM_DEBUG3_MBFREE_FSMBNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29) bnx2.h 　
19208
 BNX2_RPM_DEBUG3_MBFREE_FSM_IDLEBNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29) bnx2.h 　
19209
 BNX2_RPM_DEBUG3_MBFREE_FSM_WAITBNX2_RPM_DEBUG3_MBFREE_FSM_WAIT (1L<<29) bnx2.h 　
19210
 BNX2_RPM_DEBUG3_MBALLOC_FSMBNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30) bnx2.h 　
19211
 BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_ (0x0L<<30) bnx2.h 　
19212
 BNX2_RPM_DEBUG3_MBALLOC_FSM_IVEBNX2_RPM_DEBUG3_MBALLOC_FSM_IVE (0x1L<<30) bnx2.h 　
19213
 BNX2_RPM_DEBUG3_CCODE_EOF_ERRORBNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31) bnx2.h 　
19214
 BNX2_RPM_DEBUG4BNX2_RPM_DEBUG4 0x00001994 bnx2.h 　
19215
 BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTBNX2_RPM_DEBUG4_DFSM_MBUF_CLUST (0x1ffffffL<<0) bnx2.h 　
19216
 BNX2_RPM_DEBUG4_DFIFO_CUR_CCODEBNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25) bnx2.h 　
19217
 BNX2_RPM_DEBUG4_MBWRITE_FSMBNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28) bnx2.h 　
19218
 BNX2_RPM_DEBUG4_DFIFO_EMPTYBNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31) bnx2.h 　
19219
 BNX2_RPM_DEBUG5BNX2_RPM_DEBUG5 0x00001998 bnx2.h 　
19220
 BNX2_RPM_DEBUG5_RDROP_WPTRBNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0) bnx2.h 　
19221
 BNX2_RPM_DEBUG5_RDROP_ACPI_RPTRBNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5) bnx2.h 　
19222
 BNX2_RPM_DEBUG5_RDROP_MC_RPTRBNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10) bnx2.h 　
19223
 BNX2_RPM_DEBUG5_RDROP_RC_RPTRBNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15) bnx2.h 　
19224
 BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTBNX2_RPM_DEBUG5_RDROP_ACPI_EMPT (1L<<20) bnx2.h 　
19225
 BNX2_RPM_DEBUG5_RDROP_MC_EMPTYBNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21) bnx2.h 　
19226
 BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_ (1L<<22) bnx2.h 　
19227
 BNX2_RPM_DEBUG5_HOLDREG_WOL_DROBNX2_RPM_DEBUG5_HOLDREG_WOL_DRO (1L<<23) bnx2.h 　
19228
 BNX2_RPM_DEBUG5_HOLDREG_DISCARDBNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24) bnx2.h 　
19229
 BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOBNX2_RPM_DEBUG5_HOLDREG_MBUF_NO (1L<<25) bnx2.h 　
19230
 BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTBNX2_RPM_DEBUG5_HOLDREG_MC_EMPT (1L<<26) bnx2.h 　
19231
 BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTBNX2_RPM_DEBUG5_HOLDREG_RC_EMPT (1L<<27) bnx2.h 　
19232
 BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTBNX2_RPM_DEBUG5_HOLDREG_FC_EMPT (1L<<28) bnx2.h 　
19233
 BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMBNX2_RPM_DEBUG5_HOLDREG_ACPI_EM (1L<<29) bnx2.h 　
19234
 BNX2_RPM_DEBUG5_HOLDREG_FULL_TBNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30) bnx2.h 　
19235
 BNX2_RPM_DEBUG5_HOLDREG_RDBNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31) bnx2.h 　
19236
 BNX2_RPM_DEBUG6BNX2_RPM_DEBUG6 0x0000199c bnx2.h 　
19237
 BNX2_RPM_DEBUG6_ACPI_VECBNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0) bnx2.h 　
19238
 BNX2_RPM_DEBUG6_VECBNX2_RPM_DEBUG6_VEC (0xffffL<<16) bnx2.h 　
19239
 BNX2_RPM_DEBUG7BNX2_RPM_DEBUG7 0x000019a0 bnx2.h 　
19240
 BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CBNX2_RPM_DEBUG7_RPM_DBG7_LAST_C (0xffffffffL<<0) bnx2.h 　
19241
 BNX2_RPM_DEBUG8BNX2_RPM_DEBUG8 0x000019a4 bnx2.h 　
19242
 BNX2_RPM_DEBUG8_PS_ACPI_FSMBNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0) bnx2.h 　
19243
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLBNX2_RPM_DEBUG8_PS_ACPI_FSM_IDL (0L<<0) bnx2.h 　
19244
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOFBNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF (1L<<0) bnx2.h 　
19245
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOFBNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF (2L<<0) bnx2.h 　
19246
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOFBNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF (3L<<0) bnx2.h 　
19247
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOFBNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF (4L<<0) bnx2.h 　
19248
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ (5L<<0) bnx2.h 　
19249
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ (6L<<0) bnx2.h 　
19250
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ (7L<<0) bnx2.h 　
19251
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ (8L<<0) bnx2.h 　
19252
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ (9L<<0) bnx2.h 　
19253
 BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIBNX2_RPM_DEBUG8_PS_ACPI_FSM_WAI (10L<<0) bnx2.h 　
19254
 BNX2_RPM_DEBUG8_COMPARE_AT_W0BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4) bnx2.h 　
19255
 BNX2_RPM_DEBUG8_COMPARE_AT_W3_DBNX2_RPM_DEBUG8_COMPARE_AT_W3_D (1L<<5) bnx2.h 　
19256
 BNX2_RPM_DEBUG8_COMPARE_AT_SOF_BNX2_RPM_DEBUG8_COMPARE_AT_SOF_ (1L<<6) bnx2.h 　
19257
 BNX2_RPM_DEBUG8_COMPARE_AT_SOF_BNX2_RPM_DEBUG8_COMPARE_AT_SOF_ (1L<<7) bnx2.h 　
19258
 BNX2_RPM_DEBUG8_COMPARE_AT_SOF_BNX2_RPM_DEBUG8_COMPARE_AT_SOF_ (1L<<8) bnx2.h 　
19259
 BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLD (1L<<9) bnx2.h 　
19260
 BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLD (1L<<10) bnx2.h 　
19261
 BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLBNX2_RPM_DEBUG8_NXT_EOF_W_12_VL (1L<<11) bnx2.h 　
19262
 BNX2_RPM_DEBUG8_EOF_DETBNX2_RPM_DEBUG8_EOF_DET (1L<<12) bnx2.h 　
19263
 BNX2_RPM_DEBUG8_SOF_DETBNX2_RPM_DEBUG8_SOF_DET (1L<<13) bnx2.h 　
19264
 BNX2_RPM_DEBUG8_WAIT_4_SOFBNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14) bnx2.h 　
19265
 BNX2_RPM_DEBUG8_ALL_DONEBNX2_RPM_DEBUG8_ALL_DONE (1L<<15) bnx2.h 　
19266
 BNX2_RPM_DEBUG8_THBUF_ADDRBNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16) bnx2.h 　
19267
 BNX2_RPM_DEBUG8_BYTE_CTRBNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24) bnx2.h 　
19268
 BNX2_RPM_DEBUG9BNX2_RPM_DEBUG9 0x000019a8 bnx2.h 　
19269
 BNX2_RPM_DEBUG9_OUTFIFO_COUNTBNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0) bnx2.h 　
19270
 BNX2_RPM_DEBUG9_RDE_ACPI_RDYBNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3) bnx2.h 　
19271
 BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CTBNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4) bnx2.h 　
19272
 BNX2_RPM_DEBUG9_OUTFIFO_OVERRUNBNX2_RPM_DEBUG9_OUTFIFO_OVERRUN (1L<<28) bnx2.h 　
19273
 BNX2_RPM_DEBUG9_INFIFO_OVERRUN_BNX2_RPM_DEBUG9_INFIFO_OVERRUN_ (1L<<29) bnx2.h 　
19274
 BNX2_RPM_DEBUG9_ACPI_MATCH_INTBNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30) bnx2.h 　
19275
 BNX2_RPM_DEBUG9_ACPI_ENABLE_SYNBNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31) bnx2.h 　
19276
 BNX2_RPM_ACPI_DBG_BUF_W00BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0 bnx2.h 　
19277
 BNX2_RPM_ACPI_DBG_BUF_W01BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4 bnx2.h 　
19278
 BNX2_RPM_ACPI_DBG_BUF_W02BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8 bnx2.h 　
19279
 BNX2_RPM_ACPI_DBG_BUF_W03BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc bnx2.h 　
19280
 BNX2_RPM_ACPI_DBG_BUF_W10BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0 bnx2.h 　
19281
 BNX2_RPM_ACPI_DBG_BUF_W11BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4 bnx2.h 　
19282
 BNX2_RPM_ACPI_DBG_BUF_W12BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8 bnx2.h 　
19283
 BNX2_RPM_ACPI_DBG_BUF_W13BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc bnx2.h 　
19284
 BNX2_RPM_ACPI_DBG_BUF_W20BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0 bnx2.h 　
19285
 BNX2_RPM_ACPI_DBG_BUF_W21BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4 bnx2.h 　
19286
 BNX2_RPM_ACPI_DBG_BUF_W22BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8 bnx2.h 　
19287
 BNX2_RPM_ACPI_DBG_BUF_W23BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec bnx2.h 　
19288
 BNX2_RPM_ACPI_DBG_BUF_W30BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0 bnx2.h 　
19289
 BNX2_RPM_ACPI_DBG_BUF_W31BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4 bnx2.h 　
19290
 BNX2_RPM_ACPI_DBG_BUF_W32BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8 bnx2.h 　
19291
 BNX2_RPM_ACPI_DBG_BUF_W33BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc bnx2.h 　
19292
 BNX2_RBUF_COMMANDBNX2_RBUF_COMMAND 0x00200000 bnx2.h 　
19293
 BNX2_RBUF_COMMAND_ENABLEDBNX2_RBUF_COMMAND_ENABLED (1L<<0) bnx2.h 　
19294
 BNX2_RBUF_COMMAND_FREE_INITBNX2_RBUF_COMMAND_FREE_INIT (1L<<1) bnx2.h 　
19295
 BNX2_RBUF_COMMAND_RAM_INITBNX2_RBUF_COMMAND_RAM_INIT (1L<<2) bnx2.h 　
19296
 BNX2_RBUF_COMMAND_OVER_FREEBNX2_RBUF_COMMAND_OVER_FREE (1L<<4) bnx2.h 　
19297
 BNX2_RBUF_COMMAND_ALLOC_REQBNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5) bnx2.h 　
19298
 BNX2_RBUF_STATUS1BNX2_RBUF_STATUS1 0x00200004 bnx2.h 　
19299
 BNX2_RBUF_STATUS1_FREE_COUNTBNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0) bnx2.h 　
19300
 BNX2_RBUF_STATUS2BNX2_RBUF_STATUS2 0x00200008 bnx2.h 　
19301
 BNX2_RBUF_STATUS2_FREE_TAILBNX2_RBUF_STATUS2_FREE_TAIL (0x3ffL<<0) bnx2.h 　
19302
 BNX2_RBUF_STATUS2_FREE_HEADBNX2_RBUF_STATUS2_FREE_HEAD (0x3ffL<<16) bnx2.h 　
19303
 BNX2_RBUF_CONFIGBNX2_RBUF_CONFIG 0x0020000c bnx2.h 　
19304
 BNX2_RBUF_CONFIG_XOFF_TRIPBNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0) bnx2.h 　
19305
 BNX2_RBUF_CONFIG_XON_TRIPBNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16) bnx2.h 　
19306
 BNX2_RBUF_FW_BUF_ALLOCBNX2_RBUF_FW_BUF_ALLOC 0x00200010 bnx2.h 　
19307
 BNX2_RBUF_FW_BUF_ALLOC_VALUEBNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7) bnx2.h 　
19308
 BNX2_RBUF_FW_BUF_FREEBNX2_RBUF_FW_BUF_FREE 0x00200014 bnx2.h 　
19309
 BNX2_RBUF_FW_BUF_FREE_COUNTBNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0) bnx2.h 　
19310
 BNX2_RBUF_FW_BUF_FREE_TAILBNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7) bnx2.h 　
19311
 BNX2_RBUF_FW_BUF_FREE_HEADBNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16) bnx2.h 　
19312
 BNX2_RBUF_FW_BUF_SELBNX2_RBUF_FW_BUF_SEL 0x00200018 bnx2.h 　
19313
 BNX2_RBUF_FW_BUF_SEL_COUNTBNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0) bnx2.h 　
19314
 BNX2_RBUF_FW_BUF_SEL_TAILBNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7) bnx2.h 　
19315
 BNX2_RBUF_FW_BUF_SEL_HEADBNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16) bnx2.h 　
19316
 BNX2_RBUF_CONFIG2BNX2_RBUF_CONFIG2 0x0020001c bnx2.h 　
19317
 BNX2_RBUF_CONFIG2_MAC_DROP_TRIPBNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0) bnx2.h 　
19318
 BNX2_RBUF_CONFIG2_MAC_KEEP_TRIPBNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16) bnx2.h 　
19319
 BNX2_RBUF_CONFIG3BNX2_RBUF_CONFIG3 0x00200020 bnx2.h 　
19320
 BNX2_RBUF_CONFIG3_CU_DROP_TRIPBNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0) bnx2.h 　
19321
 BNX2_RBUF_CONFIG3_CU_KEEP_TRIPBNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16) bnx2.h 　
19322
 BNX2_RBUF_PKT_DATABNX2_RBUF_PKT_DATA 0x00208000 bnx2.h 　
19323
 BNX2_RBUF_CLIST_DATABNX2_RBUF_CLIST_DATA 0x00210000 bnx2.h 　
19324
 BNX2_RBUF_BUF_DATABNX2_RBUF_BUF_DATA 0x00220000 bnx2.h 　
19325
 BNX2_RV2P_COMMANDBNX2_RV2P_COMMAND 0x00002800 bnx2.h 　
19326
 BNX2_RV2P_COMMAND_ENABLEDBNX2_RV2P_COMMAND_ENABLED (1L<<0) bnx2.h 　
19327
 BNX2_RV2P_COMMAND_PROC1_INTRPTBNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1) bnx2.h 　
19328
 BNX2_RV2P_COMMAND_PROC2_INTRPTBNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2) bnx2.h 　
19329
 BNX2_RV2P_COMMAND_ABORT0BNX2_RV2P_COMMAND_ABORT0 (1L<<4) bnx2.h 　
19330
 BNX2_RV2P_COMMAND_ABORT1BNX2_RV2P_COMMAND_ABORT1 (1L<<5) bnx2.h 　
19331
 BNX2_RV2P_COMMAND_ABORT2BNX2_RV2P_COMMAND_ABORT2 (1L<<6) bnx2.h 　
19332
 BNX2_RV2P_COMMAND_ABORT3BNX2_RV2P_COMMAND_ABORT3 (1L<<7) bnx2.h 　
19333
 BNX2_RV2P_COMMAND_ABORT4BNX2_RV2P_COMMAND_ABORT4 (1L<<8) bnx2.h 　
19334
 BNX2_RV2P_COMMAND_ABORT5BNX2_RV2P_COMMAND_ABORT5 (1L<<9) bnx2.h 　
19335
 BNX2_RV2P_COMMAND_PROC1_RESETBNX2_RV2P_COMMAND_PROC1_RESET (1L<<16) bnx2.h 　
19336
 BNX2_RV2P_COMMAND_PROC2_RESETBNX2_RV2P_COMMAND_PROC2_RESET (1L<<17) bnx2.h 　
19337
 BNX2_RV2P_COMMAND_CTXIF_RESETBNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18) bnx2.h 　
19338
 BNX2_RV2P_STATUSBNX2_RV2P_STATUS 0x00002804 bnx2.h 　
19339
 BNX2_RV2P_STATUS_ALWAYS_0BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0) bnx2.h 　
19340
 BNX2_RV2P_STATUS_RV2P_GEN_STAT0BNX2_RV2P_STATUS_RV2P_GEN_STAT0 (1L<<8) bnx2.h 　
19341
 BNX2_RV2P_STATUS_RV2P_GEN_STAT1BNX2_RV2P_STATUS_RV2P_GEN_STAT1 (1L<<9) bnx2.h 　
19342
 BNX2_RV2P_STATUS_RV2P_GEN_STAT2BNX2_RV2P_STATUS_RV2P_GEN_STAT2 (1L<<10) bnx2.h 　
19343
 BNX2_RV2P_STATUS_RV2P_GEN_STAT3BNX2_RV2P_STATUS_RV2P_GEN_STAT3 (1L<<11) bnx2.h 　
19344
 BNX2_RV2P_STATUS_RV2P_GEN_STAT4BNX2_RV2P_STATUS_RV2P_GEN_STAT4 (1L<<12) bnx2.h 　
19345
 BNX2_RV2P_STATUS_RV2P_GEN_STAT5BNX2_RV2P_STATUS_RV2P_GEN_STAT5 (1L<<13) bnx2.h 　
19346
 BNX2_RV2P_CONFIGBNX2_RV2P_CONFIG 0x00002808 bnx2.h 　
19347
 BNX2_RV2P_CONFIG_STALL_PROC1BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0) bnx2.h 　
19348
 BNX2_RV2P_CONFIG_STALL_PROC2BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1) bnx2.h 　
19349
 BNX2_RV2P_CONFIG_PROC1_STALL_ONBNX2_RV2P_CONFIG_PROC1_STALL_ON (1L<<8) bnx2.h 　
19350
 BNX2_RV2P_CONFIG_PROC1_STALL_ONBNX2_RV2P_CONFIG_PROC1_STALL_ON (1L<<9) bnx2.h 　
19351
 BNX2_RV2P_CONFIG_PROC1_STALL_ONBNX2_RV2P_CONFIG_PROC1_STALL_ON (1L<<10) bnx2.h 　
19352
 BNX2_RV2P_CONFIG_PROC1_STALL_ONBNX2_RV2P_CONFIG_PROC1_STALL_ON (1L<<11) bnx2.h 　
19353
 BNX2_RV2P_CONFIG_PROC1_STALL_ONBNX2_RV2P_CONFIG_PROC1_STALL_ON (1L<<12) bnx2.h 　
19354
 BNX2_RV2P_CONFIG_PROC1_STALL_ONBNX2_RV2P_CONFIG_PROC1_STALL_ON (1L<<13) bnx2.h 　
19355
 BNX2_RV2P_CONFIG_PROC2_STALL_ONBNX2_RV2P_CONFIG_PROC2_STALL_ON (1L<<16) bnx2.h 　
19356
 BNX2_RV2P_CONFIG_PROC2_STALL_ONBNX2_RV2P_CONFIG_PROC2_STALL_ON (1L<<17) bnx2.h 　
19357
 BNX2_RV2P_CONFIG_PROC2_STALL_ONBNX2_RV2P_CONFIG_PROC2_STALL_ON (1L<<18) bnx2.h 　
19358
 BNX2_RV2P_CONFIG_PROC2_STALL_ONBNX2_RV2P_CONFIG_PROC2_STALL_ON (1L<<19) bnx2.h 　
19359
 BNX2_RV2P_CONFIG_PROC2_STALL_ONBNX2_RV2P_CONFIG_PROC2_STALL_ON (1L<<20) bnx2.h 　
19360
 BNX2_RV2P_CONFIG_PROC2_STALL_ONBNX2_RV2P_CONFIG_PROC2_STALL_ON (1L<<21) bnx2.h 　
19361
 BNX2_RV2P_CONFIG_PAGE_SIZEBNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24) bnx2.h 　
19362
 BNX2_RV2P_CONFIG_PAGE_SIZE_256BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24) bnx2.h 　
19363
 BNX2_RV2P_CONFIG_PAGE_SIZE_512BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24) bnx2.h 　
19364
 BNX2_RV2P_CONFIG_PAGE_SIZE_1KBNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24) bnx2.h 　
19365
 BNX2_RV2P_CONFIG_PAGE_SIZE_2KBNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24) bnx2.h 　
19366
 BNX2_RV2P_CONFIG_PAGE_SIZE_4KBNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24) bnx2.h 　
19367
 BNX2_RV2P_CONFIG_PAGE_SIZE_8KBNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24) bnx2.h 　
19368
 BNX2_RV2P_CONFIG_PAGE_SIZE_16KBNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24) bnx2.h 　
19369
 BNX2_RV2P_CONFIG_PAGE_SIZE_32KBNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24) bnx2.h 　
19370
 BNX2_RV2P_CONFIG_PAGE_SIZE_64KBNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24) bnx2.h 　
19371
 BNX2_RV2P_CONFIG_PAGE_SIZE_128KBNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24) bnx2.h 　
19372
 BNX2_RV2P_CONFIG_PAGE_SIZE_256KBNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24) bnx2.h 　
19373
 BNX2_RV2P_CONFIG_PAGE_SIZE_512KBNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24) bnx2.h 　
19374
 BNX2_RV2P_CONFIG_PAGE_SIZE_1MBNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24) bnx2.h 　
19375
 BNX2_RV2P_GEN_BFR_ADDR_0BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810 bnx2.h 　
19376
 BNX2_RV2P_GEN_BFR_ADDR_0_VALUEBNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16) bnx2.h 　
19377
 BNX2_RV2P_GEN_BFR_ADDR_1BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814 bnx2.h 　
19378
 BNX2_RV2P_GEN_BFR_ADDR_1_VALUEBNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16) bnx2.h 　
19379
 BNX2_RV2P_GEN_BFR_ADDR_2BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818 bnx2.h 　
19380
 BNX2_RV2P_GEN_BFR_ADDR_2_VALUEBNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16) bnx2.h 　
19381
 BNX2_RV2P_GEN_BFR_ADDR_3BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c bnx2.h 　
19382
 BNX2_RV2P_GEN_BFR_ADDR_3_VALUEBNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16) bnx2.h 　
19383
 BNX2_RV2P_INSTR_HIGHBNX2_RV2P_INSTR_HIGH 0x00002830 bnx2.h 　
19384
 BNX2_RV2P_INSTR_HIGH_HIGHBNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0) bnx2.h 　
19385
 BNX2_RV2P_INSTR_LOWBNX2_RV2P_INSTR_LOW 0x00002834 bnx2.h 　
19386
 BNX2_RV2P_PROC1_ADDR_CMDBNX2_RV2P_PROC1_ADDR_CMD 0x00002838 bnx2.h 　
19387
 BNX2_RV2P_PROC1_ADDR_CMD_ADDBNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0) bnx2.h 　
19388
 BNX2_RV2P_PROC1_ADDR_CMD_RDWRBNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31) bnx2.h 　
19389
 BNX2_RV2P_PROC2_ADDR_CMDBNX2_RV2P_PROC2_ADDR_CMD 0x0000283c bnx2.h 　
19390
 BNX2_RV2P_PROC2_ADDR_CMD_ADDBNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0) bnx2.h 　
19391
 BNX2_RV2P_PROC2_ADDR_CMD_RDWRBNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31) bnx2.h 　
19392
 BNX2_RV2P_PROC1_GRC_DEBUGBNX2_RV2P_PROC1_GRC_DEBUG 0x00002840 bnx2.h 　
19393
 BNX2_RV2P_PROC2_GRC_DEBUGBNX2_RV2P_PROC2_GRC_DEBUG 0x00002844 bnx2.h 　
19394
 BNX2_RV2P_GRC_PROC_DEBUGBNX2_RV2P_GRC_PROC_DEBUG 0x00002848 bnx2.h 　
19395
 BNX2_RV2P_DEBUG_VECT_PEEKBNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c bnx2.h 　
19396
 BNX2_RV2P_DEBUG_VECT_PEEK_1_VALBNX2_RV2P_DEBUG_VECT_PEEK_1_VAL (0x7ffL<<0) bnx2.h 　
19397
 BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEBNX2_RV2P_DEBUG_VECT_PEEK_1_PEE (1L<<11) bnx2.h 　
19398
 BNX2_RV2P_DEBUG_VECT_PEEK_1_SELBNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) bnx2.h 　
19399
 BNX2_RV2P_DEBUG_VECT_PEEK_2_VALBNX2_RV2P_DEBUG_VECT_PEEK_2_VAL (0x7ffL<<16) bnx2.h 　
19400
 BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEBNX2_RV2P_DEBUG_VECT_PEEK_2_PEE (1L<<27) bnx2.h 　
19401
 BNX2_RV2P_DEBUG_VECT_PEEK_2_SELBNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) bnx2.h 　
19402
 BNX2_RV2P_PFTQ_DATABNX2_RV2P_PFTQ_DATA 0x00002b40 bnx2.h 　
19403
 BNX2_RV2P_PFTQ_CMDBNX2_RV2P_PFTQ_CMD 0x00002b78 bnx2.h 　
19404
 BNX2_RV2P_PFTQ_CMD_OFFSETBNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
19405
 BNX2_RV2P_PFTQ_CMD_WR_TOPBNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
19406
 BNX2_RV2P_PFTQ_CMD_WR_TOP_0BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
19407
 BNX2_RV2P_PFTQ_CMD_WR_TOP_1BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
19408
 BNX2_RV2P_PFTQ_CMD_SFT_RESETBNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
19409
 BNX2_RV2P_PFTQ_CMD_RD_DATABNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
19410
 BNX2_RV2P_PFTQ_CMD_ADD_INTERVENBNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
19411
 BNX2_RV2P_PFTQ_CMD_ADD_DATABNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
19412
 BNX2_RV2P_PFTQ_CMD_INTERVENE_CLBNX2_RV2P_PFTQ_CMD_INTERVENE_CL (1L<<29) bnx2.h 　
19413
 BNX2_RV2P_PFTQ_CMD_POPBNX2_RV2P_PFTQ_CMD_POP (1L<<30) bnx2.h 　
19414
 BNX2_RV2P_PFTQ_CMD_BUSYBNX2_RV2P_PFTQ_CMD_BUSY (1L<<31) bnx2.h 　
19415
 BNX2_RV2P_PFTQ_CTLBNX2_RV2P_PFTQ_CTL 0x00002b7c bnx2.h 　
19416
 BNX2_RV2P_PFTQ_CTL_INTERVENEBNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
19417
 BNX2_RV2P_PFTQ_CTL_OVERFLOWBNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
19418
 BNX2_RV2P_PFTQ_CTL_FORCE_INTERVBNX2_RV2P_PFTQ_CTL_FORCE_INTERV (1L<<2) bnx2.h 　
19419
 BNX2_RV2P_PFTQ_CTL_MAX_DEPTHBNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
19420
 BNX2_RV2P_PFTQ_CTL_CUR_DEPTHBNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
19421
 BNX2_RV2P_TFTQ_DATABNX2_RV2P_TFTQ_DATA 0x00002b80 bnx2.h 　
19422
 BNX2_RV2P_TFTQ_CMDBNX2_RV2P_TFTQ_CMD 0x00002bb8 bnx2.h 　
19423
 BNX2_RV2P_TFTQ_CMD_OFFSETBNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
19424
 BNX2_RV2P_TFTQ_CMD_WR_TOPBNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
19425
 BNX2_RV2P_TFTQ_CMD_WR_TOP_0BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
19426
 BNX2_RV2P_TFTQ_CMD_WR_TOP_1BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
19427
 BNX2_RV2P_TFTQ_CMD_SFT_RESETBNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
19428
 BNX2_RV2P_TFTQ_CMD_RD_DATABNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
19429
 BNX2_RV2P_TFTQ_CMD_ADD_INTERVENBNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
19430
 BNX2_RV2P_TFTQ_CMD_ADD_DATABNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
19431
 BNX2_RV2P_TFTQ_CMD_INTERVENE_CLBNX2_RV2P_TFTQ_CMD_INTERVENE_CL (1L<<29) bnx2.h 　
19432
 BNX2_RV2P_TFTQ_CMD_POPBNX2_RV2P_TFTQ_CMD_POP (1L<<30) bnx2.h 　
19433
 BNX2_RV2P_TFTQ_CMD_BUSYBNX2_RV2P_TFTQ_CMD_BUSY (1L<<31) bnx2.h 　
19434
 BNX2_RV2P_TFTQ_CTLBNX2_RV2P_TFTQ_CTL 0x00002bbc bnx2.h 　
19435
 BNX2_RV2P_TFTQ_CTL_INTERVENEBNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
19436
 BNX2_RV2P_TFTQ_CTL_OVERFLOWBNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
19437
 BNX2_RV2P_TFTQ_CTL_FORCE_INTERVBNX2_RV2P_TFTQ_CTL_FORCE_INTERV (1L<<2) bnx2.h 　
19438
 BNX2_RV2P_TFTQ_CTL_MAX_DEPTHBNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
19439
 BNX2_RV2P_TFTQ_CTL_CUR_DEPTHBNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
19440
 BNX2_RV2P_MFTQ_DATABNX2_RV2P_MFTQ_DATA 0x00002bc0 bnx2.h 　
19441
 BNX2_RV2P_MFTQ_CMDBNX2_RV2P_MFTQ_CMD 0x00002bf8 bnx2.h 　
19442
 BNX2_RV2P_MFTQ_CMD_OFFSETBNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
19443
 BNX2_RV2P_MFTQ_CMD_WR_TOPBNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
19444
 BNX2_RV2P_MFTQ_CMD_WR_TOP_0BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
19445
 BNX2_RV2P_MFTQ_CMD_WR_TOP_1BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
19446
 BNX2_RV2P_MFTQ_CMD_SFT_RESETBNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
19447
 BNX2_RV2P_MFTQ_CMD_RD_DATABNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
19448
 BNX2_RV2P_MFTQ_CMD_ADD_INTERVENBNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
19449
 BNX2_RV2P_MFTQ_CMD_ADD_DATABNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
19450
 BNX2_RV2P_MFTQ_CMD_INTERVENE_CLBNX2_RV2P_MFTQ_CMD_INTERVENE_CL (1L<<29) bnx2.h 　
19451
 BNX2_RV2P_MFTQ_CMD_POPBNX2_RV2P_MFTQ_CMD_POP (1L<<30) bnx2.h 　
19452
 BNX2_RV2P_MFTQ_CMD_BUSYBNX2_RV2P_MFTQ_CMD_BUSY (1L<<31) bnx2.h 　
19453
 BNX2_RV2P_MFTQ_CTLBNX2_RV2P_MFTQ_CTL 0x00002bfc bnx2.h 　
19454
 BNX2_RV2P_MFTQ_CTL_INTERVENEBNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
19455
 BNX2_RV2P_MFTQ_CTL_OVERFLOWBNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
19456
 BNX2_RV2P_MFTQ_CTL_FORCE_INTERVBNX2_RV2P_MFTQ_CTL_FORCE_INTERV (1L<<2) bnx2.h 　
19457
 BNX2_RV2P_MFTQ_CTL_MAX_DEPTHBNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
19458
 BNX2_RV2P_MFTQ_CTL_CUR_DEPTHBNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
19459
 BNX2_MQ_COMMANDBNX2_MQ_COMMAND 0x00003c00 bnx2.h 　
19460
 BNX2_MQ_COMMAND_ENABLEDBNX2_MQ_COMMAND_ENABLED (1L<<0) bnx2.h 　
19461
 BNX2_MQ_COMMAND_OVERFLOWBNX2_MQ_COMMAND_OVERFLOW (1L<<4) bnx2.h 　
19462
 BNX2_MQ_COMMAND_WR_ERRORBNX2_MQ_COMMAND_WR_ERROR (1L<<5) bnx2.h 　
19463
 BNX2_MQ_COMMAND_RD_ERRORBNX2_MQ_COMMAND_RD_ERROR (1L<<6) bnx2.h 　
19464
 BNX2_MQ_STATUSBNX2_MQ_STATUS 0x00003c04 bnx2.h 　
19465
 BNX2_MQ_STATUS_CTX_ACCESS_STATBNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16) bnx2.h 　
19466
 BNX2_MQ_STATUS_CTX_ACCESS64_STABNX2_MQ_STATUS_CTX_ACCESS64_STA (1L<<17) bnx2.h 　
19467
 BNX2_MQ_STATUS_PCI_STALL_STATBNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18) bnx2.h 　
19468
 BNX2_MQ_CONFIGBNX2_MQ_CONFIG 0x00003c08 bnx2.h 　
19469
 BNX2_MQ_CONFIG_TX_HIGH_PRIBNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0) bnx2.h 　
19470
 BNX2_MQ_CONFIG_HALT_DISBNX2_MQ_CONFIG_HALT_DIS (1L<<1) bnx2.h 　
19471
 BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZEBNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4) bnx2.h 　
19472
 BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZEBNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0L<<4) bnx2.h 　
19473
 BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZEBNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (1L<<4) bnx2.h 　
19474
 BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZEBNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (2L<<4) bnx2.h 　
19475
 BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZEBNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (3L<<4) bnx2.h 　
19476
 BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZEBNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (4L<<4) bnx2.h 　
19477
 BNX2_MQ_CONFIG_MAX_DEPTHBNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8) bnx2.h 　
19478
 BNX2_MQ_CONFIG_CUR_DEPTHBNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20) bnx2.h 　
19479
 BNX2_MQ_ENQUEUE1BNX2_MQ_ENQUEUE1 0x00003c0c bnx2.h 　
19480
 BNX2_MQ_ENQUEUE1_OFFSETBNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2) bnx2.h 　
19481
 BNX2_MQ_ENQUEUE1_CIDBNX2_MQ_ENQUEUE1_CID (0x3fffL<<8) bnx2.h 　
19482
 BNX2_MQ_ENQUEUE1_BYTE_MASKBNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24) bnx2.h 　
19483
 BNX2_MQ_ENQUEUE1_KNL_MODEBNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28) bnx2.h 　
19484
 BNX2_MQ_ENQUEUE2BNX2_MQ_ENQUEUE2 0x00003c10 bnx2.h 　
19485
 BNX2_MQ_BAD_WR_ADDRBNX2_MQ_BAD_WR_ADDR 0x00003c14 bnx2.h 　
19486
 BNX2_MQ_BAD_RD_ADDRBNX2_MQ_BAD_RD_ADDR 0x00003c18 bnx2.h 　
19487
 BNX2_MQ_KNL_BYP_WIND_STARTBNX2_MQ_KNL_BYP_WIND_START 0x00003c1c bnx2.h 　
19488
 BNX2_MQ_KNL_BYP_WIND_START_VALUBNX2_MQ_KNL_BYP_WIND_START_VALU (0xfffffL<<12) bnx2.h 　
19489
 BNX2_MQ_KNL_WIND_ENDBNX2_MQ_KNL_WIND_END 0x00003c20 bnx2.h 　
19490
 BNX2_MQ_KNL_WIND_END_VALUEBNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8) bnx2.h 　
19491
 BNX2_MQ_KNL_WRITE_MASK1BNX2_MQ_KNL_WRITE_MASK1 0x00003c24 bnx2.h 　
19492
 BNX2_MQ_KNL_TX_MASK1BNX2_MQ_KNL_TX_MASK1 0x00003c28 bnx2.h 　
19493
 BNX2_MQ_KNL_CMD_MASK1BNX2_MQ_KNL_CMD_MASK1 0x00003c2c bnx2.h 　
19494
 BNX2_MQ_KNL_COND_ENQUEUE_MASK1BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30 bnx2.h 　
19495
 BNX2_MQ_KNL_RX_V2P_MASK1BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34 bnx2.h 　
19496
 BNX2_MQ_KNL_WRITE_MASK2BNX2_MQ_KNL_WRITE_MASK2 0x00003c38 bnx2.h 　
19497
 BNX2_MQ_KNL_TX_MASK2BNX2_MQ_KNL_TX_MASK2 0x00003c3c bnx2.h 　
19498
 BNX2_MQ_KNL_CMD_MASK2BNX2_MQ_KNL_CMD_MASK2 0x00003c40 bnx2.h 　
19499
 BNX2_MQ_KNL_COND_ENQUEUE_MASK2BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44 bnx2.h 　
19500
 BNX2_MQ_KNL_RX_V2P_MASK2BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48 bnx2.h 　
19501
 BNX2_MQ_KNL_BYP_WRITE_MASK1BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c bnx2.h 　
19502
 BNX2_MQ_KNL_BYP_TX_MASK1BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50 bnx2.h 　
19503
 BNX2_MQ_KNL_BYP_CMD_MASK1BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54 bnx2.h 　
19504
 BNX2_MQ_KNL_BYP_COND_ENQUEUE_MABNX2_MQ_KNL_BYP_COND_ENQUEUE_MA 0x00003c58 bnx2.h 　
19505
 BNX2_MQ_KNL_BYP_RX_V2P_MASK1BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c bnx2.h 　
19506
 BNX2_MQ_KNL_BYP_WRITE_MASK2BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60 bnx2.h 　
19507
 BNX2_MQ_KNL_BYP_TX_MASK2BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64 bnx2.h 　
19508
 BNX2_MQ_KNL_BYP_CMD_MASK2BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68 bnx2.h 　
19509
 BNX2_MQ_KNL_BYP_COND_ENQUEUE_MABNX2_MQ_KNL_BYP_COND_ENQUEUE_MA 0x00003c6c bnx2.h 　
19510
 BNX2_MQ_KNL_BYP_RX_V2P_MASK2BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70 bnx2.h 　
19511
 BNX2_MQ_MEM_WR_ADDRBNX2_MQ_MEM_WR_ADDR 0x00003c74 bnx2.h 　
19512
 BNX2_MQ_MEM_WR_ADDR_VALUEBNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0) bnx2.h 　
19513
 BNX2_MQ_MEM_WR_DATA0BNX2_MQ_MEM_WR_DATA0 0x00003c78 bnx2.h 　
19514
 BNX2_MQ_MEM_WR_DATA0_VALUEBNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0) bnx2.h 　
19515
 BNX2_MQ_MEM_WR_DATA1BNX2_MQ_MEM_WR_DATA1 0x00003c7c bnx2.h 　
19516
 BNX2_MQ_MEM_WR_DATA1_VALUEBNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0) bnx2.h 　
19517
 BNX2_MQ_MEM_WR_DATA2BNX2_MQ_MEM_WR_DATA2 0x00003c80 bnx2.h 　
19518
 BNX2_MQ_MEM_WR_DATA2_VALUEBNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0) bnx2.h 　
19519
 BNX2_MQ_MEM_RD_ADDRBNX2_MQ_MEM_RD_ADDR 0x00003c84 bnx2.h 　
19520
 BNX2_MQ_MEM_RD_ADDR_VALUEBNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0) bnx2.h 　
19521
 BNX2_MQ_MEM_RD_DATA0BNX2_MQ_MEM_RD_DATA0 0x00003c88 bnx2.h 　
19522
 BNX2_MQ_MEM_RD_DATA0_VALUEBNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0) bnx2.h 　
19523
 BNX2_MQ_MEM_RD_DATA1BNX2_MQ_MEM_RD_DATA1 0x00003c8c bnx2.h 　
19524
 BNX2_MQ_MEM_RD_DATA1_VALUEBNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0) bnx2.h 　
19525
 BNX2_MQ_MEM_RD_DATA2BNX2_MQ_MEM_RD_DATA2 0x00003c90 bnx2.h 　
19526
 BNX2_MQ_MEM_RD_DATA2_VALUEBNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0) bnx2.h 　
19527
 BNX2_TBDR_COMMANDBNX2_TBDR_COMMAND 0x00005000 bnx2.h 　
19528
 BNX2_TBDR_COMMAND_ENABLEBNX2_TBDR_COMMAND_ENABLE (1L<<0) bnx2.h 　
19529
 BNX2_TBDR_COMMAND_SOFT_RSTBNX2_TBDR_COMMAND_SOFT_RST (1L<<1) bnx2.h 　
19530
 BNX2_TBDR_COMMAND_MSTR_ABORTBNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4) bnx2.h 　
19531
 BNX2_TBDR_STATUSBNX2_TBDR_STATUS 0x00005004 bnx2.h 　
19532
 BNX2_TBDR_STATUS_DMA_WAITBNX2_TBDR_STATUS_DMA_WAIT (1L<<0) bnx2.h 　
19533
 BNX2_TBDR_STATUS_FTQ_WAITBNX2_TBDR_STATUS_FTQ_WAIT (1L<<1) bnx2.h 　
19534
 BNX2_TBDR_STATUS_FIFO_OVERFLOWBNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2) bnx2.h 　
19535
 BNX2_TBDR_STATUS_FIFO_UNDERFLOWBNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3) bnx2.h 　
19536
 BNX2_TBDR_STATUS_SEARCHMISS_ERRBNX2_TBDR_STATUS_SEARCHMISS_ERR (1L<<4) bnx2.h 　
19537
 BNX2_TBDR_STATUS_FTQ_ENTRY_CNTBNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5) bnx2.h 　
19538
 BNX2_TBDR_STATUS_BURST_CNTBNX2_TBDR_STATUS_BURST_CNT (1L<<6) bnx2.h 　
19539
 BNX2_TBDR_CONFIGBNX2_TBDR_CONFIG 0x00005008 bnx2.h 　
19540
 BNX2_TBDR_CONFIG_MAX_BDSBNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0) bnx2.h 　
19541
 BNX2_TBDR_CONFIG_SWAP_MODEBNX2_TBDR_CONFIG_SWAP_MODE (1L<<8) bnx2.h 　
19542
 BNX2_TBDR_CONFIG_PRIORITYBNX2_TBDR_CONFIG_PRIORITY (1L<<9) bnx2.h 　
19543
 BNX2_TBDR_CONFIG_CACHE_NEXT_PAGBNX2_TBDR_CONFIG_CACHE_NEXT_PAG (1L<<10) bnx2.h 　
19544
 BNX2_TBDR_CONFIG_PAGE_SIZEBNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24) bnx2.h 　
19545
 BNX2_TBDR_CONFIG_PAGE_SIZE_256BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24) bnx2.h 　
19546
 BNX2_TBDR_CONFIG_PAGE_SIZE_512BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24) bnx2.h 　
19547
 BNX2_TBDR_CONFIG_PAGE_SIZE_1KBNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24) bnx2.h 　
19548
 BNX2_TBDR_CONFIG_PAGE_SIZE_2KBNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24) bnx2.h 　
19549
 BNX2_TBDR_CONFIG_PAGE_SIZE_4KBNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24) bnx2.h 　
19550
 BNX2_TBDR_CONFIG_PAGE_SIZE_8KBNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24) bnx2.h 　
19551
 BNX2_TBDR_CONFIG_PAGE_SIZE_16KBNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24) bnx2.h 　
19552
 BNX2_TBDR_CONFIG_PAGE_SIZE_32KBNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24) bnx2.h 　
19553
 BNX2_TBDR_CONFIG_PAGE_SIZE_64KBNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24) bnx2.h 　
19554
 BNX2_TBDR_CONFIG_PAGE_SIZE_128KBNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24) bnx2.h 　
19555
 BNX2_TBDR_CONFIG_PAGE_SIZE_256KBNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24) bnx2.h 　
19556
 BNX2_TBDR_CONFIG_PAGE_SIZE_512KBNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24) bnx2.h 　
19557
 BNX2_TBDR_CONFIG_PAGE_SIZE_1MBNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24) bnx2.h 　
19558
 BNX2_TBDR_DEBUG_VECT_PEEKBNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c bnx2.h 　
19559
 BNX2_TBDR_DEBUG_VECT_PEEK_1_VALBNX2_TBDR_DEBUG_VECT_PEEK_1_VAL (0x7ffL<<0) bnx2.h 　
19560
 BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEBNX2_TBDR_DEBUG_VECT_PEEK_1_PEE (1L<<11) bnx2.h 　
19561
 BNX2_TBDR_DEBUG_VECT_PEEK_1_SELBNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) bnx2.h 　
19562
 BNX2_TBDR_DEBUG_VECT_PEEK_2_VALBNX2_TBDR_DEBUG_VECT_PEEK_2_VAL (0x7ffL<<16) bnx2.h 　
19563
 BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEBNX2_TBDR_DEBUG_VECT_PEEK_2_PEE (1L<<27) bnx2.h 　
19564
 BNX2_TBDR_DEBUG_VECT_PEEK_2_SELBNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) bnx2.h 　
19565
 BNX2_TBDR_FTQ_DATABNX2_TBDR_FTQ_DATA 0x000053c0 bnx2.h 　
19566
 BNX2_TBDR_FTQ_CMDBNX2_TBDR_FTQ_CMD 0x000053f8 bnx2.h 　
19567
 BNX2_TBDR_FTQ_CMD_OFFSETBNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
19568
 BNX2_TBDR_FTQ_CMD_WR_TOPBNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
19569
 BNX2_TBDR_FTQ_CMD_WR_TOP_0BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
19570
 BNX2_TBDR_FTQ_CMD_WR_TOP_1BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
19571
 BNX2_TBDR_FTQ_CMD_SFT_RESETBNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
19572
 BNX2_TBDR_FTQ_CMD_RD_DATABNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
19573
 BNX2_TBDR_FTQ_CMD_ADD_INTERVENBNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
19574
 BNX2_TBDR_FTQ_CMD_ADD_DATABNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
19575
 BNX2_TBDR_FTQ_CMD_INTERVENE_CLRBNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29) bnx2.h 　
19576
 BNX2_TBDR_FTQ_CMD_POPBNX2_TBDR_FTQ_CMD_POP (1L<<30) bnx2.h 　
19577
 BNX2_TBDR_FTQ_CMD_BUSYBNX2_TBDR_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
19578
 BNX2_TBDR_FTQ_CTLBNX2_TBDR_FTQ_CTL 0x000053fc bnx2.h 　
19579
 BNX2_TBDR_FTQ_CTL_INTERVENEBNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
19580
 BNX2_TBDR_FTQ_CTL_OVERFLOWBNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
19581
 BNX2_TBDR_FTQ_CTL_FORCE_INTERVEBNX2_TBDR_FTQ_CTL_FORCE_INTERVE (1L<<2) bnx2.h 　
19582
 BNX2_TBDR_FTQ_CTL_MAX_DEPTHBNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
19583
 BNX2_TBDR_FTQ_CTL_CUR_DEPTHBNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
19584
 BNX2_TDMA_COMMANDBNX2_TDMA_COMMAND 0x00005c00 bnx2.h 　
19585
 BNX2_TDMA_COMMAND_ENABLEDBNX2_TDMA_COMMAND_ENABLED (1L<<0) bnx2.h 　
19586
 BNX2_TDMA_COMMAND_MASTER_ABORTBNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4) bnx2.h 　
19587
 BNX2_TDMA_COMMAND_BAD_L2_LENGTHBNX2_TDMA_COMMAND_BAD_L2_LENGTH (1L<<7) bnx2.h 　
19588
 BNX2_TDMA_STATUSBNX2_TDMA_STATUS 0x00005c04 bnx2.h 　
19589
 BNX2_TDMA_STATUS_DMA_WAITBNX2_TDMA_STATUS_DMA_WAIT (1L<<0) bnx2.h 　
19590
 BNX2_TDMA_STATUS_PAYLOAD_WAITBNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1) bnx2.h 　
19591
 BNX2_TDMA_STATUS_PATCH_FTQ_WAITBNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2) bnx2.h 　
19592
 BNX2_TDMA_STATUS_LOCK_WAITBNX2_TDMA_STATUS_LOCK_WAIT (1L<<3) bnx2.h 　
19593
 BNX2_TDMA_STATUS_FTQ_ENTRY_CNTBNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16) bnx2.h 　
19594
 BNX2_TDMA_STATUS_BURST_CNTBNX2_TDMA_STATUS_BURST_CNT (1L<<17) bnx2.h 　
19595
 BNX2_TDMA_CONFIGBNX2_TDMA_CONFIG 0x00005c08 bnx2.h 　
19596
 BNX2_TDMA_CONFIG_ONE_DMABNX2_TDMA_CONFIG_ONE_DMA (1L<<0) bnx2.h 　
19597
 BNX2_TDMA_CONFIG_ONE_RECORDBNX2_TDMA_CONFIG_ONE_RECORD (1L<<1) bnx2.h 　
19598
 BNX2_TDMA_CONFIG_LIMIT_SZBNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4) bnx2.h 　
19599
 BNX2_TDMA_CONFIG_LIMIT_SZ_64BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4) bnx2.h 　
19600
 BNX2_TDMA_CONFIG_LIMIT_SZ_128BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4) bnx2.h 　
19601
 BNX2_TDMA_CONFIG_LIMIT_SZ_256BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4) bnx2.h 　
19602
 BNX2_TDMA_CONFIG_LIMIT_SZ_512BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4) bnx2.h 　
19603
 BNX2_TDMA_CONFIG_LINE_SZBNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8) bnx2.h 　
19604
 BNX2_TDMA_CONFIG_LINE_SZ_64BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8) bnx2.h 　
19605
 BNX2_TDMA_CONFIG_LINE_SZ_128BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8) bnx2.h 　
19606
 BNX2_TDMA_CONFIG_LINE_SZ_256BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8) bnx2.h 　
19607
 BNX2_TDMA_CONFIG_LINE_SZ_512BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8) bnx2.h 　
19608
 BNX2_TDMA_CONFIG_ALIGN_ENABNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15) bnx2.h 　
19609
 BNX2_TDMA_CONFIG_CHK_L2_BDBNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16) bnx2.h 　
19610
 BNX2_TDMA_CONFIG_FIFO_CMPBNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20) bnx2.h 　
19611
 BNX2_TDMA_PAYLOAD_PRODBNX2_TDMA_PAYLOAD_PROD 0x00005c0c bnx2.h 　
19612
 BNX2_TDMA_PAYLOAD_PROD_VALUEBNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3) bnx2.h 　
19613
 BNX2_TDMA_DBG_WATCHDOGBNX2_TDMA_DBG_WATCHDOG 0x00005c10 bnx2.h 　
19614
 BNX2_TDMA_DBG_TRIGGERBNX2_TDMA_DBG_TRIGGER 0x00005c14 bnx2.h 　
19615
 BNX2_TDMA_DMAD_FSMBNX2_TDMA_DMAD_FSM 0x00005c80 bnx2.h 　
19616
 BNX2_TDMA_DMAD_FSM_BD_INVLDBNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0) bnx2.h 　
19617
 BNX2_TDMA_DMAD_FSM_PUSHBNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4) bnx2.h 　
19618
 BNX2_TDMA_DMAD_FSM_ARB_TBDCBNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8) bnx2.h 　
19619
 BNX2_TDMA_DMAD_FSM_ARB_CTXBNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12) bnx2.h 　
19620
 BNX2_TDMA_DMAD_FSM_DR_INTFBNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16) bnx2.h 　
19621
 BNX2_TDMA_DMAD_FSM_DMADBNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20) bnx2.h 　
19622
 BNX2_TDMA_DMAD_FSM_BDBNX2_TDMA_DMAD_FSM_BD (0xfL<<24) bnx2.h 　
19623
 BNX2_TDMA_DMAD_STATUSBNX2_TDMA_DMAD_STATUS 0x00005c84 bnx2.h 　
19624
 BNX2_TDMA_DMAD_STATUS_RHOLD_PUSBNX2_TDMA_DMAD_STATUS_RHOLD_PUS (0x3L<<0) bnx2.h 　
19625
 BNX2_TDMA_DMAD_STATUS_RHOLD_DMABNX2_TDMA_DMAD_STATUS_RHOLD_DMA (0x3L<<4) bnx2.h 　
19626
 BNX2_TDMA_DMAD_STATUS_RHOLD_BD_BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ (0x3L<<8) bnx2.h 　
19627
 BNX2_TDMA_DMAD_STATUS_IFTQ_ENUMBNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12) bnx2.h 　
19628
 BNX2_TDMA_DR_INTF_FSMBNX2_TDMA_DR_INTF_FSM 0x00005c88 bnx2.h 　
19629
 BNX2_TDMA_DR_INTF_FSM_L2_COMPBNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0) bnx2.h 　
19630
 BNX2_TDMA_DR_INTF_FSM_TPATQBNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4) bnx2.h 　
19631
 BNX2_TDMA_DR_INTF_FSM_TPBUFBNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8) bnx2.h 　
19632
 BNX2_TDMA_DR_INTF_FSM_DR_BUFBNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12) bnx2.h 　
19633
 BNX2_TDMA_DR_INTF_FSM_DMADBNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16) bnx2.h 　
19634
 BNX2_TDMA_DR_INTF_STATUSBNX2_TDMA_DR_INTF_STATUS 0x00005c8c bnx2.h 　
19635
 BNX2_TDMA_DR_INTF_STATUS_HOLE_PBNX2_TDMA_DR_INTF_STATUS_HOLE_P (0x7L<<0) bnx2.h 　
19636
 BNX2_TDMA_DR_INTF_STATUS_DATA_ABNX2_TDMA_DR_INTF_STATUS_DATA_A (0x3L<<4) bnx2.h 　
19637
 BNX2_TDMA_DR_INTF_STATUS_SHIFT_BNX2_TDMA_DR_INTF_STATUS_SHIFT_ (0x7L<<8) bnx2.h 　
19638
 BNX2_TDMA_DR_INTF_STATUS_NXT_PNBNX2_TDMA_DR_INTF_STATUS_NXT_PN (0xfL<<12) bnx2.h 　
19639
 BNX2_TDMA_DR_INTF_STATUS_BYTE_CBNX2_TDMA_DR_INTF_STATUS_BYTE_C (0x7L<<16) bnx2.h 　
19640
 BNX2_TDMA_FTQ_DATABNX2_TDMA_FTQ_DATA 0x00005fc0 bnx2.h 　
19641
 BNX2_TDMA_FTQ_CMDBNX2_TDMA_FTQ_CMD 0x00005ff8 bnx2.h 　
19642
 BNX2_TDMA_FTQ_CMD_OFFSETBNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
19643
 BNX2_TDMA_FTQ_CMD_WR_TOPBNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
19644
 BNX2_TDMA_FTQ_CMD_WR_TOP_0BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
19645
 BNX2_TDMA_FTQ_CMD_WR_TOP_1BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
19646
 BNX2_TDMA_FTQ_CMD_SFT_RESETBNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
19647
 BNX2_TDMA_FTQ_CMD_RD_DATABNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
19648
 BNX2_TDMA_FTQ_CMD_ADD_INTERVENBNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
19649
 BNX2_TDMA_FTQ_CMD_ADD_DATABNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
19650
 BNX2_TDMA_FTQ_CMD_INTERVENE_CLRBNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29) bnx2.h 　
19651
 BNX2_TDMA_FTQ_CMD_POPBNX2_TDMA_FTQ_CMD_POP (1L<<30) bnx2.h 　
19652
 BNX2_TDMA_FTQ_CMD_BUSYBNX2_TDMA_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
19653
 BNX2_TDMA_FTQ_CTLBNX2_TDMA_FTQ_CTL 0x00005ffc bnx2.h 　
19654
 BNX2_TDMA_FTQ_CTL_INTERVENEBNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
19655
 BNX2_TDMA_FTQ_CTL_OVERFLOWBNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
19656
 BNX2_TDMA_FTQ_CTL_FORCE_INTERVEBNX2_TDMA_FTQ_CTL_FORCE_INTERVE (1L<<2) bnx2.h 　
19657
 BNX2_TDMA_FTQ_CTL_MAX_DEPTHBNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
19658
 BNX2_TDMA_FTQ_CTL_CUR_DEPTHBNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
19659
 BNX2_HC_COMMANDBNX2_HC_COMMAND 0x00006800 bnx2.h 　
19660
 BNX2_HC_COMMAND_ENABLEBNX2_HC_COMMAND_ENABLE (1L<<0) bnx2.h 　
19661
 BNX2_HC_COMMAND_SKIP_ABORTBNX2_HC_COMMAND_SKIP_ABORT (1L<<4) bnx2.h 　
19662
 BNX2_HC_COMMAND_COAL_NOWBNX2_HC_COMMAND_COAL_NOW (1L<<16) bnx2.h 　
19663
 BNX2_HC_COMMAND_COAL_NOW_WO_INTBNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17) bnx2.h 　
19664
 BNX2_HC_COMMAND_STATS_NOWBNX2_HC_COMMAND_STATS_NOW (1L<<18) bnx2.h 　
19665
 BNX2_HC_COMMAND_FORCE_INTBNX2_HC_COMMAND_FORCE_INT (0x3L<<19) bnx2.h 　
19666
 BNX2_HC_COMMAND_FORCE_INT_NULLBNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19) bnx2.h 　
19667
 BNX2_HC_COMMAND_FORCE_INT_HIGHBNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19) bnx2.h 　
19668
 BNX2_HC_COMMAND_FORCE_INT_LOWBNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19) bnx2.h 　
19669
 BNX2_HC_COMMAND_FORCE_INT_FREEBNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19) bnx2.h 　
19670
 BNX2_HC_COMMAND_CLR_STAT_NOWBNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21) bnx2.h 　
19671
 BNX2_HC_STATUSBNX2_HC_STATUS 0x00006804 bnx2.h 　
19672
 BNX2_HC_STATUS_MASTER_ABORTBNX2_HC_STATUS_MASTER_ABORT (1L<<0) bnx2.h 　
19673
 BNX2_HC_STATUS_PARITY_ERROR_STABNX2_HC_STATUS_PARITY_ERROR_STA (1L<<1) bnx2.h 　
19674
 BNX2_HC_STATUS_PCI_CLK_CNT_STATBNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16) bnx2.h 　
19675
 BNX2_HC_STATUS_CORE_CLK_CNT_STABNX2_HC_STATUS_CORE_CLK_CNT_STA (1L<<17) bnx2.h 　
19676
 BNX2_HC_STATUS_NUM_STATUS_BLOCKBNX2_HC_STATUS_NUM_STATUS_BLOCK (1L<<18) bnx2.h 　
19677
 BNX2_HC_STATUS_NUM_INT_GEN_STATBNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19) bnx2.h 　
19678
 BNX2_HC_STATUS_NUM_INT_MBOX_WR_BNX2_HC_STATUS_NUM_INT_MBOX_WR_ (1L<<20) bnx2.h 　
19679
 BNX2_HC_STATUS_CORE_CLKS_TO_HW_BNX2_HC_STATUS_CORE_CLKS_TO_HW_ (1L<<23) bnx2.h 　
19680
 BNX2_HC_STATUS_CORE_CLKS_TO_SW_BNX2_HC_STATUS_CORE_CLKS_TO_SW_ (1L<<24) bnx2.h 　
19681
 BNX2_HC_STATUS_CORE_CLKS_DURINGBNX2_HC_STATUS_CORE_CLKS_DURING (1L<<25) bnx2.h 　
19682
 BNX2_HC_CONFIGBNX2_HC_CONFIG 0x00006808 bnx2.h 　
19683
 BNX2_HC_CONFIG_COLLECT_STATSBNX2_HC_CONFIG_COLLECT_STATS (1L<<0) bnx2.h 　
19684
 BNX2_HC_CONFIG_RX_TMR_MODEBNX2_HC_CONFIG_RX_TMR_MODE (1L<<1) bnx2.h 　
19685
 BNX2_HC_CONFIG_TX_TMR_MODEBNX2_HC_CONFIG_TX_TMR_MODE (1L<<2) bnx2.h 　
19686
 BNX2_HC_CONFIG_COM_TMR_MODEBNX2_HC_CONFIG_COM_TMR_MODE (1L<<3) bnx2.h 　
19687
 BNX2_HC_CONFIG_CMD_TMR_MODEBNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4) bnx2.h 　
19688
 BNX2_HC_CONFIG_STATISTIC_PRIORIBNX2_HC_CONFIG_STATISTIC_PRIORI (1L<<5) bnx2.h 　
19689
 BNX2_HC_CONFIG_STATUS_PRIORITYBNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6) bnx2.h 　
19690
 BNX2_HC_CONFIG_STAT_MEM_ADDRBNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8) bnx2.h 　
19691
 BNX2_HC_ATTN_BITS_ENABLEBNX2_HC_ATTN_BITS_ENABLE 0x0000680c bnx2.h 　
19692
 BNX2_HC_STATUS_ADDR_LBNX2_HC_STATUS_ADDR_L 0x00006810 bnx2.h 　
19693
 BNX2_HC_STATUS_ADDR_HBNX2_HC_STATUS_ADDR_H 0x00006814 bnx2.h 　
19694
 BNX2_HC_STATISTICS_ADDR_LBNX2_HC_STATISTICS_ADDR_L 0x00006818 bnx2.h 　
19695
 BNX2_HC_STATISTICS_ADDR_HBNX2_HC_STATISTICS_ADDR_H 0x0000681c bnx2.h 　
19696
 BNX2_HC_TX_QUICK_CONS_TRIPBNX2_HC_TX_QUICK_CONS_TRIP 0x00006820 bnx2.h 　
19697
 BNX2_HC_TX_QUICK_CONS_TRIP_VALUBNX2_HC_TX_QUICK_CONS_TRIP_VALU (0xffL<<0) bnx2.h 　
19698
 BNX2_HC_TX_QUICK_CONS_TRIP_INTBNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16) bnx2.h 　
19699
 BNX2_HC_COMP_PROD_TRIPBNX2_HC_COMP_PROD_TRIP 0x00006824 bnx2.h 　
19700
 BNX2_HC_COMP_PROD_TRIP_VALUEBNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0) bnx2.h 　
19701
 BNX2_HC_COMP_PROD_TRIP_INTBNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16) bnx2.h 　
19702
 BNX2_HC_RX_QUICK_CONS_TRIPBNX2_HC_RX_QUICK_CONS_TRIP 0x00006828 bnx2.h 　
19703
 BNX2_HC_RX_QUICK_CONS_TRIP_VALUBNX2_HC_RX_QUICK_CONS_TRIP_VALU (0xffL<<0) bnx2.h 　
19704
 BNX2_HC_RX_QUICK_CONS_TRIP_INTBNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16) bnx2.h 　
19705
 BNX2_HC_RX_TICKSBNX2_HC_RX_TICKS 0x0000682c bnx2.h 　
19706
 BNX2_HC_RX_TICKS_VALUEBNX2_HC_RX_TICKS_VALUE (0x3ffL<<0) bnx2.h 　
19707
 BNX2_HC_RX_TICKS_INTBNX2_HC_RX_TICKS_INT (0x3ffL<<16) bnx2.h 　
19708
 BNX2_HC_TX_TICKSBNX2_HC_TX_TICKS 0x00006830 bnx2.h 　
19709
 BNX2_HC_TX_TICKS_VALUEBNX2_HC_TX_TICKS_VALUE (0x3ffL<<0) bnx2.h 　
19710
 BNX2_HC_TX_TICKS_INTBNX2_HC_TX_TICKS_INT (0x3ffL<<16) bnx2.h 　
19711
 BNX2_HC_COM_TICKSBNX2_HC_COM_TICKS 0x00006834 bnx2.h 　
19712
 BNX2_HC_COM_TICKS_VALUEBNX2_HC_COM_TICKS_VALUE (0x3ffL<<0) bnx2.h 　
19713
 BNX2_HC_COM_TICKS_INTBNX2_HC_COM_TICKS_INT (0x3ffL<<16) bnx2.h 　
19714
 BNX2_HC_CMD_TICKSBNX2_HC_CMD_TICKS 0x00006838 bnx2.h 　
19715
 BNX2_HC_CMD_TICKS_VALUEBNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0) bnx2.h 　
19716
 BNX2_HC_CMD_TICKS_INTBNX2_HC_CMD_TICKS_INT (0x3ffL<<16) bnx2.h 　
19717
 BNX2_HC_PERIODIC_TICKSBNX2_HC_PERIODIC_TICKS 0x0000683c bnx2.h 　
19718
 BNX2_HC_PERIODIC_TICKS_HC_PERIOBNX2_HC_PERIODIC_TICKS_HC_PERIO (0xffffL<<0) bnx2.h 　
19719
 BNX2_HC_STAT_COLLECT_TICKSBNX2_HC_STAT_COLLECT_TICKS 0x00006840 bnx2.h 　
19720
 BNX2_HC_STAT_COLLECT_TICKS_HC_SBNX2_HC_STAT_COLLECT_TICKS_HC_S (0xffL<<4) bnx2.h 　
19721
 BNX2_HC_STATS_TICKSBNX2_HC_STATS_TICKS 0x00006844 bnx2.h 　
19722
 BNX2_HC_STATS_TICKS_HC_STAT_TICBNX2_HC_STATS_TICKS_HC_STAT_TIC (0xffffL<<8) bnx2.h 　
19723
 BNX2_HC_STAT_MEM_DATABNX2_HC_STAT_MEM_DATA 0x0000684c bnx2.h 　
19724
 BNX2_HC_STAT_GEN_SEL_0BNX2_HC_STAT_GEN_SEL_0 0x00006850 bnx2.h 　
19725
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (0x7fL<<0) bnx2.h 　
19726
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (0L<<0) bnx2.h 　
19727
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (1L<<0) bnx2.h 　
19728
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (2L<<0) bnx2.h 　
19729
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (3L<<0) bnx2.h 　
19730
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (4L<<0) bnx2.h 　
19731
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (5L<<0) bnx2.h 　
19732
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (6L<<0) bnx2.h 　
19733
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (7L<<0) bnx2.h 　
19734
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (8L<<0) bnx2.h 　
19735
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (9L<<0) bnx2.h 　
19736
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (10L<<0) bnx2.h 　
19737
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (11L<<0) bnx2.h 　
19738
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (12L<<0) bnx2.h 　
19739
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (13L<<0) bnx2.h 　
19740
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (14L<<0) bnx2.h 　
19741
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (15L<<0) bnx2.h 　
19742
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (16L<<0) bnx2.h 　
19743
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (17L<<0) bnx2.h 　
19744
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (18L<<0) bnx2.h 　
19745
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (19L<<0) bnx2.h 　
19746
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (20L<<0) bnx2.h 　
19747
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (21L<<0) bnx2.h 　
19748
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (22L<<0) bnx2.h 　
19749
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (23L<<0) bnx2.h 　
19750
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (24L<<0) bnx2.h 　
19751
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (25L<<0) bnx2.h 　
19752
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (26L<<0) bnx2.h 　
19753
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (27L<<0) bnx2.h 　
19754
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (28L<<0) bnx2.h 　
19755
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (29L<<0) bnx2.h 　
19756
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (30L<<0) bnx2.h 　
19757
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (31L<<0) bnx2.h 　
19758
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (32L<<0) bnx2.h 　
19759
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (33L<<0) bnx2.h 　
19760
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (34L<<0) bnx2.h 　
19761
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (35L<<0) bnx2.h 　
19762
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (36L<<0) bnx2.h 　
19763
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (37L<<0) bnx2.h 　
19764
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (38L<<0) bnx2.h 　
19765
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (39L<<0) bnx2.h 　
19766
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (40L<<0) bnx2.h 　
19767
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (41L<<0) bnx2.h 　
19768
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (42L<<0) bnx2.h 　
19769
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (43L<<0) bnx2.h 　
19770
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (44L<<0) bnx2.h 　
19771
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (45L<<0) bnx2.h 　
19772
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (46L<<0) bnx2.h 　
19773
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (47L<<0) bnx2.h 　
19774
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (48L<<0) bnx2.h 　
19775
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (49L<<0) bnx2.h 　
19776
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (50L<<0) bnx2.h 　
19777
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (51L<<0) bnx2.h 　
19778
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (52L<<0) bnx2.h 　
19779
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (53L<<0) bnx2.h 　
19780
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (54L<<0) bnx2.h 　
19781
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (55L<<0) bnx2.h 　
19782
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (56L<<0) bnx2.h 　
19783
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (59L<<0) bnx2.h 　
19784
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (60L<<0) bnx2.h 　
19785
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (61L<<0) bnx2.h 　
19786
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (62L<<0) bnx2.h 　
19787
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (63L<<0) bnx2.h 　
19788
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (64L<<0) bnx2.h 　
19789
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (65L<<0) bnx2.h 　
19790
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (66L<<0) bnx2.h 　
19791
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (67L<<0) bnx2.h 　
19792
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (68L<<0) bnx2.h 　
19793
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (69L<<0) bnx2.h 　
19794
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (70L<<0) bnx2.h 　
19795
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (71L<<0) bnx2.h 　
19796
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (72L<<0) bnx2.h 　
19797
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (73L<<0) bnx2.h 　
19798
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (74L<<0) bnx2.h 　
19799
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (75L<<0) bnx2.h 　
19800
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (76L<<0) bnx2.h 　
19801
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (77L<<0) bnx2.h 　
19802
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (78L<<0) bnx2.h 　
19803
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (79L<<0) bnx2.h 　
19804
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (80L<<0) bnx2.h 　
19805
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (81L<<0) bnx2.h 　
19806
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (82L<<0) bnx2.h 　
19807
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (83L<<0) bnx2.h 　
19808
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (84L<<0) bnx2.h 　
19809
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (85L<<0) bnx2.h 　
19810
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (86L<<0) bnx2.h 　
19811
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (87L<<0) bnx2.h 　
19812
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (88L<<0) bnx2.h 　
19813
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (89L<<0) bnx2.h 　
19814
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (90L<<0) bnx2.h 　
19815
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (91L<<0) bnx2.h 　
19816
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (92L<<0) bnx2.h 　
19817
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (93L<<0) bnx2.h 　
19818
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (94L<<0) bnx2.h 　
19819
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (95L<<0) bnx2.h 　
19820
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (96L<<0) bnx2.h 　
19821
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (97L<<0) bnx2.h 　
19822
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (98L<<0) bnx2.h 　
19823
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (99L<<0) bnx2.h 　
19824
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (100L<<0) bnx2.h 　
19825
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (101L<<0) bnx2.h 　
19826
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (102L<<0) bnx2.h 　
19827
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (103L<<0) bnx2.h 　
19828
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (104L<<0) bnx2.h 　
19829
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (105L<<0) bnx2.h 　
19830
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (106L<<0) bnx2.h 　
19831
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (107L<<0) bnx2.h 　
19832
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (108L<<0) bnx2.h 　
19833
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (109L<<0) bnx2.h 　
19834
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (110L<<0) bnx2.h 　
19835
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (111L<<0) bnx2.h 　
19836
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (112L<<0) bnx2.h 　
19837
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (113L<<0) bnx2.h 　
19838
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (114L<<0) bnx2.h 　
19839
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (115L<<0) bnx2.h 　
19840
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (116L<<0) bnx2.h 　
19841
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (117L<<0) bnx2.h 　
19842
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (118L<<0) bnx2.h 　
19843
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (119L<<0) bnx2.h 　
19844
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (120L<<0) bnx2.h 　
19845
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (121L<<0) bnx2.h 　
19846
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (122L<<0) bnx2.h 　
19847
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (127L<<0) bnx2.h 　
19848
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (0x7fL<<8) bnx2.h 　
19849
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (0x7fL<<16) bnx2.h 　
19850
 BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_ (0x7fL<<24) bnx2.h 　
19851
 BNX2_HC_STAT_GEN_SEL_1BNX2_HC_STAT_GEN_SEL_1 0x00006854 bnx2.h 　
19852
 BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_ (0x7fL<<0) bnx2.h 　
19853
 BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_ (0x7fL<<8) bnx2.h 　
19854
 BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_ (0x7fL<<16) bnx2.h 　
19855
 BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_ (0x7fL<<24) bnx2.h 　
19856
 BNX2_HC_STAT_GEN_SEL_2BNX2_HC_STAT_GEN_SEL_2 0x00006858 bnx2.h 　
19857
 BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_ (0x7fL<<0) bnx2.h 　
19858
 BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_ (0x7fL<<8) bnx2.h 　
19859
 BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_ (0x7fL<<16) bnx2.h 　
19860
 BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_ (0x7fL<<24) bnx2.h 　
19861
 BNX2_HC_STAT_GEN_SEL_3BNX2_HC_STAT_GEN_SEL_3 0x0000685c bnx2.h 　
19862
 BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_ (0x7fL<<0) bnx2.h 　
19863
 BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_ (0x7fL<<8) bnx2.h 　
19864
 BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_ (0x7fL<<16) bnx2.h 　
19865
 BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_ (0x7fL<<24) bnx2.h 　
19866
 BNX2_HC_STAT_GEN_STAT0BNX2_HC_STAT_GEN_STAT0 0x00006888 bnx2.h 　
19867
 BNX2_HC_STAT_GEN_STAT1BNX2_HC_STAT_GEN_STAT1 0x0000688c bnx2.h 　
19868
 BNX2_HC_STAT_GEN_STAT2BNX2_HC_STAT_GEN_STAT2 0x00006890 bnx2.h 　
19869
 BNX2_HC_STAT_GEN_STAT3BNX2_HC_STAT_GEN_STAT3 0x00006894 bnx2.h 　
19870
 BNX2_HC_STAT_GEN_STAT4BNX2_HC_STAT_GEN_STAT4 0x00006898 bnx2.h 　
19871
 BNX2_HC_STAT_GEN_STAT5BNX2_HC_STAT_GEN_STAT5 0x0000689c bnx2.h 　
19872
 BNX2_HC_STAT_GEN_STAT6BNX2_HC_STAT_GEN_STAT6 0x000068a0 bnx2.h 　
19873
 BNX2_HC_STAT_GEN_STAT7BNX2_HC_STAT_GEN_STAT7 0x000068a4 bnx2.h 　
19874
 BNX2_HC_STAT_GEN_STAT8BNX2_HC_STAT_GEN_STAT8 0x000068a8 bnx2.h 　
19875
 BNX2_HC_STAT_GEN_STAT9BNX2_HC_STAT_GEN_STAT9 0x000068ac bnx2.h 　
19876
 BNX2_HC_STAT_GEN_STAT10BNX2_HC_STAT_GEN_STAT10 0x000068b0 bnx2.h 　
19877
 BNX2_HC_STAT_GEN_STAT11BNX2_HC_STAT_GEN_STAT11 0x000068b4 bnx2.h 　
19878
 BNX2_HC_STAT_GEN_STAT12BNX2_HC_STAT_GEN_STAT12 0x000068b8 bnx2.h 　
19879
 BNX2_HC_STAT_GEN_STAT13BNX2_HC_STAT_GEN_STAT13 0x000068bc bnx2.h 　
19880
 BNX2_HC_STAT_GEN_STAT14BNX2_HC_STAT_GEN_STAT14 0x000068c0 bnx2.h 　
19881
 BNX2_HC_STAT_GEN_STAT15BNX2_HC_STAT_GEN_STAT15 0x000068c4 bnx2.h 　
19882
 BNX2_HC_STAT_GEN_STAT_AC0BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8 bnx2.h 　
19883
 BNX2_HC_STAT_GEN_STAT_AC1BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc bnx2.h 　
19884
 BNX2_HC_STAT_GEN_STAT_AC2BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0 bnx2.h 　
19885
 BNX2_HC_STAT_GEN_STAT_AC3BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4 bnx2.h 　
19886
 BNX2_HC_STAT_GEN_STAT_AC4BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8 bnx2.h 　
19887
 BNX2_HC_STAT_GEN_STAT_AC5BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc bnx2.h 　
19888
 BNX2_HC_STAT_GEN_STAT_AC6BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0 bnx2.h 　
19889
 BNX2_HC_STAT_GEN_STAT_AC7BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4 bnx2.h 　
19890
 BNX2_HC_STAT_GEN_STAT_AC8BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8 bnx2.h 　
19891
 BNX2_HC_STAT_GEN_STAT_AC9BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec bnx2.h 　
19892
 BNX2_HC_STAT_GEN_STAT_AC10BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0 bnx2.h 　
19893
 BNX2_HC_STAT_GEN_STAT_AC11BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4 bnx2.h 　
19894
 BNX2_HC_STAT_GEN_STAT_AC12BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8 bnx2.h 　
19895
 BNX2_HC_STAT_GEN_STAT_AC13BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc bnx2.h 　
19896
 BNX2_HC_STAT_GEN_STAT_AC14BNX2_HC_STAT_GEN_STAT_AC14 0x00006900 bnx2.h 　
19897
 BNX2_HC_STAT_GEN_STAT_AC15BNX2_HC_STAT_GEN_STAT_AC15 0x00006904 bnx2.h 　
19898
 BNX2_HC_VISBNX2_HC_VIS 0x00006908 bnx2.h 　
19899
 BNX2_HC_VIS_STAT_BUILD_STATEBNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0) bnx2.h 　
19900
 BNX2_HC_VIS_STAT_BUILD_STATE_IDBNX2_HC_VIS_STAT_BUILD_STATE_ID (0L<<0) bnx2.h 　
19901
 BNX2_HC_VIS_STAT_BUILD_STATE_STBNX2_HC_VIS_STAT_BUILD_STATE_ST (1L<<0) bnx2.h 　
19902
 BNX2_HC_VIS_STAT_BUILD_STATE_REBNX2_HC_VIS_STAT_BUILD_STATE_RE (2L<<0) bnx2.h 　
19903
 BNX2_HC_VIS_STAT_BUILD_STATE_UPBNX2_HC_VIS_STAT_BUILD_STATE_UP (3L<<0) bnx2.h 　
19904
 BNX2_HC_VIS_STAT_BUILD_STATE_UPBNX2_HC_VIS_STAT_BUILD_STATE_UP (4L<<0) bnx2.h 　
19905
 BNX2_HC_VIS_STAT_BUILD_STATE_UPBNX2_HC_VIS_STAT_BUILD_STATE_UP (5L<<0) bnx2.h 　
19906
 BNX2_HC_VIS_STAT_BUILD_STATE_DMBNX2_HC_VIS_STAT_BUILD_STATE_DM (6L<<0) bnx2.h 　
19907
 BNX2_HC_VIS_STAT_BUILD_STATE_MSBNX2_HC_VIS_STAT_BUILD_STATE_MS (7L<<0) bnx2.h 　
19908
 BNX2_HC_VIS_STAT_BUILD_STATE_MSBNX2_HC_VIS_STAT_BUILD_STATE_MS (8L<<0) bnx2.h 　
19909
 BNX2_HC_VIS_STAT_BUILD_STATE_MSBNX2_HC_VIS_STAT_BUILD_STATE_MS (9L<<0) bnx2.h 　
19910
 BNX2_HC_VIS_STAT_BUILD_STATE_MSBNX2_HC_VIS_STAT_BUILD_STATE_MS (10L<<0) bnx2.h 　
19911
 BNX2_HC_VIS_DMA_STAT_STATEBNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8) bnx2.h 　
19912
 BNX2_HC_VIS_DMA_STAT_STATE_IDLEBNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8) bnx2.h 　
19913
 BNX2_HC_VIS_DMA_STAT_STATE_STATBNX2_HC_VIS_DMA_STAT_STATE_STAT (1L<<8) bnx2.h 　
19914
 BNX2_HC_VIS_DMA_STAT_STATE_STATBNX2_HC_VIS_DMA_STAT_STATE_STAT (2L<<8) bnx2.h 　
19915
 BNX2_HC_VIS_DMA_STAT_STATE_WRITBNX2_HC_VIS_DMA_STAT_STATE_WRIT (3L<<8) bnx2.h 　
19916
 BNX2_HC_VIS_DMA_STAT_STATE_COMPBNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8) bnx2.h 　
19917
 BNX2_HC_VIS_DMA_STAT_STATE_STATBNX2_HC_VIS_DMA_STAT_STATE_STAT (5L<<8) bnx2.h 　
19918
 BNX2_HC_VIS_DMA_STAT_STATE_STATBNX2_HC_VIS_DMA_STAT_STATE_STAT (6L<<8) bnx2.h 　
19919
 BNX2_HC_VIS_DMA_STAT_STATE_WRITBNX2_HC_VIS_DMA_STAT_STATE_WRIT (7L<<8) bnx2.h 　
19920
 BNX2_HC_VIS_DMA_STAT_STATE_WRITBNX2_HC_VIS_DMA_STAT_STATE_WRIT (8L<<8) bnx2.h 　
19921
 BNX2_HC_VIS_DMA_STAT_STATE_WAITBNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8) bnx2.h 　
19922
 BNX2_HC_VIS_DMA_STAT_STATE_ABORBNX2_HC_VIS_DMA_STAT_STATE_ABOR (15L<<8) bnx2.h 　
19923
 BNX2_HC_VIS_DMA_MSI_STATEBNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12) bnx2.h 　
19924
 BNX2_HC_VIS_STATISTIC_DMA_EN_STBNX2_HC_VIS_STATISTIC_DMA_EN_ST (0x3L<<15) bnx2.h 　
19925
 BNX2_HC_VIS_STATISTIC_DMA_EN_STBNX2_HC_VIS_STATISTIC_DMA_EN_ST (0L<<15) bnx2.h 　
19926
 BNX2_HC_VIS_STATISTIC_DMA_EN_STBNX2_HC_VIS_STATISTIC_DMA_EN_ST (1L<<15) bnx2.h 　
19927
 BNX2_HC_VIS_STATISTIC_DMA_EN_STBNX2_HC_VIS_STATISTIC_DMA_EN_ST (2L<<15) bnx2.h 　
19928
 BNX2_HC_VIS_1BNX2_HC_VIS_1 0x0000690c bnx2.h 　
19929
 BNX2_HC_VIS_1_HW_INTACK_STATEBNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4) bnx2.h 　
19930
 BNX2_HC_VIS_1_HW_INTACK_STATE_IBNX2_HC_VIS_1_HW_INTACK_STATE_I (0L<<4) bnx2.h 　
19931
 BNX2_HC_VIS_1_HW_INTACK_STATE_CBNX2_HC_VIS_1_HW_INTACK_STATE_C (1L<<4) bnx2.h 　
19932
 BNX2_HC_VIS_1_SW_INTACK_STATEBNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5) bnx2.h 　
19933
 BNX2_HC_VIS_1_SW_INTACK_STATE_IBNX2_HC_VIS_1_SW_INTACK_STATE_I (0L<<5) bnx2.h 　
19934
 BNX2_HC_VIS_1_SW_INTACK_STATE_CBNX2_HC_VIS_1_SW_INTACK_STATE_C (1L<<5) bnx2.h 　
19935
 BNX2_HC_VIS_1_DURING_SW_INTACK_BNX2_HC_VIS_1_DURING_SW_INTACK_ (1L<<6) bnx2.h 　
19936
 BNX2_HC_VIS_1_DURING_SW_INTACK_BNX2_HC_VIS_1_DURING_SW_INTACK_ (0L<<6) bnx2.h 　
19937
 BNX2_HC_VIS_1_DURING_SW_INTACK_BNX2_HC_VIS_1_DURING_SW_INTACK_ (1L<<6) bnx2.h 　
19938
 BNX2_HC_VIS_1_MAILBOX_COUNT_STABNX2_HC_VIS_1_MAILBOX_COUNT_STA (1L<<7) bnx2.h 　
19939
 BNX2_HC_VIS_1_MAILBOX_COUNT_STABNX2_HC_VIS_1_MAILBOX_COUNT_STA (0L<<7) bnx2.h 　
19940
 BNX2_HC_VIS_1_MAILBOX_COUNT_STABNX2_HC_VIS_1_MAILBOX_COUNT_STA (1L<<7) bnx2.h 　
19941
 BNX2_HC_VIS_1_RAM_RD_ARB_STATEBNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17) bnx2.h 　
19942
 BNX2_HC_VIS_1_RAM_RD_ARB_STATE_BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ (0L<<17) bnx2.h 　
19943
 BNX2_HC_VIS_1_RAM_RD_ARB_STATE_BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ (1L<<17) bnx2.h 　
19944
 BNX2_HC_VIS_1_RAM_RD_ARB_STATE_BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ (2L<<17) bnx2.h 　
19945
 BNX2_HC_VIS_1_RAM_RD_ARB_STATE_BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ (3L<<17) bnx2.h 　
19946
 BNX2_HC_VIS_1_RAM_RD_ARB_STATE_BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ (4L<<17) bnx2.h 　
19947
 BNX2_HC_VIS_1_RAM_RD_ARB_STATE_BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ (5L<<17) bnx2.h 　
19948
 BNX2_HC_VIS_1_RAM_RD_ARB_STATE_BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ (6L<<17) bnx2.h 　
19949
 BNX2_HC_VIS_1_RAM_RD_ARB_STATE_BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ (7L<<17) bnx2.h 　
19950
 BNX2_HC_VIS_1_RAM_WR_ARB_STATEBNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21) bnx2.h 　
19951
 BNX2_HC_VIS_1_RAM_WR_ARB_STATE_BNX2_HC_VIS_1_RAM_WR_ARB_STATE_ (0L<<21) bnx2.h 　
19952
 BNX2_HC_VIS_1_RAM_WR_ARB_STATE_BNX2_HC_VIS_1_RAM_WR_ARB_STATE_ (1L<<21) bnx2.h 　
19953
 BNX2_HC_VIS_1_INT_GEN_STATEBNX2_HC_VIS_1_INT_GEN_STATE (1L<<23) bnx2.h 　
19954
 BNX2_HC_VIS_1_INT_GEN_STATE_DLEBNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23) bnx2.h 　
19955
 BNX2_HC_VIS_1_INT_GEN_STATE_NTEBNX2_HC_VIS_1_INT_GEN_STATE_NTE (1L<<23) bnx2.h 　
19956
 BNX2_HC_VIS_1_STAT_CHAN_IDBNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24) bnx2.h 　
19957
 BNX2_HC_VIS_1_INT_BBNX2_HC_VIS_1_INT_B (1L<<27) bnx2.h 　
19958
 BNX2_HC_DEBUG_VECT_PEEKBNX2_HC_DEBUG_VECT_PEEK 0x00006910 bnx2.h 　
19959
 BNX2_HC_DEBUG_VECT_PEEK_1_VALUEBNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0) bnx2.h 　
19960
 BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_ (1L<<11) bnx2.h 　
19961
 BNX2_HC_DEBUG_VECT_PEEK_1_SELBNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12) bnx2.h 　
19962
 BNX2_HC_DEBUG_VECT_PEEK_2_VALUEBNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16) bnx2.h 　
19963
 BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_ (1L<<27) bnx2.h 　
19964
 BNX2_HC_DEBUG_VECT_PEEK_2_SELBNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28) bnx2.h 　
19965
 BNX2_TXP_CPU_MODEBNX2_TXP_CPU_MODE 0x00045000 bnx2.h 　
19966
 BNX2_TXP_CPU_MODE_LOCAL_RSTBNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0) bnx2.h 　
19967
 BNX2_TXP_CPU_MODE_STEP_ENABNX2_TXP_CPU_MODE_STEP_ENA (1L<<1) bnx2.h 　
19968
 BNX2_TXP_CPU_MODE_PAGE_0_DATA_EBNX2_TXP_CPU_MODE_PAGE_0_DATA_E (1L<<2) bnx2.h 　
19969
 BNX2_TXP_CPU_MODE_PAGE_0_INST_EBNX2_TXP_CPU_MODE_PAGE_0_INST_E (1L<<3) bnx2.h 　
19970
 BNX2_TXP_CPU_MODE_MSG_BIT1BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6) bnx2.h 　
19971
 BNX2_TXP_CPU_MODE_INTERRUPT_ENABNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7) bnx2.h 　
19972
 BNX2_TXP_CPU_MODE_SOFT_HALTBNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10) bnx2.h 　
19973
 BNX2_TXP_CPU_MODE_BAD_DATA_HALTBNX2_TXP_CPU_MODE_BAD_DATA_HALT (1L<<11) bnx2.h 　
19974
 BNX2_TXP_CPU_MODE_BAD_INST_HALTBNX2_TXP_CPU_MODE_BAD_INST_HALT (1L<<12) bnx2.h 　
19975
 BNX2_TXP_CPU_MODE_FIO_ABORT_HALBNX2_TXP_CPU_MODE_FIO_ABORT_HAL (1L<<13) bnx2.h 　
19976
 BNX2_TXP_CPU_MODE_SPAD_UNDERFLOBNX2_TXP_CPU_MODE_SPAD_UNDERFLO (1L<<15) bnx2.h 　
19977
 BNX2_TXP_CPU_STATEBNX2_TXP_CPU_STATE 0x00045004 bnx2.h 　
19978
 BNX2_TXP_CPU_STATE_BREAKPOINTBNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0) bnx2.h 　
19979
 BNX2_TXP_CPU_STATE_BAD_INST_HALBNX2_TXP_CPU_STATE_BAD_INST_HAL (1L<<2) bnx2.h 　
19980
 BNX2_TXP_CPU_STATE_PAGE_0_DATA_BNX2_TXP_CPU_STATE_PAGE_0_DATA_ (1L<<3) bnx2.h 　
19981
 BNX2_TXP_CPU_STATE_PAGE_0_INST_BNX2_TXP_CPU_STATE_PAGE_0_INST_ (1L<<4) bnx2.h 　
19982
 BNX2_TXP_CPU_STATE_BAD_DATA_ADDBNX2_TXP_CPU_STATE_BAD_DATA_ADD (1L<<5) bnx2.h 　
19983
 BNX2_TXP_CPU_STATE_BAD_pc_HALTEBNX2_TXP_CPU_STATE_BAD_pc_HALTE (1L<<6) bnx2.h 　
19984
 BNX2_TXP_CPU_STATE_ALIGN_HALTEDBNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7) bnx2.h 　
19985
 BNX2_TXP_CPU_STATE_FIO_ABORT_HABNX2_TXP_CPU_STATE_FIO_ABORT_HA (1L<<8) bnx2.h 　
19986
 BNX2_TXP_CPU_STATE_SOFT_HALTEDBNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10) bnx2.h 　
19987
 BNX2_TXP_CPU_STATE_SPAD_UNDERFLBNX2_TXP_CPU_STATE_SPAD_UNDERFL (1L<<11) bnx2.h 　
19988
 BNX2_TXP_CPU_STATE_INTERRRUPTBNX2_TXP_CPU_STATE_INTERRRUPT (1L<<12) bnx2.h 　
19989
 BNX2_TXP_CPU_STATE_DATA_ACCESS_BNX2_TXP_CPU_STATE_DATA_ACCESS_ (1L<<14) bnx2.h 　
19990
 BNX2_TXP_CPU_STATE_INST_FETCH_SBNX2_TXP_CPU_STATE_INST_FETCH_S (1L<<15) bnx2.h 　
19991
 BNX2_TXP_CPU_STATE_BLOCKED_READBNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31) bnx2.h 　
19992
 BNX2_TXP_CPU_EVENT_MASKBNX2_TXP_CPU_EVENT_MASK 0x00045008 bnx2.h 　
19993
 BNX2_TXP_CPU_EVENT_MASK_BREAKPOBNX2_TXP_CPU_EVENT_MASK_BREAKPO (1L<<0) bnx2.h 　
19994
 BNX2_TXP_CPU_EVENT_MASK_BAD_INSBNX2_TXP_CPU_EVENT_MASK_BAD_INS (1L<<2) bnx2.h 　
19995
 BNX2_TXP_CPU_EVENT_MASK_PAGE_0_BNX2_TXP_CPU_EVENT_MASK_PAGE_0_ (1L<<3) bnx2.h 　
19996
 BNX2_TXP_CPU_EVENT_MASK_PAGE_0_BNX2_TXP_CPU_EVENT_MASK_PAGE_0_ (1L<<4) bnx2.h 　
19997
 BNX2_TXP_CPU_EVENT_MASK_BAD_DATBNX2_TXP_CPU_EVENT_MASK_BAD_DAT (1L<<5) bnx2.h 　
19998
 BNX2_TXP_CPU_EVENT_MASK_BAD_PC_BNX2_TXP_CPU_EVENT_MASK_BAD_PC_ (1L<<6) bnx2.h 　
19999
 BNX2_TXP_CPU_EVENT_MASK_ALIGN_HBNX2_TXP_CPU_EVENT_MASK_ALIGN_H (1L<<7) bnx2.h 　
20000
 BNX2_TXP_CPU_EVENT_MASK_FIO_ABOBNX2_TXP_CPU_EVENT_MASK_FIO_ABO (1L<<8) bnx2.h 　
20001
 BNX2_TXP_CPU_EVENT_MASK_SOFT_HABNX2_TXP_CPU_EVENT_MASK_SOFT_HA (1L<<10) bnx2.h 　
20002
 BNX2_TXP_CPU_EVENT_MASK_SPAD_UNBNX2_TXP_CPU_EVENT_MASK_SPAD_UN (1L<<11) bnx2.h 　
20003
 BNX2_TXP_CPU_EVENT_MASK_INTERRUBNX2_TXP_CPU_EVENT_MASK_INTERRU (1L<<12) bnx2.h 　
20004
 BNX2_TXP_CPU_PROGRAM_COUNTERBNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c bnx2.h 　
20005
 BNX2_TXP_CPU_INSTRUCTIONBNX2_TXP_CPU_INSTRUCTION 0x00045020 bnx2.h 　
20006
 BNX2_TXP_CPU_DATA_ACCESSBNX2_TXP_CPU_DATA_ACCESS 0x00045024 bnx2.h 　
20007
 BNX2_TXP_CPU_INTERRUPT_ENABLEBNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028 bnx2.h 　
20008
 BNX2_TXP_CPU_INTERRUPT_VECTORBNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c bnx2.h 　
20009
 BNX2_TXP_CPU_INTERRUPT_SAVED_PCBNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030 bnx2.h 　
20010
 BNX2_TXP_CPU_HW_BREAKPOINTBNX2_TXP_CPU_HW_BREAKPOINT 0x00045034 bnx2.h 　
20011
 BNX2_TXP_CPU_HW_BREAKPOINT_DISABNX2_TXP_CPU_HW_BREAKPOINT_DISA (1L<<0) bnx2.h 　
20012
 BNX2_TXP_CPU_HW_BREAKPOINT_ADDRBNX2_TXP_CPU_HW_BREAKPOINT_ADDR (0x3fffffffL<<2) bnx2.h 　
20013
 BNX2_TXP_CPU_DEBUG_VECT_PEEKBNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038 bnx2.h 　
20014
 BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_ (0x7ffL<<0) bnx2.h 　
20015
 BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_ (1L<<11) bnx2.h 　
20016
 BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_ (0xfL<<12) bnx2.h 　
20017
 BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_ (0x7ffL<<16) bnx2.h 　
20018
 BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_ (1L<<27) bnx2.h 　
20019
 BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_ (0xfL<<28) bnx2.h 　
20020
 BNX2_TXP_CPU_LAST_BRANCH_ADDRBNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048 bnx2.h 　
20021
 BNX2_TXP_CPU_LAST_BRANCH_ADDR_TBNX2_TXP_CPU_LAST_BRANCH_ADDR_T (1L<<1) bnx2.h 　
20022
 BNX2_TXP_CPU_LAST_BRANCH_ADDR_TBNX2_TXP_CPU_LAST_BRANCH_ADDR_T (0L<<1) bnx2.h 　
20023
 BNX2_TXP_CPU_LAST_BRANCH_ADDR_TBNX2_TXP_CPU_LAST_BRANCH_ADDR_T (1L<<1) bnx2.h 　
20024
 BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBNX2_TXP_CPU_LAST_BRANCH_ADDR_L (0x3fffffffL<<2) bnx2.h 　
20025
 BNX2_TXP_CPU_REG_FILEBNX2_TXP_CPU_REG_FILE 0x00045200 bnx2.h 　
20026
 BNX2_TXP_FTQ_DATABNX2_TXP_FTQ_DATA 0x000453c0 bnx2.h 　
20027
 BNX2_TXP_FTQ_CMDBNX2_TXP_FTQ_CMD 0x000453f8 bnx2.h 　
20028
 BNX2_TXP_FTQ_CMD_OFFSETBNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20029
 BNX2_TXP_FTQ_CMD_WR_TOPBNX2_TXP_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20030
 BNX2_TXP_FTQ_CMD_WR_TOP_0BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20031
 BNX2_TXP_FTQ_CMD_WR_TOP_1BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20032
 BNX2_TXP_FTQ_CMD_SFT_RESETBNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
20033
 BNX2_TXP_FTQ_CMD_RD_DATABNX2_TXP_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20034
 BNX2_TXP_FTQ_CMD_ADD_INTERVENBNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
20035
 BNX2_TXP_FTQ_CMD_ADD_DATABNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20036
 BNX2_TXP_FTQ_CMD_INTERVENE_CLRBNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29) bnx2.h 　
20037
 BNX2_TXP_FTQ_CMD_POPBNX2_TXP_FTQ_CMD_POP (1L<<30) bnx2.h 　
20038
 BNX2_TXP_FTQ_CMD_BUSYBNX2_TXP_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
20039
 BNX2_TXP_FTQ_CTLBNX2_TXP_FTQ_CTL 0x000453fc bnx2.h 　
20040
 BNX2_TXP_FTQ_CTL_INTERVENEBNX2_TXP_FTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
20041
 BNX2_TXP_FTQ_CTL_OVERFLOWBNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20042
 BNX2_TXP_FTQ_CTL_FORCE_INTERVENBNX2_TXP_FTQ_CTL_FORCE_INTERVEN (1L<<2) bnx2.h 　
20043
 BNX2_TXP_FTQ_CTL_MAX_DEPTHBNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
20044
 BNX2_TXP_FTQ_CTL_CUR_DEPTHBNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
20045
 BNX2_TXP_SCRATCHBNX2_TXP_SCRATCH 0x00060000 bnx2.h 　
20046
 BNX2_TPAT_CPU_MODEBNX2_TPAT_CPU_MODE 0x00085000 bnx2.h 　
20047
 BNX2_TPAT_CPU_MODE_LOCAL_RSTBNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0) bnx2.h 　
20048
 BNX2_TPAT_CPU_MODE_STEP_ENABNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1) bnx2.h 　
20049
 BNX2_TPAT_CPU_MODE_PAGE_0_DATA_BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ (1L<<2) bnx2.h 　
20050
 BNX2_TPAT_CPU_MODE_PAGE_0_INST_BNX2_TPAT_CPU_MODE_PAGE_0_INST_ (1L<<3) bnx2.h 　
20051
 BNX2_TPAT_CPU_MODE_MSG_BIT1BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6) bnx2.h 　
20052
 BNX2_TPAT_CPU_MODE_INTERRUPT_ENBNX2_TPAT_CPU_MODE_INTERRUPT_EN (1L<<7) bnx2.h 　
20053
 BNX2_TPAT_CPU_MODE_SOFT_HALTBNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10) bnx2.h 　
20054
 BNX2_TPAT_CPU_MODE_BAD_DATA_HALBNX2_TPAT_CPU_MODE_BAD_DATA_HAL (1L<<11) bnx2.h 　
20055
 BNX2_TPAT_CPU_MODE_BAD_INST_HALBNX2_TPAT_CPU_MODE_BAD_INST_HAL (1L<<12) bnx2.h 　
20056
 BNX2_TPAT_CPU_MODE_FIO_ABORT_HABNX2_TPAT_CPU_MODE_FIO_ABORT_HA (1L<<13) bnx2.h 　
20057
 BNX2_TPAT_CPU_MODE_SPAD_UNDERFLBNX2_TPAT_CPU_MODE_SPAD_UNDERFL (1L<<15) bnx2.h 　
20058
 BNX2_TPAT_CPU_STATEBNX2_TPAT_CPU_STATE 0x00085004 bnx2.h 　
20059
 BNX2_TPAT_CPU_STATE_BREAKPOINTBNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0) bnx2.h 　
20060
 BNX2_TPAT_CPU_STATE_BAD_INST_HABNX2_TPAT_CPU_STATE_BAD_INST_HA (1L<<2) bnx2.h 　
20061
 BNX2_TPAT_CPU_STATE_PAGE_0_DATABNX2_TPAT_CPU_STATE_PAGE_0_DATA (1L<<3) bnx2.h 　
20062
 BNX2_TPAT_CPU_STATE_PAGE_0_INSTBNX2_TPAT_CPU_STATE_PAGE_0_INST (1L<<4) bnx2.h 　
20063
 BNX2_TPAT_CPU_STATE_BAD_DATA_ADBNX2_TPAT_CPU_STATE_BAD_DATA_AD (1L<<5) bnx2.h 　
20064
 BNX2_TPAT_CPU_STATE_BAD_pc_HALTBNX2_TPAT_CPU_STATE_BAD_pc_HALT (1L<<6) bnx2.h 　
20065
 BNX2_TPAT_CPU_STATE_ALIGN_HALTEBNX2_TPAT_CPU_STATE_ALIGN_HALTE (1L<<7) bnx2.h 　
20066
 BNX2_TPAT_CPU_STATE_FIO_ABORT_HBNX2_TPAT_CPU_STATE_FIO_ABORT_H (1L<<8) bnx2.h 　
20067
 BNX2_TPAT_CPU_STATE_SOFT_HALTEDBNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10) bnx2.h 　
20068
 BNX2_TPAT_CPU_STATE_SPAD_UNDERFBNX2_TPAT_CPU_STATE_SPAD_UNDERF (1L<<11) bnx2.h 　
20069
 BNX2_TPAT_CPU_STATE_INTERRRUPTBNX2_TPAT_CPU_STATE_INTERRRUPT (1L<<12) bnx2.h 　
20070
 BNX2_TPAT_CPU_STATE_DATA_ACCESSBNX2_TPAT_CPU_STATE_DATA_ACCESS (1L<<14) bnx2.h 　
20071
 BNX2_TPAT_CPU_STATE_INST_FETCH_BNX2_TPAT_CPU_STATE_INST_FETCH_ (1L<<15) bnx2.h 　
20072
 BNX2_TPAT_CPU_STATE_BLOCKED_REABNX2_TPAT_CPU_STATE_BLOCKED_REA (1L<<31) bnx2.h 　
20073
 BNX2_TPAT_CPU_EVENT_MASKBNX2_TPAT_CPU_EVENT_MASK 0x00085008 bnx2.h 　
20074
 BNX2_TPAT_CPU_EVENT_MASK_BREAKPBNX2_TPAT_CPU_EVENT_MASK_BREAKP (1L<<0) bnx2.h 　
20075
 BNX2_TPAT_CPU_EVENT_MASK_BAD_INBNX2_TPAT_CPU_EVENT_MASK_BAD_IN (1L<<2) bnx2.h 　
20076
 BNX2_TPAT_CPU_EVENT_MASK_PAGE_0BNX2_TPAT_CPU_EVENT_MASK_PAGE_0 (1L<<3) bnx2.h 　
20077
 BNX2_TPAT_CPU_EVENT_MASK_PAGE_0BNX2_TPAT_CPU_EVENT_MASK_PAGE_0 (1L<<4) bnx2.h 　
20078
 BNX2_TPAT_CPU_EVENT_MASK_BAD_DABNX2_TPAT_CPU_EVENT_MASK_BAD_DA (1L<<5) bnx2.h 　
20079
 BNX2_TPAT_CPU_EVENT_MASK_BAD_PCBNX2_TPAT_CPU_EVENT_MASK_BAD_PC (1L<<6) bnx2.h 　
20080
 BNX2_TPAT_CPU_EVENT_MASK_ALIGN_BNX2_TPAT_CPU_EVENT_MASK_ALIGN_ (1L<<7) bnx2.h 　
20081
 BNX2_TPAT_CPU_EVENT_MASK_FIO_ABBNX2_TPAT_CPU_EVENT_MASK_FIO_AB (1L<<8) bnx2.h 　
20082
 BNX2_TPAT_CPU_EVENT_MASK_SOFT_HBNX2_TPAT_CPU_EVENT_MASK_SOFT_H (1L<<10) bnx2.h 　
20083
 BNX2_TPAT_CPU_EVENT_MASK_SPAD_UBNX2_TPAT_CPU_EVENT_MASK_SPAD_U (1L<<11) bnx2.h 　
20084
 BNX2_TPAT_CPU_EVENT_MASK_INTERRBNX2_TPAT_CPU_EVENT_MASK_INTERR (1L<<12) bnx2.h 　
20085
 BNX2_TPAT_CPU_PROGRAM_COUNTERBNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c bnx2.h 　
20086
 BNX2_TPAT_CPU_INSTRUCTIONBNX2_TPAT_CPU_INSTRUCTION 0x00085020 bnx2.h 　
20087
 BNX2_TPAT_CPU_DATA_ACCESSBNX2_TPAT_CPU_DATA_ACCESS 0x00085024 bnx2.h 　
20088
 BNX2_TPAT_CPU_INTERRUPT_ENABLEBNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028 bnx2.h 　
20089
 BNX2_TPAT_CPU_INTERRUPT_VECTORBNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c bnx2.h 　
20090
 BNX2_TPAT_CPU_INTERRUPT_SAVED_PBNX2_TPAT_CPU_INTERRUPT_SAVED_P 0x00085030 bnx2.h 　
20091
 BNX2_TPAT_CPU_HW_BREAKPOINTBNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034 bnx2.h 　
20092
 BNX2_TPAT_CPU_HW_BREAKPOINT_DISBNX2_TPAT_CPU_HW_BREAKPOINT_DIS (1L<<0) bnx2.h 　
20093
 BNX2_TPAT_CPU_HW_BREAKPOINT_ADDBNX2_TPAT_CPU_HW_BREAKPOINT_ADD (0x3fffffffL<<2) bnx2.h 　
20094
 BNX2_TPAT_CPU_DEBUG_VECT_PEEKBNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038 bnx2.h 　
20095
 BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1 (0x7ffL<<0) bnx2.h 　
20096
 BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1 (1L<<11) bnx2.h 　
20097
 BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1 (0xfL<<12) bnx2.h 　
20098
 BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2 (0x7ffL<<16) bnx2.h 　
20099
 BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2 (1L<<27) bnx2.h 　
20100
 BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2 (0xfL<<28) bnx2.h 　
20101
 BNX2_TPAT_CPU_LAST_BRANCH_ADDRBNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048 bnx2.h 　
20102
 BNX2_TPAT_CPU_LAST_BRANCH_ADDR_BNX2_TPAT_CPU_LAST_BRANCH_ADDR_ (1L<<1) bnx2.h 　
20103
 BNX2_TPAT_CPU_LAST_BRANCH_ADDR_BNX2_TPAT_CPU_LAST_BRANCH_ADDR_ (0L<<1) bnx2.h 　
20104
 BNX2_TPAT_CPU_LAST_BRANCH_ADDR_BNX2_TPAT_CPU_LAST_BRANCH_ADDR_ (1L<<1) bnx2.h 　
20105
 BNX2_TPAT_CPU_LAST_BRANCH_ADDR_BNX2_TPAT_CPU_LAST_BRANCH_ADDR_ (0x3fffffffL<<2) bnx2.h 　
20106
 BNX2_TPAT_CPU_REG_FILEBNX2_TPAT_CPU_REG_FILE 0x00085200 bnx2.h 　
20107
 BNX2_TPAT_FTQ_DATABNX2_TPAT_FTQ_DATA 0x000853c0 bnx2.h 　
20108
 BNX2_TPAT_FTQ_CMDBNX2_TPAT_FTQ_CMD 0x000853f8 bnx2.h 　
20109
 BNX2_TPAT_FTQ_CMD_OFFSETBNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20110
 BNX2_TPAT_FTQ_CMD_WR_TOPBNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20111
 BNX2_TPAT_FTQ_CMD_WR_TOP_0BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20112
 BNX2_TPAT_FTQ_CMD_WR_TOP_1BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20113
 BNX2_TPAT_FTQ_CMD_SFT_RESETBNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
20114
 BNX2_TPAT_FTQ_CMD_RD_DATABNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20115
 BNX2_TPAT_FTQ_CMD_ADD_INTERVENBNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
20116
 BNX2_TPAT_FTQ_CMD_ADD_DATABNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20117
 BNX2_TPAT_FTQ_CMD_INTERVENE_CLRBNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29) bnx2.h 　
20118
 BNX2_TPAT_FTQ_CMD_POPBNX2_TPAT_FTQ_CMD_POP (1L<<30) bnx2.h 　
20119
 BNX2_TPAT_FTQ_CMD_BUSYBNX2_TPAT_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
20120
 BNX2_TPAT_FTQ_CTLBNX2_TPAT_FTQ_CTL 0x000853fc bnx2.h 　
20121
 BNX2_TPAT_FTQ_CTL_INTERVENEBNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
20122
 BNX2_TPAT_FTQ_CTL_OVERFLOWBNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20123
 BNX2_TPAT_FTQ_CTL_FORCE_INTERVEBNX2_TPAT_FTQ_CTL_FORCE_INTERVE (1L<<2) bnx2.h 　
20124
 BNX2_TPAT_FTQ_CTL_MAX_DEPTHBNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
20125
 BNX2_TPAT_FTQ_CTL_CUR_DEPTHBNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
20126
 BNX2_TPAT_SCRATCHBNX2_TPAT_SCRATCH 0x000a0000 bnx2.h 　
20127
 BNX2_RXP_CPU_MODEBNX2_RXP_CPU_MODE 0x000c5000 bnx2.h 　
20128
 BNX2_RXP_CPU_MODE_LOCAL_RSTBNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0) bnx2.h 　
20129
 BNX2_RXP_CPU_MODE_STEP_ENABNX2_RXP_CPU_MODE_STEP_ENA (1L<<1) bnx2.h 　
20130
 BNX2_RXP_CPU_MODE_PAGE_0_DATA_EBNX2_RXP_CPU_MODE_PAGE_0_DATA_E (1L<<2) bnx2.h 　
20131
 BNX2_RXP_CPU_MODE_PAGE_0_INST_EBNX2_RXP_CPU_MODE_PAGE_0_INST_E (1L<<3) bnx2.h 　
20132
 BNX2_RXP_CPU_MODE_MSG_BIT1BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6) bnx2.h 　
20133
 BNX2_RXP_CPU_MODE_INTERRUPT_ENABNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7) bnx2.h 　
20134
 BNX2_RXP_CPU_MODE_SOFT_HALTBNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10) bnx2.h 　
20135
 BNX2_RXP_CPU_MODE_BAD_DATA_HALTBNX2_RXP_CPU_MODE_BAD_DATA_HALT (1L<<11) bnx2.h 　
20136
 BNX2_RXP_CPU_MODE_BAD_INST_HALTBNX2_RXP_CPU_MODE_BAD_INST_HALT (1L<<12) bnx2.h 　
20137
 BNX2_RXP_CPU_MODE_FIO_ABORT_HALBNX2_RXP_CPU_MODE_FIO_ABORT_HAL (1L<<13) bnx2.h 　
20138
 BNX2_RXP_CPU_MODE_SPAD_UNDERFLOBNX2_RXP_CPU_MODE_SPAD_UNDERFLO (1L<<15) bnx2.h 　
20139
 BNX2_RXP_CPU_STATEBNX2_RXP_CPU_STATE 0x000c5004 bnx2.h 　
20140
 BNX2_RXP_CPU_STATE_BREAKPOINTBNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0) bnx2.h 　
20141
 BNX2_RXP_CPU_STATE_BAD_INST_HALBNX2_RXP_CPU_STATE_BAD_INST_HAL (1L<<2) bnx2.h 　
20142
 BNX2_RXP_CPU_STATE_PAGE_0_DATA_BNX2_RXP_CPU_STATE_PAGE_0_DATA_ (1L<<3) bnx2.h 　
20143
 BNX2_RXP_CPU_STATE_PAGE_0_INST_BNX2_RXP_CPU_STATE_PAGE_0_INST_ (1L<<4) bnx2.h 　
20144
 BNX2_RXP_CPU_STATE_BAD_DATA_ADDBNX2_RXP_CPU_STATE_BAD_DATA_ADD (1L<<5) bnx2.h 　
20145
 BNX2_RXP_CPU_STATE_BAD_pc_HALTEBNX2_RXP_CPU_STATE_BAD_pc_HALTE (1L<<6) bnx2.h 　
20146
 BNX2_RXP_CPU_STATE_ALIGN_HALTEDBNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7) bnx2.h 　
20147
 BNX2_RXP_CPU_STATE_FIO_ABORT_HABNX2_RXP_CPU_STATE_FIO_ABORT_HA (1L<<8) bnx2.h 　
20148
 BNX2_RXP_CPU_STATE_SOFT_HALTEDBNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10) bnx2.h 　
20149
 BNX2_RXP_CPU_STATE_SPAD_UNDERFLBNX2_RXP_CPU_STATE_SPAD_UNDERFL (1L<<11) bnx2.h 　
20150
 BNX2_RXP_CPU_STATE_INTERRRUPTBNX2_RXP_CPU_STATE_INTERRRUPT (1L<<12) bnx2.h 　
20151
 BNX2_RXP_CPU_STATE_DATA_ACCESS_BNX2_RXP_CPU_STATE_DATA_ACCESS_ (1L<<14) bnx2.h 　
20152
 BNX2_RXP_CPU_STATE_INST_FETCH_SBNX2_RXP_CPU_STATE_INST_FETCH_S (1L<<15) bnx2.h 　
20153
 BNX2_RXP_CPU_STATE_BLOCKED_READBNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31) bnx2.h 　
20154
 BNX2_RXP_CPU_EVENT_MASKBNX2_RXP_CPU_EVENT_MASK 0x000c5008 bnx2.h 　
20155
 BNX2_RXP_CPU_EVENT_MASK_BREAKPOBNX2_RXP_CPU_EVENT_MASK_BREAKPO (1L<<0) bnx2.h 　
20156
 BNX2_RXP_CPU_EVENT_MASK_BAD_INSBNX2_RXP_CPU_EVENT_MASK_BAD_INS (1L<<2) bnx2.h 　
20157
 BNX2_RXP_CPU_EVENT_MASK_PAGE_0_BNX2_RXP_CPU_EVENT_MASK_PAGE_0_ (1L<<3) bnx2.h 　
20158
 BNX2_RXP_CPU_EVENT_MASK_PAGE_0_BNX2_RXP_CPU_EVENT_MASK_PAGE_0_ (1L<<4) bnx2.h 　
20159
 BNX2_RXP_CPU_EVENT_MASK_BAD_DATBNX2_RXP_CPU_EVENT_MASK_BAD_DAT (1L<<5) bnx2.h 　
20160
 BNX2_RXP_CPU_EVENT_MASK_BAD_PC_BNX2_RXP_CPU_EVENT_MASK_BAD_PC_ (1L<<6) bnx2.h 　
20161
 BNX2_RXP_CPU_EVENT_MASK_ALIGN_HBNX2_RXP_CPU_EVENT_MASK_ALIGN_H (1L<<7) bnx2.h 　
20162
 BNX2_RXP_CPU_EVENT_MASK_FIO_ABOBNX2_RXP_CPU_EVENT_MASK_FIO_ABO (1L<<8) bnx2.h 　
20163
 BNX2_RXP_CPU_EVENT_MASK_SOFT_HABNX2_RXP_CPU_EVENT_MASK_SOFT_HA (1L<<10) bnx2.h 　
20164
 BNX2_RXP_CPU_EVENT_MASK_SPAD_UNBNX2_RXP_CPU_EVENT_MASK_SPAD_UN (1L<<11) bnx2.h 　
20165
 BNX2_RXP_CPU_EVENT_MASK_INTERRUBNX2_RXP_CPU_EVENT_MASK_INTERRU (1L<<12) bnx2.h 　
20166
 BNX2_RXP_CPU_PROGRAM_COUNTERBNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c bnx2.h 　
20167
 BNX2_RXP_CPU_INSTRUCTIONBNX2_RXP_CPU_INSTRUCTION 0x000c5020 bnx2.h 　
20168
 BNX2_RXP_CPU_DATA_ACCESSBNX2_RXP_CPU_DATA_ACCESS 0x000c5024 bnx2.h 　
20169
 BNX2_RXP_CPU_INTERRUPT_ENABLEBNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028 bnx2.h 　
20170
 BNX2_RXP_CPU_INTERRUPT_VECTORBNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c bnx2.h 　
20171
 BNX2_RXP_CPU_INTERRUPT_SAVED_PCBNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030 bnx2.h 　
20172
 BNX2_RXP_CPU_HW_BREAKPOINTBNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034 bnx2.h 　
20173
 BNX2_RXP_CPU_HW_BREAKPOINT_DISABNX2_RXP_CPU_HW_BREAKPOINT_DISA (1L<<0) bnx2.h 　
20174
 BNX2_RXP_CPU_HW_BREAKPOINT_ADDRBNX2_RXP_CPU_HW_BREAKPOINT_ADDR (0x3fffffffL<<2) bnx2.h 　
20175
 BNX2_RXP_CPU_DEBUG_VECT_PEEKBNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038 bnx2.h 　
20176
 BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_ (0x7ffL<<0) bnx2.h 　
20177
 BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_ (1L<<11) bnx2.h 　
20178
 BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_ (0xfL<<12) bnx2.h 　
20179
 BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_ (0x7ffL<<16) bnx2.h 　
20180
 BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_ (1L<<27) bnx2.h 　
20181
 BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_ (0xfL<<28) bnx2.h 　
20182
 BNX2_RXP_CPU_LAST_BRANCH_ADDRBNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048 bnx2.h 　
20183
 BNX2_RXP_CPU_LAST_BRANCH_ADDR_TBNX2_RXP_CPU_LAST_BRANCH_ADDR_T (1L<<1) bnx2.h 　
20184
 BNX2_RXP_CPU_LAST_BRANCH_ADDR_TBNX2_RXP_CPU_LAST_BRANCH_ADDR_T (0L<<1) bnx2.h 　
20185
 BNX2_RXP_CPU_LAST_BRANCH_ADDR_TBNX2_RXP_CPU_LAST_BRANCH_ADDR_T (1L<<1) bnx2.h 　
20186
 BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBNX2_RXP_CPU_LAST_BRANCH_ADDR_L (0x3fffffffL<<2) bnx2.h 　
20187
 BNX2_RXP_CPU_REG_FILEBNX2_RXP_CPU_REG_FILE 0x000c5200 bnx2.h 　
20188
 BNX2_RXP_CFTQ_DATABNX2_RXP_CFTQ_DATA 0x000c5380 bnx2.h 　
20189
 BNX2_RXP_CFTQ_CMDBNX2_RXP_CFTQ_CMD 0x000c53b8 bnx2.h 　
20190
 BNX2_RXP_CFTQ_CMD_OFFSETBNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20191
 BNX2_RXP_CFTQ_CMD_WR_TOPBNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20192
 BNX2_RXP_CFTQ_CMD_WR_TOP_0BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20193
 BNX2_RXP_CFTQ_CMD_WR_TOP_1BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20194
 BNX2_RXP_CFTQ_CMD_SFT_RESETBNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
20195
 BNX2_RXP_CFTQ_CMD_RD_DATABNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20196
 BNX2_RXP_CFTQ_CMD_ADD_INTERVENBNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
20197
 BNX2_RXP_CFTQ_CMD_ADD_DATABNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20198
 BNX2_RXP_CFTQ_CMD_INTERVENE_CLRBNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29) bnx2.h 　
20199
 BNX2_RXP_CFTQ_CMD_POPBNX2_RXP_CFTQ_CMD_POP (1L<<30) bnx2.h 　
20200
 BNX2_RXP_CFTQ_CMD_BUSYBNX2_RXP_CFTQ_CMD_BUSY (1L<<31) bnx2.h 　
20201
 BNX2_RXP_CFTQ_CTLBNX2_RXP_CFTQ_CTL 0x000c53bc bnx2.h 　
20202
 BNX2_RXP_CFTQ_CTL_INTERVENEBNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
20203
 BNX2_RXP_CFTQ_CTL_OVERFLOWBNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20204
 BNX2_RXP_CFTQ_CTL_FORCE_INTERVEBNX2_RXP_CFTQ_CTL_FORCE_INTERVE (1L<<2) bnx2.h 　
20205
 BNX2_RXP_CFTQ_CTL_MAX_DEPTHBNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
20206
 BNX2_RXP_CFTQ_CTL_CUR_DEPTHBNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
20207
 BNX2_RXP_FTQ_DATABNX2_RXP_FTQ_DATA 0x000c53c0 bnx2.h 　
20208
 BNX2_RXP_FTQ_CMDBNX2_RXP_FTQ_CMD 0x000c53f8 bnx2.h 　
20209
 BNX2_RXP_FTQ_CMD_OFFSETBNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20210
 BNX2_RXP_FTQ_CMD_WR_TOPBNX2_RXP_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20211
 BNX2_RXP_FTQ_CMD_WR_TOP_0BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20212
 BNX2_RXP_FTQ_CMD_WR_TOP_1BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20213
 BNX2_RXP_FTQ_CMD_SFT_RESETBNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
20214
 BNX2_RXP_FTQ_CMD_RD_DATABNX2_RXP_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20215
 BNX2_RXP_FTQ_CMD_ADD_INTERVENBNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27) bnx2.h 　
20216
 BNX2_RXP_FTQ_CMD_ADD_DATABNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20217
 BNX2_RXP_FTQ_CMD_INTERVENE_CLRBNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29) bnx2.h 　
20218
 BNX2_RXP_FTQ_CMD_POPBNX2_RXP_FTQ_CMD_POP (1L<<30) bnx2.h 　
20219
 BNX2_RXP_FTQ_CMD_BUSYBNX2_RXP_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
20220
 BNX2_RXP_FTQ_CTLBNX2_RXP_FTQ_CTL 0x000c53fc bnx2.h 　
20221
 BNX2_RXP_FTQ_CTL_INTERVENEBNX2_RXP_FTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
20222
 BNX2_RXP_FTQ_CTL_OVERFLOWBNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20223
 BNX2_RXP_FTQ_CTL_FORCE_INTERVENBNX2_RXP_FTQ_CTL_FORCE_INTERVEN (1L<<2) bnx2.h 　
20224
 BNX2_RXP_FTQ_CTL_MAX_DEPTHBNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
20225
 BNX2_RXP_FTQ_CTL_CUR_DEPTHBNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
20226
 BNX2_RXP_SCRATCHBNX2_RXP_SCRATCH 0x000e0000 bnx2.h 　
20227
 BNX2_COM_CPU_MODEBNX2_COM_CPU_MODE 0x00105000 bnx2.h 　
20228
 BNX2_COM_CPU_MODE_LOCAL_RSTBNX2_COM_CPU_MODE_LOCAL_RST (1L<<0) bnx2.h 　
20229
 BNX2_COM_CPU_MODE_STEP_ENABNX2_COM_CPU_MODE_STEP_ENA (1L<<1) bnx2.h 　
20230
 BNX2_COM_CPU_MODE_PAGE_0_DATA_EBNX2_COM_CPU_MODE_PAGE_0_DATA_E (1L<<2) bnx2.h 　
20231
 BNX2_COM_CPU_MODE_PAGE_0_INST_EBNX2_COM_CPU_MODE_PAGE_0_INST_E (1L<<3) bnx2.h 　
20232
 BNX2_COM_CPU_MODE_MSG_BIT1BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6) bnx2.h 　
20233
 BNX2_COM_CPU_MODE_INTERRUPT_ENABNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7) bnx2.h 　
20234
 BNX2_COM_CPU_MODE_SOFT_HALTBNX2_COM_CPU_MODE_SOFT_HALT (1L<<10) bnx2.h 　
20235
 BNX2_COM_CPU_MODE_BAD_DATA_HALTBNX2_COM_CPU_MODE_BAD_DATA_HALT (1L<<11) bnx2.h 　
20236
 BNX2_COM_CPU_MODE_BAD_INST_HALTBNX2_COM_CPU_MODE_BAD_INST_HALT (1L<<12) bnx2.h 　
20237
 BNX2_COM_CPU_MODE_FIO_ABORT_HALBNX2_COM_CPU_MODE_FIO_ABORT_HAL (1L<<13) bnx2.h 　
20238
 BNX2_COM_CPU_MODE_SPAD_UNDERFLOBNX2_COM_CPU_MODE_SPAD_UNDERFLO (1L<<15) bnx2.h 　
20239
 BNX2_COM_CPU_STATEBNX2_COM_CPU_STATE 0x00105004 bnx2.h 　
20240
 BNX2_COM_CPU_STATE_BREAKPOINTBNX2_COM_CPU_STATE_BREAKPOINT (1L<<0) bnx2.h 　
20241
 BNX2_COM_CPU_STATE_BAD_INST_HALBNX2_COM_CPU_STATE_BAD_INST_HAL (1L<<2) bnx2.h 　
20242
 BNX2_COM_CPU_STATE_PAGE_0_DATA_BNX2_COM_CPU_STATE_PAGE_0_DATA_ (1L<<3) bnx2.h 　
20243
 BNX2_COM_CPU_STATE_PAGE_0_INST_BNX2_COM_CPU_STATE_PAGE_0_INST_ (1L<<4) bnx2.h 　
20244
 BNX2_COM_CPU_STATE_BAD_DATA_ADDBNX2_COM_CPU_STATE_BAD_DATA_ADD (1L<<5) bnx2.h 　
20245
 BNX2_COM_CPU_STATE_BAD_pc_HALTEBNX2_COM_CPU_STATE_BAD_pc_HALTE (1L<<6) bnx2.h 　
20246
 BNX2_COM_CPU_STATE_ALIGN_HALTEDBNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7) bnx2.h 　
20247
 BNX2_COM_CPU_STATE_FIO_ABORT_HABNX2_COM_CPU_STATE_FIO_ABORT_HA (1L<<8) bnx2.h 　
20248
 BNX2_COM_CPU_STATE_SOFT_HALTEDBNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10) bnx2.h 　
20249
 BNX2_COM_CPU_STATE_SPAD_UNDERFLBNX2_COM_CPU_STATE_SPAD_UNDERFL (1L<<11) bnx2.h 　
20250
 BNX2_COM_CPU_STATE_INTERRRUPTBNX2_COM_CPU_STATE_INTERRRUPT (1L<<12) bnx2.h 　
20251
 BNX2_COM_CPU_STATE_DATA_ACCESS_BNX2_COM_CPU_STATE_DATA_ACCESS_ (1L<<14) bnx2.h 　
20252
 BNX2_COM_CPU_STATE_INST_FETCH_SBNX2_COM_CPU_STATE_INST_FETCH_S (1L<<15) bnx2.h 　
20253
 BNX2_COM_CPU_STATE_BLOCKED_READBNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31) bnx2.h 　
20254
 BNX2_COM_CPU_EVENT_MASKBNX2_COM_CPU_EVENT_MASK 0x00105008 bnx2.h 　
20255
 BNX2_COM_CPU_EVENT_MASK_BREAKPOBNX2_COM_CPU_EVENT_MASK_BREAKPO (1L<<0) bnx2.h 　
20256
 BNX2_COM_CPU_EVENT_MASK_BAD_INSBNX2_COM_CPU_EVENT_MASK_BAD_INS (1L<<2) bnx2.h 　
20257
 BNX2_COM_CPU_EVENT_MASK_PAGE_0_BNX2_COM_CPU_EVENT_MASK_PAGE_0_ (1L<<3) bnx2.h 　
20258
 BNX2_COM_CPU_EVENT_MASK_PAGE_0_BNX2_COM_CPU_EVENT_MASK_PAGE_0_ (1L<<4) bnx2.h 　
20259
 BNX2_COM_CPU_EVENT_MASK_BAD_DATBNX2_COM_CPU_EVENT_MASK_BAD_DAT (1L<<5) bnx2.h 　
20260
 BNX2_COM_CPU_EVENT_MASK_BAD_PC_BNX2_COM_CPU_EVENT_MASK_BAD_PC_ (1L<<6) bnx2.h 　
20261
 BNX2_COM_CPU_EVENT_MASK_ALIGN_HBNX2_COM_CPU_EVENT_MASK_ALIGN_H (1L<<7) bnx2.h 　
20262
 BNX2_COM_CPU_EVENT_MASK_FIO_ABOBNX2_COM_CPU_EVENT_MASK_FIO_ABO (1L<<8) bnx2.h 　
20263
 BNX2_COM_CPU_EVENT_MASK_SOFT_HABNX2_COM_CPU_EVENT_MASK_SOFT_HA (1L<<10) bnx2.h 　
20264
 BNX2_COM_CPU_EVENT_MASK_SPAD_UNBNX2_COM_CPU_EVENT_MASK_SPAD_UN (1L<<11) bnx2.h 　
20265
 BNX2_COM_CPU_EVENT_MASK_INTERRUBNX2_COM_CPU_EVENT_MASK_INTERRU (1L<<12) bnx2.h 　
20266
 BNX2_COM_CPU_PROGRAM_COUNTERBNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c bnx2.h 　
20267
 BNX2_COM_CPU_INSTRUCTIONBNX2_COM_CPU_INSTRUCTION 0x00105020 bnx2.h 　
20268
 BNX2_COM_CPU_DATA_ACCESSBNX2_COM_CPU_DATA_ACCESS 0x00105024 bnx2.h 　
20269
 BNX2_COM_CPU_INTERRUPT_ENABLEBNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028 bnx2.h 　
20270
 BNX2_COM_CPU_INTERRUPT_VECTORBNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c bnx2.h 　
20271
 BNX2_COM_CPU_INTERRUPT_SAVED_PCBNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030 bnx2.h 　
20272
 BNX2_COM_CPU_HW_BREAKPOINTBNX2_COM_CPU_HW_BREAKPOINT 0x00105034 bnx2.h 　
20273
 BNX2_COM_CPU_HW_BREAKPOINT_DISABNX2_COM_CPU_HW_BREAKPOINT_DISA (1L<<0) bnx2.h 　
20274
 BNX2_COM_CPU_HW_BREAKPOINT_ADDRBNX2_COM_CPU_HW_BREAKPOINT_ADDR (0x3fffffffL<<2) bnx2.h 　
20275
 BNX2_COM_CPU_DEBUG_VECT_PEEKBNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038 bnx2.h 　
20276
 BNX2_COM_CPU_DEBUG_VECT_PEEK_1_BNX2_COM_CPU_DEBUG_VECT_PEEK_1_ (0x7ffL<<0) bnx2.h 　
20277
 BNX2_COM_CPU_DEBUG_VECT_PEEK_1_BNX2_COM_CPU_DEBUG_VECT_PEEK_1_ (1L<<11) bnx2.h 　
20278
 BNX2_COM_CPU_DEBUG_VECT_PEEK_1_BNX2_COM_CPU_DEBUG_VECT_PEEK_1_ (0xfL<<12) bnx2.h 　
20279
 BNX2_COM_CPU_DEBUG_VECT_PEEK_2_BNX2_COM_CPU_DEBUG_VECT_PEEK_2_ (0x7ffL<<16) bnx2.h 　
20280
 BNX2_COM_CPU_DEBUG_VECT_PEEK_2_BNX2_COM_CPU_DEBUG_VECT_PEEK_2_ (1L<<27) bnx2.h 　
20281
 BNX2_COM_CPU_DEBUG_VECT_PEEK_2_BNX2_COM_CPU_DEBUG_VECT_PEEK_2_ (0xfL<<28) bnx2.h 　
20282
 BNX2_COM_CPU_LAST_BRANCH_ADDRBNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048 bnx2.h 　
20283
 BNX2_COM_CPU_LAST_BRANCH_ADDR_TBNX2_COM_CPU_LAST_BRANCH_ADDR_T (1L<<1) bnx2.h 　
20284
 BNX2_COM_CPU_LAST_BRANCH_ADDR_TBNX2_COM_CPU_LAST_BRANCH_ADDR_T (0L<<1) bnx2.h 　
20285
 BNX2_COM_CPU_LAST_BRANCH_ADDR_TBNX2_COM_CPU_LAST_BRANCH_ADDR_T (1L<<1) bnx2.h 　
20286
 BNX2_COM_CPU_LAST_BRANCH_ADDR_LBNX2_COM_CPU_LAST_BRANCH_ADDR_L (0x3fffffffL<<2) bnx2.h 　
20287
 BNX2_COM_CPU_REG_FILEBNX2_COM_CPU_REG_FILE 0x00105200 bnx2.h 　
20288
 BNX2_COM_COMXQ_FTQ_DATABNX2_COM_COMXQ_FTQ_DATA 0x00105340 bnx2.h 　
20289
 BNX2_COM_COMXQ_FTQ_CMDBNX2_COM_COMXQ_FTQ_CMD 0x00105378 bnx2.h 　
20290
 BNX2_COM_COMXQ_FTQ_CMD_OFFSETBNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20291
 BNX2_COM_COMXQ_FTQ_CMD_WR_TOPBNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20292
 BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20293
 BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20294
 BNX2_COM_COMXQ_FTQ_CMD_SFT_RESEBNX2_COM_COMXQ_FTQ_CMD_SFT_RESE (1L<<25) bnx2.h 　
20295
 BNX2_COM_COMXQ_FTQ_CMD_RD_DATABNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20296
 BNX2_COM_COMXQ_FTQ_CMD_ADD_INTEBNX2_COM_COMXQ_FTQ_CMD_ADD_INTE (1L<<27) bnx2.h 　
20297
 BNX2_COM_COMXQ_FTQ_CMD_ADD_DATABNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20298
 BNX2_COM_COMXQ_FTQ_CMD_INTERVENBNX2_COM_COMXQ_FTQ_CMD_INTERVEN (1L<<29) bnx2.h 　
20299
 BNX2_COM_COMXQ_FTQ_CMD_POPBNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30) bnx2.h 　
20300
 BNX2_COM_COMXQ_FTQ_CMD_BUSYBNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
20301
 BNX2_COM_COMXQ_FTQ_CTLBNX2_COM_COMXQ_FTQ_CTL 0x0010537c bnx2.h 　
20302
 BNX2_COM_COMXQ_FTQ_CTL_INTERVENBNX2_COM_COMXQ_FTQ_CTL_INTERVEN (1L<<0) bnx2.h 　
20303
 BNX2_COM_COMXQ_FTQ_CTL_OVERFLOWBNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20304
 BNX2_COM_COMXQ_FTQ_CTL_FORCE_INBNX2_COM_COMXQ_FTQ_CTL_FORCE_IN (1L<<2) bnx2.h 　
20305
 BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTBNX2_COM_COMXQ_FTQ_CTL_MAX_DEPT (0x3ffL<<12) bnx2.h 　
20306
 BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTBNX2_COM_COMXQ_FTQ_CTL_CUR_DEPT (0x3ffL<<22) bnx2.h 　
20307
 BNX2_COM_COMTQ_FTQ_DATABNX2_COM_COMTQ_FTQ_DATA 0x00105380 bnx2.h 　
20308
 BNX2_COM_COMTQ_FTQ_CMDBNX2_COM_COMTQ_FTQ_CMD 0x001053b8 bnx2.h 　
20309
 BNX2_COM_COMTQ_FTQ_CMD_OFFSETBNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20310
 BNX2_COM_COMTQ_FTQ_CMD_WR_TOPBNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20311
 BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20312
 BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20313
 BNX2_COM_COMTQ_FTQ_CMD_SFT_RESEBNX2_COM_COMTQ_FTQ_CMD_SFT_RESE (1L<<25) bnx2.h 　
20314
 BNX2_COM_COMTQ_FTQ_CMD_RD_DATABNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20315
 BNX2_COM_COMTQ_FTQ_CMD_ADD_INTEBNX2_COM_COMTQ_FTQ_CMD_ADD_INTE (1L<<27) bnx2.h 　
20316
 BNX2_COM_COMTQ_FTQ_CMD_ADD_DATABNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20317
 BNX2_COM_COMTQ_FTQ_CMD_INTERVENBNX2_COM_COMTQ_FTQ_CMD_INTERVEN (1L<<29) bnx2.h 　
20318
 BNX2_COM_COMTQ_FTQ_CMD_POPBNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30) bnx2.h 　
20319
 BNX2_COM_COMTQ_FTQ_CMD_BUSYBNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
20320
 BNX2_COM_COMTQ_FTQ_CTLBNX2_COM_COMTQ_FTQ_CTL 0x001053bc bnx2.h 　
20321
 BNX2_COM_COMTQ_FTQ_CTL_INTERVENBNX2_COM_COMTQ_FTQ_CTL_INTERVEN (1L<<0) bnx2.h 　
20322
 BNX2_COM_COMTQ_FTQ_CTL_OVERFLOWBNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20323
 BNX2_COM_COMTQ_FTQ_CTL_FORCE_INBNX2_COM_COMTQ_FTQ_CTL_FORCE_IN (1L<<2) bnx2.h 　
20324
 BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTBNX2_COM_COMTQ_FTQ_CTL_MAX_DEPT (0x3ffL<<12) bnx2.h 　
20325
 BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTBNX2_COM_COMTQ_FTQ_CTL_CUR_DEPT (0x3ffL<<22) bnx2.h 　
20326
 BNX2_COM_COMQ_FTQ_DATABNX2_COM_COMQ_FTQ_DATA 0x001053c0 bnx2.h 　
20327
 BNX2_COM_COMQ_FTQ_CMDBNX2_COM_COMQ_FTQ_CMD 0x001053f8 bnx2.h 　
20328
 BNX2_COM_COMQ_FTQ_CMD_OFFSETBNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20329
 BNX2_COM_COMQ_FTQ_CMD_WR_TOPBNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20330
 BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20331
 BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20332
 BNX2_COM_COMQ_FTQ_CMD_SFT_RESETBNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
20333
 BNX2_COM_COMQ_FTQ_CMD_RD_DATABNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20334
 BNX2_COM_COMQ_FTQ_CMD_ADD_INTERBNX2_COM_COMQ_FTQ_CMD_ADD_INTER (1L<<27) bnx2.h 　
20335
 BNX2_COM_COMQ_FTQ_CMD_ADD_DATABNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20336
 BNX2_COM_COMQ_FTQ_CMD_INTERVENEBNX2_COM_COMQ_FTQ_CMD_INTERVENE (1L<<29) bnx2.h 　
20337
 BNX2_COM_COMQ_FTQ_CMD_POPBNX2_COM_COMQ_FTQ_CMD_POP (1L<<30) bnx2.h 　
20338
 BNX2_COM_COMQ_FTQ_CMD_BUSYBNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
20339
 BNX2_COM_COMQ_FTQ_CTLBNX2_COM_COMQ_FTQ_CTL 0x001053fc bnx2.h 　
20340
 BNX2_COM_COMQ_FTQ_CTL_INTERVENEBNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
20341
 BNX2_COM_COMQ_FTQ_CTL_OVERFLOWBNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20342
 BNX2_COM_COMQ_FTQ_CTL_FORCE_INTBNX2_COM_COMQ_FTQ_CTL_FORCE_INT (1L<<2) bnx2.h 　
20343
 BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTHBNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
20344
 BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTHBNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
20345
 BNX2_COM_SCRATCHBNX2_COM_SCRATCH 0x00120000 bnx2.h 　
20346
 BNX2_CP_CPU_MODEBNX2_CP_CPU_MODE 0x00185000 bnx2.h 　
20347
 BNX2_CP_CPU_MODE_LOCAL_RSTBNX2_CP_CPU_MODE_LOCAL_RST (1L<<0) bnx2.h 　
20348
 BNX2_CP_CPU_MODE_STEP_ENABNX2_CP_CPU_MODE_STEP_ENA (1L<<1) bnx2.h 　
20349
 BNX2_CP_CPU_MODE_PAGE_0_DATA_ENBNX2_CP_CPU_MODE_PAGE_0_DATA_EN (1L<<2) bnx2.h 　
20350
 BNX2_CP_CPU_MODE_PAGE_0_INST_ENBNX2_CP_CPU_MODE_PAGE_0_INST_EN (1L<<3) bnx2.h 　
20351
 BNX2_CP_CPU_MODE_MSG_BIT1BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6) bnx2.h 　
20352
 BNX2_CP_CPU_MODE_INTERRUPT_ENABNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7) bnx2.h 　
20353
 BNX2_CP_CPU_MODE_SOFT_HALTBNX2_CP_CPU_MODE_SOFT_HALT (1L<<10) bnx2.h 　
20354
 BNX2_CP_CPU_MODE_BAD_DATA_HALT_BNX2_CP_CPU_MODE_BAD_DATA_HALT_ (1L<<11) bnx2.h 　
20355
 BNX2_CP_CPU_MODE_BAD_INST_HALT_BNX2_CP_CPU_MODE_BAD_INST_HALT_ (1L<<12) bnx2.h 　
20356
 BNX2_CP_CPU_MODE_FIO_ABORT_HALTBNX2_CP_CPU_MODE_FIO_ABORT_HALT (1L<<13) bnx2.h 　
20357
 BNX2_CP_CPU_MODE_SPAD_UNDERFLOWBNX2_CP_CPU_MODE_SPAD_UNDERFLOW (1L<<15) bnx2.h 　
20358
 BNX2_CP_CPU_STATEBNX2_CP_CPU_STATE 0x00185004 bnx2.h 　
20359
 BNX2_CP_CPU_STATE_BREAKPOINTBNX2_CP_CPU_STATE_BREAKPOINT (1L<<0) bnx2.h 　
20360
 BNX2_CP_CPU_STATE_BAD_INST_HALTBNX2_CP_CPU_STATE_BAD_INST_HALT (1L<<2) bnx2.h 　
20361
 BNX2_CP_CPU_STATE_PAGE_0_DATA_HBNX2_CP_CPU_STATE_PAGE_0_DATA_H (1L<<3) bnx2.h 　
20362
 BNX2_CP_CPU_STATE_PAGE_0_INST_HBNX2_CP_CPU_STATE_PAGE_0_INST_H (1L<<4) bnx2.h 　
20363
 BNX2_CP_CPU_STATE_BAD_DATA_ADDRBNX2_CP_CPU_STATE_BAD_DATA_ADDR (1L<<5) bnx2.h 　
20364
 BNX2_CP_CPU_STATE_BAD_pc_HALTEDBNX2_CP_CPU_STATE_BAD_pc_HALTED (1L<<6) bnx2.h 　
20365
 BNX2_CP_CPU_STATE_ALIGN_HALTEDBNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7) bnx2.h 　
20366
 BNX2_CP_CPU_STATE_FIO_ABORT_HALBNX2_CP_CPU_STATE_FIO_ABORT_HAL (1L<<8) bnx2.h 　
20367
 BNX2_CP_CPU_STATE_SOFT_HALTEDBNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10) bnx2.h 　
20368
 BNX2_CP_CPU_STATE_SPAD_UNDERFLOBNX2_CP_CPU_STATE_SPAD_UNDERFLO (1L<<11) bnx2.h 　
20369
 BNX2_CP_CPU_STATE_INTERRRUPTBNX2_CP_CPU_STATE_INTERRRUPT (1L<<12) bnx2.h 　
20370
 BNX2_CP_CPU_STATE_DATA_ACCESS_SBNX2_CP_CPU_STATE_DATA_ACCESS_S (1L<<14) bnx2.h 　
20371
 BNX2_CP_CPU_STATE_INST_FETCH_STBNX2_CP_CPU_STATE_INST_FETCH_ST (1L<<15) bnx2.h 　
20372
 BNX2_CP_CPU_STATE_BLOCKED_READBNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31) bnx2.h 　
20373
 BNX2_CP_CPU_EVENT_MASKBNX2_CP_CPU_EVENT_MASK 0x00185008 bnx2.h 　
20374
 BNX2_CP_CPU_EVENT_MASK_BREAKPOIBNX2_CP_CPU_EVENT_MASK_BREAKPOI (1L<<0) bnx2.h 　
20375
 BNX2_CP_CPU_EVENT_MASK_BAD_INSTBNX2_CP_CPU_EVENT_MASK_BAD_INST (1L<<2) bnx2.h 　
20376
 BNX2_CP_CPU_EVENT_MASK_PAGE_0_DBNX2_CP_CPU_EVENT_MASK_PAGE_0_D (1L<<3) bnx2.h 　
20377
 BNX2_CP_CPU_EVENT_MASK_PAGE_0_IBNX2_CP_CPU_EVENT_MASK_PAGE_0_I (1L<<4) bnx2.h 　
20378
 BNX2_CP_CPU_EVENT_MASK_BAD_DATABNX2_CP_CPU_EVENT_MASK_BAD_DATA (1L<<5) bnx2.h 　
20379
 BNX2_CP_CPU_EVENT_MASK_BAD_PC_HBNX2_CP_CPU_EVENT_MASK_BAD_PC_H (1L<<6) bnx2.h 　
20380
 BNX2_CP_CPU_EVENT_MASK_ALIGN_HABNX2_CP_CPU_EVENT_MASK_ALIGN_HA (1L<<7) bnx2.h 　
20381
 BNX2_CP_CPU_EVENT_MASK_FIO_ABORBNX2_CP_CPU_EVENT_MASK_FIO_ABOR (1L<<8) bnx2.h 　
20382
 BNX2_CP_CPU_EVENT_MASK_SOFT_HALBNX2_CP_CPU_EVENT_MASK_SOFT_HAL (1L<<10) bnx2.h 　
20383
 BNX2_CP_CPU_EVENT_MASK_SPAD_UNDBNX2_CP_CPU_EVENT_MASK_SPAD_UND (1L<<11) bnx2.h 　
20384
 BNX2_CP_CPU_EVENT_MASK_INTERRUPBNX2_CP_CPU_EVENT_MASK_INTERRUP (1L<<12) bnx2.h 　
20385
 BNX2_CP_CPU_PROGRAM_COUNTERBNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c bnx2.h 　
20386
 BNX2_CP_CPU_INSTRUCTIONBNX2_CP_CPU_INSTRUCTION 0x00185020 bnx2.h 　
20387
 BNX2_CP_CPU_DATA_ACCESSBNX2_CP_CPU_DATA_ACCESS 0x00185024 bnx2.h 　
20388
 BNX2_CP_CPU_INTERRUPT_ENABLEBNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028 bnx2.h 　
20389
 BNX2_CP_CPU_INTERRUPT_VECTORBNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c bnx2.h 　
20390
 BNX2_CP_CPU_INTERRUPT_SAVED_PCBNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030 bnx2.h 　
20391
 BNX2_CP_CPU_HW_BREAKPOINTBNX2_CP_CPU_HW_BREAKPOINT 0x00185034 bnx2.h 　
20392
 BNX2_CP_CPU_HW_BREAKPOINT_DISABBNX2_CP_CPU_HW_BREAKPOINT_DISAB (1L<<0) bnx2.h 　
20393
 BNX2_CP_CPU_HW_BREAKPOINT_ADDREBNX2_CP_CPU_HW_BREAKPOINT_ADDRE (0x3fffffffL<<2) bnx2.h 　
20394
 BNX2_CP_CPU_DEBUG_VECT_PEEKBNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038 bnx2.h 　
20395
 BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VBNX2_CP_CPU_DEBUG_VECT_PEEK_1_V (0x7ffL<<0) bnx2.h 　
20396
 BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PBNX2_CP_CPU_DEBUG_VECT_PEEK_1_P (1L<<11) bnx2.h 　
20397
 BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SBNX2_CP_CPU_DEBUG_VECT_PEEK_1_S (0xfL<<12) bnx2.h 　
20398
 BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VBNX2_CP_CPU_DEBUG_VECT_PEEK_2_V (0x7ffL<<16) bnx2.h 　
20399
 BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PBNX2_CP_CPU_DEBUG_VECT_PEEK_2_P (1L<<27) bnx2.h 　
20400
 BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SBNX2_CP_CPU_DEBUG_VECT_PEEK_2_S (0xfL<<28) bnx2.h 　
20401
 BNX2_CP_CPU_LAST_BRANCH_ADDRBNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048 bnx2.h 　
20402
 BNX2_CP_CPU_LAST_BRANCH_ADDR_TYBNX2_CP_CPU_LAST_BRANCH_ADDR_TY (1L<<1) bnx2.h 　
20403
 BNX2_CP_CPU_LAST_BRANCH_ADDR_TYBNX2_CP_CPU_LAST_BRANCH_ADDR_TY (0L<<1) bnx2.h 　
20404
 BNX2_CP_CPU_LAST_BRANCH_ADDR_TYBNX2_CP_CPU_LAST_BRANCH_ADDR_TY (1L<<1) bnx2.h 　
20405
 BNX2_CP_CPU_LAST_BRANCH_ADDR_LBBNX2_CP_CPU_LAST_BRANCH_ADDR_LB (0x3fffffffL<<2) bnx2.h 　
20406
 BNX2_CP_CPU_REG_FILEBNX2_CP_CPU_REG_FILE 0x00185200 bnx2.h 　
20407
 BNX2_CP_CPQ_FTQ_DATABNX2_CP_CPQ_FTQ_DATA 0x001853c0 bnx2.h 　
20408
 BNX2_CP_CPQ_FTQ_CMDBNX2_CP_CPQ_FTQ_CMD 0x001853f8 bnx2.h 　
20409
 BNX2_CP_CPQ_FTQ_CMD_OFFSETBNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20410
 BNX2_CP_CPQ_FTQ_CMD_WR_TOPBNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20411
 BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20412
 BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20413
 BNX2_CP_CPQ_FTQ_CMD_SFT_RESETBNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
20414
 BNX2_CP_CPQ_FTQ_CMD_RD_DATABNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20415
 BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEBNX2_CP_CPQ_FTQ_CMD_ADD_INTERVE (1L<<27) bnx2.h 　
20416
 BNX2_CP_CPQ_FTQ_CMD_ADD_DATABNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20417
 BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CBNX2_CP_CPQ_FTQ_CMD_INTERVENE_C (1L<<29) bnx2.h 　
20418
 BNX2_CP_CPQ_FTQ_CMD_POPBNX2_CP_CPQ_FTQ_CMD_POP (1L<<30) bnx2.h 　
20419
 BNX2_CP_CPQ_FTQ_CMD_BUSYBNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
20420
 BNX2_CP_CPQ_FTQ_CTLBNX2_CP_CPQ_FTQ_CTL 0x001853fc bnx2.h 　
20421
 BNX2_CP_CPQ_FTQ_CTL_INTERVENEBNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
20422
 BNX2_CP_CPQ_FTQ_CTL_OVERFLOWBNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20423
 BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERBNX2_CP_CPQ_FTQ_CTL_FORCE_INTER (1L<<2) bnx2.h 　
20424
 BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTHBNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
20425
 BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTHBNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
20426
 BNX2_CP_SCRATCHBNX2_CP_SCRATCH 0x001a0000 bnx2.h 　
20427
 BNX2_MCP_CPU_MODEBNX2_MCP_CPU_MODE 0x00145000 bnx2.h 　
20428
 BNX2_MCP_CPU_MODE_LOCAL_RSTBNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0) bnx2.h 　
20429
 BNX2_MCP_CPU_MODE_STEP_ENABNX2_MCP_CPU_MODE_STEP_ENA (1L<<1) bnx2.h 　
20430
 BNX2_MCP_CPU_MODE_PAGE_0_DATA_EBNX2_MCP_CPU_MODE_PAGE_0_DATA_E (1L<<2) bnx2.h 　
20431
 BNX2_MCP_CPU_MODE_PAGE_0_INST_EBNX2_MCP_CPU_MODE_PAGE_0_INST_E (1L<<3) bnx2.h 　
20432
 BNX2_MCP_CPU_MODE_MSG_BIT1BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6) bnx2.h 　
20433
 BNX2_MCP_CPU_MODE_INTERRUPT_ENABNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7) bnx2.h 　
20434
 BNX2_MCP_CPU_MODE_SOFT_HALTBNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10) bnx2.h 　
20435
 BNX2_MCP_CPU_MODE_BAD_DATA_HALTBNX2_MCP_CPU_MODE_BAD_DATA_HALT (1L<<11) bnx2.h 　
20436
 BNX2_MCP_CPU_MODE_BAD_INST_HALTBNX2_MCP_CPU_MODE_BAD_INST_HALT (1L<<12) bnx2.h 　
20437
 BNX2_MCP_CPU_MODE_FIO_ABORT_HALBNX2_MCP_CPU_MODE_FIO_ABORT_HAL (1L<<13) bnx2.h 　
20438
 BNX2_MCP_CPU_MODE_SPAD_UNDERFLOBNX2_MCP_CPU_MODE_SPAD_UNDERFLO (1L<<15) bnx2.h 　
20439
 BNX2_MCP_CPU_STATEBNX2_MCP_CPU_STATE 0x00145004 bnx2.h 　
20440
 BNX2_MCP_CPU_STATE_BREAKPOINTBNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0) bnx2.h 　
20441
 BNX2_MCP_CPU_STATE_BAD_INST_HALBNX2_MCP_CPU_STATE_BAD_INST_HAL (1L<<2) bnx2.h 　
20442
 BNX2_MCP_CPU_STATE_PAGE_0_DATA_BNX2_MCP_CPU_STATE_PAGE_0_DATA_ (1L<<3) bnx2.h 　
20443
 BNX2_MCP_CPU_STATE_PAGE_0_INST_BNX2_MCP_CPU_STATE_PAGE_0_INST_ (1L<<4) bnx2.h 　
20444
 BNX2_MCP_CPU_STATE_BAD_DATA_ADDBNX2_MCP_CPU_STATE_BAD_DATA_ADD (1L<<5) bnx2.h 　
20445
 BNX2_MCP_CPU_STATE_BAD_pc_HALTEBNX2_MCP_CPU_STATE_BAD_pc_HALTE (1L<<6) bnx2.h 　
20446
 BNX2_MCP_CPU_STATE_ALIGN_HALTEDBNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7) bnx2.h 　
20447
 BNX2_MCP_CPU_STATE_FIO_ABORT_HABNX2_MCP_CPU_STATE_FIO_ABORT_HA (1L<<8) bnx2.h 　
20448
 BNX2_MCP_CPU_STATE_SOFT_HALTEDBNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10) bnx2.h 　
20449
 BNX2_MCP_CPU_STATE_SPAD_UNDERFLBNX2_MCP_CPU_STATE_SPAD_UNDERFL (1L<<11) bnx2.h 　
20450
 BNX2_MCP_CPU_STATE_INTERRRUPTBNX2_MCP_CPU_STATE_INTERRRUPT (1L<<12) bnx2.h 　
20451
 BNX2_MCP_CPU_STATE_DATA_ACCESS_BNX2_MCP_CPU_STATE_DATA_ACCESS_ (1L<<14) bnx2.h 　
20452
 BNX2_MCP_CPU_STATE_INST_FETCH_SBNX2_MCP_CPU_STATE_INST_FETCH_S (1L<<15) bnx2.h 　
20453
 BNX2_MCP_CPU_STATE_BLOCKED_READBNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31) bnx2.h 　
20454
 BNX2_MCP_CPU_EVENT_MASKBNX2_MCP_CPU_EVENT_MASK 0x00145008 bnx2.h 　
20455
 BNX2_MCP_CPU_EVENT_MASK_BREAKPOBNX2_MCP_CPU_EVENT_MASK_BREAKPO (1L<<0) bnx2.h 　
20456
 BNX2_MCP_CPU_EVENT_MASK_BAD_INSBNX2_MCP_CPU_EVENT_MASK_BAD_INS (1L<<2) bnx2.h 　
20457
 BNX2_MCP_CPU_EVENT_MASK_PAGE_0_BNX2_MCP_CPU_EVENT_MASK_PAGE_0_ (1L<<3) bnx2.h 　
20458
 BNX2_MCP_CPU_EVENT_MASK_PAGE_0_BNX2_MCP_CPU_EVENT_MASK_PAGE_0_ (1L<<4) bnx2.h 　
20459
 BNX2_MCP_CPU_EVENT_MASK_BAD_DATBNX2_MCP_CPU_EVENT_MASK_BAD_DAT (1L<<5) bnx2.h 　
20460
 BNX2_MCP_CPU_EVENT_MASK_BAD_PC_BNX2_MCP_CPU_EVENT_MASK_BAD_PC_ (1L<<6) bnx2.h 　
20461
 BNX2_MCP_CPU_EVENT_MASK_ALIGN_HBNX2_MCP_CPU_EVENT_MASK_ALIGN_H (1L<<7) bnx2.h 　
20462
 BNX2_MCP_CPU_EVENT_MASK_FIO_ABOBNX2_MCP_CPU_EVENT_MASK_FIO_ABO (1L<<8) bnx2.h 　
20463
 BNX2_MCP_CPU_EVENT_MASK_SOFT_HABNX2_MCP_CPU_EVENT_MASK_SOFT_HA (1L<<10) bnx2.h 　
20464
 BNX2_MCP_CPU_EVENT_MASK_SPAD_UNBNX2_MCP_CPU_EVENT_MASK_SPAD_UN (1L<<11) bnx2.h 　
20465
 BNX2_MCP_CPU_EVENT_MASK_INTERRUBNX2_MCP_CPU_EVENT_MASK_INTERRU (1L<<12) bnx2.h 　
20466
 BNX2_MCP_CPU_PROGRAM_COUNTERBNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c bnx2.h 　
20467
 BNX2_MCP_CPU_INSTRUCTIONBNX2_MCP_CPU_INSTRUCTION 0x00145020 bnx2.h 　
20468
 BNX2_MCP_CPU_DATA_ACCESSBNX2_MCP_CPU_DATA_ACCESS 0x00145024 bnx2.h 　
20469
 BNX2_MCP_CPU_INTERRUPT_ENABLEBNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028 bnx2.h 　
20470
 BNX2_MCP_CPU_INTERRUPT_VECTORBNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c bnx2.h 　
20471
 BNX2_MCP_CPU_INTERRUPT_SAVED_PCBNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030 bnx2.h 　
20472
 BNX2_MCP_CPU_HW_BREAKPOINTBNX2_MCP_CPU_HW_BREAKPOINT 0x00145034 bnx2.h 　
20473
 BNX2_MCP_CPU_HW_BREAKPOINT_DISABNX2_MCP_CPU_HW_BREAKPOINT_DISA (1L<<0) bnx2.h 　
20474
 BNX2_MCP_CPU_HW_BREAKPOINT_ADDRBNX2_MCP_CPU_HW_BREAKPOINT_ADDR (0x3fffffffL<<2) bnx2.h 　
20475
 BNX2_MCP_CPU_DEBUG_VECT_PEEKBNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038 bnx2.h 　
20476
 BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_ (0x7ffL<<0) bnx2.h 　
20477
 BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_ (1L<<11) bnx2.h 　
20478
 BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_ (0xfL<<12) bnx2.h 　
20479
 BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_ (0x7ffL<<16) bnx2.h 　
20480
 BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_ (1L<<27) bnx2.h 　
20481
 BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_ (0xfL<<28) bnx2.h 　
20482
 BNX2_MCP_CPU_LAST_BRANCH_ADDRBNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048 bnx2.h 　
20483
 BNX2_MCP_CPU_LAST_BRANCH_ADDR_TBNX2_MCP_CPU_LAST_BRANCH_ADDR_T (1L<<1) bnx2.h 　
20484
 BNX2_MCP_CPU_LAST_BRANCH_ADDR_TBNX2_MCP_CPU_LAST_BRANCH_ADDR_T (0L<<1) bnx2.h 　
20485
 BNX2_MCP_CPU_LAST_BRANCH_ADDR_TBNX2_MCP_CPU_LAST_BRANCH_ADDR_T (1L<<1) bnx2.h 　
20486
 BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBNX2_MCP_CPU_LAST_BRANCH_ADDR_L (0x3fffffffL<<2) bnx2.h 　
20487
 BNX2_MCP_CPU_REG_FILEBNX2_MCP_CPU_REG_FILE 0x00145200 bnx2.h 　
20488
 BNX2_MCP_MCPQ_FTQ_DATABNX2_MCP_MCPQ_FTQ_DATA 0x001453c0 bnx2.h 　
20489
 BNX2_MCP_MCPQ_FTQ_CMDBNX2_MCP_MCPQ_FTQ_CMD 0x001453f8 bnx2.h 　
20490
 BNX2_MCP_MCPQ_FTQ_CMD_OFFSETBNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0) bnx2.h 　
20491
 BNX2_MCP_MCPQ_FTQ_CMD_WR_TOPBNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10) bnx2.h 　
20492
 BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10) bnx2.h 　
20493
 BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10) bnx2.h 　
20494
 BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESETBNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25) bnx2.h 　
20495
 BNX2_MCP_MCPQ_FTQ_CMD_RD_DATABNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26) bnx2.h 　
20496
 BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERBNX2_MCP_MCPQ_FTQ_CMD_ADD_INTER (1L<<27) bnx2.h 　
20497
 BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATABNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28) bnx2.h 　
20498
 BNX2_MCP_MCPQ_FTQ_CMD_INTERVENEBNX2_MCP_MCPQ_FTQ_CMD_INTERVENE (1L<<29) bnx2.h 　
20499
 BNX2_MCP_MCPQ_FTQ_CMD_POPBNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30) bnx2.h 　
20500
 BNX2_MCP_MCPQ_FTQ_CMD_BUSYBNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31) bnx2.h 　
20501
 BNX2_MCP_MCPQ_FTQ_CTLBNX2_MCP_MCPQ_FTQ_CTL 0x001453fc bnx2.h 　
20502
 BNX2_MCP_MCPQ_FTQ_CTL_INTERVENEBNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0) bnx2.h 　
20503
 BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOWBNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1) bnx2.h 　
20504
 BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTBNX2_MCP_MCPQ_FTQ_CTL_FORCE_INT (1L<<2) bnx2.h 　
20505
 BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTHBNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12) bnx2.h 　
20506
 BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTHBNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22) bnx2.h 　
20507
 BNX2_MCP_ROMBNX2_MCP_ROM 0x00150000 bnx2.h 　
20508
 BNX2_MCP_SCRATCHBNX2_MCP_SCRATCH 0x00160000 bnx2.h 　
20509
 BNX2_SHM_HDR_SIGNATUREBNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH bnx2.h 　
20510
 BNX2_SHM_HDR_SIGNATURE_SIG_MASKBNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000 bnx2.h 　
20511
 BNX2_SHM_HDR_SIGNATURE_SIGBNX2_SHM_HDR_SIGNATURE_SIG 0x53530000 bnx2.h 　
20512
 BNX2_SHM_HDR_SIGNATURE_VER_MASKBNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff bnx2.h 　
20513
 BNX2_SHM_HDR_SIGNATURE_VER_ONEBNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001 bnx2.h 　
20514
 BNX2_SHM_HDR_ADDR_0BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4 bnx2.h 　
20515
 BNX2_SHM_HDR_ADDR_1BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8 bnx2.h 　
20516
 NUM_MC_HASH_REGISTERSNUM_MC_HASH_REGISTERS 8 bnx2.h 　
20517
 PHY_BCM5706_PHY_IDPHY_BCM5706_PHY_ID 0x00206160 bnx2.h 　
20518
 BCM5708S_UP1BCM5708S_UP1 0xb bnx2.h 　
20519
 BCM5708S_UP1_2G5BCM5708S_UP1_2G5 0x1 bnx2.h 　
20520
 BCM5708S_BLK_ADDRBCM5708S_BLK_ADDR 0x1f bnx2.h 　
20521
 BCM5708S_BLK_ADDR_DIGBCM5708S_BLK_ADDR_DIG 0x0000 bnx2.h 　
20522
 BCM5708S_BLK_ADDR_DIG3BCM5708S_BLK_ADDR_DIG3 0x0002 bnx2.h 　
20523
 BCM5708S_BLK_ADDR_TX_MISCBCM5708S_BLK_ADDR_TX_MISC 0x0005 bnx2.h 　
20524
 BCM5708S_1000X_CTL1BCM5708S_1000X_CTL1 0x10 bnx2.h 　
20525
 BCM5708S_1000X_CTL1_FIBER_MODEBCM5708S_1000X_CTL1_FIBER_MODE 0x0001 bnx2.h 　
20526
 BCM5708S_1000X_CTL1_AUTODET_ENBCM5708S_1000X_CTL1_AUTODET_EN 0x0010 bnx2.h 　
20527
 BCM5708S_1000X_CTL2BCM5708S_1000X_CTL2 0x11 bnx2.h 　
20528
 BCM5708S_1000X_CTL2_PLLEL_DET_EBCM5708S_1000X_CTL2_PLLEL_DET_E 0x0001 bnx2.h 　
20529
 BCM5708S_1000X_STAT1BCM5708S_1000X_STAT1 0x14 bnx2.h 　
20530
 BCM5708S_1000X_STAT1_SGMIIBCM5708S_1000X_STAT1_SGMII 0x0001 bnx2.h 　
20531
 BCM5708S_1000X_STAT1_LINKBCM5708S_1000X_STAT1_LINK 0x0002 bnx2.h 　
20532
 BCM5708S_1000X_STAT1_FDBCM5708S_1000X_STAT1_FD 0x0004 bnx2.h 　
20533
 BCM5708S_1000X_STAT1_SPEED_MASKBCM5708S_1000X_STAT1_SPEED_MASK 0x0018 bnx2.h 　
20534
 BCM5708S_1000X_STAT1_SPEED_10BCM5708S_1000X_STAT1_SPEED_10 0x0000 bnx2.h 　
20535
 BCM5708S_1000X_STAT1_SPEED_100BCM5708S_1000X_STAT1_SPEED_100 0x0008 bnx2.h 　
20536
 BCM5708S_1000X_STAT1_SPEED_1GBCM5708S_1000X_STAT1_SPEED_1G 0x0010 bnx2.h 　
20537
 BCM5708S_1000X_STAT1_SPEED_2G5BCM5708S_1000X_STAT1_SPEED_2G5 0x0018 bnx2.h 　
20538
 BCM5708S_1000X_STAT1_TX_PAUSEBCM5708S_1000X_STAT1_TX_PAUSE 0x0020 bnx2.h 　
20539
 BCM5708S_1000X_STAT1_RX_PAUSEBCM5708S_1000X_STAT1_RX_PAUSE 0x0040 bnx2.h 　
20540
 BCM5708S_DIG_3_0BCM5708S_DIG_3_0 0x10 bnx2.h 　
20541
 BCM5708S_DIG_3_0_USE_IEEEBCM5708S_DIG_3_0_USE_IEEE 0x0001 bnx2.h 　
20542
 BCM5708S_TX_ACTL1BCM5708S_TX_ACTL1 0x15 bnx2.h 　
20543
 BCM5708S_TX_ACTL1_DRIVER_VCMBCM5708S_TX_ACTL1_DRIVER_VCM 0x30 bnx2.h 　
20544
 BCM5708S_TX_ACTL3BCM5708S_TX_ACTL3 0x17 bnx2.h 　
20545
 MIN_ETHERNET_PACKET_SIZEMIN_ETHERNET_PACKET_SIZE 60 bnx2.h 　
20546
 MAX_ETHERNET_PACKET_SIZEMAX_ETHERNET_PACKET_SIZE 1514 bnx2.h 　
20547
 MAX_ETHERNET_JUMBO_PACKET_SIZEMAX_ETHERNET_JUMBO_PACKET_SIZE 9014 bnx2.h 　
20548
 RX_COPY_THRESHRX_COPY_THRESH 92 bnx2.h 　
20549
 DMA_READ_CHANSDMA_READ_CHANS 5 bnx2.h 　
20550
 DMA_WRITE_CHANSDMA_WRITE_CHANS 3 bnx2.h 　
20551
 BCM_PAGE_BITSBCM_PAGE_BITS 12 bnx2.h 　
20552
 BCM_PAGE_SIZEBCM_PAGE_SIZE (1 << BCM_PAGE_BITS) bnx2.h 　
20553
 TX_DESC_CNTTX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd)) bnx2.h 　
20554
 MAX_TX_DESC_CNTMAX_TX_DESC_CNT (TX_DESC_CNT - 1) bnx2.h 　
20555
 MAX_RX_RINGSMAX_RX_RINGS 4 bnx2.h 　
20556
 RX_DESC_CNTRX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd)) bnx2.h 　
20557
 MAX_RX_DESC_CNTMAX_RX_DESC_CNT (RX_DESC_CNT - 1) bnx2.h 　
20558
 MAX_TOTAL_RX_DESC_CNTMAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS) bnx2.h 　
20559
 CTX_SHIFTCTX_SHIFT 7 bnx2.h 　
20560
 CTX_SIZECTX_SIZE (1 << CTX_SHIFT) bnx2.h 　
20561
 CTX_MASKCTX_MASK (CTX_SIZE - 1) bnx2.h 　
20562
 PHY_CTX_SHIFTPHY_CTX_SHIFT 6 bnx2.h 　
20563
 PHY_CTX_SIZEPHY_CTX_SIZE (1 << PHY_CTX_SHIFT) bnx2.h 　
20564
 PHY_CTX_MASKPHY_CTX_MASK (PHY_CTX_SIZE - 1) bnx2.h 　
20565
 MB_KERNEL_CTX_SHIFTMB_KERNEL_CTX_SHIFT 8 bnx2.h 　
20566
 MB_KERNEL_CTX_SIZEMB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT) bnx2.h 　
20567
 MB_KERNEL_CTX_MASKMB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1) bnx2.h 　
20568
 MAX_CID_CNTMAX_CID_CNT 0x4000 bnx2.h 　
20569
 MAX_CID_ADDRMAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT)) bnx2.h 　
20570
 INVALID_CID_ADDRINVALID_CID_ADDR 0xffffffff bnx2.h 　
20571
 TX_CIDTX_CID 16 bnx2.h 　
20572
 RX_CIDRX_CID 0 bnx2.h 　
20573
 MB_TX_CID_ADDRMB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID) bnx2.h 　
20574
 MB_RX_CID_ADDRMB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID) bnx2.h 　
20575
 SEEPROM_PAGE_BITSSEEPROM_PAGE_BITS 2 bnx2.h 　
20576
 SEEPROM_PHY_PAGE_SIZESEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS) bnx2.h 　
20577
 SEEPROM_BYTE_ADDR_MASKSEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1) bnx2.h 　
20578
 SEEPROM_PAGE_SIZESEEPROM_PAGE_SIZE 4 bnx2.h 　
20579
 SEEPROM_TOTAL_SIZESEEPROM_TOTAL_SIZE 65536 bnx2.h 　
20580
 BUFFERED_FLASH_PAGE_BITSBUFFERED_FLASH_PAGE_BITS 9 bnx2.h 　
20581
 BUFFERED_FLASH_PHY_PAGE_SIZEBUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS) bnx2.h 　
20582
 BUFFERED_FLASH_BYTE_ADDR_MASKBUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1) bnx2.h 　
20583
 BUFFERED_FLASH_PAGE_SIZEBUFFERED_FLASH_PAGE_SIZE 264 bnx2.h 　
20584
 BUFFERED_FLASH_TOTAL_SIZEBUFFERED_FLASH_TOTAL_SIZE 0x21000 bnx2.h 　
20585
 SAIFUN_FLASH_PAGE_BITSSAIFUN_FLASH_PAGE_BITS 8 bnx2.h 　
20586
 SAIFUN_FLASH_PHY_PAGE_SIZESAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS) bnx2.h 　
20587
 SAIFUN_FLASH_BYTE_ADDR_MASKSAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1) bnx2.h 　
20588
 SAIFUN_FLASH_PAGE_SIZESAIFUN_FLASH_PAGE_SIZE 256 bnx2.h 　
20589
 SAIFUN_FLASH_BASE_TOTAL_SIZESAIFUN_FLASH_BASE_TOTAL_SIZE 65536 bnx2.h 　
20590
 ST_MICRO_FLASH_PAGE_BITSST_MICRO_FLASH_PAGE_BITS 8 bnx2.h 　
20591
 ST_MICRO_FLASH_PHY_PAGE_SIZEST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS) bnx2.h 　
20592
 ST_MICRO_FLASH_BYTE_ADDR_MASKST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1) bnx2.h 　
20593
 ST_MICRO_FLASH_PAGE_SIZEST_MICRO_FLASH_PAGE_SIZE 256 bnx2.h 　
20594
 ST_MICRO_FLASH_BASE_TOTAL_SIZEST_MICRO_FLASH_BASE_TOTAL_SIZE 65536 bnx2.h 　
20595
 NVRAM_TIMEOUT_COUNTNVRAM_TIMEOUT_COUNT 30000 bnx2.h 　
20596
 FLASH_STRAP_MASKFLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \ BNX2_NVM_CFG1_BUFFER_MODE | \ BNX2_NVM_CFG1_PROTECT_MODE | \ BNX2_NVM_CFG1_FLASH_SIZE) bnx2.h 　
20597
 FLASH_BACKUP_STRAP_MASKFLASH_BACKUP_STRAP_MASK (0xf << 26) bnx2.h 　
20598
 RV2P_PROC1RV2P_PROC1 0 bnx2.h 　
20599
 RV2P_PROC2RV2P_PROC2 1 bnx2.h 　
20600
 DRV_PULSE_PERIOD_MSDRV_PULSE_PERIOD_MS 250 bnx2.h 　
20601
 FW_ACK_TIME_OUT_MSFW_ACK_TIME_OUT_MS 100 bnx2.h 　
20602
 BNX2_DRV_RESET_SIGNATUREBNX2_DRV_RESET_SIGNATURE 0x00000000 bnx2.h 　
20603
 BNX2_DRV_RESET_SIGNATURE_MAGICBNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b bnx2.h HAVK
20604
 BNX2_DRV_MBBNX2_DRV_MB 0x00000004 bnx2.h 　
20605
 BNX2_DRV_MSG_CODEBNX2_DRV_MSG_CODE 0xff000000 bnx2.h 　
20606
 BNX2_DRV_MSG_CODE_RESETBNX2_DRV_MSG_CODE_RESET 0x01000000 bnx2.h 　
20607
 BNX2_DRV_MSG_CODE_UNLOADBNX2_DRV_MSG_CODE_UNLOAD 0x02000000 bnx2.h 　
20608
 BNX2_DRV_MSG_CODE_SHUTDOWNBNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000 bnx2.h 　
20609
 BNX2_DRV_MSG_CODE_SUSPEND_WOLBNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000 bnx2.h 　
20610
 BNX2_DRV_MSG_CODE_FW_TIMEOUTBNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000 bnx2.h 　
20611
 BNX2_DRV_MSG_CODE_PULSEBNX2_DRV_MSG_CODE_PULSE 0x06000000 bnx2.h 　
20612
 BNX2_DRV_MSG_CODE_DIAGBNX2_DRV_MSG_CODE_DIAG 0x07000000 bnx2.h 　
20613
 BNX2_DRV_MSG_CODE_SUSPEND_NO_WOBNX2_DRV_MSG_CODE_SUSPEND_NO_WO 0x09000000 bnx2.h 　
20614
 BNX2_DRV_MSG_DATABNX2_DRV_MSG_DATA 0x00ff0000 bnx2.h 　
20615
 BNX2_DRV_MSG_DATA_WAIT0BNX2_DRV_MSG_DATA_WAIT0 0x00010000 bnx2.h 　
20616
 BNX2_DRV_MSG_DATA_WAIT1BNX2_DRV_MSG_DATA_WAIT1 0x00020000 bnx2.h 　
20617
 BNX2_DRV_MSG_DATA_WAIT2BNX2_DRV_MSG_DATA_WAIT2 0x00030000 bnx2.h 　
20618
 BNX2_DRV_MSG_DATA_WAIT3BNX2_DRV_MSG_DATA_WAIT3 0x00040000 bnx2.h 　
20619
 BNX2_DRV_MSG_SEQBNX2_DRV_MSG_SEQ 0x0000ffff bnx2.h 　
20620
 BNX2_FW_MBBNX2_FW_MB 0x00000008 bnx2.h 　
20621
 BNX2_FW_MSG_ACKBNX2_FW_MSG_ACK 0x0000ffff bnx2.h 　
20622
 BNX2_FW_MSG_STATUS_MASKBNX2_FW_MSG_STATUS_MASK 0x00ff0000 bnx2.h 　
20623
 BNX2_FW_MSG_STATUS_OKBNX2_FW_MSG_STATUS_OK 0x00000000 bnx2.h 　
20624
 BNX2_FW_MSG_STATUS_FAILUREBNX2_FW_MSG_STATUS_FAILURE 0x00ff0000 bnx2.h 　
20625
 BNX2_LINK_STATUSBNX2_LINK_STATUS 0x0000000c bnx2.h 　
20626
 BNX2_LINK_STATUS_INIT_VALUEBNX2_LINK_STATUS_INIT_VALUE 0xffffffff bnx2.h 　
20627
 BNX2_LINK_STATUS_LINK_UPBNX2_LINK_STATUS_LINK_UP 0x1 bnx2.h 　
20628
 BNX2_LINK_STATUS_LINK_DOWNBNX2_LINK_STATUS_LINK_DOWN 0x0 bnx2.h 　
20629
 BNX2_LINK_STATUS_SPEED_MASKBNX2_LINK_STATUS_SPEED_MASK 0x1e bnx2.h 　
20630
 BNX2_LINK_STATUS_AN_INCOMPLETEBNX2_LINK_STATUS_AN_INCOMPLETE (0<<1) bnx2.h 　
20631
 BNX2_LINK_STATUS_10HALFBNX2_LINK_STATUS_10HALF (1<<1) bnx2.h 　
20632
 BNX2_LINK_STATUS_10FULLBNX2_LINK_STATUS_10FULL (2<<1) bnx2.h 　
20633
 BNX2_LINK_STATUS_100HALFBNX2_LINK_STATUS_100HALF (3<<1) bnx2.h 　
20634
 BNX2_LINK_STATUS_100BASE_T4BNX2_LINK_STATUS_100BASE_T4 (4<<1) bnx2.h 　
20635
 BNX2_LINK_STATUS_100FULLBNX2_LINK_STATUS_100FULL (5<<1) bnx2.h 　
20636
 BNX2_LINK_STATUS_1000HALFBNX2_LINK_STATUS_1000HALF (6<<1) bnx2.h 　
20637
 BNX2_LINK_STATUS_1000FULLBNX2_LINK_STATUS_1000FULL (7<<1) bnx2.h 　
20638
 BNX2_LINK_STATUS_2500HALFBNX2_LINK_STATUS_2500HALF (8<<1) bnx2.h 　
20639
 BNX2_LINK_STATUS_2500FULLBNX2_LINK_STATUS_2500FULL (9<<1) bnx2.h 　
20640
 BNX2_LINK_STATUS_AN_ENABLEDBNX2_LINK_STATUS_AN_ENABLED (1<<5) bnx2.h 　
20641
 BNX2_LINK_STATUS_AN_COMPLETEBNX2_LINK_STATUS_AN_COMPLETE (1<<6) bnx2.h 　
20642
 BNX2_LINK_STATUS_PARALLEL_DETBNX2_LINK_STATUS_PARALLEL_DET (1<<7) bnx2.h 　
20643
 BNX2_LINK_STATUS_RESERVEDBNX2_LINK_STATUS_RESERVED (1<<8) bnx2.h 　
20644
 BNX2_LINK_STATUS_PARTNER_AD_100BNX2_LINK_STATUS_PARTNER_AD_100 (1<<9) bnx2.h 　
20645
 BNX2_LINK_STATUS_PARTNER_AD_100BNX2_LINK_STATUS_PARTNER_AD_100 (1<<10) bnx2.h 　
20646
 BNX2_LINK_STATUS_PARTNER_AD_100BNX2_LINK_STATUS_PARTNER_AD_100 (1<<11) bnx2.h 　
20647
 BNX2_LINK_STATUS_PARTNER_AD_100BNX2_LINK_STATUS_PARTNER_AD_100 (1<<12) bnx2.h 　
20648
 BNX2_LINK_STATUS_PARTNER_AD_100BNX2_LINK_STATUS_PARTNER_AD_100 (1<<13) bnx2.h 　
20649
 BNX2_LINK_STATUS_PARTNER_AD_10FBNX2_LINK_STATUS_PARTNER_AD_10F (1<<14) bnx2.h 　
20650
 BNX2_LINK_STATUS_PARTNER_AD_10HBNX2_LINK_STATUS_PARTNER_AD_10H (1<<15) bnx2.h 　
20651
 BNX2_LINK_STATUS_TX_FC_ENABLEDBNX2_LINK_STATUS_TX_FC_ENABLED (1<<16) bnx2.h 　
20652
 BNX2_LINK_STATUS_RX_FC_ENABLEDBNX2_LINK_STATUS_RX_FC_ENABLED (1<<17) bnx2.h 　
20653
 BNX2_LINK_STATUS_PARTNER_SYM_PABNX2_LINK_STATUS_PARTNER_SYM_PA (1<<18) bnx2.h 　
20654
 BNX2_LINK_STATUS_PARTNER_ASYM_PBNX2_LINK_STATUS_PARTNER_ASYM_P (1<<19) bnx2.h 　
20655
 BNX2_LINK_STATUS_SERDES_LINKBNX2_LINK_STATUS_SERDES_LINK (1<<20) bnx2.h 　
20656
 BNX2_LINK_STATUS_PARTNER_AD_250BNX2_LINK_STATUS_PARTNER_AD_250 (1<<21) bnx2.h 　
20657
 BNX2_LINK_STATUS_PARTNER_AD_250BNX2_LINK_STATUS_PARTNER_AD_250 (1<<22) bnx2.h 　
20658
 BNX2_DRV_PULSE_MBBNX2_DRV_PULSE_MB 0x00000010 bnx2.h 　
20659
 BNX2_DRV_PULSE_SEQ_MASKBNX2_DRV_PULSE_SEQ_MASK 0x00007fff bnx2.h 　
20660
 BNX2_DRV_MSG_DATA_PULSE_CODE_ALBNX2_DRV_MSG_DATA_PULSE_CODE_AL 0x00080000 bnx2.h 　
20661
 BNX2_DEV_INFO_SIGNATUREBNX2_DEV_INFO_SIGNATURE 0x00000020 bnx2.h 　
20662
 BNX2_DEV_INFO_SIGNATURE_MAGICBNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900 bnx2.h 　
20663
 BNX2_DEV_INFO_SIGNATURE_MAGIC_MBNX2_DEV_INFO_SIGNATURE_MAGIC_M 0xffffff00 bnx2.h 　
20664
 BNX2_DEV_INFO_FEATURE_CFG_VALIDBNX2_DEV_INFO_FEATURE_CFG_VALID 0x01 bnx2.h 　
20665
 BNX2_DEV_INFO_SECONDARY_PORTBNX2_DEV_INFO_SECONDARY_PORT 0x80 bnx2.h 　
20666
 BNX2_DEV_INFO_DRV_ALWAYS_ALIVEBNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40 bnx2.h 　
20667
 BNX2_SHARED_HW_CFG_PART_NUMBNX2_SHARED_HW_CFG_PART_NUM 0x00000024 bnx2.h 　
20668
 BNX2_SHARED_HW_CFG_POWER_DISSIPBNX2_SHARED_HW_CFG_POWER_DISSIP 0x00000034 bnx2.h 　
20669
 BNX2_SHARED_HW_CFG_POWER_STATE_BNX2_SHARED_HW_CFG_POWER_STATE_ 0xff000000 bnx2.h 　
20670
 BNX2_SHARED_HW_CFG_POWER_STATE_BNX2_SHARED_HW_CFG_POWER_STATE_ 0xff0000 bnx2.h 　
20671
 BNX2_SHARED_HW_CFG_POWER_STATE_BNX2_SHARED_HW_CFG_POWER_STATE_ 0xff00 bnx2.h 　
20672
 BNX2_SHARED_HW_CFG_POWER_STATE_BNX2_SHARED_HW_CFG_POWER_STATE_ 0xff bnx2.h 　
20673
 BNX2_SHARED_HW_CFGBNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038 bnx2.h 　
20674
 BNX2_SHARED_HW_CFG_CONFIGBNX2_SHARED_HW_CFG_CONFIG 0x0000003c bnx2.h 　
20675
 BNX2_SHARED_HW_CFG_DESIGN_NICBNX2_SHARED_HW_CFG_DESIGN_NIC 0 bnx2.h 　
20676
 BNX2_SHARED_HW_CFG_DESIGN_LOMBNX2_SHARED_HW_CFG_DESIGN_LOM 0x1 bnx2.h 　
20677
 BNX2_SHARED_HW_CFG_PHY_COPPERBNX2_SHARED_HW_CFG_PHY_COPPER 0 bnx2.h 　
20678
 BNX2_SHARED_HW_CFG_PHY_FIBERBNX2_SHARED_HW_CFG_PHY_FIBER 0x2 bnx2.h 　
20679
 BNX2_SHARED_HW_CFG_PHY_2_5GBNX2_SHARED_HW_CFG_PHY_2_5G 0x20 bnx2.h 　
20680
 BNX2_SHARED_HW_CFG_PHY_BACKPLANBNX2_SHARED_HW_CFG_PHY_BACKPLAN 0x40 bnx2.h 　
20681
 BNX2_SHARED_HW_CFG_LED_MODE_SHIBNX2_SHARED_HW_CFG_LED_MODE_SHI 8 bnx2.h 　
20682
 BNX2_SHARED_HW_CFG_LED_MODE_MASBNX2_SHARED_HW_CFG_LED_MODE_MAS 0x300 bnx2.h 　
20683
 BNX2_SHARED_HW_CFG_LED_MODE_MACBNX2_SHARED_HW_CFG_LED_MODE_MAC 0 bnx2.h 　
20684
 BNX2_SHARED_HW_CFG_LED_MODE_GPHBNX2_SHARED_HW_CFG_LED_MODE_GPH 0x100 bnx2.h 　
20685
 BNX2_SHARED_HW_CFG_LED_MODE_GPHBNX2_SHARED_HW_CFG_LED_MODE_GPH 0x200 bnx2.h 　
20686
 BNX2_SHARED_HW_CFG_CONFIG2BNX2_SHARED_HW_CFG_CONFIG2 0x00000040 bnx2.h 　
20687
 BNX2_SHARED_HW_CFG2_NVM_SIZE_MABNX2_SHARED_HW_CFG2_NVM_SIZE_MA 0x00fff000 bnx2.h 　
20688
 BNX2_DEV_INFO_BC_REVBNX2_DEV_INFO_BC_REV 0x0000004c bnx2.h 　
20689
 BNX2_PORT_HW_CFG_MAC_UPPERBNX2_PORT_HW_CFG_MAC_UPPER 0x00000050 bnx2.h 　
20690
 BNX2_PORT_HW_CFG_UPPERMAC_MASKBNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff bnx2.h 　
20691
 BNX2_PORT_HW_CFG_MAC_LOWERBNX2_PORT_HW_CFG_MAC_LOWER 0x00000054 bnx2.h 　
20692
 BNX2_PORT_HW_CFG_CONFIGBNX2_PORT_HW_CFG_CONFIG 0x00000058 bnx2.h 　
20693
 BNX2_PORT_HW_CFG_CFG_TXCTL3_MASBNX2_PORT_HW_CFG_CFG_TXCTL3_MAS 0x0000ffff bnx2.h 　
20694
 BNX2_PORT_HW_CFG_CFG_DFLT_LINK_BNX2_PORT_HW_CFG_CFG_DFLT_LINK_ 0x001f0000 bnx2.h 　
20695
 BNX2_PORT_HW_CFG_CFG_DFLT_LINK_BNX2_PORT_HW_CFG_CFG_DFLT_LINK_ 0x00000000 bnx2.h 　
20696
 BNX2_PORT_HW_CFG_CFG_DFLT_LINK_BNX2_PORT_HW_CFG_CFG_DFLT_LINK_ 0x00030000 bnx2.h 　
20697
 BNX2_PORT_HW_CFG_CFG_DFLT_LINK_BNX2_PORT_HW_CFG_CFG_DFLT_LINK_ 0x00040000 bnx2.h 　
20698
 BNX2_PORT_HW_CFG_IMD_MAC_A_UPPEBNX2_PORT_HW_CFG_IMD_MAC_A_UPPE 0x00000068 bnx2.h 　
20699
 BNX2_PORT_HW_CFG_IMD_MAC_A_LOWEBNX2_PORT_HW_CFG_IMD_MAC_A_LOWE 0x0000006c bnx2.h 　
20700
 BNX2_PORT_HW_CFG_IMD_MAC_B_UPPEBNX2_PORT_HW_CFG_IMD_MAC_B_UPPE 0x00000070 bnx2.h 　
20701
 BNX2_PORT_HW_CFG_IMD_MAC_B_LOWEBNX2_PORT_HW_CFG_IMD_MAC_B_LOWE 0x00000074 bnx2.h 　
20702
 BNX2_PORT_HW_CFG_ISCSI_MAC_UPPEBNX2_PORT_HW_CFG_ISCSI_MAC_UPPE 0x00000078 bnx2.h 　
20703
 BNX2_PORT_HW_CFG_ISCSI_MAC_LOWEBNX2_PORT_HW_CFG_ISCSI_MAC_LOWE 0x0000007c bnx2.h 　
20704
 BNX2_DEV_INFO_PER_PORT_HW_CONFIBNX2_DEV_INFO_PER_PORT_HW_CONFI 0x000000b4 bnx2.h 　
20705
 BNX2_DEV_INFO_FORMAT_REVBNX2_DEV_INFO_FORMAT_REV 0x000000c4 bnx2.h 　
20706
 BNX2_DEV_INFO_FORMAT_REV_MASKBNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000 bnx2.h 　
20707
 BNX2_DEV_INFO_FORMAT_REV_IDBNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24) bnx2.h 　
20708
 BNX2_SHARED_FEATUREBNX2_SHARED_FEATURE 0x000000c8 bnx2.h 　
20709
 BNX2_SHARED_FEATURE_MASKBNX2_SHARED_FEATURE_MASK 0xffffffff bnx2.h 　
20710
 BNX2_PORT_FEATUREBNX2_PORT_FEATURE 0x000000d8 bnx2.h 　
20711
 BNX2_PORT2_FEATUREBNX2_PORT2_FEATURE 0x00000014c bnx2.h 　
20712
 BNX2_PORT_FEATURE_WOL_ENABLEDBNX2_PORT_FEATURE_WOL_ENABLED 0x01000000 bnx2.h 　
20713
 BNX2_PORT_FEATURE_MBA_ENABLEDBNX2_PORT_FEATURE_MBA_ENABLED 0x02000000 bnx2.h 　
20714
 BNX2_PORT_FEATURE_ASF_ENABLEDBNX2_PORT_FEATURE_ASF_ENABLED 0x04000000 bnx2.h 　
20715
 BNX2_PORT_FEATURE_IMD_ENABLEDBNX2_PORT_FEATURE_IMD_ENABLED 0x08000000 bnx2.h 　
20716
 BNX2_PORT_FEATURE_BAR1_SIZE_MASBNX2_PORT_FEATURE_BAR1_SIZE_MAS 0xf bnx2.h 　
20717
 BNX2_PORT_FEATURE_BAR1_SIZE_DISBNX2_PORT_FEATURE_BAR1_SIZE_DIS 0x0 bnx2.h 　
20718
 BNX2_PORT_FEATURE_BAR1_SIZE_64KBNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1 bnx2.h 　
20719
 BNX2_PORT_FEATURE_BAR1_SIZE_128BNX2_PORT_FEATURE_BAR1_SIZE_128 0x2 bnx2.h 　
20720
 BNX2_PORT_FEATURE_BAR1_SIZE_256BNX2_PORT_FEATURE_BAR1_SIZE_256 0x3 bnx2.h 　
20721
 BNX2_PORT_FEATURE_BAR1_SIZE_512BNX2_PORT_FEATURE_BAR1_SIZE_512 0x4 bnx2.h 　
20722
 BNX2_PORT_FEATURE_BAR1_SIZE_1MBNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5 bnx2.h 　
20723
 BNX2_PORT_FEATURE_BAR1_SIZE_2MBNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6 bnx2.h 　
20724
 BNX2_PORT_FEATURE_BAR1_SIZE_4MBNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7 bnx2.h 　
20725
 BNX2_PORT_FEATURE_BAR1_SIZE_8MBNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8 bnx2.h 　
20726
 BNX2_PORT_FEATURE_BAR1_SIZE_16MBNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9 bnx2.h 　
20727
 BNX2_PORT_FEATURE_BAR1_SIZE_32MBNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa bnx2.h 　
20728
 BNX2_PORT_FEATURE_BAR1_SIZE_64MBNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb bnx2.h 　
20729
 BNX2_PORT_FEATURE_BAR1_SIZE_128BNX2_PORT_FEATURE_BAR1_SIZE_128 0xc bnx2.h 　
20730
 BNX2_PORT_FEATURE_BAR1_SIZE_256BNX2_PORT_FEATURE_BAR1_SIZE_256 0xd bnx2.h 　
20731
 BNX2_PORT_FEATURE_BAR1_SIZE_512BNX2_PORT_FEATURE_BAR1_SIZE_512 0xe bnx2.h 　
20732
 BNX2_PORT_FEATURE_BAR1_SIZE_1GBNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf bnx2.h 　
20733
 BNX2_PORT_FEATURE_WOLBNX2_PORT_FEATURE_WOL 0xdc bnx2.h 　
20734
 BNX2_PORT2_FEATURE_WOLBNX2_PORT2_FEATURE_WOL 0x150 bnx2.h 　
20735
 BNX2_PORT_FEATURE_WOL_DEFAULT_SBNX2_PORT_FEATURE_WOL_DEFAULT_S 4 bnx2.h 　
20736
 BNX2_PORT_FEATURE_WOL_DEFAULT_MBNX2_PORT_FEATURE_WOL_DEFAULT_M 0x30 bnx2.h 　
20737
 BNX2_PORT_FEATURE_WOL_DEFAULT_DBNX2_PORT_FEATURE_WOL_DEFAULT_D 0 bnx2.h 　
20738
 BNX2_PORT_FEATURE_WOL_DEFAULT_MBNX2_PORT_FEATURE_WOL_DEFAULT_M 0x10 bnx2.h 　
20739
 BNX2_PORT_FEATURE_WOL_DEFAULT_ABNX2_PORT_FEATURE_WOL_DEFAULT_A 0x20 bnx2.h 　
20740
 BNX2_PORT_FEATURE_WOL_DEFAULT_MBNX2_PORT_FEATURE_WOL_DEFAULT_M 0x30 bnx2.h 　
20741
 BNX2_PORT_FEATURE_WOL_LINK_SPEEBNX2_PORT_FEATURE_WOL_LINK_SPEE 0xf bnx2.h 　
20742
 BNX2_PORT_FEATURE_WOL_LINK_SPEEBNX2_PORT_FEATURE_WOL_LINK_SPEE 0 bnx2.h 　
20743
 BNX2_PORT_FEATURE_WOL_LINK_SPEEBNX2_PORT_FEATURE_WOL_LINK_SPEE 1 bnx2.h 　
20744
 BNX2_PORT_FEATURE_WOL_LINK_SPEEBNX2_PORT_FEATURE_WOL_LINK_SPEE 2 bnx2.h 　
20745
 BNX2_PORT_FEATURE_WOL_LINK_SPEEBNX2_PORT_FEATURE_WOL_LINK_SPEE 3 bnx2.h 　
20746
 BNX2_PORT_FEATURE_WOL_LINK_SPEEBNX2_PORT_FEATURE_WOL_LINK_SPEE 4 bnx2.h 　
20747
 BNX2_PORT_FEATURE_WOL_LINK_SPEEBNX2_PORT_FEATURE_WOL_LINK_SPEE 5 bnx2.h 　
20748
 BNX2_PORT_FEATURE_WOL_LINK_SPEEBNX2_PORT_FEATURE_WOL_LINK_SPEE 6 bnx2.h 　
20749
 BNX2_PORT_FEATURE_WOL_AUTONEG_ABNX2_PORT_FEATURE_WOL_AUTONEG_A 0x40 bnx2.h 　
20750
 BNX2_PORT_FEATURE_WOL_RESERVED_BNX2_PORT_FEATURE_WOL_RESERVED_ 0x400 bnx2.h 　
20751
 BNX2_PORT_FEATURE_WOL_RESERVED_BNX2_PORT_FEATURE_WOL_RESERVED_ 0x800 bnx2.h 　
20752
 BNX2_PORT_FEATURE_MBABNX2_PORT_FEATURE_MBA 0xe0 bnx2.h 　
20753
 BNX2_PORT2_FEATURE_MBABNX2_PORT2_FEATURE_MBA 0x154 bnx2.h 　
20754
 BNX2_PORT_FEATURE_MBA_BOOT_AGENBNX2_PORT_FEATURE_MBA_BOOT_AGEN 0 bnx2.h 　
20755
 BNX2_PORT_FEATURE_MBA_BOOT_AGENBNX2_PORT_FEATURE_MBA_BOOT_AGEN 0x3 bnx2.h 　
20756
 BNX2_PORT_FEATURE_MBA_BOOT_AGENBNX2_PORT_FEATURE_MBA_BOOT_AGEN 0 bnx2.h 　
20757
 BNX2_PORT_FEATURE_MBA_BOOT_AGENBNX2_PORT_FEATURE_MBA_BOOT_AGEN 1 bnx2.h 　
20758
 BNX2_PORT_FEATURE_MBA_BOOT_AGENBNX2_PORT_FEATURE_MBA_BOOT_AGEN 2 bnx2.h 　
20759
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 2 bnx2.h 　
20760
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 0x3c bnx2.h 　
20761
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 0 bnx2.h 　
20762
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 0x4 bnx2.h 　
20763
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 0x8 bnx2.h 　
20764
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 0xc bnx2.h 　
20765
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 0x10 bnx2.h 　
20766
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 0x14 bnx2.h 　
20767
 BNX2_PORT_FEATURE_MBA_LINK_SPEEBNX2_PORT_FEATURE_MBA_LINK_SPEE 0x18 bnx2.h 　
20768
 BNX2_PORT_FEATURE_MBA_SETUP_PROBNX2_PORT_FEATURE_MBA_SETUP_PRO 0x40 bnx2.h 　
20769
 BNX2_PORT_FEATURE_MBA_HOTKEY_CTBNX2_PORT_FEATURE_MBA_HOTKEY_CT 0 bnx2.h 　
20770
 BNX2_PORT_FEATURE_MBA_HOTKEY_CTBNX2_PORT_FEATURE_MBA_HOTKEY_CT 0x80 bnx2.h 　
20771
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 8 bnx2.h 　
20772
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0xff00 bnx2.h 　
20773
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0 bnx2.h 　
20774
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x100 bnx2.h 　
20775
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x200 bnx2.h 　
20776
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x300 bnx2.h 　
20777
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x400 bnx2.h 　
20778
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x500 bnx2.h 　
20779
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x600 bnx2.h 　
20780
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x700 bnx2.h 　
20781
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x800 bnx2.h 　
20782
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0x900 bnx2.h 　
20783
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0xa00 bnx2.h 　
20784
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0xb00 bnx2.h 　
20785
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0xc00 bnx2.h 　
20786
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0xd00 bnx2.h 　
20787
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0xe00 bnx2.h 　
20788
 BNX2_PORT_FEATURE_MBA_EXP_ROM_SBNX2_PORT_FEATURE_MBA_EXP_ROM_S 0xf00 bnx2.h 　
20789
 BNX2_PORT_FEATURE_MBA_MSG_TIMEOBNX2_PORT_FEATURE_MBA_MSG_TIMEO 16 bnx2.h 　
20790
 BNX2_PORT_FEATURE_MBA_MSG_TIMEOBNX2_PORT_FEATURE_MBA_MSG_TIMEO 0xf0000 bnx2.h 　
20791
 BNX2_PORT_FEATURE_MBA_BIOS_BOOTBNX2_PORT_FEATURE_MBA_BIOS_BOOT 20 bnx2.h 　
20792
 BNX2_PORT_FEATURE_MBA_BIOS_BOOTBNX2_PORT_FEATURE_MBA_BIOS_BOOT 0x300000 bnx2.h 　
20793
 BNX2_PORT_FEATURE_MBA_BIOS_BOOTBNX2_PORT_FEATURE_MBA_BIOS_BOOT 0 bnx2.h 　
20794
 BNX2_PORT_FEATURE_MBA_BIOS_BOOTBNX2_PORT_FEATURE_MBA_BIOS_BOOT 0x100000 bnx2.h 　
20795
 BNX2_PORT_FEATURE_MBA_BIOS_BOOTBNX2_PORT_FEATURE_MBA_BIOS_BOOT 0x200000 bnx2.h 　
20796
 BNX2_PORT_FEATURE_MBA_BIOS_BOOTBNX2_PORT_FEATURE_MBA_BIOS_BOOT 0x300000 bnx2.h 　
20797
 BNX2_PORT_FEATURE_IMDBNX2_PORT_FEATURE_IMD 0xe4 bnx2.h 　
20798
 BNX2_PORT2_FEATURE_IMDBNX2_PORT2_FEATURE_IMD 0x158 bnx2.h 　
20799
 BNX2_PORT_FEATURE_IMD_LINK_OVERBNX2_PORT_FEATURE_IMD_LINK_OVER 0 bnx2.h 　
20800
 BNX2_PORT_FEATURE_IMD_LINK_OVERBNX2_PORT_FEATURE_IMD_LINK_OVER 1 bnx2.h 　
20801
 BNX2_PORT_FEATURE_VLANBNX2_PORT_FEATURE_VLAN 0xe8 bnx2.h 　
20802
 BNX2_PORT2_FEATURE_VLANBNX2_PORT2_FEATURE_VLAN 0x15c bnx2.h 　
20803
 BNX2_PORT_FEATURE_MBA_VLAN_TAG_BNX2_PORT_FEATURE_MBA_VLAN_TAG_ 0xffff bnx2.h 　
20804
 BNX2_PORT_FEATURE_MBA_VLAN_ENABBNX2_PORT_FEATURE_MBA_VLAN_ENAB 0x10000 bnx2.h 　
20805
 BNX2_BC_STATE_RESET_TYPEBNX2_BC_STATE_RESET_TYPE 0x000001c0 bnx2.h 　
20806
 BNX2_BC_STATE_RESET_TYPE_SIGBNX2_BC_STATE_RESET_TYPE_SIG 0x00005254 bnx2.h 　
20807
 BNX2_BC_STATE_RESET_TYPE_SIG_MABNX2_BC_STATE_RESET_TYPE_SIG_MA 0x0000ffff bnx2.h 　
20808
 BNX2_BC_STATE_RESET_TYPE_NONEBNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \ 0x00010000) bnx2.h 　
20809
 BNX2_BC_STATE_RESET_TYPE_PCIBNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \ 0x00020000) bnx2.h 　
20810
 BNX2_BC_STATE_RESET_TYPE_VAUXBNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \ 0x00030000) bnx2.h 　
20811
 BNX2_BC_STATE_RESET_TYPE_DRV_MABNX2_BC_STATE_RESET_TYPE_DRV_MA DRV_MSG_CODE bnx2.h 　
20812
 BNX2_BC_STATE_RESET_TYPE_DRV_REBNX2_BC_STATE_RESET_TYPE_DRV_RE (BNX2_BC_STATE_RESET_TYPE_SIG | \ DRV_MSG_CODE_RESET) bnx2.h 　
20813
 BNX2_BC_STATE_RESET_TYPE_DRV_UNBNX2_BC_STATE_RESET_TYPE_DRV_UN (BNX2_BC_STATE_RESET_TYPE_SIG | \ DRV_MSG_CODE_UNLOAD) bnx2.h 　
20814
 BNX2_BC_STATE_RESET_TYPE_DRV_SHBNX2_BC_STATE_RESET_TYPE_DRV_SH (BNX2_BC_STATE_RESET_TYPE_SIG | \ DRV_MSG_CODE_SHUTDOWN) bnx2.h 　
20815
 BNX2_BC_STATE_RESET_TYPE_DRV_WOBNX2_BC_STATE_RESET_TYPE_DRV_WO (BNX2_BC_STATE_RESET_TYPE_SIG | \ DRV_MSG_CODE_WOL) bnx2.h 　
20816
 BNX2_BC_STATE_RESET_TYPE_DRV_DIBNX2_BC_STATE_RESET_TYPE_DRV_DI (BNX2_BC_STATE_RESET_TYPE_SIG | \ DRV_MSG_CODE_DIAG) bnx2.h 　
20817
 BNX2_BC_STATEBNX2_BC_STATE 0x000001c4 bnx2.h 　
20818
 BNX2_BC_STATE_ERR_MASKBNX2_BC_STATE_ERR_MASK 0x0000ff00 bnx2.h 　
20819
 BNX2_BC_STATE_SIGNBNX2_BC_STATE_SIGN 0x42530000 bnx2.h 　
20820
 BNX2_BC_STATE_SIGN_MASKBNX2_BC_STATE_SIGN_MASK 0xffff0000 bnx2.h 　
20821
 BNX2_BC_STATE_BC1_STARTBNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1) bnx2.h 　
20822
 BNX2_BC_STATE_GET_NVM_CFG1BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2) bnx2.h 　
20823
 BNX2_BC_STATE_PROG_BARBNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3) bnx2.h 　
20824
 BNX2_BC_STATE_INIT_VIDBNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4) bnx2.h 　
20825
 BNX2_BC_STATE_GET_NVM_CFG2BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5) bnx2.h 　
20826
 BNX2_BC_STATE_APPLY_WKARNDBNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6) bnx2.h 　
20827
 BNX2_BC_STATE_LOAD_BC2BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7) bnx2.h 　
20828
 BNX2_BC_STATE_GOING_BC2BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8) bnx2.h 　
20829
 BNX2_BC_STATE_GOING_DIAGBNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9) bnx2.h 　
20830
 BNX2_BC_STATE_RT_FINAL_INITBNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81) bnx2.h 　
20831
 BNX2_BC_STATE_RT_WKARNDBNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82) bnx2.h 　
20832
 BNX2_BC_STATE_RT_DRV_PULSEBNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83) bnx2.h 　
20833
 BNX2_BC_STATE_RT_FIOEVTSBNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84) bnx2.h 　
20834
 BNX2_BC_STATE_RT_DRV_CMDBNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85) bnx2.h 　
20835
 BNX2_BC_STATE_RT_LOW_POWERBNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86) bnx2.h 　
20836
 BNX2_BC_STATE_RT_SET_WOLBNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87) bnx2.h 　
20837
 BNX2_BC_STATE_RT_OTHER_FWBNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88) bnx2.h 　
20838
 BNX2_BC_STATE_RT_GOING_D3BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89) bnx2.h 　
20839
 BNX2_BC_STATE_ERR_BAD_VERSIONBNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100) bnx2.h 　
20840
 BNX2_BC_STATE_ERR_BAD_BC2_CRCBNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200) bnx2.h 　
20841
 BNX2_BC_STATE_ERR_BC1_LOOPBNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300) bnx2.h 　
20842
 BNX2_BC_STATE_ERR_UNKNOWN_CMDBNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400) bnx2.h 　
20843
 BNX2_BC_STATE_ERR_DRV_DEADBNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500) bnx2.h 　
20844
 BNX2_BC_STATE_ERR_NO_RXPBNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600) bnx2.h 　
20845
 BNX2_BC_STATE_ERR_TOO_MANY_RBUFBNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700) bnx2.h 　
20846
 BNX2_BC_STATE_DEBUG_CMDBNX2_BC_STATE_DEBUG_CMD 0x1dc bnx2.h 　
20847
 BNX2_BC_STATE_BC_DBG_CMD_SIGNATBNX2_BC_STATE_BC_DBG_CMD_SIGNAT 0x42440000 bnx2.h 　
20848
 BNX2_BC_STATE_BC_DBG_CMD_SIGNATBNX2_BC_STATE_BC_DBG_CMD_SIGNAT 0xffff0000 bnx2.h 　
20849
 BNX2_BC_STATE_BC_DBG_CMD_LOOP_CBNX2_BC_STATE_BC_DBG_CMD_LOOP_C 0xffff bnx2.h 　
20850
 BNX2_BC_STATE_BC_DBG_CMD_LOOP_IBNX2_BC_STATE_BC_DBG_CMD_LOOP_I 0xffff bnx2.h 　
20851
 HOST_VIEW_SHMEM_BASEHOST_VIEW_SHMEM_BASE 0x167c00 bnx2.h 　
20852
 AUTONEG_DISABLEAUTONEG_DISABLE 0x00 bnx2.h 　
20853
 AUTONEG_ENABLEAUTONEG_ENABLE 0x01 bnx2.h 　
20854
 RX_OFFSETRX_OFFSET (sizeof(struct l2_fhdr) + 2) bnx2.h 　
20855
 RX_BUF_CNTRX_BUF_CNT 20 bnx2.h 　
20856
 RX_BUF_USE_SIZERX_BUF_USE_SIZE (ETH_MAX_MTU + ETH_HLEN + RX_OFFSET + 8) bnx2.h 　
20857
 RX_BUF_SIZERX_BUF_SIZE (L1_CACHE_ALIGN(RX_BUF_USE_SIZE + 8)) bnx2.h 　
20858
 PP_ChipIDPP_ChipID 0x0000 cs89x0.h offset 0h -> Corp -ID
20859
 PP_ISAIOBPP_ISAIOB 0x0020 cs89x0.h IO base address
20860
 PP_CS8900_ISAINTPP_CS8900_ISAINT 0x0022 cs89x0.h ISA interrupt select
20861
 PP_CS8920_ISAINTPP_CS8920_ISAINT 0x0370 cs89x0.h ISA interrupt select
20862
 PP_CS8900_ISADMAPP_CS8900_ISADMA 0x0024 cs89x0.h ISA Rec DMA channel
20863
 PP_CS8920_ISADMAPP_CS8920_ISADMA 0x0374 cs89x0.h ISA Rec DMA channel
20864
 PP_ISASOFPP_ISASOF 0x0026 cs89x0.h ISA DMA offset
20865
 PP_DmaFrameCntPP_DmaFrameCnt 0x0028 cs89x0.h ISA DMA Frame count
20866
 PP_DmaByteCntPP_DmaByteCnt 0x002A cs89x0.h ISA DMA Byte count
20867
 PP_CS8900_ISAMemBPP_CS8900_ISAMemB 0x002C cs89x0.h Memory base
20868
 PP_CS8920_ISAMemBPP_CS8920_ISAMemB 0x0348 cs89x0.h 　
20869
 PP_ISABootBasePP_ISABootBase 0x0030 cs89x0.h Boot Prom base
20870
 PP_ISABootMaskPP_ISABootMask 0x0034 cs89x0.h Boot Prom Mask
20871
 PP_EECMDPP_EECMD 0x0040 cs89x0.h NVR Interface Command register
20872
 PP_EEDataPP_EEData 0x0042 cs89x0.h NVR Interface Data Register
20873
 PP_DebugRegPP_DebugReg 0x0044 cs89x0.h Debug Register
20874
 PP_RxCFGPP_RxCFG 0x0102 cs89x0.h Rx Bus config
20875
 PP_RxCTLPP_RxCTL 0x0104 cs89x0.h Receive Control Register
20876
 PP_TxCFGPP_TxCFG 0x0106 cs89x0.h Transmit Config Register
20877
 PP_TxCMDPP_TxCMD 0x0108 cs89x0.h Transmit Command Register
20878
 PP_BufCFGPP_BufCFG 0x010A cs89x0.h Bus configuration Register
20879
 PP_LineCTLPP_LineCTL 0x0112 cs89x0.h Line Config Register
20880
 PP_SelfCTLPP_SelfCTL 0x0114 cs89x0.h Self Command Register
20881
 PP_BusCTLPP_BusCTL 0x0116 cs89x0.h ISA bus control Register
20882
 PP_TestCTLPP_TestCTL 0x0118 cs89x0.h Test Register
20883
 PP_AutoNegCTLPP_AutoNegCTL 0x011C cs89x0.h Auto Negotiation Ctrl
20884
 PP_ISQPP_ISQ 0x0120 cs89x0.h Interrupt Status
20885
 PP_RxEventPP_RxEvent 0x0124 cs89x0.h Rx Event Register
20886
 PP_TxEventPP_TxEvent 0x0128 cs89x0.h Tx Event Register
20887
 PP_BufEventPP_BufEvent 0x012C cs89x0.h Bus Event Register
20888
 PP_RxMissPP_RxMiss 0x0130 cs89x0.h Receive Miss Count
20889
 PP_TxColPP_TxCol 0x0132 cs89x0.h Transmit Collision Count
20890
 PP_LineSTPP_LineST 0x0134 cs89x0.h Line State Register
20891
 PP_SelfSTPP_SelfST 0x0136 cs89x0.h Self State register
20892
 PP_BusSTPP_BusST 0x0138 cs89x0.h Bus Status
20893
 PP_TDRPP_TDR 0x013C cs89x0.h Time Domain Reflectometry
20894
 PP_AutoNegSTPP_AutoNegST 0x013E cs89x0.h Auto Neg Status
20895
 PP_TxCommandPP_TxCommand 0x0144 cs89x0.h Tx Command
20896
 PP_TxLengthPP_TxLength 0x0146 cs89x0.h Tx Length
20897
 PP_LAFPP_LAF 0x0150 cs89x0.h Hash Table
20898
 PP_IAPP_IA 0x0158 cs89x0.h Physical Address Register
20899
 PP_RxStatusPP_RxStatus 0x0400 cs89x0.h Receive start of frame
20900
 PP_RxLengthPP_RxLength 0x0402 cs89x0.h Receive Length of frame
20901
 PP_RxFramePP_RxFrame 0x0404 cs89x0.h Receive frame pointer
20902
 PP_TxFramePP_TxFrame 0x0A00 cs89x0.h Transmit frame pointer
20903
 DEFAULTIOBASEDEFAULTIOBASE 0x0300 cs89x0.h 　
20904
 FIRST_IOFIRST_IO 0x020C cs89x0.h First I/O port to check
20905
 LAST_IOLAST_IO 0x037C cs89x0.h Last I/O port to check (+10h)
20906
 ADD_MASKADD_MASK 0x3000 cs89x0.h Mask it use of the ADD_PORT register
20907
 ADD_SIGADD_SIG 0x3000 cs89x0.h Expected ID signature
20908
 CHIP_EISA_ID_SIGCHIP_EISA_ID_SIG 0x630E cs89x0.h Product ID Code for Crystal Chip (CS8900 spec 4.3)
20909
 EISA_ID_SIGEISA_ID_SIG 0x4D24 cs89x0.h IBM
20910
 PART_NO_SIGPART_NO_SIG 0x1010 cs89x0.h IBM
20911
 MONGOOSE_BITMONGOOSE_BIT 0x0000 cs89x0.h IBM
20912
 EISA_ID_SIGEISA_ID_SIG 0x630E cs89x0.h PnP Vendor ID (same as chip id for Crystal board)
20913
 PART_NO_SIGPART_NO_SIG 0x4000 cs89x0.h ID code CS8920 board (PnP Vendor Product code)
20914
 MONGOOSE_BITMONGOOSE_BIT 0x2000 cs89x0.h PART_NO_SIG + MONGOOSE_BUT => ID of mongoose
20915
 PRODUCT_ID_ADDPRODUCT_ID_ADD 0x0002 cs89x0.h Address of product ID
20916
 REG_TYPE_MASKREG_TYPE_MASK 0x001F cs89x0.h 　
20917
 ERSE_WR_ENBLERSE_WR_ENBL 0x00F0 cs89x0.h 　
20918
 ERSE_WR_DISABLEERSE_WR_DISABLE 0x0000 cs89x0.h 　
20919
 RX_BUF_CFGRX_BUF_CFG 0x0003 cs89x0.h 　
20920
 RX_CONTROLRX_CONTROL 0x0005 cs89x0.h 　
20921
 TX_CFGTX_CFG 0x0007 cs89x0.h 　
20922
 TX_COMMANDTX_COMMAND 0x0009 cs89x0.h 　
20923
 BUF_CFGBUF_CFG 0x000B cs89x0.h 　
20924
 LINE_CONTROLLINE_CONTROL 0x0013 cs89x0.h 　
20925
 SELF_CONTROLSELF_CONTROL 0x0015 cs89x0.h 　
20926
 BUS_CONTROLBUS_CONTROL 0x0017 cs89x0.h 　
20927
 TEST_CONTROLTEST_CONTROL 0x0019 cs89x0.h 　
20928
 RX_EVENTRX_EVENT 0x0004 cs89x0.h 　
20929
 TX_EVENTTX_EVENT 0x0008 cs89x0.h 　
20930
 BUF_EVENTBUF_EVENT 0x000C cs89x0.h 　
20931
 RX_MISS_COUNTRX_MISS_COUNT 0x0010 cs89x0.h 　
20932
 TX_COL_COUNTTX_COL_COUNT 0x0012 cs89x0.h 　
20933
 LINE_STATUSLINE_STATUS 0x0014 cs89x0.h 　
20934
 SELF_STATUSSELF_STATUS 0x0016 cs89x0.h 　
20935
 BUS_STATUSBUS_STATUS 0x0018 cs89x0.h 　
20936
 TDRTDR 0x001C cs89x0.h 　
20937
 SKIP_1SKIP_1 0x0040 cs89x0.h 　
20938
 RX_STREAM_ENBLRX_STREAM_ENBL 0x0080 cs89x0.h 　
20939
 RX_OK_ENBLRX_OK_ENBL 0x0100 cs89x0.h 　
20940
 RX_DMA_ONLYRX_DMA_ONLY 0x0200 cs89x0.h 　
20941
 AUTO_RX_DMAAUTO_RX_DMA 0x0400 cs89x0.h 　
20942
 BUFFER_CRCBUFFER_CRC 0x0800 cs89x0.h 　
20943
 RX_CRC_ERROR_ENBLRX_CRC_ERROR_ENBL 0x1000 cs89x0.h 　
20944
 RX_RUNT_ENBLRX_RUNT_ENBL 0x2000 cs89x0.h 　
20945
 RX_EXTRA_DATA_ENBLRX_EXTRA_DATA_ENBL 0x4000 cs89x0.h 　
20946
 RX_IA_HASH_ACCEPTRX_IA_HASH_ACCEPT 0x0040 cs89x0.h 　
20947
 RX_PROM_ACCEPTRX_PROM_ACCEPT 0x0080 cs89x0.h 　
20948
 RX_OK_ACCEPTRX_OK_ACCEPT 0x0100 cs89x0.h 　
20949
 RX_MULTCAST_ACCEPTRX_MULTCAST_ACCEPT 0x0200 cs89x0.h 　
20950
 RX_IA_ACCEPTRX_IA_ACCEPT 0x0400 cs89x0.h 　
20951
 RX_BROADCAST_ACCEPTRX_BROADCAST_ACCEPT 0x0800 cs89x0.h 　
20952
 RX_BAD_CRC_ACCEPTRX_BAD_CRC_ACCEPT 0x1000 cs89x0.h 　
20953
 RX_RUNT_ACCEPTRX_RUNT_ACCEPT 0x2000 cs89x0.h 　
20954
 RX_EXTRA_DATA_ACCEPTRX_EXTRA_DATA_ACCEPT 0x4000 cs89x0.h 　
20955
 RX_ALL_ACCEPTRX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT) cs89x0.h 　
20956
 DEF_RX_ACCEPTDEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT) cs89x0.h 　
20957
 TX_LOST_CRS_ENBLTX_LOST_CRS_ENBL 0x0040 cs89x0.h 　
20958
 TX_SQE_ERROR_ENBLTX_SQE_ERROR_ENBL 0x0080 cs89x0.h 　
20959
 TX_OK_ENBLTX_OK_ENBL 0x0100 cs89x0.h 　
20960
 TX_LATE_COL_ENBLTX_LATE_COL_ENBL 0x0200 cs89x0.h 　
20961
 TX_JBR_ENBLTX_JBR_ENBL 0x0400 cs89x0.h 　
20962
 TX_ANY_COL_ENBLTX_ANY_COL_ENBL 0x0800 cs89x0.h 　
20963
 TX_16_COL_ENBLTX_16_COL_ENBL 0x8000 cs89x0.h 　
20964
 TX_START_4_BYTESTX_START_4_BYTES 0x0000 cs89x0.h 　
20965
 TX_START_64_BYTESTX_START_64_BYTES 0x0040 cs89x0.h 　
20966
 TX_START_128_BYTESTX_START_128_BYTES 0x0080 cs89x0.h 　
20967
 TX_START_ALL_BYTESTX_START_ALL_BYTES 0x00C0 cs89x0.h 　
20968
 TX_FORCETX_FORCE 0x0100 cs89x0.h 　
20969
 TX_ONE_COLTX_ONE_COL 0x0200 cs89x0.h 　
20970
 TX_TWO_PART_DEFF_DISABLETX_TWO_PART_DEFF_DISABLE 0x0400 cs89x0.h 　
20971
 TX_NO_CRCTX_NO_CRC 0x1000 cs89x0.h 　
20972
 TX_RUNTTX_RUNT 0x2000 cs89x0.h 　
20973
 GENERATE_SW_INTERRUPTGENERATE_SW_INTERRUPT 0x0040 cs89x0.h 　
20974
 RX_DMA_ENBLRX_DMA_ENBL 0x0080 cs89x0.h 　
20975
 READY_FOR_TX_ENBLREADY_FOR_TX_ENBL 0x0100 cs89x0.h 　
20976
 TX_UNDERRUN_ENBLTX_UNDERRUN_ENBL 0x0200 cs89x0.h 　
20977
 RX_MISS_ENBLRX_MISS_ENBL 0x0400 cs89x0.h 　
20978
 RX_128_BYTE_ENBLRX_128_BYTE_ENBL 0x0800 cs89x0.h 　
20979
 TX_COL_COUNT_OVRFLOW_ENBLTX_COL_COUNT_OVRFLOW_ENBL 0x1000 cs89x0.h 　
20980
 RX_MISS_COUNT_OVRFLOW_ENBLRX_MISS_COUNT_OVRFLOW_ENBL 0x2000 cs89x0.h 　
20981
 RX_DEST_MATCH_ENBLRX_DEST_MATCH_ENBL 0x8000 cs89x0.h 　
20982
 SERIAL_RX_ONSERIAL_RX_ON 0x0040 cs89x0.h 　
20983
 SERIAL_TX_ONSERIAL_TX_ON 0x0080 cs89x0.h 　
20984
 AUI_ONLYAUI_ONLY 0x0100 cs89x0.h 　
20985
 AUTO_AUI_10BASETAUTO_AUI_10BASET 0x0200 cs89x0.h 　
20986
 MODIFIED_BACKOFFMODIFIED_BACKOFF 0x0800 cs89x0.h 　
20987
 NO_AUTO_POLARITYNO_AUTO_POLARITY 0x1000 cs89x0.h 　
20988
 TWO_PART_DEFDISTWO_PART_DEFDIS 0x2000 cs89x0.h 　
20989
 LOW_RX_SQUELCHLOW_RX_SQUELCH 0x4000 cs89x0.h 　
20990
 POWER_ON_RESETPOWER_ON_RESET 0x0040 cs89x0.h 　
20991
 SW_STOPSW_STOP 0x0100 cs89x0.h 　
20992
 SLEEP_ONSLEEP_ON 0x0200 cs89x0.h 　
20993
 AUTO_WAKEUPAUTO_WAKEUP 0x0400 cs89x0.h 　
20994
 HCB0_ENBLHCB0_ENBL 0x1000 cs89x0.h 　
20995
 HCB1_ENBLHCB1_ENBL 0x2000 cs89x0.h 　
20996
 HCB0HCB0 0x4000 cs89x0.h 　
20997
 HCB1HCB1 0x8000 cs89x0.h 　
20998
 RESET_RX_DMARESET_RX_DMA 0x0040 cs89x0.h 　
20999
 MEMORY_ONMEMORY_ON 0x0400 cs89x0.h 　
21000
 DMA_BURST_MODEDMA_BURST_MODE 0x0800 cs89x0.h 　
21001
 IO_CHANNEL_READY_ONIO_CHANNEL_READY_ON 0x1000 cs89x0.h 　
21002
 RX_DMA_SIZE_64KRX_DMA_SIZE_64K 0x2000 cs89x0.h 　
21003
 ENABLE_IRQENABLE_IRQ 0x8000 cs89x0.h 　
21004
 LINK_OFFLINK_OFF 0x0080 cs89x0.h 　
21005
 ENDEC_LOOPBACKENDEC_LOOPBACK 0x0200 cs89x0.h 　
21006
 AUI_LOOPBACKAUI_LOOPBACK 0x0400 cs89x0.h 　
21007
 BACKOFF_OFFBACKOFF_OFF 0x0800 cs89x0.h 　
21008
 FAST_TESTFAST_TEST 0x8000 cs89x0.h 　
21009
 RX_IA_HASHEDRX_IA_HASHED 0x0040 cs89x0.h 　
21010
 RX_DRIBBLERX_DRIBBLE 0x0080 cs89x0.h 　
21011
 RX_OKRX_OK 0x0100 cs89x0.h 　
21012
 RX_HASHEDRX_HASHED 0x0200 cs89x0.h 　
21013
 RX_IARX_IA 0x0400 cs89x0.h 　
21014
 RX_BROADCASTRX_BROADCAST 0x0800 cs89x0.h 　
21015
 RX_CRC_ERRORRX_CRC_ERROR 0x1000 cs89x0.h 　
21016
 RX_RUNTRX_RUNT 0x2000 cs89x0.h 　
21017
 RX_EXTRA_DATARX_EXTRA_DATA 0x4000 cs89x0.h 　
21018
 HASH_INDEX_MASKHASH_INDEX_MASK 0x0FC00 cs89x0.h 　
21019
 TX_LOST_CRSTX_LOST_CRS 0x0040 cs89x0.h 　
21020
 TX_SQE_ERRORTX_SQE_ERROR 0x0080 cs89x0.h 　
21021
 TX_OKTX_OK 0x0100 cs89x0.h 　
21022
 TX_LATE_COLTX_LATE_COL 0x0200 cs89x0.h 　
21023
 TX_JBRTX_JBR 0x0400 cs89x0.h 　
21024
 TX_16_COLTX_16_COL 0x8000 cs89x0.h 　
21025
 TX_SEND_OK_BITSTX_SEND_OK_BITS (TX_OK|TX_LOST_CRS) cs89x0.h 　
21026
 TX_COL_COUNT_MASKTX_COL_COUNT_MASK 0x7800 cs89x0.h 　
21027
 SW_INTERRUPTSW_INTERRUPT 0x0040 cs89x0.h 　
21028
 RX_DMARX_DMA 0x0080 cs89x0.h 　
21029
 READY_FOR_TXREADY_FOR_TX 0x0100 cs89x0.h 　
21030
 TX_UNDERRUNTX_UNDERRUN 0x0200 cs89x0.h 　
21031
 RX_MISSRX_MISS 0x0400 cs89x0.h 　
21032
 RX_128_BYTERX_128_BYTE 0x0800 cs89x0.h 　
21033
 TX_COL_OVRFLWTX_COL_OVRFLW 0x1000 cs89x0.h 　
21034
 RX_MISS_OVRFLWRX_MISS_OVRFLW 0x2000 cs89x0.h 　
21035
 RX_DEST_MATCHRX_DEST_MATCH 0x8000 cs89x0.h 　
21036
 LINK_OKLINK_OK 0x0080 cs89x0.h 　
21037
 AUI_ONAUI_ON 0x0100 cs89x0.h 　
21038
 TENBASET_ONTENBASET_ON 0x0200 cs89x0.h 　
21039
 POLARITY_OKPOLARITY_OK 0x1000 cs89x0.h 　
21040
 CRS_OKCRS_OK 0x4000 cs89x0.h 　
21041
 ACTIVE_33VACTIVE_33V 0x0040 cs89x0.h 　
21042
 INIT_DONEINIT_DONE 0x0080 cs89x0.h 　
21043
 SI_BUSYSI_BUSY 0x0100 cs89x0.h 　
21044
 EEPROM_PRESENTEEPROM_PRESENT 0x0200 cs89x0.h 　
21045
 EEPROM_OKEEPROM_OK 0x0400 cs89x0.h 　
21046
 EL_PRESENTEL_PRESENT 0x0800 cs89x0.h 　
21047
 EE_SIZE_64EE_SIZE_64 0x1000 cs89x0.h 　
21048
 TX_BID_ERRORTX_BID_ERROR 0x0080 cs89x0.h 　
21049
 READY_FOR_TX_NOWREADY_FOR_TX_NOW 0x0100 cs89x0.h 　
21050
 RE_NEG_NOWRE_NEG_NOW 0x0040 cs89x0.h 　
21051
 ALLOW_FDXALLOW_FDX 0x0080 cs89x0.h 　
21052
 AUTO_NEG_ENABLEAUTO_NEG_ENABLE 0x0100 cs89x0.h 　
21053
 NLP_ENABLENLP_ENABLE 0x0200 cs89x0.h 　
21054
 FORCE_FDXFORCE_FDX 0x8000 cs89x0.h 　
21055
 AUTO_NEG_BITSAUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE) cs89x0.h 　
21056
 AUTO_NEG_MASKAUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW) cs89x0.h 　
21057
 AUTO_NEG_BUSYAUTO_NEG_BUSY 0x0080 cs89x0.h 　
21058
 FLP_LINKFLP_LINK 0x0100 cs89x0.h 　
21059
 FLP_LINK_GOODFLP_LINK_GOOD 0x0800 cs89x0.h 　
21060
 LINK_FAULTLINK_FAULT 0x1000 cs89x0.h 　
21061
 HDX_ACTIVEHDX_ACTIVE 0x4000 cs89x0.h 　
21062
 FDX_ACTIVEFDX_ACTIVE 0x8000 cs89x0.h 　
21063
 ISQ_RECEIVER_EVENTISQ_RECEIVER_EVENT 0x04 cs89x0.h 　
21064
 ISQ_TRANSMITTER_EVENTISQ_TRANSMITTER_EVENT 0x08 cs89x0.h 　
21065
 ISQ_BUFFER_EVENTISQ_BUFFER_EVENT 0x0c cs89x0.h 　
21066
 ISQ_RX_MISS_EVENTISQ_RX_MISS_EVENT 0x10 cs89x0.h 　
21067
 ISQ_TX_COL_EVENTISQ_TX_COL_EVENT 0x12 cs89x0.h 　
21068
 ISQ_EVENT_MASKISQ_EVENT_MASK 0x003F cs89x0.h ISQ mask to find out type of event
21069
 ISQ_HISTISQ_HIST 16 cs89x0.h small history buffer
21070
 AUTOINCREMENTAUTOINCREMENT 0x8000 cs89x0.h Bit mask to set bit-15 for autoincrement
21071
 TXRXBUFSIZETXRXBUFSIZE 0x0600 cs89x0.h 　
21072
 RXDMABUFSIZERXDMABUFSIZE 0x8000 cs89x0.h 　
21073
 RXDMASIZERXDMASIZE 0x4000 cs89x0.h 　
21074
 TXRX_LENGTH_MASKTXRX_LENGTH_MASK 0x07FF cs89x0.h 　
21075
 RCV_WITH_RXONRCV_WITH_RXON 1 cs89x0.h Set SerRx ON
21076
 RCV_COUNTSRCV_COUNTS 2 cs89x0.h Use Framecnt1
21077
 RCV_PONGRCV_PONG 4 cs89x0.h Pong respondent
21078
 RCV_DONGRCV_DONG 8 cs89x0.h Dong operation
21079
 RCV_POLLINGRCV_POLLING 0x10 cs89x0.h Poll RxEvent
21080
 RCV_ISQRCV_ISQ 0x20 cs89x0.h Use ISQ, int
21081
 RCV_AUTO_DMARCV_AUTO_DMA 0x100 cs89x0.h Set AutoRxDMAE
21082
 RCV_DMARCV_DMA 0x200 cs89x0.h Set RxDMA only
21083
 RCV_DMA_ALLRCV_DMA_ALL 0x400 cs89x0.h Copy all DMA'ed
21084
 RCV_FIXED_DATARCV_FIXED_DATA 0x800 cs89x0.h Every frame same
21085
 RCV_IORCV_IO 0x1000 cs89x0.h Use ISA IO only
21086
 RCV_MEMORYRCV_MEMORY 0x2000 cs89x0.h Use ISA Memory
21087
 RAM_SIZERAM_SIZE 0x1000 cs89x0.h The card has 4k bytes or RAM
21088
 PKT_STARTPKT_START PP_TxFrame cs89x0.h Start of packet RAM
21089
 RX_FRAME_PORTRX_FRAME_PORT 0x0000 cs89x0.h 　
21090
 TX_FRAME_PORTTX_FRAME_PORT RX_FRAME_PORT cs89x0.h 　
21091
 TX_CMD_PORTTX_CMD_PORT 0x0004 cs89x0.h 　
21092
 TX_NOWTX_NOW 0x0000 cs89x0.h Tx packet after 5 bytes copied
21093
 TX_AFTER_381TX_AFTER_381 0x0020 cs89x0.h Tx packet after 381 bytes copied
21094
 TX_AFTER_ALLTX_AFTER_ALL 0x00C0 cs89x0.h Tx packet after all bytes copied
21095
 TX_LEN_PORTTX_LEN_PORT 0x0006 cs89x0.h 　
21096
 ISQ_PORTISQ_PORT 0x0008 cs89x0.h 　
21097
 ADD_PORTADD_PORT 0x000A cs89x0.h 　
21098
 DATA_PORTDATA_PORT 0x000C cs89x0.h 　
21099
 EEPROM_WRITE_ENEEPROM_WRITE_EN 0x00F0 cs89x0.h 　
21100
 EEPROM_WRITE_DISEEPROM_WRITE_DIS 0x0000 cs89x0.h 　
21101
 EEPROM_WRITE_CMDEEPROM_WRITE_CMD 0x0100 cs89x0.h 　
21102
 EEPROM_READ_CMDEEPROM_READ_CMD 0x0200 cs89x0.h 　
21103
 RBUF_EVENT_LOWRBUF_EVENT_LOW 0 cs89x0.h Low byte of RxEvent - status of received frame
21104
 RBUF_EVENT_HIGHRBUF_EVENT_HIGH 1 cs89x0.h High byte of RxEvent - status of received frame
21105
 RBUF_LEN_LOWRBUF_LEN_LOW 2 cs89x0.h Length of received data - low byte
21106
 RBUF_LEN_HIRBUF_LEN_HI 3 cs89x0.h Length of received data - high byte
21107
 RBUF_HEAD_LENRBUF_HEAD_LEN 4 cs89x0.h Length of this header
21108
 CHIP_READCHIP_READ 0x1 cs89x0.h Used to mark state of the repins code (chip or dma)
21109
 DMA_READDMA_READ 0x2 cs89x0.h Used to mark state of the repins code (chip or dma)
21110
 BIOS_START_SEGBIOS_START_SEG 0x00000 cs89x0.h 　
21111
 BIOS_OFFSET_INCBIOS_OFFSET_INC 0x0010 cs89x0.h 　
21112
 BIOS_START_SEGBIOS_START_SEG 0x0c000 cs89x0.h 　
21113
 BIOS_OFFSET_INCBIOS_OFFSET_INC 0x0200 cs89x0.h 　
21114
 BIOS_LAST_OFFSETBIOS_LAST_OFFSET 0x0fc00 cs89x0.h 　
21115
 ISA_CNF_OFFSETISA_CNF_OFFSET 0x6 cs89x0.h 　
21116
 TX_CTL_OFFSETTX_CTL_OFFSET (ISA_CNF_OFFSET + 8) cs89x0.h 8900 eeprom
21117
 AUTO_NEG_CNF_OFFSETAUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) cs89x0.h 8920 eeprom
21118
 EE_FORCE_FDXEE_FORCE_FDX 0x8000 cs89x0.h 　
21119
 EE_NLP_ENABLEEE_NLP_ENABLE 0x0200 cs89x0.h 　
21120
 EE_AUTO_NEG_ENABLEEE_AUTO_NEG_ENABLE 0x0100 cs89x0.h 　
21121
 EE_ALLOW_FDXEE_ALLOW_FDX 0x0080 cs89x0.h 　
21122
 EE_AUTO_NEG_CNF_MASKEE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX) cs89x0.h 　
21123
 IMM_BITIMM_BIT 0x0040 cs89x0.h ignore missing media
21124
 ADAPTER_CNF_OFFSETADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2) cs89x0.h 　
21125
 A_CNF_10B_TA_CNF_10B_T 0x0001 cs89x0.h 　
21126
 A_CNF_AUIA_CNF_AUI 0x0002 cs89x0.h 　
21127
 A_CNF_10B_2A_CNF_10B_2 0x0004 cs89x0.h 　
21128
 A_CNF_MEDIA_TYPEA_CNF_MEDIA_TYPE 0x0060 cs89x0.h 　
21129
 A_CNF_MEDIA_AUTOA_CNF_MEDIA_AUTO 0x0000 cs89x0.h 　
21130
 A_CNF_MEDIA_10B_TA_CNF_MEDIA_10B_T 0x0020 cs89x0.h 　
21131
 A_CNF_MEDIA_AUIA_CNF_MEDIA_AUI 0x0040 cs89x0.h 　
21132
 A_CNF_MEDIA_10B_2A_CNF_MEDIA_10B_2 0x0060 cs89x0.h 　
21133
 A_CNF_DC_DC_POLARITYA_CNF_DC_DC_POLARITY 0x0080 cs89x0.h 　
21134
 A_CNF_NO_AUTO_POLARITYA_CNF_NO_AUTO_POLARITY 0x2000 cs89x0.h 　
21135
 A_CNF_LOW_RX_SQUELCHA_CNF_LOW_RX_SQUELCH 0x4000 cs89x0.h 　
21136
 A_CNF_EXTND_10B_2A_CNF_EXTND_10B_2 0x8000 cs89x0.h 　
21137
 PACKET_PAGE_OFFSETPACKET_PAGE_OFFSET 0x8 cs89x0.h 　
21138
 INT_NO_MASKINT_NO_MASK 0x000F cs89x0.h 　
21139
 DMA_NO_MASKDMA_NO_MASK 0x0070 cs89x0.h 　
21140
 ISA_DMA_SIZEISA_DMA_SIZE 0x0200 cs89x0.h 　
21141
 ISA_AUTO_RxDMAISA_AUTO_RxDMA 0x0400 cs89x0.h 　
21142
 ISA_RxDMAISA_RxDMA 0x0800 cs89x0.h 　
21143
 DMA_BURSTDMA_BURST 0x1000 cs89x0.h 　
21144
 STREAM_TRANSFERSTREAM_TRANSFER 0x2000 cs89x0.h 　
21145
 ANY_ISA_DMAANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA) cs89x0.h 　
21146
 DMA_BASEDMA_BASE 0x00 cs89x0.h DMA controller base
21147
 DMA_BASE_2DMA_BASE_2 0x0C0 cs89x0.h DMA controller base
21148
 DMA_STATDMA_STAT 0x0D0 cs89x0.h DMA controller status register
21149
 DMA_MASKDMA_MASK 0x0D4 cs89x0.h DMA controller mask register
21150
 DMA_MODEDMA_MODE 0x0D6 cs89x0.h DMA controller mode register
21151
 DMA_RESETFFDMA_RESETFF 0x0D8 cs89x0.h DMA controller first/last flip flop
21152
 DMA_DISABLEDMA_DISABLE 0x04 cs89x0.h Disable channel n
21153
 DMA_ENABLEDMA_ENABLE 0x00 cs89x0.h Enable channel n
21154
 DMA_RX_MODEDMA_RX_MODE 0x14 cs89x0.h 　
21155
 DMA_TX_MODEDMA_TX_MODE 0x18 cs89x0.h 　
21156
 DMA_SIZEDMA_SIZE (16*1024) cs89x0.h Size of dma buffer - 16k
21157
 CS8900CS8900 0x0000 cs89x0.h 　
21158
 CS8920CS8920 0x4000 cs89x0.h 　
21159
 CS8920MCS8920M 0x6000 cs89x0.h 　
21160
 REVISON_BITSREVISON_BITS 0x1F00 cs89x0.h 　
21161
 EEVER_NUMBEREEVER_NUMBER 0x12 cs89x0.h 　
21162
 CHKSUM_LENCHKSUM_LEN 0x14 cs89x0.h 　
21163
 CHKSUM_VALCHKSUM_VAL 0x0000 cs89x0.h 　
21164
 START_EEPROM_DATASTART_EEPROM_DATA 0x001c cs89x0.h Offset into eeprom for start of data
21165
 IRQ_MAP_EEPROM_DATAIRQ_MAP_EEPROM_DATA 0x0046 cs89x0.h Offset into eeprom for the IRQ map
21166
 IRQ_MAP_LENIRQ_MAP_LEN 0x0004 cs89x0.h No of bytes to read for the IRQ map
21167
 PNP_IRQ_FRMTPNP_IRQ_FRMT 0x0022 cs89x0.h PNP small item IRQ format
21168
 CS8900_IRQ_MAPCS8900_IRQ_MAP 0x1c20 cs89x0.h This IRQ map is fixed
21169
 CS8920_NO_INTSCS8920_NO_INTS 0x0F cs89x0.h Max CS8920 interrupt select #
21170
 PNP_ADD_PORTPNP_ADD_PORT 0x0279 cs89x0.h 　
21171
 PNP_WRITE_PORTPNP_WRITE_PORT 0x0A79 cs89x0.h 　
21172
 GET_PNP_ISA_STRUCTGET_PNP_ISA_STRUCT 0x40 cs89x0.h 　
21173
 PNP_ISA_STRUCT_LENPNP_ISA_STRUCT_LEN 0x06 cs89x0.h 　
21174
 PNP_CSN_CNT_OFFPNP_CSN_CNT_OFF 0x01 cs89x0.h 　
21175
 PNP_RD_PORT_OFFPNP_RD_PORT_OFF 0x02 cs89x0.h 　
21176
 PNP_FUNCTION_OKPNP_FUNCTION_OK 0x00 cs89x0.h 　
21177
 PNP_WAKEPNP_WAKE 0x03 cs89x0.h 　
21178
 PNP_RSRC_DATAPNP_RSRC_DATA 0x04 cs89x0.h 　
21179
 PNP_RSRC_READYPNP_RSRC_READY 0x01 cs89x0.h 　
21180
 PNP_STATUSPNP_STATUS 0x05 cs89x0.h 　
21181
 PNP_ACTIVATEPNP_ACTIVATE 0x30 cs89x0.h 　
21182
 PNP_CNF_IO_HPNP_CNF_IO_H 0x60 cs89x0.h 　
21183
 PNP_CNF_IO_LPNP_CNF_IO_L 0x61 cs89x0.h 　
21184
 PNP_CNF_INTPNP_CNF_INT 0x70 cs89x0.h 　
21185
 PNP_CNF_DMAPNP_CNF_DMA 0x74 cs89x0.h 　
21186
 PNP_CNF_MEMPNP_CNF_MEM 0x48 cs89x0.h 　
21187
 BIT0BIT0 1 cs89x0.h 　
21188
 BIT15BIT15 0x8000 cs89x0.h 　
21189
 CONGENBCONGENB 0 eepro100.h Enable congestion control in the DP83840.
21190
 TX_FIFOTX_FIFO 8 eepro100.h Tx FIFO threshold in 4 byte units, 0-15
21191
 RX_FIFORX_FIFO 8 eepro100.h Rx FIFO threshold, default 32 bytes.
21192
 TX_DMA_COUNTTX_DMA_COUNT 0 eepro100.h Tx DMA burst length, 0-127, default 0.
21193
 RX_DMA_COUNTRX_DMA_COUNT 0 eepro100.h Rx DMA length, 0 means no preemption.
21194
 CU_CMD_TIMEOUTCU_CMD_TIMEOUT 1000 eepro100.h CU command accept timeout in microseconds
21195
 LINK_CHECK_PERIODLINK_CHECK_PERIOD 1000 eepro100.h # of poll() calls between link checks
21196
 RFD_PACKET_LENRFD_PACKET_LEN 1518 eepro100.h 　
21197
 RFD_IOB_LENRFD_IOB_LEN 1536 eepro100.h 　
21198
 RFD_HEADER_LENRFD_HEADER_LEN 16 eepro100.h 　
21199
 CB_ALIGNCB_ALIGN 2 eepro100.h Alignment of command blocks
21200
 RFD_COUNTRFD_COUNT 4 eepro100.h 　
21201
 TCB_COUNTTCB_COUNT 4 eepro100.h 　
21202
 RX_RING_BYTESRX_RING_BYTES ( RFD_COUNT * sizeof ( struct ifec_rfd ) ) eepro100.h 　
21203
 TX_RING_BYTESTX_RING_BYTES ( TCB_COUNT * sizeof ( struct ifec_tcb ) ) eepro100.h 　
21204
 EEPROM_ADDR_MAC_0EEPROM_ADDR_MAC_0 0 eepro100.h 　
21205
 EEPROM_ADDR_MDIO_REGISTEREEPROM_ADDR_MDIO_REGISTER 6 eepro100.h 　
21206
 EE_SHIFT_CLKEE_SHIFT_CLK 0x01 eepro100.h EEPROM shift clock.
21207
 EE_CSEE_CS 0x02 eepro100.h EEPROM chip select.
21208
 EE_DATA_WRITEEE_DATA_WRITE 0x04 eepro100.h EEPROM chip data in.
21209
 EE_DATA_READEE_DATA_READ 0x08 eepro100.h EEPROM chip data out.
21210
 EE_ENBEE_ENB ( 0x4800 | EE_CS ) eepro100.h 　
21211
 PCI_VENDOR_SMCPCI_VENDOR_SMC 0x10B8 epic100.h 　
21212
 PCI_DEVICE_SMC_EPIC100PCI_DEVICE_SMC_EPIC100 0x0005 epic100.h 　
21213
 PCI_DEVICE_ID_NONEPCI_DEVICE_ID_NONE 0xFFFF epic100.h 　
21214
 CR_STOP_RXCR_STOP_RX (0x00000001) epic100.h 　
21215
 CR_START_RXCR_START_RX (0x00000002) epic100.h 　
21216
 CR_QUEUE_TXCR_QUEUE_TX (0x00000004) epic100.h 　
21217
 CR_QUEUE_RXCR_QUEUE_RX (0x00000008) epic100.h 　
21218
 CR_NEXTFRAMECR_NEXTFRAME (0x00000010) epic100.h 　
21219
 CR_STOP_TX_DMACR_STOP_TX_DMA (0x00000020) epic100.h 　
21220
 CR_STOP_RX_DMACR_STOP_RX_DMA (0x00000040) epic100.h 　
21221
 CR_TX_UGOCR_TX_UGO (0x00000080) epic100.h 　
21222
 INTR_RX_THR_STAINTR_RX_THR_STA (0x00400000) epic100.h rx copy threshold status NI
21223
 INTR_RX_BUFF_EMPTYINTR_RX_BUFF_EMPTY (0x00200000) epic100.h rx buffers empty. NI
21224
 INTR_TX_IN_PROGINTR_TX_IN_PROG (0x00100000) epic100.h tx copy in progess. NI
21225
 INTR_RX_IN_PROGINTR_RX_IN_PROG (0x00080000) epic100.h rx copy in progress. NI
21226
 INTR_TXIDLEINTR_TXIDLE (0x00040000) epic100.h tx idle. NI
21227
 INTR_RXIDLEINTR_RXIDLE (0x00020000) epic100.h rx idle. NI
21228
 INTR_INTR_ACTIVEINTR_INTR_ACTIVE (0x00010000) epic100.h Interrupt active. NI
21229
 INTR_RX_STATUS_OKINTR_RX_STATUS_OK (0x00008000) epic100.h rx status valid. NI
21230
 INTR_PCI_TGT_ABTINTR_PCI_TGT_ABT (0x00004000) epic100.h PCI Target abort
21231
 INTR_PCI_MASTER_ABTINTR_PCI_MASTER_ABT (0x00002000) epic100.h PCI Master abort
21232
 INTR_PCI_PARITY_ERRINTR_PCI_PARITY_ERR (0x00001000) epic100.h PCI adress parity error
21233
 INTR_PCI_DATA_ERRINTR_PCI_DATA_ERR (0x00000800) epic100.h PCI data parity error
21234
 INTR_RX_THR_CROSSEDINTR_RX_THR_CROSSED (0x00000400) epic100.h rx copy threshold crossed
21235
 INTR_CNTFULLINTR_CNTFULL (0x00000200) epic100.h Counter overflow
21236
 INTR_TXUNDERRUNINTR_TXUNDERRUN (0x00000100) epic100.h tx underrun.
21237
 INTR_TXEMPTYINTR_TXEMPTY (0x00000080) epic100.h tx queue empty
21238
 INTR_TX_CH_COMPLETEINTR_TX_CH_COMPLETE (0x00000040) epic100.h tx chain complete
21239
 INTR_TXDONEINTR_TXDONE (0x00000020) epic100.h tx complete (w or w/o err)
21240
 INTR_RXERRORINTR_RXERROR (0x00000010) epic100.h rx error (CRC)
21241
 INTR_RXOVERFLOWINTR_RXOVERFLOW (0x00000008) epic100.h rx buffer overflow
21242
 INTR_RX_QUEUE_EMPTYINTR_RX_QUEUE_EMPTY (0x00000004) epic100.h rx queue empty.
21243
 INTR_RXHEADERINTR_RXHEADER (0x00000002) epic100.h header copy complete
21244
 INTR_RXDONEINTR_RXDONE (0x00000001) epic100.h Receive copy complete
21245
 INTR_CLEARINTRINTR_CLEARINTR (0x00007FFF) epic100.h 　
21246
 INTR_VALIDBITSINTR_VALIDBITS (0x007FFFFF) epic100.h 　
21247
 INTR_DISABLEINTR_DISABLE (0x00000000) epic100.h 　
21248
 INTR_CLEARERRSINTR_CLEARERRS (0x00007F18) epic100.h 　
21249
 INTR_ABNINTRINTR_ABNINTR (INTR_CNTFULL | INTR_TXUNDERRUN | INTR_RXOVERFLOW) epic100.h 　
21250
 GC_SOFT_RESETGC_SOFT_RESET (0x00000001) epic100.h 　
21251
 GC_INTR_ENABLEGC_INTR_ENABLE (0x00000002) epic100.h 　
21252
 GC_SOFT_INTRGC_SOFT_INTR (0x00000004) epic100.h 　
21253
 GC_POWER_DOWNGC_POWER_DOWN (0x00000008) epic100.h 　
21254
 GC_ONE_COPYGC_ONE_COPY (0x00000010) epic100.h 　
21255
 GC_BIG_ENDIANGC_BIG_ENDIAN (0x00000020) epic100.h 　
21256
 GC_RX_PREEMPT_TXGC_RX_PREEMPT_TX (0x00000040) epic100.h 　
21257
 GC_TX_PREEMPT_RXGC_TX_PREEMPT_RX (0x00000080) epic100.h 　
21258
 GC_RX_FIFO_THR_32GC_RX_FIFO_THR_32 (0x00000000) epic100.h 　
21259
 GC_RX_FIFO_THR_64GC_RX_FIFO_THR_64 (0x00000100) epic100.h 　
21260
 GC_RX_FIFO_THR_96GC_RX_FIFO_THR_96 (0x00000200) epic100.h 　
21261
 GC_RX_FIFO_THR_128GC_RX_FIFO_THR_128 (0x00000300) epic100.h 　
21262
 GC_MRC_MEM_READGC_MRC_MEM_READ (0x00000000) epic100.h 　
21263
 GC_MRC_READ_MULTGC_MRC_READ_MULT (0x00000400) epic100.h 　
21264
 GC_MRC_READ_LINEGC_MRC_READ_LINE (0x00000800) epic100.h 　
21265
 GC_SOFTBIT0GC_SOFTBIT0 (0x00001000) epic100.h 　
21266
 GC_SOFTBIT1GC_SOFTBIT1 (0x00002000) epic100.h 　
21267
 GC_RESET_PHYGC_RESET_PHY (0x00004000) epic100.h 　
21268
 RC_SAVE_ERRORED_PKTRC_SAVE_ERRORED_PKT (0x00000001) epic100.h 　
21269
 RC_SAVE_RUNT_FRAMESRC_SAVE_RUNT_FRAMES (0x00000002) epic100.h 　
21270
 RC_RCV_BROADCASTRC_RCV_BROADCAST (0x00000004) epic100.h 　
21271
 RC_RCV_MULTICASTRC_RCV_MULTICAST (0x00000008) epic100.h 　
21272
 RC_RCV_INVERSE_PKTRC_RCV_INVERSE_PKT (0x00000010) epic100.h 　
21273
 RC_PROMISCUOUS_MODERC_PROMISCUOUS_MODE (0x00000020) epic100.h 　
21274
 RC_MONITOR_MODERC_MONITOR_MODE (0x00000040) epic100.h 　
21275
 RC_EARLY_RCV_ENABLERC_EARLY_RCV_ENABLE (0x00000080) epic100.h 　
21276
 RD_FRAGLISTRD_FRAGLIST (0x0001) epic100.h Desc points to a fragment list
21277
 RD_LLFORMRD_LLFORM (0x0002) epic100.h Frag list format
21278
 RD_HDR_CPYRD_HDR_CPY (0x0004) epic100.h Desc used for header copy
21279
 TC_EARLY_TX_ENABLETC_EARLY_TX_ENABLE (0x00000001) epic100.h 　
21280
 TC_LM_NORMALTC_LM_NORMAL (0x00000000) epic100.h 　
21281
 TC_LM_INTERNALTC_LM_INTERNAL (0x00000002) epic100.h 　
21282
 TC_LM_EXTERNALTC_LM_EXTERNAL (0x00000004) epic100.h 　
21283
 TC_LM_FULL_DPXTC_LM_FULL_DPX (0x00000006) epic100.h 　
21284
 TX_SLOT_TIMETX_SLOT_TIME (0x00000078) epic100.h 　
21285
 TX_FIFO_THRESHTX_FIFO_THRESH 128 epic100.h Rounded down to 4 byte units.
21286
 RRING_PKT_INTACTRRING_PKT_INTACT (0x0001) epic100.h 　
21287
 RRING_ALIGN_ERRRRING_ALIGN_ERR (0x0002) epic100.h 　
21288
 RRING_CRC_ERRRRING_CRC_ERR (0x0004) epic100.h 　
21289
 RRING_MISSED_PKTRRING_MISSED_PKT (0x0008) epic100.h 　
21290
 RRING_MULTICASTRRING_MULTICAST (0x0010) epic100.h 　
21291
 RRING_BROADCASTRRING_BROADCAST (0x0020) epic100.h 　
21292
 RRING_RECEIVER_DISABLERRING_RECEIVER_DISABLE (0x0040) epic100.h 　
21293
 RRING_STATUS_VALIDRRING_STATUS_VALID (0x1000) epic100.h 　
21294
 RRING_FRAGLIST_ERRRRING_FRAGLIST_ERR (0x2000) epic100.h 　
21295
 RRING_HDR_COPIEDRRING_HDR_COPIED (0x4000) epic100.h 　
21296
 RRING_OWNRRING_OWN (0x8000) epic100.h 　
21297
 RRING_ERRORRRING_ERROR (RRING_ALIGN_ERR|RRING_CRC_ERR) epic100.h 　
21298
 TRING_PKT_INTACTTRING_PKT_INTACT (0x0001) epic100.h pkt transmitted.
21299
 TRING_PKT_NONDEFERTRING_PKT_NONDEFER (0x0002) epic100.h pkt xmitted w/o deferring
21300
 TRING_COLLTRING_COLL (0x0004) epic100.h pkt xmitted w collisions
21301
 TRING_CARRTRING_CARR (0x0008) epic100.h carrier sense lost
21302
 TRING_UNDERRUNTRING_UNDERRUN (0x0010) epic100.h DMA underrun
21303
 TRING_HB_COLLTRING_HB_COLL (0x0020) epic100.h Collision detect Heartbeat
21304
 TRING_WIN_COLLTRING_WIN_COLL (0x0040) epic100.h out of window collision
21305
 TRING_DEFERREDTRING_DEFERRED (0x0080) epic100.h Deferring
21306
 TRING_COLL_COUNTTRING_COLL_COUNT (0x0F00) epic100.h collision counter (mask)
21307
 TRING_COLL_EXCESSTRING_COLL_EXCESS (0x1000) epic100.h tx aborted: excessive colls
21308
 TRING_OWNTRING_OWN (0x8000) epic100.h desc ownership bit
21309
 TRING_ABORTTRING_ABORT (TRING_COLL_EXCESS|TRING_WIN_COLL|TRING_UNDERRUN) epic100.h 　
21310
 TRING_ERRORTRING_ERROR (TRING_DEFERRED|TRING_WIN_COLL|TRING_UNDERRUN|TRING_CARR ) epic100.h |TRING_COLL
21311
 TD_FRAGLISTTD_FRAGLIST (0x0001) epic100.h Desc points to a fragment list
21312
 TD_LLFORMTD_LLFORM (0x0002) epic100.h Frag list format
21313
 TD_IAFTD_IAF (0x0004) epic100.h Generate Interrupt after tx
21314
 TD_NOCRCTD_NOCRC (0x0008) epic100.h No CRC generated
21315
 TD_LASTDESCTD_LASTDESC (0x0010) epic100.h Last desc for this frame
21316
 EFAB_DUMMY_FIELD_LBNEFAB_DUMMY_FIELD_LBN 0 etherfabric.h 　
21317
 EFAB_DUMMY_FIELD_WIDTHEFAB_DUMMY_FIELD_WIDTH 0 etherfabric.h 　
21318
 EFAB_DWORD_0_LBNEFAB_DWORD_0_LBN 0 etherfabric.h 　
21319
 EFAB_DWORD_0_WIDTHEFAB_DWORD_0_WIDTH 32 etherfabric.h 　
21320
 EFAB_DWORD_1_LBNEFAB_DWORD_1_LBN 32 etherfabric.h 　
21321
 EFAB_DWORD_1_WIDTHEFAB_DWORD_1_WIDTH 32 etherfabric.h 　
21322
 EFAB_DWORD_2_LBNEFAB_DWORD_2_LBN 64 etherfabric.h 　
21323
 EFAB_DWORD_2_WIDTHEFAB_DWORD_2_WIDTH 32 etherfabric.h 　
21324
 EFAB_DWORD_3_LBNEFAB_DWORD_3_LBN 96 etherfabric.h 　
21325
 EFAB_DWORD_3_WIDTHEFAB_DWORD_3_WIDTH 32 etherfabric.h 　
21326
 EFAB_DWORD_FMTEFAB_DWORD_FMT "%08x" etherfabric.h 　
21327
 EFAB_QWORD_FMTEFAB_QWORD_FMT "%08x:%08x" etherfabric.h 　
21328
 EFAB_OWORD_FMTEFAB_OWORD_FMT "%08x:%08x:%08x:%08x" etherfabric.h 　
21329
 EFAB_OWORD_FIELDEFAB_OWORD_FIELD EFAB_OWORD_FIELD64 etherfabric.h 　
21330
 EFAB_QWORD_FIELDEFAB_QWORD_FIELD EFAB_QWORD_FIELD64 etherfabric.h 　
21331
 EFAB_OWORD_IS_ZEROEFAB_OWORD_IS_ZERO EFAB_OWORD_IS_ZERO64 etherfabric.h 　
21332
 EFAB_QWORD_IS_ZEROEFAB_QWORD_IS_ZERO EFAB_QWORD_IS_ZERO64 etherfabric.h 　
21333
 EFAB_OWORD_IS_ALL_ONESEFAB_OWORD_IS_ALL_ONES EFAB_OWORD_IS_ALL_ONES64 etherfabric.h 　
21334
 EFAB_QWORD_IS_ALL_ONESEFAB_QWORD_IS_ALL_ONES EFAB_QWORD_IS_ALL_ONES64 etherfabric.h 　
21335
 EFAB_OWORD_FIELDEFAB_OWORD_FIELD EFAB_OWORD_FIELD32 etherfabric.h 　
21336
 EFAB_QWORD_FIELDEFAB_QWORD_FIELD EFAB_QWORD_FIELD32 etherfabric.h 　
21337
 EFAB_OWORD_IS_ZEROEFAB_OWORD_IS_ZERO EFAB_OWORD_IS_ZERO32 etherfabric.h 　
21338
 EFAB_QWORD_IS_ZEROEFAB_QWORD_IS_ZERO EFAB_QWORD_IS_ZERO32 etherfabric.h 　
21339
 EFAB_OWORD_IS_ALL_ONESEFAB_OWORD_IS_ALL_ONES EFAB_OWORD_IS_ALL_ONES32 etherfabric.h 　
21340
 EFAB_QWORD_IS_ALL_ONESEFAB_QWORD_IS_ALL_ONES EFAB_QWORD_IS_ALL_ONES32 etherfabric.h 　
21341
 EFAB_POPULATE_OWORDEFAB_POPULATE_OWORD EFAB_POPULATE_OWORD64 etherfabric.h 　
21342
 EFAB_POPULATE_QWORDEFAB_POPULATE_QWORD EFAB_POPULATE_QWORD64 etherfabric.h 　
21343
 EFAB_POPULATE_OWORDEFAB_POPULATE_OWORD EFAB_POPULATE_OWORD32 etherfabric.h 　
21344
 EFAB_POPULATE_QWORDEFAB_POPULATE_QWORD EFAB_POPULATE_QWORD32 etherfabric.h 　
21345
 EFAB_POPULATE_OWORD_10EFAB_POPULATE_OWORD_10 EFAB_POPULATE_OWORD etherfabric.h 　
21346
 EFAB_POPULATE_QWORD_10EFAB_POPULATE_QWORD_10 EFAB_POPULATE_QWORD etherfabric.h 　
21347
 EFAB_POPULATE_DWORD_10EFAB_POPULATE_DWORD_10 EFAB_POPULATE_DWORD etherfabric.h 　
21348
 EFAB_SET_OWORD_FIELDEFAB_SET_OWORD_FIELD EFAB_SET_OWORD_FIELD64 etherfabric.h 　
21349
 EFAB_SET_QWORD_FIELDEFAB_SET_QWORD_FIELD EFAB_SET_QWORD_FIELD64 etherfabric.h 　
21350
 EFAB_SET_OWORD_FIELDEFAB_SET_OWORD_FIELD EFAB_SET_OWORD_FIELD32 etherfabric.h 　
21351
 EFAB_SET_QWORD_FIELDEFAB_SET_QWORD_FIELD EFAB_SET_QWORD_FIELD32 etherfabric.h 　
21352
 DMA_ADDR_T_WIDTHDMA_ADDR_T_WIDTH ( 8 * sizeof ( dma_addr_t ) ) etherfabric.h 　
21353
 EFAB_DMA_MAX_MASKEFAB_DMA_MAX_MASK ( ( DMA_ADDR_T_WIDTH == 64 ) ? \ ~( ( uint64_t ) 0 ) : ~( ( uint32_t ) 0 ) ) etherfabric.h 　
21354
 dma_addr_tdma_addr_t unsigned long etherfabric_nic.h 　
21355
 EFAB_BUF_ALIGNEFAB_BUF_ALIGN 4096 etherfabric_nic.h 　
21356
 EFAB_RXD_SIZEEFAB_RXD_SIZE 512 etherfabric_nic.h 　
21357
 EFAB_TXD_SIZEEFAB_TXD_SIZE 512 etherfabric_nic.h 　
21358
 EFAB_EVQ_SIZEEFAB_EVQ_SIZE 512 etherfabric_nic.h 　
21359
 EFAB_NUM_RX_DESCEFAB_NUM_RX_DESC 16 etherfabric_nic.h 　
21360
 EFAB_RX_BUF_SIZEEFAB_RX_BUF_SIZE 1600 etherfabric_nic.h 　
21361
 HFA384x_CMD_ALLOC_LEN_MINHFA384x_CMD_ALLOC_LEN_MIN ((UINT16)4) hfa384x.h 　
21362
 HFA384x_CMD_ALLOC_LEN_MAXHFA384x_CMD_ALLOC_LEN_MAX ((UINT16)2400) hfa384x.h 　
21363
 HFA384x_BAP_DATALEN_MAXHFA384x_BAP_DATALEN_MAX ((UINT16)4096) hfa384x.h 　
21364
 HFA384x_BAP_OFFSET_MAXHFA384x_BAP_OFFSET_MAX ((UINT16)4096) hfa384x.h 　
21365
 HFA384x_PORTID_MAXHFA384x_PORTID_MAX ((UINT16)7) hfa384x.h 　
21366
 HFA384x_NUMPORTS_MAXHFA384x_NUMPORTS_MAX ((UINT16)(HFA384x_PORTID_MAX+1)) hfa384x.h 　
21367
 HFA384x_PDR_LEN_MAXHFA384x_PDR_LEN_MAX ((UINT16)512) hfa384x.h in bytes, from EK
21368
 HFA384x_PDA_RECS_MAXHFA384x_PDA_RECS_MAX ((UINT16)200) hfa384x.h a guess
21369
 HFA384x_PDA_LEN_MAXHFA384x_PDA_LEN_MAX ((UINT16)1024) hfa384x.h in bytes, from EK
21370
 HFA384x_SCANRESULT_MAXHFA384x_SCANRESULT_MAX ((UINT16)31) hfa384x.h 　
21371
 HFA384x_HSCANRESULT_MAXHFA384x_HSCANRESULT_MAX ((UINT16)31) hfa384x.h 　
21372
 HFA384x_CHINFORESULT_MAXHFA384x_CHINFORESULT_MAX ((UINT16)16) hfa384x.h 　
21373
 HFA384x_DRVR_FIDSTACKLEN_MAXHFA384x_DRVR_FIDSTACKLEN_MAX (10) hfa384x.h 　
21374
 HFA384x_DRVR_TXBUF_MAXHFA384x_DRVR_TXBUF_MAX (sizeof(hfa384x_tx_frame_t) + \ WLAN_DATA_MAXLEN - \ WLAN_WEP_IV_LEN - \ WLAN_WEP_ICV_LEN + 2) hfa384x.h 　
21375
 HFA384x_DRVR_MAGICHFA384x_DRVR_MAGIC (0x4a2d) hfa384x.h 　
21376
 HFA384x_INFODATA_MAXLENHFA384x_INFODATA_MAXLEN (sizeof(hfa384x_infodata_t)) hfa384x.h 　
21377
 HFA384x_INFOFRM_MAXLENHFA384x_INFOFRM_MAXLEN (sizeof(hfa384x_InfFrame_t)) hfa384x.h 　
21378
 HFA384x_RID_GUESSING_MAXLENHFA384x_RID_GUESSING_MAXLEN 2048 hfa384x.h I'm not really sure
21379
 HFA384x_RIDDATA_MAXLENHFA384x_RIDDATA_MAXLEN HFA384x_RID_GUESSING_MAXLEN hfa384x.h 　
21380
 HFA384x_USB_RWMEM_MAXLENHFA384x_USB_RWMEM_MAXLEN 2048 hfa384x.h 　
21381
 HFA384x_BAP_PROCHFA384x_BAP_PROC ((UINT16)0) hfa384x.h 　
21382
 HFA384x_BAP_INTHFA384x_BAP_INT ((UINT16)1) hfa384x.h 　
21383
 HFA384x_PORTTYPE_IBSSHFA384x_PORTTYPE_IBSS ((UINT16)0) hfa384x.h 　
21384
 HFA384x_PORTTYPE_BSSHFA384x_PORTTYPE_BSS ((UINT16)1) hfa384x.h 　
21385
 HFA384x_PORTTYPE_WDSHFA384x_PORTTYPE_WDS ((UINT16)2) hfa384x.h 　
21386
 HFA384x_PORTTYPE_PSUEDOIBSSHFA384x_PORTTYPE_PSUEDOIBSS ((UINT16)3) hfa384x.h 　
21387
 HFA384x_PORTTYPE_HOSTAPHFA384x_PORTTYPE_HOSTAP ((UINT16)6) hfa384x.h 　
21388
 HFA384x_WEPFLAGS_PRIVINVOKEDHFA384x_WEPFLAGS_PRIVINVOKED ((UINT16)BIT0) hfa384x.h 　
21389
 HFA384x_WEPFLAGS_EXCLUDEHFA384x_WEPFLAGS_EXCLUDE ((UINT16)BIT1) hfa384x.h 　
21390
 HFA384x_WEPFLAGS_DISABLE_TXCRYPHFA384x_WEPFLAGS_DISABLE_TXCRYP ((UINT16)BIT4) hfa384x.h 　
21391
 HFA384x_WEPFLAGS_DISABLE_RXCRYPHFA384x_WEPFLAGS_DISABLE_RXCRYP ((UINT16)BIT7) hfa384x.h 　
21392
 HFA384x_WEPFLAGS_DISALLOW_MIXEDHFA384x_WEPFLAGS_DISALLOW_MIXED ((UINT16)BIT11) hfa384x.h 　
21393
 HFA384x_WEPFLAGS_IV_INTERVAL1HFA384x_WEPFLAGS_IV_INTERVAL1 ((UINT16)0) hfa384x.h 　
21394
 HFA384x_WEPFLAGS_IV_INTERVAL10HFA384x_WEPFLAGS_IV_INTERVAL10 ((UINT16)BIT5) hfa384x.h 　
21395
 HFA384x_WEPFLAGS_IV_INTERVAL50HFA384x_WEPFLAGS_IV_INTERVAL50 ((UINT16)BIT6) hfa384x.h 　
21396
 HFA384x_WEPFLAGS_IV_INTERVAL100HFA384x_WEPFLAGS_IV_INTERVAL100 ((UINT16)(BIT5 | BIT6)) hfa384x.h 　
21397
 HFA384x_WEPFLAGS_FIRMWARE_WPAHFA384x_WEPFLAGS_FIRMWARE_WPA ((UINT16)BIT8) hfa384x.h 　
21398
 HFA384x_WEPFLAGS_HOST_MICHFA384x_WEPFLAGS_HOST_MIC ((UINT16)BIT9) hfa384x.h 　
21399
 HFA384x_ROAMMODE_FWSCAN_FWROAMHFA384x_ROAMMODE_FWSCAN_FWROAM ((UINT16)1) hfa384x.h 　
21400
 HFA384x_ROAMMODE_FWSCAN_HOSTROAHFA384x_ROAMMODE_FWSCAN_HOSTROA ((UINT16)2) hfa384x.h 　
21401
 HFA384x_ROAMMODE_HOSTSCAN_HOSTRHFA384x_ROAMMODE_HOSTSCAN_HOSTR ((UINT16)3) hfa384x.h 　
21402
 HFA384x_PORTSTATUS_DISABLEDHFA384x_PORTSTATUS_DISABLED ((UINT16)1) hfa384x.h 　
21403
 HFA384x_PORTSTATUS_INITSRCHHFA384x_PORTSTATUS_INITSRCH ((UINT16)2) hfa384x.h 　
21404
 HFA384x_PORTSTATUS_CONN_IBSSHFA384x_PORTSTATUS_CONN_IBSS ((UINT16)3) hfa384x.h 　
21405
 HFA384x_PORTSTATUS_CONN_ESSHFA384x_PORTSTATUS_CONN_ESS ((UINT16)4) hfa384x.h 　
21406
 HFA384x_PORTSTATUS_OOR_ESSHFA384x_PORTSTATUS_OOR_ESS ((UINT16)5) hfa384x.h 　
21407
 HFA384x_PORTSTATUS_CONN_WDSHFA384x_PORTSTATUS_CONN_WDS ((UINT16)6) hfa384x.h 　
21408
 HFA384x_PORTSTATUS_HOSTAPHFA384x_PORTSTATUS_HOSTAP ((UINT16)8) hfa384x.h 　
21409
 HFA384x_RATEBIT_1HFA384x_RATEBIT_1 ((UINT16)1) hfa384x.h 　
21410
 HFA384x_RATEBIT_2HFA384x_RATEBIT_2 ((UINT16)2) hfa384x.h 　
21411
 HFA384x_RATEBIT_5dot5HFA384x_RATEBIT_5dot5 ((UINT16)4) hfa384x.h 　
21412
 HFA384x_RATEBIT_11HFA384x_RATEBIT_11 ((UINT16)8) hfa384x.h 　
21413
 HFA384x_TXCMD_NORECLHFA384x_TXCMD_NORECL ((UINT16)0) hfa384x.h 　
21414
 HFA384x_TXCMD_RECLHFA384x_TXCMD_RECL ((UINT16)1) hfa384x.h 　
21415
 HFA384x_ADDR_AUX_OFF_MAXHFA384x_ADDR_AUX_OFF_MAX ((UINT16)0x007f) hfa384x.h 　
21416
 HFA384x_ADDR_FLAT_AUX_PAGE_MASKHFA384x_ADDR_FLAT_AUX_PAGE_MASK (0x007fff80) hfa384x.h 　
21417
 HFA384x_ADDR_FLAT_AUX_OFF_MASKHFA384x_ADDR_FLAT_AUX_OFF_MASK (0x0000007f) hfa384x.h 　
21418
 HFA384x_ADDR_FLAT_CMD_PAGE_MASKHFA384x_ADDR_FLAT_CMD_PAGE_MASK (0xffff0000) hfa384x.h 　
21419
 HFA384x_ADDR_FLAT_CMD_OFF_MASKHFA384x_ADDR_FLAT_CMD_OFF_MASK (0x0000ffff) hfa384x.h 　
21420
 HFA384x_ADDR_AUX_PAGE_MASKHFA384x_ADDR_AUX_PAGE_MASK (0xffff) hfa384x.h 　
21421
 HFA384x_ADDR_AUX_OFF_MASKHFA384x_ADDR_AUX_OFF_MASK (0x007f) hfa384x.h 　
21422
 HFA384x_ADDR_CMD_PAGE_MASKHFA384x_ADDR_CMD_PAGE_MASK (0x007f) hfa384x.h 　
21423
 HFA384x_ADDR_CMD_OFF_MASKHFA384x_ADDR_CMD_OFF_MASK (0xffff) hfa384x.h 　
21424
 HFA384x_AUX_CTL_EXTDSHFA384x_AUX_CTL_EXTDS (0x00) hfa384x.h 　
21425
 HFA384x_AUX_CTL_NVHFA384x_AUX_CTL_NV (0x01) hfa384x.h 　
21426
 HFA384x_AUX_CTL_PHYHFA384x_AUX_CTL_PHY (0x02) hfa384x.h 　
21427
 HFA384x_AUX_CTL_ICSRAMHFA384x_AUX_CTL_ICSRAM (0x03) hfa384x.h 　
21428
 HFA3842_PDA_BASEHFA3842_PDA_BASE (0x007f0000UL) hfa384x.h 　
21429
 HFA3841_PDA_BASEHFA3841_PDA_BASE (0x003f0000UL) hfa384x.h 　
21430
 HFA3841_PDA_BOGUS_BASEHFA3841_PDA_BOGUS_BASE (0x00390000UL) hfa384x.h 　
21431
 HFA384x_DLSTATE_DISABLEDHFA384x_DLSTATE_DISABLED 0 hfa384x.h 　
21432
 HFA384x_DLSTATE_RAMENABLEDHFA384x_DLSTATE_RAMENABLED 1 hfa384x.h 　
21433
 HFA384x_DLSTATE_FLASHENABLEDHFA384x_DLSTATE_FLASHENABLED 2 hfa384x.h 　
21434
 HFA384x_DLSTATE_FLASHWRITTENHFA384x_DLSTATE_FLASHWRITTEN 3 hfa384x.h 　
21435
 HFA384x_DLSTATE_FLASHWRITEPENDIHFA384x_DLSTATE_FLASHWRITEPENDI 4 hfa384x.h 　
21436
 HFA384x_DLSTATE_GENESISHFA384x_DLSTATE_GENESIS 5 hfa384x.h 　
21437
 HFA384x_CMD_OFFHFA384x_CMD_OFF (0x00) hfa384x.h 　
21438
 HFA384x_PARAM0_OFFHFA384x_PARAM0_OFF (0x02) hfa384x.h 　
21439
 HFA384x_PARAM1_OFFHFA384x_PARAM1_OFF (0x04) hfa384x.h 　
21440
 HFA384x_PARAM2_OFFHFA384x_PARAM2_OFF (0x06) hfa384x.h 　
21441
 HFA384x_STATUS_OFFHFA384x_STATUS_OFF (0x08) hfa384x.h 　
21442
 HFA384x_RESP0_OFFHFA384x_RESP0_OFF (0x0A) hfa384x.h 　
21443
 HFA384x_RESP1_OFFHFA384x_RESP1_OFF (0x0C) hfa384x.h 　
21444
 HFA384x_RESP2_OFFHFA384x_RESP2_OFF (0x0E) hfa384x.h 　
21445
 HFA384x_INFOFID_OFFHFA384x_INFOFID_OFF (0x10) hfa384x.h 　
21446
 HFA384x_RXFID_OFFHFA384x_RXFID_OFF (0x20) hfa384x.h 　
21447
 HFA384x_ALLOCFID_OFFHFA384x_ALLOCFID_OFF (0x22) hfa384x.h 　
21448
 HFA384x_TXCOMPLFID_OFFHFA384x_TXCOMPLFID_OFF (0x24) hfa384x.h 　
21449
 HFA384x_SELECT0_OFFHFA384x_SELECT0_OFF (0x18) hfa384x.h 　
21450
 HFA384x_OFFSET0_OFFHFA384x_OFFSET0_OFF (0x1C) hfa384x.h 　
21451
 HFA384x_DATA0_OFFHFA384x_DATA0_OFF (0x36) hfa384x.h 　
21452
 HFA384x_SELECT1_OFFHFA384x_SELECT1_OFF (0x1A) hfa384x.h 　
21453
 HFA384x_OFFSET1_OFFHFA384x_OFFSET1_OFF (0x1E) hfa384x.h 　
21454
 HFA384x_DATA1_OFFHFA384x_DATA1_OFF (0x38) hfa384x.h 　
21455
 HFA384x_EVSTAT_OFFHFA384x_EVSTAT_OFF (0x30) hfa384x.h 　
21456
 HFA384x_INTEN_OFFHFA384x_INTEN_OFF (0x32) hfa384x.h 　
21457
 HFA384x_EVACK_OFFHFA384x_EVACK_OFF (0x34) hfa384x.h 　
21458
 HFA384x_CONTROL_OFFHFA384x_CONTROL_OFF (0x14) hfa384x.h 　
21459
 HFA384x_SWSUPPORT0_OFFHFA384x_SWSUPPORT0_OFF (0x28) hfa384x.h 　
21460
 HFA384x_SWSUPPORT1_OFFHFA384x_SWSUPPORT1_OFF (0x2A) hfa384x.h 　
21461
 HFA384x_SWSUPPORT2_OFFHFA384x_SWSUPPORT2_OFF (0x2C) hfa384x.h 　
21462
 HFA384x_AUXPAGE_OFFHFA384x_AUXPAGE_OFF (0x3A) hfa384x.h 　
21463
 HFA384x_AUXOFFSET_OFFHFA384x_AUXOFFSET_OFF (0x3C) hfa384x.h 　
21464
 HFA384x_AUXDATA_OFFHFA384x_AUXDATA_OFF (0x3E) hfa384x.h 　
21465
 HFA384x_CMD_OFFHFA384x_CMD_OFF (0x00) hfa384x.h 　
21466
 HFA384x_PARAM0_OFFHFA384x_PARAM0_OFF (0x04) hfa384x.h 　
21467
 HFA384x_PARAM1_OFFHFA384x_PARAM1_OFF (0x08) hfa384x.h 　
21468
 HFA384x_PARAM2_OFFHFA384x_PARAM2_OFF (0x0c) hfa384x.h 　
21469
 HFA384x_STATUS_OFFHFA384x_STATUS_OFF (0x10) hfa384x.h 　
21470
 HFA384x_RESP0_OFFHFA384x_RESP0_OFF (0x14) hfa384x.h 　
21471
 HFA384x_RESP1_OFFHFA384x_RESP1_OFF (0x18) hfa384x.h 　
21472
 HFA384x_RESP2_OFFHFA384x_RESP2_OFF (0x1c) hfa384x.h 　
21473
 HFA384x_INFOFID_OFFHFA384x_INFOFID_OFF (0x20) hfa384x.h 　
21474
 HFA384x_RXFID_OFFHFA384x_RXFID_OFF (0x40) hfa384x.h 　
21475
 HFA384x_ALLOCFID_OFFHFA384x_ALLOCFID_OFF (0x44) hfa384x.h 　
21476
 HFA384x_TXCOMPLFID_OFFHFA384x_TXCOMPLFID_OFF (0x48) hfa384x.h 　
21477
 HFA384x_SELECT0_OFFHFA384x_SELECT0_OFF (0x30) hfa384x.h 　
21478
 HFA384x_OFFSET0_OFFHFA384x_OFFSET0_OFF (0x38) hfa384x.h 　
21479
 HFA384x_DATA0_OFFHFA384x_DATA0_OFF (0x6c) hfa384x.h 　
21480
 HFA384x_SELECT1_OFFHFA384x_SELECT1_OFF (0x34) hfa384x.h 　
21481
 HFA384x_OFFSET1_OFFHFA384x_OFFSET1_OFF (0x3c) hfa384x.h 　
21482
 HFA384x_DATA1_OFFHFA384x_DATA1_OFF (0x70) hfa384x.h 　
21483
 HFA384x_EVSTAT_OFFHFA384x_EVSTAT_OFF (0x60) hfa384x.h 　
21484
 HFA384x_INTEN_OFFHFA384x_INTEN_OFF (0x64) hfa384x.h 　
21485
 HFA384x_EVACK_OFFHFA384x_EVACK_OFF (0x68) hfa384x.h 　
21486
 HFA384x_CONTROL_OFFHFA384x_CONTROL_OFF (0x28) hfa384x.h 　
21487
 HFA384x_SWSUPPORT0_OFFHFA384x_SWSUPPORT0_OFF (0x50) hfa384x.h 　
21488
 HFA384x_SWSUPPORT1_OFFHFA384x_SWSUPPORT1_OFF (0x54) hfa384x.h 　
21489
 HFA384x_SWSUPPORT2_OFFHFA384x_SWSUPPORT2_OFF (0x58) hfa384x.h 　
21490
 HFA384x_AUXPAGE_OFFHFA384x_AUXPAGE_OFF (0x74) hfa384x.h 　
21491
 HFA384x_AUXOFFSET_OFFHFA384x_AUXOFFSET_OFF (0x78) hfa384x.h 　
21492
 HFA384x_AUXDATA_OFFHFA384x_AUXDATA_OFF (0x7c) hfa384x.h 　
21493
 HFA384x_PCICOR_OFFHFA384x_PCICOR_OFF (0x4c) hfa384x.h 　
21494
 HFA384x_PCIHCR_OFFHFA384x_PCIHCR_OFF (0x5c) hfa384x.h 　
21495
 HFA384x_PCI_M0_ADDRH_OFFHFA384x_PCI_M0_ADDRH_OFF (0x80) hfa384x.h 　
21496
 HFA384x_PCI_M0_ADDRL_OFFHFA384x_PCI_M0_ADDRL_OFF (0x84) hfa384x.h 　
21497
 HFA384x_PCI_M0_LEN_OFFHFA384x_PCI_M0_LEN_OFF (0x88) hfa384x.h 　
21498
 HFA384x_PCI_M0_CTL_OFFHFA384x_PCI_M0_CTL_OFF (0x8c) hfa384x.h 　
21499
 HFA384x_PCI_STATUS_OFFHFA384x_PCI_STATUS_OFF (0x98) hfa384x.h 　
21500
 HFA384x_PCI_M1_ADDRH_OFFHFA384x_PCI_M1_ADDRH_OFF (0xa0) hfa384x.h 　
21501
 HFA384x_PCI_M1_ADDRL_OFFHFA384x_PCI_M1_ADDRL_OFF (0xa4) hfa384x.h 　
21502
 HFA384x_PCI_M1_LEN_OFFHFA384x_PCI_M1_LEN_OFF (0xa8) hfa384x.h 　
21503
 HFA384x_PCI_M1_CTL_OFFHFA384x_PCI_M1_CTL_OFF (0xac) hfa384x.h 　
21504
 HFA384x_CMD_BUSYHFA384x_CMD_BUSY ((UINT16)BIT15) hfa384x.h 　
21505
 HFA384x_CMD_AINFOHFA384x_CMD_AINFO ((UINT16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)) hfa384x.h 　
21506
 HFA384x_CMD_MACPORTHFA384x_CMD_MACPORT ((UINT16)(BIT10 | BIT9 | BIT8)) hfa384x.h 　
21507
 HFA384x_CMD_RECLHFA384x_CMD_RECL ((UINT16)BIT8) hfa384x.h 　
21508
 HFA384x_CMD_WRITEHFA384x_CMD_WRITE ((UINT16)BIT8) hfa384x.h 　
21509
 HFA384x_CMD_PROGMODEHFA384x_CMD_PROGMODE ((UINT16)(BIT9 | BIT8)) hfa384x.h 　
21510
 HFA384x_CMD_CMDCODEHFA384x_CMD_CMDCODE ((UINT16)(BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)) hfa384x.h 　
21511
 HFA384x_STATUS_RESULTHFA384x_STATUS_RESULT ((UINT16)(BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8)) hfa384x.h 　
21512
 HFA384x_STATUS_CMDCODEHFA384x_STATUS_CMDCODE ((UINT16)(BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)) hfa384x.h 　
21513
 HFA384x_OFFSET_BUSYHFA384x_OFFSET_BUSY ((UINT16)BIT15) hfa384x.h 　
21514
 HFA384x_OFFSET_ERRHFA384x_OFFSET_ERR ((UINT16)BIT14) hfa384x.h 　
21515
 HFA384x_OFFSET_DATAOFFHFA384x_OFFSET_DATAOFF ((UINT16)(BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1)) hfa384x.h 　
21516
 HFA384x_EVSTAT_TICKHFA384x_EVSTAT_TICK ((UINT16)BIT15) hfa384x.h 　
21517
 HFA384x_EVSTAT_WTERRHFA384x_EVSTAT_WTERR ((UINT16)BIT14) hfa384x.h 　
21518
 HFA384x_EVSTAT_INFDROPHFA384x_EVSTAT_INFDROP ((UINT16)BIT13) hfa384x.h 　
21519
 HFA384x_EVSTAT_INFOHFA384x_EVSTAT_INFO ((UINT16)BIT7) hfa384x.h 　
21520
 HFA384x_EVSTAT_DTIMHFA384x_EVSTAT_DTIM ((UINT16)BIT5) hfa384x.h 　
21521
 HFA384x_EVSTAT_CMDHFA384x_EVSTAT_CMD ((UINT16)BIT4) hfa384x.h 　
21522
 HFA384x_EVSTAT_ALLOCHFA384x_EVSTAT_ALLOC ((UINT16)BIT3) hfa384x.h 　
21523
 HFA384x_EVSTAT_TXEXCHFA384x_EVSTAT_TXEXC ((UINT16)BIT2) hfa384x.h 　
21524
 HFA384x_EVSTAT_TXHFA384x_EVSTAT_TX ((UINT16)BIT1) hfa384x.h 　
21525
 HFA384x_EVSTAT_RXHFA384x_EVSTAT_RX ((UINT16)BIT0) hfa384x.h 　
21526
 HFA384x_INT_BAP_OPHFA384x_INT_BAP_OP (HFA384x_EVSTAT_INFO|HFA384x_EVSTAT_RX|HFA384x_EVSTAT_TX|HFA384x_EVSTAT_TXEXC) hfa384x.h 　
21527
 HFA384x_INT_NORMALHFA384x_INT_NORMAL (HFA384x_EVSTAT_INFO|HFA384x_EVSTAT_RX|HFA384x_EVSTAT_TX|HFA384x_EVSTAT_TXEXC|HFA384x_EVSTAT_INFDROP|HFA384x_EVSTAT_ALLOC|HFA38 hfa384x.h 　
21528
 HFA384x_INTEN_TICKHFA384x_INTEN_TICK ((UINT16)BIT15) hfa384x.h 　
21529
 HFA384x_INTEN_WTERRHFA384x_INTEN_WTERR ((UINT16)BIT14) hfa384x.h 　
21530
 HFA384x_INTEN_INFDROPHFA384x_INTEN_INFDROP ((UINT16)BIT13) hfa384x.h 　
21531
 HFA384x_INTEN_INFOHFA384x_INTEN_INFO ((UINT16)BIT7) hfa384x.h 　
21532
 HFA384x_INTEN_DTIMHFA384x_INTEN_DTIM ((UINT16)BIT5) hfa384x.h 　
21533
 HFA384x_INTEN_CMDHFA384x_INTEN_CMD ((UINT16)BIT4) hfa384x.h 　
21534
 HFA384x_INTEN_ALLOCHFA384x_INTEN_ALLOC ((UINT16)BIT3) hfa384x.h 　
21535
 HFA384x_INTEN_TXEXCHFA384x_INTEN_TXEXC ((UINT16)BIT2) hfa384x.h 　
21536
 HFA384x_INTEN_TXHFA384x_INTEN_TX ((UINT16)BIT1) hfa384x.h 　
21537
 HFA384x_INTEN_RXHFA384x_INTEN_RX ((UINT16)BIT0) hfa384x.h 　
21538
 HFA384x_EVACK_TICKHFA384x_EVACK_TICK ((UINT16)BIT15) hfa384x.h 　
21539
 HFA384x_EVACK_WTERRHFA384x_EVACK_WTERR ((UINT16)BIT14) hfa384x.h 　
21540
 HFA384x_EVACK_INFDROPHFA384x_EVACK_INFDROP ((UINT16)BIT13) hfa384x.h 　
21541
 HFA384x_EVACK_INFOHFA384x_EVACK_INFO ((UINT16)BIT7) hfa384x.h 　
21542
 HFA384x_EVACK_DTIMHFA384x_EVACK_DTIM ((UINT16)BIT5) hfa384x.h 　
21543
 HFA384x_EVACK_CMDHFA384x_EVACK_CMD ((UINT16)BIT4) hfa384x.h 　
21544
 HFA384x_EVACK_ALLOCHFA384x_EVACK_ALLOC ((UINT16)BIT3) hfa384x.h 　
21545
 HFA384x_EVACK_TXEXCHFA384x_EVACK_TXEXC ((UINT16)BIT2) hfa384x.h 　
21546
 HFA384x_EVACK_TXHFA384x_EVACK_TX ((UINT16)BIT1) hfa384x.h 　
21547
 HFA384x_EVACK_RXHFA384x_EVACK_RX ((UINT16)BIT0) hfa384x.h 　
21548
 HFA384x_CONTROL_AUXENHFA384x_CONTROL_AUXEN ((UINT16)(BIT15 | BIT14)) hfa384x.h 　
21549
 HFA384x_CMDCODE_INITHFA384x_CMDCODE_INIT ((UINT16)0x00) hfa384x.h 　
21550
 HFA384x_CMDCODE_ENABLEHFA384x_CMDCODE_ENABLE ((UINT16)0x01) hfa384x.h 　
21551
 HFA384x_CMDCODE_DISABLEHFA384x_CMDCODE_DISABLE ((UINT16)0x02) hfa384x.h 　
21552
 HFA384x_CMDCODE_DIAGHFA384x_CMDCODE_DIAG ((UINT16)0x03) hfa384x.h 　
21553
 HFA384x_CMDCODE_ALLOCHFA384x_CMDCODE_ALLOC ((UINT16)0x0A) hfa384x.h 　
21554
 HFA384x_CMDCODE_TXHFA384x_CMDCODE_TX ((UINT16)0x0B) hfa384x.h 　
21555
 HFA384x_CMDCODE_CLRPRSTHFA384x_CMDCODE_CLRPRST ((UINT16)0x12) hfa384x.h 　
21556
 HFA384x_CMDCODE_NOTIFYHFA384x_CMDCODE_NOTIFY ((UINT16)0x10) hfa384x.h 　
21557
 HFA384x_CMDCODE_INQHFA384x_CMDCODE_INQ ((UINT16)0x11) hfa384x.h 　
21558
 HFA384x_CMDCODE_ACCESSHFA384x_CMDCODE_ACCESS ((UINT16)0x21) hfa384x.h 　
21559
 HFA384x_CMDCODE_DOWNLDHFA384x_CMDCODE_DOWNLD ((UINT16)0x22) hfa384x.h 　
21560
 HFA384x_CMDCODE_MONITORHFA384x_CMDCODE_MONITOR ((UINT16)(0x38)) hfa384x.h 　
21561
 HFA384x_MONITOR_ENABLEHFA384x_MONITOR_ENABLE ((UINT16)(0x0b)) hfa384x.h 　
21562
 HFA384x_MONITOR_DISABLEHFA384x_MONITOR_DISABLE ((UINT16)(0x0f)) hfa384x.h 　
21563
 HFA384x_SUCCESSHFA384x_SUCCESS ((UINT16)(0x00)) hfa384x.h 　
21564
 HFA384x_CARD_FAILHFA384x_CARD_FAIL ((UINT16)(0x01)) hfa384x.h 　
21565
 HFA384x_NO_BUFFHFA384x_NO_BUFF ((UINT16)(0x05)) hfa384x.h 　
21566
 HFA384x_CMD_ERRHFA384x_CMD_ERR ((UINT16)(0x7F)) hfa384x.h 　
21567
 HFA384x_PROGMODE_DISABLEHFA384x_PROGMODE_DISABLE ((UINT16)0x00) hfa384x.h 　
21568
 HFA384x_PROGMODE_RAMHFA384x_PROGMODE_RAM ((UINT16)0x01) hfa384x.h 　
21569
 HFA384x_PROGMODE_NVHFA384x_PROGMODE_NV ((UINT16)0x02) hfa384x.h 　
21570
 HFA384x_PROGMODE_NVWRITEHFA384x_PROGMODE_NVWRITE ((UINT16)0x03) hfa384x.h 　
21571
 HFA384x_AUXPW0HFA384x_AUXPW0 ((UINT16)0xfe01) hfa384x.h 　
21572
 HFA384x_AUXPW1HFA384x_AUXPW1 ((UINT16)0xdc23) hfa384x.h 　
21573
 HFA384x_AUXPW2HFA384x_AUXPW2 ((UINT16)0xba45) hfa384x.h 　
21574
 HFA384x_CONTROL_AUX_ISDISABLEDHFA384x_CONTROL_AUX_ISDISABLED ((UINT16)0x0000) hfa384x.h 　
21575
 HFA384x_CONTROL_AUX_ISENABLEDHFA384x_CONTROL_AUX_ISENABLED ((UINT16)0xc000) hfa384x.h 　
21576
 HFA384x_CONTROL_AUX_DOENABLEHFA384x_CONTROL_AUX_DOENABLE ((UINT16)0x8000) hfa384x.h 　
21577
 HFA384x_CONTROL_AUX_DODISABLEHFA384x_CONTROL_AUX_DODISABLE ((UINT16)0x4000) hfa384x.h 　
21578
 HFA384x_RID_CNFPORTTYPEHFA384x_RID_CNFPORTTYPE ((UINT16)0xFC00) hfa384x.h 　
21579
 HFA384x_RID_CNFOWNMACADDRHFA384x_RID_CNFOWNMACADDR ((UINT16)0xFC01) hfa384x.h 　
21580
 HFA384x_RID_CNFDESIREDSSIDHFA384x_RID_CNFDESIREDSSID ((UINT16)0xFC02) hfa384x.h 　
21581
 HFA384x_RID_CNFOWNCHANNELHFA384x_RID_CNFOWNCHANNEL ((UINT16)0xFC03) hfa384x.h 　
21582
 HFA384x_RID_CNFOWNSSIDHFA384x_RID_CNFOWNSSID ((UINT16)0xFC04) hfa384x.h 　
21583
 HFA384x_RID_CNFOWNATIMWINHFA384x_RID_CNFOWNATIMWIN ((UINT16)0xFC05) hfa384x.h 　
21584
 HFA384x_RID_CNFSYSSCALEHFA384x_RID_CNFSYSSCALE ((UINT16)0xFC06) hfa384x.h 　
21585
 HFA384x_RID_CNFMAXDATALENHFA384x_RID_CNFMAXDATALEN ((UINT16)0xFC07) hfa384x.h 　
21586
 HFA384x_RID_CNFWDSADDRHFA384x_RID_CNFWDSADDR ((UINT16)0xFC08) hfa384x.h 　
21587
 HFA384x_RID_CNFPMENABLEDHFA384x_RID_CNFPMENABLED ((UINT16)0xFC09) hfa384x.h 　
21588
 HFA384x_RID_CNFPMEPSHFA384x_RID_CNFPMEPS ((UINT16)0xFC0A) hfa384x.h 　
21589
 HFA384x_RID_CNFMULTICASTRXHFA384x_RID_CNFMULTICASTRX ((UINT16)0xFC0B) hfa384x.h 　
21590
 HFA384x_RID_CNFMAXSLEEPDURHFA384x_RID_CNFMAXSLEEPDUR ((UINT16)0xFC0C) hfa384x.h 　
21591
 HFA384x_RID_CNFPMHOLDDURHFA384x_RID_CNFPMHOLDDUR ((UINT16)0xFC0D) hfa384x.h 　
21592
 HFA384x_RID_CNFOWNNAMEHFA384x_RID_CNFOWNNAME ((UINT16)0xFC0E) hfa384x.h 　
21593
 HFA384x_RID_CNFOWNDTIMPERHFA384x_RID_CNFOWNDTIMPER ((UINT16)0xFC10) hfa384x.h 　
21594
 HFA384x_RID_CNFWDSADDR1HFA384x_RID_CNFWDSADDR1 ((UINT16)0xFC11) hfa384x.h 　
21595
 HFA384x_RID_CNFWDSADDR2HFA384x_RID_CNFWDSADDR2 ((UINT16)0xFC12) hfa384x.h 　
21596
 HFA384x_RID_CNFWDSADDR3HFA384x_RID_CNFWDSADDR3 ((UINT16)0xFC13) hfa384x.h 　
21597
 HFA384x_RID_CNFWDSADDR4HFA384x_RID_CNFWDSADDR4 ((UINT16)0xFC14) hfa384x.h 　
21598
 HFA384x_RID_CNFWDSADDR5HFA384x_RID_CNFWDSADDR5 ((UINT16)0xFC15) hfa384x.h 　
21599
 HFA384x_RID_CNFWDSADDR6HFA384x_RID_CNFWDSADDR6 ((UINT16)0xFC16) hfa384x.h 　
21600
 HFA384x_RID_CNFMCASTPMBUFFHFA384x_RID_CNFMCASTPMBUFF ((UINT16)0xFC17) hfa384x.h 　
21601
 HFA384x_RID_CNFPORTTYPE_LENHFA384x_RID_CNFPORTTYPE_LEN ((UINT16)2) hfa384x.h 　
21602
 HFA384x_RID_CNFOWNMACADDR_LENHFA384x_RID_CNFOWNMACADDR_LEN ((UINT16)6) hfa384x.h 　
21603
 HFA384x_RID_CNFDESIREDSSID_LENHFA384x_RID_CNFDESIREDSSID_LEN ((UINT16)34) hfa384x.h 　
21604
 HFA384x_RID_CNFOWNCHANNEL_LENHFA384x_RID_CNFOWNCHANNEL_LEN ((UINT16)2) hfa384x.h 　
21605
 HFA384x_RID_CNFOWNSSID_LENHFA384x_RID_CNFOWNSSID_LEN ((UINT16)34) hfa384x.h 　
21606
 HFA384x_RID_CNFOWNATIMWIN_LENHFA384x_RID_CNFOWNATIMWIN_LEN ((UINT16)2) hfa384x.h 　
21607
 HFA384x_RID_CNFSYSSCALE_LENHFA384x_RID_CNFSYSSCALE_LEN ((UINT16)0) hfa384x.h 　
21608
 HFA384x_RID_CNFMAXDATALEN_LENHFA384x_RID_CNFMAXDATALEN_LEN ((UINT16)0) hfa384x.h 　
21609
 HFA384x_RID_CNFWDSADDR_LENHFA384x_RID_CNFWDSADDR_LEN ((UINT16)6) hfa384x.h 　
21610
 HFA384x_RID_CNFPMENABLED_LENHFA384x_RID_CNFPMENABLED_LEN ((UINT16)0) hfa384x.h 　
21611
 HFA384x_RID_CNFPMEPS_LENHFA384x_RID_CNFPMEPS_LEN ((UINT16)0) hfa384x.h 　
21612
 HFA384x_RID_CNFMULTICASTRX_LENHFA384x_RID_CNFMULTICASTRX_LEN ((UINT16)0) hfa384x.h 　
21613
 HFA384x_RID_CNFMAXSLEEPDUR_LENHFA384x_RID_CNFMAXSLEEPDUR_LEN ((UINT16)0) hfa384x.h 　
21614
 HFA384x_RID_CNFPMHOLDDUR_LENHFA384x_RID_CNFPMHOLDDUR_LEN ((UINT16)0) hfa384x.h 　
21615
 HFA384x_RID_CNFOWNNAME_LENHFA384x_RID_CNFOWNNAME_LEN ((UINT16)34) hfa384x.h 　
21616
 HFA384x_RID_CNFOWNDTIMPER_LENHFA384x_RID_CNFOWNDTIMPER_LEN ((UINT16)0) hfa384x.h 　
21617
 HFA384x_RID_CNFWDSADDR1_LENHFA384x_RID_CNFWDSADDR1_LEN ((UINT16)6) hfa384x.h 　
21618
 HFA384x_RID_CNFWDSADDR2_LENHFA384x_RID_CNFWDSADDR2_LEN ((UINT16)6) hfa384x.h 　
21619
 HFA384x_RID_CNFWDSADDR3_LENHFA384x_RID_CNFWDSADDR3_LEN ((UINT16)6) hfa384x.h 　
21620
 HFA384x_RID_CNFWDSADDR4_LENHFA384x_RID_CNFWDSADDR4_LEN ((UINT16)6) hfa384x.h 　
21621
 HFA384x_RID_CNFWDSADDR5_LENHFA384x_RID_CNFWDSADDR5_LEN ((UINT16)6) hfa384x.h 　
21622
 HFA384x_RID_CNFWDSADDR6_LENHFA384x_RID_CNFWDSADDR6_LEN ((UINT16)6) hfa384x.h 　
21623
 HFA384x_RID_CNFMCASTPMBUFF_LENHFA384x_RID_CNFMCASTPMBUFF_LEN ((UINT16)0) hfa384x.h 　
21624
 HFA384x_RID_CNFAUTHENTICATION_LHFA384x_RID_CNFAUTHENTICATION_L ((UINT16)sizeof(UINT16)) hfa384x.h 　
21625
 HFA384x_RID_CNFMAXSLEEPDUR_LENHFA384x_RID_CNFMAXSLEEPDUR_LEN ((UINT16)0) hfa384x.h 　
21626
 HFA384x_RID_GROUPADDRHFA384x_RID_GROUPADDR ((UINT16)0xFC80) hfa384x.h 　
21627
 HFA384x_RID_CREATEIBSSHFA384x_RID_CREATEIBSS ((UINT16)0xFC81) hfa384x.h 　
21628
 HFA384x_RID_FRAGTHRESHHFA384x_RID_FRAGTHRESH ((UINT16)0xFC82) hfa384x.h 　
21629
 HFA384x_RID_RTSTHRESHHFA384x_RID_RTSTHRESH ((UINT16)0xFC83) hfa384x.h 　
21630
 HFA384x_RID_TXRATECNTLHFA384x_RID_TXRATECNTL ((UINT16)0xFC84) hfa384x.h 　
21631
 HFA384x_RID_PROMISCMODEHFA384x_RID_PROMISCMODE ((UINT16)0xFC85) hfa384x.h 　
21632
 HFA384x_RID_FRAGTHRESH0HFA384x_RID_FRAGTHRESH0 ((UINT16)0xFC90) hfa384x.h 　
21633
 HFA384x_RID_FRAGTHRESH1HFA384x_RID_FRAGTHRESH1 ((UINT16)0xFC91) hfa384x.h 　
21634
 HFA384x_RID_FRAGTHRESH2HFA384x_RID_FRAGTHRESH2 ((UINT16)0xFC92) hfa384x.h 　
21635
 HFA384x_RID_FRAGTHRESH3HFA384x_RID_FRAGTHRESH3 ((UINT16)0xFC93) hfa384x.h 　
21636
 HFA384x_RID_FRAGTHRESH4HFA384x_RID_FRAGTHRESH4 ((UINT16)0xFC94) hfa384x.h 　
21637
 HFA384x_RID_FRAGTHRESH5HFA384x_RID_FRAGTHRESH5 ((UINT16)0xFC95) hfa384x.h 　
21638
 HFA384x_RID_FRAGTHRESH6HFA384x_RID_FRAGTHRESH6 ((UINT16)0xFC96) hfa384x.h 　
21639
 HFA384x_RID_RTSTHRESH0HFA384x_RID_RTSTHRESH0 ((UINT16)0xFC97) hfa384x.h 　
21640
 HFA384x_RID_RTSTHRESH1HFA384x_RID_RTSTHRESH1 ((UINT16)0xFC98) hfa384x.h 　
21641
 HFA384x_RID_RTSTHRESH2HFA384x_RID_RTSTHRESH2 ((UINT16)0xFC99) hfa384x.h 　
21642
 HFA384x_RID_RTSTHRESH3HFA384x_RID_RTSTHRESH3 ((UINT16)0xFC9A) hfa384x.h 　
21643
 HFA384x_RID_RTSTHRESH4HFA384x_RID_RTSTHRESH4 ((UINT16)0xFC9B) hfa384x.h 　
21644
 HFA384x_RID_RTSTHRESH5HFA384x_RID_RTSTHRESH5 ((UINT16)0xFC9C) hfa384x.h 　
21645
 HFA384x_RID_RTSTHRESH6HFA384x_RID_RTSTHRESH6 ((UINT16)0xFC9D) hfa384x.h 　
21646
 HFA384x_RID_TXRATECNTL0HFA384x_RID_TXRATECNTL0 ((UINT16)0xFC9E) hfa384x.h 　
21647
 HFA384x_RID_TXRATECNTL1HFA384x_RID_TXRATECNTL1 ((UINT16)0xFC9F) hfa384x.h 　
21648
 HFA384x_RID_TXRATECNTL2HFA384x_RID_TXRATECNTL2 ((UINT16)0xFCA0) hfa384x.h 　
21649
 HFA384x_RID_TXRATECNTL3HFA384x_RID_TXRATECNTL3 ((UINT16)0xFCA1) hfa384x.h 　
21650
 HFA384x_RID_TXRATECNTL4HFA384x_RID_TXRATECNTL4 ((UINT16)0xFCA2) hfa384x.h 　
21651
 HFA384x_RID_TXRATECNTL5HFA384x_RID_TXRATECNTL5 ((UINT16)0xFCA3) hfa384x.h 　
21652
 HFA384x_RID_TXRATECNTL6HFA384x_RID_TXRATECNTL6 ((UINT16)0xFCA4) hfa384x.h 　
21653
 HFA384x_RID_GROUPADDR_LENHFA384x_RID_GROUPADDR_LEN ((UINT16)16 * WLAN_ADDR_LEN) hfa384x.h 　
21654
 HFA384x_RID_CREATEIBSS_LENHFA384x_RID_CREATEIBSS_LEN ((UINT16)0) hfa384x.h 　
21655
 HFA384x_RID_FRAGTHRESH_LENHFA384x_RID_FRAGTHRESH_LEN ((UINT16)0) hfa384x.h 　
21656
 HFA384x_RID_RTSTHRESH_LENHFA384x_RID_RTSTHRESH_LEN ((UINT16)0) hfa384x.h 　
21657
 HFA384x_RID_TXRATECNTL_LENHFA384x_RID_TXRATECNTL_LEN ((UINT16)4) hfa384x.h 　
21658
 HFA384x_RID_PROMISCMODE_LENHFA384x_RID_PROMISCMODE_LEN ((UINT16)2) hfa384x.h 　
21659
 HFA384x_RID_FRAGTHRESH0_LENHFA384x_RID_FRAGTHRESH0_LEN ((UINT16)0) hfa384x.h 　
21660
 HFA384x_RID_FRAGTHRESH1_LENHFA384x_RID_FRAGTHRESH1_LEN ((UINT16)0) hfa384x.h 　
21661
 HFA384x_RID_FRAGTHRESH2_LENHFA384x_RID_FRAGTHRESH2_LEN ((UINT16)0) hfa384x.h 　
21662
 HFA384x_RID_FRAGTHRESH3_LENHFA384x_RID_FRAGTHRESH3_LEN ((UINT16)0) hfa384x.h 　
21663
 HFA384x_RID_FRAGTHRESH4_LENHFA384x_RID_FRAGTHRESH4_LEN ((UINT16)0) hfa384x.h 　
21664
 HFA384x_RID_FRAGTHRESH5_LENHFA384x_RID_FRAGTHRESH5_LEN ((UINT16)0) hfa384x.h 　
21665
 HFA384x_RID_FRAGTHRESH6_LENHFA384x_RID_FRAGTHRESH6_LEN ((UINT16)0) hfa384x.h 　
21666
 HFA384x_RID_RTSTHRESH0_LENHFA384x_RID_RTSTHRESH0_LEN ((UINT16)0) hfa384x.h 　
21667
 HFA384x_RID_RTSTHRESH1_LENHFA384x_RID_RTSTHRESH1_LEN ((UINT16)0) hfa384x.h 　
21668
 HFA384x_RID_RTSTHRESH2_LENHFA384x_RID_RTSTHRESH2_LEN ((UINT16)0) hfa384x.h 　
21669
 HFA384x_RID_RTSTHRESH3_LENHFA384x_RID_RTSTHRESH3_LEN ((UINT16)0) hfa384x.h 　
21670
 HFA384x_RID_RTSTHRESH4_LENHFA384x_RID_RTSTHRESH4_LEN ((UINT16)0) hfa384x.h 　
21671
 HFA384x_RID_RTSTHRESH5_LENHFA384x_RID_RTSTHRESH5_LEN ((UINT16)0) hfa384x.h 　
21672
 HFA384x_RID_RTSTHRESH6_LENHFA384x_RID_RTSTHRESH6_LEN ((UINT16)0) hfa384x.h 　
21673
 HFA384x_RID_TXRATECNTL0_LENHFA384x_RID_TXRATECNTL0_LEN ((UINT16)0) hfa384x.h 　
21674
 HFA384x_RID_TXRATECNTL1_LENHFA384x_RID_TXRATECNTL1_LEN ((UINT16)0) hfa384x.h 　
21675
 HFA384x_RID_TXRATECNTL2_LENHFA384x_RID_TXRATECNTL2_LEN ((UINT16)0) hfa384x.h 　
21676
 HFA384x_RID_TXRATECNTL3_LENHFA384x_RID_TXRATECNTL3_LEN ((UINT16)0) hfa384x.h 　
21677
 HFA384x_RID_TXRATECNTL4_LENHFA384x_RID_TXRATECNTL4_LEN ((UINT16)0) hfa384x.h 　
21678
 HFA384x_RID_TXRATECNTL5_LENHFA384x_RID_TXRATECNTL5_LEN ((UINT16)0) hfa384x.h 　
21679
 HFA384x_RID_TXRATECNTL6_LENHFA384x_RID_TXRATECNTL6_LEN ((UINT16)0) hfa384x.h 　
21680
 HFA384x_RID_ITICKTIMEHFA384x_RID_ITICKTIME ((UINT16)0xFCE0) hfa384x.h 　
21681
 HFA384x_RID_ITICKTIME_LENHFA384x_RID_ITICKTIME_LEN ((UINT16)2) hfa384x.h 　
21682
 HFA384x_RID_MAXLOADTIMEHFA384x_RID_MAXLOADTIME ((UINT16)0xFD00) hfa384x.h 　
21683
 HFA384x_RID_DOWNLOADBUFFERHFA384x_RID_DOWNLOADBUFFER ((UINT16)0xFD01) hfa384x.h 　
21684
 HFA384x_RID_PRIIDENTITYHFA384x_RID_PRIIDENTITY ((UINT16)0xFD02) hfa384x.h 　
21685
 HFA384x_RID_PRISUPRANGEHFA384x_RID_PRISUPRANGE ((UINT16)0xFD03) hfa384x.h 　
21686
 HFA384x_RID_PRI_CFIACTRANGESHFA384x_RID_PRI_CFIACTRANGES ((UINT16)0xFD04) hfa384x.h 　
21687
 HFA384x_RID_NICSERIALNUMBERHFA384x_RID_NICSERIALNUMBER ((UINT16)0xFD0A) hfa384x.h 　
21688
 HFA384x_RID_NICIDENTITYHFA384x_RID_NICIDENTITY ((UINT16)0xFD0B) hfa384x.h 　
21689
 HFA384x_RID_MFISUPRANGEHFA384x_RID_MFISUPRANGE ((UINT16)0xFD0C) hfa384x.h 　
21690
 HFA384x_RID_CFISUPRANGEHFA384x_RID_CFISUPRANGE ((UINT16)0xFD0D) hfa384x.h 　
21691
 HFA384x_RID_CHANNELLISTHFA384x_RID_CHANNELLIST ((UINT16)0xFD10) hfa384x.h 　
21692
 HFA384x_RID_REGULATORYDOMAINSHFA384x_RID_REGULATORYDOMAINS ((UINT16)0xFD11) hfa384x.h 　
21693
 HFA384x_RID_TEMPTYPEHFA384x_RID_TEMPTYPE ((UINT16)0xFD12) hfa384x.h 　
21694
 HFA384x_RID_CISHFA384x_RID_CIS ((UINT16)0xFD13) hfa384x.h 　
21695
 HFA384x_RID_STAIDENTITYHFA384x_RID_STAIDENTITY ((UINT16)0xFD20) hfa384x.h 　
21696
 HFA384x_RID_STASUPRANGEHFA384x_RID_STASUPRANGE ((UINT16)0xFD21) hfa384x.h 　
21697
 HFA384x_RID_STA_MFIACTRANGESHFA384x_RID_STA_MFIACTRANGES ((UINT16)0xFD22) hfa384x.h 　
21698
 HFA384x_RID_STA_CFIACTRANGESHFA384x_RID_STA_CFIACTRANGES ((UINT16)0xFD23) hfa384x.h 　
21699
 HFA384x_RID_BUILDSEQHFA384x_RID_BUILDSEQ ((UINT16)0xFFFE) hfa384x.h 　
21700
 HFA384x_RID_FWIDHFA384x_RID_FWID ((UINT16)0xFFFF) hfa384x.h 　
21701
 HFA384x_RID_MAXLOADTIME_LENHFA384x_RID_MAXLOADTIME_LEN ((UINT16)0) hfa384x.h 　
21702
 HFA384x_RID_DOWNLOADBUFFER_LENHFA384x_RID_DOWNLOADBUFFER_LEN ((UINT16)sizeof(hfa384x_downloadbuffer_t)) hfa384x.h 　
21703
 HFA384x_RID_PRIIDENTITY_LENHFA384x_RID_PRIIDENTITY_LEN ((UINT16)8) hfa384x.h 　
21704
 HFA384x_RID_PRISUPRANGE_LENHFA384x_RID_PRISUPRANGE_LEN ((UINT16)10) hfa384x.h 　
21705
 HFA384x_RID_CFIACTRANGES_LENHFA384x_RID_CFIACTRANGES_LEN ((UINT16)10) hfa384x.h 　
21706
 HFA384x_RID_NICSERIALNUMBER_LENHFA384x_RID_NICSERIALNUMBER_LEN ((UINT16)12) hfa384x.h 　
21707
 HFA384x_RID_NICIDENTITY_LENHFA384x_RID_NICIDENTITY_LEN ((UINT16)8) hfa384x.h 　
21708
 HFA384x_RID_MFISUPRANGE_LENHFA384x_RID_MFISUPRANGE_LEN ((UINT16)10) hfa384x.h 　
21709
 HFA384x_RID_CFISUPRANGE_LENHFA384x_RID_CFISUPRANGE_LEN ((UINT16)10) hfa384x.h 　
21710
 HFA384x_RID_CHANNELLIST_LENHFA384x_RID_CHANNELLIST_LEN ((UINT16)0) hfa384x.h 　
21711
 HFA384x_RID_REGULATORYDOMAINS_LHFA384x_RID_REGULATORYDOMAINS_L ((UINT16)12) hfa384x.h 　
21712
 HFA384x_RID_TEMPTYPE_LENHFA384x_RID_TEMPTYPE_LEN ((UINT16)0) hfa384x.h 　
21713
 HFA384x_RID_CIS_LENHFA384x_RID_CIS_LEN ((UINT16)480) hfa384x.h 　
21714
 HFA384x_RID_STAIDENTITY_LENHFA384x_RID_STAIDENTITY_LEN ((UINT16)8) hfa384x.h 　
21715
 HFA384x_RID_STASUPRANGE_LENHFA384x_RID_STASUPRANGE_LEN ((UINT16)10) hfa384x.h 　
21716
 HFA384x_RID_MFIACTRANGES_LENHFA384x_RID_MFIACTRANGES_LEN ((UINT16)10) hfa384x.h 　
21717
 HFA384x_RID_CFIACTRANGES2_LENHFA384x_RID_CFIACTRANGES2_LEN ((UINT16)10) hfa384x.h 　
21718
 HFA384x_RID_BUILDSEQ_LENHFA384x_RID_BUILDSEQ_LEN ((UINT16)sizeof(hfa384x_BuildSeq_t)) hfa384x.h 　
21719
 HFA384x_RID_FWID_LENHFA384x_RID_FWID_LEN ((UINT16)sizeof(hfa384x_FWID_t)) hfa384x.h 　
21720
 HFA384x_RID_PORTSTATUSHFA384x_RID_PORTSTATUS ((UINT16)0xFD40) hfa384x.h 　
21721
 HFA384x_RID_CURRENTSSIDHFA384x_RID_CURRENTSSID ((UINT16)0xFD41) hfa384x.h 　
21722
 HFA384x_RID_CURRENTBSSIDHFA384x_RID_CURRENTBSSID ((UINT16)0xFD42) hfa384x.h 　
21723
 HFA384x_RID_COMMSQUALITYHFA384x_RID_COMMSQUALITY ((UINT16)0xFD43) hfa384x.h 　
21724
 HFA384x_RID_CURRENTTXRATEHFA384x_RID_CURRENTTXRATE ((UINT16)0xFD44) hfa384x.h 　
21725
 HFA384x_RID_CURRENTBCNINTHFA384x_RID_CURRENTBCNINT ((UINT16)0xFD45) hfa384x.h 　
21726
 HFA384x_RID_CURRENTSCALETHRESHHFA384x_RID_CURRENTSCALETHRESH ((UINT16)0xFD46) hfa384x.h 　
21727
 HFA384x_RID_PROTOCOLRSPTIMEHFA384x_RID_PROTOCOLRSPTIME ((UINT16)0xFD47) hfa384x.h 　
21728
 HFA384x_RID_SHORTRETRYLIMITHFA384x_RID_SHORTRETRYLIMIT ((UINT16)0xFD48) hfa384x.h 　
21729
 HFA384x_RID_LONGRETRYLIMITHFA384x_RID_LONGRETRYLIMIT ((UINT16)0xFD49) hfa384x.h 　
21730
 HFA384x_RID_MAXTXLIFETIMEHFA384x_RID_MAXTXLIFETIME ((UINT16)0xFD4A) hfa384x.h 　
21731
 HFA384x_RID_MAXRXLIFETIMEHFA384x_RID_MAXRXLIFETIME ((UINT16)0xFD4B) hfa384x.h 　
21732
 HFA384x_RID_CFPOLLABLEHFA384x_RID_CFPOLLABLE ((UINT16)0xFD4C) hfa384x.h 　
21733
 HFA384x_RID_AUTHALGORITHMSHFA384x_RID_AUTHALGORITHMS ((UINT16)0xFD4D) hfa384x.h 　
21734
 HFA384x_RID_PRIVACYOPTIMPHFA384x_RID_PRIVACYOPTIMP ((UINT16)0xFD4F) hfa384x.h 　
21735
 HFA384x_RID_DBMCOMMSQUALITYHFA384x_RID_DBMCOMMSQUALITY ((UINT16)0xFD51) hfa384x.h 　
21736
 HFA384x_RID_CURRENTTXRATE1HFA384x_RID_CURRENTTXRATE1 ((UINT16)0xFD80) hfa384x.h 　
21737
 HFA384x_RID_CURRENTTXRATE2HFA384x_RID_CURRENTTXRATE2 ((UINT16)0xFD81) hfa384x.h 　
21738
 HFA384x_RID_CURRENTTXRATE3HFA384x_RID_CURRENTTXRATE3 ((UINT16)0xFD82) hfa384x.h 　
21739
 HFA384x_RID_CURRENTTXRATE4HFA384x_RID_CURRENTTXRATE4 ((UINT16)0xFD83) hfa384x.h 　
21740
 HFA384x_RID_CURRENTTXRATE5HFA384x_RID_CURRENTTXRATE5 ((UINT16)0xFD84) hfa384x.h 　
21741
 HFA384x_RID_CURRENTTXRATE6HFA384x_RID_CURRENTTXRATE6 ((UINT16)0xFD85) hfa384x.h 　
21742
 HFA384x_RID_OWNMACADDRESSHFA384x_RID_OWNMACADDRESS ((UINT16)0xFD86) hfa384x.h 　
21743
 HFA384x_RID_SCANRESULTSHFA384x_RID_SCANRESULTS ((UINT16)0xFD88) hfa384x.h NEW
21744
 HFA384x_RID_HOSTSCANRESULTSHFA384x_RID_HOSTSCANRESULTS ((UINT16)0xFD89) hfa384x.h NEW
21745
 HFA384x_RID_AUTHENTICATIONUSEDHFA384x_RID_AUTHENTICATIONUSED ((UINT16)0xFD8A) hfa384x.h NEW
21746
 HFA384x_RID_ASSOCIATEFAILUREHFA384x_RID_ASSOCIATEFAILURE ((UINT16)0xFD8D) hfa384x.h 1.8.0
21747
 HFA384x_RID_PORTSTATUS_LENHFA384x_RID_PORTSTATUS_LEN ((UINT16)0) hfa384x.h 　
21748
 HFA384x_RID_CURRENTSSID_LENHFA384x_RID_CURRENTSSID_LEN ((UINT16)34) hfa384x.h 　
21749
 HFA384x_RID_CURRENTBSSID_LENHFA384x_RID_CURRENTBSSID_LEN ((UINT16)WLAN_BSSID_LEN) hfa384x.h 　
21750
 HFA384x_RID_COMMSQUALITY_LENHFA384x_RID_COMMSQUALITY_LEN ((UINT16)sizeof(hfa384x_commsquality_t)) hfa384x.h 　
21751
 HFA384x_RID_DBMCOMMSQUALITY_LENHFA384x_RID_DBMCOMMSQUALITY_LEN ((UINT16)sizeof(hfa384x_dbmcommsquality_t)) hfa384x.h 　
21752
 HFA384x_RID_CURRENTTXRATE_LENHFA384x_RID_CURRENTTXRATE_LEN ((UINT16)0) hfa384x.h 　
21753
 HFA384x_RID_CURRENTBCNINT_LENHFA384x_RID_CURRENTBCNINT_LEN ((UINT16)0) hfa384x.h 　
21754
 HFA384x_RID_STACURSCALETHRESH_LHFA384x_RID_STACURSCALETHRESH_L ((UINT16)12) hfa384x.h 　
21755
 HFA384x_RID_APCURSCALETHRESH_LEHFA384x_RID_APCURSCALETHRESH_LE ((UINT16)6) hfa384x.h 　
21756
 HFA384x_RID_PROTOCOLRSPTIME_LENHFA384x_RID_PROTOCOLRSPTIME_LEN ((UINT16)0) hfa384x.h 　
21757
 HFA384x_RID_SHORTRETRYLIMIT_LENHFA384x_RID_SHORTRETRYLIMIT_LEN ((UINT16)0) hfa384x.h 　
21758
 HFA384x_RID_LONGRETRYLIMIT_LENHFA384x_RID_LONGRETRYLIMIT_LEN ((UINT16)0) hfa384x.h 　
21759
 HFA384x_RID_MAXTXLIFETIME_LENHFA384x_RID_MAXTXLIFETIME_LEN ((UINT16)0) hfa384x.h 　
21760
 HFA384x_RID_MAXRXLIFETIME_LENHFA384x_RID_MAXRXLIFETIME_LEN ((UINT16)0) hfa384x.h 　
21761
 HFA384x_RID_CFPOLLABLE_LENHFA384x_RID_CFPOLLABLE_LEN ((UINT16)0) hfa384x.h 　
21762
 HFA384x_RID_AUTHALGORITHMS_LENHFA384x_RID_AUTHALGORITHMS_LEN ((UINT16)4) hfa384x.h 　
21763
 HFA384x_RID_PRIVACYOPTIMP_LENHFA384x_RID_PRIVACYOPTIMP_LEN ((UINT16)0) hfa384x.h 　
21764
 HFA384x_RID_CURRENTTXRATE1_LENHFA384x_RID_CURRENTTXRATE1_LEN ((UINT16)0) hfa384x.h 　
21765
 HFA384x_RID_CURRENTTXRATE2_LENHFA384x_RID_CURRENTTXRATE2_LEN ((UINT16)0) hfa384x.h 　
21766
 HFA384x_RID_CURRENTTXRATE3_LENHFA384x_RID_CURRENTTXRATE3_LEN ((UINT16)0) hfa384x.h 　
21767
 HFA384x_RID_CURRENTTXRATE4_LENHFA384x_RID_CURRENTTXRATE4_LEN ((UINT16)0) hfa384x.h 　
21768
 HFA384x_RID_CURRENTTXRATE5_LENHFA384x_RID_CURRENTTXRATE5_LEN ((UINT16)0) hfa384x.h 　
21769
 HFA384x_RID_CURRENTTXRATE6_LENHFA384x_RID_CURRENTTXRATE6_LEN ((UINT16)0) hfa384x.h 　
21770
 HFA384x_RID_OWNMACADDRESS_LENHFA384x_RID_OWNMACADDRESS_LEN ((UINT16)6) hfa384x.h 　
21771
 HFA384x_RID_PCFINFO_LENHFA384x_RID_PCFINFO_LEN ((UINT16)6) hfa384x.h 　
21772
 HFA384x_RID_CNFAPPCFINFO_LENHFA384x_RID_CNFAPPCFINFO_LEN ((UINT16)sizeof(hfa384x_PCFInfo_data_t)) hfa384x.h 　
21773
 HFA384x_RID_SCANREQUEST_LENHFA384x_RID_SCANREQUEST_LEN ((UINT16)sizeof(hfa384x_ScanRequest_data_t)) hfa384x.h 　
21774
 HFA384x_RID_JOINREQUEST_LENHFA384x_RID_JOINREQUEST_LEN ((UINT16)sizeof(hfa384x_JoinRequest_data_t)) hfa384x.h 　
21775
 HFA384x_RID_AUTHENTICATESTA_LENHFA384x_RID_AUTHENTICATESTA_LEN ((UINT16)sizeof(hfa384x_authenticateStation_data_t)) hfa384x.h 　
21776
 HFA384x_RID_CHANNELINFOREQUEST_HFA384x_RID_CHANNELINFOREQUEST_ ((UINT16)sizeof(hfa384x_ChannelInfoRequest_data_t)) hfa384x.h 　
21777
 HFA384x_RID_PHYTYPEHFA384x_RID_PHYTYPE ((UINT16)0xFDC0) hfa384x.h 　
21778
 HFA384x_RID_CURRENTCHANNELHFA384x_RID_CURRENTCHANNEL ((UINT16)0xFDC1) hfa384x.h 　
21779
 HFA384x_RID_CURRENTPOWERSTATEHFA384x_RID_CURRENTPOWERSTATE ((UINT16)0xFDC2) hfa384x.h 　
21780
 HFA384x_RID_CCAMODEHFA384x_RID_CCAMODE ((UINT16)0xFDC3) hfa384x.h 　
21781
 HFA384x_RID_SUPPORTEDDATARATESHFA384x_RID_SUPPORTEDDATARATES ((UINT16)0xFDC6) hfa384x.h 　
21782
 HFA384x_RID_LFOSTATUSHFA384x_RID_LFOSTATUS ((UINT16)0xFDC7) hfa384x.h 1.7.1
21783
 HFA384x_RID_PHYTYPE_LENHFA384x_RID_PHYTYPE_LEN ((UINT16)0) hfa384x.h 　
21784
 HFA384x_RID_CURRENTCHANNEL_LENHFA384x_RID_CURRENTCHANNEL_LEN ((UINT16)0) hfa384x.h 　
21785
 HFA384x_RID_CURRENTPOWERSTATE_LHFA384x_RID_CURRENTPOWERSTATE_L ((UINT16)0) hfa384x.h 　
21786
 HFA384x_RID_CCAMODE_LENHFA384x_RID_CCAMODE_LEN ((UINT16)0) hfa384x.h 　
21787
 HFA384x_RID_SUPPORTEDDATARATES_HFA384x_RID_SUPPORTEDDATARATES_ ((UINT16)10) hfa384x.h 　
21788
 HFA384x_RID_CNFWEPDEFAULTKEYIDHFA384x_RID_CNFWEPDEFAULTKEYID ((UINT16)0xFC23) hfa384x.h 　
21789
 HFA384x_RID_CNFWEPDEFAULTKEY0HFA384x_RID_CNFWEPDEFAULTKEY0 ((UINT16)0xFC24) hfa384x.h 　
21790
 HFA384x_RID_CNFWEPDEFAULTKEY1HFA384x_RID_CNFWEPDEFAULTKEY1 ((UINT16)0xFC25) hfa384x.h 　
21791
 HFA384x_RID_CNFWEPDEFAULTKEY2HFA384x_RID_CNFWEPDEFAULTKEY2 ((UINT16)0xFC26) hfa384x.h 　
21792
 HFA384x_RID_CNFWEPDEFAULTKEY3HFA384x_RID_CNFWEPDEFAULTKEY3 ((UINT16)0xFC27) hfa384x.h 　
21793
 HFA384x_RID_CNFWEPFLAGSHFA384x_RID_CNFWEPFLAGS ((UINT16)0xFC28) hfa384x.h 　
21794
 HFA384x_RID_CNFWEPKEYMAPTABLEHFA384x_RID_CNFWEPKEYMAPTABLE ((UINT16)0xFC29) hfa384x.h 　
21795
 HFA384x_RID_CNFAUTHENTICATIONHFA384x_RID_CNFAUTHENTICATION ((UINT16)0xFC2A) hfa384x.h 　
21796
 HFA384x_RID_CNFMAXASSOCSTATIONSHFA384x_RID_CNFMAXASSOCSTATIONS ((UINT16)0xFC2B) hfa384x.h 　
21797
 HFA384x_RID_CNFTXCONTROLHFA384x_RID_CNFTXCONTROL ((UINT16)0xFC2C) hfa384x.h 　
21798
 HFA384x_RID_CNFROAMINGMODEHFA384x_RID_CNFROAMINGMODE ((UINT16)0xFC2D) hfa384x.h 　
21799
 HFA384x_RID_CNFHOSTAUTHASSOCHFA384x_RID_CNFHOSTAUTHASSOC ((UINT16)0xFC2E) hfa384x.h 　
21800
 HFA384x_RID_CNFRCVCRCERRORHFA384x_RID_CNFRCVCRCERROR ((UINT16)0xFC30) hfa384x.h 　
21801
 HFA384x_RID_CNFALTRETRYCNTHFA384x_RID_CNFALTRETRYCNT ((UINT16)0xFC32) hfa384x.h 　
21802
 HFA384x_RID_CNFAPBCNINTHFA384x_RID_CNFAPBCNINT ((UINT16)0xFC33) hfa384x.h 　
21803
 HFA384x_RID_CNFAPPCFINFOHFA384x_RID_CNFAPPCFINFO ((UINT16)0xFC34) hfa384x.h 　
21804
 HFA384x_RID_CNFSTAPCFINFOHFA384x_RID_CNFSTAPCFINFO ((UINT16)0xFC35) hfa384x.h 　
21805
 HFA384x_RID_CNFPRIORITYQUSAGEHFA384x_RID_CNFPRIORITYQUSAGE ((UINT16)0xFC37) hfa384x.h 　
21806
 HFA384x_RID_CNFTIMCTRLHFA384x_RID_CNFTIMCTRL ((UINT16)0xFC40) hfa384x.h 　
21807
 HFA384x_RID_CNFTHIRTY2TALLYHFA384x_RID_CNFTHIRTY2TALLY ((UINT16)0xFC42) hfa384x.h 　
21808
 HFA384x_RID_CNFENHSECURITYHFA384x_RID_CNFENHSECURITY ((UINT16)0xFC43) hfa384x.h 　
21809
 HFA384x_RID_CNFDBMADJUSTHFA384x_RID_CNFDBMADJUST ((UINT16)0xFC46) hfa384x.h NEW
21810
 HFA384x_RID_CNFWPADATAHFA384x_RID_CNFWPADATA ((UINT16)0xFC48) hfa384x.h 1.7.0
21811
 HFA384x_RID_CNFPROPOGATIONDELAYHFA384x_RID_CNFPROPOGATIONDELAY ((UINT16)0xFC49) hfa384x.h 1.7.6
21812
 HFA384x_RID_CNFSHORTPREAMBLEHFA384x_RID_CNFSHORTPREAMBLE ((UINT16)0xFCB0) hfa384x.h 　
21813
 HFA384x_RID_CNFEXCLONGPREAMBLEHFA384x_RID_CNFEXCLONGPREAMBLE ((UINT16)0xFCB1) hfa384x.h 　
21814
 HFA384x_RID_CNFAUTHRSPTIMEOUTHFA384x_RID_CNFAUTHRSPTIMEOUT ((UINT16)0xFCB2) hfa384x.h 　
21815
 HFA384x_RID_CNFBASICRATESHFA384x_RID_CNFBASICRATES ((UINT16)0xFCB3) hfa384x.h 　
21816
 HFA384x_RID_CNFSUPPRATESHFA384x_RID_CNFSUPPRATES ((UINT16)0xFCB4) hfa384x.h 　
21817
 HFA384x_RID_CNFFALLBACKCTRLHFA384x_RID_CNFFALLBACKCTRL ((UINT16)0xFCB5) hfa384x.h NEW
21818
 HFA384x_RID_WEPKEYSTATUSHFA384x_RID_WEPKEYSTATUS ((UINT16)0xFCB6) hfa384x.h NEW
21819
 HFA384x_RID_WEPKEYMAPINDEXHFA384x_RID_WEPKEYMAPINDEX ((UINT16)0xFCB7) hfa384x.h NEW
21820
 HFA384x_RID_BROADCASTKEYIDHFA384x_RID_BROADCASTKEYID ((UINT16)0xFCB8) hfa384x.h NEW
21821
 HFA384x_RID_ENTSECFLAGEYIDHFA384x_RID_ENTSECFLAGEYID ((UINT16)0xFCB9) hfa384x.h NEW
21822
 HFA384x_RID_CNFPASSIVESCANCTRLHFA384x_RID_CNFPASSIVESCANCTRL ((UINT16)0xFCBA) hfa384x.h NEW STA
21823
 HFA384x_RID_CNFWPAHANDLINGHFA384x_RID_CNFWPAHANDLING ((UINT16)0xFCBB) hfa384x.h 1.7.0
21824
 HFA384x_RID_MDCCONTROLHFA384x_RID_MDCCONTROL ((UINT16)0xFCBC) hfa384x.h 1.7.0/1.4.0
21825
 HFA384x_RID_MDCCOUNTRYHFA384x_RID_MDCCOUNTRY ((UINT16)0xFCBD) hfa384x.h 1.7.0/1.4.0
21826
 HFA384x_RID_TXPOWERMAXHFA384x_RID_TXPOWERMAX ((UINT16)0xFCBE) hfa384x.h 1.7.0/1.4.0
21827
 HFA384x_RID_CNFLFOENBLEDHFA384x_RID_CNFLFOENBLED ((UINT16)0xFCBF) hfa384x.h 1.6.3
21828
 HFA384x_RID_CAPINFOHFA384x_RID_CAPINFO ((UINT16)0xFCC0) hfa384x.h 1.7.0/1.3.7
21829
 HFA384x_RID_LISTENINTERVALHFA384x_RID_LISTENINTERVAL ((UINT16)0xFCC1) hfa384x.h 1.7.0/1.3.7
21830
 HFA384x_RID_DIVERSITYENABLEDHFA384x_RID_DIVERSITYENABLED ((UINT16)0xFCC2) hfa384x.h 1.7.0/1.3.7
21831
 HFA384x_RID_LED_CONTROLHFA384x_RID_LED_CONTROL ((UINT16)0xFCC4) hfa384x.h 1.7.6
21832
 HFA384x_RID_HFO_DELAYHFA384x_RID_HFO_DELAY ((UINT16)0xFCC5) hfa384x.h 1.7.6
21833
 HFA384x_RID_DISSALOWEDBSSIDHFA384x_RID_DISSALOWEDBSSID ((UINT16)0xFCC6) hfa384x.h 1.8.0
21834
 HFA384x_RID_SCANREQUESTHFA384x_RID_SCANREQUEST ((UINT16)0xFCE1) hfa384x.h 　
21835
 HFA384x_RID_JOINREQUESTHFA384x_RID_JOINREQUEST ((UINT16)0xFCE2) hfa384x.h 　
21836
 HFA384x_RID_AUTHENTICATESTAHFA384x_RID_AUTHENTICATESTA ((UINT16)0xFCE3) hfa384x.h 　
21837
 HFA384x_RID_CHANNELINFOREQUESTHFA384x_RID_CHANNELINFOREQUEST ((UINT16)0xFCE4) hfa384x.h 　
21838
 HFA384x_RID_HOSTSCANHFA384x_RID_HOSTSCAN ((UINT16)0xFCE5) hfa384x.h NEW STA
21839
 HFA384x_RID_ASSOCIATESTAHFA384x_RID_ASSOCIATESTA ((UINT16)0xFCE6) hfa384x.h 　
21840
 HFA384x_RID_CNFWEPDEFAULTKEY_LEHFA384x_RID_CNFWEPDEFAULTKEY_LE ((UINT16)6) hfa384x.h 　
21841
 HFA384x_RID_CNFWEP128DEFAULTKEYHFA384x_RID_CNFWEP128DEFAULTKEY ((UINT16)14) hfa384x.h 　
21842
 HFA384x_RID_CNFPRIOQUSAGE_LENHFA384x_RID_CNFPRIOQUSAGE_LEN ((UINT16)4) hfa384x.h 　
21843
 HFA384x_PDR_PCB_PARTNUMHFA384x_PDR_PCB_PARTNUM ((UINT16)0x0001) hfa384x.h 　
21844
 HFA384x_PDR_PDAVERHFA384x_PDR_PDAVER ((UINT16)0x0002) hfa384x.h 　
21845
 HFA384x_PDR_NIC_SERIALHFA384x_PDR_NIC_SERIAL ((UINT16)0x0003) hfa384x.h 　
21846
 HFA384x_PDR_MKK_MEASUREMENTSHFA384x_PDR_MKK_MEASUREMENTS ((UINT16)0x0004) hfa384x.h 　
21847
 HFA384x_PDR_NIC_RAMSIZEHFA384x_PDR_NIC_RAMSIZE ((UINT16)0x0005) hfa384x.h 　
21848
 HFA384x_PDR_MFISUPRANGEHFA384x_PDR_MFISUPRANGE ((UINT16)0x0006) hfa384x.h 　
21849
 HFA384x_PDR_CFISUPRANGEHFA384x_PDR_CFISUPRANGE ((UINT16)0x0007) hfa384x.h 　
21850
 HFA384x_PDR_NICIDHFA384x_PDR_NICID ((UINT16)0x0008) hfa384x.h 　
21851
 HFA384x_PDR_MAC_ADDRESSHFA384x_PDR_MAC_ADDRESS ((UINT16)0x0101) hfa384x.h 　
21852
 HFA384x_PDR_REGDOMAINHFA384x_PDR_REGDOMAIN ((UINT16)0x0103) hfa384x.h 　
21853
 HFA384x_PDR_ALLOWED_CHANNELHFA384x_PDR_ALLOWED_CHANNEL ((UINT16)0x0104) hfa384x.h 　
21854
 HFA384x_PDR_DEFAULT_CHANNELHFA384x_PDR_DEFAULT_CHANNEL ((UINT16)0x0105) hfa384x.h 　
21855
 HFA384x_PDR_TEMPTYPEHFA384x_PDR_TEMPTYPE ((UINT16)0x0107) hfa384x.h 　
21856
 HFA384x_PDR_IFR_SETTINGHFA384x_PDR_IFR_SETTING ((UINT16)0x0200) hfa384x.h 　
21857
 HFA384x_PDR_RFR_SETTINGHFA384x_PDR_RFR_SETTING ((UINT16)0x0201) hfa384x.h 　
21858
 HFA384x_PDR_HFA3861_BASELINEHFA384x_PDR_HFA3861_BASELINE ((UINT16)0x0202) hfa384x.h 　
21859
 HFA384x_PDR_HFA3861_SHADOWHFA384x_PDR_HFA3861_SHADOW ((UINT16)0x0203) hfa384x.h 　
21860
 HFA384x_PDR_HFA3861_IFRFHFA384x_PDR_HFA3861_IFRF ((UINT16)0x0204) hfa384x.h 　
21861
 HFA384x_PDR_HFA3861_CHCALSPHFA384x_PDR_HFA3861_CHCALSP ((UINT16)0x0300) hfa384x.h 　
21862
 HFA384x_PDR_HFA3861_CHCALIHFA384x_PDR_HFA3861_CHCALI ((UINT16)0x0301) hfa384x.h 　
21863
 HFA384x_PDR_MAX_TX_POWERHFA384x_PDR_MAX_TX_POWER ((UINT16)0x0302) hfa384x.h 　
21864
 HFA384x_PDR_MASTER_CHAN_LISTHFA384x_PDR_MASTER_CHAN_LIST ((UINT16)0x0303) hfa384x.h 　
21865
 HFA384x_PDR_3842_NIC_CONFIGHFA384x_PDR_3842_NIC_CONFIG ((UINT16)0x0400) hfa384x.h 　
21866
 HFA384x_PDR_USB_IDHFA384x_PDR_USB_ID ((UINT16)0x0401) hfa384x.h 　
21867
 HFA384x_PDR_PCI_IDHFA384x_PDR_PCI_ID ((UINT16)0x0402) hfa384x.h 　
21868
 HFA384x_PDR_PCI_IFCONFHFA384x_PDR_PCI_IFCONF ((UINT16)0x0403) hfa384x.h 　
21869
 HFA384x_PDR_PCI_PMCONFHFA384x_PDR_PCI_PMCONF ((UINT16)0x0404) hfa384x.h 　
21870
 HFA384x_PDR_RFENRGYHFA384x_PDR_RFENRGY ((UINT16)0x0406) hfa384x.h 　
21871
 HFA384x_PDR_USB_POWER_TYPEHFA384x_PDR_USB_POWER_TYPE ((UINT16)0x0407) hfa384x.h 　
21872
 HFA384x_PDR_USB_MAX_POWERHFA384x_PDR_USB_MAX_POWER ((UINT16)0x0409) hfa384x.h 　
21873
 HFA384x_PDR_USB_MANUFACTURERHFA384x_PDR_USB_MANUFACTURER ((UINT16)0x0410) hfa384x.h 　
21874
 HFA384x_PDR_USB_PRODUCTHFA384x_PDR_USB_PRODUCT ((UINT16)0x0411) hfa384x.h 　
21875
 HFA384x_PDR_ANT_DIVERSITYHFA384x_PDR_ANT_DIVERSITY ((UINT16)0x0412) hfa384x.h 　
21876
 HFA384x_PDR_HFO_DELAYHFA384x_PDR_HFO_DELAY ((UINT16)0x0413) hfa384x.h 　
21877
 HFA384x_PDR_SCALE_THRESHHFA384x_PDR_SCALE_THRESH ((UINT16)0x0414) hfa384x.h 　
21878
 HFA384x_PDR_HFA3861_MANF_TESTSPHFA384x_PDR_HFA3861_MANF_TESTSP ((UINT16)0x0900) hfa384x.h 　
21879
 HFA384x_PDR_HFA3861_MANF_TESTIHFA384x_PDR_HFA3861_MANF_TESTI ((UINT16)0x0901) hfa384x.h 　
21880
 HFA384x_PDR_END_OF_PDAHFA384x_PDR_END_OF_PDA ((UINT16)0x0000) hfa384x.h 　
21881
 HFA384x_CMDHFA384x_CMD HFA384x_CMD_OFF hfa384x.h 　
21882
 HFA384x_PARAM0HFA384x_PARAM0 HFA384x_PARAM0_OFF hfa384x.h 　
21883
 HFA384x_PARAM1HFA384x_PARAM1 HFA384x_PARAM1_OFF hfa384x.h 　
21884
 HFA384x_PARAM2HFA384x_PARAM2 HFA384x_PARAM2_OFF hfa384x.h 　
21885
 HFA384x_STATUSHFA384x_STATUS HFA384x_STATUS_OFF hfa384x.h 　
21886
 HFA384x_RESP0HFA384x_RESP0 HFA384x_RESP0_OFF hfa384x.h 　
21887
 HFA384x_RESP1HFA384x_RESP1 HFA384x_RESP1_OFF hfa384x.h 　
21888
 HFA384x_RESP2HFA384x_RESP2 HFA384x_RESP2_OFF hfa384x.h 　
21889
 HFA384x_INFOFIDHFA384x_INFOFID HFA384x_INFOFID_OFF hfa384x.h 　
21890
 HFA384x_RXFIDHFA384x_RXFID HFA384x_RXFID_OFF hfa384x.h 　
21891
 HFA384x_ALLOCFIDHFA384x_ALLOCFID HFA384x_ALLOCFID_OFF hfa384x.h 　
21892
 HFA384x_TXCOMPLFIDHFA384x_TXCOMPLFID HFA384x_TXCOMPLFID_OFF hfa384x.h 　
21893
 HFA384x_SELECT0HFA384x_SELECT0 HFA384x_SELECT0_OFF hfa384x.h 　
21894
 HFA384x_OFFSET0HFA384x_OFFSET0 HFA384x_OFFSET0_OFF hfa384x.h 　
21895
 HFA384x_DATA0HFA384x_DATA0 HFA384x_DATA0_OFF hfa384x.h 　
21896
 HFA384x_SELECT1HFA384x_SELECT1 HFA384x_SELECT1_OFF hfa384x.h 　
21897
 HFA384x_OFFSET1HFA384x_OFFSET1 HFA384x_OFFSET1_OFF hfa384x.h 　
21898
 HFA384x_DATA1HFA384x_DATA1 HFA384x_DATA1_OFF hfa384x.h 　
21899
 HFA384x_EVSTATHFA384x_EVSTAT HFA384x_EVSTAT_OFF hfa384x.h 　
21900
 HFA384x_INTENHFA384x_INTEN HFA384x_INTEN_OFF hfa384x.h 　
21901
 HFA384x_EVACKHFA384x_EVACK HFA384x_EVACK_OFF hfa384x.h 　
21902
 HFA384x_CONTROLHFA384x_CONTROL HFA384x_CONTROL_OFF hfa384x.h 　
21903
 HFA384x_SWSUPPORT0HFA384x_SWSUPPORT0 HFA384x_SWSUPPORT0_OFF hfa384x.h 　
21904
 HFA384x_SWSUPPORT1HFA384x_SWSUPPORT1 HFA384x_SWSUPPORT1_OFF hfa384x.h 　
21905
 HFA384x_SWSUPPORT2HFA384x_SWSUPPORT2 HFA384x_SWSUPPORT2_OFF hfa384x.h 　
21906
 HFA384x_AUXPAGEHFA384x_AUXPAGE HFA384x_AUXPAGE_OFF hfa384x.h 　
21907
 HFA384x_AUXOFFSETHFA384x_AUXOFFSET HFA384x_AUXOFFSET_OFF hfa384x.h 　
21908
 HFA384x_AUXDATAHFA384x_AUXDATA HFA384x_AUXDATA_OFF hfa384x.h 　
21909
 HFA384x_PCICORHFA384x_PCICOR HFA384x_PCICOR_OFF hfa384x.h 　
21910
 HFA384x_PCIHCRHFA384x_PCIHCR HFA384x_PCIHCR_OFF hfa384x.h 　
21911
 HFA384x_STATE_PREINITHFA384x_STATE_PREINIT 0 hfa384x.h 　
21912
 HFA384x_STATE_INITHFA384x_STATE_INIT 1 hfa384x.h 　
21913
 HFA384x_STATE_RUNNINGHFA384x_STATE_RUNNING 2 hfa384x.h 　
21914
 HFA384x_HOSTAUTHASSOC_HOSTAUTHHFA384x_HOSTAUTHASSOC_HOSTAUTH BIT0 hfa384x.h 　
21915
 HFA384x_HOSTAUTHASSOC_HOSTASSOCHFA384x_HOSTAUTHASSOC_HOSTASSOC BIT1 hfa384x.h 　
21916
 HFA384x_WHAHANDLING_DISABLEDHFA384x_WHAHANDLING_DISABLED 0 hfa384x.h 　
21917
 HFA384x_WHAHANDLING_PASSTHROUGHHFA384x_WHAHANDLING_PASSTHROUGH BIT1 hfa384x.h 　
21918
 HFA384x_CNFAUTHENTICATION_OPENSHFA384x_CNFAUTHENTICATION_OPENS 0x0001 hfa384x.h 　
21919
 HFA384x_CNFAUTHENTICATION_SHAREHFA384x_CNFAUTHENTICATION_SHARE 0x0002 hfa384x.h 　
21920
 HFA384x_CNFAUTHENTICATION_LEAPHFA384x_CNFAUTHENTICATION_LEAP 0x0004 hfa384x.h 　
21921
 HFA384x_CREATEIBSS_JOINCREATEIBHFA384x_CREATEIBSS_JOINCREATEIB 0 hfa384x.h 　
21922
 HFA384x_CREATEIBSS_JOINESS_JOINHFA384x_CREATEIBSS_JOINESS_JOIN 1 hfa384x.h 　
21923
 HFA384x_CREATEIBSS_JOINIBSSHFA384x_CREATEIBSS_JOINIBSS 2 hfa384x.h 　
21924
 HFA384x_CREATEIBSS_JOINESS_JOINHFA384x_CREATEIBSS_JOINESS_JOIN 3 hfa384x.h 　
21925
 HFA384x_FWID_LENHFA384x_FWID_LEN 14 hfa384x.h 　
21926
 HFA384x_PSTATUS_DISABLEDHFA384x_PSTATUS_DISABLED ((UINT16)1) hfa384x.h 　
21927
 HFA384x_PSTATUS_SEARCHINGHFA384x_PSTATUS_SEARCHING ((UINT16)2) hfa384x.h 　
21928
 HFA384x_PSTATUS_CONN_IBSSHFA384x_PSTATUS_CONN_IBSS ((UINT16)3) hfa384x.h 　
21929
 HFA384x_PSTATUS_CONN_ESSHFA384x_PSTATUS_CONN_ESS ((UINT16)4) hfa384x.h 　
21930
 HFA384x_PSTATUS_OUTOFRANGEHFA384x_PSTATUS_OUTOFRANGE ((UINT16)5) hfa384x.h 　
21931
 HFA384x_PSTATUS_CONN_WDSHFA384x_PSTATUS_CONN_WDS ((UINT16)6) hfa384x.h 　
21932
 HFA384x_TESTRESULT_ALLPASSEDHFA384x_TESTRESULT_ALLPASSED BIT0 hfa384x.h 　
21933
 HFA384x_TESTRESULT_LFO_FAILHFA384x_TESTRESULT_LFO_FAIL BIT1 hfa384x.h 　
21934
 HFA384x_TESTRESULT_VR_HF0_FAILHFA384x_TESTRESULT_VR_HF0_FAIL BIT2 hfa384x.h 　
21935
 HFA384x_HOST_FIRM_COORDINATEHFA384x_HOST_FIRM_COORDINATE BIT7 hfa384x.h 　
21936
 HFA384x_TESTRESULT_COORDINATEHFA384x_TESTRESULT_COORDINATE BIT15 hfa384x.h 　
21937
 HFA384x_FD_STATUS_OFFHFA384x_FD_STATUS_OFF ((UINT16)0x44) hfa384x.h 　
21938
 HFA384x_FD_TIME_OFFHFA384x_FD_TIME_OFF ((UINT16)0x46) hfa384x.h 　
21939
 HFA384x_FD_SWSUPPORT_OFFHFA384x_FD_SWSUPPORT_OFF ((UINT16)0x4A) hfa384x.h 　
21940
 HFA384x_FD_SILENCE_OFFHFA384x_FD_SILENCE_OFF ((UINT16)0x4A) hfa384x.h 　
21941
 HFA384x_FD_SIGNAL_OFFHFA384x_FD_SIGNAL_OFF ((UINT16)0x4B) hfa384x.h 　
21942
 HFA384x_FD_RATE_OFFHFA384x_FD_RATE_OFF ((UINT16)0x4C) hfa384x.h 　
21943
 HFA384x_FD_RXFLOW_OFFHFA384x_FD_RXFLOW_OFF ((UINT16)0x4D) hfa384x.h 　
21944
 HFA384x_FD_RESERVED_OFFHFA384x_FD_RESERVED_OFF ((UINT16)0x4E) hfa384x.h 　
21945
 HFA384x_FD_TXCONTROL_OFFHFA384x_FD_TXCONTROL_OFF ((UINT16)0x50) hfa384x.h 　
21946
 HFA384x_FD_FRAMECONTROL_OFFHFA384x_FD_FRAMECONTROL_OFF ((UINT16)0x52) hfa384x.h 　
21947
 HFA384x_FD_DURATIONID_OFFHFA384x_FD_DURATIONID_OFF ((UINT16)0x54) hfa384x.h 　
21948
 HFA384x_FD_ADDRESS1_OFFHFA384x_FD_ADDRESS1_OFF ((UINT16)0x56) hfa384x.h 　
21949
 HFA384x_FD_ADDRESS2_OFFHFA384x_FD_ADDRESS2_OFF ((UINT16)0x5C) hfa384x.h 　
21950
 HFA384x_FD_ADDRESS3_OFFHFA384x_FD_ADDRESS3_OFF ((UINT16)0x62) hfa384x.h 　
21951
 HFA384x_FD_SEQCONTROL_OFFHFA384x_FD_SEQCONTROL_OFF ((UINT16)0x68) hfa384x.h 　
21952
 HFA384x_FD_ADDRESS4_OFFHFA384x_FD_ADDRESS4_OFF ((UINT16)0x6A) hfa384x.h 　
21953
 HFA384x_FD_DATALEN_OFFHFA384x_FD_DATALEN_OFF ((UINT16)0x70) hfa384x.h 　
21954
 HFA384x_FD_DESTADDRESS_OFFHFA384x_FD_DESTADDRESS_OFF ((UINT16)0x72) hfa384x.h 　
21955
 HFA384x_FD_SRCADDRESS_OFFHFA384x_FD_SRCADDRESS_OFF ((UINT16)0x78) hfa384x.h 　
21956
 HFA384x_FD_DATALENGTH_OFFHFA384x_FD_DATALENGTH_OFF ((UINT16)0x7E) hfa384x.h 　
21957
 HFA384x_TXSTATUS_ACKERRHFA384x_TXSTATUS_ACKERR ((UINT16)BIT5) hfa384x.h 　
21958
 HFA384x_TXSTATUS_FORMERRHFA384x_TXSTATUS_FORMERR ((UINT16)BIT3) hfa384x.h 　
21959
 HFA384x_TXSTATUS_DISCONHFA384x_TXSTATUS_DISCON ((UINT16)BIT2) hfa384x.h 　
21960
 HFA384x_TXSTATUS_AGEDERRHFA384x_TXSTATUS_AGEDERR ((UINT16)BIT1) hfa384x.h 　
21961
 HFA384x_TXSTATUS_RETRYERRHFA384x_TXSTATUS_RETRYERR ((UINT16)BIT0) hfa384x.h 　
21962
 HFA384x_TX_CFPOLLHFA384x_TX_CFPOLL ((UINT16)BIT12) hfa384x.h 　
21963
 HFA384x_TX_PRSTHFA384x_TX_PRST ((UINT16)BIT11) hfa384x.h 　
21964
 HFA384x_TX_MACPORTHFA384x_TX_MACPORT ((UINT16)(BIT10 | BIT9 | BIT8)) hfa384x.h 　
21965
 HFA384x_TX_NOENCRYPTHFA384x_TX_NOENCRYPT ((UINT16)BIT7) hfa384x.h 　
21966
 HFA384x_TX_RETRYSTRATHFA384x_TX_RETRYSTRAT ((UINT16)(BIT6 | BIT5)) hfa384x.h 　
21967
 HFA384x_TX_STRUCTYPEHFA384x_TX_STRUCTYPE ((UINT16)(BIT4 | BIT3)) hfa384x.h 　
21968
 HFA384x_TX_TXEXHFA384x_TX_TXEX ((UINT16)BIT2) hfa384x.h 　
21969
 HFA384x_TX_TXOKHFA384x_TX_TXOK ((UINT16)BIT1) hfa384x.h 　
21970
 HFA384x_RX_DATA_LEN_OFFHFA384x_RX_DATA_LEN_OFF ((UINT16)44) hfa384x.h 　
21971
 HFA384x_RX_80211HDR_OFFHFA384x_RX_80211HDR_OFF ((UINT16)14) hfa384x.h 　
21972
 HFA384x_RX_DATA_OFFHFA384x_RX_DATA_OFF ((UINT16)60) hfa384x.h 　
21973
 HFA384x_RXSTATUS_MSGTYPEHFA384x_RXSTATUS_MSGTYPE ((UINT16)(BIT15 | BIT14 | BIT13)) hfa384x.h 　
21974
 HFA384x_RXSTATUS_MACPORTHFA384x_RXSTATUS_MACPORT ((UINT16)(BIT10 | BIT9 | BIT8)) hfa384x.h 　
21975
 HFA384x_RXSTATUS_UNDECRHFA384x_RXSTATUS_UNDECR ((UINT16)BIT1) hfa384x.h 　
21976
 HFA384x_RXSTATUS_FCSERRHFA384x_RXSTATUS_FCSERR ((UINT16)BIT0) hfa384x.h 　
21977
 HFA384x_IT_HANDOVERADDRHFA384x_IT_HANDOVERADDR ((UINT16)0xF000UL) hfa384x.h 　
21978
 HFA384x_IT_HANDOVERDEAUTHADDRESHFA384x_IT_HANDOVERDEAUTHADDRES ((UINT16)0xF001UL) hfa384x.h AP 1.3.7
21979
 HFA384x_IT_COMMTALLIESHFA384x_IT_COMMTALLIES ((UINT16)0xF100UL) hfa384x.h 　
21980
 HFA384x_IT_SCANRESULTSHFA384x_IT_SCANRESULTS ((UINT16)0xF101UL) hfa384x.h 　
21981
 HFA384x_IT_CHINFORESULTSHFA384x_IT_CHINFORESULTS ((UINT16)0xF102UL) hfa384x.h 　
21982
 HFA384x_IT_HOSTSCANRESULTSHFA384x_IT_HOSTSCANRESULTS ((UINT16)0xF103UL) hfa384x.h 　
21983
 HFA384x_IT_LINKSTATUSHFA384x_IT_LINKSTATUS ((UINT16)0xF200UL) hfa384x.h 　
21984
 HFA384x_IT_ASSOCSTATUSHFA384x_IT_ASSOCSTATUS ((UINT16)0xF201UL) hfa384x.h 　
21985
 HFA384x_IT_AUTHREQHFA384x_IT_AUTHREQ ((UINT16)0xF202UL) hfa384x.h 　
21986
 HFA384x_IT_PSUSERCNTHFA384x_IT_PSUSERCNT ((UINT16)0xF203UL) hfa384x.h 　
21987
 HFA384x_IT_KEYIDCHANGEDHFA384x_IT_KEYIDCHANGED ((UINT16)0xF204UL) hfa384x.h 　
21988
 HFA384x_IT_ASSOCREQHFA384x_IT_ASSOCREQ ((UINT16)0xF205UL) hfa384x.h 　
21989
 HFA384x_IT_MICFAILUREHFA384x_IT_MICFAILURE ((UINT16)0xF206UL) hfa384x.h 　
21990
 HFA384x_CHINFORESULT_BSSACTIVEHFA384x_CHINFORESULT_BSSACTIVE BIT0 hfa384x.h 　
21991
 HFA384x_CHINFORESULT_PCFACTIVEHFA384x_CHINFORESULT_PCFACTIVE BIT1 hfa384x.h 　
21992
 HFA384x_LINK_NOTCONNECTEDHFA384x_LINK_NOTCONNECTED ((UINT16)0) hfa384x.h 　
21993
 HFA384x_LINK_CONNECTEDHFA384x_LINK_CONNECTED ((UINT16)1) hfa384x.h 　
21994
 HFA384x_LINK_DISCONNECTEDHFA384x_LINK_DISCONNECTED ((UINT16)2) hfa384x.h 　
21995
 HFA384x_LINK_AP_CHANGEHFA384x_LINK_AP_CHANGE ((UINT16)3) hfa384x.h 　
21996
 HFA384x_LINK_AP_OUTOFRANGEHFA384x_LINK_AP_OUTOFRANGE ((UINT16)4) hfa384x.h 　
21997
 HFA384x_LINK_AP_INRANGEHFA384x_LINK_AP_INRANGE ((UINT16)5) hfa384x.h 　
21998
 HFA384x_LINK_ASSOCFAILHFA384x_LINK_ASSOCFAIL ((UINT16)6) hfa384x.h 　
21999
 HFA384x_ASSOCSTATUS_STAASSOCHFA384x_ASSOCSTATUS_STAASSOC ((UINT16)1) hfa384x.h 　
22000
 HFA384x_ASSOCSTATUS_REASSOCHFA384x_ASSOCSTATUS_REASSOC ((UINT16)2) hfa384x.h 　
22001
 HFA384x_ASSOCSTATUS_DISASSOCHFA384x_ASSOCSTATUS_DISASSOC ((UINT16)3) hfa384x.h 　
22002
 HFA384x_ASSOCSTATUS_ASSOCFAILHFA384x_ASSOCSTATUS_ASSOCFAIL ((UINT16)4) hfa384x.h 　
22003
 HFA384x_ASSOCSTATUS_AUTHFAILHFA384x_ASSOCSTATUS_AUTHFAIL ((UINT16)5) hfa384x.h 　
22004
 HFA384x_ASSOCREQ_TYPE_ASSOCHFA384x_ASSOCREQ_TYPE_ASSOC 0 hfa384x.h 　
22005
 HFA384x_ASSOCREQ_TYPE_REASSOCHFA384x_ASSOCREQ_TYPE_REASSOC 1 hfa384x.h 　
22006
 HFA384x_USB_ENBULKINHFA384x_USB_ENBULKIN 6 hfa384x.h 　
22007
 HFA384x_USB_TXFRMHFA384x_USB_TXFRM 0 hfa384x.h 　
22008
 HFA384x_USB_CMDREQHFA384x_USB_CMDREQ 1 hfa384x.h 　
22009
 HFA384x_USB_WRIDREQHFA384x_USB_WRIDREQ 2 hfa384x.h 　
22010
 HFA384x_USB_RRIDREQHFA384x_USB_RRIDREQ 3 hfa384x.h 　
22011
 HFA384x_USB_WMEMREQHFA384x_USB_WMEMREQ 4 hfa384x.h 　
22012
 HFA384x_USB_RMEMREQHFA384x_USB_RMEMREQ 5 hfa384x.h 　
22013
 HFA384x_USB_INFOFRMHFA384x_USB_INFOFRM 0x8000 hfa384x.h 　
22014
 HFA384x_USB_CMDRESPHFA384x_USB_CMDRESP 0x8001 hfa384x.h 　
22015
 HFA384x_USB_WRIDRESPHFA384x_USB_WRIDRESP 0x8002 hfa384x.h 　
22016
 HFA384x_USB_RRIDRESPHFA384x_USB_RRIDRESP 0x8003 hfa384x.h 　
22017
 HFA384x_USB_WMEMRESPHFA384x_USB_WMEMRESP 0x8004 hfa384x.h 　
22018
 HFA384x_USB_RMEMRESPHFA384x_USB_RMEMRESP 0x8005 hfa384x.h 　
22019
 HFA384x_USB_BUFAVAILHFA384x_USB_BUFAVAIL 0x8006 hfa384x.h 　
22020
 HFA384x_USB_ERRORHFA384x_USB_ERROR 0x8007 hfa384x.h 　
22021
 MAX_PRISM2_GRP_ADDRMAX_PRISM2_GRP_ADDR 16 hfa384x.h 　
22022
 MAX_GRP_ADDRMAX_GRP_ADDR 32 hfa384x.h 　
22023
 WLAN_COMMENT_MAXWLAN_COMMENT_MAX 80 hfa384x.h Max. length of user comment string.
22024
 MM_SAT_PCFMM_SAT_PCF (BIT14) hfa384x.h 　
22025
 MM_GCSD_PCFMM_GCSD_PCF (BIT15) hfa384x.h 　
22026
 MM_GCSD_PCF_EBMM_GCSD_PCF_EB (BIT14 | BIT15) hfa384x.h 　
22027
 WLAN_STATE_STOPPEDWLAN_STATE_STOPPED 0 hfa384x.h Network is not active.
22028
 WLAN_STATE_STARTEDWLAN_STATE_STARTED 1 hfa384x.h Network has been started.
22029
 WLAN_AUTH_MAXWLAN_AUTH_MAX 60 hfa384x.h Max. # of authenticated stations.
22030
 WLAN_ACCESS_MAXWLAN_ACCESS_MAX 60 hfa384x.h Max. # of stations in an access list.
22031
 WLAN_ACCESS_NONEWLAN_ACCESS_NONE 0 hfa384x.h No stations may be authenticated.
22032
 WLAN_ACCESS_ALLWLAN_ACCESS_ALL 1 hfa384x.h All stations may be authenticated.
22033
 WLAN_ACCESS_ALLOWWLAN_ACCESS_ALLOW 2 hfa384x.h Authenticate only "allowed" stations.
22034
 WLAN_ACCESS_DENYWLAN_ACCESS_DENY 3 hfa384x.h Do not authenticate "denied" stations.
22035
 hfa384x_getreghfa384x_getreg __hfa384x_getreg_noswap hfa384x.h 　
22036
 hfa384x_setreghfa384x_setreg __hfa384x_setreg_noswap hfa384x.h 　
22037
 hfa384x_getreg_noswaphfa384x_getreg_noswap __hfa384x_getreg hfa384x.h 　
22038
 hfa384x_setreg_noswaphfa384x_setreg_noswap __hfa384x_setreg hfa384x.h 　
22039
 hfa384x_getreghfa384x_getreg __hfa384x_getreg hfa384x.h 　
22040
 hfa384x_setreghfa384x_setreg __hfa384x_setreg hfa384x.h 　
22041
 hfa384x_getreg_noswaphfa384x_getreg_noswap __hfa384x_getreg_noswap hfa384x.h 　
22042
 hfa384x_setreg_noswaphfa384x_setreg_noswap __hfa384x_setreg_noswap hfa384x.h 　
22043
 PCI_VENDOR_ID_JMICRONPCI_VENDOR_ID_JMICRON 0x197b jme.h 　
22044
 PCI_DEVICE_ID_JMICRON_JMC250PCI_DEVICE_ID_JMICRON_JMC250 0x0250 jme.h 　
22045
 PCI_DEVICE_ID_JMICRON_JMC260PCI_DEVICE_ID_JMICRON_JMC260 0x0260 jme.h 　
22046
 PCI_DCSR_MRRSPCI_DCSR_MRRS 0x59 jme.h 　
22047
 PCI_DCSR_MRRS_MASKPCI_DCSR_MRRS_MASK 0x70 jme.h 　
22048
 RING_DESC_ALIGNRING_DESC_ALIGN 16 jme.h Descriptor alignment
22049
 TX_DESC_SIZETX_DESC_SIZE 16 jme.h 　
22050
 TXDESC_MSS_SHIFTTXDESC_MSS_SHIFT 2 jme.h 　
22051
 RX_DESC_SIZERX_DESC_SIZE 16 jme.h 　
22052
 RX_BUF_DMA_ALIGNRX_BUF_DMA_ALIGN 8 jme.h 　
22053
 RX_PREPAD_SIZERX_PREPAD_SIZE 10 jme.h 　
22054
 ETH_CRC_LENETH_CRC_LEN 2 jme.h 　
22055
 RX_VLANHDR_LENRX_VLANHDR_LEN 2 jme.h 　
22056
 RX_EXTRA_LENRX_EXTRA_LEN (ETH_HLEN + \ ETH_CRC_LEN + \ RX_VLANHDR_LEN + \ RX_BUF_DMA_ALIGN) jme.h 　
22057
 FIXED_MTUFIXED_MTU 1500 jme.h 　
22058
 RX_ALLOC_LENRX_ALLOC_LEN (FIXED_MTU + RX_EXTRA_LEN) jme.h 　
22059
 JME_TX_DISABLE_TIMEOUTJME_TX_DISABLE_TIMEOUT 10 jme.h 10 msec
22060
 JME_RX_DISABLE_TIMEOUTJME_RX_DISABLE_TIMEOUT 10 jme.h 10 msec
22061
 WAKEUP_FRAME_NRWAKEUP_FRAME_NR 8 jme.h 　
22062
 WAKEUP_FRAME_MASK_DWNRWAKEUP_FRAME_MASK_DWNR 4 jme.h 　
22063
 JME_PHY_TIMEOUTJME_PHY_TIMEOUT 100 jme.h 100 msec
22064
 JME_PHY_REG_NRJME_PHY_REG_NR 32 jme.h 　
22065
 JME_SPDRSV_TIMEOUTJME_SPDRSV_TIMEOUT 500 jme.h 500 us
22066
 JME_EEPROM_RELOAD_TIMEOUTJME_EEPROM_RELOAD_TIMEOUT 2000 jme.h 2000 msec
22067
 JME_SMB_BUSY_TIMEOUTJME_SMB_BUSY_TIMEOUT 20 jme.h 20 msec
22068
 JME_SMB_LENJME_SMB_LEN 256 jme.h 　
22069
 JME_EEPROM_MAGICJME_EEPROM_MAGIC 0x250 jme.h 　
22070
 MTNIC_MAX_PORTSMTNIC_MAX_PORTS 2 mtnic.h 　
22071
 MTNIC_PORT1MTNIC_PORT1 0 mtnic.h 　
22072
 MTNIC_PORT2MTNIC_PORT2 1 mtnic.h 　
22073
 NUM_TX_RINGSNUM_TX_RINGS 1 mtnic.h 　
22074
 NUM_RX_RINGSNUM_RX_RINGS 1 mtnic.h 　
22075
 NUM_CQSNUM_CQS (NUM_RX_RINGS + NUM_TX_RINGS) mtnic.h 　
22076
 GO_BIT_TIMEOUTGO_BIT_TIMEOUT 6000 mtnic.h 　
22077
 TBIT_RETRIESTBIT_RETRIES 100 mtnic.h 　
22078
 UNITS_BUFFER_SIZEUNITS_BUFFER_SIZE 8 mtnic.h can be configured to 4/8/16
22079
 MAX_GAP_PROD_CONSMAX_GAP_PROD_CONS ( UNITS_BUFFER_SIZE / 4 ) mtnic.h 　
22080
 ETH_DEF_LENETH_DEF_LEN 1540 mtnic.h 40 bytes used by the card
22081
 ETH_FCS_LENETH_FCS_LEN 14 mtnic.h 　
22082
 DEF_MTUDEF_MTU ETH_DEF_LEN + ETH_FCS_LEN mtnic.h 　
22083
 DEF_IOBUF_SIZEDEF_IOBUF_SIZE ETH_DEF_LEN mtnic.h 　
22084
 MAC_ADDRESS_SIZEMAC_ADDRESS_SIZE 6 mtnic.h 　
22085
 NUM_EQESNUM_EQES 16 mtnic.h 　
22086
 ROUND_TO_CHECKROUND_TO_CHECK 0x400 mtnic.h 　
22087
 DELAY_LINK_CHECKDELAY_LINK_CHECK 300 mtnic.h 　
22088
 CHECK_LINK_TIMESCHECK_LINK_TIMES 7 mtnic.h 　
22089
 dma_addr_tdma_addr_t unsigned long mtnic.h 　
22090
 PAGE_SIZEPAGE_SIZE 4096 mtnic.h 　
22091
 PAGE_MASKPAGE_MASK (PAGE_SIZE - 1) mtnic.h 　
22092
 MTNIC_MAILBOX_SIZEMTNIC_MAILBOX_SIZE PAGE_SIZE mtnic.h 　
22093
 MTNIC_RESET_OFFSETMTNIC_RESET_OFFSET 0xF0010 mtnic.h 　
22094
 MXGEFW_VERSION_MAJORMXGEFW_VERSION_MAJOR 1 myri10ge_mcp.h 　
22095
 MXGEFW_VERSION_MINORMXGEFW_VERSION_MINOR 4 myri10ge_mcp.h 　
22096
 MXGEFW_RSS_HASH_NULLMXGEFW_RSS_HASH_NULL (0 << 14) myri10ge_mcp.h bit 15:14 = 00
22097
 MXGEFW_RSS_HASH_IPV4MXGEFW_RSS_HASH_IPV4 (1 << 14) myri10ge_mcp.h bit 15:14 = 01
22098
 MXGEFW_RSS_HASH_TCP_IPV4MXGEFW_RSS_HASH_TCP_IPV4 (2 << 14) myri10ge_mcp.h bit 15:14 = 10
22099
 MXGEFW_RSS_HASH_MASKMXGEFW_RSS_HASH_MASK (3 << 14) myri10ge_mcp.h bit 15:14 = 11
22100
 MXGEFW_FLAGS_SMALLMXGEFW_FLAGS_SMALL 0x1 myri10ge_mcp.h 　
22101
 MXGEFW_FLAGS_TSO_HDRMXGEFW_FLAGS_TSO_HDR 0x1 myri10ge_mcp.h 　
22102
 MXGEFW_FLAGS_FIRSTMXGEFW_FLAGS_FIRST 0x2 myri10ge_mcp.h 　
22103
 MXGEFW_FLAGS_ALIGN_ODDMXGEFW_FLAGS_ALIGN_ODD 0x4 myri10ge_mcp.h 　
22104
 MXGEFW_FLAGS_CKSUMMXGEFW_FLAGS_CKSUM 0x8 myri10ge_mcp.h 　
22105
 MXGEFW_FLAGS_TSO_LASTMXGEFW_FLAGS_TSO_LAST 0x8 myri10ge_mcp.h 　
22106
 MXGEFW_FLAGS_NO_TSOMXGEFW_FLAGS_NO_TSO 0x10 myri10ge_mcp.h 　
22107
 MXGEFW_FLAGS_TSO_CHOPMXGEFW_FLAGS_TSO_CHOP 0x10 myri10ge_mcp.h 　
22108
 MXGEFW_FLAGS_TSO_PLDMXGEFW_FLAGS_TSO_PLD 0x20 myri10ge_mcp.h 　
22109
 MXGEFW_SEND_SMALL_SIZEMXGEFW_SEND_SMALL_SIZE 1520 myri10ge_mcp.h 　
22110
 MXGEFW_MAX_MTUMXGEFW_MAX_MTU 9400 myri10ge_mcp.h 　
22111
 MXGEFW_MAX_SEND_DESCMXGEFW_MAX_SEND_DESC 12 myri10ge_mcp.h 　
22112
 MXGEFW_PADMXGEFW_PAD 2 myri10ge_mcp.h 　
22113
 MXGEFW_BOOT_HANDOFFMXGEFW_BOOT_HANDOFF 0xfc0000 myri10ge_mcp.h 　
22114
 MXGEFW_BOOT_DUMMY_RDMAMXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 myri10ge_mcp.h 　
22115
 MXGEFW_ETH_CMDMXGEFW_ETH_CMD 0xf80000 myri10ge_mcp.h 　
22116
 MXGEFW_ETH_SEND_4MXGEFW_ETH_SEND_4 0x200000 myri10ge_mcp.h 　
22117
 MXGEFW_ETH_SEND_1MXGEFW_ETH_SEND_1 0x240000 myri10ge_mcp.h 　
22118
 MXGEFW_ETH_SEND_2MXGEFW_ETH_SEND_2 0x280000 myri10ge_mcp.h 　
22119
 MXGEFW_ETH_SEND_3MXGEFW_ETH_SEND_3 0x2c0000 myri10ge_mcp.h 　
22120
 MXGEFW_ETH_RECV_SMALLMXGEFW_ETH_RECV_SMALL 0x300000 myri10ge_mcp.h 　
22121
 MXGEFW_ETH_RECV_BIGMXGEFW_ETH_RECV_BIG 0x340000 myri10ge_mcp.h 　
22122
 MXGEFW_ETH_SEND_GOMXGEFW_ETH_SEND_GO 0x380000 myri10ge_mcp.h 　
22123
 MXGEFW_ETH_SEND_STOPMXGEFW_ETH_SEND_STOP 0x3C0000 myri10ge_mcp.h 　
22124
 MXGEFW_OLD_IRQ_DATA_LENMXGEFW_OLD_IRQ_DATA_LEN 40 myri10ge_mcp.h 　
22125
 MXGEFW_NETQ_FILTERTYPE_NONEMXGEFW_NETQ_FILTERTYPE_NONE 0 myri10ge_mcp.h 　
22126
 MXGEFW_NETQ_FILTERTYPE_MACADDRMXGEFW_NETQ_FILTERTYPE_MACADDR 1 myri10ge_mcp.h 　
22127
 MXGEFW_NETQ_FILTERTYPE_VLANMXGEFW_NETQ_FILTERTYPE_VLAN 2 myri10ge_mcp.h 　
22128
 MXGEFW_NETQ_FILTERTYPE_VLANMACAMXGEFW_NETQ_FILTERTYPE_VLANMACA 3 myri10ge_mcp.h 　
22129
 NATSEMI_HW_TIMEOUTNATSEMI_HW_TIMEOUT 400 natsemi.h 　
22130
 TX_RING_SIZETX_RING_SIZE 4 natsemi.h 　
22131
 NUM_RX_DESCNUM_RX_DESC 4 natsemi.h 　
22132
 RX_BUF_SIZERX_BUF_SIZE 1536 natsemi.h 　
22133
 OWNOWN 0x80000000 natsemi.h 　
22134
 DSIZEDSIZE 0x00000FFF natsemi.h 　
22135
 CRC_SIZECRC_SIZE 4 natsemi.h 　
22136
 PHYID_AM79C874PHYID_AM79C874 0x0022561b natsemi.h 　
22137
 SRR_DP83815_CSRR_DP83815_C 0x0302 natsemi.h 　
22138
 SRR_DP83815_DSRR_DP83815_D 0x0403 natsemi.h 　
22139
 SRR_DP83816_A4SRR_DP83816_A4 0x0504 natsemi.h 　
22140
 SRR_DP83816_A5SRR_DP83816_A5 0x0505 natsemi.h 　
22141
 PMDCSR_VALPMDCSR_VAL 0x189c natsemi.h enable preferred adaptation circuitry
22142
 TSTDAT_VALTSTDAT_VAL 0x0 natsemi.h 　
22143
 DSPCFG_VALDSPCFG_VAL 0x5040 natsemi.h 　
22144
 SDCFG_VALSDCFG_VAL 0x008c natsemi.h set voltage thresholds for Signal Detect
22145
 DSPCFG_LOCKDSPCFG_LOCK 0x20 natsemi.h coefficient lock bit in DSPCFG
22146
 DSPCFG_COEFDSPCFG_COEF 0x1000 natsemi.h see coefficient (in TSTDAT) bit in DSPCFG
22147
 TSTDAT_FIXEDTSTDAT_FIXED 0xe8 natsemi.h magic number for bad coefficients
22148
 CFG_RESET_SAVECFG_RESET_SAVE 0xfde000 natsemi.h 　
22149
 WCSR_RESET_SAVEWCSR_RESET_SAVE 0x61f natsemi.h 　
22150
 RFCR_RESET_SAVERFCR_RESET_SAVE 0xf8500000; natsemi.h 　
22151
 EE_Write0EE_Write0 (EE_ChipSelect) natsemi.h 　
22152
 EE_Write1EE_Write1 (EE_ChipSelect | EE_DataIn) natsemi.h 　
22153
 EE_CSEE_CS 0x08 natsemi.h EEPROM chip select
22154
 EE_SKEE_SK 0x04 natsemi.h EEPROM shift clock
22155
 EE_DIEE_DI 0x01 natsemi.h Data in
22156
 EE_DOEE_DO 0x02 natsemi.h Data out
22157
 EE_MACEE_MAC 7 natsemi.h 　
22158
 EE_REGEE_REG EECtrl natsemi.h 　
22159
 VENDOR_NONEVENDOR_NONE 0 ns8390.h 　
22160
 VENDOR_WDVENDOR_WD 1 ns8390.h 　
22161
 VENDOR_NOVELLVENDOR_NOVELL 2 ns8390.h 　
22162
 VENDOR_3COMVENDOR_3COM 3 ns8390.h 　
22163
 FLAG_PIOFLAG_PIO 0x01 ns8390.h 　
22164
 FLAG_16BITFLAG_16BIT 0x02 ns8390.h 　
22165
 FLAG_790FLAG_790 0x04 ns8390.h 　
22166
 MEM_8192MEM_8192 32 ns8390.h 　
22167
 MEM_16384MEM_16384 64 ns8390.h 　
22168
 MEM_32768MEM_32768 128 ns8390.h 　
22169
 ISA_MAX_ADDRISA_MAX_ADDR 0x400 ns8390.h 　
22170
 WD_LOW_BASEWD_LOW_BASE 0x200 ns8390.h 　
22171
 WD_HIGH_BASEWD_HIGH_BASE 0x3e0 ns8390.h 　
22172
 WD_DEFAULT_MEMWD_DEFAULT_MEM 0xD0000 ns8390.h 　
22173
 WD_NIC_ADDRWD_NIC_ADDR 0x10 ns8390.h 　
22174
 WD_MSRWD_MSR 0x00 ns8390.h 　
22175
 WD_ICRWD_ICR 0x01 ns8390.h 　
22176
 WD_IARWD_IAR 0x02 ns8390.h 　
22177
 WD_BIOWD_BIO 0x03 ns8390.h 　
22178
 WD_IRRWD_IRR 0x04 ns8390.h 　
22179
 WD_LAARWD_LAAR 0x05 ns8390.h 　
22180
 WD_IJRWD_IJR 0x06 ns8390.h 　
22181
 WD_GP2WD_GP2 0x07 ns8390.h 　
22182
 WD_LARWD_LAR 0x08 ns8390.h 　
22183
 WD_BIDWD_BID 0x0E ns8390.h 　
22184
 WD_ICR_16BITWD_ICR_16BIT 0x01 ns8390.h 　
22185
 WD_MSR_MENBWD_MSR_MENB 0x40 ns8390.h 　
22186
 WD_LAAR_L16ENWD_LAAR_L16EN 0x40 ns8390.h 　
22187
 WD_LAAR_M16ENWD_LAAR_M16EN 0x80 ns8390.h 　
22188
 WD_SOFTCONFIGWD_SOFTCONFIG 0x20 ns8390.h 　
22189
 TYPE_WD8003STYPE_WD8003S 0x02 ns8390.h 　
22190
 TYPE_WD8003ETYPE_WD8003E 0x03 ns8390.h 　
22191
 TYPE_WD8013EBTTYPE_WD8013EBT 0x05 ns8390.h 　
22192
 TYPE_WD8003WTYPE_WD8003W 0x24 ns8390.h 　
22193
 TYPE_WD8003EBTYPE_WD8003EB 0x25 ns8390.h 　
22194
 TYPE_WD8013WTYPE_WD8013W 0x26 ns8390.h 　
22195
 TYPE_WD8013EPTYPE_WD8013EP 0x27 ns8390.h 　
22196
 TYPE_WD8013WCTYPE_WD8013WC 0x28 ns8390.h 　
22197
 TYPE_WD8013EPCTYPE_WD8013EPC 0x29 ns8390.h 　
22198
 TYPE_SMC8216TTYPE_SMC8216T 0x2a ns8390.h 　
22199
 TYPE_SMC8216CTYPE_SMC8216C 0x2b ns8390.h 　
22200
 TYPE_SMC8416TTYPE_SMC8416T 0x00 ns8390.h Bogus entries: the 8416 generates the
22201
 TYPE_SMC8416CTYPE_SMC8416C 0x00 ns8390.h the same codes as the 8216.
22202
 TYPE_SMC8013EBPTYPE_SMC8013EBP 0x2c ns8390.h 　
22203
 _3COM_BASE_3COM_BASE 0x300 ns8390.h 　
22204
 _3COM_TX_PAGE_OFFSET_8BIT_3COM_TX_PAGE_OFFSET_8BIT 0x20 ns8390.h 　
22205
 _3COM_TX_PAGE_OFFSET_16BIT_3COM_TX_PAGE_OFFSET_16BIT 0x0 ns8390.h 　
22206
 _3COM_RX_PAGE_OFFSET_16BIT_3COM_RX_PAGE_OFFSET_16BIT 0x20 ns8390.h 　
22207
 _3COM_ASIC_OFFSET_3COM_ASIC_OFFSET 0x400 ns8390.h 　
22208
 _3COM_NIC_OFFSET_3COM_NIC_OFFSET 0x0 ns8390.h 　
22209
 _3COM_PSTR_3COM_PSTR 0 ns8390.h 　
22210
 _3COM_PSPR_3COM_PSPR 1 ns8390.h 　
22211
 _3COM_BCFR_3COM_BCFR 3 ns8390.h 　
22212
 _3COM_BCFR_2E0_3COM_BCFR_2E0 0x01 ns8390.h 　
22213
 _3COM_BCFR_2A0_3COM_BCFR_2A0 0x02 ns8390.h 　
22214
 _3COM_BCFR_280_3COM_BCFR_280 0x04 ns8390.h 　
22215
 _3COM_BCFR_250_3COM_BCFR_250 0x08 ns8390.h 　
22216
 _3COM_BCFR_350_3COM_BCFR_350 0x10 ns8390.h 　
22217
 _3COM_BCFR_330_3COM_BCFR_330 0x20 ns8390.h 　
22218
 _3COM_BCFR_310_3COM_BCFR_310 0x40 ns8390.h 　
22219
 _3COM_BCFR_300_3COM_BCFR_300 0x80 ns8390.h 　
22220
 _3COM_PCFR_3COM_PCFR 4 ns8390.h 　
22221
 _3COM_PCFR_PIO_3COM_PCFR_PIO 0 ns8390.h 　
22222
 _3COM_PCFR_C8000_3COM_PCFR_C8000 0x10 ns8390.h 　
22223
 _3COM_PCFR_CC000_3COM_PCFR_CC000 0x20 ns8390.h 　
22224
 _3COM_PCFR_D8000_3COM_PCFR_D8000 0x40 ns8390.h 　
22225
 _3COM_PCFR_DC000_3COM_PCFR_DC000 0x80 ns8390.h 　
22226
 _3COM_CR_3COM_CR 6 ns8390.h 　
22227
 _3COM_CR_RST_3COM_CR_RST 0x01 ns8390.h Reset GA and NIC
22228
 _3COM_CR_XSEL_3COM_CR_XSEL 0x02 ns8390.h Transceiver select. BNC=1(def) AUI=0
22229
 _3COM_CR_EALO_3COM_CR_EALO 0x04 ns8390.h window EA PROM 0-15 to I/O base
22230
 _3COM_CR_EAHI_3COM_CR_EAHI 0x08 ns8390.h window EA PROM 16-31 to I/O base
22231
 _3COM_CR_SHARE_3COM_CR_SHARE 0x10 ns8390.h select interrupt sharing option
22232
 _3COM_CR_DBSEL_3COM_CR_DBSEL 0x20 ns8390.h Double buffer select
22233
 _3COM_CR_DDIR_3COM_CR_DDIR 0x40 ns8390.h DMA direction select
22234
 _3COM_CR_START_3COM_CR_START 0x80 ns8390.h Start DMA controller
22235
 _3COM_GACFR_3COM_GACFR 5 ns8390.h 　
22236
 _3COM_GACFR_MBS0_3COM_GACFR_MBS0 0x01 ns8390.h 　
22237
 _3COM_GACFR_MBS1_3COM_GACFR_MBS1 0x02 ns8390.h 　
22238
 _3COM_GACFR_MBS2_3COM_GACFR_MBS2 0x04 ns8390.h 　
22239
 _3COM_GACFR_RSEL_3COM_GACFR_RSEL 0x08 ns8390.h enable shared memory
22240
 _3COM_GACFR_TEST_3COM_GACFR_TEST 0x10 ns8390.h for GA testing
22241
 _3COM_GACFR_OWS_3COM_GACFR_OWS 0x20 ns8390.h select 0WS access to GA
22242
 _3COM_GACFR_TCM_3COM_GACFR_TCM 0x40 ns8390.h Mask DMA interrupts
22243
 _3COM_GACFR_NIM_3COM_GACFR_NIM 0x80 ns8390.h Mask NIC interrupts
22244
 _3COM_STREG_3COM_STREG 7 ns8390.h 　
22245
 _3COM_STREG_REV_3COM_STREG_REV 0x07 ns8390.h GA revision
22246
 _3COM_STREG_DIP_3COM_STREG_DIP 0x08 ns8390.h DMA in progress
22247
 _3COM_STREG_DTC_3COM_STREG_DTC 0x10 ns8390.h DMA terminal count
22248
 _3COM_STREG_OFLW_3COM_STREG_OFLW 0x20 ns8390.h Overflow
22249
 _3COM_STREG_UFLW_3COM_STREG_UFLW 0x40 ns8390.h Underflow
22250
 _3COM_STREG_DPRDY_3COM_STREG_DPRDY 0x80 ns8390.h Data port ready
22251
 _3COM_IDCFR_3COM_IDCFR 8 ns8390.h 　
22252
 _3COM_IDCFR_DRQ0_3COM_IDCFR_DRQ0 0x01 ns8390.h DMA request 1 select
22253
 _3COM_IDCFR_DRQ1_3COM_IDCFR_DRQ1 0x02 ns8390.h DMA request 2 select
22254
 _3COM_IDCFR_DRQ2_3COM_IDCFR_DRQ2 0x04 ns8390.h DMA request 3 select
22255
 _3COM_IDCFR_UNUSED_3COM_IDCFR_UNUSED 0x08 ns8390.h not used
22256
 _3COM_IDCFR_IRQ2_3COM_IDCFR_IRQ2 0x10 ns8390.h Interrupt request 2 select
22257
 _3COM_IDCFR_IRQ3_3COM_IDCFR_IRQ3 0x20 ns8390.h Interrupt request 3 select
22258
 _3COM_IDCFR_IRQ4_3COM_IDCFR_IRQ4 0x40 ns8390.h Interrupt request 4 select
22259
 _3COM_IDCFR_IRQ5_3COM_IDCFR_IRQ5 0x80 ns8390.h Interrupt request 5 select
22260
 _3COM_IRQ2_3COM_IRQ2 2 ns8390.h 　
22261
 _3COM_IRQ3_3COM_IRQ3 3 ns8390.h 　
22262
 _3COM_IRQ4_3COM_IRQ4 4 ns8390.h 　
22263
 _3COM_IRQ5_3COM_IRQ5 5 ns8390.h 　
22264
 _3COM_DAMSB_3COM_DAMSB 9 ns8390.h 　
22265
 _3COM_DALSB_3COM_DALSB 0x0a ns8390.h 　
22266
 _3COM_VPTR2_3COM_VPTR2 0x0b ns8390.h 　
22267
 _3COM_VPTR1_3COM_VPTR1 0x0c ns8390.h 　
22268
 _3COM_VPTR0_3COM_VPTR0 0x0d ns8390.h 　
22269
 _3COM_RFMSB_3COM_RFMSB 0x0e ns8390.h 　
22270
 _3COM_RFLSB_3COM_RFLSB 0x0f ns8390.h 　
22271
 NE_ASIC_OFFSETNE_ASIC_OFFSET 0x10 ns8390.h 　
22272
 NE_RESETNE_RESET 0x0F ns8390.h Used to reset card
22273
 NE_DATANE_DATA 0x00 ns8390.h Used to read/write NIC mem
22274
 COMPEX_RL2000_TRIESCOMPEX_RL2000_TRIES 200 ns8390.h 　
22275
 D8390_P0_COMMANDD8390_P0_COMMAND 0x00 ns8390.h 　
22276
 D8390_P0_PSTARTD8390_P0_PSTART 0x01 ns8390.h 　
22277
 D8390_P0_PSTOPD8390_P0_PSTOP 0x02 ns8390.h 　
22278
 D8390_P0_BOUNDD8390_P0_BOUND 0x03 ns8390.h 　
22279
 D8390_P0_TSRD8390_P0_TSR 0x04 ns8390.h 　
22280
 D8390_P0_TPSRD8390_P0_TPSR 0x04 ns8390.h 　
22281
 D8390_P0_TBCR0D8390_P0_TBCR0 0x05 ns8390.h 　
22282
 D8390_P0_TBCR1D8390_P0_TBCR1 0x06 ns8390.h 　
22283
 D8390_P0_ISRD8390_P0_ISR 0x07 ns8390.h 　
22284
 D8390_P0_RSAR0D8390_P0_RSAR0 0x08 ns8390.h 　
22285
 D8390_P0_RSAR1D8390_P0_RSAR1 0x09 ns8390.h 　
22286
 D8390_P0_RBCR0D8390_P0_RBCR0 0x0A ns8390.h 　
22287
 D8390_P0_RBCR1D8390_P0_RBCR1 0x0B ns8390.h 　
22288
 D8390_P0_RSRD8390_P0_RSR 0x0C ns8390.h 　
22289
 D8390_P0_RCRD8390_P0_RCR 0x0C ns8390.h 　
22290
 D8390_P0_TCRD8390_P0_TCR 0x0D ns8390.h 　
22291
 D8390_P0_DCRD8390_P0_DCR 0x0E ns8390.h 　
22292
 D8390_P0_IMRD8390_P0_IMR 0x0F ns8390.h 　
22293
 D8390_P1_COMMANDD8390_P1_COMMAND 0x00 ns8390.h 　
22294
 D8390_P1_PAR0D8390_P1_PAR0 0x01 ns8390.h 　
22295
 D8390_P1_PAR1D8390_P1_PAR1 0x02 ns8390.h 　
22296
 D8390_P1_PAR2D8390_P1_PAR2 0x03 ns8390.h 　
22297
 D8390_P1_PAR3D8390_P1_PAR3 0x04 ns8390.h 　
22298
 D8390_P1_PAR4D8390_P1_PAR4 0x05 ns8390.h 　
22299
 D8390_P1_PAR5D8390_P1_PAR5 0x06 ns8390.h 　
22300
 D8390_P1_CURRD8390_P1_CURR 0x07 ns8390.h 　
22301
 D8390_P1_MAR0D8390_P1_MAR0 0x08 ns8390.h 　
22302
 D8390_COMMAND_PS0D8390_COMMAND_PS0 0x0 ns8390.h Page 0 select
22303
 D8390_COMMAND_PS1D8390_COMMAND_PS1 0x40 ns8390.h Page 1 select
22304
 D8390_COMMAND_PS2D8390_COMMAND_PS2 0x80 ns8390.h Page 2 select
22305
 D8390_COMMAND_RD2D8390_COMMAND_RD2 0x20 ns8390.h Remote DMA control
22306
 D8390_COMMAND_RD1D8390_COMMAND_RD1 0x10 ns8390.h 　
22307
 D8390_COMMAND_RD0D8390_COMMAND_RD0 0x08 ns8390.h 　
22308
 D8390_COMMAND_TXPD8390_COMMAND_TXP 0x04 ns8390.h transmit packet
22309
 D8390_COMMAND_STAD8390_COMMAND_STA 0x02 ns8390.h start
22310
 D8390_COMMAND_STPD8390_COMMAND_STP 0x01 ns8390.h stop
22311
 D8390_RCR_MOND8390_RCR_MON 0x20 ns8390.h monitor mode
22312
 D8390_DCR_FT1D8390_DCR_FT1 0x40 ns8390.h 　
22313
 D8390_DCR_LSD8390_DCR_LS 0x08 ns8390.h Loopback select
22314
 D8390_DCR_WTSD8390_DCR_WTS 0x01 ns8390.h Word transfer select
22315
 D8390_ISR_PRXD8390_ISR_PRX 0x01 ns8390.h successful recv
22316
 D8390_ISR_PTXD8390_ISR_PTX 0x02 ns8390.h successful xmit
22317
 D8390_ISR_RXED8390_ISR_RXE 0x04 ns8390.h receive error
22318
 D8390_ISR_TXED8390_ISR_TXE 0x08 ns8390.h transmit error
22319
 D8390_ISR_OVWD8390_ISR_OVW 0x10 ns8390.h Overflow
22320
 D8390_ISR_CNTD8390_ISR_CNT 0x20 ns8390.h Counter overflow
22321
 D8390_ISR_RDCD8390_ISR_RDC 0x40 ns8390.h Remote DMA complete
22322
 D8390_ISR_RSTD8390_ISR_RST 0x80 ns8390.h reset
22323
 D8390_RSTAT_PRXD8390_RSTAT_PRX 0x01 ns8390.h successful recv
22324
 D8390_RSTAT_CRCD8390_RSTAT_CRC 0x02 ns8390.h CRC error
22325
 D8390_RSTAT_FAED8390_RSTAT_FAE 0x04 ns8390.h Frame alignment error
22326
 D8390_RSTAT_OVERD8390_RSTAT_OVER 0x08 ns8390.h FIFO overrun
22327
 D8390_TXBUF_SIZED8390_TXBUF_SIZE 6 ns8390.h 　
22328
 D8390_RXBUF_ENDD8390_RXBUF_END 32 ns8390.h 　
22329
 D8390_PAGE_SIZED8390_PAGE_SIZE 256 ns8390.h 　
22330
 WLAN_ADDR_LENWLAN_ADDR_LEN 6 p80211hdr.h 　
22331
 WLAN_CRC_LENWLAN_CRC_LEN 4 p80211hdr.h 　
22332
 WLAN_BSSID_LENWLAN_BSSID_LEN 6 p80211hdr.h 　
22333
 WLAN_BSS_TS_LENWLAN_BSS_TS_LEN 8 p80211hdr.h 　
22334
 WLAN_HDR_A3_LENWLAN_HDR_A3_LEN 24 p80211hdr.h 　
22335
 WLAN_HDR_A4_LENWLAN_HDR_A4_LEN 30 p80211hdr.h 　
22336
 WLAN_SSID_MAXLENWLAN_SSID_MAXLEN 32 p80211hdr.h 　
22337
 WLAN_DATA_MAXLENWLAN_DATA_MAXLEN 2312 p80211hdr.h 　
22338
 WLAN_A3FR_MAXLENWLAN_A3FR_MAXLEN (WLAN_HDR_A3_LEN + WLAN_DATA_MAXLEN + WLAN_CRC_LEN) p80211hdr.h 　
22339
 WLAN_A4FR_MAXLENWLAN_A4FR_MAXLEN (WLAN_HDR_A4_LEN + WLAN_DATA_MAXLEN + WLAN_CRC_LEN) p80211hdr.h 　
22340
 WLAN_BEACON_FR_MAXLENWLAN_BEACON_FR_MAXLEN (WLAN_HDR_A3_LEN + 334) p80211hdr.h 　
22341
 WLAN_ATIM_FR_MAXLENWLAN_ATIM_FR_MAXLEN (WLAN_HDR_A3_LEN + 0) p80211hdr.h 　
22342
 WLAN_DISASSOC_FR_MAXLENWLAN_DISASSOC_FR_MAXLEN (WLAN_HDR_A3_LEN + 2) p80211hdr.h 　
22343
 WLAN_ASSOCREQ_FR_MAXLENWLAN_ASSOCREQ_FR_MAXLEN (WLAN_HDR_A3_LEN + 48) p80211hdr.h 　
22344
 WLAN_ASSOCRESP_FR_MAXLENWLAN_ASSOCRESP_FR_MAXLEN (WLAN_HDR_A3_LEN + 16) p80211hdr.h 　
22345
 WLAN_REASSOCREQ_FR_MAXLENWLAN_REASSOCREQ_FR_MAXLEN (WLAN_HDR_A3_LEN + 54) p80211hdr.h 　
22346
 WLAN_REASSOCRESP_FR_MAXLENWLAN_REASSOCRESP_FR_MAXLEN (WLAN_HDR_A3_LEN + 16) p80211hdr.h 　
22347
 WLAN_PROBEREQ_FR_MAXLENWLAN_PROBEREQ_FR_MAXLEN (WLAN_HDR_A3_LEN + 44) p80211hdr.h 　
22348
 WLAN_PROBERESP_FR_MAXLENWLAN_PROBERESP_FR_MAXLEN (WLAN_HDR_A3_LEN + 78) p80211hdr.h 　
22349
 WLAN_AUTHEN_FR_MAXLENWLAN_AUTHEN_FR_MAXLEN (WLAN_HDR_A3_LEN + 261) p80211hdr.h 　
22350
 WLAN_DEAUTHEN_FR_MAXLENWLAN_DEAUTHEN_FR_MAXLEN (WLAN_HDR_A3_LEN + 2) p80211hdr.h 　
22351
 WLAN_WEP_NKEYSWLAN_WEP_NKEYS 4 p80211hdr.h 　
22352
 WLAN_WEP_MAXKEYLENWLAN_WEP_MAXKEYLEN 13 p80211hdr.h 　
22353
 WLAN_CHALLENGE_IE_LENWLAN_CHALLENGE_IE_LEN 130 p80211hdr.h 　
22354
 WLAN_CHALLENGE_LENWLAN_CHALLENGE_LEN 128 p80211hdr.h 　
22355
 WLAN_WEP_IV_LENWLAN_WEP_IV_LEN 4 p80211hdr.h 　
22356
 WLAN_WEP_ICV_LENWLAN_WEP_ICV_LEN 4 p80211hdr.h 　
22357
 WLAN_FTYPE_MGMTWLAN_FTYPE_MGMT 0x00 p80211hdr.h 　
22358
 WLAN_FTYPE_CTLWLAN_FTYPE_CTL 0x01 p80211hdr.h 　
22359
 WLAN_FTYPE_DATAWLAN_FTYPE_DATA 0x02 p80211hdr.h 　
22360
 WLAN_FSTYPE_ASSOCREQWLAN_FSTYPE_ASSOCREQ 0x00 p80211hdr.h 　
22361
 WLAN_FSTYPE_ASSOCRESPWLAN_FSTYPE_ASSOCRESP 0x01 p80211hdr.h 　
22362
 WLAN_FSTYPE_REASSOCREQWLAN_FSTYPE_REASSOCREQ 0x02 p80211hdr.h 　
22363
 WLAN_FSTYPE_REASSOCRESPWLAN_FSTYPE_REASSOCRESP 0x03 p80211hdr.h 　
22364
 WLAN_FSTYPE_PROBEREQWLAN_FSTYPE_PROBEREQ 0x04 p80211hdr.h 　
22365
 WLAN_FSTYPE_PROBERESPWLAN_FSTYPE_PROBERESP 0x05 p80211hdr.h 　
22366
 WLAN_FSTYPE_BEACONWLAN_FSTYPE_BEACON 0x08 p80211hdr.h 　
22367
 WLAN_FSTYPE_ATIMWLAN_FSTYPE_ATIM 0x09 p80211hdr.h 　
22368
 WLAN_FSTYPE_DISASSOCWLAN_FSTYPE_DISASSOC 0x0a p80211hdr.h 　
22369
 WLAN_FSTYPE_AUTHENWLAN_FSTYPE_AUTHEN 0x0b p80211hdr.h 　
22370
 WLAN_FSTYPE_DEAUTHENWLAN_FSTYPE_DEAUTHEN 0x0c p80211hdr.h 　
22371
 WLAN_FSTYPE_BLOCKACKREQWLAN_FSTYPE_BLOCKACKREQ 0x8 p80211hdr.h 　
22372
 WLAN_FSTYPE_BLOCKACKWLAN_FSTYPE_BLOCKACK 0x9 p80211hdr.h 　
22373
 WLAN_FSTYPE_PSPOLLWLAN_FSTYPE_PSPOLL 0x0a p80211hdr.h 　
22374
 WLAN_FSTYPE_RTSWLAN_FSTYPE_RTS 0x0b p80211hdr.h 　
22375
 WLAN_FSTYPE_CTSWLAN_FSTYPE_CTS 0x0c p80211hdr.h 　
22376
 WLAN_FSTYPE_ACKWLAN_FSTYPE_ACK 0x0d p80211hdr.h 　
22377
 WLAN_FSTYPE_CFENDWLAN_FSTYPE_CFEND 0x0e p80211hdr.h 　
22378
 WLAN_FSTYPE_CFENDCFACKWLAN_FSTYPE_CFENDCFACK 0x0f p80211hdr.h 　
22379
 WLAN_FSTYPE_DATAONLYWLAN_FSTYPE_DATAONLY 0x00 p80211hdr.h 　
22380
 WLAN_FSTYPE_DATA_CFACKWLAN_FSTYPE_DATA_CFACK 0x01 p80211hdr.h 　
22381
 WLAN_FSTYPE_DATA_CFPOLLWLAN_FSTYPE_DATA_CFPOLL 0x02 p80211hdr.h 　
22382
 WLAN_FSTYPE_DATA_CFACK_CFPOLLWLAN_FSTYPE_DATA_CFACK_CFPOLL 0x03 p80211hdr.h 　
22383
 WLAN_FSTYPE_NULLWLAN_FSTYPE_NULL 0x04 p80211hdr.h 　
22384
 WLAN_FSTYPE_CFACKWLAN_FSTYPE_CFACK 0x05 p80211hdr.h 　
22385
 WLAN_FSTYPE_CFPOLLWLAN_FSTYPE_CFPOLL 0x06 p80211hdr.h 　
22386
 WLAN_FSTYPE_CFACK_CFPOLLWLAN_FSTYPE_CFACK_CFPOLL 0x07 p80211hdr.h 　
22387
 WLAN_FCS_LENWLAN_FCS_LEN 4 p80211hdr.h 　
22388
 PCNET32_LOG_TX_BUFFERSPCNET32_LOG_TX_BUFFERS 4 pcnet32.h 　
22389
 PCNET32_LOG_RX_BUFFERSPCNET32_LOG_RX_BUFFERS 5 pcnet32.h 　
22390
 PCNET32_LOG_MAX_TX_BUFFERSPCNET32_LOG_MAX_TX_BUFFERS 9 pcnet32.h 　
22391
 PCNET32_LOG_MAX_RX_BUFFERSPCNET32_LOG_MAX_RX_BUFFERS 9 pcnet32.h 　
22392
 TX_RING_SIZETX_RING_SIZE ( 1 << ( PCNET32_LOG_TX_BUFFERS ) ) pcnet32.h 　
22393
 TX_MAX_RING_SIZETX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_TX_BUFFERS ) ) pcnet32.h 　
22394
 RX_RING_SIZERX_RING_SIZE ( 1 << ( PCNET32_LOG_RX_BUFFERS ) ) pcnet32.h 　
22395
 RX_MAX_RING_SIZERX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_RX_BUFFERS ) ) pcnet32.h 　
22396
 RX_RING_BYTESRX_RING_BYTES ( RX_RING_SIZE * sizeof(struct pcnet32_rx_desc ) ) pcnet32.h 　
22397
 TX_RING_BYTESTX_RING_BYTES ( TX_RING_SIZE * sizeof(struct pcnet32_tx_desc ) ) pcnet32.h 　
22398
 PKT_BUF_SIZEPKT_BUF_SIZE 1536 pcnet32.h 　
22399
 RX_RING_ALIGNRX_RING_ALIGN 16 pcnet32.h 　
22400
 TX_RING_ALIGNTX_RING_ALIGN 16 pcnet32.h 　
22401
 INIT_BLOCK_ALIGNINIT_BLOCK_ALIGN 32 pcnet32.h 　
22402
 PCNET32_WIO_RDPPCNET32_WIO_RDP 0x10 pcnet32.h 　
22403
 PCNET32_WIO_RAPPCNET32_WIO_RAP 0x12 pcnet32.h 　
22404
 PCNET32_WIO_RESETPCNET32_WIO_RESET 0x14 pcnet32.h 　
22405
 PCNET32_WIO_BDPPCNET32_WIO_BDP 0x16 pcnet32.h 　
22406
 PCNET32_DWIO_RDPPCNET32_DWIO_RDP 0x10 pcnet32.h 　
22407
 PCNET32_DWIO_RAPPCNET32_DWIO_RAP 0x14 pcnet32.h 　
22408
 PCNET32_DWIO_RESETPCNET32_DWIO_RESET 0x18 pcnet32.h 　
22409
 PCNET32_DWIO_BDPPCNET32_DWIO_BDP 0x1C pcnet32.h 　
22410
 PCNET32_PORT_AUIPCNET32_PORT_AUI 0x00 pcnet32.h 　
22411
 PCNET32_PORT_10BTPCNET32_PORT_10BT 0x01 pcnet32.h 　
22412
 PCNET32_PORT_GPSIPCNET32_PORT_GPSI 0x02 pcnet32.h 　
22413
 PCNET32_PORT_MIIPCNET32_PORT_MII 0x03 pcnet32.h 　
22414
 PCNET32_PORT_PORTSELPCNET32_PORT_PORTSEL 0x03 pcnet32.h 　
22415
 PCNET32_PORT_ASELPCNET32_PORT_ASEL 0x04 pcnet32.h 　
22416
 PCNET32_PORT_100PCNET32_PORT_100 0x40 pcnet32.h 　
22417
 PCNET32_PORT_FDPCNET32_PORT_FD 0x80 pcnet32.h 　
22418
 PCNET32_SWSTYLE_LANCEPCNET32_SWSTYLE_LANCE 0x00 pcnet32.h 　
22419
 PCNET32_SWSTYLE_ILACCPCNET32_SWSTYLE_ILACC 0x01 pcnet32.h 　
22420
 PCNET32_SWSTYLE_PCNET32PCNET32_SWSTYLE_PCNET32 0x02 pcnet32.h 　
22421
 PCNET32_MAX_PHYSPCNET32_MAX_PHYS 32 pcnet32.h 　
22422
 PCI_VENDOR_ID_ATPCI_VENDOR_ID_AT 0x1259 pcnet32.h 　
22423
 PCI_SUBDEVICE_ID_AT_2700FXPCI_SUBDEVICE_ID_AT_2700FX 0x2701 pcnet32.h 　
22424
 PCI_SUBDEVICE_ID_AT_2701FXPCI_SUBDEVICE_ID_AT_2701FX 0x2703 pcnet32.h 　
22425
 PNIC_PCI_VENDORPNIC_PCI_VENDOR 0xfefe pnic_api.h Hopefully these won't clash with
22426
 PNIC_PCI_DEVICEPNIC_PCI_DEVICE 0xefef pnic_api.h any real PCI device IDs.
22427
 PNIC_REG_CMDPNIC_REG_CMD 0x00 pnic_api.h Command register, 2 bytes, write only
22428
 PNIC_REG_STATPNIC_REG_STAT 0x00 pnic_api.h Status register, 2 bytes, read only
22429
 PNIC_REG_LENPNIC_REG_LEN 0x02 pnic_api.h Length register, 2 bytes, read-write
22430
 PNIC_REG_DATAPNIC_REG_DATA 0x04 pnic_api.h Data port, 1 byte, read-write
22431
 PNIC_MAX_REGPNIC_MAX_REG 0x04 pnic_api.h 　
22432
 PNIC_CMD_NOOPPNIC_CMD_NOOP 0x0000 pnic_api.h 　
22433
 PNIC_CMD_API_VERPNIC_CMD_API_VER 0x0001 pnic_api.h 　
22434
 PNIC_CMD_READ_MACPNIC_CMD_READ_MAC 0x0002 pnic_api.h 　
22435
 PNIC_CMD_RESETPNIC_CMD_RESET 0x0003 pnic_api.h 　
22436
 PNIC_CMD_XMITPNIC_CMD_XMIT 0x0004 pnic_api.h 　
22437
 PNIC_CMD_RECVPNIC_CMD_RECV 0x0005 pnic_api.h 　
22438
 PNIC_CMD_RECV_QLENPNIC_CMD_RECV_QLEN 0x0006 pnic_api.h 　
22439
 PNIC_CMD_MASK_IRQPNIC_CMD_MASK_IRQ 0x0007 pnic_api.h 　
22440
 PNIC_CMD_FORCE_IRQPNIC_CMD_FORCE_IRQ 0x0008 pnic_api.h 　
22441
 PNIC_STATUS_OKPNIC_STATUS_OK 0x4f4b pnic_api.h 'OK'
22442
 PNIC_STATUS_UNKNOWN_CMDPNIC_STATUS_UNKNOWN_CMD 0x3f3f pnic_api.h '??'
22443
 PNIC_API_VERSIONPNIC_API_VERSION 0x0101 pnic_api.h 1.1
22444
 PCI_EXP_DEVCTLPCI_EXP_DEVCTL 8 r8169.h Device Control
22445
 PCI_EXP_DEVCTL_READRQPCI_EXP_DEVCTL_READRQ 0x7000 r8169.h Max_Read_Request_Size
22446
 PCI_EXP_LNKCTLPCI_EXP_LNKCTL 16 r8169.h Link Control
22447
 PCI_EXP_LNKCTL_CLKREQ_ENPCI_EXP_LNKCTL_CLKREQ_EN 0x100 r8169.h Enable clkreq
22448
 PCI_EXP_DEVCTL_NOSNOOP_ENPCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 r8169.h Enable No Snoop
22449
 SPEED_10SPEED_10 10 r8169.h 　
22450
 SPEED_100SPEED_100 100 r8169.h 　
22451
 SPEED_1000SPEED_1000 1000 r8169.h 　
22452
 SPEED_2500SPEED_2500 2500 r8169.h 　
22453
 SPEED_10000SPEED_10000 10000 r8169.h 　
22454
 DUPLEX_HALFDUPLEX_HALF 0x00 r8169.h 　
22455
 DUPLEX_FULLDUPLEX_FULL 0x01 r8169.h 　
22456
 AUTONEG_DISABLEAUTONEG_DISABLE 0x00 r8169.h 　
22457
 AUTONEG_ENABLEAUTONEG_ENABLE 0x01 r8169.h 　
22458
 MAC_ADDR_LENMAC_ADDR_LEN 6 r8169.h 　
22459
 MAX_READ_REQUEST_SHIFTMAX_READ_REQUEST_SHIFT 12 r8169.h 　
22460
 RX_FIFO_THRESHRX_FIFO_THRESH 7 r8169.h 7 means NO threshold, Rx buffer level before first PCI xfer.
22461
 RX_DMA_BURSTRX_DMA_BURST 6 r8169.h Maximum PCI burst, '6' is 1024
22462
 TX_DMA_BURSTTX_DMA_BURST 6 r8169.h Maximum PCI burst, '6' is 1024
22463
 EarlyTxThldEarlyTxThld 0x3F r8169.h 0x3F means NO early transmit
22464
 RxPacketMaxSizeRxPacketMaxSize 0x3FE8 r8169.h 16K - 1 - ETH_HLEN - VLAN - CRC...
22465
 SafeMtuSafeMtu 0x1c20 r8169.h ... actually life sucks beyond ~7k
22466
 InterFrameGapInterFrameGap 0x03 r8169.h 3 means InterFrameGap = the shortest one
22467
 R8169_REGS_SIZER8169_REGS_SIZE 256 r8169.h 　
22468
 R8169_NAPI_WEIGHTR8169_NAPI_WEIGHT 64 r8169.h 　
22469
 NUM_TX_DESCNUM_TX_DESC 8 r8169.h Number of Tx descriptor registers
22470
 NUM_RX_DESCNUM_RX_DESC 8 r8169.h Number of Rx descriptor registers
22471
 RX_BUF_SIZERX_BUF_SIZE 1536 r8169.h Rx Buffer size
22472
 R8169_TX_RING_BYTESR8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) r8169.h 　
22473
 R8169_RX_RING_BYTESR8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) r8169.h 　
22474
 TX_RING_ALIGNTX_RING_ALIGN 256 r8169.h 　
22475
 RX_RING_ALIGNRX_RING_ALIGN 256 r8169.h 　
22476
 RTL8169_TX_TIMEOUTRTL8169_TX_TIMEOUT (6*HZ) r8169.h 　
22477
 RTL8169_PHY_TIMEOUTRTL8169_PHY_TIMEOUT (10*HZ) r8169.h 　
22478
 RTL_EEPROM_SIGRTL_EEPROM_SIG cpu_to_le32(0x8129) r8169.h 　
22479
 RTL_EEPROM_SIG_MASKRTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) r8169.h 　
22480
 RTL_EEPROM_SIG_ADDRRTL_EEPROM_SIG_ADDR 0x0000 r8169.h 　
22481
 RsvdMaskRsvdMask 0x3fffc000 r8169.h 　
22482
 PCI_VENDOR_ID_SIPCI_VENDOR_ID_SI 0x1039 sis190.h 　
22483
 PHY_MAX_ADDRPHY_MAX_ADDR 32 sis190.h 　
22484
 PHY_ID_ANYPHY_ID_ANY 0x1f sis190.h 　
22485
 MII_REG_ANYMII_REG_ANY 0x1f sis190.h 　
22486
 DRV_VERSIONDRV_VERSION "1.3" sis190.h 　
22487
 DRV_NAMEDRV_NAME "sis190" sis190.h 　
22488
 SIS190_DRIVER_NAMESIS190_DRIVER_NAME DRV_NAME " Gigabit Ethernet driver " DRV_VERSION sis190.h 　
22489
 PFXPFX DRV_NAME ": " sis190.h 　
22490
 NUM_TX_DESCNUM_TX_DESC 8 sis190.h [8..1024]
22491
 NUM_RX_DESCNUM_RX_DESC 8 sis190.h [8..8192]
22492
 TX_RING_BYTESTX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) sis190.h 　
22493
 RX_RING_BYTESRX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) sis190.h 　
22494
 RX_BUF_SIZERX_BUF_SIZE 1536 sis190.h 　
22495
 RX_BUF_MASKRX_BUF_MASK 0xfff8 sis190.h 　
22496
 RING_ALIGNMENTRING_ALIGNMENT 256 sis190.h 　
22497
 SIS190_REGS_SIZESIS190_REGS_SIZE 0x80 sis190.h 　
22498
 EhnMIIreadEhnMIIread 0x0000 sis190.h 　
22499
 EhnMIIwriteEhnMIIwrite 0x0020 sis190.h 　
22500
 EhnMIIdataShiftEhnMIIdataShift 16 sis190.h 　
22501
 EhnMIIpmdShiftEhnMIIpmdShift 6 sis190.h 7016 only
22502
 EhnMIIregShiftEhnMIIregShift 11 sis190.h 　
22503
 EhnMIIreqEhnMIIreq 0x0010 sis190.h 　
22504
 EhnMIInotDoneEhnMIInotDone 0x0010 sis190.h 　
22505
 SIS900_TOTAL_SIZESIS900_TOTAL_SIZE 0x100 sis900.h 　
22506
 MAX_DMA_RANGEMAX_DMA_RANGE 7 sis900.h actually 0 means MAXIMUM !!
22507
 TxMXDMA_shiftTxMXDMA_shift 20 sis900.h 　
22508
 RxMXDMA_shiftRxMXDMA_shift 20 sis900.h 　
22509
 TX_DMA_BURSTTX_DMA_BURST 0 sis900.h 　
22510
 RX_DMA_BURSTRX_DMA_BURST 0 sis900.h 　
22511
 TX_FILL_THRESHTX_FILL_THRESH 16 sis900.h 1/4 FIFO size
22512
 TxFILLT_shiftTxFILLT_shift 8 sis900.h 　
22513
 TxDRNT_shiftTxDRNT_shift 0 sis900.h 　
22514
 TxDRNT_100TxDRNT_100 48 sis900.h 3/4 FIFO size
22515
 TxDRNT_10TxDRNT_10 16 sis900.h 1/2 FIFO size
22516
 RxDRNT_shiftRxDRNT_shift 1 sis900.h 　
22517
 RxDRNT_100RxDRNT_100 16 sis900.h 1/2 FIFO size
22518
 RxDRNT_10RxDRNT_10 24 sis900.h 3/4 FIFO size
22519
 RFAA_shiftRFAA_shift 28 sis900.h 　
22520
 RFADDR_shiftRFADDR_shift 16 sis900.h 　
22521
 MIIreadMIIread 0x6000 sis900.h 　
22522
 MIIwriteMIIwrite 0x5002 sis900.h 　
22523
 MIIpmdShiftMIIpmdShift 7 sis900.h 　
22524
 MIIregShiftMIIregShift 2 sis900.h 　
22525
 MIIcmdLenMIIcmdLen 16 sis900.h 　
22526
 MIIcmdShiftMIIcmdShift 16 sis900.h 　
22527
 MII_ID1_OUI_LOMII_ID1_OUI_LO 0xFC00 sis900.h low bits of OUI mask
22528
 MII_ID1_MODELMII_ID1_MODEL 0x03F0 sis900.h model number
22529
 MII_ID1_REVMII_ID1_REV 0x000F sis900.h model number
22530
 FDX_CAPABLE_DUPLEX_UNKNOWNFDX_CAPABLE_DUPLEX_UNKNOWN 0 sis900.h 　
22531
 FDX_CAPABLE_HALF_SELECTEDFDX_CAPABLE_HALF_SELECTED 1 sis900.h 　
22532
 FDX_CAPABLE_FULL_SELECTEDFDX_CAPABLE_FULL_SELECTED 2 sis900.h 　
22533
 HW_SPEED_UNCONFIGHW_SPEED_UNCONFIG 0 sis900.h 　
22534
 HW_SPEED_HOMEHW_SPEED_HOME 1 sis900.h 　
22535
 HW_SPEED_10_MBPSHW_SPEED_10_MBPS 10 sis900.h 　
22536
 HW_SPEED_100_MBPSHW_SPEED_100_MBPS 100 sis900.h 　
22537
 HW_SPEED_DEFAULTHW_SPEED_DEFAULT (HW_SPEED_100_MBPS) sis900.h 　
22538
 CRC_SIZECRC_SIZE 4 sis900.h 　
22539
 MAC_HEADER_SIZEMAC_HEADER_SIZE 14 sis900.h 　
22540
 TX_BUF_SIZETX_BUF_SIZE 1536 sis900.h 　
22541
 RX_BUF_SIZERX_BUF_SIZE 1536 sis900.h 　
22542
 NUM_RX_DESCNUM_RX_DESC 4 sis900.h Number of Rx descriptor registers.
22543
 TX_TIMEOUTTX_TIMEOUT (4*TICKS_PER_SEC) sis900.h 　
22544
 PCI_DEV_REG1PCI_DEV_REG1 0x40 skge.h 　
22545
 PCI_PHY_COMAPCI_PHY_COMA 0x8000000 skge.h 　
22546
 PCI_VIOPCI_VIO 0x2000000 skge.h 　
22547
 PCI_DEV_REG2PCI_DEV_REG2 0x44 skge.h 　
22548
 PCI_VPD_ROM_SZPCI_VPD_ROM_SZ 7L<<14 skge.h VPD ROM size 0=256, 1=512, ...
22549
 PCI_REV_DESCPCI_REV_DESC 1<<2 skge.h Reverse Descriptor bytes
22550
 DRV_NAMEDRV_NAME "skge" skge.h 　
22551
 DRV_VERSIONDRV_VERSION "1.13" skge.h 　
22552
 PFXPFX DRV_NAME " " skge.h 　
22553
 NUM_TX_DESCNUM_TX_DESC 8 skge.h 　
22554
 NUM_RX_DESCNUM_RX_DESC 8 skge.h 　
22555
 SKGE_RING_ALIGNSKGE_RING_ALIGN 8 skge.h 　
22556
 RX_BUF_SIZERX_BUF_SIZE 1536 skge.h 　
22557
 PHY_RETRIESPHY_RETRIES 1000 skge.h 　
22558
 TX_RING_SIZETX_RING_SIZE ( NUM_TX_DESC * sizeof ( struct skge_rx_desc ) ) skge.h 　
22559
 RX_RING_SIZERX_RING_SIZE ( NUM_RX_DESC * sizeof ( struct skge_tx_desc ) ) skge.h 　
22560
 RING_SIZERING_SIZE ( TX_RING_SIZE + RX_RING_SIZE ) skge.h 　
22561
 SKGE_REG_SIZESKGE_REG_SIZE 0x4000 skge.h 　
22562
 SKGE_EEPROM_MAGICSKGE_EEPROM_MAGIC 0x9933aabb skge.h 　
22563
 AUTONEG_DISABLEAUTONEG_DISABLE 0x00 skge.h 　
22564
 AUTONEG_ENABLEAUTONEG_ENABLE 0x01 skge.h 　
22565
 DUPLEX_HALFDUPLEX_HALF 0x00 skge.h 　
22566
 DUPLEX_FULLDUPLEX_FULL 0x01 skge.h 　
22567
 SPEED_10SPEED_10 10 skge.h 　
22568
 SPEED_100SPEED_100 100 skge.h 　
22569
 SPEED_1000SPEED_1000 1000 skge.h 　
22570
 ADVERTISED_10baseT_HalfADVERTISED_10baseT_Half (1 << 0) skge.h 　
22571
 ADVERTISED_10baseT_FullADVERTISED_10baseT_Full (1 << 1) skge.h 　
22572
 ADVERTISED_100baseT_HalfADVERTISED_100baseT_Half (1 << 2) skge.h 　
22573
 ADVERTISED_100baseT_FullADVERTISED_100baseT_Full (1 << 3) skge.h 　
22574
 ADVERTISED_1000baseT_HalfADVERTISED_1000baseT_Half (1 << 4) skge.h 　
22575
 ADVERTISED_1000baseT_FullADVERTISED_1000baseT_Full (1 << 5) skge.h 　
22576
 SUPPORTED_10baseT_HalfSUPPORTED_10baseT_Half (1 << 0) skge.h 　
22577
 SUPPORTED_10baseT_FullSUPPORTED_10baseT_Full (1 << 1) skge.h 　
22578
 SUPPORTED_100baseT_HalfSUPPORTED_100baseT_Half (1 << 2) skge.h 　
22579
 SUPPORTED_100baseT_FullSUPPORTED_100baseT_Full (1 << 3) skge.h 　
22580
 SUPPORTED_1000baseT_HalfSUPPORTED_1000baseT_Half (1 << 4) skge.h 　
22581
 SUPPORTED_1000baseT_FullSUPPORTED_1000baseT_Full (1 << 5) skge.h 　
22582
 SUPPORTED_AutonegSUPPORTED_Autoneg (1 << 6) skge.h 　
22583
 SUPPORTED_TPSUPPORTED_TP (1 << 7) skge.h 　
22584
 SUPPORTED_FIBRESUPPORTED_FIBRE (1 << 10) skge.h 　
22585
 PCI_STATUS_ERROR_BITSPCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ PCI_STATUS_SIG_SYSTEM_ERROR | \ PCI_STATUS_REC_MASTER_ABORT | \ PCI_STATUS_REC_TARGET_ABORT | \ skge.h 　
22586
 RAM_ADR_RANRAM_ADR_RAN 0x0007ffffL skge.h Bit 18.. 0: RAM Address Range
22587
 SK_MAC_TO_53SK_MAC_TO_53 72 skge.h MAC arbiter timeout
22588
 SK_PKT_TO_53SK_PKT_TO_53 0x2000 skge.h Packet arbiter timeout
22589
 SK_PKT_TO_MAXSK_PKT_TO_MAX 0xffff skge.h Maximum value
22590
 SK_RI_TO_53SK_RI_TO_53 36 skge.h RAM interface timeout
22591
 PA_ENA_TO_ALLPA_ENA_TO_ALL (PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\ PA_ENA_TO_TX1 | PA_ENA_TO_TX2) skge.h 　
22592
 TXA_MAX_VALTXA_MAX_VAL 0x00ffffffUL skge.h Bit 23.. 0: Max TXA Timer/Cnt Val
22593
 CSR_SET_RESETCSR_SET_RESET (CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\ CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\ CSR_TRANS_RST) skge.h 　
22594
 CSR_CLR_RESETCSR_CLR_RESET (CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\ CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\ CSR_TRANS_RUN) skge.h 　
22595
 RB_MSKRB_MSK 0x0007ffff skge.h Bit 18.. 0: RAM Buffer Pointer Bits
22596
 SK_XMIT_DURSK_XMIT_DUR 0x002faf08UL skge.h 50 ms
22597
 SK_BLK_DURSK_BLK_DUR 0x01dcd650UL skge.h 500 ms
22598
 SK_DPOLL_DEFSK_DPOLL_DEF 0x00ee6b28UL skge.h 250 ms at 62.5 MHz
22599
 SK_DPOLL_MAXSK_DPOLL_MAX 0x00ffffffUL skge.h 268 ms at 62.5 MHz
22600
 SK_FACT_62SK_FACT_62 100 skge.h is given in percent
22601
 SK_FACT_53SK_FACT_53 85 skge.h on GENESIS: 53.12 MHz
22602
 SK_FACT_78SK_FACT_78 125 skge.h on YUKON: 78.12 MHz
22603
 PHY_B_AS_PAUSE_MSKPHY_B_AS_PAUSE_MSK (PHY_B_AS_PRR | PHY_B_AS_PRT) skge.h 　
22604
 PHY_B_DEF_MSKPHY_B_DEF_MSK (~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \ PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE)) skge.h 　
22605
 PHY_M_PS_PAUSE_MSKPHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) skge.h 　
22606
 GM_MIB_CNT_BASEGM_MIB_CNT_BASE 0x0100 skge.h Base Address of MIB Counters
22607
 GM_MIB_CNT_SIZEGM_MIB_CNT_SIZE 44 skge.h Number of MIB Counters
22608
 GM_GPCR_SPEED_1000GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) skge.h 　
22609
 GM_GPCR_AU_ALL_DISGM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) skge.h 　
22610
 TX_COL_DEFTX_COL_DEF 0x04 skge.h late collision after 64 byte
22611
 DATA_BLIND_DEFDATA_BLIND_DEF 0x04 skge.h 　
22612
 IPG_DATA_DEFIPG_DATA_DEF 0x1e skge.h 　
22613
 GPC_HWCFG_GMII_COPGPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0) skge.h 　
22614
 GPC_HWCFG_GMII_FIBGPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0) skge.h 　
22615
 GPC_ANEG_ADV_ALL_MGPC_ANEG_ADV_ALL_M (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0) skge.h 　
22616
 GPC_FRC10MBIT_HALFGPC_FRC10MBIT_HALF 0 skge.h 　
22617
 GPC_FRC10MBIT_FULLGPC_FRC10MBIT_FULL GPC_ANEG_0 skge.h 　
22618
 GPC_FRC100MBIT_HALFGPC_FRC100MBIT_HALF GPC_ANEG_1 skge.h 　
22619
 GPC_FRC100MBIT_FULLGPC_FRC100MBIT_FULL (GPC_ANEG_0 | GPC_ANEG_1) skge.h 　
22620
 GPC_ADV_1000_HALFGPC_ADV_1000_HALF GPC_ANEG_2 skge.h 　
22621
 GPC_ADV_1000_FULLGPC_ADV_1000_FULL GPC_ANEG_3 skge.h 　
22622
 GPC_ADV_ALLGPC_ADV_ALL (GPC_ANEG_2 | GPC_ANEG_3) skge.h 　
22623
 GPC_FORCE_MASTERGPC_FORCE_MASTER 0 skge.h 　
22624
 GPC_FORCE_SLAVEGPC_FORCE_SLAVE GPC_ANEG_0 skge.h 　
22625
 GPC_PREF_MASTERGPC_PREF_MASTER GPC_ANEG_1 skge.h 　
22626
 GPC_PREF_SLAVEGPC_PREF_SLAVE (GPC_ANEG_1 | GPC_ANEG_0) skge.h 　
22627
 WOL_CTL_DEFAULTWOL_CTL_DEFAULT (WOL_CTL_DIS_PME_ON_LINK_CHG | \ WOL_CTL_DIS_PME_ON_PATTERN | \ WOL_CTL_DIS_PME_ON_MAGIC_PKT | \ WOL_CTL_DIS_LINK_CHG_UNIT | skge.h 　
22628
 XM_RT_LIM_MSKXM_RT_LIM_MSK 0x1f skge.h Bit 4..0: Tx Retry Limit
22629
 XM_STIME_MSKXM_STIME_MSK 0x7f skge.h Bit 6..0: Tx Slottime bits
22630
 XM_IPG_MSKXM_IPG_MSK 0xff skge.h Bit 7..0: IPG value bits
22631
 XM_TX_WM_MSKXM_TX_WM_MSK 0x01ff skge.h Bit 9.. 0 Tx FIFO Watermark bits
22632
 XM_THR_MSKXM_THR_MSK 0x03ff skge.h Bit 10.. 0 Rx/Tx Request Threshold bits
22633
 XM_RX_WM_MSKXM_RX_WM_MSK 0x03ff skge.h Bit 11.. 0: Rx FIFO Watermark bits
22634
 XM_DEV_OUIXM_DEV_OUI (0x00ffffffUL<<8) skge.h Bit 31..8: Device OUI
22635
 XM_DEV_REVXM_DEV_REV (0x07L << 5) skge.h Bit 7..5: Chip Rev Num
22636
 XM_PAUSE_MODEXM_PAUSE_MODE (XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I) skge.h 　
22637
 XM_DEF_MODEXM_DEF_MODE (XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\ XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA) skge.h 　
22638
 XMR_DEF_MSKXMR_DEF_MSK (XMR_OK_LO_OV | XMR_OK_HI_OV) skge.h 　
22639
 XMT_DEF_MSKXMT_DEF_MSK (XMT_OK_LO_OV | XMT_OK_HI_OV) skge.h 　
22640
 AUTONEG_DISABLEAUTONEG_DISABLE 0x00 sky2.h 　
22641
 AUTONEG_ENABLEAUTONEG_ENABLE 0x01 sky2.h 　
22642
 DUPLEX_HALFDUPLEX_HALF 0x00 sky2.h 　
22643
 DUPLEX_FULLDUPLEX_FULL 0x01 sky2.h 　
22644
 SPEED_10SPEED_10 10 sky2.h 　
22645
 SPEED_100SPEED_100 100 sky2.h 　
22646
 SPEED_1000SPEED_1000 1000 sky2.h 　
22647
 ADVERTISED_10baseT_HalfADVERTISED_10baseT_Half (1 << 0) sky2.h 　
22648
 ADVERTISED_10baseT_FullADVERTISED_10baseT_Full (1 << 1) sky2.h 　
22649
 ADVERTISED_100baseT_HalfADVERTISED_100baseT_Half (1 << 2) sky2.h 　
22650
 ADVERTISED_100baseT_FullADVERTISED_100baseT_Full (1 << 3) sky2.h 　
22651
 ADVERTISED_1000baseT_HalfADVERTISED_1000baseT_Half (1 << 4) sky2.h 　
22652
 ADVERTISED_1000baseT_FullADVERTISED_1000baseT_Full (1 << 5) sky2.h 　
22653
 SUPPORTED_10baseT_HalfSUPPORTED_10baseT_Half (1 << 0) sky2.h 　
22654
 SUPPORTED_10baseT_FullSUPPORTED_10baseT_Full (1 << 1) sky2.h 　
22655
 SUPPORTED_100baseT_HalfSUPPORTED_100baseT_Half (1 << 2) sky2.h 　
22656
 SUPPORTED_100baseT_FullSUPPORTED_100baseT_Full (1 << 3) sky2.h 　
22657
 SUPPORTED_1000baseT_HalfSUPPORTED_1000baseT_Half (1 << 4) sky2.h 　
22658
 SUPPORTED_1000baseT_FullSUPPORTED_1000baseT_Full (1 << 5) sky2.h 　
22659
 SUPPORTED_AutonegSUPPORTED_Autoneg (1 << 6) sky2.h 　
22660
 SUPPORTED_TPSUPPORTED_TP (1 << 7) sky2.h 　
22661
 SUPPORTED_FIBRESUPPORTED_FIBRE (1 << 10) sky2.h 　
22662
 PCI_STATUS_ERROR_BITSPCI_STATUS_ERROR_BITS (PCI_STATUS_DETECTED_PARITY | \ PCI_STATUS_SIG_SYSTEM_ERROR | \ PCI_STATUS_REC_MASTER_ABORT | \ PCI_STATUS_REC_TARGET_ABORT | \ sky2.h 　
22663
 CFG_DUAL_MAC_MSKCFG_DUAL_MAC_MSK (CFG_LINK_2_AVAIL | CFG_LINK_1_AVAIL) sky2.h 　
22664
 RAM_ADR_RANRAM_ADR_RAN 0x0007ffffL sky2.h Bit 18.. 0: RAM Address Range
22665
 SK_RI_TO_53SK_RI_TO_53 36 sky2.h RAM interface timeout
22666
 TXA_MAX_VALTXA_MAX_VAL 0x00ffffffUL sky2.h Bit 23.. 0: Max TXA Timer/Cnt Val
22667
 RB_MSKRB_MSK 0x0007ffff sky2.h Bit 18.. 0: RAM Buffer Pointer Bits
22668
 PHY_M_PS_PAUSE_MSKPHY_M_PS_PAUSE_MSK (PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN) sky2.h 　
22669
 GM_GPCR_SPEED_1000GM_GPCR_SPEED_1000 (GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100) sky2.h 　
22670
 GM_GPCR_AU_ALL_DISGM_GPCR_AU_ALL_DIS (GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS) sky2.h 　
22671
 TX_COL_DEFTX_COL_DEF 0x04 sky2.h 　
22672
 DATA_BLIND_DEFDATA_BLIND_DEF 0x04 sky2.h 　
22673
 IPG_DATA_DEFIPG_DATA_DEF 0x1e sky2.h 　
22674
 GM_PHY_RETRIESGM_PHY_RETRIES 100 sky2.h 　
22675
 BANK_SELECTBANK_SELECT 14 smc9000.h 　
22676
 TCRTCR 0 smc9000.h transmit control register
22677
 TCR_ENABLETCR_ENABLE 0x0001 smc9000.h if this is 1, we can transmit
22678
 TCR_FDUPLXTCR_FDUPLX 0x0800 smc9000.h receive packets sent out
22679
 TCR_STP_SQETTCR_STP_SQET 0x1000 smc9000.h stop transmitting if Signal quality error
22680
 TCR_MON_CNSTCR_MON_CNS 0x0400 smc9000.h monitors the carrier status
22681
 TCR_PAD_ENABLETCR_PAD_ENABLE 0x0080 smc9000.h pads short packets to 64 bytes
22682
 TCR_CLEARTCR_CLEAR 0 smc9000.h do NOTHING
22683
 TCR_NORMALTCR_NORMAL (TCR_ENABLE | TCR_PAD_ENABLE) smc9000.h 　
22684
 EPH_STATUSEPH_STATUS 2 smc9000.h 　
22685
 ES_LINK_OKES_LINK_OK 0x4000 smc9000.h is the link integrity ok ?
22686
 RCRRCR 4 smc9000.h 　
22687
 RCR_SOFTRESETRCR_SOFTRESET 0x8000 smc9000.h resets the chip
22688
 RCR_STRIP_CRCRCR_STRIP_CRC 0x200 smc9000.h strips CRC
22689
 RCR_ENABLERCR_ENABLE 0x100 smc9000.h IFF this is set, we can receive packets
22690
 RCR_ALMULRCR_ALMUL 0x4 smc9000.h receive all multicast packets
22691
 RCR_PROMISCRCR_PROMISC 0x2 smc9000.h enable promiscuous mode
22692
 RCR_NORMALRCR_NORMAL (RCR_STRIP_CRC | RCR_ENABLE) smc9000.h 　
22693
 RCR_CLEARRCR_CLEAR 0x0 smc9000.h set it to a base state
22694
 COUNTERCOUNTER 6 smc9000.h 　
22695
 MIRMIR 8 smc9000.h 　
22696
 MCRMCR 10 smc9000.h 　
22697
 RPC_REGRPC_REG 0x000A smc9000.h 　
22698
 RPC_SPEEDRPC_SPEED 0x2000 smc9000.h When 1 PHY is in 100Mbps mode.
22699
 RPC_DPLXRPC_DPLX 0x1000 smc9000.h When 1 PHY is in Full-Duplex Mode
22700
 RPC_ANEGRPC_ANEG 0x0800 smc9000.h When 1 PHY is in Auto-Negotiate Mode
22701
 RPC_LSXA_SHFTRPC_LSXA_SHFT 5 smc9000.h Bits to shift LS2A,LS1A,LS0A to lsb
22702
 RPC_LSXB_SHFTRPC_LSXB_SHFT 2 smc9000.h Bits to get LS2B,LS1B,LS0B to lsb
22703
 RPC_LED_100_10RPC_LED_100_10 (0x00) smc9000.h LED = 100Mbps OR's with 10Mbps link detect
22704
 RPC_LED_RESRPC_LED_RES (0x01) smc9000.h LED = Reserved
22705
 RPC_LED_10RPC_LED_10 (0x02) smc9000.h LED = 10Mbps link detect
22706
 RPC_LED_FDRPC_LED_FD (0x03) smc9000.h LED = Full Duplex Mode
22707
 RPC_LED_TX_RXRPC_LED_TX_RX (0x04) smc9000.h LED = TX or RX packet occurred
22708
 RPC_LED_100RPC_LED_100 (0x05) smc9000.h LED = 100Mbps link dectect
22709
 RPC_LED_TXRPC_LED_TX (0x06) smc9000.h LED = TX packet occurred
22710
 RPC_LED_RXRPC_LED_RX (0x07) smc9000.h LED = RX packet occurred
22711
 RPC_DEFAULTRPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) smc9000.h 　
22712
 RPC_REGRPC_REG 0x000A smc9000.h 　
22713
 RPC_SPEEDRPC_SPEED 0x2000 smc9000.h When 1 PHY is in 100Mbps mode.
22714
 RPC_DPLXRPC_DPLX 0x1000 smc9000.h When 1 PHY is in Full-Duplex Mode
22715
 RPC_ANEGRPC_ANEG 0x0800 smc9000.h When 1 PHY is in Auto-Negotiate Mode
22716
 RPC_LSXA_SHFTRPC_LSXA_SHFT 5 smc9000.h Bits to shift LS2A,LS1A,LS0A to lsb
22717
 RPC_LSXB_SHFTRPC_LSXB_SHFT 2 smc9000.h Bits to get LS2B,LS1B,LS0B to lsb
22718
 RPC_LED_100_10RPC_LED_100_10 (0x00) smc9000.h LED = 100Mbps OR's with 10Mbps link detect
22719
 RPC_LED_RESRPC_LED_RES (0x01) smc9000.h LED = Reserved
22720
 RPC_LED_10RPC_LED_10 (0x02) smc9000.h LED = 10Mbps link detect
22721
 RPC_LED_FDRPC_LED_FD (0x03) smc9000.h LED = Full Duplex Mode
22722
 RPC_LED_TX_RXRPC_LED_TX_RX (0x04) smc9000.h LED = TX or RX packet occurred
22723
 RPC_LED_100RPC_LED_100 (0x05) smc9000.h LED = 100Mbps link dectect
22724
 RPC_LED_TXRPC_LED_TX (0x06) smc9000.h LED = TX packet occurred
22725
 RPC_LED_RXRPC_LED_RX (0x07) smc9000.h LED = RX packet occurred
22726
 RPC_DEFAULTRPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX) smc9000.h 　
22727
 CONFIGCONFIG 0 smc9000.h 　
22728
 CFG_AUI_SELECTCFG_AUI_SELECT 0x100 smc9000.h 　
22729
 BASEBASE 2 smc9000.h 　
22730
 ADDR0ADDR0 4 smc9000.h 　
22731
 ADDR1ADDR1 6 smc9000.h 　
22732
 ADDR2ADDR2 8 smc9000.h 　
22733
 GENERALGENERAL 10 smc9000.h 　
22734
 CONTROLCONTROL 12 smc9000.h 　
22735
 CTL_POWERDOWNCTL_POWERDOWN 0x2000 smc9000.h 　
22736
 CTL_LE_ENABLECTL_LE_ENABLE 0x80 smc9000.h 　
22737
 CTL_CR_ENABLECTL_CR_ENABLE 0x40 smc9000.h 　
22738
 CTL_TE_ENABLECTL_TE_ENABLE 0x0020 smc9000.h 　
22739
 CTL_AUTO_RELEASECTL_AUTO_RELEASE 0x0800 smc9000.h 　
22740
 CTL_EPROM_ACCESSCTL_EPROM_ACCESS 0x0003 smc9000.h high if Eprom is being read
22741
 MMU_CMDMMU_CMD 0 smc9000.h 　
22742
 MC_BUSYMC_BUSY 1 smc9000.h only readable bit in the register
22743
 MC_NOPMC_NOP 0 smc9000.h 　
22744
 MC_ALLOCMC_ALLOC 0x20 smc9000.h or with number of 256 byte packets
22745
 MC_RESETMC_RESET 0x40 smc9000.h 　
22746
 MC_REMOVEMC_REMOVE 0x60 smc9000.h remove the current rx packet
22747
 MC_RELEASEMC_RELEASE 0x80 smc9000.h remove and release the current rx packet
22748
 MC_FREEPKTMC_FREEPKT 0xA0 smc9000.h Release packet in PNR register
22749
 MC_ENQUEUEMC_ENQUEUE 0xC0 smc9000.h Enqueue the packet for transmit
22750
 PNR_ARRPNR_ARR 2 smc9000.h 　
22751
 FIFO_PORTSFIFO_PORTS 4 smc9000.h 　
22752
 FP_RXEMPTYFP_RXEMPTY 0x8000 smc9000.h 　
22753
 FP_TXEMPTYFP_TXEMPTY 0x80 smc9000.h 　
22754
 POINTERPOINTER 6 smc9000.h 　
22755
 PTR_READPTR_READ 0x2000 smc9000.h 　
22756
 PTR_RCVPTR_RCV 0x8000 smc9000.h 　
22757
 PTR_AUTOINCPTR_AUTOINC 0x4000 smc9000.h 　
22758
 PTR_AUTO_INCPTR_AUTO_INC 0x0040 smc9000.h 　
22759
 DATA_1DATA_1 8 smc9000.h 　
22760
 DATA_2DATA_2 10 smc9000.h 　
22761
 INTERRUPTINTERRUPT 12 smc9000.h 　
22762
 INT_MASKINT_MASK 13 smc9000.h 　
22763
 IM_RCV_INTIM_RCV_INT 0x1 smc9000.h 　
22764
 IM_TX_INTIM_TX_INT 0x2 smc9000.h 　
22765
 IM_TX_EMPTY_INTIM_TX_EMPTY_INT 0x4 smc9000.h 　
22766
 IM_ALLOC_INTIM_ALLOC_INT 0x8 smc9000.h 　
22767
 IM_RX_OVRN_INTIM_RX_OVRN_INT 0x10 smc9000.h 　
22768
 IM_EPH_INTIM_EPH_INT 0x20 smc9000.h 　
22769
 IM_ERCV_INTIM_ERCV_INT 0x40 smc9000.h not on SMC9192
22770
 MULTICAST1MULTICAST1 0 smc9000.h 　
22771
 MULTICAST2MULTICAST2 2 smc9000.h 　
22772
 MULTICAST3MULTICAST3 4 smc9000.h 　
22773
 MULTICAST4MULTICAST4 6 smc9000.h 　
22774
 MGMTMGMT 8 smc9000.h 　
22775
 REVISIONREVISION 10 smc9000.h ( hi: chip id low: rev # )
22776
 MII_REGMII_REG 0x0008 smc9000.h 　
22777
 MII_MSK_CRS100MII_MSK_CRS100 0x4000 smc9000.h Disables CRS100 detection during tx half dup
22778
 MII_MDOEMII_MDOE 0x0008 smc9000.h MII Output Enable
22779
 MII_MCLKMII_MCLK 0x0004 smc9000.h MII Clock, pin MDCLK
22780
 MII_MDIMII_MDI 0x0002 smc9000.h MII Input, pin MDI
22781
 MII_MDOMII_MDO 0x0001 smc9000.h MII Output, pin MDO
22782
 ERCVERCV 12 smc9000.h 　
22783
 CHIP_9190CHIP_9190 3 smc9000.h 　
22784
 CHIP_9194CHIP_9194 4 smc9000.h 　
22785
 CHIP_9195CHIP_9195 5 smc9000.h 　
22786
 CHIP_9196CHIP_9196 4 smc9000.h 　
22787
 CHIP_91100CHIP_91100 7 smc9000.h 　
22788
 CHIP_91100FDCHIP_91100FD 8 smc9000.h 　
22789
 REV_9196REV_9196 6 smc9000.h 　
22790
 TS_SUCCESSTS_SUCCESS 0x0001 smc9000.h 　
22791
 TS_LOSTCARTS_LOSTCAR 0x0400 smc9000.h 　
22792
 TS_LATCOLTS_LATCOL 0x0200 smc9000.h 　
22793
 TS_16COLTS_16COL 0x0010 smc9000.h 　
22794
 RS_ALGNERRRS_ALGNERR 0x8000 smc9000.h 　
22795
 RS_BADCRCRS_BADCRC 0x2000 smc9000.h 　
22796
 RS_ODDFRAMERS_ODDFRAME 0x1000 smc9000.h 　
22797
 RS_TOOLONGRS_TOOLONG 0x0800 smc9000.h 　
22798
 RS_TOOSHORTRS_TOOSHORT 0x0400 smc9000.h 　
22799
 RS_MULTICASTRS_MULTICAST 0x0001 smc9000.h 　
22800
 RS_ERRORSRS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) smc9000.h 　
22801
 PHY_CNTL_REGPHY_CNTL_REG 0x00 smc9000.h 　
22802
 PHY_CNTL_RSTPHY_CNTL_RST 0x8000 smc9000.h 1=PHY Reset
22803
 PHY_CNTL_LPBKPHY_CNTL_LPBK 0x4000 smc9000.h 1=PHY Loopback
22804
 PHY_CNTL_SPEEDPHY_CNTL_SPEED 0x2000 smc9000.h 1=100Mbps, 0=10Mpbs
22805
 PHY_CNTL_ANEG_ENPHY_CNTL_ANEG_EN 0x1000 smc9000.h 1=Enable Auto negotiation
22806
 PHY_CNTL_PDNPHY_CNTL_PDN 0x0800 smc9000.h 1=PHY Power Down mode
22807
 PHY_CNTL_MII_DISPHY_CNTL_MII_DIS 0x0400 smc9000.h 1=MII 4 bit interface disabled
22808
 PHY_CNTL_ANEG_RSTPHY_CNTL_ANEG_RST 0x0200 smc9000.h 1=Reset Auto negotiate
22809
 PHY_CNTL_DPLXPHY_CNTL_DPLX 0x0100 smc9000.h 1=Full Duplex, 0=Half Duplex
22810
 PHY_CNTL_COLTSTPHY_CNTL_COLTST 0x0080 smc9000.h 1= MII Colision Test
22811
 PHY_STAT_REGPHY_STAT_REG 0x01 smc9000.h 　
22812
 PHY_STAT_CAP_T4PHY_STAT_CAP_T4 0x8000 smc9000.h 1=100Base-T4 capable
22813
 PHY_STAT_CAP_TXFPHY_STAT_CAP_TXF 0x4000 smc9000.h 1=100Base-X full duplex capable
22814
 PHY_STAT_CAP_TXHPHY_STAT_CAP_TXH 0x2000 smc9000.h 1=100Base-X half duplex capable
22815
 PHY_STAT_CAP_TFPHY_STAT_CAP_TF 0x1000 smc9000.h 1=10Mbps full duplex capable
22816
 PHY_STAT_CAP_THPHY_STAT_CAP_TH 0x0800 smc9000.h 1=10Mbps half duplex capable
22817
 PHY_STAT_CAP_SUPRPHY_STAT_CAP_SUPR 0x0040 smc9000.h 1=recv mgmt frames with not preamble
22818
 PHY_STAT_ANEG_ACKPHY_STAT_ANEG_ACK 0x0020 smc9000.h 1=ANEG has completed
22819
 PHY_STAT_REM_FLTPHY_STAT_REM_FLT 0x0010 smc9000.h 1=Remote Fault detected
22820
 PHY_STAT_CAP_ANEGPHY_STAT_CAP_ANEG 0x0008 smc9000.h 1=Auto negotiate capable
22821
 PHY_STAT_LINKPHY_STAT_LINK 0x0004 smc9000.h 1=valid link
22822
 PHY_STAT_JABPHY_STAT_JAB 0x0002 smc9000.h 1=10Mbps jabber condition
22823
 PHY_STAT_EXREGPHY_STAT_EXREG 0x0001 smc9000.h 1=extended registers implemented
22824
 PHY_ID1_REGPHY_ID1_REG 0x02 smc9000.h PHY Identifier 1
22825
 PHY_ID2_REGPHY_ID2_REG 0x03 smc9000.h PHY Identifier 2
22826
 PHY_AD_REGPHY_AD_REG 0x04 smc9000.h 　
22827
 PHY_AD_NPPHY_AD_NP 0x8000 smc9000.h 1=PHY requests exchange of Next Page
22828
 PHY_AD_ACKPHY_AD_ACK 0x4000 smc9000.h 1=got link code word from remote
22829
 PHY_AD_RFPHY_AD_RF 0x2000 smc9000.h 1=advertise remote fault
22830
 PHY_AD_T4PHY_AD_T4 0x0200 smc9000.h 1=PHY is capable of 100Base-T4
22831
 PHY_AD_TX_FDXPHY_AD_TX_FDX 0x0100 smc9000.h 1=PHY is capable of 100Base-TX FDPLX
22832
 PHY_AD_TX_HDXPHY_AD_TX_HDX 0x0080 smc9000.h 1=PHY is capable of 100Base-TX HDPLX
22833
 PHY_AD_10_FDXPHY_AD_10_FDX 0x0040 smc9000.h 1=PHY is capable of 10Base-T FDPLX
22834
 PHY_AD_10_HDXPHY_AD_10_HDX 0x0020 smc9000.h 1=PHY is capable of 10Base-T HDPLX
22835
 PHY_AD_CSMAPHY_AD_CSMA 0x0001 smc9000.h 1=PHY is capable of 802.3 CMSA
22836
 PHY_RMT_REGPHY_RMT_REG 0x05 smc9000.h 　
22837
 PHY_CFG1_REGPHY_CFG1_REG 0x10 smc9000.h 　
22838
 PHY_CFG1_LNKDISPHY_CFG1_LNKDIS 0x8000 smc9000.h 1=Rx Link Detect Function disabled
22839
 PHY_CFG1_XMTDISPHY_CFG1_XMTDIS 0x4000 smc9000.h 1=TP Transmitter Disabled
22840
 PHY_CFG1_XMTPDNPHY_CFG1_XMTPDN 0x2000 smc9000.h 1=TP Transmitter Powered Down
22841
 PHY_CFG1_BYPSCRPHY_CFG1_BYPSCR 0x0400 smc9000.h 1=Bypass scrambler/descrambler
22842
 PHY_CFG1_UNSCDSPHY_CFG1_UNSCDS 0x0200 smc9000.h 1=Unscramble Idle Reception Disable
22843
 PHY_CFG1_EQLZRPHY_CFG1_EQLZR 0x0100 smc9000.h 1=Rx Equalizer Disabled
22844
 PHY_CFG1_CABLEPHY_CFG1_CABLE 0x0080 smc9000.h 1=STP(150ohm), 0=UTP(100ohm)
22845
 PHY_CFG1_RLVL0PHY_CFG1_RLVL0 0x0040 smc9000.h 1=Rx Squelch level reduced by 4.5db
22846
 PHY_CFG1_TLVL_SHIFTPHY_CFG1_TLVL_SHIFT 2 smc9000.h Transmit Output Level Adjust
22847
 PHY_CFG1_TLVL_MASKPHY_CFG1_TLVL_MASK 0x003C smc9000.h 　
22848
 PHY_CFG1_TRF_MASKPHY_CFG1_TRF_MASK 0x0003 smc9000.h Transmitter Rise/Fall time
22849
 PHY_CFG2_REGPHY_CFG2_REG 0x11 smc9000.h 　
22850
 PHY_CFG2_APOLDISPHY_CFG2_APOLDIS 0x0020 smc9000.h 1=Auto Polarity Correction disabled
22851
 PHY_CFG2_JABDISPHY_CFG2_JABDIS 0x0010 smc9000.h 1=Jabber disabled
22852
 PHY_CFG2_MREGPHY_CFG2_MREG 0x0008 smc9000.h 1=Multiple register access (MII mgt)
22853
 PHY_CFG2_INTMDIOPHY_CFG2_INTMDIO 0x0004 smc9000.h 1=Interrupt signaled with MDIO pulseo
22854
 PHY_INT_REGPHY_INT_REG 0x12 smc9000.h Status Output (Interrupt Status)
22855
 PHY_INT_INTPHY_INT_INT 0x8000 smc9000.h 1=bits have changed since last read
22856
 PHY_INT_LNKFAILPHY_INT_LNKFAIL 0x4000 smc9000.h 1=Link Not detected
22857
 PHY_INT_LOSSSYNCPHY_INT_LOSSSYNC 0x2000 smc9000.h 1=Descrambler has lost sync
22858
 PHY_INT_CWRDPHY_INT_CWRD 0x1000 smc9000.h 1=Invalid 4B5B code detected on rx
22859
 PHY_INT_SSDPHY_INT_SSD 0x0800 smc9000.h 1=No Start Of Stream detected on rx
22860
 PHY_INT_ESDPHY_INT_ESD 0x0400 smc9000.h 1=No End Of Stream detected on rx
22861
 PHY_INT_RPOLPHY_INT_RPOL 0x0200 smc9000.h 1=Reverse Polarity detected
22862
 PHY_INT_JABPHY_INT_JAB 0x0100 smc9000.h 1=Jabber detected
22863
 PHY_INT_SPDDETPHY_INT_SPDDET 0x0080 smc9000.h 1=100Base-TX mode, 0=10Base-T mode
22864
 PHY_INT_DPLXDETPHY_INT_DPLXDET 0x0040 smc9000.h 1=Device in Full Duplex
22865
 PHY_MASK_REGPHY_MASK_REG 0x13 smc9000.h Interrupt Mask
22866
 PHY_CNTL_REGPHY_CNTL_REG 0x00 smc9000.h 　
22867
 PHY_CNTL_RSTPHY_CNTL_RST 0x8000 smc9000.h 1=PHY Reset
22868
 PHY_CNTL_LPBKPHY_CNTL_LPBK 0x4000 smc9000.h 1=PHY Loopback
22869
 PHY_CNTL_SPEEDPHY_CNTL_SPEED 0x2000 smc9000.h 1=100Mbps, 0=10Mpbs
22870
 PHY_CNTL_ANEG_ENPHY_CNTL_ANEG_EN 0x1000 smc9000.h 1=Enable Auto negotiation
22871
 PHY_CNTL_PDNPHY_CNTL_PDN 0x0800 smc9000.h 1=PHY Power Down mode
22872
 PHY_CNTL_MII_DISPHY_CNTL_MII_DIS 0x0400 smc9000.h 1=MII 4 bit interface disabled
22873
 PHY_CNTL_ANEG_RSTPHY_CNTL_ANEG_RST 0x0200 smc9000.h 1=Reset Auto negotiate
22874
 PHY_CNTL_DPLXPHY_CNTL_DPLX 0x0100 smc9000.h 1=Full Duplex, 0=Half Duplex
22875
 PHY_CNTL_COLTSTPHY_CNTL_COLTST 0x0080 smc9000.h 1= MII Colision Test
22876
 PHY_STAT_REGPHY_STAT_REG 0x01 smc9000.h 　
22877
 PHY_STAT_CAP_T4PHY_STAT_CAP_T4 0x8000 smc9000.h 1=100Base-T4 capable
22878
 PHY_STAT_CAP_TXFPHY_STAT_CAP_TXF 0x4000 smc9000.h 1=100Base-X full duplex capable
22879
 PHY_STAT_CAP_TXHPHY_STAT_CAP_TXH 0x2000 smc9000.h 1=100Base-X half duplex capable
22880
 PHY_STAT_CAP_TFPHY_STAT_CAP_TF 0x1000 smc9000.h 1=10Mbps full duplex capable
22881
 PHY_STAT_CAP_THPHY_STAT_CAP_TH 0x0800 smc9000.h 1=10Mbps half duplex capable
22882
 PHY_STAT_CAP_SUPRPHY_STAT_CAP_SUPR 0x0040 smc9000.h 1=recv mgmt frames with not preamble
22883
 PHY_STAT_ANEG_ACKPHY_STAT_ANEG_ACK 0x0020 smc9000.h 1=ANEG has completed
22884
 PHY_STAT_REM_FLTPHY_STAT_REM_FLT 0x0010 smc9000.h 1=Remote Fault detected
22885
 PHY_STAT_CAP_ANEGPHY_STAT_CAP_ANEG 0x0008 smc9000.h 1=Auto negotiate capable
22886
 PHY_STAT_LINKPHY_STAT_LINK 0x0004 smc9000.h 1=valid link
22887
 PHY_STAT_JABPHY_STAT_JAB 0x0002 smc9000.h 1=10Mbps jabber condition
22888
 PHY_STAT_EXREGPHY_STAT_EXREG 0x0001 smc9000.h 1=extended registers implemented
22889
 PHY_ID1_REGPHY_ID1_REG 0x02 smc9000.h PHY Identifier 1
22890
 PHY_ID2_REGPHY_ID2_REG 0x03 smc9000.h PHY Identifier 2
22891
 PHY_AD_REGPHY_AD_REG 0x04 smc9000.h 　
22892
 PHY_AD_NPPHY_AD_NP 0x8000 smc9000.h 1=PHY requests exchange of Next Page
22893
 PHY_AD_ACKPHY_AD_ACK 0x4000 smc9000.h 1=got link code word from remote
22894
 PHY_AD_RFPHY_AD_RF 0x2000 smc9000.h 1=advertise remote fault
22895
 PHY_AD_T4PHY_AD_T4 0x0200 smc9000.h 1=PHY is capable of 100Base-T4
22896
 PHY_AD_TX_FDXPHY_AD_TX_FDX 0x0100 smc9000.h 1=PHY is capable of 100Base-TX FDPLX
22897
 PHY_AD_TX_HDXPHY_AD_TX_HDX 0x0080 smc9000.h 1=PHY is capable of 100Base-TX HDPLX
22898
 PHY_AD_10_FDXPHY_AD_10_FDX 0x0040 smc9000.h 1=PHY is capable of 10Base-T FDPLX
22899
 PHY_AD_10_HDXPHY_AD_10_HDX 0x0020 smc9000.h 1=PHY is capable of 10Base-T HDPLX
22900
 PHY_AD_CSMAPHY_AD_CSMA 0x0001 smc9000.h 1=PHY is capable of 802.3 CMSA
22901
 PHY_RMT_REGPHY_RMT_REG 0x05 smc9000.h 　
22902
 PHY_CFG1_REGPHY_CFG1_REG 0x10 smc9000.h 　
22903
 PHY_CFG1_LNKDISPHY_CFG1_LNKDIS 0x8000 smc9000.h 1=Rx Link Detect Function disabled
22904
 PHY_CFG1_XMTDISPHY_CFG1_XMTDIS 0x4000 smc9000.h 1=TP Transmitter Disabled
22905
 PHY_CFG1_XMTPDNPHY_CFG1_XMTPDN 0x2000 smc9000.h 1=TP Transmitter Powered Down
22906
 PHY_CFG1_BYPSCRPHY_CFG1_BYPSCR 0x0400 smc9000.h 1=Bypass scrambler/descrambler
22907
 PHY_CFG1_UNSCDSPHY_CFG1_UNSCDS 0x0200 smc9000.h 1=Unscramble Idle Reception Disable
22908
 PHY_CFG1_EQLZRPHY_CFG1_EQLZR 0x0100 smc9000.h 1=Rx Equalizer Disabled
22909
 PHY_CFG1_CABLEPHY_CFG1_CABLE 0x0080 smc9000.h 1=STP(150ohm), 0=UTP(100ohm)
22910
 PHY_CFG1_RLVL0PHY_CFG1_RLVL0 0x0040 smc9000.h 1=Rx Squelch level reduced by 4.5db
22911
 PHY_CFG1_TLVL_SHIFTPHY_CFG1_TLVL_SHIFT 2 smc9000.h Transmit Output Level Adjust
22912
 PHY_CFG1_TLVL_MASKPHY_CFG1_TLVL_MASK 0x003C smc9000.h 　
22913
 PHY_CFG1_TRF_MASKPHY_CFG1_TRF_MASK 0x0003 smc9000.h Transmitter Rise/Fall time
22914
 PHY_CFG2_REGPHY_CFG2_REG 0x11 smc9000.h 　
22915
 PHY_CFG2_APOLDISPHY_CFG2_APOLDIS 0x0020 smc9000.h 1=Auto Polarity Correction disabled
22916
 PHY_CFG2_JABDISPHY_CFG2_JABDIS 0x0010 smc9000.h 1=Jabber disabled
22917
 PHY_CFG2_MREGPHY_CFG2_MREG 0x0008 smc9000.h 1=Multiple register access (MII mgt)
22918
 PHY_CFG2_INTMDIOPHY_CFG2_INTMDIO 0x0004 smc9000.h 1=Interrupt signaled with MDIO pulseo
22919
 PHY_INT_REGPHY_INT_REG 0x12 smc9000.h Status Output (Interrupt Status)
22920
 PHY_INT_INTPHY_INT_INT 0x8000 smc9000.h 1=bits have changed since last read
22921
 PHY_INT_LNKFAILPHY_INT_LNKFAIL 0x4000 smc9000.h 1=Link Not detected
22922
 PHY_INT_LOSSSYNCPHY_INT_LOSSSYNC 0x2000 smc9000.h 1=Descrambler has lost sync
22923
 PHY_INT_CWRDPHY_INT_CWRD 0x1000 smc9000.h 1=Invalid 4B5B code detected on rx
22924
 PHY_INT_SSDPHY_INT_SSD 0x0800 smc9000.h 1=No Start Of Stream detected on rx
22925
 PHY_INT_ESDPHY_INT_ESD 0x0400 smc9000.h 1=No End Of Stream detected on rx
22926
 PHY_INT_RPOLPHY_INT_RPOL 0x0200 smc9000.h 1=Reverse Polarity detected
22927
 PHY_INT_JABPHY_INT_JAB 0x0100 smc9000.h 1=Jabber detected
22928
 PHY_INT_SPDDETPHY_INT_SPDDET 0x0080 smc9000.h 1=100Base-TX mode, 0=10Base-T mode
22929
 PHY_INT_DPLXDETPHY_INT_DPLXDET 0x0040 smc9000.h 1=Device in Full Duplex
22930
 PHY_MASK_REGPHY_MASK_REG 0x13 smc9000.h Interrupt Mask
22931
 ADVERTISED_10baseT_HalfADVERTISED_10baseT_Half (1 << 0) tg3.h 　
22932
 ADVERTISED_10baseT_FullADVERTISED_10baseT_Full (1 << 1) tg3.h 　
22933
 ADVERTISED_100baseT_HalfADVERTISED_100baseT_Half (1 << 2) tg3.h 　
22934
 ADVERTISED_100baseT_FullADVERTISED_100baseT_Full (1 << 3) tg3.h 　
22935
 ADVERTISED_1000baseT_HalfADVERTISED_1000baseT_Half (1 << 4) tg3.h 　
22936
 ADVERTISED_1000baseT_FullADVERTISED_1000baseT_Full (1 << 5) tg3.h 　
22937
 ADVERTISED_AutonegADVERTISED_Autoneg (1 << 6) tg3.h 　
22938
 ADVERTISED_TPADVERTISED_TP (1 << 7) tg3.h 　
22939
 ADVERTISED_AUIADVERTISED_AUI (1 << 8) tg3.h 　
22940
 ADVERTISED_MIIADVERTISED_MII (1 << 9) tg3.h 　
22941
 ADVERTISED_FIBREADVERTISED_FIBRE (1 << 10) tg3.h 　
22942
 ADVERTISED_BNCADVERTISED_BNC (1 << 11) tg3.h 　
22943
 SPEED_10SPEED_10 0 tg3.h 　
22944
 SPEED_100SPEED_100 1 tg3.h 　
22945
 SPEED_1000SPEED_1000 2 tg3.h 　
22946
 SPEED_INVALIDSPEED_INVALID 3 tg3.h 　
22947
 DUPLEX_HALFDUPLEX_HALF 0x00 tg3.h 　
22948
 DUPLEX_FULLDUPLEX_FULL 0x01 tg3.h 　
22949
 DUPLEX_INVALIDDUPLEX_INVALID 0x02 tg3.h 　
22950
 PORT_TPPORT_TP 0x00 tg3.h 　
22951
 PORT_AUIPORT_AUI 0x01 tg3.h 　
22952
 PORT_MIIPORT_MII 0x02 tg3.h 　
22953
 PORT_FIBREPORT_FIBRE 0x03 tg3.h 　
22954
 PORT_BNCPORT_BNC 0x04 tg3.h 　
22955
 XCVR_INTERNALXCVR_INTERNAL 0x00 tg3.h 　
22956
 XCVR_EXTERNALXCVR_EXTERNAL 0x01 tg3.h 　
22957
 XCVR_DUMMY1XCVR_DUMMY1 0x02 tg3.h 　
22958
 XCVR_DUMMY2XCVR_DUMMY2 0x03 tg3.h 　
22959
 XCVR_DUMMY3XCVR_DUMMY3 0x04 tg3.h 　
22960
 AUTONEG_DISABLEAUTONEG_DISABLE 0x00 tg3.h 　
22961
 AUTONEG_ENABLEAUTONEG_ENABLE 0x01 tg3.h 　
22962
 WAKE_PHYWAKE_PHY (1 << 0) tg3.h 　
22963
 WAKE_UCASTWAKE_UCAST (1 << 1) tg3.h 　
22964
 WAKE_MCASTWAKE_MCAST (1 << 2) tg3.h 　
22965
 WAKE_BCASTWAKE_BCAST (1 << 3) tg3.h 　
22966
 WAKE_ARPWAKE_ARP (1 << 4) tg3.h 　
22967
 WAKE_MAGICWAKE_MAGIC (1 << 5) tg3.h 　
22968
 WAKE_MAGICSECUREWAKE_MAGICSECURE (1 << 6) tg3.h only meaningful if WAKE_MAGIC
22969
 TG3_64BIT_REG_HIGHTG3_64BIT_REG_HIGH 0x00UL tg3.h 　
22970
 TG3_64BIT_REG_LOWTG3_64BIT_REG_LOW 0x04UL tg3.h 　
22971
 TG3_BDINFO_HOST_ADDRTG3_BDINFO_HOST_ADDR 0x0UL tg3.h 64-bit
22972
 TG3_BDINFO_MAXLEN_FLAGSTG3_BDINFO_MAXLEN_FLAGS 0x8UL tg3.h 32-bit
22973
 BDINFO_FLAGS_USE_EXT_RECVBDINFO_FLAGS_USE_EXT_RECV 0x00000001 tg3.h ext rx_buffer_desc
22974
 BDINFO_FLAGS_DISABLEDBDINFO_FLAGS_DISABLED 0x00000002 tg3.h 　
22975
 BDINFO_FLAGS_MAXLEN_MASKBDINFO_FLAGS_MAXLEN_MASK 0xffff0000 tg3.h 　
22976
 BDINFO_FLAGS_MAXLEN_SHIFTBDINFO_FLAGS_MAXLEN_SHIFT 16 tg3.h 　
22977
 TG3_BDINFO_NIC_ADDRTG3_BDINFO_NIC_ADDR 0xcUL tg3.h 32-bit
22978
 TG3_BDINFO_SIZETG3_BDINFO_SIZE 0x10UL tg3.h 　
22979
 RX_COPY_THRESHOLDRX_COPY_THRESHOLD 256 tg3.h 　
22980
 RX_STD_MAX_SIZERX_STD_MAX_SIZE 1536 tg3.h 　
22981
 RX_STD_MAX_SIZE_5705RX_STD_MAX_SIZE_5705 512 tg3.h 　
22982
 RX_JUMBO_MAX_SIZERX_JUMBO_MAX_SIZE 0xdeadbeef tg3.h XXX
22983
 TG3PCI_VENDORTG3PCI_VENDOR 0x00000000 tg3.h 　
22984
 TG3PCI_VENDOR_BROADCOMTG3PCI_VENDOR_BROADCOM 0x14e4 tg3.h 　
22985
 TG3PCI_DEVICETG3PCI_DEVICE 0x00000002 tg3.h 　
22986
 TG3PCI_DEVICE_TIGON3_1TG3PCI_DEVICE_TIGON3_1 0x1644 tg3.h BCM5700
22987
 TG3PCI_DEVICE_TIGON3_2TG3PCI_DEVICE_TIGON3_2 0x1645 tg3.h BCM5701
22988
 TG3PCI_DEVICE_TIGON3_3TG3PCI_DEVICE_TIGON3_3 0x1646 tg3.h BCM5702
22989
 TG3PCI_DEVICE_TIGON3_4TG3PCI_DEVICE_TIGON3_4 0x1647 tg3.h BCM5703
22990
 TG3PCI_COMMANDTG3PCI_COMMAND 0x00000004 tg3.h 　
22991
 TG3PCI_STATUSTG3PCI_STATUS 0x00000006 tg3.h 　
22992
 TG3PCI_CCREVIDTG3PCI_CCREVID 0x00000008 tg3.h 　
22993
 TG3PCI_CACHELINESZTG3PCI_CACHELINESZ 0x0000000c tg3.h 　
22994
 TG3PCI_LATTIMERTG3PCI_LATTIMER 0x0000000d tg3.h 　
22995
 TG3PCI_HEADERTYPETG3PCI_HEADERTYPE 0x0000000e tg3.h 　
22996
 TG3PCI_BISTTG3PCI_BIST 0x0000000f tg3.h 　
22997
 TG3PCI_BASE0_LOWTG3PCI_BASE0_LOW 0x00000010 tg3.h 　
22998
 TG3PCI_BASE0_HIGHTG3PCI_BASE0_HIGH 0x00000014 tg3.h 　
22999
 TG3PCI_SUBSYSVENIDTG3PCI_SUBSYSVENID 0x0000002c tg3.h 　
23000
 TG3PCI_SUBSYSIDTG3PCI_SUBSYSID 0x0000002e tg3.h 　
23001
 TG3PCI_ROMADDRTG3PCI_ROMADDR 0x00000030 tg3.h 　
23002
 TG3PCI_CAPLISTTG3PCI_CAPLIST 0x00000034 tg3.h 　
23003
 TG3PCI_IRQ_LINETG3PCI_IRQ_LINE 0x0000003c tg3.h 　
23004
 TG3PCI_IRQ_PINTG3PCI_IRQ_PIN 0x0000003d tg3.h 　
23005
 TG3PCI_MIN_GNTTG3PCI_MIN_GNT 0x0000003e tg3.h 　
23006
 TG3PCI_MAX_LATTG3PCI_MAX_LAT 0x0000003f tg3.h 　
23007
 TG3PCI_X_CAPSTG3PCI_X_CAPS 0x00000040 tg3.h 　
23008
 PCIX_CAPS_RELAXED_ORDERINGPCIX_CAPS_RELAXED_ORDERING 0x00020000 tg3.h 　
23009
 PCIX_CAPS_SPLIT_MASKPCIX_CAPS_SPLIT_MASK 0x00700000 tg3.h 　
23010
 PCIX_CAPS_SPLIT_SHIFTPCIX_CAPS_SPLIT_SHIFT 20 tg3.h 　
23011
 PCIX_CAPS_BURST_MASKPCIX_CAPS_BURST_MASK 0x000c0000 tg3.h 　
23012
 PCIX_CAPS_BURST_SHIFTPCIX_CAPS_BURST_SHIFT 18 tg3.h 　
23013
 PCIX_CAPS_MAX_BURST_CPIOBPCIX_CAPS_MAX_BURST_CPIOB 2 tg3.h 　
23014
 TG3PCI_PM_CAP_PTRTG3PCI_PM_CAP_PTR 0x00000041 tg3.h 　
23015
 TG3PCI_X_COMMANDTG3PCI_X_COMMAND 0x00000042 tg3.h 　
23016
 TG3PCI_X_STATUSTG3PCI_X_STATUS 0x00000044 tg3.h 　
23017
 TG3PCI_PM_CAP_IDTG3PCI_PM_CAP_ID 0x00000048 tg3.h 　
23018
 TG3PCI_VPD_CAP_PTRTG3PCI_VPD_CAP_PTR 0x00000049 tg3.h 　
23019
 TG3PCI_PM_CAPSTG3PCI_PM_CAPS 0x0000004a tg3.h 　
23020
 TG3PCI_PM_CTRL_STATTG3PCI_PM_CTRL_STAT 0x0000004c tg3.h 　
23021
 TG3PCI_BR_SUPP_EXTTG3PCI_BR_SUPP_EXT 0x0000004e tg3.h 　
23022
 TG3PCI_PM_DATATG3PCI_PM_DATA 0x0000004f tg3.h 　
23023
 TG3PCI_VPD_CAP_IDTG3PCI_VPD_CAP_ID 0x00000050 tg3.h 　
23024
 TG3PCI_MSI_CAP_PTRTG3PCI_MSI_CAP_PTR 0x00000051 tg3.h 　
23025
 TG3PCI_VPD_ADDR_FLAGTG3PCI_VPD_ADDR_FLAG 0x00000052 tg3.h 　
23026
 VPD_ADDR_FLAG_WRITEVPD_ADDR_FLAG_WRITE 0x00008000 tg3.h 　
23027
 TG3PCI_VPD_DATATG3PCI_VPD_DATA 0x00000054 tg3.h 　
23028
 TG3PCI_MSI_CAP_IDTG3PCI_MSI_CAP_ID 0x00000058 tg3.h 　
23029
 TG3PCI_NXT_CAP_PTRTG3PCI_NXT_CAP_PTR 0x00000059 tg3.h 　
23030
 TG3PCI_MSI_CTRLTG3PCI_MSI_CTRL 0x0000005a tg3.h 　
23031
 TG3PCI_MSI_ADDR_LOWTG3PCI_MSI_ADDR_LOW 0x0000005c tg3.h 　
23032
 TG3PCI_MSI_ADDR_HIGHTG3PCI_MSI_ADDR_HIGH 0x00000060 tg3.h 　
23033
 TG3PCI_MSI_DATATG3PCI_MSI_DATA 0x00000064 tg3.h 　
23034
 TG3PCI_MISC_HOST_CTRLTG3PCI_MISC_HOST_CTRL 0x00000068 tg3.h 　
23035
 MISC_HOST_CTRL_CLEAR_INTMISC_HOST_CTRL_CLEAR_INT 0x00000001 tg3.h 　
23036
 MISC_HOST_CTRL_MASK_PCI_INTMISC_HOST_CTRL_MASK_PCI_INT 0x00000002 tg3.h 　
23037
 MISC_HOST_CTRL_BYTE_SWAPMISC_HOST_CTRL_BYTE_SWAP 0x00000004 tg3.h 　
23038
 MISC_HOST_CTRL_WORD_SWAPMISC_HOST_CTRL_WORD_SWAP 0x00000008 tg3.h 　
23039
 MISC_HOST_CTRL_PCISTATE_RWMISC_HOST_CTRL_PCISTATE_RW 0x00000010 tg3.h 　
23040
 MISC_HOST_CTRL_CLKREG_RWMISC_HOST_CTRL_CLKREG_RW 0x00000020 tg3.h 　
23041
 MISC_HOST_CTRL_REGWORD_SWAPMISC_HOST_CTRL_REGWORD_SWAP 0x00000040 tg3.h 　
23042
 MISC_HOST_CTRL_INDIR_ACCESSMISC_HOST_CTRL_INDIR_ACCESS 0x00000080 tg3.h 　
23043
 MISC_HOST_CTRL_IRQ_MASK_MODEMISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100 tg3.h 　
23044
 MISC_HOST_CTRL_TAGGED_STATUSMISC_HOST_CTRL_TAGGED_STATUS 0x00000200 tg3.h 　
23045
 MISC_HOST_CTRL_CHIPREVMISC_HOST_CTRL_CHIPREV 0xffff0000 tg3.h 　
23046
 MISC_HOST_CTRL_CHIPREV_SHIFTMISC_HOST_CTRL_CHIPREV_SHIFT 16 tg3.h 　
23047
 CHIPREV_ID_5700_A0CHIPREV_ID_5700_A0 0x7000 tg3.h 　
23048
 CHIPREV_ID_5700_A1CHIPREV_ID_5700_A1 0x7001 tg3.h 　
23049
 CHIPREV_ID_5700_B0CHIPREV_ID_5700_B0 0x7100 tg3.h 　
23050
 CHIPREV_ID_5700_B1CHIPREV_ID_5700_B1 0x7101 tg3.h 　
23051
 CHIPREV_ID_5700_B3CHIPREV_ID_5700_B3 0x7102 tg3.h 　
23052
 CHIPREV_ID_5700_ALTIMACHIPREV_ID_5700_ALTIMA 0x7104 tg3.h 　
23053
 CHIPREV_ID_5700_C0CHIPREV_ID_5700_C0 0x7200 tg3.h 　
23054
 CHIPREV_ID_5701_A0CHIPREV_ID_5701_A0 0x0000 tg3.h 　
23055
 CHIPREV_ID_5701_B0CHIPREV_ID_5701_B0 0x0100 tg3.h 　
23056
 CHIPREV_ID_5701_B2CHIPREV_ID_5701_B2 0x0102 tg3.h 　
23057
 CHIPREV_ID_5701_B5CHIPREV_ID_5701_B5 0x0105 tg3.h 　
23058
 CHIPREV_ID_5703_A0CHIPREV_ID_5703_A0 0x1000 tg3.h 　
23059
 CHIPREV_ID_5703_A1CHIPREV_ID_5703_A1 0x1001 tg3.h 　
23060
 CHIPREV_ID_5703_A2CHIPREV_ID_5703_A2 0x1002 tg3.h 　
23061
 CHIPREV_ID_5703_A3CHIPREV_ID_5703_A3 0x1003 tg3.h 　
23062
 CHIPREV_ID_5704_A0CHIPREV_ID_5704_A0 0x2000 tg3.h 　
23063
 CHIPREV_ID_5704_A1CHIPREV_ID_5704_A1 0x2001 tg3.h 　
23064
 CHIPREV_ID_5704_A2CHIPREV_ID_5704_A2 0x2002 tg3.h 　
23065
 CHIPREV_ID_5705_A0CHIPREV_ID_5705_A0 0x3000 tg3.h 　
23066
 CHIPREV_ID_5705_A1CHIPREV_ID_5705_A1 0x3001 tg3.h 　
23067
 CHIPREV_ID_5705_A2CHIPREV_ID_5705_A2 0x3002 tg3.h 　
23068
 CHIPREV_ID_5705_A3CHIPREV_ID_5705_A3 0x3003 tg3.h 　
23069
 CHIPREV_ID_5721CHIPREV_ID_5721 0x4101 tg3.h 　
23070
 CHIPREV_ID_5750_A0CHIPREV_ID_5750_A0 0x4000 tg3.h 　
23071
 CHIPREV_ID_5750_A1CHIPREV_ID_5750_A1 0x4001 tg3.h 　
23072
 CHIPREV_ID_5750_A3CHIPREV_ID_5750_A3 0x4003 tg3.h 　
23073
 ASIC_REV_5700ASIC_REV_5700 0x07 tg3.h 　
23074
 ASIC_REV_5701ASIC_REV_5701 0x00 tg3.h 　
23075
 ASIC_REV_5703ASIC_REV_5703 0x01 tg3.h 　
23076
 ASIC_REV_5704ASIC_REV_5704 0x02 tg3.h 　
23077
 ASIC_REV_5705ASIC_REV_5705 0x03 tg3.h 　
23078
 ASIC_REV_5750ASIC_REV_5750 0x04 tg3.h 　
23079
 ASIC_REV_5787ASIC_REV_5787 0x0b tg3.h 　
23080
 CHIPREV_5700_AXCHIPREV_5700_AX 0x70 tg3.h 　
23081
 CHIPREV_5700_BXCHIPREV_5700_BX 0x71 tg3.h 　
23082
 CHIPREV_5700_CXCHIPREV_5700_CX 0x72 tg3.h 　
23083
 CHIPREV_5701_AXCHIPREV_5701_AX 0x00 tg3.h 　
23084
 METAL_REV_A0METAL_REV_A0 0x00 tg3.h 　
23085
 METAL_REV_A1METAL_REV_A1 0x01 tg3.h 　
23086
 METAL_REV_B0METAL_REV_B0 0x00 tg3.h 　
23087
 METAL_REV_B1METAL_REV_B1 0x01 tg3.h 　
23088
 METAL_REV_B2METAL_REV_B2 0x02 tg3.h 　
23089
 TG3PCI_DMA_RW_CTRLTG3PCI_DMA_RW_CTRL 0x0000006c tg3.h 　
23090
 DMA_RWCTRL_MIN_DMADMA_RWCTRL_MIN_DMA 0x000000ff tg3.h 　
23091
 DMA_RWCTRL_MIN_DMA_SHIFTDMA_RWCTRL_MIN_DMA_SHIFT 0 tg3.h 　
23092
 DMA_RWCTRL_READ_BNDRY_MASKDMA_RWCTRL_READ_BNDRY_MASK 0x00000700 tg3.h 　
23093
 DMA_RWCTRL_READ_BNDRY_DISABDMA_RWCTRL_READ_BNDRY_DISAB 0x00000000 tg3.h 　
23094
 DMA_RWCTRL_READ_BNDRY_16DMA_RWCTRL_READ_BNDRY_16 0x00000100 tg3.h 　
23095
 DMA_RWCTRL_READ_BNDRY_32DMA_RWCTRL_READ_BNDRY_32 0x00000200 tg3.h 　
23096
 DMA_RWCTRL_READ_BNDRY_64DMA_RWCTRL_READ_BNDRY_64 0x00000300 tg3.h 　
23097
 DMA_RWCTRL_READ_BNDRY_128DMA_RWCTRL_READ_BNDRY_128 0x00000400 tg3.h 　
23098
 DMA_RWCTRL_READ_BNDRY_256DMA_RWCTRL_READ_BNDRY_256 0x00000500 tg3.h 　
23099
 DMA_RWCTRL_READ_BNDRY_512DMA_RWCTRL_READ_BNDRY_512 0x00000600 tg3.h 　
23100
 DMA_RWCTRL_READ_BNDRY_1024DMA_RWCTRL_READ_BNDRY_1024 0x00000700 tg3.h 　
23101
 DMA_RWCTRL_WRITE_BNDRY_MASKDMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800 tg3.h 　
23102
 DMA_RWCTRL_WRITE_BNDRY_DISABDMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000 tg3.h 　
23103
 DMA_RWCTRL_WRITE_BNDRY_16DMA_RWCTRL_WRITE_BNDRY_16 0x00000800 tg3.h 　
23104
 DMA_RWCTRL_WRITE_BNDRY_32DMA_RWCTRL_WRITE_BNDRY_32 0x00001000 tg3.h 　
23105
 DMA_RWCTRL_WRITE_BNDRY_64DMA_RWCTRL_WRITE_BNDRY_64 0x00001800 tg3.h 　
23106
 DMA_RWCTRL_WRITE_BNDRY_128DMA_RWCTRL_WRITE_BNDRY_128 0x00002000 tg3.h 　
23107
 DMA_RWCTRL_WRITE_BNDRY_256DMA_RWCTRL_WRITE_BNDRY_256 0x00002800 tg3.h 　
23108
 DMA_RWCTRL_WRITE_BNDRY_512DMA_RWCTRL_WRITE_BNDRY_512 0x00003000 tg3.h 　
23109
 DMA_RWCTRL_WRITE_BNDRY_1024DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800 tg3.h 　
23110
 DMA_RWCTRL_ONE_DMADMA_RWCTRL_ONE_DMA 0x00004000 tg3.h 　
23111
 DMA_RWCTRL_READ_WATERDMA_RWCTRL_READ_WATER 0x00070000 tg3.h 　
23112
 DMA_RWCTRL_READ_WATER_SHIFTDMA_RWCTRL_READ_WATER_SHIFT 16 tg3.h 　
23113
 DMA_RWCTRL_WRITE_WATERDMA_RWCTRL_WRITE_WATER 0x00380000 tg3.h 　
23114
 DMA_RWCTRL_WRITE_WATER_SHIFTDMA_RWCTRL_WRITE_WATER_SHIFT 19 tg3.h 　
23115
 DMA_RWCTRL_USE_MEM_READ_MULTDMA_RWCTRL_USE_MEM_READ_MULT 0x00400000 tg3.h 　
23116
 DMA_RWCTRL_ASSERT_ALL_BEDMA_RWCTRL_ASSERT_ALL_BE 0x00800000 tg3.h 　
23117
 DMA_RWCTRL_PCI_READ_CMDDMA_RWCTRL_PCI_READ_CMD 0x0f000000 tg3.h 　
23118
 DMA_RWCTRL_PCI_READ_CMD_SHIFTDMA_RWCTRL_PCI_READ_CMD_SHIFT 24 tg3.h 　
23119
 DMA_RWCTRL_PCI_WRITE_CMDDMA_RWCTRL_PCI_WRITE_CMD 0xf0000000 tg3.h 　
23120
 DMA_RWCTRL_PCI_WRITE_CMD_SHIFTDMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28 tg3.h 　
23121
 TG3PCI_PCISTATETG3PCI_PCISTATE 0x00000070 tg3.h 　
23122
 PCISTATE_FORCE_RESETPCISTATE_FORCE_RESET 0x00000001 tg3.h 　
23123
 PCISTATE_INT_NOT_ACTIVEPCISTATE_INT_NOT_ACTIVE 0x00000002 tg3.h 　
23124
 PCISTATE_CONV_PCI_MODEPCISTATE_CONV_PCI_MODE 0x00000004 tg3.h 　
23125
 PCISTATE_BUS_SPEED_HIGHPCISTATE_BUS_SPEED_HIGH 0x00000008 tg3.h 　
23126
 PCISTATE_BUS_32BITPCISTATE_BUS_32BIT 0x00000010 tg3.h 　
23127
 PCISTATE_ROM_ENABLEPCISTATE_ROM_ENABLE 0x00000020 tg3.h 　
23128
 PCISTATE_ROM_RETRY_ENABLEPCISTATE_ROM_RETRY_ENABLE 0x00000040 tg3.h 　
23129
 PCISTATE_FLAT_VIEWPCISTATE_FLAT_VIEW 0x00000100 tg3.h 　
23130
 PCISTATE_RETRY_SAME_DMAPCISTATE_RETRY_SAME_DMA 0x00002000 tg3.h 　
23131
 TG3PCI_CLOCK_CTRLTG3PCI_CLOCK_CTRL 0x00000074 tg3.h 　
23132
 CLOCK_CTRL_CORECLK_DISABLECLOCK_CTRL_CORECLK_DISABLE 0x00000200 tg3.h 　
23133
 CLOCK_CTRL_RXCLK_DISABLECLOCK_CTRL_RXCLK_DISABLE 0x00000400 tg3.h 　
23134
 CLOCK_CTRL_TXCLK_DISABLECLOCK_CTRL_TXCLK_DISABLE 0x00000800 tg3.h 　
23135
 CLOCK_CTRL_ALTCLKCLOCK_CTRL_ALTCLK 0x00001000 tg3.h 　
23136
 CLOCK_CTRL_PWRDOWN_PLL133CLOCK_CTRL_PWRDOWN_PLL133 0x00008000 tg3.h 　
23137
 CLOCK_CTRL_44MHZ_CORECLOCK_CTRL_44MHZ_CORE 0x00040000 tg3.h 　
23138
 CLOCK_CTRL_625_CORECLOCK_CTRL_625_CORE 0x00100000 tg3.h 　
23139
 CLOCK_CTRL_FORCE_CLKRUNCLOCK_CTRL_FORCE_CLKRUN 0x00200000 tg3.h 　
23140
 CLOCK_CTRL_CLKRUN_OENABLECLOCK_CTRL_CLKRUN_OENABLE 0x00400000 tg3.h 　
23141
 CLOCK_CTRL_DELAY_PCI_GRANTCLOCK_CTRL_DELAY_PCI_GRANT 0x80000000 tg3.h 　
23142
 TG3PCI_REG_BASE_ADDRTG3PCI_REG_BASE_ADDR 0x00000078 tg3.h 　
23143
 TG3PCI_MEM_WIN_BASE_ADDRTG3PCI_MEM_WIN_BASE_ADDR 0x0000007c tg3.h 　
23144
 TG3PCI_REG_DATATG3PCI_REG_DATA 0x00000080 tg3.h 　
23145
 TG3PCI_MEM_WIN_DATATG3PCI_MEM_WIN_DATA 0x00000084 tg3.h 　
23146
 TG3PCI_MODE_CTRLTG3PCI_MODE_CTRL 0x00000088 tg3.h 　
23147
 TG3PCI_MISC_CFGTG3PCI_MISC_CFG 0x0000008c tg3.h 　
23148
 TG3PCI_MISC_LOCAL_CTRLTG3PCI_MISC_LOCAL_CTRL 0x00000090 tg3.h 　
23149
 TG3PCI_STD_RING_PROD_IDXTG3PCI_STD_RING_PROD_IDX 0x00000098 tg3.h 64-bit
23150
 TG3PCI_RCV_RET_RING_CON_IDXTG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 tg3.h 64-bit
23151
 TG3PCI_SND_PROD_IDXTG3PCI_SND_PROD_IDX 0x000000a8 tg3.h 64-bit
23152
 MAILBOX_INTERRUPT_0MAILBOX_INTERRUPT_0 0x00000200 tg3.h 64-bit
23153
 MAILBOX_INTERRUPT_1MAILBOX_INTERRUPT_1 0x00000208 tg3.h 64-bit
23154
 MAILBOX_INTERRUPT_2MAILBOX_INTERRUPT_2 0x00000210 tg3.h 64-bit
23155
 MAILBOX_INTERRUPT_3MAILBOX_INTERRUPT_3 0x00000218 tg3.h 64-bit
23156
 MAILBOX_GENERAL_0MAILBOX_GENERAL_0 0x00000220 tg3.h 64-bit
23157
 MAILBOX_GENERAL_1MAILBOX_GENERAL_1 0x00000228 tg3.h 64-bit
23158
 MAILBOX_GENERAL_2MAILBOX_GENERAL_2 0x00000230 tg3.h 64-bit
23159
 MAILBOX_GENERAL_3MAILBOX_GENERAL_3 0x00000238 tg3.h 64-bit
23160
 MAILBOX_GENERAL_4MAILBOX_GENERAL_4 0x00000240 tg3.h 64-bit
23161
 MAILBOX_GENERAL_5MAILBOX_GENERAL_5 0x00000248 tg3.h 64-bit
23162
 MAILBOX_GENERAL_6MAILBOX_GENERAL_6 0x00000250 tg3.h 64-bit
23163
 MAILBOX_GENERAL_7MAILBOX_GENERAL_7 0x00000258 tg3.h 64-bit
23164
 MAILBOX_RELOAD_STATMAILBOX_RELOAD_STAT 0x00000260 tg3.h 64-bit
23165
 MAILBOX_RCV_STD_PROD_IDXMAILBOX_RCV_STD_PROD_IDX 0x00000268 tg3.h 64-bit
23166
 MAILBOX_RCV_JUMBO_PROD_IDXMAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 tg3.h 64-bit
23167
 MAILBOX_RCV_MINI_PROD_IDXMAILBOX_RCV_MINI_PROD_IDX 0x00000278 tg3.h 64-bit
23168
 MAILBOX_RCVRET_CON_IDX_0MAILBOX_RCVRET_CON_IDX_0 0x00000280 tg3.h 64-bit
23169
 MAILBOX_RCVRET_CON_IDX_1MAILBOX_RCVRET_CON_IDX_1 0x00000288 tg3.h 64-bit
23170
 MAILBOX_RCVRET_CON_IDX_2MAILBOX_RCVRET_CON_IDX_2 0x00000290 tg3.h 64-bit
23171
 MAILBOX_RCVRET_CON_IDX_3MAILBOX_RCVRET_CON_IDX_3 0x00000298 tg3.h 64-bit
23172
 MAILBOX_RCVRET_CON_IDX_4MAILBOX_RCVRET_CON_IDX_4 0x000002a0 tg3.h 64-bit
23173
 MAILBOX_RCVRET_CON_IDX_5MAILBOX_RCVRET_CON_IDX_5 0x000002a8 tg3.h 64-bit
23174
 MAILBOX_RCVRET_CON_IDX_6MAILBOX_RCVRET_CON_IDX_6 0x000002b0 tg3.h 64-bit
23175
 MAILBOX_RCVRET_CON_IDX_7MAILBOX_RCVRET_CON_IDX_7 0x000002b8 tg3.h 64-bit
23176
 MAILBOX_RCVRET_CON_IDX_8MAILBOX_RCVRET_CON_IDX_8 0x000002c0 tg3.h 64-bit
23177
 MAILBOX_RCVRET_CON_IDX_9MAILBOX_RCVRET_CON_IDX_9 0x000002c8 tg3.h 64-bit
23178
 MAILBOX_RCVRET_CON_IDX_10MAILBOX_RCVRET_CON_IDX_10 0x000002d0 tg3.h 64-bit
23179
 MAILBOX_RCVRET_CON_IDX_11MAILBOX_RCVRET_CON_IDX_11 0x000002d8 tg3.h 64-bit
23180
 MAILBOX_RCVRET_CON_IDX_12MAILBOX_RCVRET_CON_IDX_12 0x000002e0 tg3.h 64-bit
23181
 MAILBOX_RCVRET_CON_IDX_13MAILBOX_RCVRET_CON_IDX_13 0x000002e8 tg3.h 64-bit
23182
 MAILBOX_RCVRET_CON_IDX_14MAILBOX_RCVRET_CON_IDX_14 0x000002f0 tg3.h 64-bit
23183
 MAILBOX_RCVRET_CON_IDX_15MAILBOX_RCVRET_CON_IDX_15 0x000002f8 tg3.h 64-bit
23184
 MAILBOX_SNDHOST_PROD_IDX_0MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 tg3.h 64-bit
23185
 MAILBOX_SNDHOST_PROD_IDX_1MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 tg3.h 64-bit
23186
 MAILBOX_SNDHOST_PROD_IDX_2MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 tg3.h 64-bit
23187
 MAILBOX_SNDHOST_PROD_IDX_3MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 tg3.h 64-bit
23188
 MAILBOX_SNDHOST_PROD_IDX_4MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 tg3.h 64-bit
23189
 MAILBOX_SNDHOST_PROD_IDX_5MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 tg3.h 64-bit
23190
 MAILBOX_SNDHOST_PROD_IDX_6MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 tg3.h 64-bit
23191
 MAILBOX_SNDHOST_PROD_IDX_7MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 tg3.h 64-bit
23192
 MAILBOX_SNDHOST_PROD_IDX_8MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 tg3.h 64-bit
23193
 MAILBOX_SNDHOST_PROD_IDX_9MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 tg3.h 64-bit
23194
 MAILBOX_SNDHOST_PROD_IDX_10MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 tg3.h 64-bit
23195
 MAILBOX_SNDHOST_PROD_IDX_11MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 tg3.h 64-bit
23196
 MAILBOX_SNDHOST_PROD_IDX_12MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 tg3.h 64-bit
23197
 MAILBOX_SNDHOST_PROD_IDX_13MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 tg3.h 64-bit
23198
 MAILBOX_SNDHOST_PROD_IDX_14MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 tg3.h 64-bit
23199
 MAILBOX_SNDHOST_PROD_IDX_15MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 tg3.h 64-bit
23200
 MAILBOX_SNDNIC_PROD_IDX_0MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 tg3.h 64-bit
23201
 MAILBOX_SNDNIC_PROD_IDX_1MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 tg3.h 64-bit
23202
 MAILBOX_SNDNIC_PROD_IDX_2MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 tg3.h 64-bit
23203
 MAILBOX_SNDNIC_PROD_IDX_3MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 tg3.h 64-bit
23204
 MAILBOX_SNDNIC_PROD_IDX_4MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 tg3.h 64-bit
23205
 MAILBOX_SNDNIC_PROD_IDX_5MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 tg3.h 64-bit
23206
 MAILBOX_SNDNIC_PROD_IDX_6MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 tg3.h 64-bit
23207
 MAILBOX_SNDNIC_PROD_IDX_7MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 tg3.h 64-bit
23208
 MAILBOX_SNDNIC_PROD_IDX_8MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 tg3.h 64-bit
23209
 MAILBOX_SNDNIC_PROD_IDX_9MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 tg3.h 64-bit
23210
 MAILBOX_SNDNIC_PROD_IDX_10MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 tg3.h 64-bit
23211
 MAILBOX_SNDNIC_PROD_IDX_11MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 tg3.h 64-bit
23212
 MAILBOX_SNDNIC_PROD_IDX_12MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 tg3.h 64-bit
23213
 MAILBOX_SNDNIC_PROD_IDX_13MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 tg3.h 64-bit
23214
 MAILBOX_SNDNIC_PROD_IDX_14MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 tg3.h 64-bit
23215
 MAILBOX_SNDNIC_PROD_IDX_15MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 tg3.h 64-bit
23216
 MAC_MODEMAC_MODE 0x00000400 tg3.h 　
23217
 MAC_MODE_RESETMAC_MODE_RESET 0x00000001 tg3.h 　
23218
 MAC_MODE_HALF_DUPLEXMAC_MODE_HALF_DUPLEX 0x00000002 tg3.h 　
23219
 MAC_MODE_PORT_MODE_MASKMAC_MODE_PORT_MODE_MASK 0x0000000c tg3.h 　
23220
 MAC_MODE_PORT_MODE_TBIMAC_MODE_PORT_MODE_TBI 0x0000000c tg3.h 　
23221
 MAC_MODE_PORT_MODE_GMIIMAC_MODE_PORT_MODE_GMII 0x00000008 tg3.h 　
23222
 MAC_MODE_PORT_MODE_MIIMAC_MODE_PORT_MODE_MII 0x00000004 tg3.h 　
23223
 MAC_MODE_PORT_MODE_NONEMAC_MODE_PORT_MODE_NONE 0x00000000 tg3.h 　
23224
 MAC_MODE_PORT_INT_LPBACKMAC_MODE_PORT_INT_LPBACK 0x00000010 tg3.h 　
23225
 MAC_MODE_TAGGED_MAC_CTRLMAC_MODE_TAGGED_MAC_CTRL 0x00000080 tg3.h 　
23226
 MAC_MODE_TX_BURSTINGMAC_MODE_TX_BURSTING 0x00000100 tg3.h 　
23227
 MAC_MODE_MAX_DEFERMAC_MODE_MAX_DEFER 0x00000200 tg3.h 　
23228
 MAC_MODE_LINK_POLARITYMAC_MODE_LINK_POLARITY 0x00000400 tg3.h 　
23229
 MAC_MODE_RXSTAT_ENABLEMAC_MODE_RXSTAT_ENABLE 0x00000800 tg3.h 　
23230
 MAC_MODE_RXSTAT_CLEARMAC_MODE_RXSTAT_CLEAR 0x00001000 tg3.h 　
23231
 MAC_MODE_RXSTAT_FLUSHMAC_MODE_RXSTAT_FLUSH 0x00002000 tg3.h 　
23232
 MAC_MODE_TXSTAT_ENABLEMAC_MODE_TXSTAT_ENABLE 0x00004000 tg3.h 　
23233
 MAC_MODE_TXSTAT_CLEARMAC_MODE_TXSTAT_CLEAR 0x00008000 tg3.h 　
23234
 MAC_MODE_TXSTAT_FLUSHMAC_MODE_TXSTAT_FLUSH 0x00010000 tg3.h 　
23235
 MAC_MODE_SEND_CONFIGSMAC_MODE_SEND_CONFIGS 0x00020000 tg3.h 　
23236
 MAC_MODE_MAGIC_PKT_ENABLEMAC_MODE_MAGIC_PKT_ENABLE 0x00040000 tg3.h 　
23237
 MAC_MODE_ACPI_ENABLEMAC_MODE_ACPI_ENABLE 0x00080000 tg3.h 　
23238
 MAC_MODE_MIP_ENABLEMAC_MODE_MIP_ENABLE 0x00100000 tg3.h 　
23239
 MAC_MODE_TDE_ENABLEMAC_MODE_TDE_ENABLE 0x00200000 tg3.h 　
23240
 MAC_MODE_RDE_ENABLEMAC_MODE_RDE_ENABLE 0x00400000 tg3.h 　
23241
 MAC_MODE_FHDE_ENABLEMAC_MODE_FHDE_ENABLE 0x00800000 tg3.h 　
23242
 MAC_STATUSMAC_STATUS 0x00000404 tg3.h 　
23243
 MAC_STATUS_PCS_SYNCEDMAC_STATUS_PCS_SYNCED 0x00000001 tg3.h 　
23244
 MAC_STATUS_SIGNAL_DETMAC_STATUS_SIGNAL_DET 0x00000002 tg3.h 　
23245
 MAC_STATUS_RCVD_CFGMAC_STATUS_RCVD_CFG 0x00000004 tg3.h 　
23246
 MAC_STATUS_CFG_CHANGEDMAC_STATUS_CFG_CHANGED 0x00000008 tg3.h 　
23247
 MAC_STATUS_SYNC_CHANGEDMAC_STATUS_SYNC_CHANGED 0x00000010 tg3.h 　
23248
 MAC_STATUS_PORT_DEC_ERRMAC_STATUS_PORT_DEC_ERR 0x00000400 tg3.h 　
23249
 MAC_STATUS_LNKSTATE_CHANGEDMAC_STATUS_LNKSTATE_CHANGED 0x00001000 tg3.h 　
23250
 MAC_STATUS_MI_COMPLETIONMAC_STATUS_MI_COMPLETION 0x00400000 tg3.h 　
23251
 MAC_STATUS_MI_INTERRUPTMAC_STATUS_MI_INTERRUPT 0x00800000 tg3.h 　
23252
 MAC_STATUS_AP_ERRORMAC_STATUS_AP_ERROR 0x01000000 tg3.h 　
23253
 MAC_STATUS_ODI_ERRORMAC_STATUS_ODI_ERROR 0x02000000 tg3.h 　
23254
 MAC_STATUS_RXSTAT_OVERRUNMAC_STATUS_RXSTAT_OVERRUN 0x04000000 tg3.h 　
23255
 MAC_STATUS_TXSTAT_OVERRUNMAC_STATUS_TXSTAT_OVERRUN 0x08000000 tg3.h 　
23256
 MAC_EVENTMAC_EVENT 0x00000408 tg3.h 　
23257
 MAC_EVENT_PORT_DECODE_ERRMAC_EVENT_PORT_DECODE_ERR 0x00000400 tg3.h 　
23258
 MAC_EVENT_LNKSTATE_CHANGEDMAC_EVENT_LNKSTATE_CHANGED 0x00001000 tg3.h 　
23259
 MAC_EVENT_MI_COMPLETIONMAC_EVENT_MI_COMPLETION 0x00400000 tg3.h 　
23260
 MAC_EVENT_MI_INTERRUPTMAC_EVENT_MI_INTERRUPT 0x00800000 tg3.h 　
23261
 MAC_EVENT_AP_ERRORMAC_EVENT_AP_ERROR 0x01000000 tg3.h 　
23262
 MAC_EVENT_ODI_ERRORMAC_EVENT_ODI_ERROR 0x02000000 tg3.h 　
23263
 MAC_EVENT_RXSTAT_OVERRUNMAC_EVENT_RXSTAT_OVERRUN 0x04000000 tg3.h 　
23264
 MAC_EVENT_TXSTAT_OVERRUNMAC_EVENT_TXSTAT_OVERRUN 0x08000000 tg3.h 　
23265
 MAC_LED_CTRLMAC_LED_CTRL 0x0000040c tg3.h 　
23266
 LED_CTRL_LNKLED_OVERRIDELED_CTRL_LNKLED_OVERRIDE 0x00000001 tg3.h 　
23267
 LED_CTRL_1000MBPS_ONLED_CTRL_1000MBPS_ON 0x00000002 tg3.h 　
23268
 LED_CTRL_100MBPS_ONLED_CTRL_100MBPS_ON 0x00000004 tg3.h 　
23269
 LED_CTRL_10MBPS_ONLED_CTRL_10MBPS_ON 0x00000008 tg3.h 　
23270
 LED_CTRL_TRAFFIC_OVERRIDELED_CTRL_TRAFFIC_OVERRIDE 0x00000010 tg3.h 　
23271
 LED_CTRL_TRAFFIC_BLINKLED_CTRL_TRAFFIC_BLINK 0x00000020 tg3.h 　
23272
 LED_CTRL_TRAFFIC_LEDLED_CTRL_TRAFFIC_LED 0x00000040 tg3.h 　
23273
 LED_CTRL_1000MBPS_STATUSLED_CTRL_1000MBPS_STATUS 0x00000080 tg3.h 　
23274
 LED_CTRL_100MBPS_STATUSLED_CTRL_100MBPS_STATUS 0x00000100 tg3.h 　
23275
 LED_CTRL_10MBPS_STATUSLED_CTRL_10MBPS_STATUS 0x00000200 tg3.h 　
23276
 LED_CTRL_TRAFFIC_STATUSLED_CTRL_TRAFFIC_STATUS 0x00000400 tg3.h 　
23277
 LED_CTRL_MAC_MODELED_CTRL_MAC_MODE 0x00000000 tg3.h 　
23278
 LED_CTRL_PHY_MODE_1LED_CTRL_PHY_MODE_1 0x00000800 tg3.h 　
23279
 LED_CTRL_PHY_MODE_2LED_CTRL_PHY_MODE_2 0x00001000 tg3.h 　
23280
 LED_CTRL_BLINK_RATE_MASKLED_CTRL_BLINK_RATE_MASK 0x7ff80000 tg3.h 　
23281
 LED_CTRL_BLINK_RATE_SHIFTLED_CTRL_BLINK_RATE_SHIFT 19 tg3.h 　
23282
 LED_CTRL_BLINK_PER_OVERRIDELED_CTRL_BLINK_PER_OVERRIDE 0x00080000 tg3.h 　
23283
 LED_CTRL_BLINK_RATE_OVERRIDELED_CTRL_BLINK_RATE_OVERRIDE 0x80000000 tg3.h 　
23284
 MAC_ADDR_0_HIGHMAC_ADDR_0_HIGH 0x00000410 tg3.h upper 2 bytes
23285
 MAC_ADDR_0_LOWMAC_ADDR_0_LOW 0x00000414 tg3.h lower 4 bytes
23286
 MAC_ADDR_1_HIGHMAC_ADDR_1_HIGH 0x00000418 tg3.h upper 2 bytes
23287
 MAC_ADDR_1_LOWMAC_ADDR_1_LOW 0x0000041c tg3.h lower 4 bytes
23288
 MAC_ADDR_2_HIGHMAC_ADDR_2_HIGH 0x00000420 tg3.h upper 2 bytes
23289
 MAC_ADDR_2_LOWMAC_ADDR_2_LOW 0x00000424 tg3.h lower 4 bytes
23290
 MAC_ADDR_3_HIGHMAC_ADDR_3_HIGH 0x00000428 tg3.h upper 2 bytes
23291
 MAC_ADDR_3_LOWMAC_ADDR_3_LOW 0x0000042c tg3.h lower 4 bytes
23292
 MAC_ACPI_MBUF_PTRMAC_ACPI_MBUF_PTR 0x00000430 tg3.h 　
23293
 MAC_ACPI_LEN_OFFSETMAC_ACPI_LEN_OFFSET 0x00000434 tg3.h 　
23294
 ACPI_LENOFF_LEN_MASKACPI_LENOFF_LEN_MASK 0x0000ffff tg3.h 　
23295
 ACPI_LENOFF_LEN_SHIFTACPI_LENOFF_LEN_SHIFT 0 tg3.h 　
23296
 ACPI_LENOFF_OFF_MASKACPI_LENOFF_OFF_MASK 0x0fff0000 tg3.h 　
23297
 ACPI_LENOFF_OFF_SHIFTACPI_LENOFF_OFF_SHIFT 16 tg3.h 　
23298
 MAC_TX_BACKOFF_SEEDMAC_TX_BACKOFF_SEED 0x00000438 tg3.h 　
23299
 TX_BACKOFF_SEED_MASKTX_BACKOFF_SEED_MASK 0x000003ff tg3.h 　
23300
 MAC_RX_MTU_SIZEMAC_RX_MTU_SIZE 0x0000043c tg3.h 　
23301
 RX_MTU_SIZE_MASKRX_MTU_SIZE_MASK 0x0000ffff tg3.h 　
23302
 MAC_PCS_TESTMAC_PCS_TEST 0x00000440 tg3.h 　
23303
 PCS_TEST_PATTERN_MASKPCS_TEST_PATTERN_MASK 0x000fffff tg3.h 　
23304
 PCS_TEST_PATTERN_SHIFTPCS_TEST_PATTERN_SHIFT 0 tg3.h 　
23305
 PCS_TEST_ENABLEPCS_TEST_ENABLE 0x00100000 tg3.h 　
23306
 MAC_TX_AUTO_NEGMAC_TX_AUTO_NEG 0x00000444 tg3.h 　
23307
 TX_AUTO_NEG_MASKTX_AUTO_NEG_MASK 0x0000ffff tg3.h 　
23308
 TX_AUTO_NEG_SHIFTTX_AUTO_NEG_SHIFT 0 tg3.h 　
23309
 MAC_RX_AUTO_NEGMAC_RX_AUTO_NEG 0x00000448 tg3.h 　
23310
 RX_AUTO_NEG_MASKRX_AUTO_NEG_MASK 0x0000ffff tg3.h 　
23311
 RX_AUTO_NEG_SHIFTRX_AUTO_NEG_SHIFT 0 tg3.h 　
23312
 MAC_MI_COMMAC_MI_COM 0x0000044c tg3.h 　
23313
 MI_COM_CMD_MASKMI_COM_CMD_MASK 0x0c000000 tg3.h 　
23314
 MI_COM_CMD_WRITEMI_COM_CMD_WRITE 0x04000000 tg3.h 　
23315
 MI_COM_CMD_READMI_COM_CMD_READ 0x08000000 tg3.h 　
23316
 MI_COM_READ_FAILEDMI_COM_READ_FAILED 0x10000000 tg3.h 　
23317
 MI_COM_STARTMI_COM_START 0x20000000 tg3.h 　
23318
 MI_COM_BUSYMI_COM_BUSY 0x20000000 tg3.h 　
23319
 MI_COM_PHY_ADDR_MASKMI_COM_PHY_ADDR_MASK 0x03e00000 tg3.h 　
23320
 MI_COM_PHY_ADDR_SHIFTMI_COM_PHY_ADDR_SHIFT 21 tg3.h 　
23321
 MI_COM_REG_ADDR_MASKMI_COM_REG_ADDR_MASK 0x001f0000 tg3.h 　
23322
 MI_COM_REG_ADDR_SHIFTMI_COM_REG_ADDR_SHIFT 16 tg3.h 　
23323
 MI_COM_DATA_MASKMI_COM_DATA_MASK 0x0000ffff tg3.h 　
23324
 MAC_MI_STATMAC_MI_STAT 0x00000450 tg3.h 　
23325
 MAC_MI_STAT_LNKSTAT_ATTN_ENABMAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001 tg3.h 　
23326
 MAC_MI_MODEMAC_MI_MODE 0x00000454 tg3.h 　
23327
 MAC_MI_MODE_CLK_10MHZMAC_MI_MODE_CLK_10MHZ 0x00000001 tg3.h 　
23328
 MAC_MI_MODE_SHORT_PREAMBLEMAC_MI_MODE_SHORT_PREAMBLE 0x00000002 tg3.h 　
23329
 MAC_MI_MODE_AUTO_POLLMAC_MI_MODE_AUTO_POLL 0x00000010 tg3.h 　
23330
 MAC_MI_MODE_CORE_CLK_62MHZMAC_MI_MODE_CORE_CLK_62MHZ 0x00008000 tg3.h 　
23331
 MAC_MI_MODE_BASEMAC_MI_MODE_BASE 0x000c0000 tg3.h XXX magic values XXX
23332
 MAC_AUTO_POLL_STATUSMAC_AUTO_POLL_STATUS 0x00000458 tg3.h 　
23333
 MAC_AUTO_POLL_ERRORMAC_AUTO_POLL_ERROR 0x00000001 tg3.h 　
23334
 MAC_TX_MODEMAC_TX_MODE 0x0000045c tg3.h 　
23335
 TX_MODE_RESETTX_MODE_RESET 0x00000001 tg3.h 　
23336
 TX_MODE_ENABLETX_MODE_ENABLE 0x00000002 tg3.h 　
23337
 TX_MODE_FLOW_CTRL_ENABLETX_MODE_FLOW_CTRL_ENABLE 0x00000010 tg3.h 　
23338
 TX_MODE_BIG_BCKOFF_ENABLETX_MODE_BIG_BCKOFF_ENABLE 0x00000020 tg3.h 　
23339
 TX_MODE_LONG_PAUSE_ENABLETX_MODE_LONG_PAUSE_ENABLE 0x00000040 tg3.h 　
23340
 MAC_TX_STATUSMAC_TX_STATUS 0x00000460 tg3.h 　
23341
 TX_STATUS_XOFFEDTX_STATUS_XOFFED 0x00000001 tg3.h 　
23342
 TX_STATUS_SENT_XOFFTX_STATUS_SENT_XOFF 0x00000002 tg3.h 　
23343
 TX_STATUS_SENT_XONTX_STATUS_SENT_XON 0x00000004 tg3.h 　
23344
 TX_STATUS_LINK_UPTX_STATUS_LINK_UP 0x00000008 tg3.h 　
23345
 TX_STATUS_ODI_UNDERRUNTX_STATUS_ODI_UNDERRUN 0x00000010 tg3.h 　
23346
 TX_STATUS_ODI_OVERRUNTX_STATUS_ODI_OVERRUN 0x00000020 tg3.h 　
23347
 MAC_TX_LENGTHSMAC_TX_LENGTHS 0x00000464 tg3.h 　
23348
 TX_LENGTHS_SLOT_TIME_MASKTX_LENGTHS_SLOT_TIME_MASK 0x000000ff tg3.h 　
23349
 TX_LENGTHS_SLOT_TIME_SHIFTTX_LENGTHS_SLOT_TIME_SHIFT 0 tg3.h 　
23350
 TX_LENGTHS_IPG_MASKTX_LENGTHS_IPG_MASK 0x00000f00 tg3.h 　
23351
 TX_LENGTHS_IPG_SHIFTTX_LENGTHS_IPG_SHIFT 8 tg3.h 　
23352
 TX_LENGTHS_IPG_CRS_MASKTX_LENGTHS_IPG_CRS_MASK 0x00003000 tg3.h 　
23353
 TX_LENGTHS_IPG_CRS_SHIFTTX_LENGTHS_IPG_CRS_SHIFT 12 tg3.h 　
23354
 MAC_RX_MODEMAC_RX_MODE 0x00000468 tg3.h 　
23355
 RX_MODE_RESETRX_MODE_RESET 0x00000001 tg3.h 　
23356
 RX_MODE_ENABLERX_MODE_ENABLE 0x00000002 tg3.h 　
23357
 RX_MODE_FLOW_CTRL_ENABLERX_MODE_FLOW_CTRL_ENABLE 0x00000004 tg3.h 　
23358
 RX_MODE_KEEP_MAC_CTRLRX_MODE_KEEP_MAC_CTRL 0x00000008 tg3.h 　
23359
 RX_MODE_KEEP_PAUSERX_MODE_KEEP_PAUSE 0x00000010 tg3.h 　
23360
 RX_MODE_ACCEPT_OVERSIZEDRX_MODE_ACCEPT_OVERSIZED 0x00000020 tg3.h 　
23361
 RX_MODE_ACCEPT_RUNTSRX_MODE_ACCEPT_RUNTS 0x00000040 tg3.h 　
23362
 RX_MODE_LEN_CHECKRX_MODE_LEN_CHECK 0x00000080 tg3.h 　
23363
 RX_MODE_PROMISCRX_MODE_PROMISC 0x00000100 tg3.h 　
23364
 RX_MODE_NO_CRC_CHECKRX_MODE_NO_CRC_CHECK 0x00000200 tg3.h 　
23365
 RX_MODE_KEEP_VLAN_TAGRX_MODE_KEEP_VLAN_TAG 0x00000400 tg3.h 　
23366
 MAC_RX_STATUSMAC_RX_STATUS 0x0000046c tg3.h 　
23367
 RX_STATUS_REMOTE_TX_XOFFEDRX_STATUS_REMOTE_TX_XOFFED 0x00000001 tg3.h 　
23368
 RX_STATUS_XOFF_RCVDRX_STATUS_XOFF_RCVD 0x00000002 tg3.h 　
23369
 RX_STATUS_XON_RCVDRX_STATUS_XON_RCVD 0x00000004 tg3.h 　
23370
 MAC_HASH_REG_0MAC_HASH_REG_0 0x00000470 tg3.h 　
23371
 MAC_HASH_REG_1MAC_HASH_REG_1 0x00000474 tg3.h 　
23372
 MAC_HASH_REG_2MAC_HASH_REG_2 0x00000478 tg3.h 　
23373
 MAC_HASH_REG_3MAC_HASH_REG_3 0x0000047c tg3.h 　
23374
 MAC_RCV_RULE_0MAC_RCV_RULE_0 0x00000480 tg3.h 　
23375
 MAC_RCV_VALUE_0MAC_RCV_VALUE_0 0x00000484 tg3.h 　
23376
 MAC_RCV_RULE_1MAC_RCV_RULE_1 0x00000488 tg3.h 　
23377
 MAC_RCV_VALUE_1MAC_RCV_VALUE_1 0x0000048c tg3.h 　
23378
 MAC_RCV_RULE_2MAC_RCV_RULE_2 0x00000490 tg3.h 　
23379
 MAC_RCV_VALUE_2MAC_RCV_VALUE_2 0x00000494 tg3.h 　
23380
 MAC_RCV_RULE_3MAC_RCV_RULE_3 0x00000498 tg3.h 　
23381
 MAC_RCV_VALUE_3MAC_RCV_VALUE_3 0x0000049c tg3.h 　
23382
 MAC_RCV_RULE_4MAC_RCV_RULE_4 0x000004a0 tg3.h 　
23383
 MAC_RCV_VALUE_4MAC_RCV_VALUE_4 0x000004a4 tg3.h 　
23384
 MAC_RCV_RULE_5MAC_RCV_RULE_5 0x000004a8 tg3.h 　
23385
 MAC_RCV_VALUE_5MAC_RCV_VALUE_5 0x000004ac tg3.h 　
23386
 MAC_RCV_RULE_6MAC_RCV_RULE_6 0x000004b0 tg3.h 　
23387
 MAC_RCV_VALUE_6MAC_RCV_VALUE_6 0x000004b4 tg3.h 　
23388
 MAC_RCV_RULE_7MAC_RCV_RULE_7 0x000004b8 tg3.h 　
23389
 MAC_RCV_VALUE_7MAC_RCV_VALUE_7 0x000004bc tg3.h 　
23390
 MAC_RCV_RULE_8MAC_RCV_RULE_8 0x000004c0 tg3.h 　
23391
 MAC_RCV_VALUE_8MAC_RCV_VALUE_8 0x000004c4 tg3.h 　
23392
 MAC_RCV_RULE_9MAC_RCV_RULE_9 0x000004c8 tg3.h 　
23393
 MAC_RCV_VALUE_9MAC_RCV_VALUE_9 0x000004cc tg3.h 　
23394
 MAC_RCV_RULE_10MAC_RCV_RULE_10 0x000004d0 tg3.h 　
23395
 MAC_RCV_VALUE_10MAC_RCV_VALUE_10 0x000004d4 tg3.h 　
23396
 MAC_RCV_RULE_11MAC_RCV_RULE_11 0x000004d8 tg3.h 　
23397
 MAC_RCV_VALUE_11MAC_RCV_VALUE_11 0x000004dc tg3.h 　
23398
 MAC_RCV_RULE_12MAC_RCV_RULE_12 0x000004e0 tg3.h 　
23399
 MAC_RCV_VALUE_12MAC_RCV_VALUE_12 0x000004e4 tg3.h 　
23400
 MAC_RCV_RULE_13MAC_RCV_RULE_13 0x000004e8 tg3.h 　
23401
 MAC_RCV_VALUE_13MAC_RCV_VALUE_13 0x000004ec tg3.h 　
23402
 MAC_RCV_RULE_14MAC_RCV_RULE_14 0x000004f0 tg3.h 　
23403
 MAC_RCV_VALUE_14MAC_RCV_VALUE_14 0x000004f4 tg3.h 　
23404
 MAC_RCV_RULE_15MAC_RCV_RULE_15 0x000004f8 tg3.h 　
23405
 MAC_RCV_VALUE_15MAC_RCV_VALUE_15 0x000004fc tg3.h 　
23406
 RCV_RULE_DISABLE_MASKRCV_RULE_DISABLE_MASK 0x7fffffff tg3.h 　
23407
 MAC_RCV_RULE_CFGMAC_RCV_RULE_CFG 0x00000500 tg3.h 　
23408
 RCV_RULE_CFG_DEFAULT_CLASSRCV_RULE_CFG_DEFAULT_CLASS 0x00000008 tg3.h 　
23409
 MAC_LOW_WMARK_MAX_RX_FRAMEMAC_LOW_WMARK_MAX_RX_FRAME 0x00000504 tg3.h 　
23410
 MAC_HASHREGU_0MAC_HASHREGU_0 0x00000520 tg3.h 　
23411
 MAC_HASHREGU_1MAC_HASHREGU_1 0x00000524 tg3.h 　
23412
 MAC_HASHREGU_2MAC_HASHREGU_2 0x00000528 tg3.h 　
23413
 MAC_HASHREGU_3MAC_HASHREGU_3 0x0000052c tg3.h 　
23414
 MAC_EXTADDR_0_HIGHMAC_EXTADDR_0_HIGH 0x00000530 tg3.h 　
23415
 MAC_EXTADDR_0_LOWMAC_EXTADDR_0_LOW 0x00000534 tg3.h 　
23416
 MAC_EXTADDR_1_HIGHMAC_EXTADDR_1_HIGH 0x00000538 tg3.h 　
23417
 MAC_EXTADDR_1_LOWMAC_EXTADDR_1_LOW 0x0000053c tg3.h 　
23418
 MAC_EXTADDR_2_HIGHMAC_EXTADDR_2_HIGH 0x00000540 tg3.h 　
23419
 MAC_EXTADDR_2_LOWMAC_EXTADDR_2_LOW 0x00000544 tg3.h 　
23420
 MAC_EXTADDR_3_HIGHMAC_EXTADDR_3_HIGH 0x00000548 tg3.h 　
23421
 MAC_EXTADDR_3_LOWMAC_EXTADDR_3_LOW 0x0000054c tg3.h 　
23422
 MAC_EXTADDR_4_HIGHMAC_EXTADDR_4_HIGH 0x00000550 tg3.h 　
23423
 MAC_EXTADDR_4_LOWMAC_EXTADDR_4_LOW 0x00000554 tg3.h 　
23424
 MAC_EXTADDR_5_HIGHMAC_EXTADDR_5_HIGH 0x00000558 tg3.h 　
23425
 MAC_EXTADDR_5_LOWMAC_EXTADDR_5_LOW 0x0000055c tg3.h 　
23426
 MAC_EXTADDR_6_HIGHMAC_EXTADDR_6_HIGH 0x00000560 tg3.h 　
23427
 MAC_EXTADDR_6_LOWMAC_EXTADDR_6_LOW 0x00000564 tg3.h 　
23428
 MAC_EXTADDR_7_HIGHMAC_EXTADDR_7_HIGH 0x00000568 tg3.h 　
23429
 MAC_EXTADDR_7_LOWMAC_EXTADDR_7_LOW 0x0000056c tg3.h 　
23430
 MAC_EXTADDR_8_HIGHMAC_EXTADDR_8_HIGH 0x00000570 tg3.h 　
23431
 MAC_EXTADDR_8_LOWMAC_EXTADDR_8_LOW 0x00000574 tg3.h 　
23432
 MAC_EXTADDR_9_HIGHMAC_EXTADDR_9_HIGH 0x00000578 tg3.h 　
23433
 MAC_EXTADDR_9_LOWMAC_EXTADDR_9_LOW 0x0000057c tg3.h 　
23434
 MAC_EXTADDR_10_HIGHMAC_EXTADDR_10_HIGH 0x00000580 tg3.h 　
23435
 MAC_EXTADDR_10_LOWMAC_EXTADDR_10_LOW 0x00000584 tg3.h 　
23436
 MAC_EXTADDR_11_HIGHMAC_EXTADDR_11_HIGH 0x00000588 tg3.h 　
23437
 MAC_EXTADDR_11_LOWMAC_EXTADDR_11_LOW 0x0000058c tg3.h 　
23438
 MAC_SERDES_CFGMAC_SERDES_CFG 0x00000590 tg3.h 　
23439
 MAC_SERDES_STATMAC_SERDES_STAT 0x00000594 tg3.h 　
23440
 MAC_TX_MAC_STATE_BASEMAC_TX_MAC_STATE_BASE 0x00000600 tg3.h 16 bytes
23441
 MAC_RX_MAC_STATE_BASEMAC_RX_MAC_STATE_BASE 0x00000610 tg3.h 20 bytes
23442
 MAC_TX_STATS_OCTETSMAC_TX_STATS_OCTETS 0x00000800 tg3.h 　
23443
 MAC_TX_STATS_RESV1MAC_TX_STATS_RESV1 0x00000804 tg3.h 　
23444
 MAC_TX_STATS_COLLISIONSMAC_TX_STATS_COLLISIONS 0x00000808 tg3.h 　
23445
 MAC_TX_STATS_XON_SENTMAC_TX_STATS_XON_SENT 0x0000080c tg3.h 　
23446
 MAC_TX_STATS_XOFF_SENTMAC_TX_STATS_XOFF_SENT 0x00000810 tg3.h 　
23447
 MAC_TX_STATS_RESV2MAC_TX_STATS_RESV2 0x00000814 tg3.h 　
23448
 MAC_TX_STATS_MAC_ERRORSMAC_TX_STATS_MAC_ERRORS 0x00000818 tg3.h 　
23449
 MAC_TX_STATS_SINGLE_COLLISIONSMAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c tg3.h 　
23450
 MAC_TX_STATS_MULT_COLLISIONSMAC_TX_STATS_MULT_COLLISIONS 0x00000820 tg3.h 　
23451
 MAC_TX_STATS_DEFERREDMAC_TX_STATS_DEFERRED 0x00000824 tg3.h 　
23452
 MAC_TX_STATS_RESV3MAC_TX_STATS_RESV3 0x00000828 tg3.h 　
23453
 MAC_TX_STATS_EXCESSIVE_COLMAC_TX_STATS_EXCESSIVE_COL 0x0000082c tg3.h 　
23454
 MAC_TX_STATS_LATE_COLMAC_TX_STATS_LATE_COL 0x00000830 tg3.h 　
23455
 MAC_TX_STATS_RESV4_1MAC_TX_STATS_RESV4_1 0x00000834 tg3.h 　
23456
 MAC_TX_STATS_RESV4_2MAC_TX_STATS_RESV4_2 0x00000838 tg3.h 　
23457
 MAC_TX_STATS_RESV4_3MAC_TX_STATS_RESV4_3 0x0000083c tg3.h 　
23458
 MAC_TX_STATS_RESV4_4MAC_TX_STATS_RESV4_4 0x00000840 tg3.h 　
23459
 MAC_TX_STATS_RESV4_5MAC_TX_STATS_RESV4_5 0x00000844 tg3.h 　
23460
 MAC_TX_STATS_RESV4_6MAC_TX_STATS_RESV4_6 0x00000848 tg3.h 　
23461
 MAC_TX_STATS_RESV4_7MAC_TX_STATS_RESV4_7 0x0000084c tg3.h 　
23462
 MAC_TX_STATS_RESV4_8MAC_TX_STATS_RESV4_8 0x00000850 tg3.h 　
23463
 MAC_TX_STATS_RESV4_9MAC_TX_STATS_RESV4_9 0x00000854 tg3.h 　
23464
 MAC_TX_STATS_RESV4_10MAC_TX_STATS_RESV4_10 0x00000858 tg3.h 　
23465
 MAC_TX_STATS_RESV4_11MAC_TX_STATS_RESV4_11 0x0000085c tg3.h 　
23466
 MAC_TX_STATS_RESV4_12MAC_TX_STATS_RESV4_12 0x00000860 tg3.h 　
23467
 MAC_TX_STATS_RESV4_13MAC_TX_STATS_RESV4_13 0x00000864 tg3.h 　
23468
 MAC_TX_STATS_RESV4_14MAC_TX_STATS_RESV4_14 0x00000868 tg3.h 　
23469
 MAC_TX_STATS_UCASTMAC_TX_STATS_UCAST 0x0000086c tg3.h 　
23470
 MAC_TX_STATS_MCASTMAC_TX_STATS_MCAST 0x00000870 tg3.h 　
23471
 MAC_TX_STATS_BCASTMAC_TX_STATS_BCAST 0x00000874 tg3.h 　
23472
 MAC_TX_STATS_RESV5_1MAC_TX_STATS_RESV5_1 0x00000878 tg3.h 　
23473
 MAC_TX_STATS_RESV5_2MAC_TX_STATS_RESV5_2 0x0000087c tg3.h 　
23474
 MAC_RX_STATS_OCTETSMAC_RX_STATS_OCTETS 0x00000880 tg3.h 　
23475
 MAC_RX_STATS_RESV1MAC_RX_STATS_RESV1 0x00000884 tg3.h 　
23476
 MAC_RX_STATS_FRAGMENTSMAC_RX_STATS_FRAGMENTS 0x00000888 tg3.h 　
23477
 MAC_RX_STATS_UCASTMAC_RX_STATS_UCAST 0x0000088c tg3.h 　
23478
 MAC_RX_STATS_MCASTMAC_RX_STATS_MCAST 0x00000890 tg3.h 　
23479
 MAC_RX_STATS_BCASTMAC_RX_STATS_BCAST 0x00000894 tg3.h 　
23480
 MAC_RX_STATS_FCS_ERRORSMAC_RX_STATS_FCS_ERRORS 0x00000898 tg3.h 　
23481
 MAC_RX_STATS_ALIGN_ERRORSMAC_RX_STATS_ALIGN_ERRORS 0x0000089c tg3.h 　
23482
 MAC_RX_STATS_XON_PAUSE_RECVDMAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0 tg3.h 　
23483
 MAC_RX_STATS_XOFF_PAUSE_RECVDMAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4 tg3.h 　
23484
 MAC_RX_STATS_MAC_CTRL_RECVDMAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8 tg3.h 　
23485
 MAC_RX_STATS_XOFF_ENTEREDMAC_RX_STATS_XOFF_ENTERED 0x000008ac tg3.h 　
23486
 MAC_RX_STATS_FRAME_TOO_LONGMAC_RX_STATS_FRAME_TOO_LONG 0x000008b0 tg3.h 　
23487
 MAC_RX_STATS_JABBERSMAC_RX_STATS_JABBERS 0x000008b4 tg3.h 　
23488
 MAC_RX_STATS_UNDERSIZEMAC_RX_STATS_UNDERSIZE 0x000008b8 tg3.h 　
23489
 SNDDATAI_MODESNDDATAI_MODE 0x00000c00 tg3.h 　
23490
 SNDDATAI_MODE_RESETSNDDATAI_MODE_RESET 0x00000001 tg3.h 　
23491
 SNDDATAI_MODE_ENABLESNDDATAI_MODE_ENABLE 0x00000002 tg3.h 　
23492
 SNDDATAI_MODE_STAT_OFLOW_ENABSNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004 tg3.h 　
23493
 SNDDATAI_STATUSSNDDATAI_STATUS 0x00000c04 tg3.h 　
23494
 SNDDATAI_STATUS_STAT_OFLOWSNDDATAI_STATUS_STAT_OFLOW 0x00000004 tg3.h 　
23495
 SNDDATAI_STATSCTRLSNDDATAI_STATSCTRL 0x00000c08 tg3.h 　
23496
 SNDDATAI_SCTRL_ENABLESNDDATAI_SCTRL_ENABLE 0x00000001 tg3.h 　
23497
 SNDDATAI_SCTRL_FASTUPDSNDDATAI_SCTRL_FASTUPD 0x00000002 tg3.h 　
23498
 SNDDATAI_SCTRL_CLEARSNDDATAI_SCTRL_CLEAR 0x00000004 tg3.h 　
23499
 SNDDATAI_SCTRL_FLUSHSNDDATAI_SCTRL_FLUSH 0x00000008 tg3.h 　
23500
 SNDDATAI_SCTRL_FORCE_ZEROSNDDATAI_SCTRL_FORCE_ZERO 0x00000010 tg3.h 　
23501
 SNDDATAI_STATSENABSNDDATAI_STATSENAB 0x00000c0c tg3.h 　
23502
 SNDDATAI_STATSINCMASKSNDDATAI_STATSINCMASK 0x00000c10 tg3.h 　
23503
 SNDDATAI_COS_CNT_0SNDDATAI_COS_CNT_0 0x00000c80 tg3.h 　
23504
 SNDDATAI_COS_CNT_1SNDDATAI_COS_CNT_1 0x00000c84 tg3.h 　
23505
 SNDDATAI_COS_CNT_2SNDDATAI_COS_CNT_2 0x00000c88 tg3.h 　
23506
 SNDDATAI_COS_CNT_3SNDDATAI_COS_CNT_3 0x00000c8c tg3.h 　
23507
 SNDDATAI_COS_CNT_4SNDDATAI_COS_CNT_4 0x00000c90 tg3.h 　
23508
 SNDDATAI_COS_CNT_5SNDDATAI_COS_CNT_5 0x00000c94 tg3.h 　
23509
 SNDDATAI_COS_CNT_6SNDDATAI_COS_CNT_6 0x00000c98 tg3.h 　
23510
 SNDDATAI_COS_CNT_7SNDDATAI_COS_CNT_7 0x00000c9c tg3.h 　
23511
 SNDDATAI_COS_CNT_8SNDDATAI_COS_CNT_8 0x00000ca0 tg3.h 　
23512
 SNDDATAI_COS_CNT_9SNDDATAI_COS_CNT_9 0x00000ca4 tg3.h 　
23513
 SNDDATAI_COS_CNT_10SNDDATAI_COS_CNT_10 0x00000ca8 tg3.h 　
23514
 SNDDATAI_COS_CNT_11SNDDATAI_COS_CNT_11 0x00000cac tg3.h 　
23515
 SNDDATAI_COS_CNT_12SNDDATAI_COS_CNT_12 0x00000cb0 tg3.h 　
23516
 SNDDATAI_COS_CNT_13SNDDATAI_COS_CNT_13 0x00000cb4 tg3.h 　
23517
 SNDDATAI_COS_CNT_14SNDDATAI_COS_CNT_14 0x00000cb8 tg3.h 　
23518
 SNDDATAI_COS_CNT_15SNDDATAI_COS_CNT_15 0x00000cbc tg3.h 　
23519
 SNDDATAI_DMA_RDQ_FULL_CNTSNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0 tg3.h 　
23520
 SNDDATAI_DMA_PRIO_RDQ_FULL_CNTSNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4 tg3.h 　
23521
 SNDDATAI_SDCQ_FULL_CNTSNDDATAI_SDCQ_FULL_CNT 0x00000cc8 tg3.h 　
23522
 SNDDATAI_NICRNG_SSND_PIDX_CNTSNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc tg3.h 　
23523
 SNDDATAI_STATS_UPDATED_CNTSNDDATAI_STATS_UPDATED_CNT 0x00000cd0 tg3.h 　
23524
 SNDDATAI_INTERRUPTS_CNTSNDDATAI_INTERRUPTS_CNT 0x00000cd4 tg3.h 　
23525
 SNDDATAI_AVOID_INTERRUPTS_CNTSNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8 tg3.h 　
23526
 SNDDATAI_SND_THRESH_HIT_CNTSNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc tg3.h 　
23527
 SNDDATAC_MODESNDDATAC_MODE 0x00001000 tg3.h 　
23528
 SNDDATAC_MODE_RESETSNDDATAC_MODE_RESET 0x00000001 tg3.h 　
23529
 SNDDATAC_MODE_ENABLESNDDATAC_MODE_ENABLE 0x00000002 tg3.h 　
23530
 SNDBDS_MODESNDBDS_MODE 0x00001400 tg3.h 　
23531
 SNDBDS_MODE_RESETSNDBDS_MODE_RESET 0x00000001 tg3.h 　
23532
 SNDBDS_MODE_ENABLESNDBDS_MODE_ENABLE 0x00000002 tg3.h 　
23533
 SNDBDS_MODE_ATTN_ENABLESNDBDS_MODE_ATTN_ENABLE 0x00000004 tg3.h 　
23534
 SNDBDS_STATUSSNDBDS_STATUS 0x00001404 tg3.h 　
23535
 SNDBDS_STATUS_ERROR_ATTNSNDBDS_STATUS_ERROR_ATTN 0x00000004 tg3.h 　
23536
 SNDBDS_HWDIAGSNDBDS_HWDIAG 0x00001408 tg3.h 　
23537
 SNDBDS_SEL_CON_IDX_0SNDBDS_SEL_CON_IDX_0 0x00001440 tg3.h 　
23538
 SNDBDS_SEL_CON_IDX_1SNDBDS_SEL_CON_IDX_1 0x00001444 tg3.h 　
23539
 SNDBDS_SEL_CON_IDX_2SNDBDS_SEL_CON_IDX_2 0x00001448 tg3.h 　
23540
 SNDBDS_SEL_CON_IDX_3SNDBDS_SEL_CON_IDX_3 0x0000144c tg3.h 　
23541
 SNDBDS_SEL_CON_IDX_4SNDBDS_SEL_CON_IDX_4 0x00001450 tg3.h 　
23542
 SNDBDS_SEL_CON_IDX_5SNDBDS_SEL_CON_IDX_5 0x00001454 tg3.h 　
23543
 SNDBDS_SEL_CON_IDX_6SNDBDS_SEL_CON_IDX_6 0x00001458 tg3.h 　
23544
 SNDBDS_SEL_CON_IDX_7SNDBDS_SEL_CON_IDX_7 0x0000145c tg3.h 　
23545
 SNDBDS_SEL_CON_IDX_8SNDBDS_SEL_CON_IDX_8 0x00001460 tg3.h 　
23546
 SNDBDS_SEL_CON_IDX_9SNDBDS_SEL_CON_IDX_9 0x00001464 tg3.h 　
23547
 SNDBDS_SEL_CON_IDX_10SNDBDS_SEL_CON_IDX_10 0x00001468 tg3.h 　
23548
 SNDBDS_SEL_CON_IDX_11SNDBDS_SEL_CON_IDX_11 0x0000146c tg3.h 　
23549
 SNDBDS_SEL_CON_IDX_12SNDBDS_SEL_CON_IDX_12 0x00001470 tg3.h 　
23550
 SNDBDS_SEL_CON_IDX_13SNDBDS_SEL_CON_IDX_13 0x00001474 tg3.h 　
23551
 SNDBDS_SEL_CON_IDX_14SNDBDS_SEL_CON_IDX_14 0x00001478 tg3.h 　
23552
 SNDBDS_SEL_CON_IDX_15SNDBDS_SEL_CON_IDX_15 0x0000147c tg3.h 　
23553
 SNDBDI_MODESNDBDI_MODE 0x00001800 tg3.h 　
23554
 SNDBDI_MODE_RESETSNDBDI_MODE_RESET 0x00000001 tg3.h 　
23555
 SNDBDI_MODE_ENABLESNDBDI_MODE_ENABLE 0x00000002 tg3.h 　
23556
 SNDBDI_MODE_ATTN_ENABLESNDBDI_MODE_ATTN_ENABLE 0x00000004 tg3.h 　
23557
 SNDBDI_STATUSSNDBDI_STATUS 0x00001804 tg3.h 　
23558
 SNDBDI_STATUS_ERROR_ATTNSNDBDI_STATUS_ERROR_ATTN 0x00000004 tg3.h 　
23559
 SNDBDI_IN_PROD_IDX_0SNDBDI_IN_PROD_IDX_0 0x00001808 tg3.h 　
23560
 SNDBDI_IN_PROD_IDX_1SNDBDI_IN_PROD_IDX_1 0x0000180c tg3.h 　
23561
 SNDBDI_IN_PROD_IDX_2SNDBDI_IN_PROD_IDX_2 0x00001810 tg3.h 　
23562
 SNDBDI_IN_PROD_IDX_3SNDBDI_IN_PROD_IDX_3 0x00001814 tg3.h 　
23563
 SNDBDI_IN_PROD_IDX_4SNDBDI_IN_PROD_IDX_4 0x00001818 tg3.h 　
23564
 SNDBDI_IN_PROD_IDX_5SNDBDI_IN_PROD_IDX_5 0x0000181c tg3.h 　
23565
 SNDBDI_IN_PROD_IDX_6SNDBDI_IN_PROD_IDX_6 0x00001820 tg3.h 　
23566
 SNDBDI_IN_PROD_IDX_7SNDBDI_IN_PROD_IDX_7 0x00001824 tg3.h 　
23567
 SNDBDI_IN_PROD_IDX_8SNDBDI_IN_PROD_IDX_8 0x00001828 tg3.h 　
23568
 SNDBDI_IN_PROD_IDX_9SNDBDI_IN_PROD_IDX_9 0x0000182c tg3.h 　
23569
 SNDBDI_IN_PROD_IDX_10SNDBDI_IN_PROD_IDX_10 0x00001830 tg3.h 　
23570
 SNDBDI_IN_PROD_IDX_11SNDBDI_IN_PROD_IDX_11 0x00001834 tg3.h 　
23571
 SNDBDI_IN_PROD_IDX_12SNDBDI_IN_PROD_IDX_12 0x00001838 tg3.h 　
23572
 SNDBDI_IN_PROD_IDX_13SNDBDI_IN_PROD_IDX_13 0x0000183c tg3.h 　
23573
 SNDBDI_IN_PROD_IDX_14SNDBDI_IN_PROD_IDX_14 0x00001840 tg3.h 　
23574
 SNDBDI_IN_PROD_IDX_15SNDBDI_IN_PROD_IDX_15 0x00001844 tg3.h 　
23575
 SNDBDC_MODESNDBDC_MODE 0x00001c00 tg3.h 　
23576
 SNDBDC_MODE_RESETSNDBDC_MODE_RESET 0x00000001 tg3.h 　
23577
 SNDBDC_MODE_ENABLESNDBDC_MODE_ENABLE 0x00000002 tg3.h 　
23578
 SNDBDC_MODE_ATTN_ENABLESNDBDC_MODE_ATTN_ENABLE 0x00000004 tg3.h 　
23579
 RCVLPC_MODERCVLPC_MODE 0x00002000 tg3.h 　
23580
 RCVLPC_MODE_RESETRCVLPC_MODE_RESET 0x00000001 tg3.h 　
23581
 RCVLPC_MODE_ENABLERCVLPC_MODE_ENABLE 0x00000002 tg3.h 　
23582
 RCVLPC_MODE_CLASS0_ATTN_ENABRCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004 tg3.h 　
23583
 RCVLPC_MODE_MAPOOR_AATTN_ENABRCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008 tg3.h 　
23584
 RCVLPC_MODE_STAT_OFLOW_ENABRCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010 tg3.h 　
23585
 RCVLPC_STATUSRCVLPC_STATUS 0x00002004 tg3.h 　
23586
 RCVLPC_STATUS_CLASS0RCVLPC_STATUS_CLASS0 0x00000004 tg3.h 　
23587
 RCVLPC_STATUS_MAPOORRCVLPC_STATUS_MAPOOR 0x00000008 tg3.h 　
23588
 RCVLPC_STATUS_STAT_OFLOWRCVLPC_STATUS_STAT_OFLOW 0x00000010 tg3.h 　
23589
 RCVLPC_LOCKRCVLPC_LOCK 0x00002008 tg3.h 　
23590
 RCVLPC_LOCK_REQ_MASKRCVLPC_LOCK_REQ_MASK 0x0000ffff tg3.h 　
23591
 RCVLPC_LOCK_REQ_SHIFTRCVLPC_LOCK_REQ_SHIFT 0 tg3.h 　
23592
 RCVLPC_LOCK_GRANT_MASKRCVLPC_LOCK_GRANT_MASK 0xffff0000 tg3.h 　
23593
 RCVLPC_LOCK_GRANT_SHIFTRCVLPC_LOCK_GRANT_SHIFT 16 tg3.h 　
23594
 RCVLPC_NON_EMPTY_BITSRCVLPC_NON_EMPTY_BITS 0x0000200c tg3.h 　
23595
 RCVLPC_NON_EMPTY_BITS_MASKRCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff tg3.h 　
23596
 RCVLPC_CONFIGRCVLPC_CONFIG 0x00002010 tg3.h 　
23597
 RCVLPC_STATSCTRLRCVLPC_STATSCTRL 0x00002014 tg3.h 　
23598
 RCVLPC_STATSCTRL_ENABLERCVLPC_STATSCTRL_ENABLE 0x00000001 tg3.h 　
23599
 RCVLPC_STATSCTRL_FASTUPDRCVLPC_STATSCTRL_FASTUPD 0x00000002 tg3.h 　
23600
 RCVLPC_STATS_ENABLERCVLPC_STATS_ENABLE 0x00002018 tg3.h 　
23601
 RCVLPC_STATSENAB_LNGBRST_RFIXRCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 tg3.h 　
23602
 RCVLPC_STATS_INCMASKRCVLPC_STATS_INCMASK 0x0000201c tg3.h 　
23603
 RCVLPC_SELLST_BASERCVLPC_SELLST_BASE 0x00002100 tg3.h 16 16-byte entries
23604
 SELLST_TAILSELLST_TAIL 0x00000004 tg3.h 　
23605
 SELLST_CONTSELLST_CONT 0x00000008 tg3.h 　
23606
 SELLST_UNUSEDSELLST_UNUSED 0x0000000c tg3.h 　
23607
 RCVLPC_COS_CNTL_BASERCVLPC_COS_CNTL_BASE 0x00002200 tg3.h 16 4-byte entries
23608
 RCVLPC_DROP_FILTER_CNTRCVLPC_DROP_FILTER_CNT 0x00002240 tg3.h 　
23609
 RCVLPC_DMA_WQ_FULL_CNTRCVLPC_DMA_WQ_FULL_CNT 0x00002244 tg3.h 　
23610
 RCVLPC_DMA_HIPRIO_WQ_FULL_CNTRCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248 tg3.h 　
23611
 RCVLPC_NO_RCV_BD_CNTRCVLPC_NO_RCV_BD_CNT 0x0000224c tg3.h 　
23612
 RCVLPC_IN_DISCARDS_CNTRCVLPC_IN_DISCARDS_CNT 0x00002250 tg3.h 　
23613
 RCVLPC_IN_ERRORS_CNTRCVLPC_IN_ERRORS_CNT 0x00002254 tg3.h 　
23614
 RCVLPC_RCV_THRESH_HIT_CNTRCVLPC_RCV_THRESH_HIT_CNT 0x00002258 tg3.h 　
23615
 RCVDBDI_MODERCVDBDI_MODE 0x00002400 tg3.h 　
23616
 RCVDBDI_MODE_RESETRCVDBDI_MODE_RESET 0x00000001 tg3.h 　
23617
 RCVDBDI_MODE_ENABLERCVDBDI_MODE_ENABLE 0x00000002 tg3.h 　
23618
 RCVDBDI_MODE_JUMBOBD_NEEDEDRCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004 tg3.h 　
23619
 RCVDBDI_MODE_FRM_TOO_BIGRCVDBDI_MODE_FRM_TOO_BIG 0x00000008 tg3.h 　
23620
 RCVDBDI_MODE_INV_RING_SZRCVDBDI_MODE_INV_RING_SZ 0x00000010 tg3.h 　
23621
 RCVDBDI_STATUSRCVDBDI_STATUS 0x00002404 tg3.h 　
23622
 RCVDBDI_STATUS_JUMBOBD_NEEDEDRCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004 tg3.h 　
23623
 RCVDBDI_STATUS_FRM_TOO_BIGRCVDBDI_STATUS_FRM_TOO_BIG 0x00000008 tg3.h 　
23624
 RCVDBDI_STATUS_INV_RING_SZRCVDBDI_STATUS_INV_RING_SZ 0x00000010 tg3.h 　
23625
 RCVDBDI_SPLIT_FRAME_MINSZRCVDBDI_SPLIT_FRAME_MINSZ 0x00002408 tg3.h 　
23626
 RCVDBDI_JUMBO_BDRCVDBDI_JUMBO_BD 0x00002440 tg3.h TG3_BDINFO_...
23627
 RCVDBDI_STD_BDRCVDBDI_STD_BD 0x00002450 tg3.h TG3_BDINFO_...
23628
 RCVDBDI_MINI_BDRCVDBDI_MINI_BD 0x00002460 tg3.h TG3_BDINFO_...
23629
 RCVDBDI_JUMBO_CON_IDXRCVDBDI_JUMBO_CON_IDX 0x00002470 tg3.h 　
23630
 RCVDBDI_STD_CON_IDXRCVDBDI_STD_CON_IDX 0x00002474 tg3.h 　
23631
 RCVDBDI_MINI_CON_IDXRCVDBDI_MINI_CON_IDX 0x00002478 tg3.h 　
23632
 RCVDBDI_BD_PROD_IDX_0RCVDBDI_BD_PROD_IDX_0 0x00002480 tg3.h 　
23633
 RCVDBDI_BD_PROD_IDX_1RCVDBDI_BD_PROD_IDX_1 0x00002484 tg3.h 　
23634
 RCVDBDI_BD_PROD_IDX_2RCVDBDI_BD_PROD_IDX_2 0x00002488 tg3.h 　
23635
 RCVDBDI_BD_PROD_IDX_3RCVDBDI_BD_PROD_IDX_3 0x0000248c tg3.h 　
23636
 RCVDBDI_BD_PROD_IDX_4RCVDBDI_BD_PROD_IDX_4 0x00002490 tg3.h 　
23637
 RCVDBDI_BD_PROD_IDX_5RCVDBDI_BD_PROD_IDX_5 0x00002494 tg3.h 　
23638
 RCVDBDI_BD_PROD_IDX_6RCVDBDI_BD_PROD_IDX_6 0x00002498 tg3.h 　
23639
 RCVDBDI_BD_PROD_IDX_7RCVDBDI_BD_PROD_IDX_7 0x0000249c tg3.h 　
23640
 RCVDBDI_BD_PROD_IDX_8RCVDBDI_BD_PROD_IDX_8 0x000024a0 tg3.h 　
23641
 RCVDBDI_BD_PROD_IDX_9RCVDBDI_BD_PROD_IDX_9 0x000024a4 tg3.h 　
23642
 RCVDBDI_BD_PROD_IDX_10RCVDBDI_BD_PROD_IDX_10 0x000024a8 tg3.h 　
23643
 RCVDBDI_BD_PROD_IDX_11RCVDBDI_BD_PROD_IDX_11 0x000024ac tg3.h 　
23644
 RCVDBDI_BD_PROD_IDX_12RCVDBDI_BD_PROD_IDX_12 0x000024b0 tg3.h 　
23645
 RCVDBDI_BD_PROD_IDX_13RCVDBDI_BD_PROD_IDX_13 0x000024b4 tg3.h 　
23646
 RCVDBDI_BD_PROD_IDX_14RCVDBDI_BD_PROD_IDX_14 0x000024b8 tg3.h 　
23647
 RCVDBDI_BD_PROD_IDX_15RCVDBDI_BD_PROD_IDX_15 0x000024bc tg3.h 　
23648
 RCVDBDI_HWDIAGRCVDBDI_HWDIAG 0x000024c0 tg3.h 　
23649
 RCVDCC_MODERCVDCC_MODE 0x00002800 tg3.h 　
23650
 RCVDCC_MODE_RESETRCVDCC_MODE_RESET 0x00000001 tg3.h 　
23651
 RCVDCC_MODE_ENABLERCVDCC_MODE_ENABLE 0x00000002 tg3.h 　
23652
 RCVDCC_MODE_ATTN_ENABLERCVDCC_MODE_ATTN_ENABLE 0x00000004 tg3.h 　
23653
 RCVBDI_MODERCVBDI_MODE 0x00002c00 tg3.h 　
23654
 RCVBDI_MODE_RESETRCVBDI_MODE_RESET 0x00000001 tg3.h 　
23655
 RCVBDI_MODE_ENABLERCVBDI_MODE_ENABLE 0x00000002 tg3.h 　
23656
 RCVBDI_MODE_RCB_ATTN_ENABRCVBDI_MODE_RCB_ATTN_ENAB 0x00000004 tg3.h 　
23657
 RCVBDI_STATUSRCVBDI_STATUS 0x00002c04 tg3.h 　
23658
 RCVBDI_STATUS_RCB_ATTNRCVBDI_STATUS_RCB_ATTN 0x00000004 tg3.h 　
23659
 RCVBDI_JUMBO_PROD_IDXRCVBDI_JUMBO_PROD_IDX 0x00002c08 tg3.h 　
23660
 RCVBDI_STD_PROD_IDXRCVBDI_STD_PROD_IDX 0x00002c0c tg3.h 　
23661
 RCVBDI_MINI_PROD_IDXRCVBDI_MINI_PROD_IDX 0x00002c10 tg3.h 　
23662
 RCVBDI_MINI_THRESHRCVBDI_MINI_THRESH 0x00002c14 tg3.h 　
23663
 RCVBDI_STD_THRESHRCVBDI_STD_THRESH 0x00002c18 tg3.h 　
23664
 RCVBDI_JUMBO_THRESHRCVBDI_JUMBO_THRESH 0x00002c1c tg3.h 　
23665
 RCVCC_MODERCVCC_MODE 0x00003000 tg3.h 　
23666
 RCVCC_MODE_RESETRCVCC_MODE_RESET 0x00000001 tg3.h 　
23667
 RCVCC_MODE_ENABLERCVCC_MODE_ENABLE 0x00000002 tg3.h 　
23668
 RCVCC_MODE_ATTN_ENABLERCVCC_MODE_ATTN_ENABLE 0x00000004 tg3.h 　
23669
 RCVCC_STATUSRCVCC_STATUS 0x00003004 tg3.h 　
23670
 RCVCC_STATUS_ERROR_ATTNRCVCC_STATUS_ERROR_ATTN 0x00000004 tg3.h 　
23671
 RCVCC_JUMP_PROD_IDXRCVCC_JUMP_PROD_IDX 0x00003008 tg3.h 　
23672
 RCVCC_STD_PROD_IDXRCVCC_STD_PROD_IDX 0x0000300c tg3.h 　
23673
 RCVCC_MINI_PROD_IDXRCVCC_MINI_PROD_IDX 0x00003010 tg3.h 　
23674
 RCVLSC_MODERCVLSC_MODE 0x00003400 tg3.h 　
23675
 RCVLSC_MODE_RESETRCVLSC_MODE_RESET 0x00000001 tg3.h 　
23676
 RCVLSC_MODE_ENABLERCVLSC_MODE_ENABLE 0x00000002 tg3.h 　
23677
 RCVLSC_MODE_ATTN_ENABLERCVLSC_MODE_ATTN_ENABLE 0x00000004 tg3.h 　
23678
 RCVLSC_STATUSRCVLSC_STATUS 0x00003404 tg3.h 　
23679
 RCVLSC_STATUS_ERROR_ATTNRCVLSC_STATUS_ERROR_ATTN 0x00000004 tg3.h 　
23680
 MBFREE_MODEMBFREE_MODE 0x00003800 tg3.h 　
23681
 MBFREE_MODE_RESETMBFREE_MODE_RESET 0x00000001 tg3.h 　
23682
 MBFREE_MODE_ENABLEMBFREE_MODE_ENABLE 0x00000002 tg3.h 　
23683
 MBFREE_STATUSMBFREE_STATUS 0x00003804 tg3.h 　
23684
 HOSTCC_MODEHOSTCC_MODE 0x00003c00 tg3.h 　
23685
 HOSTCC_MODE_RESETHOSTCC_MODE_RESET 0x00000001 tg3.h 　
23686
 HOSTCC_MODE_ENABLEHOSTCC_MODE_ENABLE 0x00000002 tg3.h 　
23687
 HOSTCC_MODE_ATTNHOSTCC_MODE_ATTN 0x00000004 tg3.h 　
23688
 HOSTCC_MODE_NOWHOSTCC_MODE_NOW 0x00000008 tg3.h 　
23689
 HOSTCC_MODE_FULL_STATUSHOSTCC_MODE_FULL_STATUS 0x00000000 tg3.h 　
23690
 HOSTCC_MODE_64BYTEHOSTCC_MODE_64BYTE 0x00000080 tg3.h 　
23691
 HOSTCC_MODE_32BYTEHOSTCC_MODE_32BYTE 0x00000100 tg3.h 　
23692
 HOSTCC_MODE_CLRTICK_RXBDHOSTCC_MODE_CLRTICK_RXBD 0x00000200 tg3.h 　
23693
 HOSTCC_MODE_CLRTICK_TXBDHOSTCC_MODE_CLRTICK_TXBD 0x00000400 tg3.h 　
23694
 HOSTCC_MODE_NOINT_ON_NOWHOSTCC_MODE_NOINT_ON_NOW 0x00000800 tg3.h 　
23695
 HOSTCC_MODE_NOINT_ON_FORCEHOSTCC_MODE_NOINT_ON_FORCE 0x00001000 tg3.h 　
23696
 HOSTCC_STATUSHOSTCC_STATUS 0x00003c04 tg3.h 　
23697
 HOSTCC_STATUS_ERROR_ATTNHOSTCC_STATUS_ERROR_ATTN 0x00000004 tg3.h 　
23698
 HOSTCC_RXCOL_TICKSHOSTCC_RXCOL_TICKS 0x00003c08 tg3.h 　
23699
 LOW_RXCOL_TICKSLOW_RXCOL_TICKS 0x00000032 tg3.h 　
23700
 DEFAULT_RXCOL_TICKSDEFAULT_RXCOL_TICKS 0x00000048 tg3.h 　
23701
 HIGH_RXCOL_TICKSHIGH_RXCOL_TICKS 0x00000096 tg3.h 　
23702
 HOSTCC_TXCOL_TICKSHOSTCC_TXCOL_TICKS 0x00003c0c tg3.h 　
23703
 LOW_TXCOL_TICKSLOW_TXCOL_TICKS 0x00000096 tg3.h 　
23704
 DEFAULT_TXCOL_TICKSDEFAULT_TXCOL_TICKS 0x0000012c tg3.h 　
23705
 HIGH_TXCOL_TICKSHIGH_TXCOL_TICKS 0x00000145 tg3.h 　
23706
 HOSTCC_RXMAX_FRAMESHOSTCC_RXMAX_FRAMES 0x00003c10 tg3.h 　
23707
 LOW_RXMAX_FRAMESLOW_RXMAX_FRAMES 0x00000005 tg3.h 　
23708
 DEFAULT_RXMAX_FRAMESDEFAULT_RXMAX_FRAMES 0x00000008 tg3.h 　
23709
 HIGH_RXMAX_FRAMESHIGH_RXMAX_FRAMES 0x00000012 tg3.h 　
23710
 HOSTCC_TXMAX_FRAMESHOSTCC_TXMAX_FRAMES 0x00003c14 tg3.h 　
23711
 LOW_TXMAX_FRAMESLOW_TXMAX_FRAMES 0x00000035 tg3.h 　
23712
 DEFAULT_TXMAX_FRAMESDEFAULT_TXMAX_FRAMES 0x0000004b tg3.h 　
23713
 HIGH_TXMAX_FRAMESHIGH_TXMAX_FRAMES 0x00000052 tg3.h 　
23714
 HOSTCC_RXCOAL_TICK_INTHOSTCC_RXCOAL_TICK_INT 0x00003c18 tg3.h 　
23715
 DEFAULT_RXCOAL_TICK_INTDEFAULT_RXCOAL_TICK_INT 0x00000019 tg3.h 　
23716
 HOSTCC_TXCOAL_TICK_INTHOSTCC_TXCOAL_TICK_INT 0x00003c1c tg3.h 　
23717
 DEFAULT_TXCOAL_TICK_INTDEFAULT_TXCOAL_TICK_INT 0x00000019 tg3.h 　
23718
 HOSTCC_RXCOAL_MAXF_INTHOSTCC_RXCOAL_MAXF_INT 0x00003c20 tg3.h 　
23719
 DEFAULT_RXCOAL_MAXF_INTDEFAULT_RXCOAL_MAXF_INT 0x00000005 tg3.h 　
23720
 HOSTCC_TXCOAL_MAXF_INTHOSTCC_TXCOAL_MAXF_INT 0x00003c24 tg3.h 　
23721
 DEFAULT_TXCOAL_MAXF_INTDEFAULT_TXCOAL_MAXF_INT 0x00000005 tg3.h 　
23722
 HOSTCC_STAT_COAL_TICKSHOSTCC_STAT_COAL_TICKS 0x00003c28 tg3.h 　
23723
 DEFAULT_STAT_COAL_TICKSDEFAULT_STAT_COAL_TICKS 0x000f4240 tg3.h 　
23724
 HOSTCC_STATS_BLK_HOST_ADDRHOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 tg3.h 64-bit
23725
 HOSTCC_STATUS_BLK_HOST_ADDRHOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 tg3.h 64-bit
23726
 HOSTCC_STATS_BLK_NIC_ADDRHOSTCC_STATS_BLK_NIC_ADDR 0x00003c40 tg3.h 　
23727
 HOSTCC_STATUS_BLK_NIC_ADDRHOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44 tg3.h 　
23728
 HOSTCC_FLOW_ATTNHOSTCC_FLOW_ATTN 0x00003c48 tg3.h 　
23729
 HOSTCC_JUMBO_CON_IDXHOSTCC_JUMBO_CON_IDX 0x00003c50 tg3.h 　
23730
 HOSTCC_STD_CON_IDXHOSTCC_STD_CON_IDX 0x00003c54 tg3.h 　
23731
 HOSTCC_MINI_CON_IDXHOSTCC_MINI_CON_IDX 0x00003c58 tg3.h 　
23732
 HOSTCC_RET_PROD_IDX_0HOSTCC_RET_PROD_IDX_0 0x00003c80 tg3.h 　
23733
 HOSTCC_RET_PROD_IDX_1HOSTCC_RET_PROD_IDX_1 0x00003c84 tg3.h 　
23734
 HOSTCC_RET_PROD_IDX_2HOSTCC_RET_PROD_IDX_2 0x00003c88 tg3.h 　
23735
 HOSTCC_RET_PROD_IDX_3HOSTCC_RET_PROD_IDX_3 0x00003c8c tg3.h 　
23736
 HOSTCC_RET_PROD_IDX_4HOSTCC_RET_PROD_IDX_4 0x00003c90 tg3.h 　
23737
 HOSTCC_RET_PROD_IDX_5HOSTCC_RET_PROD_IDX_5 0x00003c94 tg3.h 　
23738
 HOSTCC_RET_PROD_IDX_6HOSTCC_RET_PROD_IDX_6 0x00003c98 tg3.h 　
23739
 HOSTCC_RET_PROD_IDX_7HOSTCC_RET_PROD_IDX_7 0x00003c9c tg3.h 　
23740
 HOSTCC_RET_PROD_IDX_8HOSTCC_RET_PROD_IDX_8 0x00003ca0 tg3.h 　
23741
 HOSTCC_RET_PROD_IDX_9HOSTCC_RET_PROD_IDX_9 0x00003ca4 tg3.h 　
23742
 HOSTCC_RET_PROD_IDX_10HOSTCC_RET_PROD_IDX_10 0x00003ca8 tg3.h 　
23743
 HOSTCC_RET_PROD_IDX_11HOSTCC_RET_PROD_IDX_11 0x00003cac tg3.h 　
23744
 HOSTCC_RET_PROD_IDX_12HOSTCC_RET_PROD_IDX_12 0x00003cb0 tg3.h 　
23745
 HOSTCC_RET_PROD_IDX_13HOSTCC_RET_PROD_IDX_13 0x00003cb4 tg3.h 　
23746
 HOSTCC_RET_PROD_IDX_14HOSTCC_RET_PROD_IDX_14 0x00003cb8 tg3.h 　
23747
 HOSTCC_RET_PROD_IDX_15HOSTCC_RET_PROD_IDX_15 0x00003cbc tg3.h 　
23748
 HOSTCC_SND_CON_IDX_0HOSTCC_SND_CON_IDX_0 0x00003cc0 tg3.h 　
23749
 HOSTCC_SND_CON_IDX_1HOSTCC_SND_CON_IDX_1 0x00003cc4 tg3.h 　
23750
 HOSTCC_SND_CON_IDX_2HOSTCC_SND_CON_IDX_2 0x00003cc8 tg3.h 　
23751
 HOSTCC_SND_CON_IDX_3HOSTCC_SND_CON_IDX_3 0x00003ccc tg3.h 　
23752
 HOSTCC_SND_CON_IDX_4HOSTCC_SND_CON_IDX_4 0x00003cd0 tg3.h 　
23753
 HOSTCC_SND_CON_IDX_5HOSTCC_SND_CON_IDX_5 0x00003cd4 tg3.h 　
23754
 HOSTCC_SND_CON_IDX_6HOSTCC_SND_CON_IDX_6 0x00003cd8 tg3.h 　
23755
 HOSTCC_SND_CON_IDX_7HOSTCC_SND_CON_IDX_7 0x00003cdc tg3.h 　
23756
 HOSTCC_SND_CON_IDX_8HOSTCC_SND_CON_IDX_8 0x00003ce0 tg3.h 　
23757
 HOSTCC_SND_CON_IDX_9HOSTCC_SND_CON_IDX_9 0x00003ce4 tg3.h 　
23758
 HOSTCC_SND_CON_IDX_10HOSTCC_SND_CON_IDX_10 0x00003ce8 tg3.h 　
23759
 HOSTCC_SND_CON_IDX_11HOSTCC_SND_CON_IDX_11 0x00003cec tg3.h 　
23760
 HOSTCC_SND_CON_IDX_12HOSTCC_SND_CON_IDX_12 0x00003cf0 tg3.h 　
23761
 HOSTCC_SND_CON_IDX_13HOSTCC_SND_CON_IDX_13 0x00003cf4 tg3.h 　
23762
 HOSTCC_SND_CON_IDX_14HOSTCC_SND_CON_IDX_14 0x00003cf8 tg3.h 　
23763
 HOSTCC_SND_CON_IDX_15HOSTCC_SND_CON_IDX_15 0x00003cfc tg3.h 　
23764
 MEMARB_MODEMEMARB_MODE 0x00004000 tg3.h 　
23765
 MEMARB_MODE_RESETMEMARB_MODE_RESET 0x00000001 tg3.h 　
23766
 MEMARB_MODE_ENABLEMEMARB_MODE_ENABLE 0x00000002 tg3.h 　
23767
 MEMARB_STATUSMEMARB_STATUS 0x00004004 tg3.h 　
23768
 MEMARB_TRAP_ADDR_LOWMEMARB_TRAP_ADDR_LOW 0x00004008 tg3.h 　
23769
 MEMARB_TRAP_ADDR_HIGHMEMARB_TRAP_ADDR_HIGH 0x0000400c tg3.h 　
23770
 BUFMGR_MODEBUFMGR_MODE 0x00004400 tg3.h 　
23771
 BUFMGR_MODE_RESETBUFMGR_MODE_RESET 0x00000001 tg3.h 　
23772
 BUFMGR_MODE_ENABLEBUFMGR_MODE_ENABLE 0x00000002 tg3.h 　
23773
 BUFMGR_MODE_ATTN_ENABLEBUFMGR_MODE_ATTN_ENABLE 0x00000004 tg3.h 　
23774
 BUFMGR_MODE_BM_TESTBUFMGR_MODE_BM_TEST 0x00000008 tg3.h 　
23775
 BUFMGR_MODE_MBLOW_ATTN_ENABBUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010 tg3.h 　
23776
 BUFMGR_STATUSBUFMGR_STATUS 0x00004404 tg3.h 　
23777
 BUFMGR_STATUS_ERRORBUFMGR_STATUS_ERROR 0x00000004 tg3.h 　
23778
 BUFMGR_STATUS_MBLOWBUFMGR_STATUS_MBLOW 0x00000010 tg3.h 　
23779
 BUFMGR_MB_POOL_ADDRBUFMGR_MB_POOL_ADDR 0x00004408 tg3.h 　
23780
 BUFMGR_MB_POOL_SIZEBUFMGR_MB_POOL_SIZE 0x0000440c tg3.h 　
23781
 BUFMGR_MB_RDMA_LOW_WATERBUFMGR_MB_RDMA_LOW_WATER 0x00004410 tg3.h 　
23782
 DEFAULT_MB_RDMA_LOW_WATERDEFAULT_MB_RDMA_LOW_WATER 0x00000050 tg3.h 　
23783
 DEFAULT_MB_RDMA_LOW_WATER_5705DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000 tg3.h 　
23784
 DEFAULT_MB_RDMA_LOW_WATER_JUMBODEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130 tg3.h 　
23785
 BUFMGR_MB_MACRX_LOW_WATERBUFMGR_MB_MACRX_LOW_WATER 0x00004414 tg3.h 　
23786
 DEFAULT_MB_MACRX_LOW_WATERDEFAULT_MB_MACRX_LOW_WATER 0x00000020 tg3.h 　
23787
 DEFAULT_MB_MACRX_LOW_WATER_5705DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010 tg3.h 　
23788
 DEFAULT_MB_MACRX_LOW_WATER_JUMBDEFAULT_MB_MACRX_LOW_WATER_JUMB 0x00000098 tg3.h 　
23789
 BUFMGR_MB_HIGH_WATERBUFMGR_MB_HIGH_WATER 0x00004418 tg3.h 　
23790
 DEFAULT_MB_HIGH_WATERDEFAULT_MB_HIGH_WATER 0x00000060 tg3.h 　
23791
 DEFAULT_MB_HIGH_WATER_5705DEFAULT_MB_HIGH_WATER_5705 0x00000060 tg3.h 　
23792
 DEFAULT_MB_HIGH_WATER_JUMBODEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c tg3.h 　
23793
 BUFMGR_RX_MB_ALLOC_REQBUFMGR_RX_MB_ALLOC_REQ 0x0000441c tg3.h 　
23794
 BUFMGR_MB_ALLOC_BITBUFMGR_MB_ALLOC_BIT 0x10000000 tg3.h 　
23795
 BUFMGR_RX_MB_ALLOC_RESPBUFMGR_RX_MB_ALLOC_RESP 0x00004420 tg3.h 　
23796
 BUFMGR_TX_MB_ALLOC_REQBUFMGR_TX_MB_ALLOC_REQ 0x00004424 tg3.h 　
23797
 BUFMGR_TX_MB_ALLOC_RESPBUFMGR_TX_MB_ALLOC_RESP 0x00004428 tg3.h 　
23798
 BUFMGR_DMA_DESC_POOL_ADDRBUFMGR_DMA_DESC_POOL_ADDR 0x0000442c tg3.h 　
23799
 BUFMGR_DMA_DESC_POOL_SIZEBUFMGR_DMA_DESC_POOL_SIZE 0x00004430 tg3.h 　
23800
 BUFMGR_DMA_LOW_WATERBUFMGR_DMA_LOW_WATER 0x00004434 tg3.h 　
23801
 DEFAULT_DMA_LOW_WATERDEFAULT_DMA_LOW_WATER 0x00000005 tg3.h 　
23802
 BUFMGR_DMA_HIGH_WATERBUFMGR_DMA_HIGH_WATER 0x00004438 tg3.h 　
23803
 DEFAULT_DMA_HIGH_WATERDEFAULT_DMA_HIGH_WATER 0x0000000a tg3.h 　
23804
 BUFMGR_RX_DMA_ALLOC_REQBUFMGR_RX_DMA_ALLOC_REQ 0x0000443c tg3.h 　
23805
 BUFMGR_RX_DMA_ALLOC_RESPBUFMGR_RX_DMA_ALLOC_RESP 0x00004440 tg3.h 　
23806
 BUFMGR_TX_DMA_ALLOC_REQBUFMGR_TX_DMA_ALLOC_REQ 0x00004444 tg3.h 　
23807
 BUFMGR_TX_DMA_ALLOC_RESPBUFMGR_TX_DMA_ALLOC_RESP 0x00004448 tg3.h 　
23808
 BUFMGR_HWDIAG_0BUFMGR_HWDIAG_0 0x0000444c tg3.h 　
23809
 BUFMGR_HWDIAG_1BUFMGR_HWDIAG_1 0x00004450 tg3.h 　
23810
 BUFMGR_HWDIAG_2BUFMGR_HWDIAG_2 0x00004454 tg3.h 　
23811
 RDMAC_MODERDMAC_MODE 0x00004800 tg3.h 　
23812
 RDMAC_MODE_RESETRDMAC_MODE_RESET 0x00000001 tg3.h 　
23813
 RDMAC_MODE_ENABLERDMAC_MODE_ENABLE 0x00000002 tg3.h 　
23814
 RDMAC_MODE_TGTABORT_ENABRDMAC_MODE_TGTABORT_ENAB 0x00000004 tg3.h 　
23815
 RDMAC_MODE_MSTABORT_ENABRDMAC_MODE_MSTABORT_ENAB 0x00000008 tg3.h 　
23816
 RDMAC_MODE_PARITYERR_ENABRDMAC_MODE_PARITYERR_ENAB 0x00000010 tg3.h 　
23817
 RDMAC_MODE_ADDROFLOW_ENABRDMAC_MODE_ADDROFLOW_ENAB 0x00000020 tg3.h 　
23818
 RDMAC_MODE_FIFOOFLOW_ENABRDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 tg3.h 　
23819
 RDMAC_MODE_FIFOURUN_ENABRDMAC_MODE_FIFOURUN_ENAB 0x00000080 tg3.h 　
23820
 RDMAC_MODE_FIFOOREAD_ENABRDMAC_MODE_FIFOOREAD_ENAB 0x00000100 tg3.h 　
23821
 RDMAC_MODE_LNGREAD_ENABRDMAC_MODE_LNGREAD_ENAB 0x00000200 tg3.h 　
23822
 RDMAC_MODE_SPLIT_ENABLERDMAC_MODE_SPLIT_ENABLE 0x00000800 tg3.h 　
23823
 RDMAC_MODE_SPLIT_RESETRDMAC_MODE_SPLIT_RESET 0x00001000 tg3.h 　
23824
 RDMAC_MODE_FIFO_SIZE_128RDMAC_MODE_FIFO_SIZE_128 0x00020000 tg3.h 　
23825
 RDMAC_MODE_FIFO_LONG_BURSTRDMAC_MODE_FIFO_LONG_BURST 0x00030000 tg3.h 　
23826
 RDMAC_STATUSRDMAC_STATUS 0x00004804 tg3.h 　
23827
 RDMAC_STATUS_TGTABORTRDMAC_STATUS_TGTABORT 0x00000004 tg3.h 　
23828
 RDMAC_STATUS_MSTABORTRDMAC_STATUS_MSTABORT 0x00000008 tg3.h 　
23829
 RDMAC_STATUS_PARITYERRRDMAC_STATUS_PARITYERR 0x00000010 tg3.h 　
23830
 RDMAC_STATUS_ADDROFLOWRDMAC_STATUS_ADDROFLOW 0x00000020 tg3.h 　
23831
 RDMAC_STATUS_FIFOOFLOWRDMAC_STATUS_FIFOOFLOW 0x00000040 tg3.h 　
23832
 RDMAC_STATUS_FIFOURUNRDMAC_STATUS_FIFOURUN 0x00000080 tg3.h 　
23833
 RDMAC_STATUS_FIFOOREADRDMAC_STATUS_FIFOOREAD 0x00000100 tg3.h 　
23834
 RDMAC_STATUS_LNGREADRDMAC_STATUS_LNGREAD 0x00000200 tg3.h 　
23835
 WDMAC_MODEWDMAC_MODE 0x00004c00 tg3.h 　
23836
 WDMAC_MODE_RESETWDMAC_MODE_RESET 0x00000001 tg3.h 　
23837
 WDMAC_MODE_ENABLEWDMAC_MODE_ENABLE 0x00000002 tg3.h 　
23838
 WDMAC_MODE_TGTABORT_ENABWDMAC_MODE_TGTABORT_ENAB 0x00000004 tg3.h 　
23839
 WDMAC_MODE_MSTABORT_ENABWDMAC_MODE_MSTABORT_ENAB 0x00000008 tg3.h 　
23840
 WDMAC_MODE_PARITYERR_ENABWDMAC_MODE_PARITYERR_ENAB 0x00000010 tg3.h 　
23841
 WDMAC_MODE_ADDROFLOW_ENABWDMAC_MODE_ADDROFLOW_ENAB 0x00000020 tg3.h 　
23842
 WDMAC_MODE_FIFOOFLOW_ENABWDMAC_MODE_FIFOOFLOW_ENAB 0x00000040 tg3.h 　
23843
 WDMAC_MODE_FIFOURUN_ENABWDMAC_MODE_FIFOURUN_ENAB 0x00000080 tg3.h 　
23844
 WDMAC_MODE_FIFOOREAD_ENABWDMAC_MODE_FIFOOREAD_ENAB 0x00000100 tg3.h 　
23845
 WDMAC_MODE_LNGREAD_ENABWDMAC_MODE_LNGREAD_ENAB 0x00000200 tg3.h 　
23846
 WDMAC_MODE_RX_ACCELWDMAC_MODE_RX_ACCEL 0x00000400 tg3.h 　
23847
 WDMAC_STATUSWDMAC_STATUS 0x00004c04 tg3.h 　
23848
 WDMAC_STATUS_TGTABORTWDMAC_STATUS_TGTABORT 0x00000004 tg3.h 　
23849
 WDMAC_STATUS_MSTABORTWDMAC_STATUS_MSTABORT 0x00000008 tg3.h 　
23850
 WDMAC_STATUS_PARITYERRWDMAC_STATUS_PARITYERR 0x00000010 tg3.h 　
23851
 WDMAC_STATUS_ADDROFLOWWDMAC_STATUS_ADDROFLOW 0x00000020 tg3.h 　
23852
 WDMAC_STATUS_FIFOOFLOWWDMAC_STATUS_FIFOOFLOW 0x00000040 tg3.h 　
23853
 WDMAC_STATUS_FIFOURUNWDMAC_STATUS_FIFOURUN 0x00000080 tg3.h 　
23854
 WDMAC_STATUS_FIFOOREADWDMAC_STATUS_FIFOOREAD 0x00000100 tg3.h 　
23855
 WDMAC_STATUS_LNGREADWDMAC_STATUS_LNGREAD 0x00000200 tg3.h 　
23856
 CPU_MODECPU_MODE 0x00000000 tg3.h 　
23857
 CPU_MODE_RESETCPU_MODE_RESET 0x00000001 tg3.h 　
23858
 CPU_MODE_HALTCPU_MODE_HALT 0x00000400 tg3.h 　
23859
 CPU_STATECPU_STATE 0x00000004 tg3.h 　
23860
 CPU_EVTMASKCPU_EVTMASK 0x00000008 tg3.h 　
23861
 CPU_PCCPU_PC 0x0000001c tg3.h 　
23862
 CPU_INSNCPU_INSN 0x00000020 tg3.h 　
23863
 CPU_SPAD_UFLOWCPU_SPAD_UFLOW 0x00000024 tg3.h 　
23864
 CPU_WDOG_CLEARCPU_WDOG_CLEAR 0x00000028 tg3.h 　
23865
 CPU_WDOG_VECTORCPU_WDOG_VECTOR 0x0000002c tg3.h 　
23866
 CPU_WDOG_PCCPU_WDOG_PC 0x00000030 tg3.h 　
23867
 CPU_HW_BPCPU_HW_BP 0x00000034 tg3.h 　
23868
 CPU_WDOG_SAVED_STATECPU_WDOG_SAVED_STATE 0x00000044 tg3.h 　
23869
 CPU_LAST_BRANCH_ADDRCPU_LAST_BRANCH_ADDR 0x00000048 tg3.h 　
23870
 CPU_SPAD_UFLOW_SETCPU_SPAD_UFLOW_SET 0x0000004c tg3.h 　
23871
 CPU_R0CPU_R0 0x00000200 tg3.h 　
23872
 CPU_R1CPU_R1 0x00000204 tg3.h 　
23873
 CPU_R2CPU_R2 0x00000208 tg3.h 　
23874
 CPU_R3CPU_R3 0x0000020c tg3.h 　
23875
 CPU_R4CPU_R4 0x00000210 tg3.h 　
23876
 CPU_R5CPU_R5 0x00000214 tg3.h 　
23877
 CPU_R6CPU_R6 0x00000218 tg3.h 　
23878
 CPU_R7CPU_R7 0x0000021c tg3.h 　
23879
 CPU_R8CPU_R8 0x00000220 tg3.h 　
23880
 CPU_R9CPU_R9 0x00000224 tg3.h 　
23881
 CPU_R10CPU_R10 0x00000228 tg3.h 　
23882
 CPU_R11CPU_R11 0x0000022c tg3.h 　
23883
 CPU_R12CPU_R12 0x00000230 tg3.h 　
23884
 CPU_R13CPU_R13 0x00000234 tg3.h 　
23885
 CPU_R14CPU_R14 0x00000238 tg3.h 　
23886
 CPU_R15CPU_R15 0x0000023c tg3.h 　
23887
 CPU_R16CPU_R16 0x00000240 tg3.h 　
23888
 CPU_R17CPU_R17 0x00000244 tg3.h 　
23889
 CPU_R18CPU_R18 0x00000248 tg3.h 　
23890
 CPU_R19CPU_R19 0x0000024c tg3.h 　
23891
 CPU_R20CPU_R20 0x00000250 tg3.h 　
23892
 CPU_R21CPU_R21 0x00000254 tg3.h 　
23893
 CPU_R22CPU_R22 0x00000258 tg3.h 　
23894
 CPU_R23CPU_R23 0x0000025c tg3.h 　
23895
 CPU_R24CPU_R24 0x00000260 tg3.h 　
23896
 CPU_R25CPU_R25 0x00000264 tg3.h 　
23897
 CPU_R26CPU_R26 0x00000268 tg3.h 　
23898
 CPU_R27CPU_R27 0x0000026c tg3.h 　
23899
 CPU_R28CPU_R28 0x00000270 tg3.h 　
23900
 CPU_R29CPU_R29 0x00000274 tg3.h 　
23901
 CPU_R30CPU_R30 0x00000278 tg3.h 　
23902
 CPU_R31CPU_R31 0x0000027c tg3.h 　
23903
 RX_CPU_BASERX_CPU_BASE 0x00005000 tg3.h 　
23904
 TX_CPU_BASETX_CPU_BASE 0x00005400 tg3.h 　
23905
 GRCMBOX_INTERRUPT_0GRCMBOX_INTERRUPT_0 0x00005800 tg3.h 64-bit
23906
 GRCMBOX_INTERRUPT_1GRCMBOX_INTERRUPT_1 0x00005808 tg3.h 64-bit
23907
 GRCMBOX_INTERRUPT_2GRCMBOX_INTERRUPT_2 0x00005810 tg3.h 64-bit
23908
 GRCMBOX_INTERRUPT_3GRCMBOX_INTERRUPT_3 0x00005818 tg3.h 64-bit
23909
 GRCMBOX_GENERAL_0GRCMBOX_GENERAL_0 0x00005820 tg3.h 64-bit
23910
 GRCMBOX_GENERAL_1GRCMBOX_GENERAL_1 0x00005828 tg3.h 64-bit
23911
 GRCMBOX_GENERAL_2GRCMBOX_GENERAL_2 0x00005830 tg3.h 64-bit
23912
 GRCMBOX_GENERAL_3GRCMBOX_GENERAL_3 0x00005838 tg3.h 64-bit
23913
 GRCMBOX_GENERAL_4GRCMBOX_GENERAL_4 0x00005840 tg3.h 64-bit
23914
 GRCMBOX_GENERAL_5GRCMBOX_GENERAL_5 0x00005848 tg3.h 64-bit
23915
 GRCMBOX_GENERAL_6GRCMBOX_GENERAL_6 0x00005850 tg3.h 64-bit
23916
 GRCMBOX_GENERAL_7GRCMBOX_GENERAL_7 0x00005858 tg3.h 64-bit
23917
 GRCMBOX_RELOAD_STATGRCMBOX_RELOAD_STAT 0x00005860 tg3.h 64-bit
23918
 GRCMBOX_RCVSTD_PROD_IDXGRCMBOX_RCVSTD_PROD_IDX 0x00005868 tg3.h 64-bit
23919
 GRCMBOX_RCVJUMBO_PROD_IDXGRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 tg3.h 64-bit
23920
 GRCMBOX_RCVMINI_PROD_IDXGRCMBOX_RCVMINI_PROD_IDX 0x00005878 tg3.h 64-bit
23921
 GRCMBOX_RCVRET_CON_IDX_0GRCMBOX_RCVRET_CON_IDX_0 0x00005880 tg3.h 64-bit
23922
 GRCMBOX_RCVRET_CON_IDX_1GRCMBOX_RCVRET_CON_IDX_1 0x00005888 tg3.h 64-bit
23923
 GRCMBOX_RCVRET_CON_IDX_2GRCMBOX_RCVRET_CON_IDX_2 0x00005890 tg3.h 64-bit
23924
 GRCMBOX_RCVRET_CON_IDX_3GRCMBOX_RCVRET_CON_IDX_3 0x00005898 tg3.h 64-bit
23925
 GRCMBOX_RCVRET_CON_IDX_4GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 tg3.h 64-bit
23926
 GRCMBOX_RCVRET_CON_IDX_5GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 tg3.h 64-bit
23927
 GRCMBOX_RCVRET_CON_IDX_6GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 tg3.h 64-bit
23928
 GRCMBOX_RCVRET_CON_IDX_7GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 tg3.h 64-bit
23929
 GRCMBOX_RCVRET_CON_IDX_8GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 tg3.h 64-bit
23930
 GRCMBOX_RCVRET_CON_IDX_9GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 tg3.h 64-bit
23931
 GRCMBOX_RCVRET_CON_IDX_10GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 tg3.h 64-bit
23932
 GRCMBOX_RCVRET_CON_IDX_11GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 tg3.h 64-bit
23933
 GRCMBOX_RCVRET_CON_IDX_12GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 tg3.h 64-bit
23934
 GRCMBOX_RCVRET_CON_IDX_13GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 tg3.h 64-bit
23935
 GRCMBOX_RCVRET_CON_IDX_14GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 tg3.h 64-bit
23936
 GRCMBOX_RCVRET_CON_IDX_15GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 tg3.h 64-bit
23937
 GRCMBOX_SNDHOST_PROD_IDX_0GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 tg3.h 64-bit
23938
 GRCMBOX_SNDHOST_PROD_IDX_1GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 tg3.h 64-bit
23939
 GRCMBOX_SNDHOST_PROD_IDX_2GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 tg3.h 64-bit
23940
 GRCMBOX_SNDHOST_PROD_IDX_3GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 tg3.h 64-bit
23941
 GRCMBOX_SNDHOST_PROD_IDX_4GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 tg3.h 64-bit
23942
 GRCMBOX_SNDHOST_PROD_IDX_5GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 tg3.h 64-bit
23943
 GRCMBOX_SNDHOST_PROD_IDX_6GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 tg3.h 64-bit
23944
 GRCMBOX_SNDHOST_PROD_IDX_7GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 tg3.h 64-bit
23945
 GRCMBOX_SNDHOST_PROD_IDX_8GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 tg3.h 64-bit
23946
 GRCMBOX_SNDHOST_PROD_IDX_9GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 tg3.h 64-bit
23947
 GRCMBOX_SNDHOST_PROD_IDX_10GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 tg3.h 64-bit
23948
 GRCMBOX_SNDHOST_PROD_IDX_11GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 tg3.h 64-bit
23949
 GRCMBOX_SNDHOST_PROD_IDX_12GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 tg3.h 64-bit
23950
 GRCMBOX_SNDHOST_PROD_IDX_13GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 tg3.h 64-bit
23951
 GRCMBOX_SNDHOST_PROD_IDX_14GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 tg3.h 64-bit
23952
 GRCMBOX_SNDHOST_PROD_IDX_15GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 tg3.h 64-bit
23953
 GRCMBOX_SNDNIC_PROD_IDX_0GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 tg3.h 64-bit
23954
 GRCMBOX_SNDNIC_PROD_IDX_1GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 tg3.h 64-bit
23955
 GRCMBOX_SNDNIC_PROD_IDX_2GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 tg3.h 64-bit
23956
 GRCMBOX_SNDNIC_PROD_IDX_3GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 tg3.h 64-bit
23957
 GRCMBOX_SNDNIC_PROD_IDX_4GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 tg3.h 64-bit
23958
 GRCMBOX_SNDNIC_PROD_IDX_5GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 tg3.h 64-bit
23959
 GRCMBOX_SNDNIC_PROD_IDX_6GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 tg3.h 64-bit
23960
 GRCMBOX_SNDNIC_PROD_IDX_7GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 tg3.h 64-bit
23961
 GRCMBOX_SNDNIC_PROD_IDX_8GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 tg3.h 64-bit
23962
 GRCMBOX_SNDNIC_PROD_IDX_9GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 tg3.h 64-bit
23963
 GRCMBOX_SNDNIC_PROD_IDX_10GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 tg3.h 64-bit
23964
 GRCMBOX_SNDNIC_PROD_IDX_11GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 tg3.h 64-bit
23965
 GRCMBOX_SNDNIC_PROD_IDX_12GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 tg3.h 64-bit
23966
 GRCMBOX_SNDNIC_PROD_IDX_13GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 tg3.h 64-bit
23967
 GRCMBOX_SNDNIC_PROD_IDX_14GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 tg3.h 64-bit
23968
 GRCMBOX_SNDNIC_PROD_IDX_15GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 tg3.h 64-bit
23969
 GRCMBOX_HIGH_PRIO_EV_VECTORGRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00 tg3.h 　
23970
 GRCMBOX_HIGH_PRIO_EV_MASKGRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04 tg3.h 　
23971
 GRCMBOX_LOW_PRIO_EV_VECGRCMBOX_LOW_PRIO_EV_VEC 0x00005a08 tg3.h 　
23972
 GRCMBOX_LOW_PRIO_EV_MASKGRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c tg3.h 　
23973
 FTQ_RESETFTQ_RESET 0x00005c00 tg3.h 　
23974
 FTQ_RESET_DMA_READ_QUEUEFTQ_RESET_DMA_READ_QUEUE (1 << 1) tg3.h 　
23975
 FTQ_RESET_DMA_HIGH_PRI_READFTQ_RESET_DMA_HIGH_PRI_READ (1 << 2) tg3.h 　
23976
 FTQ_RESET_SEND_BD_COMPLETIONFTQ_RESET_SEND_BD_COMPLETION (1 << 4) tg3.h 　
23977
 FTQ_RESET_DMA_WRITEFTQ_RESET_DMA_WRITE (1 << 6) tg3.h 　
23978
 FTQ_RESET_DMA_HIGH_PRI_WRITEFTQ_RESET_DMA_HIGH_PRI_WRITE (1 << 7) tg3.h 　
23979
 FTQ_RESET_SEND_DATA_COMPLETIONFTQ_RESET_SEND_DATA_COMPLETION (1 << 9) tg3.h 　
23980
 FTQ_RESET_HOST_COALESCINGFTQ_RESET_HOST_COALESCING (1 << 10) tg3.h 　
23981
 FTQ_RESET_MAC_TXFTQ_RESET_MAC_TX (1 << 11) tg3.h 　
23982
 FTQ_RESET_RX_BD_COMPLETEFTQ_RESET_RX_BD_COMPLETE (1 << 13) tg3.h 　
23983
 FTQ_RESET_RX_LIST_PLCMTFTQ_RESET_RX_LIST_PLCMT (1 << 14) tg3.h 　
23984
 FTQ_RESET_RX_DATA_COMPLETIONFTQ_RESET_RX_DATA_COMPLETION (1 << 16) tg3.h 　
23985
 FTQ_DMA_NORM_READ_CTLFTQ_DMA_NORM_READ_CTL 0x00005c10 tg3.h 　
23986
 FTQ_DMA_NORM_READ_FULL_CNTFTQ_DMA_NORM_READ_FULL_CNT 0x00005c14 tg3.h 　
23987
 FTQ_DMA_NORM_READ_FIFO_ENQDEQFTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18 tg3.h 　
23988
 FTQ_DMA_NORM_READ_WRITE_PEEKFTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c tg3.h 　
23989
 FTQ_DMA_HIGH_READ_CTLFTQ_DMA_HIGH_READ_CTL 0x00005c20 tg3.h 　
23990
 FTQ_DMA_HIGH_READ_FULL_CNTFTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24 tg3.h 　
23991
 FTQ_DMA_HIGH_READ_FIFO_ENQDEQFTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28 tg3.h 　
23992
 FTQ_DMA_HIGH_READ_WRITE_PEEKFTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c tg3.h 　
23993
 FTQ_DMA_COMP_DISC_CTLFTQ_DMA_COMP_DISC_CTL 0x00005c30 tg3.h 　
23994
 FTQ_DMA_COMP_DISC_FULL_CNTFTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34 tg3.h 　
23995
 FTQ_DMA_COMP_DISC_FIFO_ENQDEQFTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38 tg3.h 　
23996
 FTQ_DMA_COMP_DISC_WRITE_PEEKFTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c tg3.h 　
23997
 FTQ_SEND_BD_COMP_CTLFTQ_SEND_BD_COMP_CTL 0x00005c40 tg3.h 　
23998
 FTQ_SEND_BD_COMP_FULL_CNTFTQ_SEND_BD_COMP_FULL_CNT 0x00005c44 tg3.h 　
23999
 FTQ_SEND_BD_COMP_FIFO_ENQDEQFTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48 tg3.h 　
24000
 FTQ_SEND_BD_COMP_WRITE_PEEKFTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c tg3.h 　
24001
 FTQ_SEND_DATA_INIT_CTLFTQ_SEND_DATA_INIT_CTL 0x00005c50 tg3.h 　
24002
 FTQ_SEND_DATA_INIT_FULL_CNTFTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54 tg3.h 　
24003
 FTQ_SEND_DATA_INIT_FIFO_ENQDEQFTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58 tg3.h 　
24004
 FTQ_SEND_DATA_INIT_WRITE_PEEKFTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c tg3.h 　
24005
 FTQ_DMA_NORM_WRITE_CTLFTQ_DMA_NORM_WRITE_CTL 0x00005c60 tg3.h 　
24006
 FTQ_DMA_NORM_WRITE_FULL_CNTFTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64 tg3.h 　
24007
 FTQ_DMA_NORM_WRITE_FIFO_ENQDEQFTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68 tg3.h 　
24008
 FTQ_DMA_NORM_WRITE_WRITE_PEEKFTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c tg3.h 　
24009
 FTQ_DMA_HIGH_WRITE_CTLFTQ_DMA_HIGH_WRITE_CTL 0x00005c70 tg3.h 　
24010
 FTQ_DMA_HIGH_WRITE_FULL_CNTFTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74 tg3.h 　
24011
 FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQFTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78 tg3.h 　
24012
 FTQ_DMA_HIGH_WRITE_WRITE_PEEKFTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c tg3.h 　
24013
 FTQ_SWTYPE1_CTLFTQ_SWTYPE1_CTL 0x00005c80 tg3.h 　
24014
 FTQ_SWTYPE1_FULL_CNTFTQ_SWTYPE1_FULL_CNT 0x00005c84 tg3.h 　
24015
 FTQ_SWTYPE1_FIFO_ENQDEQFTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88 tg3.h 　
24016
 FTQ_SWTYPE1_WRITE_PEEKFTQ_SWTYPE1_WRITE_PEEK 0x00005c8c tg3.h 　
24017
 FTQ_SEND_DATA_COMP_CTLFTQ_SEND_DATA_COMP_CTL 0x00005c90 tg3.h 　
24018
 FTQ_SEND_DATA_COMP_FULL_CNTFTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94 tg3.h 　
24019
 FTQ_SEND_DATA_COMP_FIFO_ENQDEQFTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98 tg3.h 　
24020
 FTQ_SEND_DATA_COMP_WRITE_PEEKFTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c tg3.h 　
24021
 FTQ_HOST_COAL_CTLFTQ_HOST_COAL_CTL 0x00005ca0 tg3.h 　
24022
 FTQ_HOST_COAL_FULL_CNTFTQ_HOST_COAL_FULL_CNT 0x00005ca4 tg3.h 　
24023
 FTQ_HOST_COAL_FIFO_ENQDEQFTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8 tg3.h 　
24024
 FTQ_HOST_COAL_WRITE_PEEKFTQ_HOST_COAL_WRITE_PEEK 0x00005cac tg3.h 　
24025
 FTQ_MAC_TX_CTLFTQ_MAC_TX_CTL 0x00005cb0 tg3.h 　
24026
 FTQ_MAC_TX_FULL_CNTFTQ_MAC_TX_FULL_CNT 0x00005cb4 tg3.h 　
24027
 FTQ_MAC_TX_FIFO_ENQDEQFTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8 tg3.h 　
24028
 FTQ_MAC_TX_WRITE_PEEKFTQ_MAC_TX_WRITE_PEEK 0x00005cbc tg3.h 　
24029
 FTQ_MB_FREE_CTLFTQ_MB_FREE_CTL 0x00005cc0 tg3.h 　
24030
 FTQ_MB_FREE_FULL_CNTFTQ_MB_FREE_FULL_CNT 0x00005cc4 tg3.h 　
24031
 FTQ_MB_FREE_FIFO_ENQDEQFTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8 tg3.h 　
24032
 FTQ_MB_FREE_WRITE_PEEKFTQ_MB_FREE_WRITE_PEEK 0x00005ccc tg3.h 　
24033
 FTQ_RCVBD_COMP_CTLFTQ_RCVBD_COMP_CTL 0x00005cd0 tg3.h 　
24034
 FTQ_RCVBD_COMP_FULL_CNTFTQ_RCVBD_COMP_FULL_CNT 0x00005cd4 tg3.h 　
24035
 FTQ_RCVBD_COMP_FIFO_ENQDEQFTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8 tg3.h 　
24036
 FTQ_RCVBD_COMP_WRITE_PEEKFTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc tg3.h 　
24037
 FTQ_RCVLST_PLMT_CTLFTQ_RCVLST_PLMT_CTL 0x00005ce0 tg3.h 　
24038
 FTQ_RCVLST_PLMT_FULL_CNTFTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4 tg3.h 　
24039
 FTQ_RCVLST_PLMT_FIFO_ENQDEQFTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8 tg3.h 　
24040
 FTQ_RCVLST_PLMT_WRITE_PEEKFTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec tg3.h 　
24041
 FTQ_RCVDATA_INI_CTLFTQ_RCVDATA_INI_CTL 0x00005cf0 tg3.h 　
24042
 FTQ_RCVDATA_INI_FULL_CNTFTQ_RCVDATA_INI_FULL_CNT 0x00005cf4 tg3.h 　
24043
 FTQ_RCVDATA_INI_FIFO_ENQDEQFTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8 tg3.h 　
24044
 FTQ_RCVDATA_INI_WRITE_PEEKFTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc tg3.h 　
24045
 FTQ_RCVDATA_COMP_CTLFTQ_RCVDATA_COMP_CTL 0x00005d00 tg3.h 　
24046
 FTQ_RCVDATA_COMP_FULL_CNTFTQ_RCVDATA_COMP_FULL_CNT 0x00005d04 tg3.h 　
24047
 FTQ_RCVDATA_COMP_FIFO_ENQDEQFTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08 tg3.h 　
24048
 FTQ_RCVDATA_COMP_WRITE_PEEKFTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c tg3.h 　
24049
 FTQ_SWTYPE2_CTLFTQ_SWTYPE2_CTL 0x00005d10 tg3.h 　
24050
 FTQ_SWTYPE2_FULL_CNTFTQ_SWTYPE2_FULL_CNT 0x00005d14 tg3.h 　
24051
 FTQ_SWTYPE2_FIFO_ENQDEQFTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18 tg3.h 　
24052
 FTQ_SWTYPE2_WRITE_PEEKFTQ_SWTYPE2_WRITE_PEEK 0x00005d1c tg3.h 　
24053
 MSGINT_MODEMSGINT_MODE 0x00006000 tg3.h 　
24054
 MSGINT_MODE_RESETMSGINT_MODE_RESET 0x00000001 tg3.h 　
24055
 MSGINT_MODE_ENABLEMSGINT_MODE_ENABLE 0x00000002 tg3.h 　
24056
 MSGINT_STATUSMSGINT_STATUS 0x00006004 tg3.h 　
24057
 MSGINT_FIFOMSGINT_FIFO 0x00006008 tg3.h 　
24058
 DMAC_MODEDMAC_MODE 0x00006400 tg3.h 　
24059
 DMAC_MODE_RESETDMAC_MODE_RESET 0x00000001 tg3.h 　
24060
 DMAC_MODE_ENABLEDMAC_MODE_ENABLE 0x00000002 tg3.h 　
24061
 GRC_MODEGRC_MODE 0x00006800 tg3.h 　
24062
 GRC_MODE_UPD_ON_COALGRC_MODE_UPD_ON_COAL 0x00000001 tg3.h 　
24063
 GRC_MODE_BSWAP_NONFRM_DATAGRC_MODE_BSWAP_NONFRM_DATA 0x00000002 tg3.h 　
24064
 GRC_MODE_WSWAP_NONFRM_DATAGRC_MODE_WSWAP_NONFRM_DATA 0x00000004 tg3.h 　
24065
 GRC_MODE_BSWAP_DATAGRC_MODE_BSWAP_DATA 0x00000010 tg3.h 　
24066
 GRC_MODE_WSWAP_DATAGRC_MODE_WSWAP_DATA 0x00000020 tg3.h 　
24067
 GRC_MODE_SPLITHDRGRC_MODE_SPLITHDR 0x00000100 tg3.h 　
24068
 GRC_MODE_NOFRM_CRACKINGGRC_MODE_NOFRM_CRACKING 0x00000200 tg3.h 　
24069
 GRC_MODE_INCL_CRCGRC_MODE_INCL_CRC 0x00000400 tg3.h 　
24070
 GRC_MODE_ALLOW_BAD_FRMSGRC_MODE_ALLOW_BAD_FRMS 0x00000800 tg3.h 　
24071
 GRC_MODE_NOIRQ_ON_SENDSGRC_MODE_NOIRQ_ON_SENDS 0x00002000 tg3.h 　
24072
 GRC_MODE_NOIRQ_ON_RCVGRC_MODE_NOIRQ_ON_RCV 0x00004000 tg3.h 　
24073
 GRC_MODE_FORCE_PCI32BITGRC_MODE_FORCE_PCI32BIT 0x00008000 tg3.h 　
24074
 GRC_MODE_HOST_STACKUPGRC_MODE_HOST_STACKUP 0x00010000 tg3.h 　
24075
 GRC_MODE_HOST_SENDBDSGRC_MODE_HOST_SENDBDS 0x00020000 tg3.h 　
24076
 GRC_MODE_NO_TX_PHDR_CSUMGRC_MODE_NO_TX_PHDR_CSUM 0x00100000 tg3.h 　
24077
 GRC_MODE_NO_RX_PHDR_CSUMGRC_MODE_NO_RX_PHDR_CSUM 0x00800000 tg3.h 　
24078
 GRC_MODE_IRQ_ON_TX_CPU_ATTNGRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000 tg3.h 　
24079
 GRC_MODE_IRQ_ON_RX_CPU_ATTNGRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000 tg3.h 　
24080
 GRC_MODE_IRQ_ON_MAC_ATTNGRC_MODE_IRQ_ON_MAC_ATTN 0x04000000 tg3.h 　
24081
 GRC_MODE_IRQ_ON_DMA_ATTNGRC_MODE_IRQ_ON_DMA_ATTN 0x08000000 tg3.h 　
24082
 GRC_MODE_IRQ_ON_FLOW_ATTNGRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000 tg3.h 　
24083
 GRC_MODE_4X_NIC_SEND_RINGSGRC_MODE_4X_NIC_SEND_RINGS 0x20000000 tg3.h 　
24084
 GRC_MODE_MCAST_FRM_ENABLEGRC_MODE_MCAST_FRM_ENABLE 0x40000000 tg3.h 　
24085
 GRC_MISC_CFGGRC_MISC_CFG 0x00006804 tg3.h 　
24086
 GRC_MISC_CFG_CORECLK_RESETGRC_MISC_CFG_CORECLK_RESET 0x00000001 tg3.h 　
24087
 GRC_MISC_CFG_PRESCALAR_MASKGRC_MISC_CFG_PRESCALAR_MASK 0x000000fe tg3.h 　
24088
 GRC_MISC_CFG_PRESCALAR_SHIFTGRC_MISC_CFG_PRESCALAR_SHIFT 1 tg3.h 　
24089
 GRC_MISC_CFG_BOARD_ID_MASKGRC_MISC_CFG_BOARD_ID_MASK 0x0001e000 tg3.h 　
24090
 GRC_MISC_CFG_BOARD_ID_5700GRC_MISC_CFG_BOARD_ID_5700 0x0001e000 tg3.h 　
24091
 GRC_MISC_CFG_BOARD_ID_5701GRC_MISC_CFG_BOARD_ID_5701 0x00000000 tg3.h 　
24092
 GRC_MISC_CFG_BOARD_ID_5702FEGRC_MISC_CFG_BOARD_ID_5702FE 0x00004000 tg3.h 　
24093
 GRC_MISC_CFG_BOARD_ID_5703GRC_MISC_CFG_BOARD_ID_5703 0x00000000 tg3.h 　
24094
 GRC_MISC_CFG_BOARD_ID_5703SGRC_MISC_CFG_BOARD_ID_5703S 0x00002000 tg3.h 　
24095
 GRC_MISC_CFG_BOARD_ID_5704GRC_MISC_CFG_BOARD_ID_5704 0x00000000 tg3.h 　
24096
 GRC_MISC_CFG_BOARD_ID_5704CIOBEGRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000 tg3.h 　
24097
 GRC_MISC_CFG_BOARD_ID_5704_A2GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000 tg3.h 　
24098
 GRC_MISC_CFG_BOARD_ID_5788GRC_MISC_CFG_BOARD_ID_5788 0x00010000 tg3.h 　
24099
 GRC_MISC_CFG_BOARD_ID_5788MGRC_MISC_CFG_BOARD_ID_5788M 0x00018000 tg3.h 　
24100
 GRC_MISC_CFG_BOARD_ID_AC91002A1GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000 tg3.h 　
24101
 GRC_MISC_CFG_KEEP_GPHY_POWERGRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000 tg3.h 　
24102
 GRC_LOCAL_CTRLGRC_LOCAL_CTRL 0x00006808 tg3.h 　
24103
 GRC_LCLCTRL_INT_ACTIVEGRC_LCLCTRL_INT_ACTIVE 0x00000001 tg3.h 　
24104
 GRC_LCLCTRL_CLEARINTGRC_LCLCTRL_CLEARINT 0x00000002 tg3.h 　
24105
 GRC_LCLCTRL_SETINTGRC_LCLCTRL_SETINT 0x00000004 tg3.h 　
24106
 GRC_LCLCTRL_INT_ON_ATTNGRC_LCLCTRL_INT_ON_ATTN 0x00000008 tg3.h 　
24107
 GRC_LCLCTRL_GPIO_INPUT0GRC_LCLCTRL_GPIO_INPUT0 0x00000100 tg3.h 　
24108
 GRC_LCLCTRL_GPIO_INPUT1GRC_LCLCTRL_GPIO_INPUT1 0x00000200 tg3.h 　
24109
 GRC_LCLCTRL_GPIO_INPUT2GRC_LCLCTRL_GPIO_INPUT2 0x00000400 tg3.h 　
24110
 GRC_LCLCTRL_GPIO_OE0GRC_LCLCTRL_GPIO_OE0 0x00000800 tg3.h 　
24111
 GRC_LCLCTRL_GPIO_OE1GRC_LCLCTRL_GPIO_OE1 0x00001000 tg3.h 　
24112
 GRC_LCLCTRL_GPIO_OE2GRC_LCLCTRL_GPIO_OE2 0x00002000 tg3.h 　
24113
 GRC_LCLCTRL_GPIO_OUTPUT0GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000 tg3.h 　
24114
 GRC_LCLCTRL_GPIO_OUTPUT1GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000 tg3.h 　
24115
 GRC_LCLCTRL_GPIO_OUTPUT2GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000 tg3.h 　
24116
 GRC_LCLCTRL_EXTMEM_ENABLEGRC_LCLCTRL_EXTMEM_ENABLE 0x00020000 tg3.h 　
24117
 GRC_LCLCTRL_MEMSZ_MASKGRC_LCLCTRL_MEMSZ_MASK 0x001c0000 tg3.h 　
24118
 GRC_LCLCTRL_MEMSZ_256KGRC_LCLCTRL_MEMSZ_256K 0x00000000 tg3.h 　
24119
 GRC_LCLCTRL_MEMSZ_512KGRC_LCLCTRL_MEMSZ_512K 0x00040000 tg3.h 　
24120
 GRC_LCLCTRL_MEMSZ_1MGRC_LCLCTRL_MEMSZ_1M 0x00080000 tg3.h 　
24121
 GRC_LCLCTRL_MEMSZ_2MGRC_LCLCTRL_MEMSZ_2M 0x000c0000 tg3.h 　
24122
 GRC_LCLCTRL_MEMSZ_4MGRC_LCLCTRL_MEMSZ_4M 0x00100000 tg3.h 　
24123
 GRC_LCLCTRL_MEMSZ_8MGRC_LCLCTRL_MEMSZ_8M 0x00140000 tg3.h 　
24124
 GRC_LCLCTRL_MEMSZ_16MGRC_LCLCTRL_MEMSZ_16M 0x00180000 tg3.h 　
24125
 GRC_LCLCTRL_BANK_SELECTGRC_LCLCTRL_BANK_SELECT 0x00200000 tg3.h 　
24126
 GRC_LCLCTRL_SSRAM_TYPEGRC_LCLCTRL_SSRAM_TYPE 0x00400000 tg3.h 　
24127
 GRC_LCLCTRL_AUTO_SEEPROMGRC_LCLCTRL_AUTO_SEEPROM 0x01000000 tg3.h 　
24128
 GRC_TIMERGRC_TIMER 0x0000680c tg3.h 　
24129
 GRC_RX_CPU_EVENTGRC_RX_CPU_EVENT 0x00006810 tg3.h 　
24130
 GRC_RX_TIMER_REFGRC_RX_TIMER_REF 0x00006814 tg3.h 　
24131
 GRC_RX_CPU_SEMGRC_RX_CPU_SEM 0x00006818 tg3.h 　
24132
 GRC_REMOTE_RX_CPU_ATTNGRC_REMOTE_RX_CPU_ATTN 0x0000681c tg3.h 　
24133
 GRC_TX_CPU_EVENTGRC_TX_CPU_EVENT 0x00006820 tg3.h 　
24134
 GRC_TX_TIMER_REFGRC_TX_TIMER_REF 0x00006824 tg3.h 　
24135
 GRC_TX_CPU_SEMGRC_TX_CPU_SEM 0x00006828 tg3.h 　
24136
 GRC_REMOTE_TX_CPU_ATTNGRC_REMOTE_TX_CPU_ATTN 0x0000682c tg3.h 　
24137
 GRC_MEM_POWER_UPGRC_MEM_POWER_UP 0x00006830 tg3.h 64-bit
24138
 GRC_EEPROM_ADDRGRC_EEPROM_ADDR 0x00006838 tg3.h 　
24139
 EEPROM_ADDR_WRITEEEPROM_ADDR_WRITE 0x00000000 tg3.h 　
24140
 EEPROM_ADDR_READEEPROM_ADDR_READ 0x80000000 tg3.h 　
24141
 EEPROM_ADDR_COMPLETEEEPROM_ADDR_COMPLETE 0x40000000 tg3.h 　
24142
 EEPROM_ADDR_FSM_RESETEEPROM_ADDR_FSM_RESET 0x20000000 tg3.h 　
24143
 EEPROM_ADDR_DEVID_MASKEEPROM_ADDR_DEVID_MASK 0x1c000000 tg3.h 　
24144
 EEPROM_ADDR_DEVID_SHIFTEEPROM_ADDR_DEVID_SHIFT 26 tg3.h 　
24145
 EEPROM_ADDR_STARTEEPROM_ADDR_START 0x02000000 tg3.h 　
24146
 EEPROM_ADDR_CLKPERD_SHIFTEEPROM_ADDR_CLKPERD_SHIFT 16 tg3.h 　
24147
 EEPROM_ADDR_ADDR_MASKEEPROM_ADDR_ADDR_MASK 0x0000ffff tg3.h 　
24148
 EEPROM_ADDR_ADDR_SHIFTEEPROM_ADDR_ADDR_SHIFT 0 tg3.h 　
24149
 EEPROM_DEFAULT_CLOCK_PERIODEEPROM_DEFAULT_CLOCK_PERIOD 0x60 tg3.h 　
24150
 EEPROM_CHIP_SIZEEEPROM_CHIP_SIZE (64 * 1024) tg3.h 　
24151
 GRC_EEPROM_DATAGRC_EEPROM_DATA 0x0000683c tg3.h 　
24152
 GRC_EEPROM_CTRLGRC_EEPROM_CTRL 0x00006840 tg3.h 　
24153
 GRC_MDI_CTRLGRC_MDI_CTRL 0x00006844 tg3.h 　
24154
 GRC_SEEPROM_DELAYGRC_SEEPROM_DELAY 0x00006848 tg3.h 　
24155
 NVRAM_CMDNVRAM_CMD 0x00007000 tg3.h 　
24156
 NVRAM_CMD_RESETNVRAM_CMD_RESET 0x00000001 tg3.h 　
24157
 NVRAM_CMD_DONENVRAM_CMD_DONE 0x00000008 tg3.h 　
24158
 NVRAM_CMD_GONVRAM_CMD_GO 0x00000010 tg3.h 　
24159
 NVRAM_CMD_WRNVRAM_CMD_WR 0x00000020 tg3.h 　
24160
 NVRAM_CMD_RDNVRAM_CMD_RD 0x00000000 tg3.h 　
24161
 NVRAM_CMD_ERASENVRAM_CMD_ERASE 0x00000040 tg3.h 　
24162
 NVRAM_CMD_FIRSTNVRAM_CMD_FIRST 0x00000080 tg3.h 　
24163
 NVRAM_CMD_LASTNVRAM_CMD_LAST 0x00000100 tg3.h 　
24164
 NVRAM_STATNVRAM_STAT 0x00007004 tg3.h 　
24165
 NVRAM_WRDATANVRAM_WRDATA 0x00007008 tg3.h 　
24166
 NVRAM_ADDRNVRAM_ADDR 0x0000700c tg3.h 　
24167
 NVRAM_ADDR_MSKNVRAM_ADDR_MSK 0x00ffffff tg3.h 　
24168
 NVRAM_RDDATANVRAM_RDDATA 0x00007010 tg3.h 　
24169
 NVRAM_CFG1NVRAM_CFG1 0x00007014 tg3.h 　
24170
 NVRAM_CFG1_FLASHIF_ENABNVRAM_CFG1_FLASHIF_ENAB 0x00000001 tg3.h 　
24171
 NVRAM_CFG1_BUFFERED_MODENVRAM_CFG1_BUFFERED_MODE 0x00000002 tg3.h 　
24172
 NVRAM_CFG1_PASS_THRUNVRAM_CFG1_PASS_THRU 0x00000004 tg3.h 　
24173
 NVRAM_CFG1_BIT_BANGNVRAM_CFG1_BIT_BANG 0x00000008 tg3.h 　
24174
 NVRAM_CFG1_COMPAT_BYPASSNVRAM_CFG1_COMPAT_BYPASS 0x80000000 tg3.h 　
24175
 NVRAM_CFG2NVRAM_CFG2 0x00007018 tg3.h 　
24176
 NVRAM_CFG3NVRAM_CFG3 0x0000701c tg3.h 　
24177
 NVRAM_SWARBNVRAM_SWARB 0x00007020 tg3.h 　
24178
 SWARB_REQ_SET0SWARB_REQ_SET0 0x00000001 tg3.h 　
24179
 SWARB_REQ_SET1SWARB_REQ_SET1 0x00000002 tg3.h 　
24180
 SWARB_REQ_SET2SWARB_REQ_SET2 0x00000004 tg3.h 　
24181
 SWARB_REQ_SET3SWARB_REQ_SET3 0x00000008 tg3.h 　
24182
 SWARB_REQ_CLR0SWARB_REQ_CLR0 0x00000010 tg3.h 　
24183
 SWARB_REQ_CLR1SWARB_REQ_CLR1 0x00000020 tg3.h 　
24184
 SWARB_REQ_CLR2SWARB_REQ_CLR2 0x00000040 tg3.h 　
24185
 SWARB_REQ_CLR3SWARB_REQ_CLR3 0x00000080 tg3.h 　
24186
 SWARB_GNT0SWARB_GNT0 0x00000100 tg3.h 　
24187
 SWARB_GNT1SWARB_GNT1 0x00000200 tg3.h 　
24188
 SWARB_GNT2SWARB_GNT2 0x00000400 tg3.h 　
24189
 SWARB_GNT3SWARB_GNT3 0x00000800 tg3.h 　
24190
 SWARB_REQ0SWARB_REQ0 0x00001000 tg3.h 　
24191
 SWARB_REQ1SWARB_REQ1 0x00002000 tg3.h 　
24192
 SWARB_REQ2SWARB_REQ2 0x00004000 tg3.h 　
24193
 SWARB_REQ3SWARB_REQ3 0x00008000 tg3.h 　
24194
 NVRAM_BUFFERED_PAGE_SIZENVRAM_BUFFERED_PAGE_SIZE 264 tg3.h 　
24195
 NVRAM_BUFFERED_PAGE_POSNVRAM_BUFFERED_PAGE_POS 9 tg3.h 　
24196
 NIC_SRAM_WIN_BASENIC_SRAM_WIN_BASE 0x00008000 tg3.h 　
24197
 NIC_SRAM_PAGE_ZERONIC_SRAM_PAGE_ZERO 0x00000000 tg3.h 　
24198
 NIC_SRAM_SEND_RCBNIC_SRAM_SEND_RCB 0x00000100 tg3.h 16 * TG3_BDINFO_...
24199
 NIC_SRAM_RCV_RET_RCBNIC_SRAM_RCV_RET_RCB 0x00000200 tg3.h 16 * TG3_BDINFO_...
24200
 NIC_SRAM_STATS_BLKNIC_SRAM_STATS_BLK 0x00000300 tg3.h 　
24201
 NIC_SRAM_STATUS_BLKNIC_SRAM_STATUS_BLK 0x00000b00 tg3.h 　
24202
 NIC_SRAM_FIRMWARE_MBOXNIC_SRAM_FIRMWARE_MBOX 0x00000b50 tg3.h 　
24203
 NIC_SRAM_FIRMWARE_MBOX_MAGIC1NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654 tg3.h 　
24204
 NIC_SRAM_FIRMWARE_MBOX_MAGIC2NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b tg3.h !dma on linkchg
24205
 NIC_SRAM_DATA_SIGNIC_SRAM_DATA_SIG 0x00000b54 tg3.h 　
24206
 NIC_SRAM_DATA_SIG_MAGICNIC_SRAM_DATA_SIG_MAGIC 0x4b657654 tg3.h ascii for 'KevT'
24207
 NIC_SRAM_DATA_CFGNIC_SRAM_DATA_CFG 0x00000b58 tg3.h 　
24208
 NIC_SRAM_DATA_CFG_LED_MODE_MASKNIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c tg3.h 　
24209
 NIC_SRAM_DATA_CFG_LED_MODE_UNKNNIC_SRAM_DATA_CFG_LED_MODE_UNKN 0x00000000 tg3.h 　
24210
 NIC_SRAM_DATA_CFG_LED_TRIPLE_SPNIC_SRAM_DATA_CFG_LED_TRIPLE_SP 0x00000004 tg3.h 　
24211
 NIC_SRAM_DATA_CFG_LED_OPEN_DRAINIC_SRAM_DATA_CFG_LED_OPEN_DRAI 0x00000004 tg3.h 　
24212
 NIC_SRAM_DATA_CFG_LED_LINK_SPDNIC_SRAM_DATA_CFG_LED_LINK_SPD 0x00000008 tg3.h 　
24213
 NIC_SRAM_DATA_CFG_LED_OUTPUTNIC_SRAM_DATA_CFG_LED_OUTPUT 0x00000008 tg3.h 　
24214
 NIC_SRAM_DATA_CFG_PHY_TYPE_MASKNIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030 tg3.h 　
24215
 NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNNIC_SRAM_DATA_CFG_PHY_TYPE_UNKN 0x00000000 tg3.h 　
24216
 NIC_SRAM_DATA_CFG_PHY_TYPE_COPPNIC_SRAM_DATA_CFG_PHY_TYPE_COPP 0x00000010 tg3.h 　
24217
 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBENIC_SRAM_DATA_CFG_PHY_TYPE_FIBE 0x00000020 tg3.h 　
24218
 NIC_SRAM_DATA_CFG_WOL_ENABLENIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040 tg3.h 　
24219
 NIC_SRAM_DATA_CFG_ASF_ENABLENIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080 tg3.h 　
24220
 NIC_SRAM_DATA_CFG_EEPROM_WPNIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100 tg3.h 　
24221
 NIC_SRAM_DATA_CFG_MINI_PCINIC_SRAM_DATA_CFG_MINI_PCI 0x00001000 tg3.h 　
24222
 NIC_SRAM_DATA_CFG_FIBER_WOLNIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000 tg3.h 　
24223
 NIC_SRAM_DATA_PHY_IDNIC_SRAM_DATA_PHY_ID 0x00000b74 tg3.h 　
24224
 NIC_SRAM_DATA_PHY_ID1_MASKNIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000 tg3.h 　
24225
 NIC_SRAM_DATA_PHY_ID2_MASKNIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff tg3.h 　
24226
 NIC_SRAM_FW_CMD_MBOXNIC_SRAM_FW_CMD_MBOX 0x00000b78 tg3.h 　
24227
 FWCMD_NICDRV_ALIVEFWCMD_NICDRV_ALIVE 0x00000001 tg3.h 　
24228
 FWCMD_NICDRV_PAUSE_FWFWCMD_NICDRV_PAUSE_FW 0x00000002 tg3.h 　
24229
 FWCMD_NICDRV_IPV4ADDR_CHGFWCMD_NICDRV_IPV4ADDR_CHG 0x00000003 tg3.h 　
24230
 FWCMD_NICDRV_IPV6ADDR_CHGFWCMD_NICDRV_IPV6ADDR_CHG 0x00000004 tg3.h 　
24231
 FWCMD_NICDRV_FIX_DMARFWCMD_NICDRV_FIX_DMAR 0x00000005 tg3.h 　
24232
 FWCMD_NICDRV_FIX_DMAWFWCMD_NICDRV_FIX_DMAW 0x00000006 tg3.h 　
24233
 NIC_SRAM_FW_CMD_LEN_MBOXNIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c tg3.h 　
24234
 NIC_SRAM_FW_CMD_DATA_MBOXNIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80 tg3.h 　
24235
 NIC_SRAM_FW_ASF_STATUS_MBOXNIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00 tg3.h 　
24236
 NIC_SRAM_FW_DRV_STATE_MBOXNIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04 tg3.h 　
24237
 DRV_STATE_STARTDRV_STATE_START 0x00000001 tg3.h 　
24238
 DRV_STATE_UNLOADDRV_STATE_UNLOAD 0x00000002 tg3.h 　
24239
 DRV_STATE_WOLDRV_STATE_WOL 0x00000003 tg3.h 　
24240
 DRV_STATE_SUSPENDDRV_STATE_SUSPEND 0x00000004 tg3.h 　
24241
 NIC_SRAM_FW_RESET_TYPE_MBOXNIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08 tg3.h 　
24242
 NIC_SRAM_MAC_ADDR_HIGH_MBOXNIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14 tg3.h 　
24243
 NIC_SRAM_MAC_ADDR_LOW_MBOXNIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18 tg3.h 　
24244
 NIC_SRAM_RX_MINI_BUFFER_DESCNIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000 tg3.h 　
24245
 NIC_SRAM_DMA_DESC_POOL_BASENIC_SRAM_DMA_DESC_POOL_BASE 0x00002000 tg3.h 　
24246
 NIC_SRAM_DMA_DESC_POOL_SIZENIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000 tg3.h 　
24247
 NIC_SRAM_TX_BUFFER_DESCNIC_SRAM_TX_BUFFER_DESC 0x00004000 tg3.h 512 entries
24248
 NIC_SRAM_RX_BUFFER_DESCNIC_SRAM_RX_BUFFER_DESC 0x00006000 tg3.h 256 entries
24249
 NIC_SRAM_RX_JUMBO_BUFFER_DESCNIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 tg3.h 256 entries
24250
 NIC_SRAM_MBUF_POOL_BASENIC_SRAM_MBUF_POOL_BASE 0x00008000 tg3.h 　
24251
 NIC_SRAM_MBUF_POOL_SIZE96NIC_SRAM_MBUF_POOL_SIZE96 0x00018000 tg3.h 　
24252
 NIC_SRAM_MBUF_POOL_SIZE64NIC_SRAM_MBUF_POOL_SIZE64 0x00010000 tg3.h 　
24253
 NIC_SRAM_MBUF_POOL_BASE5705NIC_SRAM_MBUF_POOL_BASE5705 0x00010000 tg3.h 　
24254
 NIC_SRAM_MBUF_POOL_SIZE5705NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000 tg3.h 　
24255
 PHY_ADDRPHY_ADDR 0x01 tg3.h 　
24256
 TG3_BMCR_SPEED1000TG3_BMCR_SPEED1000 0x0040 tg3.h 　
24257
 MII_TG3_CTRLMII_TG3_CTRL 0x09 tg3.h 1000-baseT control register
24258
 MII_TG3_CTRL_ADV_1000_HALFMII_TG3_CTRL_ADV_1000_HALF 0x0100 tg3.h 　
24259
 MII_TG3_CTRL_ADV_1000_FULLMII_TG3_CTRL_ADV_1000_FULL 0x0200 tg3.h 　
24260
 MII_TG3_CTRL_AS_MASTERMII_TG3_CTRL_AS_MASTER 0x0800 tg3.h 　
24261
 MII_TG3_CTRL_ENABLE_AS_MASTERMII_TG3_CTRL_ENABLE_AS_MASTER 0x1000 tg3.h 　
24262
 MII_TG3_EXT_CTRLMII_TG3_EXT_CTRL 0x10 tg3.h Extended control register
24263
 MII_TG3_EXT_CTRL_LNK3_LED_MODEMII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002 tg3.h 　
24264
 MII_TG3_EXT_CTRL_TBIMII_TG3_EXT_CTRL_TBI 0x8000 tg3.h 　
24265
 MII_TG3_EXT_STATMII_TG3_EXT_STAT 0x11 tg3.h Extended status register
24266
 MII_TG3_EXT_STAT_LPASSMII_TG3_EXT_STAT_LPASS 0x0100 tg3.h 　
24267
 MII_TG3_DSP_RW_PORTMII_TG3_DSP_RW_PORT 0x15 tg3.h DSP coefficient read/write port
24268
 MII_TG3_DSP_ADDRESSMII_TG3_DSP_ADDRESS 0x17 tg3.h DSP address register
24269
 MII_TG3_AUX_CTRLMII_TG3_AUX_CTRL 0x18 tg3.h auxilliary control register
24270
 MII_TG3_AUX_STATMII_TG3_AUX_STAT 0x19 tg3.h auxilliary status register
24271
 MII_TG3_AUX_STAT_LPASSMII_TG3_AUX_STAT_LPASS 0x0004 tg3.h 　
24272
 MII_TG3_AUX_STAT_SPDMASKMII_TG3_AUX_STAT_SPDMASK 0x0700 tg3.h 　
24273
 MII_TG3_AUX_STAT_10HALFMII_TG3_AUX_STAT_10HALF 0x0100 tg3.h 　
24274
 MII_TG3_AUX_STAT_10FULLMII_TG3_AUX_STAT_10FULL 0x0200 tg3.h 　
24275
 MII_TG3_AUX_STAT_100HALFMII_TG3_AUX_STAT_100HALF 0x0300 tg3.h 　
24276
 MII_TG3_AUX_STAT_100_4MII_TG3_AUX_STAT_100_4 0x0400 tg3.h 　
24277
 MII_TG3_AUX_STAT_100FULLMII_TG3_AUX_STAT_100FULL 0x0500 tg3.h 　
24278
 MII_TG3_AUX_STAT_1000HALFMII_TG3_AUX_STAT_1000HALF 0x0600 tg3.h 　
24279
 MII_TG3_AUX_STAT_1000FULLMII_TG3_AUX_STAT_1000FULL 0x0700 tg3.h 　
24280
 MII_TG3_ISTATMII_TG3_ISTAT 0x1a tg3.h IRQ status register
24281
 MII_TG3_IMASKMII_TG3_IMASK 0x1b tg3.h IRQ mask register
24282
 MII_TG3_INT_LINKCHGMII_TG3_INT_LINKCHG 0x0002 tg3.h 　
24283
 MII_TG3_INT_SPEEDCHGMII_TG3_INT_SPEEDCHG 0x0004 tg3.h 　
24284
 MII_TG3_INT_DUPLEXCHGMII_TG3_INT_DUPLEXCHG 0x0008 tg3.h 　
24285
 MII_TG3_INT_ANEG_PAGE_RXMII_TG3_INT_ANEG_PAGE_RX 0x0400 tg3.h 　
24286
 TXD_ADDRTXD_ADDR 0x00UL tg3.h 64-bit
24287
 TXD_LEN_FLAGSTXD_LEN_FLAGS 0x08UL tg3.h 32-bit (upper 16-bits are len)
24288
 TXD_VLAN_TAGTXD_VLAN_TAG 0x0cUL tg3.h 32-bit (upper 16-bits are tag)
24289
 TXD_SIZETXD_SIZE 0x10UL tg3.h 　
24290
 TG3_HW_STATUS_SIZETG3_HW_STATUS_SIZE 0x50 tg3.h 　
24291
 FALSEFALSE 0 tlan.h 　
24292
 TRUETRUE 1 tlan.h 　
24293
 TLAN_MIN_FRAME_SIZETLAN_MIN_FRAME_SIZE 64 tlan.h 　
24294
 TLAN_MAX_FRAME_SIZETLAN_MAX_FRAME_SIZE 1600 tlan.h 　
24295
 TLAN_NUM_RX_LISTSTLAN_NUM_RX_LISTS 4 tlan.h 　
24296
 TLAN_NUM_TX_LISTSTLAN_NUM_TX_LISTS 2 tlan.h 　
24297
 TLAN_IGNORETLAN_IGNORE 0 tlan.h 　
24298
 TLAN_RECORDTLAN_RECORD 1 tlan.h 　
24299
 TLAN_DEBUG_GNRLTLAN_DEBUG_GNRL 0x0001 tlan.h 　
24300
 TLAN_DEBUG_TXTLAN_DEBUG_TX 0x0002 tlan.h 　
24301
 TLAN_DEBUG_RXTLAN_DEBUG_RX 0x0004 tlan.h 　
24302
 TLAN_DEBUG_LISTTLAN_DEBUG_LIST 0x0008 tlan.h 　
24303
 TLAN_DEBUG_PROBETLAN_DEBUG_PROBE 0x0010 tlan.h 　
24304
 TX_TIMEOUTTX_TIMEOUT (10*HZ) tlan.h We need time for auto-neg
24305
 MAX_TLAN_BOARDSMAX_TLAN_BOARDS 8 tlan.h Max number of boards installed at a time
24306
 PCI_DEVICE_ID_NETELLIGENT_10_T2PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012 tlan.h 　
24307
 PCI_DEVICE_ID_NETELLIGENT_10_10PCI_DEVICE_ID_NETELLIGENT_10_10 0xB030 tlan.h 　
24308
 PCI_DEVICE_ID_OLICOM_OC2183PCI_DEVICE_ID_OLICOM_OC2183 0x0013 tlan.h 　
24309
 PCI_DEVICE_ID_OLICOM_OC2325PCI_DEVICE_ID_OLICOM_OC2325 0x0012 tlan.h 　
24310
 PCI_DEVICE_ID_OLICOM_OC2326PCI_DEVICE_ID_OLICOM_OC2326 0x0014 tlan.h 　
24311
 TLAN_ADAPTER_NONETLAN_ADAPTER_NONE 0x00000000 tlan.h 　
24312
 TLAN_ADAPTER_UNMANAGED_PHYTLAN_ADAPTER_UNMANAGED_PHY 0x00000001 tlan.h 　
24313
 TLAN_ADAPTER_BIT_RATE_PHYTLAN_ADAPTER_BIT_RATE_PHY 0x00000002 tlan.h 　
24314
 TLAN_ADAPTER_USE_INTERN_10TLAN_ADAPTER_USE_INTERN_10 0x00000004 tlan.h 　
24315
 TLAN_ADAPTER_ACTIVITY_LEDTLAN_ADAPTER_ACTIVITY_LED 0x00000008 tlan.h 　
24316
 TLAN_SPEED_DEFAULTTLAN_SPEED_DEFAULT 0 tlan.h 　
24317
 TLAN_SPEED_10TLAN_SPEED_10 10 tlan.h 　
24318
 TLAN_SPEED_100TLAN_SPEED_100 100 tlan.h 　
24319
 TLAN_DUPLEX_DEFAULTTLAN_DUPLEX_DEFAULT 0 tlan.h 　
24320
 TLAN_DUPLEX_HALFTLAN_DUPLEX_HALF 1 tlan.h 　
24321
 TLAN_DUPLEX_FULLTLAN_DUPLEX_FULL 2 tlan.h 　
24322
 EISA_IDEISA_ID 0xc80 tlan.h EISA ID Registers
24323
 EISA_ID0EISA_ID0 0xc80 tlan.h EISA ID Register 0
24324
 EISA_ID1EISA_ID1 0xc81 tlan.h EISA ID Register 1
24325
 EISA_ID2EISA_ID2 0xc82 tlan.h EISA ID Register 2
24326
 EISA_ID3EISA_ID3 0xc83 tlan.h EISA ID Register 3
24327
 EISA_CREISA_CR 0xc84 tlan.h EISA Control Register
24328
 EISA_REG0EISA_REG0 0xc88 tlan.h EISA Configuration Register 0
24329
 EISA_REG1EISA_REG1 0xc89 tlan.h EISA Configuration Register 1
24330
 EISA_REG2EISA_REG2 0xc8a tlan.h EISA Configuration Register 2
24331
 EISA_REG3EISA_REG3 0xc8f tlan.h EISA Configuration Register 3
24332
 EISA_APROMEISA_APROM 0xc90 tlan.h Ethernet Address PROM
24333
 TLAN_BUFFERS_PER_LISTTLAN_BUFFERS_PER_LIST 10 tlan.h 　
24334
 TLAN_LAST_BUFFERTLAN_LAST_BUFFER 0x80000000 tlan.h 　
24335
 TLAN_CSTAT_UNUSEDTLAN_CSTAT_UNUSED 0x8000 tlan.h 　
24336
 TLAN_CSTAT_FRM_CMPTLAN_CSTAT_FRM_CMP 0x4000 tlan.h 　
24337
 TLAN_CSTAT_READYTLAN_CSTAT_READY 0x3000 tlan.h 　
24338
 TLAN_CSTAT_EOCTLAN_CSTAT_EOC 0x0800 tlan.h 　
24339
 TLAN_CSTAT_RX_ERRORTLAN_CSTAT_RX_ERROR 0x0400 tlan.h 　
24340
 TLAN_CSTAT_PASS_CRCTLAN_CSTAT_PASS_CRC 0x0200 tlan.h 　
24341
 TLAN_CSTAT_DP_PRTLAN_CSTAT_DP_PR 0x0100 tlan.h 　
24342
 TLAN_PHY_MAX_ADDRTLAN_PHY_MAX_ADDR 0x1F tlan.h 　
24343
 TLAN_PHY_NONETLAN_PHY_NONE 0x20 tlan.h 　
24344
 TLAN_TIMER_LINK_BEATTLAN_TIMER_LINK_BEAT 1 tlan.h 　
24345
 TLAN_TIMER_ACTIVITYTLAN_TIMER_ACTIVITY 2 tlan.h 　
24346
 TLAN_TIMER_PHY_PDOWNTLAN_TIMER_PHY_PDOWN 3 tlan.h 　
24347
 TLAN_TIMER_PHY_PUPTLAN_TIMER_PHY_PUP 4 tlan.h 　
24348
 TLAN_TIMER_PHY_RESETTLAN_TIMER_PHY_RESET 5 tlan.h 　
24349
 TLAN_TIMER_PHY_START_LINKTLAN_TIMER_PHY_START_LINK 6 tlan.h 　
24350
 TLAN_TIMER_PHY_FINISH_ANTLAN_TIMER_PHY_FINISH_AN 7 tlan.h 　
24351
 TLAN_TIMER_FINISH_RESETTLAN_TIMER_FINISH_RESET 8 tlan.h 　
24352
 TLAN_TIMER_ACT_DELAYTLAN_TIMER_ACT_DELAY (HZ/10) tlan.h 　
24353
 TLAN_EEPROM_ACKTLAN_EEPROM_ACK 0 tlan.h 　
24354
 TLAN_EEPROM_STOPTLAN_EEPROM_STOP 1 tlan.h 　
24355
 TLAN_HOST_CMDTLAN_HOST_CMD 0x00 tlan.h 　
24356
 TLAN_HC_GOTLAN_HC_GO 0x80000000 tlan.h 　
24357
 TLAN_HC_STOPTLAN_HC_STOP 0x40000000 tlan.h 　
24358
 TLAN_HC_ACKTLAN_HC_ACK 0x20000000 tlan.h 　
24359
 TLAN_HC_CS_MASKTLAN_HC_CS_MASK 0x1FE00000 tlan.h 　
24360
 TLAN_HC_EOCTLAN_HC_EOC 0x00100000 tlan.h 　
24361
 TLAN_HC_RTTLAN_HC_RT 0x00080000 tlan.h 　
24362
 TLAN_HC_NESTLAN_HC_NES 0x00040000 tlan.h 　
24363
 TLAN_HC_AD_RSTTLAN_HC_AD_RST 0x00008000 tlan.h 　
24364
 TLAN_HC_LD_TMRTLAN_HC_LD_TMR 0x00004000 tlan.h 　
24365
 TLAN_HC_LD_THRTLAN_HC_LD_THR 0x00002000 tlan.h 　
24366
 TLAN_HC_REQ_INTTLAN_HC_REQ_INT 0x00001000 tlan.h 　
24367
 TLAN_HC_INT_OFFTLAN_HC_INT_OFF 0x00000800 tlan.h 　
24368
 TLAN_HC_INT_ONTLAN_HC_INT_ON 0x00000400 tlan.h 　
24369
 TLAN_HC_AC_MASKTLAN_HC_AC_MASK 0x000000FF tlan.h 　
24370
 TLAN_CH_PARMTLAN_CH_PARM 0x04 tlan.h 　
24371
 TLAN_DIO_ADRTLAN_DIO_ADR 0x08 tlan.h 　
24372
 TLAN_DA_ADR_INCTLAN_DA_ADR_INC 0x8000 tlan.h 　
24373
 TLAN_DA_RAM_ADRTLAN_DA_RAM_ADR 0x4000 tlan.h 　
24374
 TLAN_HOST_INTTLAN_HOST_INT 0x0A tlan.h 　
24375
 TLAN_HI_IV_MASKTLAN_HI_IV_MASK 0x1FE0 tlan.h 　
24376
 TLAN_HI_IT_MASKTLAN_HI_IT_MASK 0x001C tlan.h 　
24377
 TLAN_DIO_DATATLAN_DIO_DATA 0x0C tlan.h 　
24378
 TLAN_NET_CMDTLAN_NET_CMD 0x00 tlan.h 　
24379
 TLAN_NET_CMD_NRESETTLAN_NET_CMD_NRESET 0x80 tlan.h 　
24380
 TLAN_NET_CMD_NWRAPTLAN_NET_CMD_NWRAP 0x40 tlan.h 　
24381
 TLAN_NET_CMD_CSFTLAN_NET_CMD_CSF 0x20 tlan.h 　
24382
 TLAN_NET_CMD_CAFTLAN_NET_CMD_CAF 0x10 tlan.h 　
24383
 TLAN_NET_CMD_NOBRXTLAN_NET_CMD_NOBRX 0x08 tlan.h 　
24384
 TLAN_NET_CMD_DUPLEXTLAN_NET_CMD_DUPLEX 0x04 tlan.h 　
24385
 TLAN_NET_CMD_TRFRAMTLAN_NET_CMD_TRFRAM 0x02 tlan.h 　
24386
 TLAN_NET_CMD_TXPACETLAN_NET_CMD_TXPACE 0x01 tlan.h 　
24387
 TLAN_NET_SIOTLAN_NET_SIO 0x01 tlan.h 　
24388
 TLAN_NET_SIO_MINTENTLAN_NET_SIO_MINTEN 0x80 tlan.h 　
24389
 TLAN_NET_SIO_ECLOKTLAN_NET_SIO_ECLOK 0x40 tlan.h 　
24390
 TLAN_NET_SIO_ETXENTLAN_NET_SIO_ETXEN 0x20 tlan.h 　
24391
 TLAN_NET_SIO_EDATATLAN_NET_SIO_EDATA 0x10 tlan.h 　
24392
 TLAN_NET_SIO_NMRSTTLAN_NET_SIO_NMRST 0x08 tlan.h 　
24393
 TLAN_NET_SIO_MCLKTLAN_NET_SIO_MCLK 0x04 tlan.h 　
24394
 TLAN_NET_SIO_MTXENTLAN_NET_SIO_MTXEN 0x02 tlan.h 　
24395
 TLAN_NET_SIO_MDATATLAN_NET_SIO_MDATA 0x01 tlan.h 　
24396
 TLAN_NET_STSTLAN_NET_STS 0x02 tlan.h 　
24397
 TLAN_NET_STS_MIRQTLAN_NET_STS_MIRQ 0x80 tlan.h 　
24398
 TLAN_NET_STS_HBEATTLAN_NET_STS_HBEAT 0x40 tlan.h 　
24399
 TLAN_NET_STS_TXSTOPTLAN_NET_STS_TXSTOP 0x20 tlan.h 　
24400
 TLAN_NET_STS_RXSTOPTLAN_NET_STS_RXSTOP 0x10 tlan.h 　
24401
 TLAN_NET_STS_RSRVDTLAN_NET_STS_RSRVD 0x0F tlan.h 　
24402
 TLAN_NET_MASKTLAN_NET_MASK 0x03 tlan.h 　
24403
 TLAN_NET_MASK_MASK7TLAN_NET_MASK_MASK7 0x80 tlan.h 　
24404
 TLAN_NET_MASK_MASK6TLAN_NET_MASK_MASK6 0x40 tlan.h 　
24405
 TLAN_NET_MASK_MASK5TLAN_NET_MASK_MASK5 0x20 tlan.h 　
24406
 TLAN_NET_MASK_MASK4TLAN_NET_MASK_MASK4 0x10 tlan.h 　
24407
 TLAN_NET_MASK_RSRVDTLAN_NET_MASK_RSRVD 0x0F tlan.h 　
24408
 TLAN_NET_CONFIGTLAN_NET_CONFIG 0x04 tlan.h 　
24409
 TLAN_NET_CFG_RCLKTLAN_NET_CFG_RCLK 0x8000 tlan.h 　
24410
 TLAN_NET_CFG_TCLKTLAN_NET_CFG_TCLK 0x4000 tlan.h 　
24411
 TLAN_NET_CFG_BITTLAN_NET_CFG_BIT 0x2000 tlan.h 　
24412
 TLAN_NET_CFG_RXCRCTLAN_NET_CFG_RXCRC 0x1000 tlan.h 　
24413
 TLAN_NET_CFG_PEFTLAN_NET_CFG_PEF 0x0800 tlan.h 　
24414
 TLAN_NET_CFG_1FRAGTLAN_NET_CFG_1FRAG 0x0400 tlan.h 　
24415
 TLAN_NET_CFG_1CHANTLAN_NET_CFG_1CHAN 0x0200 tlan.h 　
24416
 TLAN_NET_CFG_MTESTTLAN_NET_CFG_MTEST 0x0100 tlan.h 　
24417
 TLAN_NET_CFG_PHY_ENTLAN_NET_CFG_PHY_EN 0x0080 tlan.h 　
24418
 TLAN_NET_CFG_MSMASKTLAN_NET_CFG_MSMASK 0x007F tlan.h 　
24419
 TLAN_MAN_TESTTLAN_MAN_TEST 0x06 tlan.h 　
24420
 TLAN_DEF_VENDOR_IDTLAN_DEF_VENDOR_ID 0x08 tlan.h 　
24421
 TLAN_DEF_DEVICE_IDTLAN_DEF_DEVICE_ID 0x0A tlan.h 　
24422
 TLAN_DEF_REVISIONTLAN_DEF_REVISION 0x0C tlan.h 　
24423
 TLAN_DEF_SUBCLASSTLAN_DEF_SUBCLASS 0x0D tlan.h 　
24424
 TLAN_DEF_MIN_LATTLAN_DEF_MIN_LAT 0x0E tlan.h 　
24425
 TLAN_DEF_MAX_LATTLAN_DEF_MAX_LAT 0x0F tlan.h 　
24426
 TLAN_AREG_0TLAN_AREG_0 0x10 tlan.h 　
24427
 TLAN_AREG_1TLAN_AREG_1 0x16 tlan.h 　
24428
 TLAN_AREG_2TLAN_AREG_2 0x1C tlan.h 　
24429
 TLAN_AREG_3TLAN_AREG_3 0x22 tlan.h 　
24430
 TLAN_HASH_1TLAN_HASH_1 0x28 tlan.h 　
24431
 TLAN_HASH_2TLAN_HASH_2 0x2C tlan.h 　
24432
 TLAN_GOOD_TX_FRMSTLAN_GOOD_TX_FRMS 0x30 tlan.h 　
24433
 TLAN_TX_UNDERUNSTLAN_TX_UNDERUNS 0x33 tlan.h 　
24434
 TLAN_GOOD_RX_FRMSTLAN_GOOD_RX_FRMS 0x34 tlan.h 　
24435
 TLAN_RX_OVERRUNSTLAN_RX_OVERRUNS 0x37 tlan.h 　
24436
 TLAN_DEFERRED_TXTLAN_DEFERRED_TX 0x38 tlan.h 　
24437
 TLAN_CRC_ERRORSTLAN_CRC_ERRORS 0x3A tlan.h 　
24438
 TLAN_CODE_ERRORSTLAN_CODE_ERRORS 0x3B tlan.h 　
24439
 TLAN_MULTICOL_FRMSTLAN_MULTICOL_FRMS 0x3C tlan.h 　
24440
 TLAN_SINGLECOL_FRMSTLAN_SINGLECOL_FRMS 0x3E tlan.h 　
24441
 TLAN_EXCESSCOL_FRMSTLAN_EXCESSCOL_FRMS 0x40 tlan.h 　
24442
 TLAN_LATE_COLSTLAN_LATE_COLS 0x41 tlan.h 　
24443
 TLAN_CARRIER_LOSSTLAN_CARRIER_LOSS 0x42 tlan.h 　
24444
 TLAN_ACOMMITTLAN_ACOMMIT 0x43 tlan.h 　
24445
 TLAN_LED_REGTLAN_LED_REG 0x44 tlan.h 　
24446
 TLAN_LED_ACTTLAN_LED_ACT 0x10 tlan.h 　
24447
 TLAN_LED_LINKTLAN_LED_LINK 0x01 tlan.h 　
24448
 TLAN_BSIZE_REGTLAN_BSIZE_REG 0x45 tlan.h 　
24449
 TLAN_MAX_RXTLAN_MAX_RX 0x46 tlan.h 　
24450
 TLAN_INT_DISTLAN_INT_DIS 0x48 tlan.h 　
24451
 TLAN_ID_TX_EOCTLAN_ID_TX_EOC 0x04 tlan.h 　
24452
 TLAN_ID_RX_EOFTLAN_ID_RX_EOF 0x02 tlan.h 　
24453
 TLAN_ID_RX_EOCTLAN_ID_RX_EOC 0x01 tlan.h 　
24454
 TLAN_INT_NUMBER_OF_INTSTLAN_INT_NUMBER_OF_INTS 8 tlan.h 　
24455
 TLAN_INT_NONETLAN_INT_NONE 0x0000 tlan.h 　
24456
 TLAN_INT_TX_EOFTLAN_INT_TX_EOF 0x0001 tlan.h 　
24457
 TLAN_INT_STAT_OVERFLOWTLAN_INT_STAT_OVERFLOW 0x0002 tlan.h 　
24458
 TLAN_INT_RX_EOFTLAN_INT_RX_EOF 0x0003 tlan.h 　
24459
 TLAN_INT_DUMMYTLAN_INT_DUMMY 0x0004 tlan.h 　
24460
 TLAN_INT_TX_EOCTLAN_INT_TX_EOC 0x0005 tlan.h 　
24461
 TLAN_INT_STATUS_CHECKTLAN_INT_STATUS_CHECK 0x0006 tlan.h 　
24462
 TLAN_INT_RX_EOCTLAN_INT_RX_EOC 0x0007 tlan.h 　
24463
 TLAN_TLPHY_IDTLAN_TLPHY_ID 0x10 tlan.h 　
24464
 TLAN_TLPHY_CTLTLAN_TLPHY_CTL 0x11 tlan.h 　
24465
 TLAN_TC_IGLINKTLAN_TC_IGLINK 0x8000 tlan.h 　
24466
 TLAN_TC_SWAPOLTLAN_TC_SWAPOL 0x4000 tlan.h 　
24467
 TLAN_TC_AUISELTLAN_TC_AUISEL 0x2000 tlan.h 　
24468
 TLAN_TC_SQEENTLAN_TC_SQEEN 0x1000 tlan.h 　
24469
 TLAN_TC_MTESTTLAN_TC_MTEST 0x0800 tlan.h 　
24470
 TLAN_TC_RESERVEDTLAN_TC_RESERVED 0x07F8 tlan.h 　
24471
 TLAN_TC_NFEWTLAN_TC_NFEW 0x0004 tlan.h 　
24472
 TLAN_TC_INTENTLAN_TC_INTEN 0x0002 tlan.h 　
24473
 TLAN_TC_TINTTLAN_TC_TINT 0x0001 tlan.h 　
24474
 TLAN_TLPHY_STSTLAN_TLPHY_STS 0x12 tlan.h 　
24475
 TLAN_TS_MINTTLAN_TS_MINT 0x8000 tlan.h 　
24476
 TLAN_TS_PHOKTLAN_TS_PHOK 0x4000 tlan.h 　
24477
 TLAN_TS_POLOKTLAN_TS_POLOK 0x2000 tlan.h 　
24478
 TLAN_TS_TPENERGYTLAN_TS_TPENERGY 0x1000 tlan.h 　
24479
 TLAN_TS_RESERVEDTLAN_TS_RESERVED 0x0FFF tlan.h 　
24480
 TLAN_TLPHY_PARTLAN_TLPHY_PAR 0x19 tlan.h 　
24481
 TLAN_PHY_CIM_STATTLAN_PHY_CIM_STAT 0x0020 tlan.h 　
24482
 TLAN_PHY_SPEED_100TLAN_PHY_SPEED_100 0x0040 tlan.h 　
24483
 TLAN_PHY_DUPLEX_FULLTLAN_PHY_DUPLEX_FULL 0x0080 tlan.h 　
24484
 TLAN_PHY_AN_EN_STATTLAN_PHY_AN_EN_STAT 0x0400 tlan.h 　
24485
 NAT_SEM_ID1NAT_SEM_ID1 0x2000 tlan.h 　
24486
 NAT_SEM_ID2NAT_SEM_ID2 0x5C01 tlan.h 　
24487
 LEVEL1_ID1LEVEL1_ID1 0x7810 tlan.h 　
24488
 LEVEL1_ID2LEVEL1_ID2 0x0000 tlan.h 　
24489
 VELOCITY_NAMEVELOCITY_NAME "via-velocity" via-velocity.h 　
24490
 VELOCITY_FULL_DRV_NAMVELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver" via-velocity.h 　
24491
 VELOCITY_VERSIONVELOCITY_VERSION "1.13" via-velocity.h 　
24492
 PKT_BUF_SZPKT_BUF_SZ 1564 via-velocity.h 　
24493
 MAX_UNITSMAX_UNITS 8 via-velocity.h 　
24494
 OPTION_DEFAULTOPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1} via-velocity.h 　
24495
 REV_ID_VT6110REV_ID_VT6110 (0) via-velocity.h 　
24496
 B_OWNED_BY_CHIPB_OWNED_BY_CHIP 1 via-velocity.h 　
24497
 B_OWNED_BY_HOSTB_OWNED_BY_HOST 0 via-velocity.h 　
24498
 RSR_DETAGRSR_DETAG 0x0080 via-velocity.h 　
24499
 RSR_SNTAGRSR_SNTAG 0x0040 via-velocity.h 　
24500
 RSR_RXERRSR_RXER 0x0020 via-velocity.h 　
24501
 RSR_RLRSR_RL 0x0010 via-velocity.h 　
24502
 RSR_CERSR_CE 0x0008 via-velocity.h 　
24503
 RSR_FAERSR_FAE 0x0004 via-velocity.h 　
24504
 RSR_CRCRSR_CRC 0x0002 via-velocity.h 　
24505
 RSR_VIDMRSR_VIDM 0x0001 via-velocity.h 　
24506
 RSR_RXOKRSR_RXOK 0x8000 via-velocity.h rx OK
24507
 RSR_PFTRSR_PFT 0x4000 via-velocity.h Perfect filtering address match
24508
 RSR_MARRSR_MAR 0x2000 via-velocity.h MAC accept multicast address packet
24509
 RSR_BARRSR_BAR 0x1000 via-velocity.h MAC accept broadcast address packet
24510
 RSR_PHYRSR_PHY 0x0800 via-velocity.h MAC accept physical address packet
24511
 RSR_VTAGRSR_VTAG 0x0400 via-velocity.h 802.1p/1q tagging packet indicator
24512
 RSR_STPRSR_STP 0x0200 via-velocity.h start of packet
24513
 RSR_EDPRSR_EDP 0x0100 via-velocity.h end of packet
24514
 RSR1_RXOKRSR1_RXOK 0x80 via-velocity.h rx OK
24515
 RSR1_PFTRSR1_PFT 0x40 via-velocity.h Perfect filtering address match
24516
 RSR1_MARRSR1_MAR 0x20 via-velocity.h MAC accept multicast address packet
24517
 RSR1_BARRSR1_BAR 0x10 via-velocity.h MAC accept broadcast address packet
24518
 RSR1_PHYRSR1_PHY 0x08 via-velocity.h MAC accept physical address packet
24519
 RSR1_VTAGRSR1_VTAG 0x04 via-velocity.h 802.1p/1q tagging packet indicator
24520
 RSR1_STPRSR1_STP 0x02 via-velocity.h start of packet
24521
 RSR1_EDPRSR1_EDP 0x01 via-velocity.h end of packet
24522
 CSM_IPOKCSM_IPOK 0x40 via-velocity.h IP Checkusm validatiaon ok
24523
 CSM_TUPOKCSM_TUPOK 0x20 via-velocity.h TCP/UDP Checkusm validatiaon ok
24524
 CSM_FRAGCSM_FRAG 0x10 via-velocity.h Fragment IP datagram
24525
 CSM_IPKTCSM_IPKT 0x04 via-velocity.h Received an IP packet
24526
 CSM_TCPKTCSM_TCPKT 0x02 via-velocity.h Received a TCP packet
24527
 CSM_UDPKTCSM_UDPKT 0x01 via-velocity.h Received a UDP packet
24528
 TSR0_ABTTSR0_ABT 0x0080 via-velocity.h Tx abort because of excessive collision
24529
 TSR0_OWTTSR0_OWT 0x0040 via-velocity.h Jumbo frame Tx abort
24530
 TSR0_OWCTSR0_OWC 0x0020 via-velocity.h Out of window collision
24531
 TSR0_COLSTSR0_COLS 0x0010 via-velocity.h experience collision in this transmit event
24532
 TSR0_NCR3TSR0_NCR3 0x0008 via-velocity.h collision retry counter[3]
24533
 TSR0_NCR2TSR0_NCR2 0x0004 via-velocity.h collision retry counter[2]
24534
 TSR0_NCR1TSR0_NCR1 0x0002 via-velocity.h collision retry counter[1]
24535
 TSR0_NCR0TSR0_NCR0 0x0001 via-velocity.h collision retry counter[0]
24536
 TSR0_TERRTSR0_TERR 0x8000 via-velocity.h 　
24537
 TSR0_FDXTSR0_FDX 0x4000 via-velocity.h current transaction is serviced by full duplex mode
24538
 TSR0_GMIITSR0_GMII 0x2000 via-velocity.h current transaction is serviced by GMII mode
24539
 TSR0_LNKFLTSR0_LNKFL 0x1000 via-velocity.h packet serviced during link down
24540
 TSR0_SHDNTSR0_SHDN 0x0400 via-velocity.h shutdown case
24541
 TSR0_CRSTSR0_CRS 0x0200 via-velocity.h carrier sense lost
24542
 TSR0_CDHTSR0_CDH 0x0100 via-velocity.h AQE test fail (CD heartbeat)
24543
 TSR1_TERRTSR1_TERR 0x80 via-velocity.h 　
24544
 TSR1_FDXTSR1_FDX 0x40 via-velocity.h current transaction is serviced by full duplex mode
24545
 TSR1_GMIITSR1_GMII 0x20 via-velocity.h current transaction is serviced by GMII mode
24546
 TSR1_LNKFLTSR1_LNKFL 0x10 via-velocity.h packet serviced during link down
24547
 TSR1_SHDNTSR1_SHDN 0x04 via-velocity.h shutdown case
24548
 TSR1_CRSTSR1_CRS 0x02 via-velocity.h carrier sense lost
24549
 TSR1_CDHTSR1_CDH 0x01 via-velocity.h AQE test fail (CD heartbeat)
24550
 TCR0_TICTCR0_TIC 0x80 via-velocity.h assert interrupt immediately while descriptor has been send complete
24551
 TCR0_PICTCR0_PIC 0x40 via-velocity.h priority interrupt request, INA# is issued over adaptive interrupt scheme
24552
 TCR0_VETAGTCR0_VETAG 0x20 via-velocity.h enable VLAN tag
24553
 TCR0_IPCKTCR0_IPCK 0x10 via-velocity.h request IP checksum calculation.
24554
 TCR0_UDPCKTCR0_UDPCK 0x08 via-velocity.h request UDP checksum calculation.
24555
 TCR0_TCPCKTCR0_TCPCK 0x04 via-velocity.h request TCP checksum calculation.
24556
 TCR0_JMBOTCR0_JMBO 0x02 via-velocity.h indicate a jumbo packet in GMAC side
24557
 TCR0_CRCTCR0_CRC 0x01 via-velocity.h disable CRC generation
24558
 TCPLS_NORMALTCPLS_NORMAL 3 via-velocity.h 　
24559
 TCPLS_STARTTCPLS_START 2 via-velocity.h 　
24560
 TCPLS_ENDTCPLS_END 1 via-velocity.h 　
24561
 TCPLS_MEDTCPLS_MED 0 via-velocity.h 　
24562
 CB_RX_BUF_SIZECB_RX_BUF_SIZE 2048UL via-velocity.h max buffer size
24563
 CB_MAX_RD_NUMCB_MAX_RD_NUM 512 via-velocity.h MAX # of RD
24564
 CB_MAX_TD_NUMCB_MAX_TD_NUM 256 via-velocity.h MAX # of TD
24565
 CB_INIT_RD_NUM_3119CB_INIT_RD_NUM_3119 128 via-velocity.h init # of RD, for setup VT3119
24566
 CB_INIT_TD_NUM_3119CB_INIT_TD_NUM_3119 64 via-velocity.h init # of TD, for setup VT3119
24567
 CB_INIT_RD_NUMCB_INIT_RD_NUM 128 via-velocity.h init # of RD, for setup default
24568
 CB_INIT_TD_NUMCB_INIT_TD_NUM 64 via-velocity.h init # of TD, for setup default
24569
 CB_TD_RING_NUMCB_TD_RING_NUM 4 via-velocity.h # of TD rings.
24570
 CB_MAX_SEG_PER_PKTCB_MAX_SEG_PER_PKT 7 via-velocity.h max data seg per packet (Tx)
24571
 CB_MAX_TX_ABORT_RETRYCB_MAX_TX_ABORT_RETRY 3 via-velocity.h 　
24572
 MCAM_SIZEMCAM_SIZE 64 via-velocity.h 　
24573
 VCAM_SIZEVCAM_SIZE 64 via-velocity.h 　
24574
 TX_QUEUE_NOTX_QUEUE_NO 4 via-velocity.h 　
24575
 MAX_HW_MIB_COUNTERMAX_HW_MIB_COUNTER 32 via-velocity.h 　
24576
 VELOCITY_MIN_MTUVELOCITY_MIN_MTU (1514-14) via-velocity.h 　
24577
 VELOCITY_MAX_MTUVELOCITY_MAX_MTU (9000) via-velocity.h 　
24578
 MAC_REG_PARMAC_REG_PAR 0x00 via-velocity.h physical address
24579
 MAC_REG_RCRMAC_REG_RCR 0x06 via-velocity.h 　
24580
 MAC_REG_TCRMAC_REG_TCR 0x07 via-velocity.h 　
24581
 MAC_REG_CR0_SETMAC_REG_CR0_SET 0x08 via-velocity.h 　
24582
 MAC_REG_CR1_SETMAC_REG_CR1_SET 0x09 via-velocity.h 　
24583
 MAC_REG_CR2_SETMAC_REG_CR2_SET 0x0A via-velocity.h 　
24584
 MAC_REG_CR3_SETMAC_REG_CR3_SET 0x0B via-velocity.h 　
24585
 MAC_REG_CR0_CLRMAC_REG_CR0_CLR 0x0C via-velocity.h 　
24586
 MAC_REG_CR1_CLRMAC_REG_CR1_CLR 0x0D via-velocity.h 　
24587
 MAC_REG_CR2_CLRMAC_REG_CR2_CLR 0x0E via-velocity.h 　
24588
 MAC_REG_CR3_CLRMAC_REG_CR3_CLR 0x0F via-velocity.h 　
24589
 MAC_REG_MARMAC_REG_MAR 0x10 via-velocity.h 　
24590
 MAC_REG_CAMMAC_REG_CAM 0x10 via-velocity.h 　
24591
 MAC_REG_DEC_BASE_HIMAC_REG_DEC_BASE_HI 0x18 via-velocity.h 　
24592
 MAC_REG_DBF_BASE_HIMAC_REG_DBF_BASE_HI 0x1C via-velocity.h 　
24593
 MAC_REG_ISR_CTLMAC_REG_ISR_CTL 0x20 via-velocity.h 　
24594
 MAC_REG_ISR_HOTMRMAC_REG_ISR_HOTMR 0x20 via-velocity.h 　
24595
 MAC_REG_ISR_TSUPTHRMAC_REG_ISR_TSUPTHR 0x20 via-velocity.h 　
24596
 MAC_REG_ISR_RSUPTHRMAC_REG_ISR_RSUPTHR 0x20 via-velocity.h 　
24597
 MAC_REG_ISR_CTL1MAC_REG_ISR_CTL1 0x21 via-velocity.h 　
24598
 MAC_REG_TXE_SRMAC_REG_TXE_SR 0x22 via-velocity.h 　
24599
 MAC_REG_RXE_SRMAC_REG_RXE_SR 0x23 via-velocity.h 　
24600
 MAC_REG_ISRMAC_REG_ISR 0x24 via-velocity.h 　
24601
 MAC_REG_ISR0MAC_REG_ISR0 0x24 via-velocity.h 　
24602
 MAC_REG_ISR1MAC_REG_ISR1 0x25 via-velocity.h 　
24603
 MAC_REG_ISR2MAC_REG_ISR2 0x26 via-velocity.h 　
24604
 MAC_REG_ISR3MAC_REG_ISR3 0x27 via-velocity.h 　
24605
 MAC_REG_IMRMAC_REG_IMR 0x28 via-velocity.h 　
24606
 MAC_REG_IMR0MAC_REG_IMR0 0x28 via-velocity.h 　
24607
 MAC_REG_IMR1MAC_REG_IMR1 0x29 via-velocity.h 　
24608
 MAC_REG_IMR2MAC_REG_IMR2 0x2A via-velocity.h 　
24609
 MAC_REG_IMR3MAC_REG_IMR3 0x2B via-velocity.h 　
24610
 MAC_REG_TDCSR_SETMAC_REG_TDCSR_SET 0x30 via-velocity.h 　
24611
 MAC_REG_RDCSR_SETMAC_REG_RDCSR_SET 0x32 via-velocity.h 　
24612
 MAC_REG_TDCSR_CLRMAC_REG_TDCSR_CLR 0x34 via-velocity.h 　
24613
 MAC_REG_RDCSR_CLRMAC_REG_RDCSR_CLR 0x36 via-velocity.h 　
24614
 MAC_REG_RDBASE_LOMAC_REG_RDBASE_LO 0x38 via-velocity.h 　
24615
 MAC_REG_RDINDXMAC_REG_RDINDX 0x3C via-velocity.h 　
24616
 MAC_REG_TDBASE_LOMAC_REG_TDBASE_LO 0x40 via-velocity.h 　
24617
 MAC_REG_RDCSIZEMAC_REG_RDCSIZE 0x50 via-velocity.h 　
24618
 MAC_REG_TDCSIZEMAC_REG_TDCSIZE 0x52 via-velocity.h 　
24619
 MAC_REG_TDINDXMAC_REG_TDINDX 0x54 via-velocity.h 　
24620
 MAC_REG_TDIDX0MAC_REG_TDIDX0 0x54 via-velocity.h 　
24621
 MAC_REG_TDIDX1MAC_REG_TDIDX1 0x56 via-velocity.h 　
24622
 MAC_REG_TDIDX2MAC_REG_TDIDX2 0x58 via-velocity.h 　
24623
 MAC_REG_TDIDX3MAC_REG_TDIDX3 0x5A via-velocity.h 　
24624
 MAC_REG_PAUSE_TIMERMAC_REG_PAUSE_TIMER 0x5C via-velocity.h 　
24625
 MAC_REG_RBRDUMAC_REG_RBRDU 0x5E via-velocity.h 　
24626
 MAC_REG_FIFO_TEST0MAC_REG_FIFO_TEST0 0x60 via-velocity.h 　
24627
 MAC_REG_FIFO_TEST1MAC_REG_FIFO_TEST1 0x64 via-velocity.h 　
24628
 MAC_REG_CAMADDRMAC_REG_CAMADDR 0x68 via-velocity.h 　
24629
 MAC_REG_CAMCRMAC_REG_CAMCR 0x69 via-velocity.h 　
24630
 MAC_REG_GFTESTMAC_REG_GFTEST 0x6A via-velocity.h 　
24631
 MAC_REG_FTSTCMDMAC_REG_FTSTCMD 0x6B via-velocity.h 　
24632
 MAC_REG_MIICFGMAC_REG_MIICFG 0x6C via-velocity.h 　
24633
 MAC_REG_MIISRMAC_REG_MIISR 0x6D via-velocity.h 　
24634
 MAC_REG_PHYSR0MAC_REG_PHYSR0 0x6E via-velocity.h 　
24635
 MAC_REG_PHYSR1MAC_REG_PHYSR1 0x6F via-velocity.h 　
24636
 MAC_REG_MIICRMAC_REG_MIICR 0x70 via-velocity.h 　
24637
 MAC_REG_MIIADRMAC_REG_MIIADR 0x71 via-velocity.h 　
24638
 MAC_REG_MIIDATAMAC_REG_MIIDATA 0x72 via-velocity.h 　
24639
 MAC_REG_SOFT_TIMER0MAC_REG_SOFT_TIMER0 0x74 via-velocity.h 　
24640
 MAC_REG_SOFT_TIMER1MAC_REG_SOFT_TIMER1 0x76 via-velocity.h 　
24641
 MAC_REG_CFGAMAC_REG_CFGA 0x78 via-velocity.h 　
24642
 MAC_REG_CFGBMAC_REG_CFGB 0x79 via-velocity.h 　
24643
 MAC_REG_CFGCMAC_REG_CFGC 0x7A via-velocity.h 　
24644
 MAC_REG_CFGDMAC_REG_CFGD 0x7B via-velocity.h 　
24645
 MAC_REG_DCFG0MAC_REG_DCFG0 0x7C via-velocity.h 　
24646
 MAC_REG_DCFG1MAC_REG_DCFG1 0x7D via-velocity.h 　
24647
 MAC_REG_MCFG0MAC_REG_MCFG0 0x7E via-velocity.h 　
24648
 MAC_REG_MCFG1MAC_REG_MCFG1 0x7F via-velocity.h 　
24649
 MAC_REG_TBISTMAC_REG_TBIST 0x80 via-velocity.h 　
24650
 MAC_REG_RBISTMAC_REG_RBIST 0x81 via-velocity.h 　
24651
 MAC_REG_PMCCMAC_REG_PMCC 0x82 via-velocity.h 　
24652
 MAC_REG_STICKHWMAC_REG_STICKHW 0x83 via-velocity.h 　
24653
 MAC_REG_MIBCRMAC_REG_MIBCR 0x84 via-velocity.h 　
24654
 MAC_REG_EERSVMAC_REG_EERSV 0x85 via-velocity.h 　
24655
 MAC_REG_REVIDMAC_REG_REVID 0x86 via-velocity.h 　
24656
 MAC_REG_MIBREADMAC_REG_MIBREAD 0x88 via-velocity.h 　
24657
 MAC_REG_BPMAMAC_REG_BPMA 0x8C via-velocity.h 　
24658
 MAC_REG_EEWR_DATAMAC_REG_EEWR_DATA 0x8C via-velocity.h 　
24659
 MAC_REG_BPMD_WRMAC_REG_BPMD_WR 0x8F via-velocity.h 　
24660
 MAC_REG_BPCMDMAC_REG_BPCMD 0x90 via-velocity.h 　
24661
 MAC_REG_BPMD_RDMAC_REG_BPMD_RD 0x91 via-velocity.h 　
24662
 MAC_REG_EECHKSUMMAC_REG_EECHKSUM 0x92 via-velocity.h 　
24663
 MAC_REG_EECSRMAC_REG_EECSR 0x93 via-velocity.h 　
24664
 MAC_REG_EERD_DATAMAC_REG_EERD_DATA 0x94 via-velocity.h 　
24665
 MAC_REG_EADDRMAC_REG_EADDR 0x96 via-velocity.h 　
24666
 MAC_REG_EMBCMDMAC_REG_EMBCMD 0x97 via-velocity.h 　
24667
 MAC_REG_JMPSR0MAC_REG_JMPSR0 0x98 via-velocity.h 　
24668
 MAC_REG_JMPSR1MAC_REG_JMPSR1 0x99 via-velocity.h 　
24669
 MAC_REG_JMPSR2MAC_REG_JMPSR2 0x9A via-velocity.h 　
24670
 MAC_REG_JMPSR3MAC_REG_JMPSR3 0x9B via-velocity.h 　
24671
 MAC_REG_CHIPGSRMAC_REG_CHIPGSR 0x9C via-velocity.h 　
24672
 MAC_REG_TESTCFGMAC_REG_TESTCFG 0x9D via-velocity.h 　
24673
 MAC_REG_DEBUGMAC_REG_DEBUG 0x9E via-velocity.h 　
24674
 MAC_REG_CHIPGCRMAC_REG_CHIPGCR 0x9F via-velocity.h 　
24675
 MAC_REG_WOLCR0_SETMAC_REG_WOLCR0_SET 0xA0 via-velocity.h 　
24676
 MAC_REG_WOLCR1_SETMAC_REG_WOLCR1_SET 0xA1 via-velocity.h 　
24677
 MAC_REG_PWCFG_SETMAC_REG_PWCFG_SET 0xA2 via-velocity.h 　
24678
 MAC_REG_WOLCFG_SETMAC_REG_WOLCFG_SET 0xA3 via-velocity.h 　
24679
 MAC_REG_WOLCR0_CLRMAC_REG_WOLCR0_CLR 0xA4 via-velocity.h 　
24680
 MAC_REG_WOLCR1_CLRMAC_REG_WOLCR1_CLR 0xA5 via-velocity.h 　
24681
 MAC_REG_PWCFG_CLRMAC_REG_PWCFG_CLR 0xA6 via-velocity.h 　
24682
 MAC_REG_WOLCFG_CLRMAC_REG_WOLCFG_CLR 0xA7 via-velocity.h 　
24683
 MAC_REG_WOLSR0_SETMAC_REG_WOLSR0_SET 0xA8 via-velocity.h 　
24684
 MAC_REG_WOLSR1_SETMAC_REG_WOLSR1_SET 0xA9 via-velocity.h 　
24685
 MAC_REG_WOLSR0_CLRMAC_REG_WOLSR0_CLR 0xAC via-velocity.h 　
24686
 MAC_REG_WOLSR1_CLRMAC_REG_WOLSR1_CLR 0xAD via-velocity.h 　
24687
 MAC_REG_PATRN_CRC0MAC_REG_PATRN_CRC0 0xB0 via-velocity.h 　
24688
 MAC_REG_PATRN_CRC1MAC_REG_PATRN_CRC1 0xB2 via-velocity.h 　
24689
 MAC_REG_PATRN_CRC2MAC_REG_PATRN_CRC2 0xB4 via-velocity.h 　
24690
 MAC_REG_PATRN_CRC3MAC_REG_PATRN_CRC3 0xB6 via-velocity.h 　
24691
 MAC_REG_PATRN_CRC4MAC_REG_PATRN_CRC4 0xB8 via-velocity.h 　
24692
 MAC_REG_PATRN_CRC5MAC_REG_PATRN_CRC5 0xBA via-velocity.h 　
24693
 MAC_REG_PATRN_CRC6MAC_REG_PATRN_CRC6 0xBC via-velocity.h 　
24694
 MAC_REG_PATRN_CRC7MAC_REG_PATRN_CRC7 0xBE via-velocity.h 　
24695
 MAC_REG_BYTEMSK0_0MAC_REG_BYTEMSK0_0 0xC0 via-velocity.h 　
24696
 MAC_REG_BYTEMSK0_1MAC_REG_BYTEMSK0_1 0xC4 via-velocity.h 　
24697
 MAC_REG_BYTEMSK0_2MAC_REG_BYTEMSK0_2 0xC8 via-velocity.h 　
24698
 MAC_REG_BYTEMSK0_3MAC_REG_BYTEMSK0_3 0xCC via-velocity.h 　
24699
 MAC_REG_BYTEMSK1_0MAC_REG_BYTEMSK1_0 0xD0 via-velocity.h 　
24700
 MAC_REG_BYTEMSK1_1MAC_REG_BYTEMSK1_1 0xD4 via-velocity.h 　
24701
 MAC_REG_BYTEMSK1_2MAC_REG_BYTEMSK1_2 0xD8 via-velocity.h 　
24702
 MAC_REG_BYTEMSK1_3MAC_REG_BYTEMSK1_3 0xDC via-velocity.h 　
24703
 MAC_REG_BYTEMSK2_0MAC_REG_BYTEMSK2_0 0xE0 via-velocity.h 　
24704
 MAC_REG_BYTEMSK2_1MAC_REG_BYTEMSK2_1 0xE4 via-velocity.h 　
24705
 MAC_REG_BYTEMSK2_2MAC_REG_BYTEMSK2_2 0xE8 via-velocity.h 　
24706
 MAC_REG_BYTEMSK2_3MAC_REG_BYTEMSK2_3 0xEC via-velocity.h 　
24707
 MAC_REG_BYTEMSK3_0MAC_REG_BYTEMSK3_0 0xF0 via-velocity.h 　
24708
 MAC_REG_BYTEMSK3_1MAC_REG_BYTEMSK3_1 0xF4 via-velocity.h 　
24709
 MAC_REG_BYTEMSK3_2MAC_REG_BYTEMSK3_2 0xF8 via-velocity.h 　
24710
 MAC_REG_BYTEMSK3_3MAC_REG_BYTEMSK3_3 0xFC via-velocity.h 　
24711
 RCR_ASRCR_AS 0x80 via-velocity.h 　
24712
 RCR_APRCR_AP 0x40 via-velocity.h 　
24713
 RCR_ALRCR_AL 0x20 via-velocity.h 　
24714
 RCR_PROMRCR_PROM 0x10 via-velocity.h 　
24715
 RCR_ABRCR_AB 0x08 via-velocity.h 　
24716
 RCR_AMRCR_AM 0x04 via-velocity.h 　
24717
 RCR_ARRCR_AR 0x02 via-velocity.h 　
24718
 RCR_SEPRCR_SEP 0x01 via-velocity.h 　
24719
 TCR_TB2BDISTCR_TB2BDIS 0x80 via-velocity.h 　
24720
 TCR_COLTMC1TCR_COLTMC1 0x08 via-velocity.h 　
24721
 TCR_COLTMC0TCR_COLTMC0 0x04 via-velocity.h 　
24722
 TCR_LB1TCR_LB1 0x02 via-velocity.h loopback[1]
24723
 TCR_LB0TCR_LB0 0x01 via-velocity.h loopback[0]
24724
 CR0_TXONCR0_TXON 0x00000008UL via-velocity.h 　
24725
 CR0_RXONCR0_RXON 0x00000004UL via-velocity.h 　
24726
 CR0_STOPCR0_STOP 0x00000002UL via-velocity.h stop MAC, default = 1
24727
 CR0_STRTCR0_STRT 0x00000001UL via-velocity.h start MAC
24728
 CR0_SFRSTCR0_SFRST 0x00008000UL via-velocity.h software reset
24729
 CR0_TM1ENCR0_TM1EN 0x00004000UL via-velocity.h 　
24730
 CR0_TM0ENCR0_TM0EN 0x00002000UL via-velocity.h 　
24731
 CR0_DPOLLCR0_DPOLL 0x00000800UL via-velocity.h disable rx/tx auto polling
24732
 CR0_DISAUCR0_DISAU 0x00000100UL via-velocity.h 　
24733
 CR0_XONENCR0_XONEN 0x00800000UL via-velocity.h 　
24734
 CR0_FDXTFCENCR0_FDXTFCEN 0x00400000UL via-velocity.h full-duplex TX flow control enable
24735
 CR0_FDXRFCENCR0_FDXRFCEN 0x00200000UL via-velocity.h full-duplex RX flow control enable
24736
 CR0_HDXFCENCR0_HDXFCEN 0x00100000UL via-velocity.h half-duplex flow control enable
24737
 CR0_XHITH1CR0_XHITH1 0x00080000UL via-velocity.h TX XON high threshold 1
24738
 CR0_XHITH0CR0_XHITH0 0x00040000UL via-velocity.h TX XON high threshold 0
24739
 CR0_XLTH1CR0_XLTH1 0x00020000UL via-velocity.h TX pause frame low threshold 1
24740
 CR0_XLTH0CR0_XLTH0 0x00010000UL via-velocity.h TX pause frame low threshold 0
24741
 CR0_GSPRSTCR0_GSPRST 0x80000000UL via-velocity.h 　
24742
 CR0_FORSRSTCR0_FORSRST 0x40000000UL via-velocity.h 　
24743
 CR0_FPHYRSTCR0_FPHYRST 0x20000000UL via-velocity.h 　
24744
 CR0_DIAGCR0_DIAG 0x10000000UL via-velocity.h 　
24745
 CR0_INTPCTLCR0_INTPCTL 0x04000000UL via-velocity.h 　
24746
 CR0_GINTMSK1CR0_GINTMSK1 0x02000000UL via-velocity.h 　
24747
 CR0_GINTMSK0CR0_GINTMSK0 0x01000000UL via-velocity.h 　
24748
 CR1_SFRSTCR1_SFRST 0x80 via-velocity.h software reset
24749
 CR1_TM1ENCR1_TM1EN 0x40 via-velocity.h 　
24750
 CR1_TM0ENCR1_TM0EN 0x20 via-velocity.h 　
24751
 CR1_DPOLLCR1_DPOLL 0x08 via-velocity.h disable rx/tx auto polling
24752
 CR1_DISAUCR1_DISAU 0x01 via-velocity.h 　
24753
 CR2_XONENCR2_XONEN 0x80 via-velocity.h 　
24754
 CR2_FDXTFCENCR2_FDXTFCEN 0x40 via-velocity.h full-duplex TX flow control enable
24755
 CR2_FDXRFCENCR2_FDXRFCEN 0x20 via-velocity.h full-duplex RX flow control enable
24756
 CR2_HDXFCENCR2_HDXFCEN 0x10 via-velocity.h half-duplex flow control enable
24757
 CR2_XHITH1CR2_XHITH1 0x08 via-velocity.h TX XON high threshold 1
24758
 CR2_XHITH0CR2_XHITH0 0x04 via-velocity.h TX XON high threshold 0
24759
 CR2_XLTH1CR2_XLTH1 0x02 via-velocity.h TX pause frame low threshold 1
24760
 CR2_XLTH0CR2_XLTH0 0x01 via-velocity.h TX pause frame low threshold 0
24761
 CR3_GSPRSTCR3_GSPRST 0x80 via-velocity.h 　
24762
 CR3_FORSRSTCR3_FORSRST 0x40 via-velocity.h 　
24763
 CR3_FPHYRSTCR3_FPHYRST 0x20 via-velocity.h 　
24764
 CR3_DIAGCR3_DIAG 0x10 via-velocity.h 　
24765
 CR3_INTPCTLCR3_INTPCTL 0x04 via-velocity.h 　
24766
 CR3_GINTMSK1CR3_GINTMSK1 0x02 via-velocity.h 　
24767
 CR3_GINTMSK0CR3_GINTMSK0 0x01 via-velocity.h 　
24768
 ISRCTL_UDPINTISRCTL_UDPINT 0x8000 via-velocity.h 　
24769
 ISRCTL_TSUPDISISRCTL_TSUPDIS 0x4000 via-velocity.h 　
24770
 ISRCTL_RSUPDISISRCTL_RSUPDIS 0x2000 via-velocity.h 　
24771
 ISRCTL_PMSK1ISRCTL_PMSK1 0x1000 via-velocity.h 　
24772
 ISRCTL_PMSK0ISRCTL_PMSK0 0x0800 via-velocity.h 　
24773
 ISRCTL_INTPDISRCTL_INTPD 0x0400 via-velocity.h 　
24774
 ISRCTL_HCRLDISRCTL_HCRLD 0x0200 via-velocity.h 　
24775
 ISRCTL_SCRLDISRCTL_SCRLD 0x0100 via-velocity.h 　
24776
 ISRCTL1_UDPINTISRCTL1_UDPINT 0x80 via-velocity.h 　
24777
 ISRCTL1_TSUPDISISRCTL1_TSUPDIS 0x40 via-velocity.h 　
24778
 ISRCTL1_RSUPDISISRCTL1_RSUPDIS 0x20 via-velocity.h 　
24779
 ISRCTL1_PMSK1ISRCTL1_PMSK1 0x10 via-velocity.h 　
24780
 ISRCTL1_PMSK0ISRCTL1_PMSK0 0x08 via-velocity.h 　
24781
 ISRCTL1_INTPDISRCTL1_INTPD 0x04 via-velocity.h 　
24782
 ISRCTL1_HCRLDISRCTL1_HCRLD 0x02 via-velocity.h 　
24783
 ISRCTL1_SCRLDISRCTL1_SCRLD 0x01 via-velocity.h 　
24784
 TXESR_TFDBSTXESR_TFDBS 0x08 via-velocity.h 　
24785
 TXESR_TDWBSTXESR_TDWBS 0x04 via-velocity.h 　
24786
 TXESR_TDRBSTXESR_TDRBS 0x02 via-velocity.h 　
24787
 TXESR_TDSTRTXESR_TDSTR 0x01 via-velocity.h 　
24788
 RXESR_RFDBSRXESR_RFDBS 0x08 via-velocity.h 　
24789
 RXESR_RDWBSRXESR_RDWBS 0x04 via-velocity.h 　
24790
 RXESR_RDRBSRXESR_RDRBS 0x02 via-velocity.h 　
24791
 RXESR_RDSTRRXESR_RDSTR 0x01 via-velocity.h 　
24792
 ISR_ISR3ISR_ISR3 0x80000000UL via-velocity.h 　
24793
 ISR_ISR2ISR_ISR2 0x40000000UL via-velocity.h 　
24794
 ISR_ISR1ISR_ISR1 0x20000000UL via-velocity.h 　
24795
 ISR_ISR0ISR_ISR0 0x10000000UL via-velocity.h 　
24796
 ISR_TXSTLIISR_TXSTLI 0x02000000UL via-velocity.h 　
24797
 ISR_RXSTLIISR_RXSTLI 0x01000000UL via-velocity.h 　
24798
 ISR_HFLDISR_HFLD 0x00800000UL via-velocity.h 　
24799
 ISR_UDPIISR_UDPI 0x00400000UL via-velocity.h 　
24800
 ISR_MIBFIISR_MIBFI 0x00200000UL via-velocity.h 　
24801
 ISR_SHDNIISR_SHDNI 0x00100000UL via-velocity.h 　
24802
 ISR_PHYIISR_PHYI 0x00080000UL via-velocity.h 　
24803
 ISR_PWEIISR_PWEI 0x00040000UL via-velocity.h 　
24804
 ISR_TMR1IISR_TMR1I 0x00020000UL via-velocity.h 　
24805
 ISR_TMR0IISR_TMR0I 0x00010000UL via-velocity.h 　
24806
 ISR_SRCIISR_SRCI 0x00008000UL via-velocity.h 　
24807
 ISR_LSTPEIISR_LSTPEI 0x00004000UL via-velocity.h 　
24808
 ISR_LSTEIISR_LSTEI 0x00002000UL via-velocity.h 　
24809
 ISR_OVFIISR_OVFI 0x00001000UL via-velocity.h 　
24810
 ISR_FLONIISR_FLONI 0x00000800UL via-velocity.h 　
24811
 ISR_RACEIISR_RACEI 0x00000400UL via-velocity.h 　
24812
 ISR_TXWB1IISR_TXWB1I 0x00000200UL via-velocity.h 　
24813
 ISR_TXWB0IISR_TXWB0I 0x00000100UL via-velocity.h 　
24814
 ISR_PTX3IISR_PTX3I 0x00000080UL via-velocity.h 　
24815
 ISR_PTX2IISR_PTX2I 0x00000040UL via-velocity.h 　
24816
 ISR_PTX1IISR_PTX1I 0x00000020UL via-velocity.h 　
24817
 ISR_PTX0IISR_PTX0I 0x00000010UL via-velocity.h 　
24818
 ISR_PTXIISR_PTXI 0x00000008UL via-velocity.h 　
24819
 ISR_PRXIISR_PRXI 0x00000004UL via-velocity.h 　
24820
 ISR_PPTXIISR_PPTXI 0x00000002UL via-velocity.h 　
24821
 ISR_PPRXIISR_PPRXI 0x00000001UL via-velocity.h 　
24822
 IMR_TXSTLMIMR_TXSTLM 0x02000000UL via-velocity.h 　
24823
 IMR_UDPIMIMR_UDPIM 0x00400000UL via-velocity.h 　
24824
 IMR_MIBFIMIMR_MIBFIM 0x00200000UL via-velocity.h 　
24825
 IMR_SHDNIMIMR_SHDNIM 0x00100000UL via-velocity.h 　
24826
 IMR_PHYIMIMR_PHYIM 0x00080000UL via-velocity.h 　
24827
 IMR_PWEIMIMR_PWEIM 0x00040000UL via-velocity.h 　
24828
 IMR_TMR1IMIMR_TMR1IM 0x00020000UL via-velocity.h 　
24829
 IMR_TMR0IMIMR_TMR0IM 0x00010000UL via-velocity.h 　
24830
 IMR_SRCIMIMR_SRCIM 0x00008000UL via-velocity.h 　
24831
 IMR_LSTPEIMIMR_LSTPEIM 0x00004000UL via-velocity.h 　
24832
 IMR_LSTEIMIMR_LSTEIM 0x00002000UL via-velocity.h 　
24833
 IMR_OVFIMIMR_OVFIM 0x00001000UL via-velocity.h 　
24834
 IMR_FLONIMIMR_FLONIM 0x00000800UL via-velocity.h 　
24835
 IMR_RACEIMIMR_RACEIM 0x00000400UL via-velocity.h 　
24836
 IMR_TXWB1IMIMR_TXWB1IM 0x00000200UL via-velocity.h 　
24837
 IMR_TXWB0IMIMR_TXWB0IM 0x00000100UL via-velocity.h 　
24838
 IMR_PTX3IMIMR_PTX3IM 0x00000080UL via-velocity.h 　
24839
 IMR_PTX2IMIMR_PTX2IM 0x00000040UL via-velocity.h 　
24840
 IMR_PTX1IMIMR_PTX1IM 0x00000020UL via-velocity.h 　
24841
 IMR_PTX0IMIMR_PTX0IM 0x00000010UL via-velocity.h 　
24842
 IMR_PTXIMIMR_PTXIM 0x00000008UL via-velocity.h 　
24843
 IMR_PRXIMIMR_PRXIM 0x00000004UL via-velocity.h 　
24844
 IMR_PPTXIMIMR_PPTXIM 0x00000002UL via-velocity.h 　
24845
 IMR_PPRXIMIMR_PPRXIM 0x00000001UL via-velocity.h 　
24846
 INT_MASK_DEFINT_MASK_DEF ( IMR_PPTXIM|IMR_PPRXIM| IMR_PTXIM|IMR_PRXIM | \ IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM| \ IMR_OVFIM|IMR_LSTEIM|IMR_LSTP via-velocity.h 　
24847
 TRDCSR_DEADTRDCSR_DEAD 0x0008 via-velocity.h 　
24848
 TRDCSR_WAKTRDCSR_WAK 0x0004 via-velocity.h 　
24849
 TRDCSR_ACTTRDCSR_ACT 0x0002 via-velocity.h 　
24850
 TRDCSR_RUNTRDCSR_RUN 0x0001 via-velocity.h 　
24851
 CAMADDR_CAMENCAMADDR_CAMEN 0x80 via-velocity.h 　
24852
 CAMADDR_VCAMSLCAMADDR_VCAMSL 0x40 via-velocity.h 　
24853
 CAMCR_PS1CAMCR_PS1 0x80 via-velocity.h 　
24854
 CAMCR_PS0CAMCR_PS0 0x40 via-velocity.h 　
24855
 CAMCR_AITRPKTCAMCR_AITRPKT 0x20 via-velocity.h 　
24856
 CAMCR_AITR16CAMCR_AITR16 0x10 via-velocity.h 　
24857
 CAMCR_CAMRDCAMCR_CAMRD 0x08 via-velocity.h 　
24858
 CAMCR_CAMWRCAMCR_CAMWR 0x04 via-velocity.h 　
24859
 CAMCR_PS_CAM_MASKCAMCR_PS_CAM_MASK 0x40 via-velocity.h 　
24860
 CAMCR_PS_CAM_DATACAMCR_PS_CAM_DATA 0x80 via-velocity.h 　
24861
 CAMCR_PS_MARCAMCR_PS_MAR 0x00 via-velocity.h 　
24862
 MIICFG_MPO1MIICFG_MPO1 0x80 via-velocity.h 　
24863
 MIICFG_MPO0MIICFG_MPO0 0x40 via-velocity.h 　
24864
 MIICFG_MFDCMIICFG_MFDC 0x20 via-velocity.h 　
24865
 MIISR_MIDLEMIISR_MIDLE 0x80 via-velocity.h 　
24866
 PHYSR0_PHYRSTPHYSR0_PHYRST 0x80 via-velocity.h 　
24867
 PHYSR0_LINKGDPHYSR0_LINKGD 0x40 via-velocity.h 　
24868
 PHYSR0_FDPXPHYSR0_FDPX 0x10 via-velocity.h 　
24869
 PHYSR0_SPDGPHYSR0_SPDG 0x08 via-velocity.h 　
24870
 PHYSR0_SPD10PHYSR0_SPD10 0x04 via-velocity.h 　
24871
 PHYSR0_RXFLCPHYSR0_RXFLC 0x02 via-velocity.h 　
24872
 PHYSR0_TXFLCPHYSR0_TXFLC 0x01 via-velocity.h 　
24873
 PHYSR1_PHYTBIPHYSR1_PHYTBI 0x01 via-velocity.h 　
24874
 MIICR_MAUTOMIICR_MAUTO 0x80 via-velocity.h 　
24875
 MIICR_RCMDMIICR_RCMD 0x40 via-velocity.h 　
24876
 MIICR_WCMDMIICR_WCMD 0x20 via-velocity.h 　
24877
 MIICR_MDPMMIICR_MDPM 0x10 via-velocity.h 　
24878
 MIICR_MOUTMIICR_MOUT 0x08 via-velocity.h 　
24879
 MIICR_MDOMIICR_MDO 0x04 via-velocity.h 　
24880
 MIICR_MDIMIICR_MDI 0x02 via-velocity.h 　
24881
 MIICR_MDCMIICR_MDC 0x01 via-velocity.h 　
24882
 MIIADR_SWMPLMIIADR_SWMPL 0x80 via-velocity.h 　
24883
 CFGA_PMHCTGCFGA_PMHCTG 0x08 via-velocity.h 　
24884
 CFGA_GPIO1PDCFGA_GPIO1PD 0x04 via-velocity.h 　
24885
 CFGA_ABSHDNCFGA_ABSHDN 0x02 via-velocity.h 　
24886
 CFGA_PACPICFGA_PACPI 0x01 via-velocity.h 　
24887
 CFGB_GTCKOPTCFGB_GTCKOPT 0x80 via-velocity.h 　
24888
 CFGB_MIIOPTCFGB_MIIOPT 0x40 via-velocity.h 　
24889
 CFGB_CRSEOPTCFGB_CRSEOPT 0x20 via-velocity.h 　
24890
 CFGB_OFSETCFGB_OFSET 0x10 via-velocity.h 　
24891
 CFGB_CRANDOMCFGB_CRANDOM 0x08 via-velocity.h 　
24892
 CFGB_CAPCFGB_CAP 0x04 via-velocity.h 　
24893
 CFGB_MBACFGB_MBA 0x02 via-velocity.h 　
24894
 CFGB_BAKOPTCFGB_BAKOPT 0x01 via-velocity.h 　
24895
 CFGC_EELOADCFGC_EELOAD 0x80 via-velocity.h 　
24896
 CFGC_BROPTCFGC_BROPT 0x40 via-velocity.h 　
24897
 CFGC_DLYENCFGC_DLYEN 0x20 via-velocity.h 　
24898
 CFGC_DTSELCFGC_DTSEL 0x10 via-velocity.h 　
24899
 CFGC_BTSELCFGC_BTSEL 0x08 via-velocity.h 　
24900
 CFGC_BPS2CFGC_BPS2 0x04 via-velocity.h bootrom select[2]
24901
 CFGC_BPS1CFGC_BPS1 0x02 via-velocity.h bootrom select[1]
24902
 CFGC_BPS0CFGC_BPS0 0x01 via-velocity.h bootrom select[0]
24903
 CFGD_IODISCFGD_IODIS 0x80 via-velocity.h 　
24904
 CFGD_MSLVDACENCFGD_MSLVDACEN 0x40 via-velocity.h 　
24905
 CFGD_CFGDACENCFGD_CFGDACEN 0x20 via-velocity.h 　
24906
 CFGD_PCI64ENCFGD_PCI64EN 0x10 via-velocity.h 　
24907
 CFGD_HTMRL4CFGD_HTMRL4 0x08 via-velocity.h 　
24908
 DCFG_XMWIDCFG_XMWI 0x8000 via-velocity.h 　
24909
 DCFG_XMRMDCFG_XMRM 0x4000 via-velocity.h 　
24910
 DCFG_XMRLDCFG_XMRL 0x2000 via-velocity.h 　
24911
 DCFG_PERDISDCFG_PERDIS 0x1000 via-velocity.h 　
24912
 DCFG_MRWAITDCFG_MRWAIT 0x0400 via-velocity.h 　
24913
 DCFG_MWWAITDCFG_MWWAIT 0x0200 via-velocity.h 　
24914
 DCFG_LATMENDCFG_LATMEN 0x0100 via-velocity.h 　
24915
 MCFG_RXARBMCFG_RXARB 0x0080 via-velocity.h 　
24916
 MCFG_RFT1MCFG_RFT1 0x0020 via-velocity.h 　
24917
 MCFG_RFT0MCFG_RFT0 0x0010 via-velocity.h 　
24918
 MCFG_LOWTHOPTMCFG_LOWTHOPT 0x0008 via-velocity.h 　
24919
 MCFG_PQENMCFG_PQEN 0x0004 via-velocity.h 　
24920
 MCFG_RTGOPTMCFG_RTGOPT 0x0002 via-velocity.h 　
24921
 MCFG_VIDFRMCFG_VIDFR 0x0001 via-velocity.h 　
24922
 MCFG_TXARBMCFG_TXARB 0x8000 via-velocity.h 　
24923
 MCFG_TXQBK1MCFG_TXQBK1 0x0800 via-velocity.h 　
24924
 MCFG_TXQBK0MCFG_TXQBK0 0x0400 via-velocity.h 　
24925
 MCFG_TXQNOBKMCFG_TXQNOBK 0x0200 via-velocity.h 　
24926
 MCFG_SNAPOPTMCFG_SNAPOPT 0x0100 via-velocity.h 　
24927
 PMCC_DSIPMCC_DSI 0x80 via-velocity.h 　
24928
 PMCC_D2_DISPMCC_D2_DIS 0x40 via-velocity.h 　
24929
 PMCC_D1_DISPMCC_D1_DIS 0x20 via-velocity.h 　
24930
 PMCC_D3C_ENPMCC_D3C_EN 0x10 via-velocity.h 　
24931
 PMCC_D3H_ENPMCC_D3H_EN 0x08 via-velocity.h 　
24932
 PMCC_D2_ENPMCC_D2_EN 0x04 via-velocity.h 　
24933
 PMCC_D1_ENPMCC_D1_EN 0x02 via-velocity.h 　
24934
 PMCC_D0_ENPMCC_D0_EN 0x01 via-velocity.h 　
24935
 STICKHW_SWPTAGSTICKHW_SWPTAG 0x10 via-velocity.h 　
24936
 STICKHW_WOLSRSTICKHW_WOLSR 0x08 via-velocity.h 　
24937
 STICKHW_WOLENSTICKHW_WOLEN 0x04 via-velocity.h 　
24938
 STICKHW_DS1STICKHW_DS1 0x02 via-velocity.h R/W by software/cfg cycle
24939
 STICKHW_DS0STICKHW_DS0 0x01 via-velocity.h suspend well DS write port
24940
 MIBCR_MIBISTOKMIBCR_MIBISTOK 0x80 via-velocity.h 　
24941
 MIBCR_MIBISTGOMIBCR_MIBISTGO 0x40 via-velocity.h 　
24942
 MIBCR_MIBINCMIBCR_MIBINC 0x20 via-velocity.h 　
24943
 MIBCR_MIBHIMIBCR_MIBHI 0x10 via-velocity.h 　
24944
 MIBCR_MIBFRZMIBCR_MIBFRZ 0x08 via-velocity.h 　
24945
 MIBCR_MIBFLSHMIBCR_MIBFLSH 0x04 via-velocity.h 　
24946
 MIBCR_MPTRINIMIBCR_MPTRINI 0x02 via-velocity.h 　
24947
 MIBCR_MIBCLRMIBCR_MIBCLR 0x01 via-velocity.h 　
24948
 EERSV_BOOT_RPLEERSV_BOOT_RPL ((u8) 0x01) via-velocity.h Boot method selection for VT6110
24949
 EERSV_BOOT_MASKEERSV_BOOT_MASK ((u8) 0x06) via-velocity.h 　
24950
 EERSV_BOOT_INT19EERSV_BOOT_INT19 ((u8) 0x00) via-velocity.h 　
24951
 EERSV_BOOT_INT18EERSV_BOOT_INT18 ((u8) 0x02) via-velocity.h 　
24952
 EERSV_BOOT_LOCALEERSV_BOOT_LOCAL ((u8) 0x04) via-velocity.h 　
24953
 EERSV_BOOT_BEVEERSV_BOOT_BEV ((u8) 0x06) via-velocity.h 　
24954
 BPCMD_BPDNEBPCMD_BPDNE 0x80 via-velocity.h 　
24955
 BPCMD_EBPWRBPCMD_EBPWR 0x02 via-velocity.h 　
24956
 BPCMD_EBPRDBPCMD_EBPRD 0x01 via-velocity.h 　
24957
 EECSR_EMBPEECSR_EMBP 0x40 via-velocity.h eeprom embeded programming
24958
 EECSR_RELOADEECSR_RELOAD 0x20 via-velocity.h eeprom content reload
24959
 EECSR_DPMEECSR_DPM 0x10 via-velocity.h eeprom direct programming
24960
 EECSR_ECSEECSR_ECS 0x08 via-velocity.h eeprom CS pin
24961
 EECSR_ECKEECSR_ECK 0x04 via-velocity.h eeprom CK pin
24962
 EECSR_EDIEECSR_EDI 0x02 via-velocity.h eeprom DI pin
24963
 EECSR_EDOEECSR_EDO 0x01 via-velocity.h eeprom DO pin
24964
 EMBCMD_EDONEEMBCMD_EDONE 0x80 via-velocity.h 　
24965
 EMBCMD_EWDISEMBCMD_EWDIS 0x08 via-velocity.h 　
24966
 EMBCMD_EWENEMBCMD_EWEN 0x04 via-velocity.h 　
24967
 EMBCMD_EWREMBCMD_EWR 0x02 via-velocity.h 　
24968
 EMBCMD_ERDEMBCMD_ERD 0x01 via-velocity.h 　
24969
 TESTCFG_HBDISTESTCFG_HBDIS 0x80 via-velocity.h 　
24970
 CHIPGCR_FCGMIICHIPGCR_FCGMII 0x80 via-velocity.h 　
24971
 CHIPGCR_FCFDXCHIPGCR_FCFDX 0x40 via-velocity.h 　
24972
 CHIPGCR_FCRESVCHIPGCR_FCRESV 0x20 via-velocity.h 　
24973
 CHIPGCR_FCMODECHIPGCR_FCMODE 0x10 via-velocity.h 　
24974
 CHIPGCR_LPSOPTCHIPGCR_LPSOPT 0x08 via-velocity.h 　
24975
 CHIPGCR_TM1USCHIPGCR_TM1US 0x04 via-velocity.h 　
24976
 CHIPGCR_TM0USCHIPGCR_TM0US 0x02 via-velocity.h 　
24977
 CHIPGCR_PHYINTENCHIPGCR_PHYINTEN 0x01 via-velocity.h 　
24978
 WOLCR_MSWOLEN7WOLCR_MSWOLEN7 0x0080 via-velocity.h enable pattern match filtering
24979
 WOLCR_MSWOLEN6WOLCR_MSWOLEN6 0x0040 via-velocity.h 　
24980
 WOLCR_MSWOLEN5WOLCR_MSWOLEN5 0x0020 via-velocity.h 　
24981
 WOLCR_MSWOLEN4WOLCR_MSWOLEN4 0x0010 via-velocity.h 　
24982
 WOLCR_MSWOLEN3WOLCR_MSWOLEN3 0x0008 via-velocity.h 　
24983
 WOLCR_MSWOLEN2WOLCR_MSWOLEN2 0x0004 via-velocity.h 　
24984
 WOLCR_MSWOLEN1WOLCR_MSWOLEN1 0x0002 via-velocity.h 　
24985
 WOLCR_MSWOLEN0WOLCR_MSWOLEN0 0x0001 via-velocity.h 　
24986
 WOLCR_ARP_ENWOLCR_ARP_EN 0x0001 via-velocity.h 　
24987
 WOLCR_LINKOFF_ENWOLCR_LINKOFF_EN 0x0800 via-velocity.h link off detected enable
24988
 WOLCR_LINKON_ENWOLCR_LINKON_EN 0x0400 via-velocity.h link on detected enable
24989
 WOLCR_MAGIC_ENWOLCR_MAGIC_EN 0x0200 via-velocity.h magic packet filter enable
24990
 WOLCR_UNICAST_ENWOLCR_UNICAST_EN 0x0100 via-velocity.h unicast filter enable
24991
 PWCFG_PHYPWOPTPWCFG_PHYPWOPT 0x80 via-velocity.h internal MII I/F timing
24992
 PWCFG_PCISTICKPWCFG_PCISTICK 0x40 via-velocity.h PCI sticky R/W enable
24993
 PWCFG_WOLTYPEPWCFG_WOLTYPE 0x20 via-velocity.h pulse(1) or button (0)
24994
 PWCFG_LEGCY_WOLPWCFG_LEGCY_WOL 0x10 via-velocity.h 　
24995
 PWCFG_PMCSR_PME_SRPWCFG_PMCSR_PME_SR 0x08 via-velocity.h 　
24996
 PWCFG_PMCSR_PME_ENPWCFG_PMCSR_PME_EN 0x04 via-velocity.h control by PCISTICK
24997
 PWCFG_LEGACY_WOLSRPWCFG_LEGACY_WOLSR 0x02 via-velocity.h Legacy WOL_SR shadow
24998
 PWCFG_LEGACY_WOLENPWCFG_LEGACY_WOLEN 0x01 via-velocity.h Legacy WOL_EN shadow
24999
 WOLCFG_PMEOVRWOLCFG_PMEOVR 0x80 via-velocity.h for legacy use, force PMEEN always
25000
 WOLCFG_SAMWOLCFG_SAM 0x20 via-velocity.h accept multicast case reset, default=0
25001
 WOLCFG_SABWOLCFG_SAB 0x10 via-velocity.h accept broadcast case reset, default=0
25002
 WOLCFG_SMIIACCWOLCFG_SMIIACC 0x08 via-velocity.h ??
25003
 WOLCFG_SGENWHWOLCFG_SGENWH 0x02 via-velocity.h 　
25004
 WOLCFG_PHYINTENWOLCFG_PHYINTEN 0x01 via-velocity.h 0:PHYINT trigger enable, 1:use internal MII
25005
 WOLSR_LINKOFF_INTWOLSR_LINKOFF_INT 0x0800 via-velocity.h 　
25006
 WOLSR_LINKON_INTWOLSR_LINKON_INT 0x0400 via-velocity.h 　
25007
 WOLSR_MAGIC_INTWOLSR_MAGIC_INT 0x0200 via-velocity.h 　
25008
 WOLSR_UNICAST_INTWOLSR_UNICAST_INT 0x0100 via-velocity.h 　
25009
 PKT_TYPE_NONEPKT_TYPE_NONE 0x0000 via-velocity.h Turn off receiver
25010
 PKT_TYPE_DIRECTEDPKT_TYPE_DIRECTED 0x0001 via-velocity.h obselete, directed address is always accepted
25011
 PKT_TYPE_MULTICASTPKT_TYPE_MULTICAST 0x0002 via-velocity.h 　
25012
 PKT_TYPE_ALL_MULTICASTPKT_TYPE_ALL_MULTICAST 0x0004 via-velocity.h 　
25013
 PKT_TYPE_BROADCASTPKT_TYPE_BROADCAST 0x0008 via-velocity.h 　
25014
 PKT_TYPE_PROMISCUOUSPKT_TYPE_PROMISCUOUS 0x0020 via-velocity.h 　
25015
 PKT_TYPE_LONGPKT_TYPE_LONG 0x2000 via-velocity.h NOTE.... the definition of LONG is >2048 bytes in our chip
25016
 PKT_TYPE_RUNTPKT_TYPE_RUNT 0x4000 via-velocity.h 　
25017
 PKT_TYPE_ERRORPKT_TYPE_ERROR 0x8000 via-velocity.h Accept error packets, e.g. CRC error
25018
 MAC_LB_NONEMAC_LB_NONE 0x00 via-velocity.h 　
25019
 MAC_LB_INTERNALMAC_LB_INTERNAL 0x01 via-velocity.h 　
25020
 MAC_LB_EXTERNALMAC_LB_EXTERNAL 0x02 via-velocity.h 　
25021
 IMR_MASK_VALUEIMR_MASK_VALUE 0x0033FF0FUL via-velocity.h initial value of IMR
25022
 IMR_MASK_VALUEIMR_MASK_VALUE 0x0013FB0FUL via-velocity.h initial value of IMR
25023
 REV_ID_VT3119_A0REV_ID_VT3119_A0 0x00 via-velocity.h 　
25024
 REV_ID_VT3119_A1REV_ID_VT3119_A1 0x01 via-velocity.h 　
25025
 REV_ID_VT3216_A0REV_ID_VT3216_A0 0x10 via-velocity.h 　
25026
 W_MAX_TIMEOUTW_MAX_TIMEOUT 0x0FFFU via-velocity.h 　
25027
 MII_REG_BMCRMII_REG_BMCR 0x00 via-velocity.h physical address
25028
 MII_REG_BMSRMII_REG_BMSR 0x01 via-velocity.h 　
25029
 MII_REG_PHYID1MII_REG_PHYID1 0x02 via-velocity.h OUI
25030
 MII_REG_PHYID2MII_REG_PHYID2 0x03 via-velocity.h OUI + Module ID + REV ID
25031
 MII_REG_ANARMII_REG_ANAR 0x04 via-velocity.h 　
25032
 MII_REG_ANLPARMII_REG_ANLPAR 0x05 via-velocity.h 　
25033
 MII_REG_G1000CRMII_REG_G1000CR 0x09 via-velocity.h 　
25034
 MII_REG_G1000SRMII_REG_G1000SR 0x0A via-velocity.h 　
25035
 MII_REG_MODCFGMII_REG_MODCFG 0x10 via-velocity.h 　
25036
 MII_REG_TCSRMII_REG_TCSR 0x16 via-velocity.h 　
25037
 MII_REG_PLEDMII_REG_PLED 0x1B via-velocity.h 　
25038
 MII_REG_PCRMII_REG_PCR 0x17 via-velocity.h 　
25039
 MII_REG_PCSRMII_REG_PCSR 0x17 via-velocity.h 　
25040
 MII_REG_AUXCRMII_REG_AUXCR 0x1C via-velocity.h 　
25041
 MII_REG_PSCRMII_REG_PSCR 0x10 via-velocity.h PHY specific control register
25042
 BMCR_RESETBMCR_RESET 0x8000 via-velocity.h 　
25043
 BMCR_LBKBMCR_LBK 0x4000 via-velocity.h 　
25044
 BMCR_SPEED100BMCR_SPEED100 0x2000 via-velocity.h 　
25045
 BMCR_AUTOBMCR_AUTO 0x1000 via-velocity.h 　
25046
 BMCR_PDBMCR_PD 0x0800 via-velocity.h 　
25047
 BMCR_ISOBMCR_ISO 0x0400 via-velocity.h 　
25048
 BMCR_REAUTOBMCR_REAUTO 0x0200 via-velocity.h 　
25049
 BMCR_FDXBMCR_FDX 0x0100 via-velocity.h 　
25050
 BMCR_SPEED1GBMCR_SPEED1G 0x0040 via-velocity.h 　
25051
 BMSR_AUTOCMBMSR_AUTOCM 0x0020 via-velocity.h 　
25052
 BMSR_LNKBMSR_LNK 0x0004 via-velocity.h 　
25053
 ANAR_ASMDIRANAR_ASMDIR 0x0800 via-velocity.h Asymmetric PAUSE support
25054
 ANAR_PAUSEANAR_PAUSE 0x0400 via-velocity.h Symmetric PAUSE Support
25055
 ANAR_T4ANAR_T4 0x0200 via-velocity.h 　
25056
 ANAR_TXFDANAR_TXFD 0x0100 via-velocity.h 　
25057
 ANAR_TXANAR_TX 0x0080 via-velocity.h 　
25058
 ANAR_10FDANAR_10FD 0x0040 via-velocity.h 　
25059
 ANAR_10ANAR_10 0x0020 via-velocity.h 　
25060
 ANLPAR_ASMDIRANLPAR_ASMDIR 0x0800 via-velocity.h Asymmetric PAUSE support
25061
 ANLPAR_PAUSEANLPAR_PAUSE 0x0400 via-velocity.h Symmetric PAUSE Support
25062
 ANLPAR_T4ANLPAR_T4 0x0200 via-velocity.h 　
25063
 ANLPAR_TXFDANLPAR_TXFD 0x0100 via-velocity.h 　
25064
 ANLPAR_TXANLPAR_TX 0x0080 via-velocity.h 　
25065
 ANLPAR_10FDANLPAR_10FD 0x0040 via-velocity.h 　
25066
 ANLPAR_10ANLPAR_10 0x0020 via-velocity.h 　
25067
 G1000CR_1000FDG1000CR_1000FD 0x0200 via-velocity.h PHY is 1000-T Full-duplex capable
25068
 G1000CR_1000G1000CR_1000 0x0100 via-velocity.h PHY is 1000-T Half-duplex capable
25069
 G1000SR_1000FDG1000SR_1000FD 0x0800 via-velocity.h LP PHY is 1000-T Full-duplex capable
25070
 G1000SR_1000G1000SR_1000 0x0400 via-velocity.h LP PHY is 1000-T Half-duplex capable
25071
 TCSR_ECHODISTCSR_ECHODIS 0x2000 via-velocity.h 　
25072
 AUXCR_MDPPSAUXCR_MDPPS 0x0004 via-velocity.h 　
25073
 PLED_LALBEPLED_LALBE 0x0004 via-velocity.h 　
25074
 PSCR_ACRSTXPSCR_ACRSTX 0x0800 via-velocity.h Assert CRS on Transmit
25075
 PHYID_CICADA_CS8201PHYID_CICADA_CS8201 0x000FC410UL via-velocity.h 　
25076
 PHYID_VT3216_32BITPHYID_VT3216_32BIT 0x000FC610UL via-velocity.h 　
25077
 PHYID_VT3216_64BITPHYID_VT3216_64BIT 0x000FC600UL via-velocity.h 　
25078
 PHYID_MARVELL_1000PHYID_MARVELL_1000 0x01410C50UL via-velocity.h 　
25079
 PHYID_MARVELL_1000SPHYID_MARVELL_1000S 0x01410C40UL via-velocity.h 　
25080
 PHYID_REV_ID_MASKPHYID_REV_ID_MASK 0x0000000FUL via-velocity.h 　
25081
 VELOCITY_WOL_MAGICVELOCITY_WOL_MAGIC 0x00000000UL via-velocity.h 　
25082
 VELOCITY_WOL_PHYVELOCITY_WOL_PHY 0x00000001UL via-velocity.h 　
25083
 VELOCITY_WOL_ARPVELOCITY_WOL_ARP 0x00000002UL via-velocity.h 　
25084
 VELOCITY_WOL_UCASTVELOCITY_WOL_UCAST 0x00000004UL via-velocity.h 　
25085
 VELOCITY_WOL_BCASTVELOCITY_WOL_BCAST 0x00000010UL via-velocity.h 　
25086
 VELOCITY_WOL_MCASTVELOCITY_WOL_MCAST 0x00000020UL via-velocity.h 　
25087
 VELOCITY_WOL_MAGIC_SECVELOCITY_WOL_MAGIC_SEC 0x00000040UL via-velocity.h 　
25088
 VELOCITY_FLAGS_TAGGINGVELOCITY_FLAGS_TAGGING 0x00000001UL via-velocity.h 　
25089
 VELOCITY_FLAGS_TX_CSUMVELOCITY_FLAGS_TX_CSUM 0x00000002UL via-velocity.h 　
25090
 VELOCITY_FLAGS_RX_CSUMVELOCITY_FLAGS_RX_CSUM 0x00000004UL via-velocity.h 　
25091
 VELOCITY_FLAGS_IP_ALIGNVELOCITY_FLAGS_IP_ALIGN 0x00000008UL via-velocity.h 　
25092
 VELOCITY_FLAGS_VAL_PKT_LENVELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL via-velocity.h 　
25093
 VELOCITY_FLAGS_FLOW_CTRLVELOCITY_FLAGS_FLOW_CTRL 0x01000000UL via-velocity.h 　
25094
 VELOCITY_FLAGS_OPENEDVELOCITY_FLAGS_OPENED 0x00010000UL via-velocity.h 　
25095
 VELOCITY_FLAGS_VMNS_CONNECTEDVELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL via-velocity.h 　
25096
 VELOCITY_FLAGS_VMNS_COMMITTEDVELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL via-velocity.h 　
25097
 VELOCITY_FLAGS_WOL_ENABLEDVELOCITY_FLAGS_WOL_ENABLED 0x00080000UL via-velocity.h 　
25098
 VELOCITY_LINK_FAILVELOCITY_LINK_FAIL 0x00000001UL via-velocity.h 　
25099
 VELOCITY_SPEED_10VELOCITY_SPEED_10 0x00000002UL via-velocity.h 　
25100
 VELOCITY_SPEED_100VELOCITY_SPEED_100 0x00000004UL via-velocity.h 　
25101
 VELOCITY_SPEED_1000VELOCITY_SPEED_1000 0x00000008UL via-velocity.h 　
25102
 VELOCITY_DUPLEX_FULLVELOCITY_DUPLEX_FULL 0x00000010UL via-velocity.h 　
25103
 VELOCITY_AUTONEG_ENABLEVELOCITY_AUTONEG_ENABLE 0x00000020UL via-velocity.h 　
25104
 VELOCITY_FORCED_BY_EEPROMVELOCITY_FORCED_BY_EEPROM 0x00000040UL via-velocity.h 　
25105
 VELOCITY_LINK_CHANGEVELOCITY_LINK_CHANGE 0x00000001UL via-velocity.h 　
25106
 RX_DESC_MINRX_DESC_MIN 4 via-velocity.h 　
25107
 RX_DESC_MAXRX_DESC_MAX 255 via-velocity.h 　
25108
 RX_DESC_DEFRX_DESC_DEF RX_DESC_MIN via-velocity.h 　
25109
 TX_DESC_MINTX_DESC_MIN 1 via-velocity.h 　
25110
 TX_DESC_MAXTX_DESC_MAX 256 via-velocity.h 　
25111
 TX_DESC_DEFTX_DESC_DEF TX_DESC_MIN via-velocity.h 　
25112
 VIRTIO_NET_F_CSUMVIRTIO_NET_F_CSUM 0 virtio-net.h Host handles pkts w/ partial csum
25113
 VIRTIO_NET_F_GUEST_CSUMVIRTIO_NET_F_GUEST_CSUM 1 virtio-net.h Guest handles pkts w/ partial csum
25114
 VIRTIO_NET_F_MACVIRTIO_NET_F_MAC 5 virtio-net.h Host has given MAC address.
25115
 VIRTIO_NET_F_GSOVIRTIO_NET_F_GSO 6 virtio-net.h Host handles pkts w/ any GSO type
25116
 VIRTIO_NET_F_GUEST_TSO4VIRTIO_NET_F_GUEST_TSO4 7 virtio-net.h Guest can handle TSOv4 in.
25117
 VIRTIO_NET_F_GUEST_TSO6VIRTIO_NET_F_GUEST_TSO6 8 virtio-net.h Guest can handle TSOv6 in.
25118
 VIRTIO_NET_F_GUEST_ECNVIRTIO_NET_F_GUEST_ECN 9 virtio-net.h Guest can handle TSO[6] w/ ECN in.
25119
 VIRTIO_NET_F_GUEST_UFOVIRTIO_NET_F_GUEST_UFO 10 virtio-net.h Guest can handle UFO in.
25120
 VIRTIO_NET_F_HOST_TSO4VIRTIO_NET_F_HOST_TSO4 11 virtio-net.h Host can handle TSOv4 in.
25121
 VIRTIO_NET_F_HOST_TSO6VIRTIO_NET_F_HOST_TSO6 12 virtio-net.h Host can handle TSOv6 in.
25122
 VIRTIO_NET_F_HOST_ECNVIRTIO_NET_F_HOST_ECN 13 virtio-net.h Host can handle TSO[6] w/ ECN in.
25123
 VIRTIO_NET_F_HOST_UFOVIRTIO_NET_F_HOST_UFO 14 virtio-net.h Host can handle UFO in.
25124
 WLAN_Ix86WLAN_Ix86 1 wlan_compat.h 　
25125
 WLAN_PPCWLAN_PPC 2 wlan_compat.h 　
25126
 WLAN_Ix96WLAN_Ix96 3 wlan_compat.h 　
25127
 WLAN_ARMWLAN_ARM 4 wlan_compat.h 　
25128
 WLAN_ALPHAWLAN_ALPHA 5 wlan_compat.h 　
25129
 WLAN_MIPSWLAN_MIPS 6 wlan_compat.h 　
25130
 WLAN_HPPAWLAN_HPPA 7 wlan_compat.h 　
25131
 WLAN_I386COREWLAN_I386CORE 1 wlan_compat.h 　
25132
 WLAN_PPCCOREWLAN_PPCCORE 2 wlan_compat.h 　
25133
 WLAN_I296WLAN_I296 3 wlan_compat.h 　
25134
 WLAN_ARMCOREWLAN_ARMCORE 4 wlan_compat.h 　
25135
 WLAN_ALPHACOREWLAN_ALPHACORE 5 wlan_compat.h 　
25136
 WLAN_MIPSCOREWLAN_MIPSCORE 6 wlan_compat.h 　
25137
 WLAN_HPPACOREWLAN_HPPACORE 7 wlan_compat.h 　
25138
 WLAN_I386PARTWLAN_I386PART 1 wlan_compat.h 　
25139
 WLAN_MPC860WLAN_MPC860 2 wlan_compat.h 　
25140
 WLAN_MPC823WLAN_MPC823 3 wlan_compat.h 　
25141
 WLAN_I296SAWLAN_I296SA 4 wlan_compat.h 　
25142
 WLAN_PPCPARTWLAN_PPCPART 5 wlan_compat.h 　
25143
 WLAN_ARMPARTWLAN_ARMPART 6 wlan_compat.h 　
25144
 WLAN_ALPHAPARTWLAN_ALPHAPART 7 wlan_compat.h 　
25145
 WLAN_MIPSPARTWLAN_MIPSPART 8 wlan_compat.h 　
25146
 WLAN_HPPAPARTWLAN_HPPAPART 9 wlan_compat.h 　
25147
 WLAN_PCATWLAN_PCAT 1 wlan_compat.h 　
25148
 WLAN_MBXWLAN_MBX 2 wlan_compat.h 　
25149
 WLAN_RPXWLAN_RPX 3 wlan_compat.h 　
25150
 WLAN_LWARCHWLAN_LWARCH 4 wlan_compat.h 　
25151
 WLAN_PMACWLAN_PMAC 5 wlan_compat.h 　
25152
 WLAN_SKIFFWLAN_SKIFF 6 wlan_compat.h 　
25153
 WLAN_BITSYWLAN_BITSY 7 wlan_compat.h 　
25154
 WLAN_ALPHAARCHWLAN_ALPHAARCH 7 wlan_compat.h 　
25155
 WLAN_MIPSARCHWLAN_MIPSARCH 9 wlan_compat.h 　
25156
 WLAN_HPPAARCHWLAN_HPPAARCH 10 wlan_compat.h 　
25157
 WLAN_LINUX_KERNELWLAN_LINUX_KERNEL 1 wlan_compat.h 　
25158
 WLAN_LINUX_USERWLAN_LINUX_USER 2 wlan_compat.h 　
25159
 WLAN_PCMCIAWLAN_PCMCIA 1 wlan_compat.h 　
25160
 WLAN_ISAWLAN_ISA 2 wlan_compat.h 　
25161
 WLAN_PCIWLAN_PCI 3 wlan_compat.h 　
25162
 WLAN_USBWLAN_USB 4 wlan_compat.h 　
25163
 WLAN_PLXWLAN_PLX 5 wlan_compat.h 　
25164
 WLAN_OSWLAN_OS WLAN_LINUX_KERNEL wlan_compat.h 　
25165
 WLAN_OSWLAN_OS WLAN_LINUX_USER wlan_compat.h 　
25166
 WLAN_CPU_FAMILYWLAN_CPU_FAMILY WLAN_Ix86 wlan_compat.h 　
25167
 WLAN_CPU_COREWLAN_CPU_CORE WLAN_I386CORE wlan_compat.h 　
25168
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_I386PART wlan_compat.h 　
25169
 WLAN_SYSARCHWLAN_SYSARCH WLAN_PCAT wlan_compat.h 　
25170
 WLAN_CPU_FAMILYWLAN_CPU_FAMILY WLAN_PPC wlan_compat.h 　
25171
 WLAN_CPU_COREWLAN_CPU_CORE WLAN_PPCCORE wlan_compat.h 　
25172
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_MPC860 wlan_compat.h 　
25173
 WLAN_SYSARCHWLAN_SYSARCH WLAN_MBX wlan_compat.h 　
25174
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_MPC823 wlan_compat.h 　
25175
 WLAN_SYSARCHWLAN_SYSARCH WLAN_RPX wlan_compat.h 　
25176
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_MPC860 wlan_compat.h 　
25177
 WLAN_SYSARCHWLAN_SYSARCH WLAN_RPX wlan_compat.h 　
25178
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_PPCPART wlan_compat.h 　
25179
 WLAN_SYSARCHWLAN_SYSARCH WLAN_PMAC wlan_compat.h 　
25180
 WLAN_CPU_FAMILYWLAN_CPU_FAMILY WLAN_ARM wlan_compat.h 　
25181
 WLAN_CPU_COREWLAN_CPU_CORE WLAN_ARMCORE wlan_compat.h 　
25182
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_ARM_PART wlan_compat.h 　
25183
 WLAN_SYSARCHWLAN_SYSARCH WLAN_SKIFF wlan_compat.h 　
25184
 WLAN_CPU_FAMILYWLAN_CPU_FAMILY WLAN_ALPHA wlan_compat.h 　
25185
 WLAN_CPU_COREWLAN_CPU_CORE WLAN_ALPHACORE wlan_compat.h 　
25186
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_ALPHAPART wlan_compat.h 　
25187
 WLAN_SYSARCHWLAN_SYSARCH WLAN_ALPHAARCH wlan_compat.h 　
25188
 WLAN_CPU_FAMILYWLAN_CPU_FAMILY WLAN_MIPS wlan_compat.h 　
25189
 WLAN_CPU_COREWLAN_CPU_CORE WLAN_MIPSCORE wlan_compat.h 　
25190
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_MIPSPART wlan_compat.h 　
25191
 WLAN_SYSARCHWLAN_SYSARCH WLAN_MIPSARCH wlan_compat.h 　
25192
 WLAN_CPU_FAMILYWLAN_CPU_FAMILY WLAN_HPPA wlan_compat.h 　
25193
 WLAN_CPU_COREWLAN_CPU_CORE WLAN_HPPACORE wlan_compat.h 　
25194
 WLAN_CPU_PARTWLAN_CPU_PART WLAN_HPPAPART wlan_compat.h 　
25195
 WLAN_SYSARCHWLAN_SYSARCH WLAN_HPPAARCH wlan_compat.h 　
25196
 BIT0BIT0 0x00000001 wlan_compat.h 　
25197
 BIT1BIT1 0x00000002 wlan_compat.h 　
25198
 BIT2BIT2 0x00000004 wlan_compat.h 　
25199
 BIT3BIT3 0x00000008 wlan_compat.h 　
25200
 BIT4BIT4 0x00000010 wlan_compat.h 　
25201
 BIT5BIT5 0x00000020 wlan_compat.h 　
25202
 BIT6BIT6 0x00000040 wlan_compat.h 　
25203
 BIT7BIT7 0x00000080 wlan_compat.h 　
25204
 BIT8BIT8 0x00000100 wlan_compat.h 　
25205
 BIT9BIT9 0x00000200 wlan_compat.h 　
25206
 BIT10BIT10 0x00000400 wlan_compat.h 　
25207
 BIT11BIT11 0x00000800 wlan_compat.h 　
25208
 BIT12BIT12 0x00001000 wlan_compat.h 　
25209
 BIT13BIT13 0x00002000 wlan_compat.h 　
25210
 BIT14BIT14 0x00004000 wlan_compat.h 　
25211
 BIT15BIT15 0x00008000 wlan_compat.h 　
25212
 BIT16BIT16 0x00010000 wlan_compat.h 　
25213
 BIT17BIT17 0x00020000 wlan_compat.h 　
25214
 BIT18BIT18 0x00040000 wlan_compat.h 　
25215
 BIT19BIT19 0x00080000 wlan_compat.h 　
25216
 BIT20BIT20 0x00100000 wlan_compat.h 　
25217
 BIT21BIT21 0x00200000 wlan_compat.h 　
25218
 BIT22BIT22 0x00400000 wlan_compat.h 　
25219
 BIT23BIT23 0x00800000 wlan_compat.h 　
25220
 BIT24BIT24 0x01000000 wlan_compat.h 　
25221
 BIT25BIT25 0x02000000 wlan_compat.h 　
25222
 BIT26BIT26 0x04000000 wlan_compat.h 　
25223
 BIT27BIT27 0x08000000 wlan_compat.h 　
25224
 BIT28BIT28 0x10000000 wlan_compat.h 　
25225
 BIT29BIT29 0x20000000 wlan_compat.h 　
25226
 BIT30BIT30 0x40000000 wlan_compat.h 　
25227
 BIT31BIT31 0x80000000 wlan_compat.h 　
25228
 UINT8_MAXUINT8_MAX (0xffUL) wlan_compat.h 　
25229
 UINT16_MAXUINT16_MAX (0xffffUL) wlan_compat.h 　
25230
 UINT32_MAXUINT32_MAX (0xffffffffUL) wlan_compat.h 　
25231
 INT8_MAXINT8_MAX (0x7fL) wlan_compat.h 　
25232
 INT16_MAXINT16_MAX (0x7fffL) wlan_compat.h 　
25233
 INT32_MAXINT32_MAX (0x7fffffffL) wlan_compat.h 　
25234
 __WLAN_ATTRIB_PACK____WLAN_ATTRIB_PACK__ __attribute__ ((packed)) wlan_compat.h 　
25235
 __WLAN_INLINE____WLAN_INLINE__ inline wlan_compat.h 　
25236
 WLAN_MIN_ARRAYWLAN_MIN_ARRAY 0 wlan_compat.h 　
25237
 WLAN_DBVARWLAN_DBVAR wlan_debug wlan_compat.h 　
25238
 DBFENTERDBFENTER { if ( WLAN_DBVAR >= 4 ){ WLAN_LOG_DEBUG0(3,"Enter\n"); } } wlan_compat.h 　
25239
 DBFEXITDBFEXIT { if ( WLAN_DBVAR >= 4 ){ WLAN_LOG_DEBUG0(3,"Exit\n"); } } wlan_compat.h 　
25240
 wlan_ms_per_tickwlan_ms_per_tick (1000UL / (wlan_ticks_per_sec)) wlan_compat.h 　
25241
 MODVERSIONSMODVERSIONS 1 wlan_compat.h 　
25242
 __SMP____SMP__ 1 wlan_compat.h 　
25243
 CONFIG_NETLINKCONFIG_NETLINK 1 wlan_compat.h 　
25244
 ATH5K_CALIB_INTERVALATH5K_CALIB_INTERVAL 10 ath5k.c Calibrate PHY every 10 seconds
25245
 ATH5K_RETRIESATH5K_RETRIES 4 ath5k.c Number of times to retry packet sends
25246
 ATH5K_DESC_ALIGNATH5K_DESC_ALIGN 16 ath5k.c Alignment for TX/RX descriptors
25247
 ATH5K_SPMBL_NOATH5K_SPMBL_NO 1 ath5k.c 　
25248
 ATH5K_SPMBL_YESATH5K_SPMBL_YES 2 ath5k.c 　
25249
 ATH5K_SPMBL_BOTHATH5K_SPMBL_BOTH 3 ath5k.c 　
25250
 ATH5K_NR_RATESATH5K_NR_RATES 15 ath5k.c 　
25251
 FCS_LENFCS_LEN 4 ath5k_desc.c 　
25252
 ERRFILEERRFILE ERRFILE_ath5k ath5k.h 　
25253
 PCI_DEVICE_ID_ATHEROS_AR5210PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 ath5k.h AR5210
25254
 PCI_DEVICE_ID_ATHEROS_AR5311PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 ath5k.h AR5311
25255
 PCI_DEVICE_ID_ATHEROS_AR5211PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 ath5k.h AR5211
25256
 PCI_DEVICE_ID_ATHEROS_AR5212PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 ath5k.h AR5212
25257
 PCI_DEVICE_ID_3COM_3CRDAG675PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 ath5k.h 3CRDAG675 (Atheros AR5212)
25258
 PCI_DEVICE_ID_3COM_2_3CRPAG175PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 ath5k.h 3CRPAG175 (Atheros AR5212)
25259
 PCI_DEVICE_ID_ATHEROS_AR5210_APPCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 ath5k.h AR5210 (Early)
25260
 PCI_DEVICE_ID_ATHEROS_AR5212_IBPCI_DEVICE_ID_ATHEROS_AR5212_IB 0x1014 ath5k.h AR5212 (IBM MiniPCI)
25261
 PCI_DEVICE_ID_ATHEROS_AR5210_DEPCI_DEVICE_ID_ATHEROS_AR5210_DE 0x1107 ath5k.h AR5210 (no eeprom)
25262
 PCI_DEVICE_ID_ATHEROS_AR5212_DEPCI_DEVICE_ID_ATHEROS_AR5212_DE 0x1113 ath5k.h AR5212 (no eeprom)
25263
 PCI_DEVICE_ID_ATHEROS_AR5211_DEPCI_DEVICE_ID_ATHEROS_AR5211_DE 0x1112 ath5k.h AR5211 (no eeprom)
25264
 PCI_DEVICE_ID_ATHEROS_AR5212_FPPCI_DEVICE_ID_ATHEROS_AR5212_FP 0xf013 ath5k.h AR5212 (emulation board)
25265
 PCI_DEVICE_ID_ATHEROS_AR5211_LEPCI_DEVICE_ID_ATHEROS_AR5211_LE 0xff12 ath5k.h AR5211 (emulation board)
25266
 PCI_DEVICE_ID_ATHEROS_AR5211_FPPCI_DEVICE_ID_ATHEROS_AR5211_FP 0xf11b ath5k.h AR5211 (emulation board)
25267
 PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0052 ath5k.h AR5312 WMAC (AP31)
25268
 PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0057 ath5k.h AR5312 WMAC (AP30-040)
25269
 PCI_DEVICE_ID_ATHEROS_AR5312_REPCI_DEVICE_ID_ATHEROS_AR5312_RE 0x0058 ath5k.h AR5312 WMAC (AP43-030)
25270
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0014 ath5k.h AR5212 compatible
25271
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0015 ath5k.h AR5212 compatible
25272
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0016 ath5k.h AR5212 compatible
25273
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0017 ath5k.h AR5212 compatible
25274
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0018 ath5k.h AR5212 compatible
25275
 PCI_DEVICE_ID_ATHEROS_AR5212_00PCI_DEVICE_ID_ATHEROS_AR5212_00 0x0019 ath5k.h AR5212 compatible
25276
 PCI_DEVICE_ID_ATHEROS_AR2413PCI_DEVICE_ID_ATHEROS_AR2413 0x001a ath5k.h AR2413 (Griffin-lite)
25277
 PCI_DEVICE_ID_ATHEROS_AR5413PCI_DEVICE_ID_ATHEROS_AR5413 0x001b ath5k.h AR5413 (Eagle)
25278
 PCI_DEVICE_ID_ATHEROS_AR5424PCI_DEVICE_ID_ATHEROS_AR5424 0x001c ath5k.h AR5424 (Condor PCI-E)
25279
 PCI_DEVICE_ID_ATHEROS_AR5416PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 ath5k.h AR5416
25280
 PCI_DEVICE_ID_ATHEROS_AR5418PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 ath5k.h AR5418
25281
 AR5K_INI_RFGAIN_5GHZAR5K_INI_RFGAIN_5GHZ 0 ath5k.h 　
25282
 AR5K_INI_RFGAIN_2GHZAR5K_INI_RFGAIN_2GHZ 1 ath5k.h 　
25283
 AR5K_INI_VAL_11AAR5K_INI_VAL_11A 0 ath5k.h 　
25284
 AR5K_INI_VAL_11A_TURBOAR5K_INI_VAL_11A_TURBO 1 ath5k.h 　
25285
 AR5K_INI_VAL_11BAR5K_INI_VAL_11B 2 ath5k.h 　
25286
 AR5K_INI_VAL_11GAR5K_INI_VAL_11G 3 ath5k.h 　
25287
 AR5K_INI_VAL_11G_TURBOAR5K_INI_VAL_11G_TURBO 4 ath5k.h 　
25288
 AR5K_INI_VAL_XRAR5K_INI_VAL_XR 0 ath5k.h 　
25289
 AR5K_INI_VAL_MAXAR5K_INI_VAL_MAX 5 ath5k.h 　
25290
 IEEE80211_MAX_LENIEEE80211_MAX_LEN 2352 ath5k.h 　
25291
 AR5K_TUNE_DMA_BEACON_RESPAR5K_TUNE_DMA_BEACON_RESP 2 ath5k.h 　
25292
 AR5K_TUNE_SW_BEACON_RESPAR5K_TUNE_SW_BEACON_RESP 10 ath5k.h 　
25293
 AR5K_TUNE_ADDITIONAL_SWBA_BACKOAR5K_TUNE_ADDITIONAL_SWBA_BACKO 0 ath5k.h 　
25294
 AR5K_TUNE_RADAR_ALERTAR5K_TUNE_RADAR_ALERT 0 ath5k.h 　
25295
 AR5K_TUNE_MIN_TX_FIFO_THRESAR5K_TUNE_MIN_TX_FIFO_THRES 1 ath5k.h 　
25296
 AR5K_TUNE_MAX_TX_FIFO_THRESAR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1) ath5k.h 　
25297
 AR5K_TUNE_REGISTER_TIMEOUTAR5K_TUNE_REGISTER_TIMEOUT 20000 ath5k.h 　
25298
 AR5K_TUNE_RSSI_THRESAR5K_TUNE_RSSI_THRES 129 ath5k.h 　
25299
 AR5K_TUNE_BMISS_THRESAR5K_TUNE_BMISS_THRES 7 ath5k.h 　
25300
 AR5K_TUNE_REGISTER_DWELL_TIMEAR5K_TUNE_REGISTER_DWELL_TIME 20000 ath5k.h 　
25301
 AR5K_TUNE_BEACON_INTERVALAR5K_TUNE_BEACON_INTERVAL 100 ath5k.h 　
25302
 AR5K_TUNE_AIFSAR5K_TUNE_AIFS 2 ath5k.h 　
25303
 AR5K_TUNE_AIFS_11BAR5K_TUNE_AIFS_11B 2 ath5k.h 　
25304
 AR5K_TUNE_AIFS_XRAR5K_TUNE_AIFS_XR 0 ath5k.h 　
25305
 AR5K_TUNE_CWMINAR5K_TUNE_CWMIN 15 ath5k.h 　
25306
 AR5K_TUNE_CWMIN_11BAR5K_TUNE_CWMIN_11B 31 ath5k.h 　
25307
 AR5K_TUNE_CWMIN_XRAR5K_TUNE_CWMIN_XR 3 ath5k.h 　
25308
 AR5K_TUNE_CWMAXAR5K_TUNE_CWMAX 1023 ath5k.h 　
25309
 AR5K_TUNE_CWMAX_11BAR5K_TUNE_CWMAX_11B 1023 ath5k.h 　
25310
 AR5K_TUNE_CWMAX_XRAR5K_TUNE_CWMAX_XR 7 ath5k.h 　
25311
 AR5K_TUNE_NOISE_FLOORAR5K_TUNE_NOISE_FLOOR -72 ath5k.h 　
25312
 AR5K_TUNE_MAX_TXPOWERAR5K_TUNE_MAX_TXPOWER 63 ath5k.h 　
25313
 AR5K_TUNE_DEFAULT_TXPOWERAR5K_TUNE_DEFAULT_TXPOWER 25 ath5k.h 　
25314
 AR5K_TUNE_TPC_TXPOWERAR5K_TUNE_TPC_TXPOWER 0 ath5k.h 　
25315
 AR5K_TUNE_ANT_DIVERSITYAR5K_TUNE_ANT_DIVERSITY 1 ath5k.h 　
25316
 AR5K_TUNE_HWTXTRIESAR5K_TUNE_HWTXTRIES 4 ath5k.h 　
25317
 AR5K_INIT_CARR_SENSE_ENAR5K_INIT_CARR_SENSE_EN 1 ath5k.h 　
25318
 AR5K_INIT_CFGAR5K_INIT_CFG ( \ AR5K_CFG_SWTD | AR5K_CFG_SWRD \ ) ath5k.h 　
25319
 AR5K_INIT_CFGAR5K_INIT_CFG 0x00000000 ath5k.h 　
25320
 AR5K_INIT_CYCRSSI_THR1AR5K_INIT_CYCRSSI_THR1 2 ath5k.h 　
25321
 AR5K_INIT_TX_LATENCYAR5K_INIT_TX_LATENCY 502 ath5k.h 　
25322
 AR5K_INIT_USECAR5K_INIT_USEC 39 ath5k.h 　
25323
 AR5K_INIT_USEC_TURBOAR5K_INIT_USEC_TURBO 79 ath5k.h 　
25324
 AR5K_INIT_USEC_32AR5K_INIT_USEC_32 31 ath5k.h 　
25325
 AR5K_INIT_SLOT_TIMEAR5K_INIT_SLOT_TIME 396 ath5k.h 　
25326
 AR5K_INIT_SLOT_TIME_TURBOAR5K_INIT_SLOT_TIME_TURBO 480 ath5k.h 　
25327
 AR5K_INIT_ACK_CTS_TIMEOUTAR5K_INIT_ACK_CTS_TIMEOUT 1024 ath5k.h 　
25328
 AR5K_INIT_ACK_CTS_TIMEOUT_TURBOAR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800 ath5k.h 　
25329
 AR5K_INIT_PROG_IFSAR5K_INIT_PROG_IFS 920 ath5k.h 　
25330
 AR5K_INIT_PROG_IFS_TURBOAR5K_INIT_PROG_IFS_TURBO 960 ath5k.h 　
25331
 AR5K_INIT_EIFSAR5K_INIT_EIFS 3440 ath5k.h 　
25332
 AR5K_INIT_EIFS_TURBOAR5K_INIT_EIFS_TURBO 6880 ath5k.h 　
25333
 AR5K_INIT_SIFSAR5K_INIT_SIFS 560 ath5k.h 　
25334
 AR5K_INIT_SIFS_TURBOAR5K_INIT_SIFS_TURBO 480 ath5k.h 　
25335
 AR5K_INIT_SH_RETRYAR5K_INIT_SH_RETRY 10 ath5k.h 　
25336
 AR5K_INIT_LG_RETRYAR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY ath5k.h 　
25337
 AR5K_INIT_SSH_RETRYAR5K_INIT_SSH_RETRY 32 ath5k.h 　
25338
 AR5K_INIT_SLG_RETRYAR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY ath5k.h 　
25339
 AR5K_INIT_TX_RETRYAR5K_INIT_TX_RETRY 10 ath5k.h 　
25340
 AR5K_INIT_TRANSMIT_LATENCYAR5K_INIT_TRANSMIT_LATENCY ( \ (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ (AR5K_INIT_USEC) \ ) ath5k.h 　
25341
 AR5K_INIT_TRANSMIT_LATENCY_TURBAR5K_INIT_TRANSMIT_LATENCY_TURB ( \ (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \ (AR5K_INIT_USEC_TURBO) \ ) ath5k.h 　
25342
 AR5K_INIT_PROTO_TIME_CNTRLAR5K_INIT_PROTO_TIME_CNTRL ( \ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \ (AR5K_INIT_PROG_IFS) \ ) ath5k.h 　
25343
 AR5K_INIT_PROTO_TIME_CNTRL_TURBAR5K_INIT_PROTO_TIME_CNTRL_TURB ( \ (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \ (AR5K_INIT_PROG_IFS_TURBO) \ ) ath5k.h 　
25344
 AR5K_TXQ_USEDEFAULTAR5K_TXQ_USEDEFAULT ((u32) -1) ath5k.h 　
25345
 AR5K_SREV_UNKNOWNAR5K_SREV_UNKNOWN 0xffff ath5k.h 　
25346
 AR5K_SREV_AR5210AR5K_SREV_AR5210 0x00 ath5k.h Crete
25347
 AR5K_SREV_AR5311AR5K_SREV_AR5311 0x10 ath5k.h Maui 1
25348
 AR5K_SREV_AR5311AAR5K_SREV_AR5311A 0x20 ath5k.h Maui 2
25349
 AR5K_SREV_AR5311BAR5K_SREV_AR5311B 0x30 ath5k.h Spirit
25350
 AR5K_SREV_AR5211AR5K_SREV_AR5211 0x40 ath5k.h Oahu
25351
 AR5K_SREV_AR5212AR5K_SREV_AR5212 0x50 ath5k.h Venice
25352
 AR5K_SREV_AR5213AR5K_SREV_AR5213 0x55 ath5k.h ???
25353
 AR5K_SREV_AR5213AAR5K_SREV_AR5213A 0x59 ath5k.h Hainan
25354
 AR5K_SREV_AR2413AR5K_SREV_AR2413 0x78 ath5k.h Griffin lite
25355
 AR5K_SREV_AR2414AR5K_SREV_AR2414 0x70 ath5k.h Griffin
25356
 AR5K_SREV_AR5424AR5K_SREV_AR5424 0x90 ath5k.h Condor
25357
 AR5K_SREV_AR5413AR5K_SREV_AR5413 0xa4 ath5k.h Eagle lite
25358
 AR5K_SREV_AR5414AR5K_SREV_AR5414 0xa0 ath5k.h Eagle
25359
 AR5K_SREV_AR2415AR5K_SREV_AR2415 0xb0 ath5k.h Talon
25360
 AR5K_SREV_AR5416AR5K_SREV_AR5416 0xc0 ath5k.h PCI-E
25361
 AR5K_SREV_AR5418AR5K_SREV_AR5418 0xca ath5k.h PCI-E
25362
 AR5K_SREV_AR2425AR5K_SREV_AR2425 0xe0 ath5k.h Swan
25363
 AR5K_SREV_AR2417AR5K_SREV_AR2417 0xf0 ath5k.h Nala
25364
 AR5K_SREV_RAD_5110AR5K_SREV_RAD_5110 0x00 ath5k.h 　
25365
 AR5K_SREV_RAD_5111AR5K_SREV_RAD_5111 0x10 ath5k.h 　
25366
 AR5K_SREV_RAD_5111AAR5K_SREV_RAD_5111A 0x15 ath5k.h 　
25367
 AR5K_SREV_RAD_2111AR5K_SREV_RAD_2111 0x20 ath5k.h 　
25368
 AR5K_SREV_RAD_5112AR5K_SREV_RAD_5112 0x30 ath5k.h 　
25369
 AR5K_SREV_RAD_5112AAR5K_SREV_RAD_5112A 0x35 ath5k.h 　
25370
 AR5K_SREV_RAD_5112BAR5K_SREV_RAD_5112B 0x36 ath5k.h 　
25371
 AR5K_SREV_RAD_2112AR5K_SREV_RAD_2112 0x40 ath5k.h 　
25372
 AR5K_SREV_RAD_2112AAR5K_SREV_RAD_2112A 0x45 ath5k.h 　
25373
 AR5K_SREV_RAD_2112BAR5K_SREV_RAD_2112B 0x46 ath5k.h 　
25374
 AR5K_SREV_RAD_2413AR5K_SREV_RAD_2413 0x50 ath5k.h 　
25375
 AR5K_SREV_RAD_5413AR5K_SREV_RAD_5413 0x60 ath5k.h 　
25376
 AR5K_SREV_RAD_2316AR5K_SREV_RAD_2316 0x70 ath5k.h Cobra SoC
25377
 AR5K_SREV_RAD_2317AR5K_SREV_RAD_2317 0x80 ath5k.h 　
25378
 AR5K_SREV_RAD_5424AR5K_SREV_RAD_5424 0xa0 ath5k.h Mostly same as 5413
25379
 AR5K_SREV_RAD_2425AR5K_SREV_RAD_2425 0xa2 ath5k.h 　
25380
 AR5K_SREV_RAD_5133AR5K_SREV_RAD_5133 0xc0 ath5k.h 　
25381
 AR5K_SREV_PHY_5211AR5K_SREV_PHY_5211 0x30 ath5k.h 　
25382
 AR5K_SREV_PHY_5212AR5K_SREV_PHY_5212 0x41 ath5k.h 　
25383
 AR5K_SREV_PHY_5212AAR5K_SREV_PHY_5212A 0x42 ath5k.h 　
25384
 AR5K_SREV_PHY_5212BAR5K_SREV_PHY_5212B 0x43 ath5k.h 　
25385
 AR5K_SREV_PHY_2413AR5K_SREV_PHY_2413 0x45 ath5k.h 　
25386
 AR5K_SREV_PHY_5413AR5K_SREV_PHY_5413 0x61 ath5k.h 　
25387
 AR5K_SREV_PHY_2425AR5K_SREV_PHY_2425 0x70 ath5k.h 　
25388
 MODULATION_XRMODULATION_XR 0x00000200 ath5k.h 　
25389
 MODULATION_TURBOMODULATION_TURBO 0x00000080 ath5k.h 　
25390
 AR5K_TXSTAT_ALTRATEAR5K_TXSTAT_ALTRATE 0x80 ath5k.h 　
25391
 AR5K_TXERR_XRETRYAR5K_TXERR_XRETRY 0x01 ath5k.h 　
25392
 AR5K_TXERR_FILTAR5K_TXERR_FILT 0x02 ath5k.h 　
25393
 AR5K_TXERR_FIFOAR5K_TXERR_FIFO 0x04 ath5k.h 　
25394
 AR5K_TXQ_FLAG_TXOKINT_ENABLEAR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 ath5k.h Enable TXOK interrupt
25395
 AR5K_TXQ_FLAG_TXERRINT_ENABLEAR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 ath5k.h Enable TXERR interrupt
25396
 AR5K_TXQ_FLAG_TXEOLINT_ENABLEAR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 ath5k.h Enable TXEOL interrupt -not used-
25397
 AR5K_TXQ_FLAG_TXDESCINT_ENABLEAR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 ath5k.h Enable TXDESC interrupt -not used-
25398
 AR5K_TXQ_FLAG_TXURNINT_ENABLEAR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 ath5k.h Enable TXURN interrupt
25399
 AR5K_TXQ_FLAG_CBRORNINT_ENABLEAR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 ath5k.h Enable CBRORN interrupt
25400
 AR5K_TXQ_FLAG_CBRURNINT_ENABLEAR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 ath5k.h Enable CBRURN interrupt
25401
 AR5K_TXQ_FLAG_QTRIGINT_ENABLEAR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 ath5k.h Enable QTRIG interrupt
25402
 AR5K_TXQ_FLAG_TXNOFRMINT_ENABLEAR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 ath5k.h Enable TXNOFRM interrupt
25403
 AR5K_TXQ_FLAG_BACKOFF_DISABLEAR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 ath5k.h Disable random post-backoff
25404
 AR5K_TXQ_FLAG_RDYTIME_EXP_POLICAR5K_TXQ_FLAG_RDYTIME_EXP_POLIC 0x0300 ath5k.h Enable ready time expiry policy (?)
25405
 AR5K_TXQ_FLAG_FRAG_BURST_BACKOFAR5K_TXQ_FLAG_FRAG_BURST_BACKOF 0x0800 ath5k.h Enable backoff while bursting
25406
 AR5K_TXQ_FLAG_POST_FR_BKOFF_DISAR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 ath5k.h Disable backoff while bursting
25407
 AR5K_TXQ_FLAG_COMPRESSION_ENABLAR5K_TXQ_FLAG_COMPRESSION_ENABL 0x2000 ath5k.h Enable hw compression -not implemented-
25408
 AR5K_RXERR_CRCAR5K_RXERR_CRC 0x01 ath5k.h 　
25409
 AR5K_RXERR_PHYAR5K_RXERR_PHY 0x02 ath5k.h 　
25410
 AR5K_RXERR_FIFOAR5K_RXERR_FIFO 0x04 ath5k.h 　
25411
 AR5K_RXERR_DECRYPTAR5K_RXERR_DECRYPT 0x08 ath5k.h 　
25412
 AR5K_RXERR_MICAR5K_RXERR_MIC 0x10 ath5k.h 　
25413
 AR5K_RXKEYIX_INVALIDAR5K_RXKEYIX_INVALID ((u8) - 1) ath5k.h 　
25414
 AR5K_TXKEYIX_INVALIDAR5K_TXKEYIX_INVALID ((u32) - 1) ath5k.h 　
25415
 AR5K_SLOT_TIME_9AR5K_SLOT_TIME_9 396 ath5k.h 　
25416
 AR5K_SLOT_TIME_20AR5K_SLOT_TIME_20 880 ath5k.h 　
25417
 AR5K_SLOT_TIME_MAXAR5K_SLOT_TIME_MAX 0xffff ath5k.h 　
25418
 CHANNEL_CW_INTCHANNEL_CW_INT 0x0008 ath5k.h Contention Window interference detected
25419
 CHANNEL_TURBOCHANNEL_TURBO 0x0010 ath5k.h Turbo Channel
25420
 CHANNEL_CCKCHANNEL_CCK 0x0020 ath5k.h CCK channel
25421
 CHANNEL_OFDMCHANNEL_OFDM 0x0040 ath5k.h OFDM channel
25422
 CHANNEL_2GHZCHANNEL_2GHZ 0x0080 ath5k.h 2GHz channel.
25423
 CHANNEL_5GHZCHANNEL_5GHZ 0x0100 ath5k.h 5GHz channel
25424
 CHANNEL_PASSIVECHANNEL_PASSIVE 0x0200 ath5k.h Only passive scan allowed
25425
 CHANNEL_DYNCHANNEL_DYN 0x0400 ath5k.h Dynamic CCK-OFDM channel (for g operation)
25426
 CHANNEL_XRCHANNEL_XR 0x0800 ath5k.h XR channel
25427
 CHANNEL_ACHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) ath5k.h 　
25428
 CHANNEL_BCHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) ath5k.h 　
25429
 CHANNEL_GCHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) ath5k.h 　
25430
 CHANNEL_TCHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO) ath5k.h 　
25431
 CHANNEL_TGCHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO) ath5k.h 　
25432
 CHANNEL_108ACHANNEL_108A CHANNEL_T ath5k.h 　
25433
 CHANNEL_108GCHANNEL_108G CHANNEL_TG ath5k.h 　
25434
 CHANNEL_XCHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) ath5k.h 　
25435
 CHANNEL_ALLCHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \ CHANNEL_TURBO) ath5k.h 　
25436
 CHANNEL_ALL_NOTURBOCHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO) ath5k.h 　
25437
 CHANNEL_MODESCHANNEL_MODES CHANNEL_ALL ath5k.h 　
25438
 AR5K_MAX_RATESAR5K_MAX_RATES 32 ath5k.h 　
25439
 ATH5K_RATE_CODE_1MATH5K_RATE_CODE_1M 0x1B ath5k.h 　
25440
 ATH5K_RATE_CODE_2MATH5K_RATE_CODE_2M 0x1A ath5k.h 　
25441
 ATH5K_RATE_CODE_5_5MATH5K_RATE_CODE_5_5M 0x19 ath5k.h 　
25442
 ATH5K_RATE_CODE_11MATH5K_RATE_CODE_11M 0x18 ath5k.h 　
25443
 ATH5K_RATE_CODE_6MATH5K_RATE_CODE_6M 0x0B ath5k.h 　
25444
 ATH5K_RATE_CODE_9MATH5K_RATE_CODE_9M 0x0F ath5k.h 　
25445
 ATH5K_RATE_CODE_12MATH5K_RATE_CODE_12M 0x0A ath5k.h 　
25446
 ATH5K_RATE_CODE_18MATH5K_RATE_CODE_18M 0x0E ath5k.h 　
25447
 ATH5K_RATE_CODE_24MATH5K_RATE_CODE_24M 0x09 ath5k.h 　
25448
 ATH5K_RATE_CODE_36MATH5K_RATE_CODE_36M 0x0D ath5k.h 　
25449
 ATH5K_RATE_CODE_48MATH5K_RATE_CODE_48M 0x08 ath5k.h 　
25450
 ATH5K_RATE_CODE_54MATH5K_RATE_CODE_54M 0x0C ath5k.h 　
25451
 ATH5K_RATE_CODE_XR_500KATH5K_RATE_CODE_XR_500K 0x07 ath5k.h 　
25452
 ATH5K_RATE_CODE_XR_1MATH5K_RATE_CODE_XR_1M 0x02 ath5k.h 　
25453
 ATH5K_RATE_CODE_XR_2MATH5K_RATE_CODE_XR_2M 0x06 ath5k.h 　
25454
 ATH5K_RATE_CODE_XR_3MATH5K_RATE_CODE_XR_3M 0x01 ath5k.h 　
25455
 AR5K_SET_SHORT_PREAMBLEAR5K_SET_SHORT_PREAMBLE 0x04 ath5k.h 　
25456
 AR5K_KEYCACHE_SIZEAR5K_KEYCACHE_SIZE 8 ath5k.h 　
25457
 AR5K_RSSI_EP_MULTIPLIERAR5K_RSSI_EP_MULTIPLIER (1<<7) ath5k.h 　
25458
 AR5K_SOFTLED_PINAR5K_SOFTLED_PIN 0 ath5k.h 　
25459
 AR5K_SOFTLED_ONAR5K_SOFTLED_ON 0 ath5k.h 　
25460
 AR5K_SOFTLED_OFFAR5K_SOFTLED_OFF 1 ath5k.h 　
25461
 AR5K_MAX_GPIOAR5K_MAX_GPIO 10 ath5k.h 　
25462
 AR5K_MAX_RF_BANKSAR5K_MAX_RF_BANKS 8 ath5k.h 　
25463
 ATH_RXBUFATH_RXBUF 16 base.h number of RX buffers
25464
 ATH_TXBUFATH_TXBUF 16 base.h number of TX buffers
25465
 ATH_CHAN_MAXATH_CHAN_MAX (26+26+26+200+200) base.h 　
25466
 ATH_CHAN_MAXATH_CHAN_MAX (14+14+14+252+20) base.h 　
25467
 AR5K_DESC_RX_CTL0AR5K_DESC_RX_CTL0 0x00000000 desc.h 　
25468
 AR5K_DESC_RX_CTL1_BUF_LENAR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff desc.h 　
25469
 AR5K_DESC_RX_CTL1_INTREQAR5K_DESC_RX_CTL1_INTREQ 0x00002000 desc.h 　
25470
 AR5K_5210_RX_DESC_STATUS0_DATA_AR5K_5210_RX_DESC_STATUS0_DATA_ 0x00000fff desc.h 　
25471
 AR5K_5210_RX_DESC_STATUS0_MOREAR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 desc.h 　
25472
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x00078000 desc.h 　
25473
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 15 desc.h 　
25474
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x07f80000 desc.h 　
25475
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 19 desc.h 　
25476
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 0x38000000 desc.h 　
25477
 AR5K_5210_RX_DESC_STATUS0_RECEIAR5K_5210_RX_DESC_STATUS0_RECEI 27 desc.h 　
25478
 AR5K_5210_RX_DESC_STATUS1_DONEAR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 desc.h 　
25479
 AR5K_5210_RX_DESC_STATUS1_FRAMEAR5K_5210_RX_DESC_STATUS1_FRAME 0x00000002 desc.h 　
25480
 AR5K_5210_RX_DESC_STATUS1_CRC_EAR5K_5210_RX_DESC_STATUS1_CRC_E 0x00000004 desc.h 　
25481
 AR5K_5210_RX_DESC_STATUS1_FIFO_AR5K_5210_RX_DESC_STATUS1_FIFO_ 0x00000008 desc.h 　
25482
 AR5K_5210_RX_DESC_STATUS1_DECRYAR5K_5210_RX_DESC_STATUS1_DECRY 0x00000010 desc.h 　
25483
 AR5K_5210_RX_DESC_STATUS1_PHY_EAR5K_5210_RX_DESC_STATUS1_PHY_E 0x000000e0 desc.h 　
25484
 AR5K_5210_RX_DESC_STATUS1_PHY_EAR5K_5210_RX_DESC_STATUS1_PHY_E 5 desc.h 　
25485
 AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 0x00000100 desc.h 　
25486
 AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 0x00007e00 desc.h 　
25487
 AR5K_5210_RX_DESC_STATUS1_KEY_IAR5K_5210_RX_DESC_STATUS1_KEY_I 9 desc.h 　
25488
 AR5K_5210_RX_DESC_STATUS1_RECEIAR5K_5210_RX_DESC_STATUS1_RECEI 0x0fff8000 desc.h 　
25489
 AR5K_5210_RX_DESC_STATUS1_RECEIAR5K_5210_RX_DESC_STATUS1_RECEI 15 desc.h 　
25490
 AR5K_5210_RX_DESC_STATUS1_KEY_CAR5K_5210_RX_DESC_STATUS1_KEY_C 0x10000000 desc.h 　
25491
 AR5K_5212_RX_DESC_STATUS0_DATA_AR5K_5212_RX_DESC_STATUS0_DATA_ 0x00000fff desc.h 　
25492
 AR5K_5212_RX_DESC_STATUS0_MOREAR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 desc.h 　
25493
 AR5K_5212_RX_DESC_STATUS0_DECOMAR5K_5212_RX_DESC_STATUS0_DECOM 0x00002000 desc.h 　
25494
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0x000f8000 desc.h 　
25495
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 15 desc.h 　
25496
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0x0ff00000 desc.h 　
25497
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 20 desc.h 　
25498
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 0xf0000000 desc.h 　
25499
 AR5K_5212_RX_DESC_STATUS0_RECEIAR5K_5212_RX_DESC_STATUS0_RECEI 28 desc.h 　
25500
 AR5K_5212_RX_DESC_STATUS1_DONEAR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 desc.h 　
25501
 AR5K_5212_RX_DESC_STATUS1_FRAMEAR5K_5212_RX_DESC_STATUS1_FRAME 0x00000002 desc.h 　
25502
 AR5K_5212_RX_DESC_STATUS1_CRC_EAR5K_5212_RX_DESC_STATUS1_CRC_E 0x00000004 desc.h 　
25503
 AR5K_5212_RX_DESC_STATUS1_DECRYAR5K_5212_RX_DESC_STATUS1_DECRY 0x00000008 desc.h 　
25504
 AR5K_5212_RX_DESC_STATUS1_PHY_EAR5K_5212_RX_DESC_STATUS1_PHY_E 0x00000010 desc.h 　
25505
 AR5K_5212_RX_DESC_STATUS1_MIC_EAR5K_5212_RX_DESC_STATUS1_MIC_E 0x00000020 desc.h 　
25506
 AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 0x00000100 desc.h 　
25507
 AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 0x0000fe00 desc.h 　
25508
 AR5K_5212_RX_DESC_STATUS1_KEY_IAR5K_5212_RX_DESC_STATUS1_KEY_I 9 desc.h 　
25509
 AR5K_5212_RX_DESC_STATUS1_RECEIAR5K_5212_RX_DESC_STATUS1_RECEI 0x7fff0000 desc.h 　
25510
 AR5K_5212_RX_DESC_STATUS1_RECEIAR5K_5212_RX_DESC_STATUS1_RECEI 16 desc.h 　
25511
 AR5K_5212_RX_DESC_STATUS1_KEY_CAR5K_5212_RX_DESC_STATUS1_KEY_C 0x80000000 desc.h 　
25512
 AR5K_RX_DESC_ERROR0AR5K_RX_DESC_ERROR0 0x00000000 desc.h 　
25513
 AR5K_RX_DESC_ERROR1_PHY_ERROR_CAR5K_RX_DESC_ERROR1_PHY_ERROR_C 0x0000ff00 desc.h 　
25514
 AR5K_RX_DESC_ERROR1_PHY_ERROR_CAR5K_RX_DESC_ERROR1_PHY_ERROR_C 8 desc.h 　
25515
 AR5K_DESC_RX_PHY_ERROR_NONEAR5K_DESC_RX_PHY_ERROR_NONE 0x00 desc.h 　
25516
 AR5K_DESC_RX_PHY_ERROR_TIMINGAR5K_DESC_RX_PHY_ERROR_TIMING 0x20 desc.h 　
25517
 AR5K_DESC_RX_PHY_ERROR_PARITYAR5K_DESC_RX_PHY_ERROR_PARITY 0x40 desc.h 　
25518
 AR5K_DESC_RX_PHY_ERROR_RATEAR5K_DESC_RX_PHY_ERROR_RATE 0x60 desc.h 　
25519
 AR5K_DESC_RX_PHY_ERROR_LENGTHAR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 desc.h 　
25520
 AR5K_DESC_RX_PHY_ERROR_64QAMAR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 desc.h 　
25521
 AR5K_DESC_RX_PHY_ERROR_SERVICEAR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 desc.h 　
25522
 AR5K_DESC_RX_PHY_ERROR_TRANSMITAR5K_DESC_RX_PHY_ERROR_TRANSMIT 0xe0 desc.h 　
25523
 AR5K_2W_TX_DESC_CTL0_FRAME_LENAR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff desc.h 　
25524
 AR5K_2W_TX_DESC_CTL0_HEADER_LENAR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 desc.h [5210 ?]
25525
 AR5K_2W_TX_DESC_CTL0_HEADER_LENAR5K_2W_TX_DESC_CTL0_HEADER_LEN 12 desc.h 　
25526
 AR5K_2W_TX_DESC_CTL0_XMIT_RATEAR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 desc.h 　
25527
 AR5K_2W_TX_DESC_CTL0_XMIT_RATE_AR5K_2W_TX_DESC_CTL0_XMIT_RATE_ 18 desc.h 　
25528
 AR5K_2W_TX_DESC_CTL0_RTSENAAR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 desc.h 　
25529
 AR5K_2W_TX_DESC_CTL0_CLRDMASKAR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 desc.h 　
25530
 AR5K_2W_TX_DESC_CTL0_LONG_PACKEAR5K_2W_TX_DESC_CTL0_LONG_PACKE 0x00800000 desc.h [5210]
25531
 AR5K_2W_TX_DESC_CTL0_VEOLAR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 desc.h [5211]
25532
 AR5K_2W_TX_DESC_CTL0_FRAME_TYPEAR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 desc.h [5210]
25533
 AR5K_2W_TX_DESC_CTL0_FRAME_TYPEAR5K_2W_TX_DESC_CTL0_FRAME_TYPE 26 desc.h 　
25534
 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 0x02000000 desc.h 　
25535
 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 0x1e000000 desc.h 　
25536
 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X (ah->ah_version == AR5K_AR5210 ? \ AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) desc.h 　
25537
 AR5K_2W_TX_DESC_CTL0_ANT_MODE_XAR5K_2W_TX_DESC_CTL0_ANT_MODE_X 25 desc.h 　
25538
 AR5K_2W_TX_DESC_CTL0_INTREQAR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 desc.h 　
25539
 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEAR5K_2W_TX_DESC_CTL0_ENCRYPT_KE 0x40000000 desc.h 　
25540
 AR5K_2W_TX_DESC_CTL1_BUF_LENAR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff desc.h 　
25541
 AR5K_2W_TX_DESC_CTL1_MOREAR5K_2W_TX_DESC_CTL1_MORE 0x00001000 desc.h 　
25542
 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 0x0007e000 desc.h 　
25543
 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 0x000fe000 desc.h 　
25544
 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE (ah->ah_version == AR5K_AR5210 ? \ AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_52 desc.h 　
25545
 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEAR5K_2W_TX_DESC_CTL1_ENCRYPT_KE 13 desc.h 　
25546
 AR5K_2W_TX_DESC_CTL1_FRAME_TYPEAR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 desc.h [5211]
25547
 AR5K_2W_TX_DESC_CTL1_FRAME_TYPEAR5K_2W_TX_DESC_CTL1_FRAME_TYPE 20 desc.h 　
25548
 AR5K_2W_TX_DESC_CTL1_NOACKAR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 desc.h [5211]
25549
 AR5K_2W_TX_DESC_CTL1_RTS_DURATIAR5K_2W_TX_DESC_CTL1_RTS_DURATI 0xfff80000 desc.h [5210 ?]
25550
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x00 desc.h 　
25551
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x04 desc.h 　
25552
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x08 desc.h 　
25553
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x0c desc.h 　
25554
 AR5K_AR5210_TX_DESC_FRAME_TYPE_AR5K_AR5210_TX_DESC_FRAME_TYPE_ 0x10 desc.h 　
25555
 AR5K_DESC_TX_STATUS0_FRAME_XMITAR5K_DESC_TX_STATUS0_FRAME_XMIT 0x00000001 desc.h 　
25556
 AR5K_DESC_TX_STATUS0_EXCESSIVE_AR5K_DESC_TX_STATUS0_EXCESSIVE_ 0x00000002 desc.h 　
25557
 AR5K_DESC_TX_STATUS0_FIFO_UNDERAR5K_DESC_TX_STATUS0_FIFO_UNDER 0x00000004 desc.h 　
25558
 AR5K_DESC_TX_STATUS0_FILTEREDAR5K_DESC_TX_STATUS0_FILTERED 0x00000008 desc.h 　
25559
 AR5K_DESC_TX_STATUS0_SHORT_RETRAR5K_DESC_TX_STATUS0_SHORT_RETR 0x000000f0 desc.h 　
25560
 AR5K_DESC_TX_STATUS0_SHORT_RETRAR5K_DESC_TX_STATUS0_SHORT_RETR 4 desc.h 　
25561
 AR5K_DESC_TX_STATUS0_LONG_RETRYAR5K_DESC_TX_STATUS0_LONG_RETRY 0x00000f00 desc.h 　
25562
 AR5K_DESC_TX_STATUS0_LONG_RETRYAR5K_DESC_TX_STATUS0_LONG_RETRY 8 desc.h 　
25563
 AR5K_DESC_TX_STATUS0_VIRT_COLL_AR5K_DESC_TX_STATUS0_VIRT_COLL_ 0x0000f000 desc.h 　
25564
 AR5K_DESC_TX_STATUS0_VIRT_COLL_AR5K_DESC_TX_STATUS0_VIRT_COLL_ 12 desc.h 　
25565
 AR5K_DESC_TX_STATUS0_SEND_TIMESAR5K_DESC_TX_STATUS0_SEND_TIMES 0xffff0000 desc.h 　
25566
 AR5K_DESC_TX_STATUS0_SEND_TIMESAR5K_DESC_TX_STATUS0_SEND_TIMES 16 desc.h 　
25567
 AR5K_DESC_TX_STATUS1_DONEAR5K_DESC_TX_STATUS1_DONE 0x00000001 desc.h 　
25568
 AR5K_DESC_TX_STATUS1_SEQ_NUMAR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe desc.h 　
25569
 AR5K_DESC_TX_STATUS1_SEQ_NUM_SAR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 desc.h 　
25570
 AR5K_DESC_TX_STATUS1_ACK_SIG_STAR5K_DESC_TX_STATUS1_ACK_SIG_ST 0x001fe000 desc.h 　
25571
 AR5K_DESC_TX_STATUS1_ACK_SIG_STAR5K_DESC_TX_STATUS1_ACK_SIG_ST 13 desc.h 　
25572
 AR5K_DESC_TX_STATUS1_FINAL_TS_IAR5K_DESC_TX_STATUS1_FINAL_TS_I 0x00600000 desc.h 　
25573
 AR5K_DESC_TX_STATUS1_FINAL_TS_IAR5K_DESC_TX_STATUS1_FINAL_TS_I 21 desc.h 　
25574
 AR5K_DESC_TX_STATUS1_COMP_SUCCEAR5K_DESC_TX_STATUS1_COMP_SUCCE 0x00800000 desc.h 　
25575
 AR5K_DESC_TX_STATUS1_XMIT_ANTENAR5K_DESC_TX_STATUS1_XMIT_ANTEN 0x01000000 desc.h 　
25576
 AR5K_RXDESC_INTREQAR5K_RXDESC_INTREQ 0x0020 desc.h 　
25577
 AR5K_TXDESC_CLRDMASKAR5K_TXDESC_CLRDMASK 0x0001 desc.h 　
25578
 AR5K_TXDESC_NOACKAR5K_TXDESC_NOACK 0x0002 desc.h [5211+]
25579
 AR5K_TXDESC_RTSENAAR5K_TXDESC_RTSENA 0x0004 desc.h 　
25580
 AR5K_TXDESC_CTSENAAR5K_TXDESC_CTSENA 0x0008 desc.h 　
25581
 AR5K_TXDESC_INTREQAR5K_TXDESC_INTREQ 0x0010 desc.h 　
25582
 AR5K_TXDESC_VEOLAR5K_TXDESC_VEOL 0x0020 desc.h [5211+]
25583
 AR5K_EEPROM_MAGICAR5K_EEPROM_MAGIC 0x003d eeprom.h EEPROM Magic number
25584
 AR5K_EEPROM_MAGIC_VALUEAR5K_EEPROM_MAGIC_VALUE 0x5aa5 eeprom.h Default - found on EEPROM
25585
 AR5K_EEPROM_MAGIC_5212AR5K_EEPROM_MAGIC_5212 0x0000145c eeprom.h 5212
25586
 AR5K_EEPROM_MAGIC_5211AR5K_EEPROM_MAGIC_5211 0x0000145b eeprom.h 5211
25587
 AR5K_EEPROM_MAGIC_5210AR5K_EEPROM_MAGIC_5210 0x0000145a eeprom.h 5210
25588
 AR5K_EEPROM_IS_HB63AR5K_EEPROM_IS_HB63 0x000b eeprom.h Talon detect
25589
 AR5K_EEPROM_RFKILLAR5K_EEPROM_RFKILL 0x0f eeprom.h 　
25590
 AR5K_EEPROM_RFKILL_GPIO_SELAR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c eeprom.h 　
25591
 AR5K_EEPROM_RFKILL_GPIO_SEL_SAR5K_EEPROM_RFKILL_GPIO_SEL_S 2 eeprom.h 　
25592
 AR5K_EEPROM_RFKILL_POLARITYAR5K_EEPROM_RFKILL_POLARITY 0x00000002 eeprom.h 　
25593
 AR5K_EEPROM_RFKILL_POLARITY_SAR5K_EEPROM_RFKILL_POLARITY_S 1 eeprom.h 　
25594
 AR5K_EEPROM_REG_DOMAINAR5K_EEPROM_REG_DOMAIN 0x00bf eeprom.h EEPROM regdom
25595
 AR5K_EEPROM_CHECKSUMAR5K_EEPROM_CHECKSUM 0x00c0 eeprom.h EEPROM checksum
25596
 AR5K_EEPROM_INFO_BASEAR5K_EEPROM_INFO_BASE 0x00c0 eeprom.h EEPROM header
25597
 AR5K_EEPROM_INFO_MAXAR5K_EEPROM_INFO_MAX (0x400 - AR5K_EEPROM_INFO_BASE) eeprom.h 　
25598
 AR5K_EEPROM_INFO_CKSUMAR5K_EEPROM_INFO_CKSUM 0xffff eeprom.h 　
25599
 AR5K_EEPROM_VERSIONAR5K_EEPROM_VERSION AR5K_EEPROM_INFO(1) eeprom.h EEPROM Version
25600
 AR5K_EEPROM_VERSION_3_0AR5K_EEPROM_VERSION_3_0 0x3000 eeprom.h No idea what's going on before this version
25601
 AR5K_EEPROM_VERSION_3_1AR5K_EEPROM_VERSION_3_1 0x3001 eeprom.h ob/db values for 2Ghz (ar5211_rfregs)
25602
 AR5K_EEPROM_VERSION_3_2AR5K_EEPROM_VERSION_3_2 0x3002 eeprom.h different frequency representation (eeprom_bin2freq)
25603
 AR5K_EEPROM_VERSION_3_3AR5K_EEPROM_VERSION_3_3 0x3003 eeprom.h offsets changed, has 32 CTLs (see below) and ee_false_detect (eeprom_read_modes)
25604
 AR5K_EEPROM_VERSION_3_4AR5K_EEPROM_VERSION_3_4 0x3004 eeprom.h has ee_i_gain, ee_cck_ofdm_power_delta (eeprom_read_modes)
25605
 AR5K_EEPROM_VERSION_4_0AR5K_EEPROM_VERSION_4_0 0x4000 eeprom.h has ee_misc, ee_cal_pier, ee_turbo_max_power and ee_xr_power (eeprom_init)
25606
 AR5K_EEPROM_VERSION_4_1AR5K_EEPROM_VERSION_4_1 0x4001 eeprom.h has ee_margin_tx_rx (eeprom_init)
25607
 AR5K_EEPROM_VERSION_4_2AR5K_EEPROM_VERSION_4_2 0x4002 eeprom.h has ee_cck_ofdm_gain_delta (eeprom_init)
25608
 AR5K_EEPROM_VERSION_4_3AR5K_EEPROM_VERSION_4_3 0x4003 eeprom.h power calibration changes
25609
 AR5K_EEPROM_VERSION_4_4AR5K_EEPROM_VERSION_4_4 0x4004 eeprom.h 　
25610
 AR5K_EEPROM_VERSION_4_5AR5K_EEPROM_VERSION_4_5 0x4005 eeprom.h 　
25611
 AR5K_EEPROM_VERSION_4_6AR5K_EEPROM_VERSION_4_6 0x4006 eeprom.h has ee_scaled_cck_delta
25612
 AR5K_EEPROM_VERSION_4_7AR5K_EEPROM_VERSION_4_7 0x3007 eeprom.h 4007 ?
25613
 AR5K_EEPROM_VERSION_4_9AR5K_EEPROM_VERSION_4_9 0x4009 eeprom.h EAR futureproofing
25614
 AR5K_EEPROM_VERSION_5_0AR5K_EEPROM_VERSION_5_0 0x5000 eeprom.h Has 2413 PDADC calibration etc
25615
 AR5K_EEPROM_VERSION_5_1AR5K_EEPROM_VERSION_5_1 0x5001 eeprom.h Has capability values
25616
 AR5K_EEPROM_VERSION_5_3AR5K_EEPROM_VERSION_5_3 0x5003 eeprom.h Has spur mitigation tables
25617
 AR5K_EEPROM_MODE_11AAR5K_EEPROM_MODE_11A 0 eeprom.h 　
25618
 AR5K_EEPROM_MODE_11BAR5K_EEPROM_MODE_11B 1 eeprom.h 　
25619
 AR5K_EEPROM_MODE_11GAR5K_EEPROM_MODE_11G 2 eeprom.h 　
25620
 AR5K_EEPROM_HDRAR5K_EEPROM_HDR AR5K_EEPROM_INFO(2) eeprom.h Header that contains the device caps
25621
 AR5K_EEPROM_RFKILL_GPIO_SELAR5K_EEPROM_RFKILL_GPIO_SEL 0x0000001c eeprom.h 　
25622
 AR5K_EEPROM_RFKILL_GPIO_SEL_SAR5K_EEPROM_RFKILL_GPIO_SEL_S 2 eeprom.h 　
25623
 AR5K_EEPROM_RFKILL_POLARITYAR5K_EEPROM_RFKILL_POLARITY 0x00000002 eeprom.h 　
25624
 AR5K_EEPROM_RFKILL_POLARITY_SAR5K_EEPROM_RFKILL_POLARITY_S 1 eeprom.h 　
25625
 AR5K_EEPROM_MISC0AR5K_EEPROM_MISC0 AR5K_EEPROM_INFO(4) eeprom.h 　
25626
 AR5K_EEPROM_MISC1AR5K_EEPROM_MISC1 AR5K_EEPROM_INFO(5) eeprom.h 　
25627
 AR5K_EEPROM_MISC2AR5K_EEPROM_MISC2 AR5K_EEPROM_INFO(6) eeprom.h 　
25628
 AR5K_EEPROM_MISC3AR5K_EEPROM_MISC3 AR5K_EEPROM_INFO(7) eeprom.h 　
25629
 AR5K_EEPROM_MISC4AR5K_EEPROM_MISC4 AR5K_EEPROM_INFO(8) eeprom.h 　
25630
 AR5K_EEPROM_MISC5AR5K_EEPROM_MISC5 AR5K_EEPROM_INFO(9) eeprom.h 　
25631
 AR5K_EEPROM_MISC6AR5K_EEPROM_MISC6 AR5K_EEPROM_INFO(10) eeprom.h 　
25632
 AR5K_EEPROM_TX_CHAIN_DISAR5K_EEPROM_TX_CHAIN_DIS ((_v) & 0x8) eeprom.h 　
25633
 AR5K_EEPROM_RX_CHAIN_DISAR5K_EEPROM_RX_CHAIN_DIS (((_v) >> 3) & 0x8) eeprom.h 　
25634
 AR5K_EEPROM_FCC_MID_ENAR5K_EEPROM_FCC_MID_EN (((_v) >> 6) & 0x1) eeprom.h 　
25635
 AR5K_EEPROM_JAP_U1EVEN_ENAR5K_EEPROM_JAP_U1EVEN_EN (((_v) >> 7) & 0x1) eeprom.h 　
25636
 AR5K_EEPROM_JAP_U2_ENAR5K_EEPROM_JAP_U2_EN (((_v) >> 8) & 0x1) eeprom.h 　
25637
 AR5K_EEPROM_JAP_U1ODD_ENAR5K_EEPROM_JAP_U1ODD_EN (((_v) >> 9) & 0x1) eeprom.h 　
25638
 AR5K_EEPROM_JAP_11A_NEW_ENAR5K_EEPROM_JAP_11A_NEW_EN (((_v) >> 10) & 0x1) eeprom.h 　
25639
 AR5K_EEPROM_GROUP1_OFFSETAR5K_EEPROM_GROUP1_OFFSET 0x0 eeprom.h 　
25640
 AR5K_EEPROM_GROUP2_OFFSETAR5K_EEPROM_GROUP2_OFFSET 0x5 eeprom.h 　
25641
 AR5K_EEPROM_GROUP3_OFFSETAR5K_EEPROM_GROUP3_OFFSET 0x37 eeprom.h 　
25642
 AR5K_EEPROM_GROUP4_OFFSETAR5K_EEPROM_GROUP4_OFFSET 0x46 eeprom.h 　
25643
 AR5K_EEPROM_GROUP5_OFFSETAR5K_EEPROM_GROUP5_OFFSET 0x55 eeprom.h 　
25644
 AR5K_EEPROM_GROUP6_OFFSETAR5K_EEPROM_GROUP6_OFFSET 0x65 eeprom.h 　
25645
 AR5K_EEPROM_GROUP7_OFFSETAR5K_EEPROM_GROUP7_OFFSET 0x69 eeprom.h 　
25646
 AR5K_EEPROM_GROUP8_OFFSETAR5K_EEPROM_GROUP8_OFFSET 0x6f eeprom.h 　
25647
 AR5K_EEPROM_OBDB0_2GHZAR5K_EEPROM_OBDB0_2GHZ 0x00ec eeprom.h 　
25648
 AR5K_EEPROM_OBDB1_2GHZAR5K_EEPROM_OBDB1_2GHZ 0x00ed eeprom.h 　
25649
 AR5K_EEPROM_PROTECTAR5K_EEPROM_PROTECT 0x003f eeprom.h EEPROM protect status
25650
 AR5K_EEPROM_PROTECT_RD_0_31AR5K_EEPROM_PROTECT_RD_0_31 0x0001 eeprom.h Read protection bit for offsets 0x0 - 0x1f
25651
 AR5K_EEPROM_PROTECT_WR_0_31AR5K_EEPROM_PROTECT_WR_0_31 0x0002 eeprom.h Write protection bit for offsets 0x0 - 0x1f
25652
 AR5K_EEPROM_PROTECT_RD_32_63AR5K_EEPROM_PROTECT_RD_32_63 0x0004 eeprom.h 0x20 - 0x3f
25653
 AR5K_EEPROM_PROTECT_WR_32_63AR5K_EEPROM_PROTECT_WR_32_63 0x0008 eeprom.h 　
25654
 AR5K_EEPROM_PROTECT_RD_64_127AR5K_EEPROM_PROTECT_RD_64_127 0x0010 eeprom.h 0x40 - 0x7f
25655
 AR5K_EEPROM_PROTECT_WR_64_127AR5K_EEPROM_PROTECT_WR_64_127 0x0020 eeprom.h 　
25656
 AR5K_EEPROM_PROTECT_RD_128_191AR5K_EEPROM_PROTECT_RD_128_191 0x0040 eeprom.h 0x80 - 0xbf (regdom)
25657
 AR5K_EEPROM_PROTECT_WR_128_191AR5K_EEPROM_PROTECT_WR_128_191 0x0080 eeprom.h 　
25658
 AR5K_EEPROM_PROTECT_RD_192_207AR5K_EEPROM_PROTECT_RD_192_207 0x0100 eeprom.h 0xc0 - 0xcf
25659
 AR5K_EEPROM_PROTECT_WR_192_207AR5K_EEPROM_PROTECT_WR_192_207 0x0200 eeprom.h 　
25660
 AR5K_EEPROM_PROTECT_RD_208_223AR5K_EEPROM_PROTECT_RD_208_223 0x0400 eeprom.h 0xd0 - 0xdf
25661
 AR5K_EEPROM_PROTECT_WR_208_223AR5K_EEPROM_PROTECT_WR_208_223 0x0800 eeprom.h 　
25662
 AR5K_EEPROM_PROTECT_RD_224_239AR5K_EEPROM_PROTECT_RD_224_239 0x1000 eeprom.h 0xe0 - 0xef
25663
 AR5K_EEPROM_PROTECT_WR_224_239AR5K_EEPROM_PROTECT_WR_224_239 0x2000 eeprom.h 　
25664
 AR5K_EEPROM_PROTECT_RD_240_255AR5K_EEPROM_PROTECT_RD_240_255 0x4000 eeprom.h 0xf0 - 0xff
25665
 AR5K_EEPROM_PROTECT_WR_240_255AR5K_EEPROM_PROTECT_WR_240_255 0x8000 eeprom.h 　
25666
 AR5K_EEPROM_EEP_SCALEAR5K_EEPROM_EEP_SCALE 100 eeprom.h 　
25667
 AR5K_EEPROM_EEP_DELTAAR5K_EEPROM_EEP_DELTA 10 eeprom.h 　
25668
 AR5K_EEPROM_N_MODESAR5K_EEPROM_N_MODES 3 eeprom.h 　
25669
 AR5K_EEPROM_N_5GHZ_CHANAR5K_EEPROM_N_5GHZ_CHAN 10 eeprom.h 　
25670
 AR5K_EEPROM_N_2GHZ_CHANAR5K_EEPROM_N_2GHZ_CHAN 3 eeprom.h 　
25671
 AR5K_EEPROM_N_2GHZ_CHAN_2413AR5K_EEPROM_N_2GHZ_CHAN_2413 4 eeprom.h 　
25672
 AR5K_EEPROM_N_2GHZ_CHAN_MAXAR5K_EEPROM_N_2GHZ_CHAN_MAX 4 eeprom.h 　
25673
 AR5K_EEPROM_MAX_CHANAR5K_EEPROM_MAX_CHAN 10 eeprom.h 　
25674
 AR5K_EEPROM_N_PWR_POINTS_5111AR5K_EEPROM_N_PWR_POINTS_5111 11 eeprom.h 　
25675
 AR5K_EEPROM_N_PCDACAR5K_EEPROM_N_PCDAC 11 eeprom.h 　
25676
 AR5K_EEPROM_N_PHASE_CALAR5K_EEPROM_N_PHASE_CAL 5 eeprom.h 　
25677
 AR5K_EEPROM_N_TEST_FREQAR5K_EEPROM_N_TEST_FREQ 8 eeprom.h 　
25678
 AR5K_EEPROM_N_EDGESAR5K_EEPROM_N_EDGES 8 eeprom.h 　
25679
 AR5K_EEPROM_N_INTERCEPTSAR5K_EEPROM_N_INTERCEPTS 11 eeprom.h 　
25680
 AR5K_EEPROM_PCDAC_MAR5K_EEPROM_PCDAC_M 0x3f eeprom.h 　
25681
 AR5K_EEPROM_PCDAC_STARTAR5K_EEPROM_PCDAC_START 1 eeprom.h 　
25682
 AR5K_EEPROM_PCDAC_STOPAR5K_EEPROM_PCDAC_STOP 63 eeprom.h 　
25683
 AR5K_EEPROM_PCDAC_STEPAR5K_EEPROM_PCDAC_STEP 1 eeprom.h 　
25684
 AR5K_EEPROM_NON_EDGE_MAR5K_EEPROM_NON_EDGE_M 0x40 eeprom.h 　
25685
 AR5K_EEPROM_CHANNEL_POWERAR5K_EEPROM_CHANNEL_POWER 8 eeprom.h 　
25686
 AR5K_EEPROM_N_OBDBAR5K_EEPROM_N_OBDB 4 eeprom.h 　
25687
 AR5K_EEPROM_OBDB_DISAR5K_EEPROM_OBDB_DIS 0xffff eeprom.h 　
25688
 AR5K_EEPROM_CHANNEL_DISAR5K_EEPROM_CHANNEL_DIS 0xff eeprom.h 　
25689
 AR5K_EEPROM_MAX_CTLSAR5K_EEPROM_MAX_CTLS 32 eeprom.h 　
25690
 AR5K_EEPROM_N_PD_CURVESAR5K_EEPROM_N_PD_CURVES 4 eeprom.h 　
25691
 AR5K_EEPROM_N_XPD0_POINTSAR5K_EEPROM_N_XPD0_POINTS 4 eeprom.h 　
25692
 AR5K_EEPROM_N_XPD3_POINTSAR5K_EEPROM_N_XPD3_POINTS 3 eeprom.h 　
25693
 AR5K_EEPROM_N_PD_GAINSAR5K_EEPROM_N_PD_GAINS 4 eeprom.h 　
25694
 AR5K_EEPROM_N_PD_POINTSAR5K_EEPROM_N_PD_POINTS 5 eeprom.h 　
25695
 AR5K_EEPROM_N_INTERCEPT_10_2GHZAR5K_EEPROM_N_INTERCEPT_10_2GHZ 35 eeprom.h 　
25696
 AR5K_EEPROM_N_INTERCEPT_10_5GHZAR5K_EEPROM_N_INTERCEPT_10_5GHZ 55 eeprom.h 　
25697
 AR5K_EEPROM_POWER_MAR5K_EEPROM_POWER_M 0x3f eeprom.h 　
25698
 AR5K_EEPROM_POWER_MINAR5K_EEPROM_POWER_MIN 0 eeprom.h 　
25699
 AR5K_EEPROM_POWER_MAXAR5K_EEPROM_POWER_MAX 3150 eeprom.h 　
25700
 AR5K_EEPROM_POWER_STEPAR5K_EEPROM_POWER_STEP 50 eeprom.h 　
25701
 AR5K_EEPROM_POWER_TABLE_SIZEAR5K_EEPROM_POWER_TABLE_SIZE 64 eeprom.h 　
25702
 AR5K_EEPROM_N_POWER_LOC_11BAR5K_EEPROM_N_POWER_LOC_11B 4 eeprom.h 　
25703
 AR5K_EEPROM_N_POWER_LOC_11GAR5K_EEPROM_N_POWER_LOC_11G 6 eeprom.h 　
25704
 AR5K_EEPROM_I_GAINAR5K_EEPROM_I_GAIN 10 eeprom.h 　
25705
 AR5K_EEPROM_CCK_OFDM_DELTAAR5K_EEPROM_CCK_OFDM_DELTA 15 eeprom.h 　
25706
 AR5K_EEPROM_N_IQ_CALAR5K_EEPROM_N_IQ_CAL 2 eeprom.h 　
25707
 AR5K_CTL_FCCAR5K_CTL_FCC 0x10 eeprom.h 　
25708
 AR5K_CTL_CUSTOMAR5K_CTL_CUSTOM 0x20 eeprom.h 　
25709
 AR5K_CTL_ETSIAR5K_CTL_ETSI 0x30 eeprom.h 　
25710
 AR5K_CTL_MKKAR5K_CTL_MKK 0x40 eeprom.h 　
25711
 AR5K_CTL_NO_REGDOMAINAR5K_CTL_NO_REGDOMAIN 0xf0 eeprom.h 　
25712
 AR5K_CTL_NO_CTLAR5K_CTL_NO_CTL 0xff eeprom.h 　
25713
 AR5K_NOQCU_TXDP0AR5K_NOQCU_TXDP0 0x0000 reg.h Queue 0 - data
25714
 AR5K_NOQCU_TXDP1AR5K_NOQCU_TXDP1 0x0004 reg.h Queue 1 - beacons
25715
 AR5K_CRAR5K_CR 0x0008 reg.h Register Address
25716
 AR5K_CR_TXE0AR5K_CR_TXE0 0x00000001 reg.h TX Enable for queue 0 on 5210
25717
 AR5K_CR_TXE1AR5K_CR_TXE1 0x00000002 reg.h TX Enable for queue 1 on 5210
25718
 AR5K_CR_RXEAR5K_CR_RXE 0x00000004 reg.h RX Enable
25719
 AR5K_CR_TXD0AR5K_CR_TXD0 0x00000008 reg.h TX Disable for queue 0 on 5210
25720
 AR5K_CR_TXD1AR5K_CR_TXD1 0x00000010 reg.h TX Disable for queue 1 on 5210
25721
 AR5K_CR_RXDAR5K_CR_RXD 0x00000020 reg.h RX Disable
25722
 AR5K_CR_SWIAR5K_CR_SWI 0x00000040 reg.h Software Interrupt
25723
 AR5K_RXDPAR5K_RXDP 0x000c reg.h 　
25724
 AR5K_CFGAR5K_CFG 0x0014 reg.h Register Address
25725
 AR5K_CFG_SWTDAR5K_CFG_SWTD 0x00000001 reg.h Byte-swap TX descriptor (for big endian archs)
25726
 AR5K_CFG_SWTBAR5K_CFG_SWTB 0x00000002 reg.h Byte-swap TX buffer
25727
 AR5K_CFG_SWRDAR5K_CFG_SWRD 0x00000004 reg.h Byte-swap RX descriptor
25728
 AR5K_CFG_SWRBAR5K_CFG_SWRB 0x00000008 reg.h Byte-swap RX buffer
25729
 AR5K_CFG_SWRGAR5K_CFG_SWRG 0x00000010 reg.h Byte-swap Register access
25730
 AR5K_CFG_IBSSAR5K_CFG_IBSS 0x00000020 reg.h 0-BSS, 1-IBSS [5211+]
25731
 AR5K_CFG_PHY_OKAR5K_CFG_PHY_OK 0x00000100 reg.h [5211+]
25732
 AR5K_CFG_EEBSAR5K_CFG_EEBS 0x00000200 reg.h EEPROM is busy
25733
 AR5K_CFG_CLKGDAR5K_CFG_CLKGD 0x00000400 reg.h Clock gated (Disable dynamic clock)
25734
 AR5K_CFG_TXCNTAR5K_CFG_TXCNT 0x00007800 reg.h Tx frame count (?) [5210]
25735
 AR5K_CFG_TXCNT_SAR5K_CFG_TXCNT_S 11 reg.h 　
25736
 AR5K_CFG_TXFSTATAR5K_CFG_TXFSTAT 0x00008000 reg.h Tx frame status (?) [5210]
25737
 AR5K_CFG_TXFSTRTAR5K_CFG_TXFSTRT 0x00010000 reg.h [5210]
25738
 AR5K_CFG_PCI_THRESAR5K_CFG_PCI_THRES 0x00060000 reg.h PCI Master req q threshold [5211+]
25739
 AR5K_CFG_PCI_THRES_SAR5K_CFG_PCI_THRES_S 17 reg.h 　
25740
 AR5K_IERAR5K_IER 0x0024 reg.h Register Address
25741
 AR5K_IER_DISABLEAR5K_IER_DISABLE 0x00000000 reg.h Disable card interrupts
25742
 AR5K_IER_ENABLEAR5K_IER_ENABLE 0x00000001 reg.h Enable card interrupts
25743
 AR5K_BCRAR5K_BCR 0x0028 reg.h Register Address
25744
 AR5K_BCR_APAR5K_BCR_AP 0x00000000 reg.h AP mode
25745
 AR5K_BCR_ADHOCAR5K_BCR_ADHOC 0x00000001 reg.h Ad-Hoc mode
25746
 AR5K_BCR_BDMAEAR5K_BCR_BDMAE 0x00000002 reg.h DMA enable
25747
 AR5K_BCR_TQ1FVAR5K_BCR_TQ1FV 0x00000004 reg.h Use Queue1 for CAB traffic
25748
 AR5K_BCR_TQ1VAR5K_BCR_TQ1V 0x00000008 reg.h Use Queue1 for Beacon traffic
25749
 AR5K_BCR_BCGETAR5K_BCR_BCGET 0x00000010 reg.h 　
25750
 AR5K_RTSD0AR5K_RTSD0 0x0028 reg.h Register Address
25751
 AR5K_RTSD0_6AR5K_RTSD0_6 0x000000ff reg.h 6Mb RTS duration mask (?)
25752
 AR5K_RTSD0_6_SAR5K_RTSD0_6_S 0 reg.h 6Mb RTS duration shift (?)
25753
 AR5K_RTSD0_9AR5K_RTSD0_9 0x0000ff00 reg.h 9Mb
25754
 AR5K_RTSD0_9_SAR5K_RTSD0_9_S 8 reg.h 　
25755
 AR5K_RTSD0_12AR5K_RTSD0_12 0x00ff0000 reg.h 12Mb
25756
 AR5K_RTSD0_12_SAR5K_RTSD0_12_S 16 reg.h 　
25757
 AR5K_RTSD0_18AR5K_RTSD0_18 0xff000000 reg.h 16Mb
25758
 AR5K_RTSD0_18_SAR5K_RTSD0_18_S 24 reg.h 　
25759
 AR5K_BSRAR5K_BSR 0x002c reg.h Register Address
25760
 AR5K_BSR_BDLYSWAR5K_BSR_BDLYSW 0x00000001 reg.h SW Beacon delay (?)
25761
 AR5K_BSR_BDLYDMAAR5K_BSR_BDLYDMA 0x00000002 reg.h DMA Beacon delay (?)
25762
 AR5K_BSR_TXQ1FAR5K_BSR_TXQ1F 0x00000004 reg.h Beacon queue (1) finished
25763
 AR5K_BSR_ATIMDLYAR5K_BSR_ATIMDLY 0x00000008 reg.h ATIM delay (?)
25764
 AR5K_BSR_SNPADHOCAR5K_BSR_SNPADHOC 0x00000100 reg.h Ad-hoc mode set (?)
25765
 AR5K_BSR_SNPBDMAEAR5K_BSR_SNPBDMAE 0x00000200 reg.h Beacon DMA enabled (?)
25766
 AR5K_BSR_SNPTQ1FVAR5K_BSR_SNPTQ1FV 0x00000400 reg.h Queue1 is used for CAB traffic (?)
25767
 AR5K_BSR_SNPTQ1VAR5K_BSR_SNPTQ1V 0x00000800 reg.h Queue1 is used for Beacon traffic (?)
25768
 AR5K_BSR_SNAPSHOTSVALIDAR5K_BSR_SNAPSHOTSVALID 0x00001000 reg.h BCR snapshots are valid (?)
25769
 AR5K_BSR_SWBA_CNTAR5K_BSR_SWBA_CNT 0x00ff0000 reg.h 　
25770
 AR5K_RTSD1AR5K_RTSD1 0x002c reg.h Register Address
25771
 AR5K_RTSD1_24AR5K_RTSD1_24 0x000000ff reg.h 24Mb
25772
 AR5K_RTSD1_24_SAR5K_RTSD1_24_S 0 reg.h 　
25773
 AR5K_RTSD1_36AR5K_RTSD1_36 0x0000ff00 reg.h 36Mb
25774
 AR5K_RTSD1_36_SAR5K_RTSD1_36_S 8 reg.h 　
25775
 AR5K_RTSD1_48AR5K_RTSD1_48 0x00ff0000 reg.h 48Mb
25776
 AR5K_RTSD1_48_SAR5K_RTSD1_48_S 16 reg.h 　
25777
 AR5K_RTSD1_54AR5K_RTSD1_54 0xff000000 reg.h 54Mb
25778
 AR5K_RTSD1_54_SAR5K_RTSD1_54_S 24 reg.h 　
25779
 AR5K_TXCFGAR5K_TXCFG 0x0030 reg.h Register Address
25780
 AR5K_TXCFG_SDMAMRAR5K_TXCFG_SDMAMR 0x00000007 reg.h DMA size (read)
25781
 AR5K_TXCFG_SDMAMR_SAR5K_TXCFG_SDMAMR_S 0 reg.h 　
25782
 AR5K_TXCFG_B_MODEAR5K_TXCFG_B_MODE 0x00000008 reg.h Set b mode for 5111 (enable 2111)
25783
 AR5K_TXCFG_TXFSTPAR5K_TXCFG_TXFSTP 0x00000008 reg.h TX DMA full Stop [5210]
25784
 AR5K_TXCFG_TXFULLAR5K_TXCFG_TXFULL 0x000003f0 reg.h TX Triger level mask
25785
 AR5K_TXCFG_TXFULL_SAR5K_TXCFG_TXFULL_S 4 reg.h 　
25786
 AR5K_TXCFG_TXFULL_0BAR5K_TXCFG_TXFULL_0B 0x00000000 reg.h 　
25787
 AR5K_TXCFG_TXFULL_64BAR5K_TXCFG_TXFULL_64B 0x00000010 reg.h 　
25788
 AR5K_TXCFG_TXFULL_128BAR5K_TXCFG_TXFULL_128B 0x00000020 reg.h 　
25789
 AR5K_TXCFG_TXFULL_192BAR5K_TXCFG_TXFULL_192B 0x00000030 reg.h 　
25790
 AR5K_TXCFG_TXFULL_256BAR5K_TXCFG_TXFULL_256B 0x00000040 reg.h 　
25791
 AR5K_TXCFG_TXCONT_ENAR5K_TXCFG_TXCONT_EN 0x00000080 reg.h 　
25792
 AR5K_TXCFG_DMASIZEAR5K_TXCFG_DMASIZE 0x00000100 reg.h Flag for passing DMA size [5210]
25793
 AR5K_TXCFG_JUMBO_DESC_ENAR5K_TXCFG_JUMBO_DESC_EN 0x00000400 reg.h Enable jumbo tx descriptors [5211+]
25794
 AR5K_TXCFG_ADHOC_BCN_ATIMAR5K_TXCFG_ADHOC_BCN_ATIM 0x00000800 reg.h Adhoc Beacon ATIM Policy
25795
 AR5K_TXCFG_ATIM_WINDOW_DEF_DISAR5K_TXCFG_ATIM_WINDOW_DEF_DIS 0x00001000 reg.h Disable ATIM window defer [5211+]
25796
 AR5K_TXCFG_RTSRNDAR5K_TXCFG_RTSRND 0x00001000 reg.h [5211+]
25797
 AR5K_TXCFG_FRMPAD_DISAR5K_TXCFG_FRMPAD_DIS 0x00002000 reg.h [5211+]
25798
 AR5K_TXCFG_RDY_CBR_DISAR5K_TXCFG_RDY_CBR_DIS 0x00004000 reg.h Ready time CBR disable [5211+]
25799
 AR5K_TXCFG_JUMBO_FRM_MODEAR5K_TXCFG_JUMBO_FRM_MODE 0x00008000 reg.h Jumbo frame mode [5211+]
25800
 AR5K_TXCFG_DCU_DBL_BUF_DISAR5K_TXCFG_DCU_DBL_BUF_DIS 0x00008000 reg.h Disable double buffering on DCU
25801
 AR5K_TXCFG_DCU_CACHING_DISAR5K_TXCFG_DCU_CACHING_DIS 0x00010000 reg.h Disable DCU caching
25802
 AR5K_RXCFGAR5K_RXCFG 0x0034 reg.h Register Address
25803
 AR5K_RXCFG_SDMAMWAR5K_RXCFG_SDMAMW 0x00000007 reg.h DMA size (write)
25804
 AR5K_RXCFG_SDMAMW_SAR5K_RXCFG_SDMAMW_S 0 reg.h 　
25805
 AR5K_RXCFG_ZLFDMAAR5K_RXCFG_ZLFDMA 0x00000008 reg.h Enable Zero-length frame DMA
25806
 AR5K_RXCFG_DEF_ANTENNAAR5K_RXCFG_DEF_ANTENNA 0x00000010 reg.h Default antenna (?)
25807
 AR5K_RXCFG_JUMBO_RXEAR5K_RXCFG_JUMBO_RXE 0x00000020 reg.h Enable jumbo rx descriptors [5211+]
25808
 AR5K_RXCFG_JUMBO_WRAPAR5K_RXCFG_JUMBO_WRAP 0x00000040 reg.h Wrap jumbo frames [5211+]
25809
 AR5K_RXCFG_SLE_ENTRYAR5K_RXCFG_SLE_ENTRY 0x00000080 reg.h Sleep entry policy
25810
 AR5K_RXJLAAR5K_RXJLA 0x0038 reg.h 　
25811
 AR5K_MIBCAR5K_MIBC 0x0040 reg.h Register Address
25812
 AR5K_MIBC_COWAR5K_MIBC_COW 0x00000001 reg.h Warn test indicator
25813
 AR5K_MIBC_FMCAR5K_MIBC_FMC 0x00000002 reg.h Freeze MIB Counters
25814
 AR5K_MIBC_CMCAR5K_MIBC_CMC 0x00000004 reg.h Clean MIB Counters
25815
 AR5K_MIBC_MCSAR5K_MIBC_MCS 0x00000008 reg.h MIB counter strobe
25816
 AR5K_TOPSAR5K_TOPS 0x0044 reg.h 　
25817
 AR5K_TOPS_MAR5K_TOPS_M 0x0000ffff reg.h 　
25818
 AR5K_RXNOFRMAR5K_RXNOFRM 0x0048 reg.h 　
25819
 AR5K_RXNOFRM_MAR5K_RXNOFRM_M 0x000003ff reg.h 　
25820
 AR5K_TXNOFRMAR5K_TXNOFRM 0x004c reg.h 　
25821
 AR5K_TXNOFRM_MAR5K_TXNOFRM_M 0x000003ff reg.h 　
25822
 AR5K_TXNOFRM_QCUAR5K_TXNOFRM_QCU 0x000ffc00 reg.h 　
25823
 AR5K_TXNOFRM_QCU_SAR5K_TXNOFRM_QCU_S 10 reg.h 　
25824
 AR5K_RPGTOAR5K_RPGTO 0x0050 reg.h 　
25825
 AR5K_RPGTO_MAR5K_RPGTO_M 0x000003ff reg.h 　
25826
 AR5K_RFCNTAR5K_RFCNT 0x0054 reg.h 　
25827
 AR5K_RFCNT_MAR5K_RFCNT_M 0x0000001f reg.h [5211+] (?)
25828
 AR5K_RFCNT_RFCLAR5K_RFCNT_RFCL 0x0000000f reg.h [5210]
25829
 AR5K_MISCAR5K_MISC 0x0058 reg.h Register Address
25830
 AR5K_MISC_DMA_OBS_MAR5K_MISC_DMA_OBS_M 0x000001e0 reg.h 　
25831
 AR5K_MISC_DMA_OBS_SAR5K_MISC_DMA_OBS_S 5 reg.h 　
25832
 AR5K_MISC_MISC_OBS_MAR5K_MISC_MISC_OBS_M 0x00000e00 reg.h 　
25833
 AR5K_MISC_MISC_OBS_SAR5K_MISC_MISC_OBS_S 9 reg.h 　
25834
 AR5K_MISC_MAC_OBS_LSB_MAR5K_MISC_MAC_OBS_LSB_M 0x00007000 reg.h 　
25835
 AR5K_MISC_MAC_OBS_LSB_SAR5K_MISC_MAC_OBS_LSB_S 12 reg.h 　
25836
 AR5K_MISC_MAC_OBS_MSB_MAR5K_MISC_MAC_OBS_MSB_M 0x00038000 reg.h 　
25837
 AR5K_MISC_MAC_OBS_MSB_SAR5K_MISC_MAC_OBS_MSB_S 15 reg.h 　
25838
 AR5K_MISC_LED_DECAYAR5K_MISC_LED_DECAY 0x001c0000 reg.h [5210]
25839
 AR5K_MISC_LED_BLINKAR5K_MISC_LED_BLINK 0x00e00000 reg.h [5210]
25840
 AR5K_QCUDCU_CLKGTAR5K_QCUDCU_CLKGT 0x005c reg.h Register Address (?)
25841
 AR5K_QCUDCU_CLKGT_QCUAR5K_QCUDCU_CLKGT_QCU 0x0000ffff reg.h Mask for QCU clock
25842
 AR5K_QCUDCU_CLKGT_DCUAR5K_QCUDCU_CLKGT_DCU 0x07ff0000 reg.h Mask for DCU clock
25843
 AR5K_ISRAR5K_ISR 0x001c reg.h Register Address [5210]
25844
 AR5K_PISRAR5K_PISR 0x0080 reg.h Register Address [5211+]
25845
 AR5K_ISR_RXOKAR5K_ISR_RXOK 0x00000001 reg.h Frame successfuly recieved
25846
 AR5K_ISR_RXDESCAR5K_ISR_RXDESC 0x00000002 reg.h RX descriptor request
25847
 AR5K_ISR_RXERRAR5K_ISR_RXERR 0x00000004 reg.h Receive error
25848
 AR5K_ISR_RXNOFRMAR5K_ISR_RXNOFRM 0x00000008 reg.h No frame received (receive timeout)
25849
 AR5K_ISR_RXEOLAR5K_ISR_RXEOL 0x00000010 reg.h Empty RX descriptor
25850
 AR5K_ISR_RXORNAR5K_ISR_RXORN 0x00000020 reg.h Receive FIFO overrun
25851
 AR5K_ISR_TXOKAR5K_ISR_TXOK 0x00000040 reg.h Frame successfuly transmited
25852
 AR5K_ISR_TXDESCAR5K_ISR_TXDESC 0x00000080 reg.h TX descriptor request
25853
 AR5K_ISR_TXERRAR5K_ISR_TXERR 0x00000100 reg.h Transmit error
25854
 AR5K_ISR_TXNOFRMAR5K_ISR_TXNOFRM 0x00000200 reg.h No frame transmited (transmit timeout)
25855
 AR5K_ISR_TXEOLAR5K_ISR_TXEOL 0x00000400 reg.h Empty TX descriptor
25856
 AR5K_ISR_TXURNAR5K_ISR_TXURN 0x00000800 reg.h Transmit FIFO underrun
25857
 AR5K_ISR_MIBAR5K_ISR_MIB 0x00001000 reg.h Update MIB counters
25858
 AR5K_ISR_SWIAR5K_ISR_SWI 0x00002000 reg.h Software interrupt
25859
 AR5K_ISR_RXPHYAR5K_ISR_RXPHY 0x00004000 reg.h PHY error
25860
 AR5K_ISR_RXKCMAR5K_ISR_RXKCM 0x00008000 reg.h RX Key cache miss
25861
 AR5K_ISR_SWBAAR5K_ISR_SWBA 0x00010000 reg.h Software beacon alert
25862
 AR5K_ISR_BRSSIAR5K_ISR_BRSSI 0x00020000 reg.h Beacon rssi below threshold (?)
25863
 AR5K_ISR_BMISSAR5K_ISR_BMISS 0x00040000 reg.h Beacon missed
25864
 AR5K_ISR_HIUERRAR5K_ISR_HIUERR 0x00080000 reg.h Host Interface Unit error [5211+]
25865
 AR5K_ISR_BNRAR5K_ISR_BNR 0x00100000 reg.h Beacon not ready [5211+]
25866
 AR5K_ISR_MCABTAR5K_ISR_MCABT 0x00100000 reg.h Master Cycle Abort [5210]
25867
 AR5K_ISR_RXCHIRPAR5K_ISR_RXCHIRP 0x00200000 reg.h CHIRP Received [5212+]
25868
 AR5K_ISR_SSERRAR5K_ISR_SSERR 0x00200000 reg.h Signaled System Error [5210]
25869
 AR5K_ISR_DPERRAR5K_ISR_DPERR 0x00400000 reg.h Det par Error (?) [5210]
25870
 AR5K_ISR_RXDOPPLERAR5K_ISR_RXDOPPLER 0x00400000 reg.h Doppler chirp received [5212+]
25871
 AR5K_ISR_TIMAR5K_ISR_TIM 0x00800000 reg.h [5211+]
25872
 AR5K_ISR_BCNMISCAR5K_ISR_BCNMISC 0x00800000 reg.h 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
25873
 AR5K_ISR_GPIOAR5K_ISR_GPIO 0x01000000 reg.h GPIO (rf kill)
25874
 AR5K_ISR_QCBRORNAR5K_ISR_QCBRORN 0x02000000 reg.h QCU CBR overrun [5211+]
25875
 AR5K_ISR_QCBRURNAR5K_ISR_QCBRURN 0x04000000 reg.h QCU CBR underrun [5211+]
25876
 AR5K_ISR_QTRIGAR5K_ISR_QTRIG 0x08000000 reg.h QCU scheduling trigger [5211+]
25877
 AR5K_SISR0AR5K_SISR0 0x0084 reg.h Register Address [5211+]
25878
 AR5K_SISR0_QCU_TXOKAR5K_SISR0_QCU_TXOK 0x000003ff reg.h Mask for QCU_TXOK
25879
 AR5K_SISR0_QCU_TXOK_SAR5K_SISR0_QCU_TXOK_S 0 reg.h 　
25880
 AR5K_SISR0_QCU_TXDESCAR5K_SISR0_QCU_TXDESC 0x03ff0000 reg.h Mask for QCU_TXDESC
25881
 AR5K_SISR0_QCU_TXDESC_SAR5K_SISR0_QCU_TXDESC_S 16 reg.h 　
25882
 AR5K_SISR1AR5K_SISR1 0x0088 reg.h Register Address [5211+]
25883
 AR5K_SISR1_QCU_TXERRAR5K_SISR1_QCU_TXERR 0x000003ff reg.h Mask for QCU_TXERR
25884
 AR5K_SISR1_QCU_TXERR_SAR5K_SISR1_QCU_TXERR_S 0 reg.h 　
25885
 AR5K_SISR1_QCU_TXEOLAR5K_SISR1_QCU_TXEOL 0x03ff0000 reg.h Mask for QCU_TXEOL
25886
 AR5K_SISR1_QCU_TXEOL_SAR5K_SISR1_QCU_TXEOL_S 16 reg.h 　
25887
 AR5K_SISR2AR5K_SISR2 0x008c reg.h Register Address [5211+]
25888
 AR5K_SISR2_QCU_TXURNAR5K_SISR2_QCU_TXURN 0x000003ff reg.h Mask for QCU_TXURN
25889
 AR5K_SISR2_QCU_TXURN_SAR5K_SISR2_QCU_TXURN_S 0 reg.h 　
25890
 AR5K_SISR2_MCABTAR5K_SISR2_MCABT 0x00100000 reg.h Master Cycle Abort
25891
 AR5K_SISR2_SSERRAR5K_SISR2_SSERR 0x00200000 reg.h Signaled System Error
25892
 AR5K_SISR2_DPERRAR5K_SISR2_DPERR 0x00400000 reg.h Bus parity error
25893
 AR5K_SISR2_TIMAR5K_SISR2_TIM 0x01000000 reg.h [5212+]
25894
 AR5K_SISR2_CAB_ENDAR5K_SISR2_CAB_END 0x02000000 reg.h [5212+]
25895
 AR5K_SISR2_DTIM_SYNCAR5K_SISR2_DTIM_SYNC 0x04000000 reg.h DTIM sync lost [5212+]
25896
 AR5K_SISR2_BCN_TIMEOUTAR5K_SISR2_BCN_TIMEOUT 0x08000000 reg.h Beacon Timeout [5212+]
25897
 AR5K_SISR2_CAB_TIMEOUTAR5K_SISR2_CAB_TIMEOUT 0x10000000 reg.h CAB Timeout [5212+]
25898
 AR5K_SISR2_DTIMAR5K_SISR2_DTIM 0x20000000 reg.h [5212+]
25899
 AR5K_SISR2_TSFOORAR5K_SISR2_TSFOOR 0x80000000 reg.h TSF OOR (?)
25900
 AR5K_SISR3AR5K_SISR3 0x0090 reg.h Register Address [5211+]
25901
 AR5K_SISR3_QCBRORNAR5K_SISR3_QCBRORN 0x000003ff reg.h Mask for QCBRORN
25902
 AR5K_SISR3_QCBRORN_SAR5K_SISR3_QCBRORN_S 0 reg.h 　
25903
 AR5K_SISR3_QCBRURNAR5K_SISR3_QCBRURN 0x03ff0000 reg.h Mask for QCBRURN
25904
 AR5K_SISR3_QCBRURN_SAR5K_SISR3_QCBRURN_S 16 reg.h 　
25905
 AR5K_SISR4AR5K_SISR4 0x0094 reg.h Register Address [5211+]
25906
 AR5K_SISR4_QTRIGAR5K_SISR4_QTRIG 0x000003ff reg.h Mask for QTRIG
25907
 AR5K_SISR4_QTRIG_SAR5K_SISR4_QTRIG_S 0 reg.h 　
25908
 AR5K_RAC_PISRAR5K_RAC_PISR 0x00c0 reg.h Read and clear PISR
25909
 AR5K_RAC_SISR0AR5K_RAC_SISR0 0x00c4 reg.h Read and clear SISR0
25910
 AR5K_RAC_SISR1AR5K_RAC_SISR1 0x00c8 reg.h Read and clear SISR1
25911
 AR5K_RAC_SISR2AR5K_RAC_SISR2 0x00cc reg.h Read and clear SISR2
25912
 AR5K_RAC_SISR3AR5K_RAC_SISR3 0x00d0 reg.h Read and clear SISR3
25913
 AR5K_RAC_SISR4AR5K_RAC_SISR4 0x00d4 reg.h Read and clear SISR4
25914
 AR5K_IMRAR5K_IMR 0x0020 reg.h Register Address [5210]
25915
 AR5K_PIMRAR5K_PIMR 0x00a0 reg.h Register Address [5211+]
25916
 AR5K_IMR_RXOKAR5K_IMR_RXOK 0x00000001 reg.h Frame successfuly recieved
25917
 AR5K_IMR_RXDESCAR5K_IMR_RXDESC 0x00000002 reg.h RX descriptor request
25918
 AR5K_IMR_RXERRAR5K_IMR_RXERR 0x00000004 reg.h Receive error
25919
 AR5K_IMR_RXNOFRMAR5K_IMR_RXNOFRM 0x00000008 reg.h No frame received (receive timeout)
25920
 AR5K_IMR_RXEOLAR5K_IMR_RXEOL 0x00000010 reg.h Empty RX descriptor
25921
 AR5K_IMR_RXORNAR5K_IMR_RXORN 0x00000020 reg.h Receive FIFO overrun
25922
 AR5K_IMR_TXOKAR5K_IMR_TXOK 0x00000040 reg.h Frame successfuly transmited
25923
 AR5K_IMR_TXDESCAR5K_IMR_TXDESC 0x00000080 reg.h TX descriptor request
25924
 AR5K_IMR_TXERRAR5K_IMR_TXERR 0x00000100 reg.h Transmit error
25925
 AR5K_IMR_TXNOFRMAR5K_IMR_TXNOFRM 0x00000200 reg.h No frame transmited (transmit timeout)
25926
 AR5K_IMR_TXEOLAR5K_IMR_TXEOL 0x00000400 reg.h Empty TX descriptor
25927
 AR5K_IMR_TXURNAR5K_IMR_TXURN 0x00000800 reg.h Transmit FIFO underrun
25928
 AR5K_IMR_MIBAR5K_IMR_MIB 0x00001000 reg.h Update MIB counters
25929
 AR5K_IMR_SWIAR5K_IMR_SWI 0x00002000 reg.h Software interrupt
25930
 AR5K_IMR_RXPHYAR5K_IMR_RXPHY 0x00004000 reg.h PHY error
25931
 AR5K_IMR_RXKCMAR5K_IMR_RXKCM 0x00008000 reg.h RX Key cache miss
25932
 AR5K_IMR_SWBAAR5K_IMR_SWBA 0x00010000 reg.h Software beacon alert
25933
 AR5K_IMR_BRSSIAR5K_IMR_BRSSI 0x00020000 reg.h Beacon rssi below threshold (?)
25934
 AR5K_IMR_BMISSAR5K_IMR_BMISS 0x00040000 reg.h Beacon missed
25935
 AR5K_IMR_HIUERRAR5K_IMR_HIUERR 0x00080000 reg.h Host Interface Unit error [5211+]
25936
 AR5K_IMR_BNRAR5K_IMR_BNR 0x00100000 reg.h Beacon not ready [5211+]
25937
 AR5K_IMR_MCABTAR5K_IMR_MCABT 0x00100000 reg.h Master Cycle Abort [5210]
25938
 AR5K_IMR_RXCHIRPAR5K_IMR_RXCHIRP 0x00200000 reg.h CHIRP Received [5212+]
25939
 AR5K_IMR_SSERRAR5K_IMR_SSERR 0x00200000 reg.h Signaled System Error [5210]
25940
 AR5K_IMR_DPERRAR5K_IMR_DPERR 0x00400000 reg.h Det par Error (?) [5210]
25941
 AR5K_IMR_RXDOPPLERAR5K_IMR_RXDOPPLER 0x00400000 reg.h Doppler chirp received [5212+]
25942
 AR5K_IMR_TIMAR5K_IMR_TIM 0x00800000 reg.h [5211+]
25943
 AR5K_IMR_BCNMISCAR5K_IMR_BCNMISC 0x00800000 reg.h 'or' of TIM, CAB_END, DTIM_SYNC, BCN_TIMEOUT,
25944
 AR5K_IMR_GPIOAR5K_IMR_GPIO 0x01000000 reg.h GPIO (rf kill)
25945
 AR5K_IMR_QCBRORNAR5K_IMR_QCBRORN 0x02000000 reg.h QCU CBR overrun (?) [5211+]
25946
 AR5K_IMR_QCBRURNAR5K_IMR_QCBRURN 0x04000000 reg.h QCU CBR underrun (?) [5211+]
25947
 AR5K_IMR_QTRIGAR5K_IMR_QTRIG 0x08000000 reg.h QCU scheduling trigger [5211+]
25948
 AR5K_SIMR0AR5K_SIMR0 0x00a4 reg.h Register Address [5211+]
25949
 AR5K_SIMR0_QCU_TXOKAR5K_SIMR0_QCU_TXOK 0x000003ff reg.h Mask for QCU_TXOK
25950
 AR5K_SIMR0_QCU_TXOK_SAR5K_SIMR0_QCU_TXOK_S 0 reg.h 　
25951
 AR5K_SIMR0_QCU_TXDESCAR5K_SIMR0_QCU_TXDESC 0x03ff0000 reg.h Mask for QCU_TXDESC
25952
 AR5K_SIMR0_QCU_TXDESC_SAR5K_SIMR0_QCU_TXDESC_S 16 reg.h 　
25953
 AR5K_SIMR1AR5K_SIMR1 0x00a8 reg.h Register Address [5211+]
25954
 AR5K_SIMR1_QCU_TXERRAR5K_SIMR1_QCU_TXERR 0x000003ff reg.h Mask for QCU_TXERR
25955
 AR5K_SIMR1_QCU_TXERR_SAR5K_SIMR1_QCU_TXERR_S 0 reg.h 　
25956
 AR5K_SIMR1_QCU_TXEOLAR5K_SIMR1_QCU_TXEOL 0x03ff0000 reg.h Mask for QCU_TXEOL
25957
 AR5K_SIMR1_QCU_TXEOL_SAR5K_SIMR1_QCU_TXEOL_S 16 reg.h 　
25958
 AR5K_SIMR2AR5K_SIMR2 0x00ac reg.h Register Address [5211+]
25959
 AR5K_SIMR2_QCU_TXURNAR5K_SIMR2_QCU_TXURN 0x000003ff reg.h Mask for QCU_TXURN
25960
 AR5K_SIMR2_QCU_TXURN_SAR5K_SIMR2_QCU_TXURN_S 0 reg.h 　
25961
 AR5K_SIMR2_MCABTAR5K_SIMR2_MCABT 0x00100000 reg.h Master Cycle Abort
25962
 AR5K_SIMR2_SSERRAR5K_SIMR2_SSERR 0x00200000 reg.h Signaled System Error
25963
 AR5K_SIMR2_DPERRAR5K_SIMR2_DPERR 0x00400000 reg.h Bus parity error
25964
 AR5K_SIMR2_TIMAR5K_SIMR2_TIM 0x01000000 reg.h [5212+]
25965
 AR5K_SIMR2_CAB_ENDAR5K_SIMR2_CAB_END 0x02000000 reg.h [5212+]
25966
 AR5K_SIMR2_DTIM_SYNCAR5K_SIMR2_DTIM_SYNC 0x04000000 reg.h DTIM Sync lost [5212+]
25967
 AR5K_SIMR2_BCN_TIMEOUTAR5K_SIMR2_BCN_TIMEOUT 0x08000000 reg.h Beacon Timeout [5212+]
25968
 AR5K_SIMR2_CAB_TIMEOUTAR5K_SIMR2_CAB_TIMEOUT 0x10000000 reg.h CAB Timeout [5212+]
25969
 AR5K_SIMR2_DTIMAR5K_SIMR2_DTIM 0x20000000 reg.h [5212+]
25970
 AR5K_SIMR2_TSFOORAR5K_SIMR2_TSFOOR 0x80000000 reg.h TSF OOR (?)
25971
 AR5K_SIMR3AR5K_SIMR3 0x00b0 reg.h Register Address [5211+]
25972
 AR5K_SIMR3_QCBRORNAR5K_SIMR3_QCBRORN 0x000003ff reg.h Mask for QCBRORN
25973
 AR5K_SIMR3_QCBRORN_SAR5K_SIMR3_QCBRORN_S 0 reg.h 　
25974
 AR5K_SIMR3_QCBRURNAR5K_SIMR3_QCBRURN 0x03ff0000 reg.h Mask for QCBRURN
25975
 AR5K_SIMR3_QCBRURN_SAR5K_SIMR3_QCBRURN_S 16 reg.h 　
25976
 AR5K_SIMR4AR5K_SIMR4 0x00b4 reg.h Register Address [5211+]
25977
 AR5K_SIMR4_QTRIGAR5K_SIMR4_QTRIG 0x000003ff reg.h Mask for QTRIG
25978
 AR5K_SIMR4_QTRIG_SAR5K_SIMR4_QTRIG_S 0 reg.h 　
25979
 AR5K_DCM_ADDRAR5K_DCM_ADDR 0x0400 reg.h Decompression mask address (index)
25980
 AR5K_DCM_DATAAR5K_DCM_DATA 0x0404 reg.h Decompression mask data
25981
 AR5K_WOW_PCFGAR5K_WOW_PCFG 0x0410 reg.h Register Address
25982
 AR5K_WOW_PCFG_PAT_MATCH_ENAR5K_WOW_PCFG_PAT_MATCH_EN 0x00000001 reg.h Pattern match enable
25983
 AR5K_WOW_PCFG_LONG_FRAME_POLAR5K_WOW_PCFG_LONG_FRAME_POL 0x00000002 reg.h Long frame policy
25984
 AR5K_WOW_PCFG_WOBMISSAR5K_WOW_PCFG_WOBMISS 0x00000004 reg.h Wake on bea(con) miss (?)
25985
 AR5K_WOW_PCFG_PAT_0_ENAR5K_WOW_PCFG_PAT_0_EN 0x00000100 reg.h Enable pattern 0
25986
 AR5K_WOW_PCFG_PAT_1_ENAR5K_WOW_PCFG_PAT_1_EN 0x00000200 reg.h Enable pattern 1
25987
 AR5K_WOW_PCFG_PAT_2_ENAR5K_WOW_PCFG_PAT_2_EN 0x00000400 reg.h Enable pattern 2
25988
 AR5K_WOW_PCFG_PAT_3_ENAR5K_WOW_PCFG_PAT_3_EN 0x00000800 reg.h Enable pattern 3
25989
 AR5K_WOW_PCFG_PAT_4_ENAR5K_WOW_PCFG_PAT_4_EN 0x00001000 reg.h Enable pattern 4
25990
 AR5K_WOW_PCFG_PAT_5_ENAR5K_WOW_PCFG_PAT_5_EN 0x00002000 reg.h Enable pattern 5
25991
 AR5K_WOW_PAT_IDXAR5K_WOW_PAT_IDX 0x0414 reg.h 　
25992
 AR5K_WOW_PAT_DATAAR5K_WOW_PAT_DATA 0x0418 reg.h Register Address
25993
 AR5K_WOW_PAT_DATA_0_3_VAR5K_WOW_PAT_DATA_0_3_V 0x00000001 reg.h Pattern 0, 3 value
25994
 AR5K_WOW_PAT_DATA_1_4_VAR5K_WOW_PAT_DATA_1_4_V 0x00000100 reg.h Pattern 1, 4 value
25995
 AR5K_WOW_PAT_DATA_2_5_VAR5K_WOW_PAT_DATA_2_5_V 0x00010000 reg.h Pattern 2, 5 value
25996
 AR5K_WOW_PAT_DATA_0_3_MAR5K_WOW_PAT_DATA_0_3_M 0x01000000 reg.h Pattern 0, 3 mask
25997
 AR5K_WOW_PAT_DATA_1_4_MAR5K_WOW_PAT_DATA_1_4_M 0x04000000 reg.h Pattern 1, 4 mask
25998
 AR5K_WOW_PAT_DATA_2_5_MAR5K_WOW_PAT_DATA_2_5_M 0x10000000 reg.h Pattern 2, 5 mask
25999
 AR5K_DCCFGAR5K_DCCFG 0x0420 reg.h Register Address
26000
 AR5K_DCCFG_GLOBAL_ENAR5K_DCCFG_GLOBAL_EN 0x00000001 reg.h Enable decompression on all queues
26001
 AR5K_DCCFG_BYPASS_ENAR5K_DCCFG_BYPASS_EN 0x00000002 reg.h Bypass decompression
26002
 AR5K_DCCFG_BCAST_ENAR5K_DCCFG_BCAST_EN 0x00000004 reg.h Enable decompression for bcast frames
26003
 AR5K_DCCFG_MCAST_ENAR5K_DCCFG_MCAST_EN 0x00000008 reg.h Enable decompression for mcast frames
26004
 AR5K_CCFGAR5K_CCFG 0x0600 reg.h Register Address
26005
 AR5K_CCFG_WINDOW_SIZEAR5K_CCFG_WINDOW_SIZE 0x00000007 reg.h Compression window size
26006
 AR5K_CCFG_CPC_ENAR5K_CCFG_CPC_EN 0x00000008 reg.h Enable performance counters
26007
 AR5K_CCFG_CCUAR5K_CCFG_CCU 0x0604 reg.h Register Address
26008
 AR5K_CCFG_CCU_CUP_ENAR5K_CCFG_CCU_CUP_EN 0x00000001 reg.h CCU Catchup enable
26009
 AR5K_CCFG_CCU_CREDITAR5K_CCFG_CCU_CREDIT 0x00000002 reg.h CCU Credit (field)
26010
 AR5K_CCFG_CCU_CD_THRESAR5K_CCFG_CCU_CD_THRES 0x00000080 reg.h CCU Cyc(lic?) debt threshold (field)
26011
 AR5K_CCFG_CCU_CUP_LCNTAR5K_CCFG_CCU_CUP_LCNT 0x00010000 reg.h CCU Catchup lit(?) count
26012
 AR5K_CCFG_CCU_INITAR5K_CCFG_CCU_INIT 0x00100200 reg.h Initial value during reset
26013
 AR5K_CPC0AR5K_CPC0 0x0610 reg.h Compression performance counter 0
26014
 AR5K_CPC1AR5K_CPC1 0x0614 reg.h Compression performance counter 1
26015
 AR5K_CPC2AR5K_CPC2 0x0618 reg.h Compression performance counter 2
26016
 AR5K_CPC3AR5K_CPC3 0x061c reg.h Compression performance counter 3
26017
 AR5K_CPCOVFAR5K_CPCOVF 0x0620 reg.h Compression performance overflow
26018
 AR5K_QCU_TXDP_BASEAR5K_QCU_TXDP_BASE 0x0800 reg.h Register Address - Queue0 TXDP
26019
 AR5K_QCU_TXEAR5K_QCU_TXE 0x0840 reg.h 　
26020
 AR5K_QCU_TXDAR5K_QCU_TXD 0x0880 reg.h 　
26021
 AR5K_QCU_CBRCFG_BASEAR5K_QCU_CBRCFG_BASE 0x08c0 reg.h Register Address - Queue0 CBRCFG
26022
 AR5K_QCU_CBRCFG_INTVALAR5K_QCU_CBRCFG_INTVAL 0x00ffffff reg.h CBR Interval mask
26023
 AR5K_QCU_CBRCFG_INTVAL_SAR5K_QCU_CBRCFG_INTVAL_S 0 reg.h 　
26024
 AR5K_QCU_CBRCFG_ORN_THRESAR5K_QCU_CBRCFG_ORN_THRES 0xff000000 reg.h CBR overrun threshold mask
26025
 AR5K_QCU_CBRCFG_ORN_THRES_SAR5K_QCU_CBRCFG_ORN_THRES_S 24 reg.h 　
26026
 AR5K_QCU_RDYTIMECFG_BASEAR5K_QCU_RDYTIMECFG_BASE 0x0900 reg.h Register Address - Queue0 RDYTIMECFG
26027
 AR5K_QCU_RDYTIMECFG_INTVALAR5K_QCU_RDYTIMECFG_INTVAL 0x00ffffff reg.h Ready time interval mask
26028
 AR5K_QCU_RDYTIMECFG_INTVAL_SAR5K_QCU_RDYTIMECFG_INTVAL_S 0 reg.h 　
26029
 AR5K_QCU_RDYTIMECFG_ENABLEAR5K_QCU_RDYTIMECFG_ENABLE 0x01000000 reg.h Ready time enable mask
26030
 AR5K_QCU_ONESHOTARM_SETAR5K_QCU_ONESHOTARM_SET 0x0940 reg.h Register Address -QCU "one shot arm set (?)"
26031
 AR5K_QCU_ONESHOTARM_SET_MAR5K_QCU_ONESHOTARM_SET_M 0x0000ffff reg.h 　
26032
 AR5K_QCU_ONESHOTARM_CLEARAR5K_QCU_ONESHOTARM_CLEAR 0x0980 reg.h Register Address -QCU "one shot arm clear (?)"
26033
 AR5K_QCU_ONESHOTARM_CLEAR_MAR5K_QCU_ONESHOTARM_CLEAR_M 0x0000ffff reg.h 　
26034
 AR5K_QCU_MISC_BASEAR5K_QCU_MISC_BASE 0x09c0 reg.h Register Address -Queue0 MISC
26035
 AR5K_QCU_MISC_FRSHED_MAR5K_QCU_MISC_FRSHED_M 0x0000000f reg.h Frame sheduling mask
26036
 AR5K_QCU_MISC_FRSHED_ASAPAR5K_QCU_MISC_FRSHED_ASAP 0 reg.h ASAP
26037
 AR5K_QCU_MISC_FRSHED_CBRAR5K_QCU_MISC_FRSHED_CBR 1 reg.h Constant Bit Rate
26038
 AR5K_QCU_MISC_FRSHED_DBA_GTAR5K_QCU_MISC_FRSHED_DBA_GT 2 reg.h DMA Beacon alert gated
26039
 AR5K_QCU_MISC_FRSHED_TIM_GTAR5K_QCU_MISC_FRSHED_TIM_GT 3 reg.h TIMT gated
26040
 AR5K_QCU_MISC_FRSHED_BCN_SENT_GAR5K_QCU_MISC_FRSHED_BCN_SENT_G 4 reg.h Beacon sent gated
26041
 AR5K_QCU_MISC_ONESHOT_ENABLEAR5K_QCU_MISC_ONESHOT_ENABLE 0x00000010 reg.h Oneshot enable
26042
 AR5K_QCU_MISC_CBREXP_DISAR5K_QCU_MISC_CBREXP_DIS 0x00000020 reg.h Disable CBR expired counter (normal queue)
26043
 AR5K_QCU_MISC_CBREXP_BCN_DISAR5K_QCU_MISC_CBREXP_BCN_DIS 0x00000040 reg.h Disable CBR expired counter (beacon queue)
26044
 AR5K_QCU_MISC_BCN_ENABLEAR5K_QCU_MISC_BCN_ENABLE 0x00000080 reg.h Enable Beacon use
26045
 AR5K_QCU_MISC_CBR_THRES_ENABLEAR5K_QCU_MISC_CBR_THRES_ENABLE 0x00000100 reg.h CBR expired threshold enabled
26046
 AR5K_QCU_MISC_RDY_VEOL_POLICYAR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 reg.h TXE reset when RDYTIME expired or VEOL
26047
 AR5K_QCU_MISC_CBR_RESET_CNTAR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 reg.h CBR threshold (counter) reset
26048
 AR5K_QCU_MISC_DCU_EARLYAR5K_QCU_MISC_DCU_EARLY 0x00000800 reg.h DCU early termination
26049
 AR5K_QCU_MISC_DCU_CMP_ENAR5K_QCU_MISC_DCU_CMP_EN 0x00001000 reg.h Enable frame compression
26050
 AR5K_QCU_STS_BASEAR5K_QCU_STS_BASE 0x0a00 reg.h Register Address - Queue0 STS
26051
 AR5K_QCU_STS_FRMPENDCNTAR5K_QCU_STS_FRMPENDCNT 0x00000003 reg.h Frames pending counter
26052
 AR5K_QCU_STS_CBREXPCNTAR5K_QCU_STS_CBREXPCNT 0x0000ff00 reg.h CBR expired counter
26053
 AR5K_QCU_RDYTIMESHDNAR5K_QCU_RDYTIMESHDN 0x0a40 reg.h 　
26054
 AR5K_QCU_RDYTIMESHDN_MAR5K_QCU_RDYTIMESHDN_M 0x000003ff reg.h 　
26055
 AR5K_QCU_CBB_SELECTAR5K_QCU_CBB_SELECT 0x0b00 reg.h 　
26056
 AR5K_QCU_CBB_ADDRAR5K_QCU_CBB_ADDR 0x0b04 reg.h 　
26057
 AR5K_QCU_CBB_ADDR_SAR5K_QCU_CBB_ADDR_S 9 reg.h 　
26058
 AR5K_QCU_CBCFGAR5K_QCU_CBCFG 0x0b08 reg.h 　
26059
 AR5K_DCU_QCUMASK_BASEAR5K_DCU_QCUMASK_BASE 0x1000 reg.h Register Address -Queue0 DCU_QCUMASK
26060
 AR5K_DCU_QCUMASK_MAR5K_DCU_QCUMASK_M 0x000003ff reg.h 　
26061
 AR5K_DCU_LCL_IFS_BASEAR5K_DCU_LCL_IFS_BASE 0x1040 reg.h Register Address -Queue0 DCU_LCL_IFS
26062
 AR5K_DCU_LCL_IFS_CW_MINAR5K_DCU_LCL_IFS_CW_MIN 0x000003ff reg.h Minimum Contention Window
26063
 AR5K_DCU_LCL_IFS_CW_MIN_SAR5K_DCU_LCL_IFS_CW_MIN_S 0 reg.h 　
26064
 AR5K_DCU_LCL_IFS_CW_MAXAR5K_DCU_LCL_IFS_CW_MAX 0x000ffc00 reg.h Maximum Contention Window
26065
 AR5K_DCU_LCL_IFS_CW_MAX_SAR5K_DCU_LCL_IFS_CW_MAX_S 10 reg.h 　
26066
 AR5K_DCU_LCL_IFS_AIFSAR5K_DCU_LCL_IFS_AIFS 0x0ff00000 reg.h Arbitrated Interframe Space
26067
 AR5K_DCU_LCL_IFS_AIFS_SAR5K_DCU_LCL_IFS_AIFS_S 20 reg.h 　
26068
 AR5K_DCU_LCL_IFS_AIFS_MAXAR5K_DCU_LCL_IFS_AIFS_MAX 0xfc reg.h Anything above that can cause DCU to hang
26069
 AR5K_DCU_RETRY_LMT_BASEAR5K_DCU_RETRY_LMT_BASE 0x1080 reg.h Register Address -Queue0 DCU_RETRY_LMT
26070
 AR5K_DCU_RETRY_LMT_SH_RETRYAR5K_DCU_RETRY_LMT_SH_RETRY 0x0000000f reg.h Short retry limit mask
26071
 AR5K_DCU_RETRY_LMT_SH_RETRY_SAR5K_DCU_RETRY_LMT_SH_RETRY_S 0 reg.h 　
26072
 AR5K_DCU_RETRY_LMT_LG_RETRYAR5K_DCU_RETRY_LMT_LG_RETRY 0x000000f0 reg.h Long retry limit mask
26073
 AR5K_DCU_RETRY_LMT_LG_RETRY_SAR5K_DCU_RETRY_LMT_LG_RETRY_S 4 reg.h 　
26074
 AR5K_DCU_RETRY_LMT_SSH_RETRYAR5K_DCU_RETRY_LMT_SSH_RETRY 0x00003f00 reg.h Station short retry limit mask (?)
26075
 AR5K_DCU_RETRY_LMT_SSH_RETRY_SAR5K_DCU_RETRY_LMT_SSH_RETRY_S 8 reg.h 　
26076
 AR5K_DCU_RETRY_LMT_SLG_RETRYAR5K_DCU_RETRY_LMT_SLG_RETRY 0x000fc000 reg.h Station long retry limit mask (?)
26077
 AR5K_DCU_RETRY_LMT_SLG_RETRY_SAR5K_DCU_RETRY_LMT_SLG_RETRY_S 14 reg.h 　
26078
 AR5K_DCU_CHAN_TIME_BASEAR5K_DCU_CHAN_TIME_BASE 0x10c0 reg.h Register Address -Queue0 DCU_CHAN_TIME
26079
 AR5K_DCU_CHAN_TIME_DURAR5K_DCU_CHAN_TIME_DUR 0x000fffff reg.h Channel time duration
26080
 AR5K_DCU_CHAN_TIME_DUR_SAR5K_DCU_CHAN_TIME_DUR_S 0 reg.h 　
26081
 AR5K_DCU_CHAN_TIME_ENABLEAR5K_DCU_CHAN_TIME_ENABLE 0x00100000 reg.h Enable channel time
26082
 AR5K_DCU_MISC_BASEAR5K_DCU_MISC_BASE 0x1100 reg.h Register Address -Queue0 DCU_MISC
26083
 AR5K_DCU_MISC_BACKOFFAR5K_DCU_MISC_BACKOFF 0x0000003f reg.h Mask for backoff threshold
26084
 AR5K_DCU_MISC_ETS_RTS_POLAR5K_DCU_MISC_ETS_RTS_POL 0x00000040 reg.h End of transmission series
26085
 AR5K_DCU_MISC_ETS_CW_POLAR5K_DCU_MISC_ETS_CW_POL 0x00000080 reg.h End of transmission series
26086
 AR5K_DCU_MISC_FRAG_WAITAR5K_DCU_MISC_FRAG_WAIT 0x00000100 reg.h Wait for next fragment
26087
 AR5K_DCU_MISC_BACKOFF_FRAGAR5K_DCU_MISC_BACKOFF_FRAG 0x00000200 reg.h Enable backoff while bursting
26088
 AR5K_DCU_MISC_HCFPOLL_ENABLEAR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 reg.h CF - Poll enable
26089
 AR5K_DCU_MISC_BACKOFF_PERSISTAR5K_DCU_MISC_BACKOFF_PERSIST 0x00001000 reg.h Persistent backoff
26090
 AR5K_DCU_MISC_FRMPRFTCH_ENABLEAR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 reg.h Enable frame pre-fetch
26091
 AR5K_DCU_MISC_VIRTCOLAR5K_DCU_MISC_VIRTCOL 0x0000c000 reg.h Mask for Virtual Collision (?)
26092
 AR5K_DCU_MISC_VIRTCOL_NORMALAR5K_DCU_MISC_VIRTCOL_NORMAL 0 reg.h 　
26093
 AR5K_DCU_MISC_VIRTCOL_IGNOREAR5K_DCU_MISC_VIRTCOL_IGNORE 1 reg.h 　
26094
 AR5K_DCU_MISC_BCN_ENABLEAR5K_DCU_MISC_BCN_ENABLE 0x00010000 reg.h Enable Beacon use
26095
 AR5K_DCU_MISC_ARBLOCK_CTLAR5K_DCU_MISC_ARBLOCK_CTL 0x00060000 reg.h Arbiter lockout control mask
26096
 AR5K_DCU_MISC_ARBLOCK_CTL_SAR5K_DCU_MISC_ARBLOCK_CTL_S 17 reg.h 　
26097
 AR5K_DCU_MISC_ARBLOCK_CTL_NONEAR5K_DCU_MISC_ARBLOCK_CTL_NONE 0 reg.h No arbiter lockout
26098
 AR5K_DCU_MISC_ARBLOCK_CTL_INTFRAR5K_DCU_MISC_ARBLOCK_CTL_INTFR 1 reg.h Intra-frame lockout
26099
 AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAAR5K_DCU_MISC_ARBLOCK_CTL_GLOBA 2 reg.h Global lockout
26100
 AR5K_DCU_MISC_ARBLOCK_IGNOREAR5K_DCU_MISC_ARBLOCK_IGNORE 0x00080000 reg.h Ignore Arbiter lockout
26101
 AR5K_DCU_MISC_SEQ_NUM_INCR_DISAR5K_DCU_MISC_SEQ_NUM_INCR_DIS 0x00100000 reg.h Disable sequence number increment
26102
 AR5K_DCU_MISC_POST_FR_BKOFF_DISAR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 reg.h Disable post-frame backoff
26103
 AR5K_DCU_MISC_VIRT_COLL_POLICYAR5K_DCU_MISC_VIRT_COLL_POLICY 0x00400000 reg.h Virtual Collision cw policy
26104
 AR5K_DCU_MISC_BLOWN_IFS_POLICYAR5K_DCU_MISC_BLOWN_IFS_POLICY 0x00800000 reg.h Blown IFS policy (?)
26105
 AR5K_DCU_MISC_SEQNUM_CTLAR5K_DCU_MISC_SEQNUM_CTL 0x01000000 reg.h Sequence number control (?)
26106
 AR5K_DCU_SEQNUM_BASEAR5K_DCU_SEQNUM_BASE 0x1140 reg.h 　
26107
 AR5K_DCU_SEQNUM_MAR5K_DCU_SEQNUM_M 0x00000fff reg.h 　
26108
 AR5K_DCU_GBL_IFS_SIFSAR5K_DCU_GBL_IFS_SIFS 0x1030 reg.h 　
26109
 AR5K_DCU_GBL_IFS_SIFS_MAR5K_DCU_GBL_IFS_SIFS_M 0x0000ffff reg.h 　
26110
 AR5K_DCU_GBL_IFS_SLOTAR5K_DCU_GBL_IFS_SLOT 0x1070 reg.h 　
26111
 AR5K_DCU_GBL_IFS_SLOT_MAR5K_DCU_GBL_IFS_SLOT_M 0x0000ffff reg.h 　
26112
 AR5K_DCU_GBL_IFS_EIFSAR5K_DCU_GBL_IFS_EIFS 0x10b0 reg.h 　
26113
 AR5K_DCU_GBL_IFS_EIFS_MAR5K_DCU_GBL_IFS_EIFS_M 0x0000ffff reg.h 　
26114
 AR5K_DCU_GBL_IFS_MISCAR5K_DCU_GBL_IFS_MISC 0x10f0 reg.h Register Address
26115
 AR5K_DCU_GBL_IFS_MISC_LFSR_SLICAR5K_DCU_GBL_IFS_MISC_LFSR_SLIC 0x00000007 reg.h LFSR Slice Select
26116
 AR5K_DCU_GBL_IFS_MISC_TURBO_MODAR5K_DCU_GBL_IFS_MISC_TURBO_MOD 0x00000008 reg.h Turbo mode
26117
 AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_ 0x000003f0 reg.h SIFS Duration mask
26118
 AR5K_DCU_GBL_IFS_MISC_USEC_DURAR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 reg.h USEC Duration mask
26119
 AR5K_DCU_GBL_IFS_MISC_USEC_DUR_AR5K_DCU_GBL_IFS_MISC_USEC_DUR_ 10 reg.h 　
26120
 AR5K_DCU_GBL_IFS_MISC_DCU_ARB_DAR5K_DCU_GBL_IFS_MISC_DCU_ARB_D 0x00300000 reg.h DCU Arbiter delay mask
26121
 AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_ 0x00400000 reg.h SIFS cnt reset policy (?)
26122
 AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_ 0x00800000 reg.h AIFS cnt reset policy (?)
26123
 AR5K_DCU_GBL_IFS_MISC_RND_LFSR_AR5K_DCU_GBL_IFS_MISC_RND_LFSR_ 0x01000000 reg.h Disable random LFSR slice
26124
 AR5K_DCU_FPAR5K_DCU_FP 0x1230 reg.h Register Address
26125
 AR5K_DCU_FP_NOBURST_DCU_ENAR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 reg.h Enable non-burst prefetch on DCU (?)
26126
 AR5K_DCU_FP_NOBURST_ENAR5K_DCU_FP_NOBURST_EN 0x00000010 reg.h Enable non-burst prefetch (?)
26127
 AR5K_DCU_FP_BURST_DCU_ENAR5K_DCU_FP_BURST_DCU_EN 0x00000020 reg.h Enable burst prefetch on DCU (?)
26128
 AR5K_DCU_TXPAR5K_DCU_TXP 0x1270 reg.h Register Address
26129
 AR5K_DCU_TXP_MAR5K_DCU_TXP_M 0x000003ff reg.h Tx pause mask
26130
 AR5K_DCU_TXP_STATUSAR5K_DCU_TXP_STATUS 0x00010000 reg.h Tx pause status
26131
 AR5K_DCU_TX_FILTER_0_BASEAR5K_DCU_TX_FILTER_0_BASE 0x1038 reg.h 　
26132
 AR5K_DCU_TX_FILTER_1_BASEAR5K_DCU_TX_FILTER_1_BASE 0x103c reg.h 　
26133
 AR5K_DCU_TX_FILTER_CLRAR5K_DCU_TX_FILTER_CLR 0x143c reg.h 　
26134
 AR5K_DCU_TX_FILTER_SETAR5K_DCU_TX_FILTER_SET 0x147c reg.h 　
26135
 AR5K_RESET_CTLAR5K_RESET_CTL 0x4000 reg.h Register Address
26136
 AR5K_RESET_CTL_PCUAR5K_RESET_CTL_PCU 0x00000001 reg.h Protocol Control Unit reset
26137
 AR5K_RESET_CTL_DMAAR5K_RESET_CTL_DMA 0x00000002 reg.h DMA (Rx/Tx) reset [5210]
26138
 AR5K_RESET_CTL_BASEBANDAR5K_RESET_CTL_BASEBAND 0x00000002 reg.h Baseband reset [5211+]
26139
 AR5K_RESET_CTL_MACAR5K_RESET_CTL_MAC 0x00000004 reg.h MAC reset (PCU+Baseband ?) [5210]
26140
 AR5K_RESET_CTL_PHYAR5K_RESET_CTL_PHY 0x00000008 reg.h PHY reset [5210]
26141
 AR5K_RESET_CTL_PCIAR5K_RESET_CTL_PCI 0x00000010 reg.h PCI Core reset (interrupts etc)
26142
 AR5K_SLEEP_CTLAR5K_SLEEP_CTL 0x4004 reg.h Register Address
26143
 AR5K_SLEEP_CTL_SLDURAR5K_SLEEP_CTL_SLDUR 0x0000ffff reg.h Sleep duration mask
26144
 AR5K_SLEEP_CTL_SLDUR_SAR5K_SLEEP_CTL_SLDUR_S 0 reg.h 　
26145
 AR5K_SLEEP_CTL_SLEAR5K_SLEEP_CTL_SLE 0x00030000 reg.h Sleep enable mask
26146
 AR5K_SLEEP_CTL_SLE_SAR5K_SLEEP_CTL_SLE_S 16 reg.h 　
26147
 AR5K_SLEEP_CTL_SLE_WAKEAR5K_SLEEP_CTL_SLE_WAKE 0x00000000 reg.h Force chip awake
26148
 AR5K_SLEEP_CTL_SLE_SLPAR5K_SLEEP_CTL_SLE_SLP 0x00010000 reg.h Force chip sleep
26149
 AR5K_SLEEP_CTL_SLE_ALLOWAR5K_SLEEP_CTL_SLE_ALLOW 0x00020000 reg.h Normal sleep policy
26150
 AR5K_SLEEP_CTL_SLE_UNITSAR5K_SLEEP_CTL_SLE_UNITS 0x00000008 reg.h [5211+]
26151
 AR5K_SLEEP_CTL_DUR_TIM_POLAR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 reg.h Sleep duration timing policy
26152
 AR5K_SLEEP_CTL_DUR_WRITE_POLAR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 reg.h Sleep duration write policy
26153
 AR5K_SLEEP_CTL_SLE_POLAR5K_SLEEP_CTL_SLE_POL 0x00100000 reg.h Sleep policy mode
26154
 AR5K_INTPENDAR5K_INTPEND 0x4008 reg.h 　
26155
 AR5K_INTPEND_MAR5K_INTPEND_M 0x00000001 reg.h 　
26156
 AR5K_SFRAR5K_SFR 0x400c reg.h 　
26157
 AR5K_SFR_ENAR5K_SFR_EN 0x00000001 reg.h 　
26158
 AR5K_PCICFGAR5K_PCICFG 0x4010 reg.h Register Address
26159
 AR5K_PCICFG_EEAEAR5K_PCICFG_EEAE 0x00000001 reg.h Eeprom access enable [5210]
26160
 AR5K_PCICFG_SLEEP_CLOCK_ENAR5K_PCICFG_SLEEP_CLOCK_EN 0x00000002 reg.h Enable sleep clock
26161
 AR5K_PCICFG_CLKRUNENAR5K_PCICFG_CLKRUNEN 0x00000004 reg.h CLKRUN enable [5211+]
26162
 AR5K_PCICFG_EESIZEAR5K_PCICFG_EESIZE 0x00000018 reg.h Mask for EEPROM size [5211+]
26163
 AR5K_PCICFG_EESIZE_SAR5K_PCICFG_EESIZE_S 3 reg.h 　
26164
 AR5K_PCICFG_EESIZE_4KAR5K_PCICFG_EESIZE_4K 0 reg.h 4K
26165
 AR5K_PCICFG_EESIZE_8KAR5K_PCICFG_EESIZE_8K 1 reg.h 8K
26166
 AR5K_PCICFG_EESIZE_16KAR5K_PCICFG_EESIZE_16K 2 reg.h 16K
26167
 AR5K_PCICFG_EESIZE_FAILAR5K_PCICFG_EESIZE_FAIL 3 reg.h Failed to get size [5211+]
26168
 AR5K_PCICFG_LEDAR5K_PCICFG_LED 0x00000060 reg.h Led status [5211+]
26169
 AR5K_PCICFG_LED_NONEAR5K_PCICFG_LED_NONE 0x00000000 reg.h Default [5211+]
26170
 AR5K_PCICFG_LED_PENDAR5K_PCICFG_LED_PEND 0x00000020 reg.h Scan / Auth pending
26171
 AR5K_PCICFG_LED_ASSOCAR5K_PCICFG_LED_ASSOC 0x00000040 reg.h Associated
26172
 AR5K_PCICFG_BUS_SELAR5K_PCICFG_BUS_SEL 0x00000380 reg.h Mask for "bus select" [5211+] (?)
26173
 AR5K_PCICFG_CBEFIX_DISAR5K_PCICFG_CBEFIX_DIS 0x00000400 reg.h Disable CBE fix
26174
 AR5K_PCICFG_SL_INTENAR5K_PCICFG_SL_INTEN 0x00000800 reg.h Enable interrupts when asleep
26175
 AR5K_PCICFG_LED_BCTLAR5K_PCICFG_LED_BCTL 0x00001000 reg.h Led blink (?) [5210]
26176
 AR5K_PCICFG_RETRY_FIXAR5K_PCICFG_RETRY_FIX 0x00001000 reg.h Enable pci core retry fix
26177
 AR5K_PCICFG_SL_INPENAR5K_PCICFG_SL_INPEN 0x00002000 reg.h Sleep even whith pending interrupts
26178
 AR5K_PCICFG_SPWR_DNAR5K_PCICFG_SPWR_DN 0x00010000 reg.h Mask for power status
26179
 AR5K_PCICFG_LEDMODEAR5K_PCICFG_LEDMODE 0x000e0000 reg.h Ledmode [5211+]
26180
 AR5K_PCICFG_LEDMODE_PROPAR5K_PCICFG_LEDMODE_PROP 0x00000000 reg.h Blink on standard traffic [5211+]
26181
 AR5K_PCICFG_LEDMODE_PROMAR5K_PCICFG_LEDMODE_PROM 0x00020000 reg.h Default mode (blink on any traffic) [5211+]
26182
 AR5K_PCICFG_LEDMODE_PWRAR5K_PCICFG_LEDMODE_PWR 0x00040000 reg.h Some other blinking mode (?) [5211+]
26183
 AR5K_PCICFG_LEDMODE_RANDAR5K_PCICFG_LEDMODE_RAND 0x00060000 reg.h Random blinking (?) [5211+]
26184
 AR5K_PCICFG_LEDBLINKAR5K_PCICFG_LEDBLINK 0x00700000 reg.h Led blink rate
26185
 AR5K_PCICFG_LEDBLINK_SAR5K_PCICFG_LEDBLINK_S 20 reg.h 　
26186
 AR5K_PCICFG_LEDSLOWAR5K_PCICFG_LEDSLOW 0x00800000 reg.h Slowest led blink rate [5211+]
26187
 AR5K_PCICFG_LEDSTATEAR5K_PCICFG_LEDSTATE (AR5K_PCICFG_LED | AR5K_PCICFG_LEDMODE | \ AR5K_PCICFG_LEDBLINK | AR5K_PCICFG_LEDSLOW) reg.h 　
26188
 AR5K_PCICFG_SLEEP_CLOCK_RATEAR5K_PCICFG_SLEEP_CLOCK_RATE 0x03000000 reg.h Sleep clock rate
26189
 AR5K_PCICFG_SLEEP_CLOCK_RATE_SAR5K_PCICFG_SLEEP_CLOCK_RATE_S 24 reg.h 　
26190
 AR5K_NUM_GPIOAR5K_NUM_GPIO 6 reg.h 　
26191
 AR5K_GPIOCRAR5K_GPIOCR 0x4014 reg.h Register Address
26192
 AR5K_GPIOCR_INT_ENAAR5K_GPIOCR_INT_ENA 0x00008000 reg.h Enable GPIO interrupt
26193
 AR5K_GPIOCR_INT_SELLAR5K_GPIOCR_INT_SELL 0x00000000 reg.h Generate interrupt when pin is low
26194
 AR5K_GPIOCR_INT_SELHAR5K_GPIOCR_INT_SELH 0x00010000 reg.h Generate interrupt when pin is high
26195
 AR5K_GPIODOAR5K_GPIODO 0x4018 reg.h 　
26196
 AR5K_GPIODIAR5K_GPIODI 0x401c reg.h 　
26197
 AR5K_GPIODI_MAR5K_GPIODI_M 0x0000002f reg.h 　
26198
 AR5K_SREVAR5K_SREV 0x4020 reg.h Register Address
26199
 AR5K_SREV_REVAR5K_SREV_REV 0x0000000f reg.h Mask for revision
26200
 AR5K_SREV_REV_SAR5K_SREV_REV_S 0 reg.h 　
26201
 AR5K_SREV_VERAR5K_SREV_VER 0x000000ff reg.h Mask for version
26202
 AR5K_SREV_VER_SAR5K_SREV_VER_S 4 reg.h 　
26203
 AR5K_TXEPOSTAR5K_TXEPOST 0x4028 reg.h 　
26204
 AR5K_QCU_SLEEP_MASKAR5K_QCU_SLEEP_MASK 0x402c reg.h 　
26205
 AR5K_5414_CBCFGAR5K_5414_CBCFG 0x4068 reg.h 　
26206
 AR5K_5414_CBCFG_BUF_DISAR5K_5414_CBCFG_BUF_DIS 0x10 reg.h Disable buffer
26207
 AR5K_PCIE_PM_CTLAR5K_PCIE_PM_CTL 0x4068 reg.h Register address
26208
 AR5K_PCIE_PM_CTL_L1_WHEN_D2AR5K_PCIE_PM_CTL_L1_WHEN_D2 0x00000001 reg.h enable PCIe core enter L1
26209
 AR5K_PCIE_PM_CTL_L0_L0S_CLEARAR5K_PCIE_PM_CTL_L0_L0S_CLEAR 0x00000002 reg.h Clear L0 and L0S counters
26210
 AR5K_PCIE_PM_CTL_L0_L0S_ENAR5K_PCIE_PM_CTL_L0_L0S_EN 0x00000004 reg.h Start L0 nd L0S counters
26211
 AR5K_PCIE_PM_CTL_LDRESET_ENAR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 reg.h Enable reset when link goes
26212
 AR5K_PCIE_PM_CTL_PME_ENAR5K_PCIE_PM_CTL_PME_EN 0x00000010 reg.h PME Enable
26213
 AR5K_PCIE_PM_CTL_AUX_PWR_DETAR5K_PCIE_PM_CTL_AUX_PWR_DET 0x00000020 reg.h Aux power detect
26214
 AR5K_PCIE_PM_CTL_PME_CLEARAR5K_PCIE_PM_CTL_PME_CLEAR 0x00000040 reg.h Clear PME
26215
 AR5K_PCIE_PM_CTL_PSM_D0AR5K_PCIE_PM_CTL_PSM_D0 0x00000080 reg.h 　
26216
 AR5K_PCIE_PM_CTL_PSM_D1AR5K_PCIE_PM_CTL_PSM_D1 0x00000100 reg.h 　
26217
 AR5K_PCIE_PM_CTL_PSM_D2AR5K_PCIE_PM_CTL_PSM_D2 0x00000200 reg.h 　
26218
 AR5K_PCIE_PM_CTL_PSM_D3AR5K_PCIE_PM_CTL_PSM_D3 0x00000400 reg.h 　
26219
 AR5K_PCIE_WAENAR5K_PCIE_WAEN 0x407c reg.h 　
26220
 AR5K_PCIE_SERDESAR5K_PCIE_SERDES 0x4080 reg.h 　
26221
 AR5K_PCIE_SERDES_RESETAR5K_PCIE_SERDES_RESET 0x4084 reg.h 　
26222
 AR5K_EEPROM_BASEAR5K_EEPROM_BASE 0x6000 reg.h 　
26223
 AR5K_EEPROM_DATA_5211AR5K_EEPROM_DATA_5211 0x6004 reg.h 　
26224
 AR5K_EEPROM_DATA_5210AR5K_EEPROM_DATA_5210 0x6800 reg.h 　
26225
 AR5K_EEPROM_DATAAR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \ AR5K_EEPROM_DATA_5210 : AR5K_EEPROM_DATA_5211) reg.h 　
26226
 AR5K_EEPROM_CMDAR5K_EEPROM_CMD 0x6008 reg.h Register Addres
26227
 AR5K_EEPROM_CMD_READAR5K_EEPROM_CMD_READ 0x00000001 reg.h EEPROM read
26228
 AR5K_EEPROM_CMD_WRITEAR5K_EEPROM_CMD_WRITE 0x00000002 reg.h EEPROM write
26229
 AR5K_EEPROM_CMD_RESETAR5K_EEPROM_CMD_RESET 0x00000004 reg.h EEPROM reset
26230
 AR5K_EEPROM_STAT_5210AR5K_EEPROM_STAT_5210 0x6c00 reg.h Register Address [5210]
26231
 AR5K_EEPROM_STAT_5211AR5K_EEPROM_STAT_5211 0x600c reg.h Register Address [5211+]
26232
 AR5K_EEPROM_STATUSAR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \ AR5K_EEPROM_STAT_5210 : AR5K_EEPROM_STAT_5211) reg.h 　
26233
 AR5K_EEPROM_STAT_RDERRAR5K_EEPROM_STAT_RDERR 0x00000001 reg.h EEPROM read failed
26234
 AR5K_EEPROM_STAT_RDDONEAR5K_EEPROM_STAT_RDDONE 0x00000002 reg.h EEPROM read successful
26235
 AR5K_EEPROM_STAT_WRERRAR5K_EEPROM_STAT_WRERR 0x00000004 reg.h EEPROM write failed
26236
 AR5K_EEPROM_STAT_WRDONEAR5K_EEPROM_STAT_WRDONE 0x00000008 reg.h EEPROM write successful
26237
 AR5K_EEPROM_CFGAR5K_EEPROM_CFG 0x6010 reg.h Register Addres
26238
 AR5K_EEPROM_CFG_SIZEAR5K_EEPROM_CFG_SIZE 0x00000003 reg.h Size determination override
26239
 AR5K_EEPROM_CFG_SIZE_AUTOAR5K_EEPROM_CFG_SIZE_AUTO 0 reg.h 　
26240
 AR5K_EEPROM_CFG_SIZE_4KBITAR5K_EEPROM_CFG_SIZE_4KBIT 1 reg.h 　
26241
 AR5K_EEPROM_CFG_SIZE_8KBITAR5K_EEPROM_CFG_SIZE_8KBIT 2 reg.h 　
26242
 AR5K_EEPROM_CFG_SIZE_16KBITAR5K_EEPROM_CFG_SIZE_16KBIT 3 reg.h 　
26243
 AR5K_EEPROM_CFG_WR_WAIT_DISAR5K_EEPROM_CFG_WR_WAIT_DIS 0x00000004 reg.h Disable write wait
26244
 AR5K_EEPROM_CFG_CLK_RATEAR5K_EEPROM_CFG_CLK_RATE 0x00000018 reg.h Clock rate
26245
 AR5K_EEPROM_CFG_CLK_RATE_SAR5K_EEPROM_CFG_CLK_RATE_S 3 reg.h 　
26246
 AR5K_EEPROM_CFG_CLK_RATE_156KHZAR5K_EEPROM_CFG_CLK_RATE_156KHZ 0 reg.h 　
26247
 AR5K_EEPROM_CFG_CLK_RATE_312KHZAR5K_EEPROM_CFG_CLK_RATE_312KHZ 1 reg.h 　
26248
 AR5K_EEPROM_CFG_CLK_RATE_625KHZAR5K_EEPROM_CFG_CLK_RATE_625KHZ 2 reg.h 　
26249
 AR5K_EEPROM_CFG_PROT_KEYAR5K_EEPROM_CFG_PROT_KEY 0x00ffff00 reg.h Protection key
26250
 AR5K_EEPROM_CFG_PROT_KEY_SAR5K_EEPROM_CFG_PROT_KEY_S 8 reg.h 　
26251
 AR5K_EEPROM_CFG_LIND_ENAR5K_EEPROM_CFG_LIND_EN 0x01000000 reg.h Enable length indicator (?)
26252
 AR5K_PCU_MINAR5K_PCU_MIN 0x8000 reg.h 　
26253
 AR5K_PCU_MAXAR5K_PCU_MAX 0x8fff reg.h 　
26254
 AR5K_STA_ID0AR5K_STA_ID0 0x8000 reg.h 　
26255
 AR5K_STA_ID0_ARRD_L32AR5K_STA_ID0_ARRD_L32 0xffffffff reg.h 　
26256
 AR5K_STA_ID1AR5K_STA_ID1 0x8004 reg.h Register Address
26257
 AR5K_STA_ID1_ADDR_U16AR5K_STA_ID1_ADDR_U16 0x0000ffff reg.h Upper 16 bits of MAC addres
26258
 AR5K_STA_ID1_APAR5K_STA_ID1_AP 0x00010000 reg.h Set AP mode
26259
 AR5K_STA_ID1_ADHOCAR5K_STA_ID1_ADHOC 0x00020000 reg.h Set Ad-Hoc mode
26260
 AR5K_STA_ID1_PWR_SVAR5K_STA_ID1_PWR_SV 0x00040000 reg.h Power save reporting
26261
 AR5K_STA_ID1_NO_KEYSRCHAR5K_STA_ID1_NO_KEYSRCH 0x00080000 reg.h No key search
26262
 AR5K_STA_ID1_NO_PSPOLLAR5K_STA_ID1_NO_PSPOLL 0x00100000 reg.h No power save polling [5210]
26263
 AR5K_STA_ID1_PCF_5211AR5K_STA_ID1_PCF_5211 0x00100000 reg.h Enable PCF on [5211+]
26264
 AR5K_STA_ID1_PCF_5210AR5K_STA_ID1_PCF_5210 0x00200000 reg.h Enable PCF on [5210]
26265
 AR5K_STA_ID1_PCFAR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \ AR5K_STA_ID1_PCF_5210 : AR5K_STA_ID1_PCF_5211) reg.h 　
26266
 AR5K_STA_ID1_DEFAULT_ANTENNAAR5K_STA_ID1_DEFAULT_ANTENNA 0x00200000 reg.h Use default antenna
26267
 AR5K_STA_ID1_DESC_ANTENNAAR5K_STA_ID1_DESC_ANTENNA 0x00400000 reg.h Update antenna from descriptor
26268
 AR5K_STA_ID1_RTS_DEF_ANTENNAAR5K_STA_ID1_RTS_DEF_ANTENNA 0x00800000 reg.h Use default antenna for RTS
26269
 AR5K_STA_ID1_ACKCTS_6MBAR5K_STA_ID1_ACKCTS_6MB 0x01000000 reg.h Use 6Mbit/s for ACK/CTS
26270
 AR5K_STA_ID1_BASE_RATE_11BAR5K_STA_ID1_BASE_RATE_11B 0x02000000 reg.h Use 11b base rate for ACK/CTS [5211+]
26271
 AR5K_STA_ID1_SELFGEN_DEF_ANTAR5K_STA_ID1_SELFGEN_DEF_ANT 0x04000000 reg.h Use def. antenna for self generated frames
26272
 AR5K_STA_ID1_CRYPT_MIC_ENAR5K_STA_ID1_CRYPT_MIC_EN 0x08000000 reg.h Enable MIC
26273
 AR5K_STA_ID1_KEYSRCH_MODEAR5K_STA_ID1_KEYSRCH_MODE 0x10000000 reg.h Look up key when key id != 0
26274
 AR5K_STA_ID1_PRESERVE_SEQ_NUMAR5K_STA_ID1_PRESERVE_SEQ_NUM 0x20000000 reg.h Preserve sequence number
26275
 AR5K_STA_ID1_CBCIV_ENDIANAR5K_STA_ID1_CBCIV_ENDIAN 0x40000000 reg.h ???
26276
 AR5K_STA_ID1_KEYSRCH_MCASTAR5K_STA_ID1_KEYSRCH_MCAST 0x80000000 reg.h Do key cache search for mcast frames
26277
 AR5K_BSS_ID0AR5K_BSS_ID0 0x8008 reg.h 　
26278
 AR5K_BSS_ID1AR5K_BSS_ID1 0x800c reg.h 　
26279
 AR5K_BSS_ID1_AIDAR5K_BSS_ID1_AID 0xffff0000 reg.h 　
26280
 AR5K_BSS_ID1_AID_SAR5K_BSS_ID1_AID_S 16 reg.h 　
26281
 AR5K_SLOT_TIMEAR5K_SLOT_TIME 0x8010 reg.h 　
26282
 AR5K_TIME_OUTAR5K_TIME_OUT 0x8014 reg.h Register Address
26283
 AR5K_TIME_OUT_ACKAR5K_TIME_OUT_ACK 0x00001fff reg.h ACK timeout mask
26284
 AR5K_TIME_OUT_ACK_SAR5K_TIME_OUT_ACK_S 0 reg.h 　
26285
 AR5K_TIME_OUT_CTSAR5K_TIME_OUT_CTS 0x1fff0000 reg.h CTS timeout mask
26286
 AR5K_TIME_OUT_CTS_SAR5K_TIME_OUT_CTS_S 16 reg.h 　
26287
 AR5K_RSSI_THRAR5K_RSSI_THR 0x8018 reg.h Register Address
26288
 AR5K_RSSI_THR_MAR5K_RSSI_THR_M 0x000000ff reg.h Mask for RSSI threshold [5211+]
26289
 AR5K_RSSI_THR_BMISS_5210AR5K_RSSI_THR_BMISS_5210 0x00000700 reg.h Mask for Beacon Missed threshold [5210]
26290
 AR5K_RSSI_THR_BMISS_5210_SAR5K_RSSI_THR_BMISS_5210_S 8 reg.h 　
26291
 AR5K_RSSI_THR_BMISS_5211AR5K_RSSI_THR_BMISS_5211 0x0000ff00 reg.h Mask for Beacon Missed threshold [5211+]
26292
 AR5K_RSSI_THR_BMISS_5211_SAR5K_RSSI_THR_BMISS_5211_S 8 reg.h 　
26293
 AR5K_RSSI_THR_BMISSAR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \ AR5K_RSSI_THR_BMISS_5210 : AR5K_RSSI_THR_BMISS_5211) reg.h 　
26294
 AR5K_RSSI_THR_BMISS_SAR5K_RSSI_THR_BMISS_S 8 reg.h 　
26295
 AR5K_NODCU_RETRY_LMTAR5K_NODCU_RETRY_LMT 0x801c reg.h Register Address
26296
 AR5K_NODCU_RETRY_LMT_SH_RETRYAR5K_NODCU_RETRY_LMT_SH_RETRY 0x0000000f reg.h Short retry limit mask
26297
 AR5K_NODCU_RETRY_LMT_SH_RETRY_SAR5K_NODCU_RETRY_LMT_SH_RETRY_S 0 reg.h 　
26298
 AR5K_NODCU_RETRY_LMT_LG_RETRYAR5K_NODCU_RETRY_LMT_LG_RETRY 0x000000f0 reg.h Long retry mask
26299
 AR5K_NODCU_RETRY_LMT_LG_RETRY_SAR5K_NODCU_RETRY_LMT_LG_RETRY_S 4 reg.h 　
26300
 AR5K_NODCU_RETRY_LMT_SSH_RETRYAR5K_NODCU_RETRY_LMT_SSH_RETRY 0x00003f00 reg.h Station short retry limit mask
26301
 AR5K_NODCU_RETRY_LMT_SSH_RETRY_AR5K_NODCU_RETRY_LMT_SSH_RETRY_ 8 reg.h 　
26302
 AR5K_NODCU_RETRY_LMT_SLG_RETRYAR5K_NODCU_RETRY_LMT_SLG_RETRY 0x000fc000 reg.h Station long retry limit mask
26303
 AR5K_NODCU_RETRY_LMT_SLG_RETRY_AR5K_NODCU_RETRY_LMT_SLG_RETRY_ 14 reg.h 　
26304
 AR5K_NODCU_RETRY_LMT_CW_MINAR5K_NODCU_RETRY_LMT_CW_MIN 0x3ff00000 reg.h Minimum contention window mask
26305
 AR5K_NODCU_RETRY_LMT_CW_MIN_SAR5K_NODCU_RETRY_LMT_CW_MIN_S 20 reg.h 　
26306
 AR5K_USEC_5210AR5K_USEC_5210 0x8020 reg.h Register Address [5210]
26307
 AR5K_USEC_5211AR5K_USEC_5211 0x801c reg.h Register Address [5211+]
26308
 AR5K_USECAR5K_USEC (ah->ah_version == AR5K_AR5210 ? \ AR5K_USEC_5210 : AR5K_USEC_5211) reg.h 　
26309
 AR5K_USEC_1AR5K_USEC_1 0x0000007f reg.h clock cycles for 1us
26310
 AR5K_USEC_1_SAR5K_USEC_1_S 0 reg.h 　
26311
 AR5K_USEC_32AR5K_USEC_32 0x00003f80 reg.h clock cycles for 1us while on 32Mhz clock
26312
 AR5K_USEC_32_SAR5K_USEC_32_S 7 reg.h 　
26313
 AR5K_USEC_TX_LATENCY_5211AR5K_USEC_TX_LATENCY_5211 0x007fc000 reg.h 　
26314
 AR5K_USEC_TX_LATENCY_5211_SAR5K_USEC_TX_LATENCY_5211_S 14 reg.h 　
26315
 AR5K_USEC_RX_LATENCY_5211AR5K_USEC_RX_LATENCY_5211 0x1f800000 reg.h 　
26316
 AR5K_USEC_RX_LATENCY_5211_SAR5K_USEC_RX_LATENCY_5211_S 23 reg.h 　
26317
 AR5K_USEC_TX_LATENCY_5210AR5K_USEC_TX_LATENCY_5210 0x000fc000 reg.h also for 5311
26318
 AR5K_USEC_TX_LATENCY_5210_SAR5K_USEC_TX_LATENCY_5210_S 14 reg.h 　
26319
 AR5K_USEC_RX_LATENCY_5210AR5K_USEC_RX_LATENCY_5210 0x03f00000 reg.h also for 5311
26320
 AR5K_USEC_RX_LATENCY_5210_SAR5K_USEC_RX_LATENCY_5210_S 20 reg.h 　
26321
 AR5K_BEACON_5210AR5K_BEACON_5210 0x8024 reg.h Register Address [5210]
26322
 AR5K_BEACON_5211AR5K_BEACON_5211 0x8020 reg.h Register Address [5211+]
26323
 AR5K_BEACONAR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \ AR5K_BEACON_5210 : AR5K_BEACON_5211) reg.h 　
26324
 AR5K_BEACON_PERIODAR5K_BEACON_PERIOD 0x0000ffff reg.h Mask for beacon period
26325
 AR5K_BEACON_PERIOD_SAR5K_BEACON_PERIOD_S 0 reg.h 　
26326
 AR5K_BEACON_TIMAR5K_BEACON_TIM 0x007f0000 reg.h Mask for TIM offset
26327
 AR5K_BEACON_TIM_SAR5K_BEACON_TIM_S 16 reg.h 　
26328
 AR5K_BEACON_ENABLEAR5K_BEACON_ENABLE 0x00800000 reg.h Enable beacons
26329
 AR5K_BEACON_RESET_TSFAR5K_BEACON_RESET_TSF 0x01000000 reg.h Force TSF reset
26330
 AR5K_CFP_PERIOD_5210AR5K_CFP_PERIOD_5210 0x8028 reg.h 　
26331
 AR5K_CFP_PERIOD_5211AR5K_CFP_PERIOD_5211 0x8024 reg.h 　
26332
 AR5K_CFP_PERIODAR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \ AR5K_CFP_PERIOD_5210 : AR5K_CFP_PERIOD_5211) reg.h 　
26333
 AR5K_TIMER0_5210AR5K_TIMER0_5210 0x802c reg.h 　
26334
 AR5K_TIMER0_5211AR5K_TIMER0_5211 0x8028 reg.h 　
26335
 AR5K_TIMER0AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER0_5210 : AR5K_TIMER0_5211) reg.h 　
26336
 AR5K_TIMER1_5210AR5K_TIMER1_5210 0x8030 reg.h 　
26337
 AR5K_TIMER1_5211AR5K_TIMER1_5211 0x802c reg.h 　
26338
 AR5K_TIMER1AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER1_5210 : AR5K_TIMER1_5211) reg.h 　
26339
 AR5K_TIMER2_5210AR5K_TIMER2_5210 0x8034 reg.h 　
26340
 AR5K_TIMER2_5211AR5K_TIMER2_5211 0x8030 reg.h 　
26341
 AR5K_TIMER2AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER2_5210 : AR5K_TIMER2_5211) reg.h 　
26342
 AR5K_TIMER3_5210AR5K_TIMER3_5210 0x8038 reg.h 　
26343
 AR5K_TIMER3_5211AR5K_TIMER3_5211 0x8034 reg.h 　
26344
 AR5K_TIMER3AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TIMER3_5210 : AR5K_TIMER3_5211) reg.h 　
26345
 AR5K_IFS0AR5K_IFS0 0x8040 reg.h 　
26346
 AR5K_IFS0_SIFSAR5K_IFS0_SIFS 0x000007ff reg.h 　
26347
 AR5K_IFS0_SIFS_SAR5K_IFS0_SIFS_S 0 reg.h 　
26348
 AR5K_IFS0_DIFSAR5K_IFS0_DIFS 0x007ff800 reg.h 　
26349
 AR5K_IFS0_DIFS_SAR5K_IFS0_DIFS_S 11 reg.h 　
26350
 AR5K_IFS1AR5K_IFS1 0x8044 reg.h 　
26351
 AR5K_IFS1_PIFSAR5K_IFS1_PIFS 0x00000fff reg.h 　
26352
 AR5K_IFS1_PIFS_SAR5K_IFS1_PIFS_S 0 reg.h 　
26353
 AR5K_IFS1_EIFSAR5K_IFS1_EIFS 0x03fff000 reg.h 　
26354
 AR5K_IFS1_EIFS_SAR5K_IFS1_EIFS_S 12 reg.h 　
26355
 AR5K_IFS1_CS_ENAR5K_IFS1_CS_EN 0x04000000 reg.h 　
26356
 AR5K_CFP_DUR_5210AR5K_CFP_DUR_5210 0x8048 reg.h 　
26357
 AR5K_CFP_DUR_5211AR5K_CFP_DUR_5211 0x8038 reg.h 　
26358
 AR5K_CFP_DURAR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \ AR5K_CFP_DUR_5210 : AR5K_CFP_DUR_5211) reg.h 　
26359
 AR5K_RX_FILTER_5210AR5K_RX_FILTER_5210 0x804c reg.h Register Address [5210]
26360
 AR5K_RX_FILTER_5211AR5K_RX_FILTER_5211 0x803c reg.h Register Address [5211+]
26361
 AR5K_RX_FILTERAR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \ AR5K_RX_FILTER_5210 : AR5K_RX_FILTER_5211) reg.h 　
26362
 AR5K_RX_FILTER_UCASTAR5K_RX_FILTER_UCAST 0x00000001 reg.h Don't filter unicast frames
26363
 AR5K_RX_FILTER_MCASTAR5K_RX_FILTER_MCAST 0x00000002 reg.h Don't filter multicast frames
26364
 AR5K_RX_FILTER_BCASTAR5K_RX_FILTER_BCAST 0x00000004 reg.h Don't filter broadcast frames
26365
 AR5K_RX_FILTER_CONTROLAR5K_RX_FILTER_CONTROL 0x00000008 reg.h Don't filter control frames
26366
 AR5K_RX_FILTER_BEACONAR5K_RX_FILTER_BEACON 0x00000010 reg.h Don't filter beacon frames
26367
 AR5K_RX_FILTER_PROMAR5K_RX_FILTER_PROM 0x00000020 reg.h Set promiscuous mode
26368
 AR5K_RX_FILTER_XRPOLLAR5K_RX_FILTER_XRPOLL 0x00000040 reg.h Don't filter XR poll frame [5212+]
26369
 AR5K_RX_FILTER_PROBEREQAR5K_RX_FILTER_PROBEREQ 0x00000080 reg.h Don't filter probe requests [5212+]
26370
 AR5K_RX_FILTER_PHYERR_5212AR5K_RX_FILTER_PHYERR_5212 0x00000100 reg.h Don't filter phy errors [5212+]
26371
 AR5K_RX_FILTER_RADARERR_5212AR5K_RX_FILTER_RADARERR_5212 0x00000200 reg.h Don't filter phy radar errors [5212+]
26372
 AR5K_RX_FILTER_PHYERR_5211AR5K_RX_FILTER_PHYERR_5211 0x00000040 reg.h [5211]
26373
 AR5K_RX_FILTER_RADARERR_5211AR5K_RX_FILTER_RADARERR_5211 0x00000080 reg.h [5211]
26374
 AR5K_RX_FILTER_PHYERRAR5K_RX_FILTER_PHYERR ((ah->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_PHYERR_5211 : AR5K_RX_FILTER_PHYERR_5212)) reg.h 　
26375
 AR5K_RX_FILTER_RADARERRAR5K_RX_FILTER_RADARERR ((ah->ah_version == AR5K_AR5211 ? \ AR5K_RX_FILTER_RADARERR_5211 : AR5K_RX_FILTER_RADARERR_5212)) reg.h 　
26376
 AR5K_MCAST_FILTER0_5210AR5K_MCAST_FILTER0_5210 0x8050 reg.h 　
26377
 AR5K_MCAST_FILTER0_5211AR5K_MCAST_FILTER0_5211 0x8040 reg.h 　
26378
 AR5K_MCAST_FILTER0AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_MCAST_FILTER0_5210 : AR5K_MCAST_FILTER0_5211) reg.h 　
26379
 AR5K_MCAST_FILTER1_5210AR5K_MCAST_FILTER1_5210 0x8054 reg.h 　
26380
 AR5K_MCAST_FILTER1_5211AR5K_MCAST_FILTER1_5211 0x8044 reg.h 　
26381
 AR5K_MCAST_FILTER1AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \ AR5K_MCAST_FILTER1_5210 : AR5K_MCAST_FILTER1_5211) reg.h 　
26382
 AR5K_TX_MASK0AR5K_TX_MASK0 0x8058 reg.h 　
26383
 AR5K_TX_MASK1AR5K_TX_MASK1 0x805c reg.h 　
26384
 AR5K_CLR_TMASKAR5K_CLR_TMASK 0x8060 reg.h 　
26385
 AR5K_TRIG_LVLAR5K_TRIG_LVL 0x8064 reg.h 　
26386
 AR5K_DIAG_SW_5210AR5K_DIAG_SW_5210 0x8068 reg.h Register Address [5210]
26387
 AR5K_DIAG_SW_5211AR5K_DIAG_SW_5211 0x8048 reg.h Register Address [5211+]
26388
 AR5K_DIAG_SWAR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_5210 : AR5K_DIAG_SW_5211) reg.h 　
26389
 AR5K_DIAG_SW_DIS_WEP_ACKAR5K_DIAG_SW_DIS_WEP_ACK 0x00000001 reg.h Disable ACKs if WEP key is invalid
26390
 AR5K_DIAG_SW_DIS_ACKAR5K_DIAG_SW_DIS_ACK 0x00000002 reg.h Disable ACKs
26391
 AR5K_DIAG_SW_DIS_CTSAR5K_DIAG_SW_DIS_CTS 0x00000004 reg.h Disable CTSs
26392
 AR5K_DIAG_SW_DIS_ENCAR5K_DIAG_SW_DIS_ENC 0x00000008 reg.h Disable encryption
26393
 AR5K_DIAG_SW_DIS_DECAR5K_DIAG_SW_DIS_DEC 0x00000010 reg.h Disable decryption
26394
 AR5K_DIAG_SW_DIS_TXAR5K_DIAG_SW_DIS_TX 0x00000020 reg.h Disable transmit [5210]
26395
 AR5K_DIAG_SW_DIS_RX_5210AR5K_DIAG_SW_DIS_RX_5210 0x00000040 reg.h Disable recieve
26396
 AR5K_DIAG_SW_DIS_RX_5211AR5K_DIAG_SW_DIS_RX_5211 0x00000020 reg.h 　
26397
 AR5K_DIAG_SW_DIS_RXAR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_DIS_RX_5210 : AR5K_DIAG_SW_DIS_RX_5211) reg.h 　
26398
 AR5K_DIAG_SW_LOOP_BACK_5210AR5K_DIAG_SW_LOOP_BACK_5210 0x00000080 reg.h Loopback (i guess it goes with DIS_TX) [5210]
26399
 AR5K_DIAG_SW_LOOP_BACK_5211AR5K_DIAG_SW_LOOP_BACK_5211 0x00000040 reg.h 　
26400
 AR5K_DIAG_SW_LOOP_BACKAR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_LOOP_BACK_5210 : AR5K_DIAG_SW_LOOP_BACK_5211) reg.h 　
26401
 AR5K_DIAG_SW_CORR_FCS_5210AR5K_DIAG_SW_CORR_FCS_5210 0x00000100 reg.h Corrupted FCS
26402
 AR5K_DIAG_SW_CORR_FCS_5211AR5K_DIAG_SW_CORR_FCS_5211 0x00000080 reg.h 　
26403
 AR5K_DIAG_SW_CORR_FCSAR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CORR_FCS_5210 : AR5K_DIAG_SW_CORR_FCS_5211) reg.h 　
26404
 AR5K_DIAG_SW_CHAN_INFO_5210AR5K_DIAG_SW_CHAN_INFO_5210 0x00000200 reg.h Dump channel info
26405
 AR5K_DIAG_SW_CHAN_INFO_5211AR5K_DIAG_SW_CHAN_INFO_5211 0x00000100 reg.h 　
26406
 AR5K_DIAG_SW_CHAN_INFOAR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_CHAN_INFO_5210 : AR5K_DIAG_SW_CHAN_INFO_5211) reg.h 　
26407
 AR5K_DIAG_SW_EN_SCRAM_SEED_5210AR5K_DIAG_SW_EN_SCRAM_SEED_5210 0x00000400 reg.h Enable fixed scrambler seed
26408
 AR5K_DIAG_SW_EN_SCRAM_SEED_5211AR5K_DIAG_SW_EN_SCRAM_SEED_5211 0x00000200 reg.h 　
26409
 AR5K_DIAG_SW_EN_SCRAM_SEEDAR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_EN_SCRAM_SEED_5210 : AR5K_DIAG_SW_EN_SCRAM_SEED_5211) reg.h 　
26410
 AR5K_DIAG_SW_ECO_ENABLEAR5K_DIAG_SW_ECO_ENABLE 0x00000400 reg.h [5211+]
26411
 AR5K_DIAG_SW_SCVRAM_SEEDAR5K_DIAG_SW_SCVRAM_SEED 0x0003f800 reg.h [5210]
26412
 AR5K_DIAG_SW_SCRAM_SEED_MAR5K_DIAG_SW_SCRAM_SEED_M 0x0001fc00 reg.h Scrambler seed mask
26413
 AR5K_DIAG_SW_SCRAM_SEED_SAR5K_DIAG_SW_SCRAM_SEED_S 10 reg.h 　
26414
 AR5K_DIAG_SW_DIS_SEQ_INCAR5K_DIAG_SW_DIS_SEQ_INC 0x00040000 reg.h Disable seqnum increment (?)[5210]
26415
 AR5K_DIAG_SW_FRAME_NV0_5210AR5K_DIAG_SW_FRAME_NV0_5210 0x00080000 reg.h 　
26416
 AR5K_DIAG_SW_FRAME_NV0_5211AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 reg.h Accept frames of non-zero protocol number
26417
 AR5K_DIAG_SW_FRAME_NV0AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \ AR5K_DIAG_SW_FRAME_NV0_5210 : AR5K_DIAG_SW_FRAME_NV0_5211) reg.h 　
26418
 AR5K_DIAG_SW_OBSPT_MAR5K_DIAG_SW_OBSPT_M 0x000c0000 reg.h Observation point select (?)
26419
 AR5K_DIAG_SW_OBSPT_SAR5K_DIAG_SW_OBSPT_S 18 reg.h 　
26420
 AR5K_DIAG_SW_RX_CLEAR_HIGHAR5K_DIAG_SW_RX_CLEAR_HIGH 0x0010000 reg.h Force RX Clear high
26421
 AR5K_DIAG_SW_IGNORE_CARR_SENSEAR5K_DIAG_SW_IGNORE_CARR_SENSE 0x0020000 reg.h Ignore virtual carrier sense
26422
 AR5K_DIAG_SW_CHANEL_IDLE_HIGHAR5K_DIAG_SW_CHANEL_IDLE_HIGH 0x0040000 reg.h Force channel idle high
26423
 AR5K_DIAG_SW_PHEAR_MEAR5K_DIAG_SW_PHEAR_ME 0x0080000 reg.h ???
26424
 AR5K_TSF_L32_5210AR5K_TSF_L32_5210 0x806c reg.h 　
26425
 AR5K_TSF_L32_5211AR5K_TSF_L32_5211 0x804c reg.h 　
26426
 AR5K_TSF_L32AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TSF_L32_5210 : AR5K_TSF_L32_5211) reg.h 　
26427
 AR5K_TSF_U32_5210AR5K_TSF_U32_5210 0x8070 reg.h 　
26428
 AR5K_TSF_U32_5211AR5K_TSF_U32_5211 0x8050 reg.h 　
26429
 AR5K_TSF_U32AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \ AR5K_TSF_U32_5210 : AR5K_TSF_U32_5211) reg.h 　
26430
 AR5K_LAST_TSTPAR5K_LAST_TSTP 0x8080 reg.h 　
26431
 AR5K_ADDAC_TESTAR5K_ADDAC_TEST 0x8054 reg.h Register Address
26432
 AR5K_ADDAC_TEST_TXCONTAR5K_ADDAC_TEST_TXCONT 0x00000001 reg.h Test continuous tx
26433
 AR5K_ADDAC_TEST_TST_MODEAR5K_ADDAC_TEST_TST_MODE 0x00000002 reg.h Test mode
26434
 AR5K_ADDAC_TEST_LOOP_ENAR5K_ADDAC_TEST_LOOP_EN 0x00000004 reg.h Enable loop
26435
 AR5K_ADDAC_TEST_LOOP_LENAR5K_ADDAC_TEST_LOOP_LEN 0x00000008 reg.h Loop length (field)
26436
 AR5K_ADDAC_TEST_USE_U8AR5K_ADDAC_TEST_USE_U8 0x00004000 reg.h Use upper 8 bits
26437
 AR5K_ADDAC_TEST_MSBAR5K_ADDAC_TEST_MSB 0x00008000 reg.h State of MSB
26438
 AR5K_ADDAC_TEST_TRIG_SELAR5K_ADDAC_TEST_TRIG_SEL 0x00010000 reg.h Trigger select
26439
 AR5K_ADDAC_TEST_TRIG_PTYAR5K_ADDAC_TEST_TRIG_PTY 0x00020000 reg.h Trigger polarity
26440
 AR5K_ADDAC_TEST_RXCONTAR5K_ADDAC_TEST_RXCONT 0x00040000 reg.h Continuous capture
26441
 AR5K_ADDAC_TEST_CAPTUREAR5K_ADDAC_TEST_CAPTURE 0x00080000 reg.h Begin capture
26442
 AR5K_ADDAC_TEST_TST_ARMAR5K_ADDAC_TEST_TST_ARM 0x00100000 reg.h ARM rx buffer for capture
26443
 AR5K_DEFAULT_ANTENNAAR5K_DEFAULT_ANTENNA 0x8058 reg.h 　
26444
 AR5K_FRAME_CTL_QOSMAR5K_FRAME_CTL_QOSM 0x805c reg.h 　
26445
 AR5K_SEQ_MASKAR5K_SEQ_MASK 0x8060 reg.h 　
26446
 AR5K_RETRY_CNTAR5K_RETRY_CNT 0x8084 reg.h Register Address [5210]
26447
 AR5K_RETRY_CNT_SSHAR5K_RETRY_CNT_SSH 0x0000003f reg.h Station short retry count (?)
26448
 AR5K_RETRY_CNT_SLGAR5K_RETRY_CNT_SLG 0x00000fc0 reg.h Station long retry count (?)
26449
 AR5K_BACKOFFAR5K_BACKOFF 0x8088 reg.h Register Address [5210]
26450
 AR5K_BACKOFF_CWAR5K_BACKOFF_CW 0x000003ff reg.h Backoff Contention Window (?)
26451
 AR5K_BACKOFF_CNTAR5K_BACKOFF_CNT 0x03ff0000 reg.h Backoff count (?)
26452
 AR5K_NAV_5210AR5K_NAV_5210 0x808c reg.h 　
26453
 AR5K_NAV_5211AR5K_NAV_5211 0x8084 reg.h 　
26454
 AR5K_NAVAR5K_NAV (ah->ah_version == AR5K_AR5210 ? \ AR5K_NAV_5210 : AR5K_NAV_5211) reg.h 　
26455
 AR5K_RTS_OK_5210AR5K_RTS_OK_5210 0x8090 reg.h 　
26456
 AR5K_RTS_OK_5211AR5K_RTS_OK_5211 0x8088 reg.h 　
26457
 AR5K_RTS_OKAR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \ AR5K_RTS_OK_5210 : AR5K_RTS_OK_5211) reg.h 　
26458
 AR5K_RTS_FAIL_5210AR5K_RTS_FAIL_5210 0x8094 reg.h 　
26459
 AR5K_RTS_FAIL_5211AR5K_RTS_FAIL_5211 0x808c reg.h 　
26460
 AR5K_RTS_FAILAR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_RTS_FAIL_5210 : AR5K_RTS_FAIL_5211) reg.h 　
26461
 AR5K_ACK_FAIL_5210AR5K_ACK_FAIL_5210 0x8098 reg.h 　
26462
 AR5K_ACK_FAIL_5211AR5K_ACK_FAIL_5211 0x8090 reg.h 　
26463
 AR5K_ACK_FAILAR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_ACK_FAIL_5210 : AR5K_ACK_FAIL_5211) reg.h 　
26464
 AR5K_FCS_FAIL_5210AR5K_FCS_FAIL_5210 0x809c reg.h 　
26465
 AR5K_FCS_FAIL_5211AR5K_FCS_FAIL_5211 0x8094 reg.h 　
26466
 AR5K_FCS_FAILAR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \ AR5K_FCS_FAIL_5210 : AR5K_FCS_FAIL_5211) reg.h 　
26467
 AR5K_BEACON_CNT_5210AR5K_BEACON_CNT_5210 0x80a0 reg.h 　
26468
 AR5K_BEACON_CNT_5211AR5K_BEACON_CNT_5211 0x8098 reg.h 　
26469
 AR5K_BEACON_CNTAR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \ AR5K_BEACON_CNT_5210 : AR5K_BEACON_CNT_5211) reg.h 　
26470
 AR5K_TPCAR5K_TPC 0x80e8 reg.h 　
26471
 AR5K_TPC_ACKAR5K_TPC_ACK 0x0000003f reg.h ack frames
26472
 AR5K_TPC_ACK_SAR5K_TPC_ACK_S 0 reg.h 　
26473
 AR5K_TPC_CTSAR5K_TPC_CTS 0x00003f00 reg.h cts frames
26474
 AR5K_TPC_CTS_SAR5K_TPC_CTS_S 8 reg.h 　
26475
 AR5K_TPC_CHIRPAR5K_TPC_CHIRP 0x003f0000 reg.h chirp frames
26476
 AR5K_TPC_CHIRP_SAR5K_TPC_CHIRP_S 16 reg.h 　
26477
 AR5K_TPC_DOPPLERAR5K_TPC_DOPPLER 0x0f000000 reg.h doppler chirp span
26478
 AR5K_TPC_DOPPLER_SAR5K_TPC_DOPPLER_S 24 reg.h 　
26479
 AR5K_XRMODEAR5K_XRMODE 0x80c0 reg.h Register Address
26480
 AR5K_XRMODE_POLL_TYPE_MAR5K_XRMODE_POLL_TYPE_M 0x0000003f reg.h Mask for Poll type (?)
26481
 AR5K_XRMODE_POLL_TYPE_SAR5K_XRMODE_POLL_TYPE_S 0 reg.h 　
26482
 AR5K_XRMODE_POLL_SUBTYPE_MAR5K_XRMODE_POLL_SUBTYPE_M 0x0000003c reg.h Mask for Poll subtype (?)
26483
 AR5K_XRMODE_POLL_SUBTYPE_SAR5K_XRMODE_POLL_SUBTYPE_S 2 reg.h 　
26484
 AR5K_XRMODE_POLL_WAIT_ALLAR5K_XRMODE_POLL_WAIT_ALL 0x00000080 reg.h Wait for poll
26485
 AR5K_XRMODE_SIFS_DELAYAR5K_XRMODE_SIFS_DELAY 0x000fff00 reg.h Mask for SIFS delay
26486
 AR5K_XRMODE_FRAME_HOLD_MAR5K_XRMODE_FRAME_HOLD_M 0xfff00000 reg.h Mask for frame hold (?)
26487
 AR5K_XRMODE_FRAME_HOLD_SAR5K_XRMODE_FRAME_HOLD_S 20 reg.h 　
26488
 AR5K_XRDELAYAR5K_XRDELAY 0x80c4 reg.h Register Address
26489
 AR5K_XRDELAY_SLOT_DELAY_MAR5K_XRDELAY_SLOT_DELAY_M 0x0000ffff reg.h Mask for slot delay
26490
 AR5K_XRDELAY_SLOT_DELAY_SAR5K_XRDELAY_SLOT_DELAY_S 0 reg.h 　
26491
 AR5K_XRDELAY_CHIRP_DELAY_MAR5K_XRDELAY_CHIRP_DELAY_M 0xffff0000 reg.h Mask for CHIRP data delay
26492
 AR5K_XRDELAY_CHIRP_DELAY_SAR5K_XRDELAY_CHIRP_DELAY_S 16 reg.h 　
26493
 AR5K_XRTIMEOUTAR5K_XRTIMEOUT 0x80c8 reg.h Register Address
26494
 AR5K_XRTIMEOUT_CHIRP_MAR5K_XRTIMEOUT_CHIRP_M 0x0000ffff reg.h Mask for CHIRP timeout
26495
 AR5K_XRTIMEOUT_CHIRP_SAR5K_XRTIMEOUT_CHIRP_S 0 reg.h 　
26496
 AR5K_XRTIMEOUT_POLL_MAR5K_XRTIMEOUT_POLL_M 0xffff0000 reg.h Mask for Poll timeout
26497
 AR5K_XRTIMEOUT_POLL_SAR5K_XRTIMEOUT_POLL_S 16 reg.h 　
26498
 AR5K_XRCHIRPAR5K_XRCHIRP 0x80cc reg.h Register Address
26499
 AR5K_XRCHIRP_SENDAR5K_XRCHIRP_SEND 0x00000001 reg.h Send CHIRP
26500
 AR5K_XRCHIRP_GAPAR5K_XRCHIRP_GAP 0xffff0000 reg.h Mask for CHIRP gap (?)
26501
 AR5K_XRSTOMPAR5K_XRSTOMP 0x80d0 reg.h Register Address
26502
 AR5K_XRSTOMP_TXAR5K_XRSTOMP_TX 0x00000001 reg.h Stomp Tx (?)
26503
 AR5K_XRSTOMP_RXAR5K_XRSTOMP_RX 0x00000002 reg.h Stomp Rx (?)
26504
 AR5K_XRSTOMP_TX_RSSIAR5K_XRSTOMP_TX_RSSI 0x00000004 reg.h Stomp Tx RSSI (?)
26505
 AR5K_XRSTOMP_TX_BSSIDAR5K_XRSTOMP_TX_BSSID 0x00000008 reg.h Stomp Tx BSSID (?)
26506
 AR5K_XRSTOMP_DATAAR5K_XRSTOMP_DATA 0x00000010 reg.h Stomp data (?)
26507
 AR5K_XRSTOMP_RSSI_THRESAR5K_XRSTOMP_RSSI_THRES 0x0000ff00 reg.h Mask for XR RSSI threshold
26508
 AR5K_SLEEP0AR5K_SLEEP0 0x80d4 reg.h Register Address
26509
 AR5K_SLEEP0_NEXT_DTIMAR5K_SLEEP0_NEXT_DTIM 0x0007ffff reg.h Mask for next DTIM (?)
26510
 AR5K_SLEEP0_NEXT_DTIM_SAR5K_SLEEP0_NEXT_DTIM_S 0 reg.h 　
26511
 AR5K_SLEEP0_ASSUME_DTIMAR5K_SLEEP0_ASSUME_DTIM 0x00080000 reg.h Assume DTIM
26512
 AR5K_SLEEP0_ENH_SLEEP_ENAR5K_SLEEP0_ENH_SLEEP_EN 0x00100000 reg.h Enable enchanced sleep control
26513
 AR5K_SLEEP0_CABTOAR5K_SLEEP0_CABTO 0xff000000 reg.h Mask for CAB Time Out
26514
 AR5K_SLEEP0_CABTO_SAR5K_SLEEP0_CABTO_S 24 reg.h 　
26515
 AR5K_SLEEP1AR5K_SLEEP1 0x80d8 reg.h Register Address
26516
 AR5K_SLEEP1_NEXT_TIMAR5K_SLEEP1_NEXT_TIM 0x0007ffff reg.h Mask for next TIM (?)
26517
 AR5K_SLEEP1_NEXT_TIM_SAR5K_SLEEP1_NEXT_TIM_S 0 reg.h 　
26518
 AR5K_SLEEP1_BEACON_TOAR5K_SLEEP1_BEACON_TO 0xff000000 reg.h Mask for Beacon Time Out
26519
 AR5K_SLEEP1_BEACON_TO_SAR5K_SLEEP1_BEACON_TO_S 24 reg.h 　
26520
 AR5K_SLEEP2AR5K_SLEEP2 0x80dc reg.h Register Address
26521
 AR5K_SLEEP2_TIM_PERAR5K_SLEEP2_TIM_PER 0x0000ffff reg.h Mask for TIM period (?)
26522
 AR5K_SLEEP2_TIM_PER_SAR5K_SLEEP2_TIM_PER_S 0 reg.h 　
26523
 AR5K_SLEEP2_DTIM_PERAR5K_SLEEP2_DTIM_PER 0xffff0000 reg.h Mask for DTIM period (?)
26524
 AR5K_SLEEP2_DTIM_PER_SAR5K_SLEEP2_DTIM_PER_S 16 reg.h 　
26525
 AR5K_BSS_IDM0AR5K_BSS_IDM0 0x80e0 reg.h Upper bits
26526
 AR5K_BSS_IDM1AR5K_BSS_IDM1 0x80e4 reg.h Lower bits
26527
 AR5K_TXPCAR5K_TXPC 0x80e8 reg.h Register Address
26528
 AR5K_TXPC_ACK_MAR5K_TXPC_ACK_M 0x0000003f reg.h ACK tx power
26529
 AR5K_TXPC_ACK_SAR5K_TXPC_ACK_S 0 reg.h 　
26530
 AR5K_TXPC_CTS_MAR5K_TXPC_CTS_M 0x00003f00 reg.h CTS tx power
26531
 AR5K_TXPC_CTS_SAR5K_TXPC_CTS_S 8 reg.h 　
26532
 AR5K_TXPC_CHIRP_MAR5K_TXPC_CHIRP_M 0x003f0000 reg.h CHIRP tx power
26533
 AR5K_TXPC_CHIRP_SAR5K_TXPC_CHIRP_S 16 reg.h 　
26534
 AR5K_TXPC_DOPPLERAR5K_TXPC_DOPPLER 0x0f000000 reg.h Doppler chirp span (?)
26535
 AR5K_TXPC_DOPPLER_SAR5K_TXPC_DOPPLER_S 24 reg.h 　
26536
 AR5K_PROFCNT_TXAR5K_PROFCNT_TX 0x80ec reg.h Tx count
26537
 AR5K_PROFCNT_RXAR5K_PROFCNT_RX 0x80f0 reg.h Rx count
26538
 AR5K_PROFCNT_RXCLRAR5K_PROFCNT_RXCLR 0x80f4 reg.h Clear Rx count
26539
 AR5K_PROFCNT_CYCLEAR5K_PROFCNT_CYCLE 0x80f8 reg.h Cycle count (?)
26540
 AR5K_QUIET_CTL1AR5K_QUIET_CTL1 0x80fc reg.h Register Address
26541
 AR5K_QUIET_CTL1_NEXT_QT_TSFAR5K_QUIET_CTL1_NEXT_QT_TSF 0x0000ffff reg.h Next quiet period TSF (TU)
26542
 AR5K_QUIET_CTL1_NEXT_QT_TSF_SAR5K_QUIET_CTL1_NEXT_QT_TSF_S 0 reg.h 　
26543
 AR5K_QUIET_CTL1_QT_ENAR5K_QUIET_CTL1_QT_EN 0x00010000 reg.h Enable quiet period
26544
 AR5K_QUIET_CTL1_ACK_CTS_ENAR5K_QUIET_CTL1_ACK_CTS_EN 0x00020000 reg.h Send ACK/CTS during quiet period
26545
 AR5K_QUIET_CTL2AR5K_QUIET_CTL2 0x8100 reg.h Register Address
26546
 AR5K_QUIET_CTL2_QT_PERAR5K_QUIET_CTL2_QT_PER 0x0000ffff reg.h Mask for quiet period periodicity
26547
 AR5K_QUIET_CTL2_QT_PER_SAR5K_QUIET_CTL2_QT_PER_S 0 reg.h 　
26548
 AR5K_QUIET_CTL2_QT_DURAR5K_QUIET_CTL2_QT_DUR 0xffff0000 reg.h Mask for quiet period duration
26549
 AR5K_QUIET_CTL2_QT_DUR_SAR5K_QUIET_CTL2_QT_DUR_S 16 reg.h 　
26550
 AR5K_TSF_PARMAR5K_TSF_PARM 0x8104 reg.h Register Address
26551
 AR5K_TSF_PARM_INCAR5K_TSF_PARM_INC 0x000000ff reg.h Mask for TSF increment
26552
 AR5K_TSF_PARM_INC_SAR5K_TSF_PARM_INC_S 0 reg.h 　
26553
 AR5K_QOS_NOACKAR5K_QOS_NOACK 0x8108 reg.h Register Address
26554
 AR5K_QOS_NOACK_2BIT_VALUESAR5K_QOS_NOACK_2BIT_VALUES 0x0000000f reg.h ???
26555
 AR5K_QOS_NOACK_2BIT_VALUES_SAR5K_QOS_NOACK_2BIT_VALUES_S 0 reg.h 　
26556
 AR5K_QOS_NOACK_BIT_OFFSETAR5K_QOS_NOACK_BIT_OFFSET 0x00000070 reg.h ???
26557
 AR5K_QOS_NOACK_BIT_OFFSET_SAR5K_QOS_NOACK_BIT_OFFSET_S 4 reg.h 　
26558
 AR5K_QOS_NOACK_BYTE_OFFSETAR5K_QOS_NOACK_BYTE_OFFSET 0x00000180 reg.h ???
26559
 AR5K_QOS_NOACK_BYTE_OFFSET_SAR5K_QOS_NOACK_BYTE_OFFSET_S 7 reg.h 　
26560
 AR5K_PHY_ERR_FILAR5K_PHY_ERR_FIL 0x810c reg.h 　
26561
 AR5K_PHY_ERR_FIL_RADARAR5K_PHY_ERR_FIL_RADAR 0x00000020 reg.h Radar signal
26562
 AR5K_PHY_ERR_FIL_OFDMAR5K_PHY_ERR_FIL_OFDM 0x00020000 reg.h OFDM false detect (ANI)
26563
 AR5K_PHY_ERR_FIL_CCKAR5K_PHY_ERR_FIL_CCK 0x02000000 reg.h CCK false detect (ANI)
26564
 AR5K_XRLAT_TXAR5K_XRLAT_TX 0x8110 reg.h 　
26565
 AR5K_ACKSIFSAR5K_ACKSIFS 0x8114 reg.h Register Address
26566
 AR5K_ACKSIFS_INCAR5K_ACKSIFS_INC 0x00000000 reg.h ACK SIFS Increment (field)
26567
 AR5K_MIC_QOS_CTLAR5K_MIC_QOS_CTL 0x8118 reg.h Register Address
26568
 AR5K_MIC_QOS_CTL_MQ_ENAR5K_MIC_QOS_CTL_MQ_EN 0x00010000 reg.h Enable MIC QoS
26569
 AR5K_MIC_QOS_SELAR5K_MIC_QOS_SEL 0x811c reg.h 　
26570
 AR5K_MISC_MODEAR5K_MISC_MODE 0x8120 reg.h Register Address
26571
 AR5K_MISC_MODE_FBSSID_MATCHAR5K_MISC_MODE_FBSSID_MATCH 0x00000001 reg.h Force BSSID match
26572
 AR5K_MISC_MODE_ACKSIFS_MEMAR5K_MISC_MODE_ACKSIFS_MEM 0x00000002 reg.h ACK SIFS memory (?)
26573
 AR5K_MISC_MODE_COMBINED_MICAR5K_MISC_MODE_COMBINED_MIC 0x00000004 reg.h use rx/tx MIC key
26574
 AR5K_OFDM_FIL_CNTAR5K_OFDM_FIL_CNT 0x8124 reg.h 　
26575
 AR5K_CCK_FIL_CNTAR5K_CCK_FIL_CNT 0x8128 reg.h 　
26576
 AR5K_PHYERR_CNT1AR5K_PHYERR_CNT1 0x812c reg.h 　
26577
 AR5K_PHYERR_CNT1_MASKAR5K_PHYERR_CNT1_MASK 0x8130 reg.h 　
26578
 AR5K_PHYERR_CNT2AR5K_PHYERR_CNT2 0x8134 reg.h 　
26579
 AR5K_PHYERR_CNT2_MASKAR5K_PHYERR_CNT2_MASK 0x8138 reg.h 　
26580
 AR5K_TSF_THRESAR5K_TSF_THRES 0x813c reg.h 　
26581
 AR5K_RATE_ACKSIFS_BASEAR5K_RATE_ACKSIFS_BASE 0x8680 reg.h Register Address
26582
 AR5K_RATE_ACKSIFS_NORMALAR5K_RATE_ACKSIFS_NORMAL 0x00000001 reg.h Normal SIFS (field)
26583
 AR5K_RATE_ACKSIFS_TURBOAR5K_RATE_ACKSIFS_TURBO 0x00000400 reg.h Turbo SIFS (field)
26584
 AR5K_RATE_DUR_BASEAR5K_RATE_DUR_BASE 0x8700 reg.h 　
26585
 AR5K_RATE2DB_BASEAR5K_RATE2DB_BASE 0x87c0 reg.h 　
26586
 AR5K_DB2RATE_BASEAR5K_DB2RATE_BASE 0x87e0 reg.h 　
26587
 AR5K_KEYTABLE_0_5210AR5K_KEYTABLE_0_5210 0x9000 reg.h 　
26588
 AR5K_KEYTABLE_0_5211AR5K_KEYTABLE_0_5211 0x8800 reg.h 　
26589
 AR5K_KEYTABLE_TYPE_40AR5K_KEYTABLE_TYPE_40 0x00000000 reg.h 　
26590
 AR5K_KEYTABLE_TYPE_104AR5K_KEYTABLE_TYPE_104 0x00000001 reg.h 　
26591
 AR5K_KEYTABLE_TYPE_128AR5K_KEYTABLE_TYPE_128 0x00000003 reg.h 　
26592
 AR5K_KEYTABLE_TYPE_TKIPAR5K_KEYTABLE_TYPE_TKIP 0x00000004 reg.h [5212+]
26593
 AR5K_KEYTABLE_TYPE_AESAR5K_KEYTABLE_TYPE_AES 0x00000005 reg.h [5211+]
26594
 AR5K_KEYTABLE_TYPE_CCMAR5K_KEYTABLE_TYPE_CCM 0x00000006 reg.h [5212+]
26595
 AR5K_KEYTABLE_TYPE_NULLAR5K_KEYTABLE_TYPE_NULL 0x00000007 reg.h [5211+]
26596
 AR5K_KEYTABLE_ANTENNAAR5K_KEYTABLE_ANTENNA 0x00000008 reg.h [5212+]
26597
 AR5K_KEYTABLE_VALIDAR5K_KEYTABLE_VALID 0x00008000 reg.h 　
26598
 AR5K_KEYTABLE_MIC_OFFSETAR5K_KEYTABLE_MIC_OFFSET 64 reg.h 　
26599
 AR5K_KEYTABLE_SIZE_5210AR5K_KEYTABLE_SIZE_5210 64 reg.h 　
26600
 AR5K_KEYTABLE_SIZE_5211AR5K_KEYTABLE_SIZE_5211 128 reg.h 　
26601
 AR5K_KEYTABLE_SIZEAR5K_KEYTABLE_SIZE (ah->ah_version == AR5K_AR5210 ? \ AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211) reg.h 　
26602
 AR5K_PHY_BASEAR5K_PHY_BASE 0x9800 reg.h 　
26603
 AR5K_PHY_TST2AR5K_PHY_TST2 0x9800 reg.h Register Address
26604
 AR5K_PHY_TST2_TRIG_SELAR5K_PHY_TST2_TRIG_SEL 0x00000007 reg.h Trigger select (?)
26605
 AR5K_PHY_TST2_TRIGAR5K_PHY_TST2_TRIG 0x00000010 reg.h Trigger (?)
26606
 AR5K_PHY_TST2_CBUS_MODEAR5K_PHY_TST2_CBUS_MODE 0x00000060 reg.h Cardbus mode (?)
26607
 AR5K_PHY_TST2_CLK32AR5K_PHY_TST2_CLK32 0x00000400 reg.h CLK_OUT is CLK32 (32Khz external)
26608
 AR5K_PHY_TST2_CHANCOR_DUMP_ENAR5K_PHY_TST2_CHANCOR_DUMP_EN 0x00000800 reg.h Enable Chancor dump (?)
26609
 AR5K_PHY_TST2_EVEN_CHANCOR_DUMPAR5K_PHY_TST2_EVEN_CHANCOR_DUMP 0x00001000 reg.h Even Chancor dump (?)
26610
 AR5K_PHY_TST2_RFSILENT_ENAR5K_PHY_TST2_RFSILENT_EN 0x00002000 reg.h Enable RFSILENT
26611
 AR5K_PHY_TST2_ALT_RFDATAAR5K_PHY_TST2_ALT_RFDATA 0x00004000 reg.h Alternate RFDATA (5-2GHz switch ?)
26612
 AR5K_PHY_TST2_MINI_OBS_ENAR5K_PHY_TST2_MINI_OBS_EN 0x00008000 reg.h Enable mini OBS (?)
26613
 AR5K_PHY_TST2_RX2_IS_RX5_INVAR5K_PHY_TST2_RX2_IS_RX5_INV 0x00010000 reg.h 2GHz rx path is the 5GHz path inverted (?)
26614
 AR5K_PHY_TST2_SLOW_CLK160AR5K_PHY_TST2_SLOW_CLK160 0x00020000 reg.h Slow CLK160 (?)
26615
 AR5K_PHY_TST2_AGC_OBS_SEL_3AR5K_PHY_TST2_AGC_OBS_SEL_3 0x00040000 reg.h AGC OBS Select 3 (?)
26616
 AR5K_PHY_TST2_BBB_OBS_SELAR5K_PHY_TST2_BBB_OBS_SEL 0x00080000 reg.h BB OBS Select (field ?)
26617
 AR5K_PHY_TST2_ADC_OBS_SELAR5K_PHY_TST2_ADC_OBS_SEL 0x00800000 reg.h ADC OBS Select (field ?)
26618
 AR5K_PHY_TST2_RX_CLR_SELAR5K_PHY_TST2_RX_CLR_SEL 0x08000000 reg.h RX Clear Select (?)
26619
 AR5K_PHY_TST2_FORCE_AGC_CLRAR5K_PHY_TST2_FORCE_AGC_CLR 0x10000000 reg.h Force AGC clear (?)
26620
 AR5K_PHY_SHIFT_2GHZAR5K_PHY_SHIFT_2GHZ 0x00004007 reg.h Used to access 2GHz radios
26621
 AR5K_PHY_SHIFT_5GHZAR5K_PHY_SHIFT_5GHZ 0x00000007 reg.h Used to access 5GHz radios (default)
26622
 AR5K_PHY_TURBOAR5K_PHY_TURBO 0x9804 reg.h Register Address
26623
 AR5K_PHY_TURBO_MODEAR5K_PHY_TURBO_MODE 0x00000001 reg.h Enable turbo mode
26624
 AR5K_PHY_TURBO_SHORTAR5K_PHY_TURBO_SHORT 0x00000002 reg.h Set short symbols to turbo mode
26625
 AR5K_PHY_TURBO_MIMOAR5K_PHY_TURBO_MIMO 0x00000004 reg.h Set turbo for mimo mimo
26626
 AR5K_PHY_AGCAR5K_PHY_AGC 0x9808 reg.h Register Address
26627
 AR5K_PHY_TST1AR5K_PHY_TST1 0x9808 reg.h 　
26628
 AR5K_PHY_AGC_DISABLEAR5K_PHY_AGC_DISABLE 0x08000000 reg.h Disable AGC to A2 (?)
26629
 AR5K_PHY_TST1_TXHOLDAR5K_PHY_TST1_TXHOLD 0x00003800 reg.h Set tx hold (?)
26630
 AR5K_PHY_TST1_TXSRC_SRCAR5K_PHY_TST1_TXSRC_SRC 0x00000002 reg.h Used with bit 7 (?)
26631
 AR5K_PHY_TST1_TXSRC_SRC_SAR5K_PHY_TST1_TXSRC_SRC_S 1 reg.h 　
26632
 AR5K_PHY_TST1_TXSRC_ALTAR5K_PHY_TST1_TXSRC_ALT 0x00000080 reg.h Set input to tsdac (?)
26633
 AR5K_PHY_TST1_TXSRC_ALT_SAR5K_PHY_TST1_TXSRC_ALT_S 7 reg.h 　
26634
 AR5K_PHY_TIMING_3AR5K_PHY_TIMING_3 0x9814 reg.h 　
26635
 AR5K_PHY_TIMING_3_DSC_MANAR5K_PHY_TIMING_3_DSC_MAN 0xfffe0000 reg.h 　
26636
 AR5K_PHY_TIMING_3_DSC_MAN_SAR5K_PHY_TIMING_3_DSC_MAN_S 17 reg.h 　
26637
 AR5K_PHY_TIMING_3_DSC_EXPAR5K_PHY_TIMING_3_DSC_EXP 0x0001e000 reg.h 　
26638
 AR5K_PHY_TIMING_3_DSC_EXP_SAR5K_PHY_TIMING_3_DSC_EXP_S 13 reg.h 　
26639
 AR5K_PHY_CHIP_IDAR5K_PHY_CHIP_ID 0x9818 reg.h 　
26640
 AR5K_PHY_ACTAR5K_PHY_ACT 0x981c reg.h Register Address
26641
 AR5K_PHY_ACT_ENABLEAR5K_PHY_ACT_ENABLE 0x00000001 reg.h Activate PHY
26642
 AR5K_PHY_ACT_DISABLEAR5K_PHY_ACT_DISABLE 0x00000002 reg.h Deactivate PHY
26643
 AR5K_PHY_RF_CTL2AR5K_PHY_RF_CTL2 0x9824 reg.h Register Address
26644
 AR5K_PHY_RF_CTL2_TXF2TXD_STARTAR5K_PHY_RF_CTL2_TXF2TXD_START 0x0000000f reg.h TX frame to TX data start
26645
 AR5K_PHY_RF_CTL2_TXF2TXD_START_AR5K_PHY_RF_CTL2_TXF2TXD_START_ 0 reg.h 　
26646
 AR5K_PHY_RF_CTL3AR5K_PHY_RF_CTL3 0x9828 reg.h Register Address
26647
 AR5K_PHY_RF_CTL3_TXE2XLNA_ONAR5K_PHY_RF_CTL3_TXE2XLNA_ON 0x0000ff00 reg.h TX end to XLNA on
26648
 AR5K_PHY_RF_CTL3_TXE2XLNA_ON_SAR5K_PHY_RF_CTL3_TXE2XLNA_ON_S 8 reg.h 　
26649
 AR5K_PHY_ADC_CTLAR5K_PHY_ADC_CTL 0x982c reg.h 　
26650
 AR5K_PHY_ADC_CTL_INBUFGAIN_OFFAR5K_PHY_ADC_CTL_INBUFGAIN_OFF 0x00000003 reg.h 　
26651
 AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_AR5K_PHY_ADC_CTL_INBUFGAIN_OFF_ 0 reg.h 　
26652
 AR5K_PHY_ADC_CTL_PWD_DAC_OFFAR5K_PHY_ADC_CTL_PWD_DAC_OFF 0x00002000 reg.h 　
26653
 AR5K_PHY_ADC_CTL_PWD_BAND_GAP_OAR5K_PHY_ADC_CTL_PWD_BAND_GAP_O 0x00004000 reg.h 　
26654
 AR5K_PHY_ADC_CTL_PWD_ADC_OFFAR5K_PHY_ADC_CTL_PWD_ADC_OFF 0x00008000 reg.h 　
26655
 AR5K_PHY_ADC_CTL_INBUFGAIN_ONAR5K_PHY_ADC_CTL_INBUFGAIN_ON 0x00030000 reg.h 　
26656
 AR5K_PHY_ADC_CTL_INBUFGAIN_ON_SAR5K_PHY_ADC_CTL_INBUFGAIN_ON_S 16 reg.h 　
26657
 AR5K_PHY_RF_CTL4AR5K_PHY_RF_CTL4 0x9834 reg.h Register Address
26658
 AR5K_PHY_RF_CTL4_TXF2XPA_A_ONAR5K_PHY_RF_CTL4_TXF2XPA_A_ON 0x00000001 reg.h TX frame to XPA A on (field)
26659
 AR5K_PHY_RF_CTL4_TXF2XPA_B_ONAR5K_PHY_RF_CTL4_TXF2XPA_B_ON 0x00000100 reg.h TX frame to XPA B on (field)
26660
 AR5K_PHY_RF_CTL4_TXE2XPA_A_OFFAR5K_PHY_RF_CTL4_TXE2XPA_A_OFF 0x00010000 reg.h TX end to XPA A off (field)
26661
 AR5K_PHY_RF_CTL4_TXE2XPA_B_OFFAR5K_PHY_RF_CTL4_TXE2XPA_B_OFF 0x01000000 reg.h TX end to XPA B off (field)
26662
 AR5K_PHY_PA_CTLAR5K_PHY_PA_CTL 0x9838 reg.h Register Address
26663
 AR5K_PHY_PA_CTL_XPA_A_HIAR5K_PHY_PA_CTL_XPA_A_HI 0x00000001 reg.h XPA A high (?)
26664
 AR5K_PHY_PA_CTL_XPA_B_HIAR5K_PHY_PA_CTL_XPA_B_HI 0x00000002 reg.h XPA B high (?)
26665
 AR5K_PHY_PA_CTL_XPA_A_ENAR5K_PHY_PA_CTL_XPA_A_EN 0x00000004 reg.h Enable XPA A
26666
 AR5K_PHY_PA_CTL_XPA_B_ENAR5K_PHY_PA_CTL_XPA_B_EN 0x00000008 reg.h Enable XPA B
26667
 AR5K_PHY_SETTLINGAR5K_PHY_SETTLING 0x9844 reg.h Register Address
26668
 AR5K_PHY_SETTLING_AGCAR5K_PHY_SETTLING_AGC 0x0000007f reg.h AGC settling time
26669
 AR5K_PHY_SETTLING_AGC_SAR5K_PHY_SETTLING_AGC_S 0 reg.h 　
26670
 AR5K_PHY_SETTLING_SWITCHAR5K_PHY_SETTLING_SWITCH 0x00003f80 reg.h Switch settlig time
26671
 AR5K_PHY_SETTLING_SWITCH_SAR5K_PHY_SETTLING_SWITCH_S 7 reg.h 　
26672
 AR5K_PHY_GAINAR5K_PHY_GAIN 0x9848 reg.h Register Address
26673
 AR5K_PHY_GAIN_TXRX_ATTENAR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 reg.h TX-RX Attenuation
26674
 AR5K_PHY_GAIN_TXRX_ATTEN_SAR5K_PHY_GAIN_TXRX_ATTEN_S 12 reg.h 　
26675
 AR5K_PHY_GAIN_TXRX_RF_MAXAR5K_PHY_GAIN_TXRX_RF_MAX 0x007c0000 reg.h 　
26676
 AR5K_PHY_GAIN_TXRX_RF_MAX_SAR5K_PHY_GAIN_TXRX_RF_MAX_S 18 reg.h 　
26677
 AR5K_PHY_GAIN_OFFSETAR5K_PHY_GAIN_OFFSET 0x984c reg.h Register Address
26678
 AR5K_PHY_GAIN_OFFSET_RXTX_FLAGAR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 reg.h RX-TX flag (?)
26679
 AR5K_PHY_DESIRED_SIZEAR5K_PHY_DESIRED_SIZE 0x9850 reg.h Register Address
26680
 AR5K_PHY_DESIRED_SIZE_ADCAR5K_PHY_DESIRED_SIZE_ADC 0x000000ff reg.h ADC desired size
26681
 AR5K_PHY_DESIRED_SIZE_ADC_SAR5K_PHY_DESIRED_SIZE_ADC_S 0 reg.h 　
26682
 AR5K_PHY_DESIRED_SIZE_PGAAR5K_PHY_DESIRED_SIZE_PGA 0x0000ff00 reg.h PGA desired size
26683
 AR5K_PHY_DESIRED_SIZE_PGA_SAR5K_PHY_DESIRED_SIZE_PGA_S 8 reg.h 　
26684
 AR5K_PHY_DESIRED_SIZE_TOTAR5K_PHY_DESIRED_SIZE_TOT 0x0ff00000 reg.h Total desired size
26685
 AR5K_PHY_DESIRED_SIZE_TOT_SAR5K_PHY_DESIRED_SIZE_TOT_S 20 reg.h 　
26686
 AR5K_PHY_SIGAR5K_PHY_SIG 0x9858 reg.h Register Address
26687
 AR5K_PHY_SIG_FIRSTEPAR5K_PHY_SIG_FIRSTEP 0x0003f000 reg.h FIRSTEP
26688
 AR5K_PHY_SIG_FIRSTEP_SAR5K_PHY_SIG_FIRSTEP_S 12 reg.h 　
26689
 AR5K_PHY_SIG_FIRPWRAR5K_PHY_SIG_FIRPWR 0x03fc0000 reg.h FIPWR
26690
 AR5K_PHY_SIG_FIRPWR_SAR5K_PHY_SIG_FIRPWR_S 18 reg.h 　
26691
 AR5K_PHY_AGCCOARSEAR5K_PHY_AGCCOARSE 0x985c reg.h Register Address
26692
 AR5K_PHY_AGCCOARSE_LOAR5K_PHY_AGCCOARSE_LO 0x00007f80 reg.h AGC Coarse low
26693
 AR5K_PHY_AGCCOARSE_LO_SAR5K_PHY_AGCCOARSE_LO_S 7 reg.h 　
26694
 AR5K_PHY_AGCCOARSE_HIAR5K_PHY_AGCCOARSE_HI 0x003f8000 reg.h AGC Coarse high
26695
 AR5K_PHY_AGCCOARSE_HI_SAR5K_PHY_AGCCOARSE_HI_S 15 reg.h 　
26696
 AR5K_PHY_AGCCTLAR5K_PHY_AGCCTL 0x9860 reg.h Register address
26697
 AR5K_PHY_AGCCTL_CALAR5K_PHY_AGCCTL_CAL 0x00000001 reg.h Enable PHY calibration
26698
 AR5K_PHY_AGCCTL_NFAR5K_PHY_AGCCTL_NF 0x00000002 reg.h Enable Noise Floor calibration
26699
 AR5K_PHY_AGCCTL_NF_ENAR5K_PHY_AGCCTL_NF_EN 0x00008000 reg.h Enable nf calibration to happen (?)
26700
 AR5K_PHY_AGCCTL_NF_NOUPDATEAR5K_PHY_AGCCTL_NF_NOUPDATE 0x00020000 reg.h Don't update nf automaticaly
26701
 AR5K_PHY_NFAR5K_PHY_NF 0x9864 reg.h Register address
26702
 AR5K_PHY_NF_MAR5K_PHY_NF_M 0x000001ff reg.h Noise floor mask
26703
 AR5K_PHY_NF_ACTIVEAR5K_PHY_NF_ACTIVE 0x00000100 reg.h Noise floor calibration still active
26704
 AR5K_PHY_NF_THRESH62AR5K_PHY_NF_THRESH62 0x0007f000 reg.h Thresh62 -check ANI patent- (field)
26705
 AR5K_PHY_NF_THRESH62_SAR5K_PHY_NF_THRESH62_S 12 reg.h 　
26706
 AR5K_PHY_NF_MINCCA_PWRAR5K_PHY_NF_MINCCA_PWR 0x0ff80000 reg.h ???
26707
 AR5K_PHY_NF_MINCCA_PWR_SAR5K_PHY_NF_MINCCA_PWR_S 19 reg.h 　
26708
 AR5K_PHY_ADCSATAR5K_PHY_ADCSAT 0x9868 reg.h 　
26709
 AR5K_PHY_ADCSAT_ICNTAR5K_PHY_ADCSAT_ICNT 0x0001f800 reg.h 　
26710
 AR5K_PHY_ADCSAT_ICNT_SAR5K_PHY_ADCSAT_ICNT_S 11 reg.h 　
26711
 AR5K_PHY_ADCSAT_THRAR5K_PHY_ADCSAT_THR 0x000007e0 reg.h 　
26712
 AR5K_PHY_ADCSAT_THR_SAR5K_PHY_ADCSAT_THR_S 5 reg.h 　
26713
 AR5K_PHY_WEAK_OFDM_HIGH_THRAR5K_PHY_WEAK_OFDM_HIGH_THR 0x9868 reg.h 　
26714
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 0x0000001f reg.h 　
26715
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 0 reg.h 　
26716
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M1AR5K_PHY_WEAK_OFDM_HIGH_THR_M1 0x00fe0000 reg.h 　
26717
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_AR5K_PHY_WEAK_OFDM_HIGH_THR_M1_ 17 reg.h 　
26718
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2AR5K_PHY_WEAK_OFDM_HIGH_THR_M2 0x7f000000 reg.h 　
26719
 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_ 24 reg.h 　
26720
 AR5K_PHY_WEAK_OFDM_LOW_THRAR5K_PHY_WEAK_OFDM_LOW_THR 0x986c reg.h 　
26721
 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFAR5K_PHY_WEAK_OFDM_LOW_THR_SELF 0x00000001 reg.h 　
26722
 AR5K_PHY_WEAK_OFDM_LOW_THR_M2_CAR5K_PHY_WEAK_OFDM_LOW_THR_M2_C 0x00003f00 reg.h 　
26723
 AR5K_PHY_WEAK_OFDM_LOW_THR_M2_CAR5K_PHY_WEAK_OFDM_LOW_THR_M2_C 8 reg.h 　
26724
 AR5K_PHY_WEAK_OFDM_LOW_THR_M1AR5K_PHY_WEAK_OFDM_LOW_THR_M1 0x001fc000 reg.h 　
26725
 AR5K_PHY_WEAK_OFDM_LOW_THR_M1_SAR5K_PHY_WEAK_OFDM_LOW_THR_M1_S 14 reg.h 　
26726
 AR5K_PHY_WEAK_OFDM_LOW_THR_M2AR5K_PHY_WEAK_OFDM_LOW_THR_M2 0x0fe00000 reg.h 　
26727
 AR5K_PHY_WEAK_OFDM_LOW_THR_M2_SAR5K_PHY_WEAK_OFDM_LOW_THR_M2_S 21 reg.h 　
26728
 AR5K_PHY_SCRAR5K_PHY_SCR 0x9870 reg.h 　
26729
 AR5K_PHY_SLMTAR5K_PHY_SLMT 0x9874 reg.h 　
26730
 AR5K_PHY_SLMT_32MHZAR5K_PHY_SLMT_32MHZ 0x0000007f reg.h 　
26731
 AR5K_PHY_SCALAR5K_PHY_SCAL 0x9878 reg.h 　
26732
 AR5K_PHY_SCAL_32MHZAR5K_PHY_SCAL_32MHZ 0x0000000e reg.h 　
26733
 AR5K_PHY_SCAL_32MHZ_2417AR5K_PHY_SCAL_32MHZ_2417 0x0000000a reg.h 　
26734
 AR5K_PHY_SCAL_32MHZ_HB63AR5K_PHY_SCAL_32MHZ_HB63 0x00000032 reg.h 　
26735
 AR5K_PHY_PLLAR5K_PHY_PLL 0x987c reg.h 　
26736
 AR5K_PHY_PLL_20MHZAR5K_PHY_PLL_20MHZ 0x00000013 reg.h For half rate (?)
26737
 AR5K_PHY_PLL_40MHZ_5211AR5K_PHY_PLL_40MHZ_5211 0x00000018 reg.h 　
26738
 AR5K_PHY_PLL_40MHZ_5212AR5K_PHY_PLL_40MHZ_5212 0x000000aa reg.h 　
26739
 AR5K_PHY_PLL_40MHZ_5413AR5K_PHY_PLL_40MHZ_5413 0x00000004 reg.h 　
26740
 AR5K_PHY_PLL_40MHZAR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \ AR5K_PHY_PLL_40MHZ_5211 : AR5K_PHY_PLL_40MHZ_5212) reg.h 　
26741
 AR5K_PHY_PLL_44MHZ_5211AR5K_PHY_PLL_44MHZ_5211 0x00000019 reg.h 　
26742
 AR5K_PHY_PLL_44MHZ_5212AR5K_PHY_PLL_44MHZ_5212 0x000000ab reg.h 　
26743
 AR5K_PHY_PLL_44MHZAR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \ AR5K_PHY_PLL_44MHZ_5211 : AR5K_PHY_PLL_44MHZ_5212) reg.h 　
26744
 AR5K_PHY_PLL_RF5111AR5K_PHY_PLL_RF5111 0x00000000 reg.h 　
26745
 AR5K_PHY_PLL_RF5112AR5K_PHY_PLL_RF5112 0x00000040 reg.h 　
26746
 AR5K_PHY_PLL_HALF_RATEAR5K_PHY_PLL_HALF_RATE 0x00000100 reg.h 　
26747
 AR5K_PHY_PLL_QUARTER_RATEAR5K_PHY_PLL_QUARTER_RATE 0x00000200 reg.h 　
26748
 AR5K_RF_BUFFERAR5K_RF_BUFFER 0x989c reg.h 　
26749
 AR5K_RF_BUFFER_CONTROL_0AR5K_RF_BUFFER_CONTROL_0 0x98c0 reg.h Channel on 5110
26750
 AR5K_RF_BUFFER_CONTROL_1AR5K_RF_BUFFER_CONTROL_1 0x98c4 reg.h Bank 7 on 5112
26751
 AR5K_RF_BUFFER_CONTROL_2AR5K_RF_BUFFER_CONTROL_2 0x98cc reg.h Bank 7 on 5111
26752
 AR5K_RF_BUFFER_CONTROL_3AR5K_RF_BUFFER_CONTROL_3 0x98d0 reg.h Bank 2 on 5112
26753
 AR5K_RF_BUFFER_CONTROL_4AR5K_RF_BUFFER_CONTROL_4 0x98d4 reg.h RF Stage register on 5110
26754
 AR5K_RF_BUFFER_CONTROL_5AR5K_RF_BUFFER_CONTROL_5 0x98d8 reg.h Bank 3 on 5111
26755
 AR5K_RF_BUFFER_CONTROL_6AR5K_RF_BUFFER_CONTROL_6 0x98dc reg.h Bank 3 on 5112
26756
 AR5K_PHY_RFSTGAR5K_PHY_RFSTG 0x98d4 reg.h 　
26757
 AR5K_PHY_RFSTG_DISABLEAR5K_PHY_RFSTG_DISABLE 0x00000021 reg.h 　
26758
 AR5K_PHY_BIN_MASK_1AR5K_PHY_BIN_MASK_1 0x9900 reg.h 　
26759
 AR5K_PHY_BIN_MASK_2AR5K_PHY_BIN_MASK_2 0x9904 reg.h 　
26760
 AR5K_PHY_BIN_MASK_3AR5K_PHY_BIN_MASK_3 0x9908 reg.h 　
26761
 AR5K_PHY_BIN_MASK_CTLAR5K_PHY_BIN_MASK_CTL 0x990c reg.h 　
26762
 AR5K_PHY_BIN_MASK_CTL_MASK_4AR5K_PHY_BIN_MASK_CTL_MASK_4 0x00003fff reg.h 　
26763
 AR5K_PHY_BIN_MASK_CTL_MASK_4_SAR5K_PHY_BIN_MASK_CTL_MASK_4_S 0 reg.h 　
26764
 AR5K_PHY_BIN_MASK_CTL_RATEAR5K_PHY_BIN_MASK_CTL_RATE 0xff000000 reg.h 　
26765
 AR5K_PHY_BIN_MASK_CTL_RATE_SAR5K_PHY_BIN_MASK_CTL_RATE_S 24 reg.h 　
26766
 AR5K_PHY_ANT_CTLAR5K_PHY_ANT_CTL 0x9910 reg.h Register Address
26767
 AR5K_PHY_ANT_CTL_TXRX_ENAR5K_PHY_ANT_CTL_TXRX_EN 0x00000001 reg.h Enable TX/RX (?)
26768
 AR5K_PHY_ANT_CTL_SECTORED_ANTAR5K_PHY_ANT_CTL_SECTORED_ANT 0x00000004 reg.h Sectored Antenna
26769
 AR5K_PHY_ANT_CTL_HITUNE5AR5K_PHY_ANT_CTL_HITUNE5 0x00000008 reg.h Hitune5 (?)
26770
 AR5K_PHY_ANT_CTL_SWTABLE_IDLEAR5K_PHY_ANT_CTL_SWTABLE_IDLE 0x000003f0 reg.h Switch table idle (?)
26771
 AR5K_PHY_ANT_CTL_SWTABLE_IDLE_SAR5K_PHY_ANT_CTL_SWTABLE_IDLE_S 4 reg.h 　
26772
 AR5K_PHY_RX_DELAYAR5K_PHY_RX_DELAY 0x9914 reg.h Register Address
26773
 AR5K_PHY_RX_DELAY_MAR5K_PHY_RX_DELAY_M 0x00003fff reg.h Mask for RX activate to receive delay (/100ns)
26774
 AR5K_PHY_MAX_RX_LENAR5K_PHY_MAX_RX_LEN 0x991c reg.h 　
26775
 AR5K_PHY_IQAR5K_PHY_IQ 0x9920 reg.h Register Address
26776
 AR5K_PHY_IQ_CORR_Q_Q_COFFAR5K_PHY_IQ_CORR_Q_Q_COFF 0x0000001f reg.h Mask for q correction info
26777
 AR5K_PHY_IQ_CORR_Q_I_COFFAR5K_PHY_IQ_CORR_Q_I_COFF 0x000007e0 reg.h Mask for i correction info
26778
 AR5K_PHY_IQ_CORR_Q_I_COFF_SAR5K_PHY_IQ_CORR_Q_I_COFF_S 5 reg.h 　
26779
 AR5K_PHY_IQ_CORR_ENABLEAR5K_PHY_IQ_CORR_ENABLE 0x00000800 reg.h Enable i/q correction
26780
 AR5K_PHY_IQ_CAL_NUM_LOG_MAXAR5K_PHY_IQ_CAL_NUM_LOG_MAX 0x0000f000 reg.h Mask for max number of samples in log scale
26781
 AR5K_PHY_IQ_CAL_NUM_LOG_MAX_SAR5K_PHY_IQ_CAL_NUM_LOG_MAX_S 12 reg.h 　
26782
 AR5K_PHY_IQ_RUNAR5K_PHY_IQ_RUN 0x00010000 reg.h Run i/q calibration
26783
 AR5K_PHY_IQ_USE_PT_DFAR5K_PHY_IQ_USE_PT_DF 0x00020000 reg.h Use pilot track df (?)
26784
 AR5K_PHY_IQ_EARLY_TRIG_THRAR5K_PHY_IQ_EARLY_TRIG_THR 0x00200000 reg.h Early trigger threshold (?) (field)
26785
 AR5K_PHY_IQ_PILOT_MASK_ENAR5K_PHY_IQ_PILOT_MASK_EN 0x10000000 reg.h Enable pilot mask (?)
26786
 AR5K_PHY_IQ_CHAN_MASK_ENAR5K_PHY_IQ_CHAN_MASK_EN 0x20000000 reg.h Enable channel mask (?)
26787
 AR5K_PHY_IQ_SPUR_FILT_ENAR5K_PHY_IQ_SPUR_FILT_EN 0x40000000 reg.h Enable spur filter
26788
 AR5K_PHY_IQ_SPUR_RSSI_ENAR5K_PHY_IQ_SPUR_RSSI_EN 0x80000000 reg.h Enable spur rssi
26789
 AR5K_PHY_OFDM_SELFCORRAR5K_PHY_OFDM_SELFCORR 0x9924 reg.h Register Address
26790
 AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x00000001 reg.h Enable cyclic RSSI thr 1
26791
 AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x000000fe reg.h Mask for Cyclic RSSI threshold 1
26792
 AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 1 reg.h 　
26793
 AR5K_PHY_OFDM_SELFCORR_CYPWR_THAR5K_PHY_OFDM_SELFCORR_CYPWR_TH 0x00000100 reg.h Cyclic RSSI threshold 3 (field) (?)
26794
 AR5K_PHY_OFDM_SELFCORR_RSSI_1ATAR5K_PHY_OFDM_SELFCORR_RSSI_1AT 0x00008000 reg.h Enable 1A RSSI threshold (?)
26795
 AR5K_PHY_OFDM_SELFCORR_RSSI_1ATAR5K_PHY_OFDM_SELFCORR_RSSI_1AT 0x00010000 reg.h 1A RSSI threshold (field) (?)
26796
 AR5K_PHY_OFDM_SELFCORR_LSCTHR_HAR5K_PHY_OFDM_SELFCORR_LSCTHR_H 0x00800000 reg.h Long sc threshold hi rssi (?)
26797
 AR5K_PHY_WARM_RESETAR5K_PHY_WARM_RESET 0x9928 reg.h 　
26798
 AR5K_PHY_CTLAR5K_PHY_CTL 0x992c reg.h Register Address
26799
 AR5K_PHY_CTL_RX_DRAIN_RATEAR5K_PHY_CTL_RX_DRAIN_RATE 0x00000001 reg.h RX drain rate (?)
26800
 AR5K_PHY_CTL_LATE_TX_SIG_SYMAR5K_PHY_CTL_LATE_TX_SIG_SYM 0x00000002 reg.h Late tx signal symbol (?)
26801
 AR5K_PHY_CTL_GEN_SCRAMBLERAR5K_PHY_CTL_GEN_SCRAMBLER 0x00000004 reg.h Generate scrambler
26802
 AR5K_PHY_CTL_TX_ANT_SELAR5K_PHY_CTL_TX_ANT_SEL 0x00000008 reg.h TX antenna select
26803
 AR5K_PHY_CTL_TX_ANT_STATICAR5K_PHY_CTL_TX_ANT_STATIC 0x00000010 reg.h Static TX antenna
26804
 AR5K_PHY_CTL_RX_ANT_SELAR5K_PHY_CTL_RX_ANT_SEL 0x00000020 reg.h RX antenna select
26805
 AR5K_PHY_CTL_RX_ANT_STATICAR5K_PHY_CTL_RX_ANT_STATIC 0x00000040 reg.h Static RX antenna
26806
 AR5K_PHY_CTL_LOW_FREQ_SLE_ENAR5K_PHY_CTL_LOW_FREQ_SLE_EN 0x00000080 reg.h Enable low freq sleep
26807
 AR5K_PHY_PAPD_PROBEAR5K_PHY_PAPD_PROBE 0x9930 reg.h 　
26808
 AR5K_PHY_PAPD_PROBE_SH_HI_PARAR5K_PHY_PAPD_PROBE_SH_HI_PAR 0x00000001 reg.h 　
26809
 AR5K_PHY_PAPD_PROBE_PCDAC_BIASAR5K_PHY_PAPD_PROBE_PCDAC_BIAS 0x00000002 reg.h 　
26810
 AR5K_PHY_PAPD_PROBE_COMP_GAINAR5K_PHY_PAPD_PROBE_COMP_GAIN 0x00000040 reg.h 　
26811
 AR5K_PHY_PAPD_PROBE_TXPOWERAR5K_PHY_PAPD_PROBE_TXPOWER 0x00007e00 reg.h 　
26812
 AR5K_PHY_PAPD_PROBE_TXPOWER_SAR5K_PHY_PAPD_PROBE_TXPOWER_S 9 reg.h 　
26813
 AR5K_PHY_PAPD_PROBE_TX_NEXTAR5K_PHY_PAPD_PROBE_TX_NEXT 0x00008000 reg.h 　
26814
 AR5K_PHY_PAPD_PROBE_PREDIST_ENAR5K_PHY_PAPD_PROBE_PREDIST_EN 0x00010000 reg.h 　
26815
 AR5K_PHY_PAPD_PROBE_TYPEAR5K_PHY_PAPD_PROBE_TYPE 0x01800000 reg.h [5112+]
26816
 AR5K_PHY_PAPD_PROBE_TYPE_SAR5K_PHY_PAPD_PROBE_TYPE_S 23 reg.h 　
26817
 AR5K_PHY_PAPD_PROBE_TYPE_OFDMAR5K_PHY_PAPD_PROBE_TYPE_OFDM 0 reg.h 　
26818
 AR5K_PHY_PAPD_PROBE_TYPE_XRAR5K_PHY_PAPD_PROBE_TYPE_XR 1 reg.h 　
26819
 AR5K_PHY_PAPD_PROBE_TYPE_CCKAR5K_PHY_PAPD_PROBE_TYPE_CCK 2 reg.h 　
26820
 AR5K_PHY_PAPD_PROBE_GAINFAR5K_PHY_PAPD_PROBE_GAINF 0xfe000000 reg.h 　
26821
 AR5K_PHY_PAPD_PROBE_GAINF_SAR5K_PHY_PAPD_PROBE_GAINF_S 25 reg.h 　
26822
 AR5K_PHY_PAPD_PROBE_INI_5111AR5K_PHY_PAPD_PROBE_INI_5111 0x00004883 reg.h [5212+]
26823
 AR5K_PHY_PAPD_PROBE_INI_5112AR5K_PHY_PAPD_PROBE_INI_5112 0x00004882 reg.h [5212+]
26824
 AR5K_PHY_TXPOWER_RATE1AR5K_PHY_TXPOWER_RATE1 0x9934 reg.h 　
26825
 AR5K_PHY_TXPOWER_RATE2AR5K_PHY_TXPOWER_RATE2 0x9938 reg.h 　
26826
 AR5K_PHY_TXPOWER_RATE_MAXAR5K_PHY_TXPOWER_RATE_MAX 0x993c reg.h 　
26827
 AR5K_PHY_TXPOWER_RATE_MAX_TPC_EAR5K_PHY_TXPOWER_RATE_MAX_TPC_E 0x00000040 reg.h 　
26828
 AR5K_PHY_TXPOWER_RATE3AR5K_PHY_TXPOWER_RATE3 0xa234 reg.h 　
26829
 AR5K_PHY_TXPOWER_RATE4AR5K_PHY_TXPOWER_RATE4 0xa238 reg.h 　
26830
 AR5K_PHY_FRAME_CTL_5210AR5K_PHY_FRAME_CTL_5210 0x9804 reg.h 　
26831
 AR5K_PHY_FRAME_CTL_5211AR5K_PHY_FRAME_CTL_5211 0x9944 reg.h 　
26832
 AR5K_PHY_FRAME_CTLAR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \ AR5K_PHY_FRAME_CTL_5210 : AR5K_PHY_FRAME_CTL_5211) reg.h 　
26833
 AR5K_PHY_FRAME_CTL_TX_CLIPAR5K_PHY_FRAME_CTL_TX_CLIP 0x00000038 reg.h Mask for tx clip (?)
26834
 AR5K_PHY_FRAME_CTL_TX_CLIP_SAR5K_PHY_FRAME_CTL_TX_CLIP_S 3 reg.h 　
26835
 AR5K_PHY_FRAME_CTL_PREP_CHINFOAR5K_PHY_FRAME_CTL_PREP_CHINFO 0x00010000 reg.h Prepend chan info
26836
 AR5K_PHY_FRAME_CTL_EMUAR5K_PHY_FRAME_CTL_EMU 0x80000000 reg.h 　
26837
 AR5K_PHY_FRAME_CTL_EMU_SAR5K_PHY_FRAME_CTL_EMU_S 31 reg.h 　
26838
 AR5K_PHY_FRAME_CTL_TIMING_ERRAR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 reg.h PHY timing error
26839
 AR5K_PHY_FRAME_CTL_PARITY_ERRAR5K_PHY_FRAME_CTL_PARITY_ERR 0x02000000 reg.h Parity error
26840
 AR5K_PHY_FRAME_CTL_ILLRATE_ERRAR5K_PHY_FRAME_CTL_ILLRATE_ERR 0x04000000 reg.h Illegal rate
26841
 AR5K_PHY_FRAME_CTL_ILLLEN_ERRAR5K_PHY_FRAME_CTL_ILLLEN_ERR 0x08000000 reg.h Illegal length
26842
 AR5K_PHY_FRAME_CTL_SERVICE_ERRAR5K_PHY_FRAME_CTL_SERVICE_ERR 0x20000000 reg.h 　
26843
 AR5K_PHY_FRAME_CTL_TXURN_ERRAR5K_PHY_FRAME_CTL_TXURN_ERR 0x40000000 reg.h TX underrun
26844
 AR5K_PHY_FRAME_CTL_INIAR5K_PHY_FRAME_CTL_INI AR5K_PHY_FRAME_CTL_SERVICE_ERR | \ AR5K_PHY_FRAME_CTL_TXURN_ERR | \ AR5K_PHY_FRAME_CTL_ILLLEN_ERR | \ AR5K_PHY_FRAME_CTL_ILLRAT reg.h 　
26845
 AR5K_PHY_TX_PWR_ADJAR5K_PHY_TX_PWR_ADJ 0x994c reg.h 　
26846
 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DEAR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE 0x00000fc0 reg.h 　
26847
 AR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DEAR5K_PHY_TX_PWR_ADJ_CCK_GAIN_DE 6 reg.h 　
26848
 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_IAR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I 0x00fc0000 reg.h 　
26849
 AR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_IAR5K_PHY_TX_PWR_ADJ_CCK_PCDAC_I 18 reg.h 　
26850
 AR5K_PHY_RADARAR5K_PHY_RADAR 0x9954 reg.h 　
26851
 AR5K_PHY_RADAR_ENABLEAR5K_PHY_RADAR_ENABLE 0x00000001 reg.h 　
26852
 AR5K_PHY_RADAR_DISABLEAR5K_PHY_RADAR_DISABLE 0x00000000 reg.h 　
26853
 AR5K_PHY_RADAR_INBANDTHRAR5K_PHY_RADAR_INBANDTHR 0x0000003e reg.h Inband threshold
26854
 AR5K_PHY_RADAR_INBANDTHR_SAR5K_PHY_RADAR_INBANDTHR_S 1 reg.h 　
26855
 AR5K_PHY_RADAR_PRSSI_THRAR5K_PHY_RADAR_PRSSI_THR 0x00000fc0 reg.h Pulse RSSI/SNR threshold
26856
 AR5K_PHY_RADAR_PRSSI_THR_SAR5K_PHY_RADAR_PRSSI_THR_S 6 reg.h 　
26857
 AR5K_PHY_RADAR_PHEIGHT_THRAR5K_PHY_RADAR_PHEIGHT_THR 0x0003f000 reg.h Pulse height threshold
26858
 AR5K_PHY_RADAR_PHEIGHT_THR_SAR5K_PHY_RADAR_PHEIGHT_THR_S 12 reg.h 　
26859
 AR5K_PHY_RADAR_RSSI_THRAR5K_PHY_RADAR_RSSI_THR 0x00fc0000 reg.h Radar RSSI/SNR threshold.
26860
 AR5K_PHY_RADAR_RSSI_THR_SAR5K_PHY_RADAR_RSSI_THR_S 18 reg.h 　
26861
 AR5K_PHY_RADAR_FIRPWR_THRAR5K_PHY_RADAR_FIRPWR_THR 0x7f000000 reg.h Finite Impulse Response
26862
 AR5K_PHY_RADAR_FIRPWR_THRSAR5K_PHY_RADAR_FIRPWR_THRS 24 reg.h 　
26863
 AR5K_PHY_ANT_SWITCH_TABLE_0AR5K_PHY_ANT_SWITCH_TABLE_0 0x9960 reg.h 　
26864
 AR5K_PHY_ANT_SWITCH_TABLE_1AR5K_PHY_ANT_SWITCH_TABLE_1 0x9964 reg.h 　
26865
 AR5K_PHY_NFTHRESAR5K_PHY_NFTHRES 0x9968 reg.h 　
26866
 AR5K_PHY_SIGMA_DELTAAR5K_PHY_SIGMA_DELTA 0x996C reg.h 　
26867
 AR5K_PHY_SIGMA_DELTA_ADC_SELAR5K_PHY_SIGMA_DELTA_ADC_SEL 0x00000003 reg.h 　
26868
 AR5K_PHY_SIGMA_DELTA_ADC_SEL_SAR5K_PHY_SIGMA_DELTA_ADC_SEL_S 0 reg.h 　
26869
 AR5K_PHY_SIGMA_DELTA_FILT2AR5K_PHY_SIGMA_DELTA_FILT2 0x000000f8 reg.h 　
26870
 AR5K_PHY_SIGMA_DELTA_FILT2_SAR5K_PHY_SIGMA_DELTA_FILT2_S 3 reg.h 　
26871
 AR5K_PHY_SIGMA_DELTA_FILT1AR5K_PHY_SIGMA_DELTA_FILT1 0x00001f00 reg.h 　
26872
 AR5K_PHY_SIGMA_DELTA_FILT1_SAR5K_PHY_SIGMA_DELTA_FILT1_S 8 reg.h 　
26873
 AR5K_PHY_SIGMA_DELTA_ADC_CLIPAR5K_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000 reg.h 　
26874
 AR5K_PHY_SIGMA_DELTA_ADC_CLIP_SAR5K_PHY_SIGMA_DELTA_ADC_CLIP_S 13 reg.h 　
26875
 AR5K_PHY_RESTARTAR5K_PHY_RESTART 0x9970 reg.h restart
26876
 AR5K_PHY_RESTART_DIV_GCAR5K_PHY_RESTART_DIV_GC 0x001c0000 reg.h Fast diversity gc_limit (?)
26877
 AR5K_PHY_RESTART_DIV_GC_SAR5K_PHY_RESTART_DIV_GC_S 18 reg.h 　
26878
 AR5K_PHY_RFBUS_REQAR5K_PHY_RFBUS_REQ 0x997C reg.h 　
26879
 AR5K_PHY_RFBUS_REQ_REQUESTAR5K_PHY_RFBUS_REQ_REQUEST 0x00000001 reg.h 　
26880
 AR5K_PHY_TIMING_7AR5K_PHY_TIMING_7 0x9980 reg.h 　
26881
 AR5K_PHY_TIMING_8AR5K_PHY_TIMING_8 0x9984 reg.h 　
26882
 AR5K_PHY_TIMING_8_PILOT_MASK_2AR5K_PHY_TIMING_8_PILOT_MASK_2 0x000fffff reg.h 　
26883
 AR5K_PHY_TIMING_8_PILOT_MASK_2_AR5K_PHY_TIMING_8_PILOT_MASK_2_ 0 reg.h 　
26884
 AR5K_PHY_BIN_MASK2_1AR5K_PHY_BIN_MASK2_1 0x9988 reg.h 　
26885
 AR5K_PHY_BIN_MASK2_2AR5K_PHY_BIN_MASK2_2 0x998c reg.h 　
26886
 AR5K_PHY_BIN_MASK2_3AR5K_PHY_BIN_MASK2_3 0x9990 reg.h 　
26887
 AR5K_PHY_BIN_MASK2_4AR5K_PHY_BIN_MASK2_4 0x9994 reg.h 　
26888
 AR5K_PHY_BIN_MASK2_4_MASK_4AR5K_PHY_BIN_MASK2_4_MASK_4 0x00003fff reg.h 　
26889
 AR5K_PHY_BIN_MASK2_4_MASK_4_SAR5K_PHY_BIN_MASK2_4_MASK_4_S 0 reg.h 　
26890
 AR5K_PHY_TIMING_9AR5K_PHY_TIMING_9 0x9998 reg.h 　
26891
 AR5K_PHY_TIMING_10AR5K_PHY_TIMING_10 0x999c reg.h 　
26892
 AR5K_PHY_TIMING_10_PILOT_MASK_2AR5K_PHY_TIMING_10_PILOT_MASK_2 0x000fffff reg.h 　
26893
 AR5K_PHY_TIMING_10_PILOT_MASK_2AR5K_PHY_TIMING_10_PILOT_MASK_2 0 reg.h 　
26894
 AR5K_PHY_TIMING_11AR5K_PHY_TIMING_11 0x99a0 reg.h Register address
26895
 AR5K_PHY_TIMING_11_SPUR_DELTA_PAR5K_PHY_TIMING_11_SPUR_DELTA_P 0x000fffff reg.h Spur delta phase
26896
 AR5K_PHY_TIMING_11_SPUR_DELTA_PAR5K_PHY_TIMING_11_SPUR_DELTA_P 0 reg.h 　
26897
 AR5K_PHY_TIMING_11_SPUR_FREQ_SDAR5K_PHY_TIMING_11_SPUR_FREQ_SD 0x3ff00000 reg.h Freq sigma delta
26898
 AR5K_PHY_TIMING_11_SPUR_FREQ_SDAR5K_PHY_TIMING_11_SPUR_FREQ_SD 20 reg.h 　
26899
 AR5K_PHY_TIMING_11_USE_SPUR_IN_AR5K_PHY_TIMING_11_USE_SPUR_IN_ 0x40000000 reg.h Spur filter in AGC detector
26900
 AR5K_PHY_TIMING_11_USE_SPUR_IN_AR5K_PHY_TIMING_11_USE_SPUR_IN_ 0x80000000 reg.h Spur filter in OFDM self correlator
26901
 AR5K_BB_GAIN_BASEAR5K_BB_GAIN_BASE 0x9b00 reg.h BaseBand Amplifier Gain table base address
26902
 AR5K_RF_GAIN_BASEAR5K_RF_GAIN_BASE 0x9a00 reg.h RF Amplrifier Gain table base address
26903
 AR5K_PHY_IQRES_CAL_PWR_IAR5K_PHY_IQRES_CAL_PWR_I 0x9c10 reg.h I (Inphase) power value
26904
 AR5K_PHY_IQRES_CAL_PWR_QAR5K_PHY_IQRES_CAL_PWR_Q 0x9c14 reg.h Q (Quadrature) power value
26905
 AR5K_PHY_IQRES_CAL_CORRAR5K_PHY_IQRES_CAL_CORR 0x9c18 reg.h I/Q Correlation
26906
 AR5K_PHY_CURRENT_RSSIAR5K_PHY_CURRENT_RSSI 0x9c1c reg.h 　
26907
 AR5K_PHY_RFBUS_GRANTAR5K_PHY_RFBUS_GRANT 0x9c20 reg.h 　
26908
 AR5K_PHY_RFBUS_GRANT_OKAR5K_PHY_RFBUS_GRANT_OK 0x00000001 reg.h 　
26909
 AR5K_PHY_ADC_TESTAR5K_PHY_ADC_TEST 0x9c24 reg.h 　
26910
 AR5K_PHY_ADC_TEST_IAR5K_PHY_ADC_TEST_I 0x00000001 reg.h 　
26911
 AR5K_PHY_ADC_TEST_QAR5K_PHY_ADC_TEST_Q 0x00000200 reg.h 　
26912
 AR5K_PHY_DAC_TESTAR5K_PHY_DAC_TEST 0x9c28 reg.h 　
26913
 AR5K_PHY_DAC_TEST_IAR5K_PHY_DAC_TEST_I 0x00000001 reg.h 　
26914
 AR5K_PHY_DAC_TEST_QAR5K_PHY_DAC_TEST_Q 0x00000200 reg.h 　
26915
 AR5K_PHY_PTATAR5K_PHY_PTAT 0x9c2c reg.h 　
26916
 AR5K_PHY_BAD_TX_RATEAR5K_PHY_BAD_TX_RATE 0x9c30 reg.h 　
26917
 AR5K_PHY_SPUR_PWRAR5K_PHY_SPUR_PWR 0x9c34 reg.h Register Address
26918
 AR5K_PHY_SPUR_PWR_IAR5K_PHY_SPUR_PWR_I 0x00000001 reg.h SPUR Power estimate for I (field)
26919
 AR5K_PHY_SPUR_PWR_QAR5K_PHY_SPUR_PWR_Q 0x00000100 reg.h SPUR Power estimate for Q (field)
26920
 AR5K_PHY_SPUR_PWR_FILTAR5K_PHY_SPUR_PWR_FILT 0x00010000 reg.h Power with SPUR removed (field)
26921
 AR5K_PHY_CHAN_STATUSAR5K_PHY_CHAN_STATUS 0x9c38 reg.h 　
26922
 AR5K_PHY_CHAN_STATUS_BT_ACTAR5K_PHY_CHAN_STATUS_BT_ACT 0x00000001 reg.h 　
26923
 AR5K_PHY_CHAN_STATUS_RX_CLR_RAWAR5K_PHY_CHAN_STATUS_RX_CLR_RAW 0x00000002 reg.h 　
26924
 AR5K_PHY_CHAN_STATUS_RX_CLR_MACAR5K_PHY_CHAN_STATUS_RX_CLR_MAC 0x00000004 reg.h 　
26925
 AR5K_PHY_CHAN_STATUS_RX_CLR_PAPAR5K_PHY_CHAN_STATUS_RX_CLR_PAP 0x00000008 reg.h 　
26926
 AR5K_PHY_HEAVY_CLIP_ENABLEAR5K_PHY_HEAVY_CLIP_ENABLE 0x99e0 reg.h 　
26927
 AR5K_PHY_SCLOCKAR5K_PHY_SCLOCK 0x99f0 reg.h 　
26928
 AR5K_PHY_SCLOCK_32MHZAR5K_PHY_SCLOCK_32MHZ 0x0000000c reg.h 　
26929
 AR5K_PHY_SDELAYAR5K_PHY_SDELAY 0x99f4 reg.h 　
26930
 AR5K_PHY_SDELAY_32MHZAR5K_PHY_SDELAY_32MHZ 0x000000ff reg.h 　
26931
 AR5K_PHY_SPENDINGAR5K_PHY_SPENDING 0x99f8 reg.h 　
26932
 AR5K_PHY_PAPD_I_BASEAR5K_PHY_PAPD_I_BASE 0xa000 reg.h 　
26933
 AR5K_PHY_PCDAC_TXPOWER_BASEAR5K_PHY_PCDAC_TXPOWER_BASE 0xa180 reg.h 　
26934
 AR5K_PHY_MODEAR5K_PHY_MODE 0x0a200 reg.h Register Address
26935
 AR5K_PHY_MODE_MODAR5K_PHY_MODE_MOD 0x00000001 reg.h PHY Modulation bit
26936
 AR5K_PHY_MODE_MOD_OFDMAR5K_PHY_MODE_MOD_OFDM 0 reg.h 　
26937
 AR5K_PHY_MODE_MOD_CCKAR5K_PHY_MODE_MOD_CCK 1 reg.h 　
26938
 AR5K_PHY_MODE_FREQAR5K_PHY_MODE_FREQ 0x00000002 reg.h Freq mode bit
26939
 AR5K_PHY_MODE_FREQ_5GHZAR5K_PHY_MODE_FREQ_5GHZ 0 reg.h 　
26940
 AR5K_PHY_MODE_FREQ_2GHZAR5K_PHY_MODE_FREQ_2GHZ 2 reg.h 　
26941
 AR5K_PHY_MODE_MOD_DYNAR5K_PHY_MODE_MOD_DYN 0x00000004 reg.h Enable Dynamic OFDM/CCK mode [5112+]
26942
 AR5K_PHY_MODE_RADAR5K_PHY_MODE_RAD 0x00000008 reg.h [5212+]
26943
 AR5K_PHY_MODE_RAD_RF5111AR5K_PHY_MODE_RAD_RF5111 0 reg.h 　
26944
 AR5K_PHY_MODE_RAD_RF5112AR5K_PHY_MODE_RAD_RF5112 8 reg.h 　
26945
 AR5K_PHY_MODE_XRAR5K_PHY_MODE_XR 0x00000010 reg.h Enable XR mode [5112+]
26946
 AR5K_PHY_MODE_HALF_RATEAR5K_PHY_MODE_HALF_RATE 0x00000020 reg.h Enable Half rate (test)
26947
 AR5K_PHY_MODE_QUARTER_RATEAR5K_PHY_MODE_QUARTER_RATE 0x00000040 reg.h Enable Quarter rat (test)
26948
 AR5K_PHY_CCKTXCTLAR5K_PHY_CCKTXCTL 0xa204 reg.h 　
26949
 AR5K_PHY_CCKTXCTL_WORLDAR5K_PHY_CCKTXCTL_WORLD 0x00000000 reg.h 　
26950
 AR5K_PHY_CCKTXCTL_JAPANAR5K_PHY_CCKTXCTL_JAPAN 0x00000010 reg.h 　
26951
 AR5K_PHY_CCKTXCTL_SCRAMBLER_DISAR5K_PHY_CCKTXCTL_SCRAMBLER_DIS 0x00000001 reg.h 　
26952
 AR5K_PHY_CCKTXCTK_DAC_SCALEAR5K_PHY_CCKTXCTK_DAC_SCALE 0x00000004 reg.h 　
26953
 AR5K_PHY_CCK_CROSSCORRAR5K_PHY_CCK_CROSSCORR 0xa208 reg.h 　
26954
 AR5K_PHY_CCK_CROSSCORR_WEAK_SIGAR5K_PHY_CCK_CROSSCORR_WEAK_SIG 0x0000000f reg.h 　
26955
 AR5K_PHY_CCK_CROSSCORR_WEAK_SIGAR5K_PHY_CCK_CROSSCORR_WEAK_SIG 0 reg.h 　
26956
 AR5K_PHY_FAST_ANT_DIVAR5K_PHY_FAST_ANT_DIV 0xa208 reg.h 　
26957
 AR5K_PHY_FAST_ANT_DIV_ENAR5K_PHY_FAST_ANT_DIV_EN 0x00002000 reg.h 　
26958
 AR5K_PHY_GAIN_2GHZAR5K_PHY_GAIN_2GHZ 0xa20c reg.h 　
26959
 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRXAR5K_PHY_GAIN_2GHZ_MARGIN_TXRX 0x00fc0000 reg.h 　
26960
 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX_ 18 reg.h 　
26961
 AR5K_PHY_GAIN_2GHZ_INI_5111AR5K_PHY_GAIN_2GHZ_INI_5111 0x6480416c reg.h 　
26962
 AR5K_PHY_CCK_RX_CTL_4AR5K_PHY_CCK_RX_CTL_4 0xa21c reg.h 　
26963
 AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ 0x01f80000 reg.h 　
26964
 AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_AR5K_PHY_CCK_RX_CTL_4_FREQ_EST_ 19 reg.h 　
26965
 AR5K_PHY_DAG_CCK_CTLAR5K_PHY_DAG_CCK_CTL 0xa228 reg.h 　
26966
 AR5K_PHY_DAG_CCK_CTL_EN_RSSI_THAR5K_PHY_DAG_CCK_CTL_EN_RSSI_TH 0x00000200 reg.h 　
26967
 AR5K_PHY_DAG_CCK_CTL_RSSI_THRAR5K_PHY_DAG_CCK_CTL_RSSI_THR 0x0001fc00 reg.h 　
26968
 AR5K_PHY_DAG_CCK_CTL_RSSI_THR_SAR5K_PHY_DAG_CCK_CTL_RSSI_THR_S 10 reg.h 　
26969
 AR5K_PHY_FAST_ADCAR5K_PHY_FAST_ADC 0xa24c reg.h 　
26970
 AR5K_PHY_BLUETOOTHAR5K_PHY_BLUETOOTH 0xa254 reg.h 　
26971
 AR5K_PHY_TPC_RG1AR5K_PHY_TPC_RG1 0xa258 reg.h 　
26972
 AR5K_PHY_TPC_RG1_NUM_PD_GAINAR5K_PHY_TPC_RG1_NUM_PD_GAIN 0x0000c000 reg.h 　
26973
 AR5K_PHY_TPC_RG1_NUM_PD_GAIN_SAR5K_PHY_TPC_RG1_NUM_PD_GAIN_S 14 reg.h 　
26974
 AR5K_PHY_TPC_RG1_PDGAIN_1AR5K_PHY_TPC_RG1_PDGAIN_1 0x00030000 reg.h 　
26975
 AR5K_PHY_TPC_RG1_PDGAIN_1_SAR5K_PHY_TPC_RG1_PDGAIN_1_S 16 reg.h 　
26976
 AR5K_PHY_TPC_RG1_PDGAIN_2AR5K_PHY_TPC_RG1_PDGAIN_2 0x000c0000 reg.h 　
26977
 AR5K_PHY_TPC_RG1_PDGAIN_2_SAR5K_PHY_TPC_RG1_PDGAIN_2_S 18 reg.h 　
26978
 AR5K_PHY_TPC_RG1_PDGAIN_3AR5K_PHY_TPC_RG1_PDGAIN_3 0x00300000 reg.h 　
26979
 AR5K_PHY_TPC_RG1_PDGAIN_3_SAR5K_PHY_TPC_RG1_PDGAIN_3_S 20 reg.h 　
26980
 AR5K_PHY_TPC_RG5AR5K_PHY_TPC_RG5 0xa26C reg.h 　
26981
 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAAR5K_PHY_TPC_RG5_PD_GAIN_OVERLA 0x0000000F reg.h 　
26982
 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAAR5K_PHY_TPC_RG5_PD_GAIN_OVERLA 0 reg.h 　
26983
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x000003F0 reg.h 　
26984
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 4 reg.h 　
26985
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x0000FC00 reg.h 　
26986
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 10 reg.h 　
26987
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x003F0000 reg.h 　
26988
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 16 reg.h 　
26989
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 0x0FC00000 reg.h 　
26990
 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDAAR5K_PHY_TPC_RG5_PD_GAIN_BOUNDA 22 reg.h 　
26991
 AR5K_PHY_PDADC_TXPOWER_BASEAR5K_PHY_PDADC_TXPOWER_BASE 0xa280 reg.h 　
26992
 AR5K_RF5111_OB_2GHZAR5K_RF5111_OB_2GHZ { 3, 119, 0 } rfbuffer.h 　
26993
 AR5K_RF5111_DB_2GHZAR5K_RF5111_DB_2GHZ { 3, 122, 0 } rfbuffer.h 　
26994
 AR5K_RF5111_OB_5GHZAR5K_RF5111_OB_5GHZ { 3, 104, 0 } rfbuffer.h 　
26995
 AR5K_RF5111_DB_5GHZAR5K_RF5111_DB_5GHZ { 3, 107, 0 } rfbuffer.h 　
26996
 AR5K_RF5111_PWD_XPDAR5K_RF5111_PWD_XPD { 1, 95, 0 } rfbuffer.h 　
26997
 AR5K_RF5111_XPD_GAINAR5K_RF5111_XPD_GAIN { 4, 96, 0 } rfbuffer.h 　
26998
 AR5K_RF5111_GAIN_IAR5K_RF5111_GAIN_I { 6, 29, 0 } rfbuffer.h 　
26999
 AR5K_RF5111_PLO_SELAR5K_RF5111_PLO_SEL { 1, 4, 0 } rfbuffer.h 　
27000
 AR5K_RF5111_RFGAIN_SELAR5K_RF5111_RFGAIN_SEL { 1, 36, 0 } rfbuffer.h 　
27001
 AR5K_RF5111_RFGAIN_STEPAR5K_RF5111_RFGAIN_STEP { 6, 37, 0 } rfbuffer.h 　
27002
 AR5K_RF5111_WAIT_SAR5K_RF5111_WAIT_S { 5, 19, 0 } rfbuffer.h 　
27003
 AR5K_RF5111_WAIT_IAR5K_RF5111_WAIT_I { 5, 24, 0 } rfbuffer.h 　
27004
 AR5K_RF5111_MAX_TIMEAR5K_RF5111_MAX_TIME { 2, 49, 0 } rfbuffer.h 　
27005
 AR5K_RF5112X_GAIN_IAR5K_RF5112X_GAIN_I { 6, 14, 0 } rfbuffer.h 　
27006
 AR5K_RF5112X_MIXVGA_OVRAR5K_RF5112X_MIXVGA_OVR { 1, 36, 0 } rfbuffer.h 　
27007
 AR5K_RF5112X_MIXGAIN_OVRAR5K_RF5112X_MIXGAIN_OVR { 2, 37, 0 } rfbuffer.h 　
27008
 AR5K_RF5112X_MIXGAIN_STEPAR5K_RF5112X_MIXGAIN_STEP { 4, 32, 0 } rfbuffer.h 　
27009
 AR5K_RF5112X_PD_DELAY_AAR5K_RF5112X_PD_DELAY_A { 4, 58, 0 } rfbuffer.h 　
27010
 AR5K_RF5112X_PD_DELAY_BAR5K_RF5112X_PD_DELAY_B { 4, 62, 0 } rfbuffer.h 　
27011
 AR5K_RF5112X_PD_DELAY_XRAR5K_RF5112X_PD_DELAY_XR { 4, 66, 0 } rfbuffer.h 　
27012
 AR5K_RF5112X_PD_PERIOD_AAR5K_RF5112X_PD_PERIOD_A { 4, 70, 0 } rfbuffer.h 　
27013
 AR5K_RF5112X_PD_PERIOD_BAR5K_RF5112X_PD_PERIOD_B { 4, 74, 0 } rfbuffer.h 　
27014
 AR5K_RF5112X_PD_PERIOD_XRAR5K_RF5112X_PD_PERIOD_XR { 4, 78, 0 } rfbuffer.h 　
27015
 AR5K_RF5112_OB_2GHZAR5K_RF5112_OB_2GHZ { 3, 269, 0 } rfbuffer.h 　
27016
 AR5K_RF5112_DB_2GHZAR5K_RF5112_DB_2GHZ { 3, 272, 0 } rfbuffer.h 　
27017
 AR5K_RF5112_OB_5GHZAR5K_RF5112_OB_5GHZ { 3, 261, 0 } rfbuffer.h 　
27018
 AR5K_RF5112_DB_5GHZAR5K_RF5112_DB_5GHZ { 3, 264, 0 } rfbuffer.h 　
27019
 AR5K_RF5112_FIXED_BIAS_AAR5K_RF5112_FIXED_BIAS_A { 1, 260, 0 } rfbuffer.h 　
27020
 AR5K_RF5112_FIXED_BIAS_BAR5K_RF5112_FIXED_BIAS_B { 1, 259, 0 } rfbuffer.h 　
27021
 AR5K_RF5112_XPD_SELAR5K_RF5112_XPD_SEL { 1, 284, 0 } rfbuffer.h 　
27022
 AR5K_RF5112_XPD_GAINAR5K_RF5112_XPD_GAIN { 2, 252, 0 } rfbuffer.h 　
27023
 AR5K_RF5112A_OB_2GHZAR5K_RF5112A_OB_2GHZ { 3, 287, 0 } rfbuffer.h 　
27024
 AR5K_RF5112A_DB_2GHZAR5K_RF5112A_DB_2GHZ { 3, 290, 0 } rfbuffer.h 　
27025
 AR5K_RF5112A_OB_5GHZAR5K_RF5112A_OB_5GHZ { 3, 279, 0 } rfbuffer.h 　
27026
 AR5K_RF5112A_DB_5GHZAR5K_RF5112A_DB_5GHZ { 3, 282, 0 } rfbuffer.h 　
27027
 AR5K_RF5112A_FIXED_BIAS_AAR5K_RF5112A_FIXED_BIAS_A { 1, 278, 0 } rfbuffer.h 　
27028
 AR5K_RF5112A_FIXED_BIAS_BAR5K_RF5112A_FIXED_BIAS_B { 1, 277, 0 } rfbuffer.h 　
27029
 AR5K_RF5112A_XPD_SELAR5K_RF5112A_XPD_SEL { 1, 302, 0 } rfbuffer.h 　
27030
 AR5K_RF5112A_PDGAINLOAR5K_RF5112A_PDGAINLO { 2, 270, 0 } rfbuffer.h 　
27031
 AR5K_RF5112A_PDGAINHIAR5K_RF5112A_PDGAINHI { 2, 257, 0 } rfbuffer.h 　
27032
 AR5K_RF5112A_HIGH_VC_CPAR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 } rfbuffer.h 　
27033
 AR5K_RF5112A_MID_VC_CPAR5K_RF5112A_MID_VC_CP { 2, 92, 2 } rfbuffer.h 　
27034
 AR5K_RF5112A_LOW_VC_CPAR5K_RF5112A_LOW_VC_CP { 2, 94, 2 } rfbuffer.h 　
27035
 AR5K_RF5112A_PUSH_UPAR5K_RF5112A_PUSH_UP { 1, 254, 2 } rfbuffer.h 　
27036
 AR5K_RF5112A_PAD2GNDAR5K_RF5112A_PAD2GND { 1, 281, 1 } rfbuffer.h 　
27037
 AR5K_RF5112A_XB2_LVLAR5K_RF5112A_XB2_LVL { 2, 1, 3 } rfbuffer.h 　
27038
 AR5K_RF5112A_XB5_LVLAR5K_RF5112A_XB5_LVL { 2, 3, 3 } rfbuffer.h 　
27039
 AR5K_RF2413_OB_2GHZAR5K_RF2413_OB_2GHZ { 3, 168, 0 } rfbuffer.h 　
27040
 AR5K_RF2413_DB_2GHZAR5K_RF2413_DB_2GHZ { 3, 165, 0 } rfbuffer.h 　
27041
 AR5K_RF2316_OB_2GHZAR5K_RF2316_OB_2GHZ { 3, 178, 0 } rfbuffer.h 　
27042
 AR5K_RF2316_DB_2GHZAR5K_RF2316_DB_2GHZ { 3, 175, 0 } rfbuffer.h 　
27043
 AR5K_RF5413_OB_2GHZAR5K_RF5413_OB_2GHZ { 3, 241, 0 } rfbuffer.h 　
27044
 AR5K_RF5413_DB_2GHZAR5K_RF5413_DB_2GHZ { 3, 238, 0 } rfbuffer.h 　
27045
 AR5K_RF5413_OB_5GHZAR5K_RF5413_OB_5GHZ { 3, 247, 0 } rfbuffer.h 　
27046
 AR5K_RF5413_DB_5GHZAR5K_RF5413_DB_5GHZ { 3, 244, 0 } rfbuffer.h 　
27047
 AR5K_RF5413_PWD_ICLOBUF2GAR5K_RF5413_PWD_ICLOBUF2G { 3, 131, 3 } rfbuffer.h 　
27048
 AR5K_RF5413_DERBY_CHAN_SEL_MODEAR5K_RF5413_DERBY_CHAN_SEL_MODE { 1, 291, 2 } rfbuffer.h 　
27049
 AR5K_RF2425_OB_2GHZAR5K_RF2425_OB_2GHZ { 3, 193, 0 } rfbuffer.h 　
27050
 AR5K_RF2425_DB_2GHZAR5K_RF2425_DB_2GHZ { 3, 190, 0 } rfbuffer.h 　
27051
 AR5K_GAIN_CRN_FIX_BITS_5111AR5K_GAIN_CRN_FIX_BITS_5111 4 rfgain.h 　
27052
 AR5K_GAIN_CRN_FIX_BITS_5112AR5K_GAIN_CRN_FIX_BITS_5112 7 rfgain.h 　
27053
 AR5K_GAIN_CRN_MAX_FIX_BITSAR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112 rfgain.h 　
27054
 AR5K_GAIN_DYN_ADJUST_HI_MARGINAR5K_GAIN_DYN_ADJUST_HI_MARGIN 15 rfgain.h 　
27055
 AR5K_GAIN_DYN_ADJUST_LO_MARGINAR5K_GAIN_DYN_ADJUST_LO_MARGIN 20 rfgain.h 　
27056
 AR5K_GAIN_CCK_PROBE_CORRAR5K_GAIN_CCK_PROBE_CORR 5 rfgain.h 　
27057
 AR5K_GAIN_CCK_OFDM_GAIN_DELTAAR5K_GAIN_CCK_OFDM_GAIN_DELTA 15 rfgain.h 　
27058
 AR5K_GAIN_STEP_COUNTAR5K_GAIN_STEP_COUNT 10 rfgain.h 　
27059
 IGP01E1000_AGC_LENGTH_TABLE_SIZIGP01E1000_AGC_LENGTH_TABLE_SIZ (sizeof(e1000_igp_cable_length_table) / \ sizeof(e1000_igp_cable_length_table[0])) e1000_82541.c 　
27060
 M88E1000_CABLE_LENGTH_TABLE_SIZM88E1000_CABLE_LENGTH_TABLE_SIZ (sizeof(e1000_m88_cable_length_table) / \ sizeof(e1000_m88_cable_length_table[0])) e1000_phy.c 　
27061
 IGP02E1000_CABLE_LENGTH_TABLE_SIGP02E1000_CABLE_LENGTH_TABLE_S (sizeof(e1000_igp_2_cable_length_table) / \ sizeof(e1000_igp_2_cable_length_table[0])) e1000_phy.c 　
27062
 BAR_0BAR_0 0 e1000.h 　
27063
 BAR_1BAR_1 1 e1000.h 　
27064
 BAR_5BAR_5 5 e1000.h 　
27065
 E1000_DEFAULT_TXDE1000_DEFAULT_TXD 256 e1000.h 　
27066
 E1000_MAX_TXDE1000_MAX_TXD 256 e1000.h 　
27067
 E1000_MIN_TXDE1000_MIN_TXD 80 e1000.h 　
27068
 E1000_MAX_82544_TXDE1000_MAX_82544_TXD 4096 e1000.h 　
27069
 E1000_DEFAULT_TXD_PWRE1000_DEFAULT_TXD_PWR 12 e1000.h 　
27070
 E1000_MAX_TXD_PWRE1000_MAX_TXD_PWR 12 e1000.h 　
27071
 E1000_MIN_TXD_PWRE1000_MIN_TXD_PWR 7 e1000.h 　
27072
 E1000_DEFAULT_RXDE1000_DEFAULT_RXD 256 e1000.h 　
27073
 E1000_MAX_RXDE1000_MAX_RXD 256 e1000.h 　
27074
 E1000_MIN_RXDE1000_MIN_RXD 80 e1000.h 　
27075
 E1000_MAX_82544_RXDE1000_MAX_82544_RXD 4096 e1000.h 　
27076
 E1000_MIN_ITR_USECSE1000_MIN_ITR_USECS 10 e1000.h 100000 irq/sec
27077
 E1000_MAX_ITR_USECSE1000_MAX_ITR_USECS 10000 e1000.h 100 irq/sec
27078
 MAXIMUM_ETHERNET_VLAN_SIZEMAXIMUM_ETHERNET_VLAN_SIZE 1522 e1000.h 　
27079
 E1000_RXBUFFER_128E1000_RXBUFFER_128 128 e1000.h 　
27080
 E1000_RXBUFFER_256E1000_RXBUFFER_256 256 e1000.h 　
27081
 E1000_RXBUFFER_512E1000_RXBUFFER_512 512 e1000.h 　
27082
 E1000_RXBUFFER_1024E1000_RXBUFFER_1024 1024 e1000.h 　
27083
 E1000_RXBUFFER_2048E1000_RXBUFFER_2048 2048 e1000.h 　
27084
 E1000_RXBUFFER_4096E1000_RXBUFFER_4096 4096 e1000.h 　
27085
 E1000_RXBUFFER_8192E1000_RXBUFFER_8192 8192 e1000.h 　
27086
 E1000_RXBUFFER_16384E1000_RXBUFFER_16384 16384 e1000.h 　
27087
 E1000_SMARTSPEED_DOWNSHIFTE1000_SMARTSPEED_DOWNSHIFT 3 e1000.h 　
27088
 E1000_SMARTSPEED_MAXE1000_SMARTSPEED_MAX 15 e1000.h 　
27089
 E1000_PBA_BYTES_SHIFTE1000_PBA_BYTES_SHIFT 0xA e1000.h 　
27090
 E1000_TX_HEAD_ADDR_SHIFTE1000_TX_HEAD_ADDR_SHIFT 7 e1000.h 　
27091
 E1000_PBA_TX_MASKE1000_PBA_TX_MASK 0xFFFF0000 e1000.h 　
27092
 E1000_ERT_2048E1000_ERT_2048 0x100 e1000.h 　
27093
 E1000_FC_PAUSE_TIMEE1000_FC_PAUSE_TIME 0x0680 e1000.h 858 usec
27094
 E1000_TX_QUEUE_WAKEE1000_TX_QUEUE_WAKE 16 e1000.h 　
27095
 E1000_RX_BUFFER_WRITEE1000_RX_BUFFER_WRITE 16 e1000.h Must be power of 2
27096
 AUTO_ALL_MODESAUTO_ALL_MODES 0 e1000.h 　
27097
 E1000_EEPROM_82544_APME1000_EEPROM_82544_APM 0x0004 e1000.h 　
27098
 E1000_EEPROM_APMEE1000_EEPROM_APME 0x0400 e1000.h 　
27099
 E1000_FLAG_HAS_SMBUSE1000_FLAG_HAS_SMBUS (1 << 0) e1000.h 　
27100
 E1000_FLAG_HAS_INTR_MODERATIONE1000_FLAG_HAS_INTR_MODERATION (1 << 4) e1000.h 　
27101
 E1000_FLAG_BAD_TX_CARRIER_STATSE1000_FLAG_BAD_TX_CARRIER_STATS (1 << 6) e1000.h 　
27102
 E1000_FLAG_QUAD_PORT_AE1000_FLAG_QUAD_PORT_A (1 << 8) e1000.h 　
27103
 E1000_FLAG_SMART_POWER_DOWNE1000_FLAG_SMART_POWER_DOWN (1 << 9) e1000.h 　
27104
 NVM_WORD_SIZE_BASE_SHIFT_82541NVM_WORD_SIZE_BASE_SHIFT_82541 (NVM_WORD_SIZE_BASE_SHIFT + 1) e1000_82541.h 　
27105
 IGP01E1000_PHY_CHANNEL_NUMIGP01E1000_PHY_CHANNEL_NUM 4 e1000_82541.h 　
27106
 IGP01E1000_PHY_AGC_AIGP01E1000_PHY_AGC_A 0x1172 e1000_82541.h 　
27107
 IGP01E1000_PHY_AGC_BIGP01E1000_PHY_AGC_B 0x1272 e1000_82541.h 　
27108
 IGP01E1000_PHY_AGC_CIGP01E1000_PHY_AGC_C 0x1472 e1000_82541.h 　
27109
 IGP01E1000_PHY_AGC_DIGP01E1000_PHY_AGC_D 0x1872 e1000_82541.h 　
27110
 IGP01E1000_PHY_AGC_PARAM_AIGP01E1000_PHY_AGC_PARAM_A 0x1171 e1000_82541.h 　
27111
 IGP01E1000_PHY_AGC_PARAM_BIGP01E1000_PHY_AGC_PARAM_B 0x1271 e1000_82541.h 　
27112
 IGP01E1000_PHY_AGC_PARAM_CIGP01E1000_PHY_AGC_PARAM_C 0x1471 e1000_82541.h 　
27113
 IGP01E1000_PHY_AGC_PARAM_DIGP01E1000_PHY_AGC_PARAM_D 0x1871 e1000_82541.h 　
27114
 IGP01E1000_PHY_EDAC_MU_INDEXIGP01E1000_PHY_EDAC_MU_INDEX 0xC000 e1000_82541.h 　
27115
 IGP01E1000_PHY_EDAC_SIGN_EXT_9_IGP01E1000_PHY_EDAC_SIGN_EXT_9_ 0x8000 e1000_82541.h 　
27116
 IGP01E1000_PHY_DSP_RESETIGP01E1000_PHY_DSP_RESET 0x1F33 e1000_82541.h 　
27117
 IGP01E1000_PHY_DSP_FFEIGP01E1000_PHY_DSP_FFE 0x1F35 e1000_82541.h 　
27118
 IGP01E1000_PHY_DSP_FFE_CM_CPIGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 e1000_82541.h 　
27119
 IGP01E1000_PHY_DSP_FFE_DEFAULTIGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A e1000_82541.h 　
27120
 IGP01E1000_IEEE_FORCE_GIGIGP01E1000_IEEE_FORCE_GIG 0x0140 e1000_82541.h 　
27121
 IGP01E1000_IEEE_RESTART_AUTONEGIGP01E1000_IEEE_RESTART_AUTONEG 0x3300 e1000_82541.h 　
27122
 IGP01E1000_AGC_LENGTH_SHIFTIGP01E1000_AGC_LENGTH_SHIFT 7 e1000_82541.h 　
27123
 IGP01E1000_AGC_RANGEIGP01E1000_AGC_RANGE 10 e1000_82541.h 　
27124
 FFE_IDLE_ERR_COUNT_TIMEOUT_20FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 e1000_82541.h 　
27125
 FFE_IDLE_ERR_COUNT_TIMEOUT_100FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 e1000_82541.h 　
27126
 IGP01E1000_ANALOG_FUSE_STATUSIGP01E1000_ANALOG_FUSE_STATUS 0x20D0 e1000_82541.h 　
27127
 IGP01E1000_ANALOG_SPARE_FUSE_STIGP01E1000_ANALOG_SPARE_FUSE_ST 0x20D1 e1000_82541.h 　
27128
 IGP01E1000_ANALOG_FUSE_CONTROLIGP01E1000_ANALOG_FUSE_CONTROL 0x20DC e1000_82541.h 　
27129
 IGP01E1000_ANALOG_FUSE_BYPASSIGP01E1000_ANALOG_FUSE_BYPASS 0x20DE e1000_82541.h 　
27130
 IGP01E1000_ANALOG_SPARE_FUSE_ENIGP01E1000_ANALOG_SPARE_FUSE_EN 0x0100 e1000_82541.h 　
27131
 IGP01E1000_ANALOG_FUSE_FINE_MASIGP01E1000_ANALOG_FUSE_FINE_MAS 0x0F80 e1000_82541.h 　
27132
 IGP01E1000_ANALOG_FUSE_COARSE_MIGP01E1000_ANALOG_FUSE_COARSE_M 0x0070 e1000_82541.h 　
27133
 IGP01E1000_ANALOG_FUSE_COARSE_TIGP01E1000_ANALOG_FUSE_COARSE_T 0x0040 e1000_82541.h 　
27134
 IGP01E1000_ANALOG_FUSE_COARSE_1IGP01E1000_ANALOG_FUSE_COARSE_1 0x0010 e1000_82541.h 　
27135
 IGP01E1000_ANALOG_FUSE_FINE_1IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 e1000_82541.h 　
27136
 IGP01E1000_ANALOG_FUSE_FINE_10IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 e1000_82541.h 　
27137
 IGP01E1000_ANALOG_FUSE_POLY_MASIGP01E1000_ANALOG_FUSE_POLY_MAS 0xF000 e1000_82541.h 　
27138
 IGP01E1000_ANALOG_FUSE_ENABLE_SIGP01E1000_ANALOG_FUSE_ENABLE_S 0x0002 e1000_82541.h 　
27139
 IGP01E1000_MSE_CHANNEL_DIGP01E1000_MSE_CHANNEL_D 0x000F e1000_82541.h 　
27140
 IGP01E1000_MSE_CHANNEL_CIGP01E1000_MSE_CHANNEL_C 0x00F0 e1000_82541.h 　
27141
 IGP01E1000_MSE_CHANNEL_BIGP01E1000_MSE_CHANNEL_B 0x0F00 e1000_82541.h 　
27142
 IGP01E1000_MSE_CHANNEL_AIGP01E1000_MSE_CHANNEL_A 0xF000 e1000_82541.h 　
27143
 PHY_PREAMBLEPHY_PREAMBLE 0xFFFFFFFF e1000_82543.h 　
27144
 PHY_PREAMBLE_SIZEPHY_PREAMBLE_SIZE 32 e1000_82543.h 　
27145
 PHY_SOFPHY_SOF 0x1 e1000_82543.h 　
27146
 PHY_OP_READPHY_OP_READ 0x2 e1000_82543.h 　
27147
 PHY_OP_WRITEPHY_OP_WRITE 0x1 e1000_82543.h 　
27148
 PHY_TURNAROUNDPHY_TURNAROUND 0x2 e1000_82543.h 　
27149
 TBI_COMPAT_ENABLEDTBI_COMPAT_ENABLED 0x1 e1000_82543.h Global "knob" for the workaround
27150
 TBI_SBP_ENABLEDTBI_SBP_ENABLED 0x2 e1000_82543.h 　
27151
 REQ_TX_DESCRIPTOR_MULTIPLEREQ_TX_DESCRIPTOR_MULTIPLE 8 e1000_defines.h 　
27152
 REQ_RX_DESCRIPTOR_MULTIPLEREQ_RX_DESCRIPTOR_MULTIPLE 8 e1000_defines.h 　
27153
 E1000_WUC_APMEE1000_WUC_APME 0x00000001 e1000_defines.h APM Enable
27154
 E1000_WUC_PME_ENE1000_WUC_PME_EN 0x00000002 e1000_defines.h PME Enable
27155
 E1000_WUC_PME_STATUSE1000_WUC_PME_STATUS 0x00000004 e1000_defines.h PME Status
27156
 E1000_WUC_APMPMEE1000_WUC_APMPME 0x00000008 e1000_defines.h Assert PME on APM Wakeup
27157
 E1000_WUC_LSCWEE1000_WUC_LSCWE 0x00000010 e1000_defines.h Link Status wake up enable
27158
 E1000_WUC_LSCWOE1000_WUC_LSCWO 0x00000020 e1000_defines.h Link Status wake up override
27159
 E1000_WUC_SPME1000_WUC_SPM 0x80000000 e1000_defines.h Enable SPM
27160
 E1000_WUC_PHY_WAKEE1000_WUC_PHY_WAKE 0x00000100 e1000_defines.h if PHY supports wakeup
27161
 E1000_WUFC_LNKCE1000_WUFC_LNKC 0x00000001 e1000_defines.h Link Status Change Wakeup Enable
27162
 E1000_WUFC_MAGE1000_WUFC_MAG 0x00000002 e1000_defines.h Magic Packet Wakeup Enable
27163
 E1000_WUFC_EXE1000_WUFC_EX 0x00000004 e1000_defines.h Directed Exact Wakeup Enable
27164
 E1000_WUFC_MCE1000_WUFC_MC 0x00000008 e1000_defines.h Directed Multicast Wakeup Enable
27165
 E1000_WUFC_BCE1000_WUFC_BC 0x00000010 e1000_defines.h Broadcast Wakeup Enable
27166
 E1000_WUFC_ARPE1000_WUFC_ARP 0x00000020 e1000_defines.h ARP Request Packet Wakeup Enable
27167
 E1000_WUFC_IPV4E1000_WUFC_IPV4 0x00000040 e1000_defines.h Directed IPv4 Packet Wakeup Enable
27168
 E1000_WUFC_IPV6E1000_WUFC_IPV6 0x00000080 e1000_defines.h Directed IPv6 Packet Wakeup Enable
27169
 E1000_WUFC_IGNORE_TCOE1000_WUFC_IGNORE_TCO 0x00008000 e1000_defines.h Ignore WakeOn TCO packets
27170
 E1000_WUFC_FLX0E1000_WUFC_FLX0 0x00010000 e1000_defines.h Flexible Filter 0 Enable
27171
 E1000_WUFC_FLX1E1000_WUFC_FLX1 0x00020000 e1000_defines.h Flexible Filter 1 Enable
27172
 E1000_WUFC_FLX2E1000_WUFC_FLX2 0x00040000 e1000_defines.h Flexible Filter 2 Enable
27173
 E1000_WUFC_FLX3E1000_WUFC_FLX3 0x00080000 e1000_defines.h Flexible Filter 3 Enable
27174
 E1000_WUFC_ALL_FILTERSE1000_WUFC_ALL_FILTERS 0x000F00FF e1000_defines.h Mask for all wakeup filters
27175
 E1000_WUFC_FLX_OFFSETE1000_WUFC_FLX_OFFSET 16 e1000_defines.h Offset to the Flexible Filters bits
27176
 E1000_WUFC_FLX_FILTERSE1000_WUFC_FLX_FILTERS 0x000F0000 e1000_defines.h Mask for the 4 flexible filters
27177
 E1000_WUS_LNKCE1000_WUS_LNKC E1000_WUFC_LNKC e1000_defines.h 　
27178
 E1000_WUS_MAGE1000_WUS_MAG E1000_WUFC_MAG e1000_defines.h 　
27179
 E1000_WUS_EXE1000_WUS_EX E1000_WUFC_EX e1000_defines.h 　
27180
 E1000_WUS_MCE1000_WUS_MC E1000_WUFC_MC e1000_defines.h 　
27181
 E1000_WUS_BCE1000_WUS_BC E1000_WUFC_BC e1000_defines.h 　
27182
 E1000_WUS_ARPE1000_WUS_ARP E1000_WUFC_ARP e1000_defines.h 　
27183
 E1000_WUS_IPV4E1000_WUS_IPV4 E1000_WUFC_IPV4 e1000_defines.h 　
27184
 E1000_WUS_IPV6E1000_WUS_IPV6 E1000_WUFC_IPV6 e1000_defines.h 　
27185
 E1000_WUS_FLX0E1000_WUS_FLX0 E1000_WUFC_FLX0 e1000_defines.h 　
27186
 E1000_WUS_FLX1E1000_WUS_FLX1 E1000_WUFC_FLX1 e1000_defines.h 　
27187
 E1000_WUS_FLX2E1000_WUS_FLX2 E1000_WUFC_FLX2 e1000_defines.h 　
27188
 E1000_WUS_FLX3E1000_WUS_FLX3 E1000_WUFC_FLX3 e1000_defines.h 　
27189
 E1000_WUS_FLX_FILTERSE1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS e1000_defines.h 　
27190
 E1000_WUPL_LENGTH_MASKE1000_WUPL_LENGTH_MASK 0x0FFF e1000_defines.h Only the lower 12 bits are valid
27191
 E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 4 e1000_defines.h 　
27192
 E1000_FLEXIBLE_FILTER_SIZE_MAXE1000_FLEXIBLE_FILTER_SIZE_MAX 128 e1000_defines.h 　
27193
 E1000_FFLT_SIZEE1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX e1000_defines.h 　
27194
 E1000_FFMT_SIZEE1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000_defines.h 　
27195
 E1000_FFVT_SIZEE1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000_defines.h 　
27196
 E1000_CTRL_EXT_GPI0_ENE1000_CTRL_EXT_GPI0_EN 0x00000001 e1000_defines.h Maps SDP4 to GPI0
27197
 E1000_CTRL_EXT_GPI1_ENE1000_CTRL_EXT_GPI1_EN 0x00000002 e1000_defines.h Maps SDP5 to GPI1
27198
 E1000_CTRL_EXT_PHYINT_ENE1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN e1000_defines.h 　
27199
 E1000_CTRL_EXT_GPI2_ENE1000_CTRL_EXT_GPI2_EN 0x00000004 e1000_defines.h Maps SDP6 to GPI2
27200
 E1000_CTRL_EXT_GPI3_ENE1000_CTRL_EXT_GPI3_EN 0x00000008 e1000_defines.h Maps SDP7 to GPI3
27201
 E1000_CTRL_EXT_SDP4_DATAE1000_CTRL_EXT_SDP4_DATA 0x00000010 e1000_defines.h Value of SW Definable Pin 4
27202
 E1000_CTRL_EXT_SDP5_DATAE1000_CTRL_EXT_SDP5_DATA 0x00000020 e1000_defines.h Value of SW Definable Pin 5
27203
 E1000_CTRL_EXT_PHY_INTE1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA e1000_defines.h 　
27204
 E1000_CTRL_EXT_SDP6_DATAE1000_CTRL_EXT_SDP6_DATA 0x00000040 e1000_defines.h Value of SW Definable Pin 6
27205
 E1000_CTRL_EXT_SDP7_DATAE1000_CTRL_EXT_SDP7_DATA 0x00000080 e1000_defines.h Value of SW Definable Pin 7
27206
 E1000_CTRL_EXT_SDP4_DIRE1000_CTRL_EXT_SDP4_DIR 0x00000100 e1000_defines.h Direction of SDP4 0=in 1=out
27207
 E1000_CTRL_EXT_SDP5_DIRE1000_CTRL_EXT_SDP5_DIR 0x00000200 e1000_defines.h Direction of SDP5 0=in 1=out
27208
 E1000_CTRL_EXT_SDP6_DIRE1000_CTRL_EXT_SDP6_DIR 0x00000400 e1000_defines.h Direction of SDP6 0=in 1=out
27209
 E1000_CTRL_EXT_SDP7_DIRE1000_CTRL_EXT_SDP7_DIR 0x00000800 e1000_defines.h Direction of SDP7 0=in 1=out
27210
 E1000_CTRL_EXT_ASDCHKE1000_CTRL_EXT_ASDCHK 0x00001000 e1000_defines.h Initiate an ASD sequence
27211
 E1000_CTRL_EXT_EE_RSTE1000_CTRL_EXT_EE_RST 0x00002000 e1000_defines.h Reinitialize from EEPROM
27212
 E1000_CTRL_EXT_IPSE1000_CTRL_EXT_IPS 0x00004000 e1000_defines.h Invert Power State
27213
 E1000_CTRL_EXT_SPD_BYPSE1000_CTRL_EXT_SPD_BYPS 0x00008000 e1000_defines.h Speed Select Bypass
27214
 E1000_CTRL_EXT_RO_DISE1000_CTRL_EXT_RO_DIS 0x00020000 e1000_defines.h Relaxed Ordering disable
27215
 E1000_CTRL_EXT_DMA_DYN_CLK_ENE1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 e1000_defines.h DMA Dynamic Clock Gating
27216
 E1000_CTRL_EXT_LINK_MODE_MASKE1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 e1000_defines.h 　
27217
 E1000_CTRL_EXT_LINK_MODE_GMIIE1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 e1000_defines.h 　
27218
 E1000_CTRL_EXT_LINK_MODE_TBIE1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 e1000_defines.h 　
27219
 E1000_CTRL_EXT_LINK_MODE_KMRNE1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 e1000_defines.h 　
27220
 E1000_CTRL_EXT_LINK_MODE_PCIE_SE1000_CTRL_EXT_LINK_MODE_PCIE_S 0x00C00000 e1000_defines.h 　
27221
 E1000_CTRL_EXT_LINK_MODE_PCIX_SE1000_CTRL_EXT_LINK_MODE_PCIX_S 0x00800000 e1000_defines.h 　
27222
 E1000_CTRL_EXT_LINK_MODE_SGMIIE1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 e1000_defines.h 　
27223
 E1000_CTRL_EXT_EIAMEE1000_CTRL_EXT_EIAME 0x01000000 e1000_defines.h 　
27224
 E1000_CTRL_EXT_IRCAE1000_CTRL_EXT_IRCA 0x00000001 e1000_defines.h 　
27225
 E1000_CTRL_EXT_WR_WMARK_MASKE1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 e1000_defines.h 　
27226
 E1000_CTRL_EXT_WR_WMARK_256E1000_CTRL_EXT_WR_WMARK_256 0x00000000 e1000_defines.h 　
27227
 E1000_CTRL_EXT_WR_WMARK_320E1000_CTRL_EXT_WR_WMARK_320 0x01000000 e1000_defines.h 　
27228
 E1000_CTRL_EXT_WR_WMARK_384E1000_CTRL_EXT_WR_WMARK_384 0x02000000 e1000_defines.h 　
27229
 E1000_CTRL_EXT_WR_WMARK_448E1000_CTRL_EXT_WR_WMARK_448 0x03000000 e1000_defines.h 　
27230
 E1000_CTRL_EXT_CANCE1000_CTRL_EXT_CANC 0x04000000 e1000_defines.h Int delay cancellation
27231
 E1000_CTRL_EXT_DRV_LOADE1000_CTRL_EXT_DRV_LOAD 0x10000000 e1000_defines.h Driver loaded bit for FW
27232
 E1000_CTRL_EXT_IAMEE1000_CTRL_EXT_IAME 0x08000000 e1000_defines.h Int acknowledge Auto-mask
27233
 E1000_CRTL_EXT_PB_PARENE1000_CRTL_EXT_PB_PAREN 0x01000000 e1000_defines.h packet buffer parity error
27234
 E1000_CTRL_EXT_DF_PARENE1000_CTRL_EXT_DF_PAREN 0x02000000 e1000_defines.h descriptor FIFO parity
27235
 E1000_CTRL_EXT_GHOST_PARENE1000_CTRL_EXT_GHOST_PAREN 0x40000000 e1000_defines.h 　
27236
 E1000_CTRL_EXT_PBA_CLRE1000_CTRL_EXT_PBA_CLR 0x80000000 e1000_defines.h PBA Clear
27237
 E1000_I2CCMD_REG_ADDR_SHIFTE1000_I2CCMD_REG_ADDR_SHIFT 16 e1000_defines.h 　
27238
 E1000_I2CCMD_REG_ADDRE1000_I2CCMD_REG_ADDR 0x00FF0000 e1000_defines.h 　
27239
 E1000_I2CCMD_PHY_ADDR_SHIFTE1000_I2CCMD_PHY_ADDR_SHIFT 24 e1000_defines.h 　
27240
 E1000_I2CCMD_PHY_ADDRE1000_I2CCMD_PHY_ADDR 0x07000000 e1000_defines.h 　
27241
 E1000_I2CCMD_OPCODE_READE1000_I2CCMD_OPCODE_READ 0x08000000 e1000_defines.h 　
27242
 E1000_I2CCMD_OPCODE_WRITEE1000_I2CCMD_OPCODE_WRITE 0x00000000 e1000_defines.h 　
27243
 E1000_I2CCMD_RESETE1000_I2CCMD_RESET 0x10000000 e1000_defines.h 　
27244
 E1000_I2CCMD_READYE1000_I2CCMD_READY 0x20000000 e1000_defines.h 　
27245
 E1000_I2CCMD_INTERRUPT_ENAE1000_I2CCMD_INTERRUPT_ENA 0x40000000 e1000_defines.h 　
27246
 E1000_I2CCMD_ERRORE1000_I2CCMD_ERROR 0x80000000 e1000_defines.h 　
27247
 E1000_MAX_SGMII_PHY_REG_ADDRE1000_MAX_SGMII_PHY_REG_ADDR 255 e1000_defines.h 　
27248
 E1000_I2CCMD_PHY_TIMEOUTE1000_I2CCMD_PHY_TIMEOUT 200 e1000_defines.h 　
27249
 E1000_RXD_STAT_DDE1000_RXD_STAT_DD 0x01 e1000_defines.h Descriptor Done
27250
 E1000_RXD_STAT_EOPE1000_RXD_STAT_EOP 0x02 e1000_defines.h End of Packet
27251
 E1000_RXD_STAT_IXSME1000_RXD_STAT_IXSM 0x04 e1000_defines.h Ignore checksum
27252
 E1000_RXD_STAT_VPE1000_RXD_STAT_VP 0x08 e1000_defines.h IEEE VLAN Packet
27253
 E1000_RXD_STAT_UDPCSE1000_RXD_STAT_UDPCS 0x10 e1000_defines.h UDP xsum calculated
27254
 E1000_RXD_STAT_TCPCSE1000_RXD_STAT_TCPCS 0x20 e1000_defines.h TCP xsum calculated
27255
 E1000_RXD_STAT_IPCSE1000_RXD_STAT_IPCS 0x40 e1000_defines.h IP xsum calculated
27256
 E1000_RXD_STAT_PIFE1000_RXD_STAT_PIF 0x80 e1000_defines.h passed in-exact filter
27257
 E1000_RXD_STAT_CRCVE1000_RXD_STAT_CRCV 0x100 e1000_defines.h Speculative CRC Valid
27258
 E1000_RXD_STAT_IPIDVE1000_RXD_STAT_IPIDV 0x200 e1000_defines.h IP identification valid
27259
 E1000_RXD_STAT_UDPVE1000_RXD_STAT_UDPV 0x400 e1000_defines.h Valid UDP checksum
27260
 E1000_RXD_STAT_DYNINTE1000_RXD_STAT_DYNINT 0x800 e1000_defines.h Pkt caused INT via DYNINT
27261
 E1000_RXD_STAT_ACKE1000_RXD_STAT_ACK 0x8000 e1000_defines.h ACK Packet indication
27262
 E1000_RXD_ERR_CEE1000_RXD_ERR_CE 0x01 e1000_defines.h CRC Error
27263
 E1000_RXD_ERR_SEE1000_RXD_ERR_SE 0x02 e1000_defines.h Symbol Error
27264
 E1000_RXD_ERR_SEQE1000_RXD_ERR_SEQ 0x04 e1000_defines.h Sequence Error
27265
 E1000_RXD_ERR_CXEE1000_RXD_ERR_CXE 0x10 e1000_defines.h Carrier Extension Error
27266
 E1000_RXD_ERR_TCPEE1000_RXD_ERR_TCPE 0x20 e1000_defines.h TCP/UDP Checksum Error
27267
 E1000_RXD_ERR_IPEE1000_RXD_ERR_IPE 0x40 e1000_defines.h IP Checksum Error
27268
 E1000_RXD_ERR_RXEE1000_RXD_ERR_RXE 0x80 e1000_defines.h Rx Data Error
27269
 E1000_RXD_SPC_VLAN_MASKE1000_RXD_SPC_VLAN_MASK 0x0FFF e1000_defines.h VLAN ID is in lower 12 bits
27270
 E1000_RXD_SPC_PRI_MASKE1000_RXD_SPC_PRI_MASK 0xE000 e1000_defines.h Priority is in upper 3 bits
27271
 E1000_RXD_SPC_PRI_SHIFTE1000_RXD_SPC_PRI_SHIFT 13 e1000_defines.h 　
27272
 E1000_RXD_SPC_CFI_MASKE1000_RXD_SPC_CFI_MASK 0x1000 e1000_defines.h CFI is bit 12
27273
 E1000_RXD_SPC_CFI_SHIFTE1000_RXD_SPC_CFI_SHIFT 12 e1000_defines.h 　
27274
 E1000_RXDEXT_STATERR_CEE1000_RXDEXT_STATERR_CE 0x01000000 e1000_defines.h 　
27275
 E1000_RXDEXT_STATERR_SEE1000_RXDEXT_STATERR_SE 0x02000000 e1000_defines.h 　
27276
 E1000_RXDEXT_STATERR_SEQE1000_RXDEXT_STATERR_SEQ 0x04000000 e1000_defines.h 　
27277
 E1000_RXDEXT_STATERR_CXEE1000_RXDEXT_STATERR_CXE 0x10000000 e1000_defines.h 　
27278
 E1000_RXDEXT_STATERR_TCPEE1000_RXDEXT_STATERR_TCPE 0x20000000 e1000_defines.h 　
27279
 E1000_RXDEXT_STATERR_IPEE1000_RXDEXT_STATERR_IPE 0x40000000 e1000_defines.h 　
27280
 E1000_RXDEXT_STATERR_RXEE1000_RXDEXT_STATERR_RXE 0x80000000 e1000_defines.h 　
27281
 E1000_RXD_ERR_FRAME_ERR_MASKE1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ E1000_RXD_ERR_SE | \ E1000_RXD_ERR_SEQ | \ E1000_RXD_ER e1000_defines.h 　
27282
 E1000_RXDEXT_ERR_FRAME_ERR_MASKE1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_SE | \ E1000_RXDEXT_STATERR_SEQ | \ E10 e1000_defines.h 　
27283
 E1000_MRQC_ENABLE_MASKE1000_MRQC_ENABLE_MASK 0x00000007 e1000_defines.h 　
27284
 E1000_MRQC_ENABLE_RSS_2QE1000_MRQC_ENABLE_RSS_2Q 0x00000001 e1000_defines.h 　
27285
 E1000_MRQC_ENABLE_RSS_INTE1000_MRQC_ENABLE_RSS_INT 0x00000004 e1000_defines.h 　
27286
 E1000_MRQC_RSS_FIELD_MASKE1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 e1000_defines.h 　
27287
 E1000_MRQC_RSS_FIELD_IPV4_TCPE1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 e1000_defines.h 　
27288
 E1000_MRQC_RSS_FIELD_IPV4E1000_MRQC_RSS_FIELD_IPV4 0x00020000 e1000_defines.h 　
27289
 E1000_MRQC_RSS_FIELD_IPV6_TCP_EE1000_MRQC_RSS_FIELD_IPV6_TCP_E 0x00040000 e1000_defines.h 　
27290
 E1000_MRQC_RSS_FIELD_IPV6_EXE1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 e1000_defines.h 　
27291
 E1000_MRQC_RSS_FIELD_IPV6E1000_MRQC_RSS_FIELD_IPV6 0x00100000 e1000_defines.h 　
27292
 E1000_MRQC_RSS_FIELD_IPV6_TCPE1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 e1000_defines.h 　
27293
 E1000_RXDPS_HDRSTAT_HDRSPE1000_RXDPS_HDRSTAT_HDRSP 0x00008000 e1000_defines.h 　
27294
 E1000_RXDPS_HDRSTAT_HDRLEN_MASKE1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF e1000_defines.h 　
27295
 E1000_MANC_SMBUS_ENE1000_MANC_SMBUS_EN 0x00000001 e1000_defines.h SMBus Enabled - RO
27296
 E1000_MANC_ASF_ENE1000_MANC_ASF_EN 0x00000002 e1000_defines.h ASF Enabled - RO
27297
 E1000_MANC_R_ON_FORCEE1000_MANC_R_ON_FORCE 0x00000004 e1000_defines.h Reset on Force TCO - RO
27298
 E1000_MANC_RMCP_ENE1000_MANC_RMCP_EN 0x00000100 e1000_defines.h Enable RCMP 026Fh Filtering
27299
 E1000_MANC_0298_ENE1000_MANC_0298_EN 0x00000200 e1000_defines.h Enable RCMP 0298h Filtering
27300
 E1000_MANC_IPV4_ENE1000_MANC_IPV4_EN 0x00000400 e1000_defines.h Enable IPv4
27301
 E1000_MANC_IPV6_ENE1000_MANC_IPV6_EN 0x00000800 e1000_defines.h Enable IPv6
27302
 E1000_MANC_SNAP_ENE1000_MANC_SNAP_EN 0x00001000 e1000_defines.h Accept LLC/SNAP
27303
 E1000_MANC_ARP_ENE1000_MANC_ARP_EN 0x00002000 e1000_defines.h Enable ARP Request Filtering
27304
 E1000_MANC_NEIGHBOR_ENE1000_MANC_NEIGHBOR_EN 0x00004000 e1000_defines.h 　
27305
 E1000_MANC_ARP_RES_ENE1000_MANC_ARP_RES_EN 0x00008000 e1000_defines.h Enable ARP response Filtering
27306
 E1000_MANC_TCO_RESETE1000_MANC_TCO_RESET 0x00010000 e1000_defines.h TCO Reset Occurred
27307
 E1000_MANC_RCV_TCO_ENE1000_MANC_RCV_TCO_EN 0x00020000 e1000_defines.h Receive TCO Packets Enabled
27308
 E1000_MANC_REPORT_STATUSE1000_MANC_REPORT_STATUS 0x00040000 e1000_defines.h Status Reporting Enabled
27309
 E1000_MANC_RCV_ALLE1000_MANC_RCV_ALL 0x00080000 e1000_defines.h Receive All Enabled
27310
 E1000_MANC_BLK_PHY_RST_ON_IDEE1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 e1000_defines.h Block phy resets
27311
 E1000_MANC_EN_MAC_ADDR_FILTERE1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 e1000_defines.h 　
27312
 E1000_MANC_EN_MNG2HOSTE1000_MANC_EN_MNG2HOST 0x00200000 e1000_defines.h 　
27313
 E1000_MANC_EN_IP_ADDR_FILTERE1000_MANC_EN_IP_ADDR_FILTER 0x00400000 e1000_defines.h 　
27314
 E1000_MANC_EN_XSUM_FILTERE1000_MANC_EN_XSUM_FILTER 0x00800000 e1000_defines.h Enable checksum filtering
27315
 E1000_MANC_BR_ENE1000_MANC_BR_EN 0x01000000 e1000_defines.h Enable broadcast filtering
27316
 E1000_MANC_SMB_REQE1000_MANC_SMB_REQ 0x01000000 e1000_defines.h SMBus Request
27317
 E1000_MANC_SMB_GNTE1000_MANC_SMB_GNT 0x02000000 e1000_defines.h SMBus Grant
27318
 E1000_MANC_SMB_CLK_INE1000_MANC_SMB_CLK_IN 0x04000000 e1000_defines.h SMBus Clock In
27319
 E1000_MANC_SMB_DATA_INE1000_MANC_SMB_DATA_IN 0x08000000 e1000_defines.h SMBus Data In
27320
 E1000_MANC_SMB_DATA_OUTE1000_MANC_SMB_DATA_OUT 0x10000000 e1000_defines.h SMBus Data Out
27321
 E1000_MANC_SMB_CLK_OUTE1000_MANC_SMB_CLK_OUT 0x20000000 e1000_defines.h SMBus Clock Out
27322
 E1000_MANC_SMB_DATA_OUT_SHIFTE1000_MANC_SMB_DATA_OUT_SHIFT 28 e1000_defines.h SMBus Data Out Shift
27323
 E1000_MANC_SMB_CLK_OUT_SHIFTE1000_MANC_SMB_CLK_OUT_SHIFT 29 e1000_defines.h SMBus Clock Out Shift
27324
 E1000_RCTL_RSTE1000_RCTL_RST 0x00000001 e1000_defines.h Software reset
27325
 E1000_RCTL_ENE1000_RCTL_EN 0x00000002 e1000_defines.h enable
27326
 E1000_RCTL_SBPE1000_RCTL_SBP 0x00000004 e1000_defines.h store bad packet
27327
 E1000_RCTL_UPEE1000_RCTL_UPE 0x00000008 e1000_defines.h unicast promisc enable
27328
 E1000_RCTL_MPEE1000_RCTL_MPE 0x00000010 e1000_defines.h multicast promisc enable
27329
 E1000_RCTL_LPEE1000_RCTL_LPE 0x00000020 e1000_defines.h long packet enable
27330
 E1000_RCTL_LBM_NOE1000_RCTL_LBM_NO 0x00000000 e1000_defines.h no loopback mode
27331
 E1000_RCTL_LBM_MACE1000_RCTL_LBM_MAC 0x00000040 e1000_defines.h MAC loopback mode
27332
 E1000_RCTL_LBM_SLPE1000_RCTL_LBM_SLP 0x00000080 e1000_defines.h serial link loopback mode
27333
 E1000_RCTL_LBM_TCVRE1000_RCTL_LBM_TCVR 0x000000C0 e1000_defines.h tcvr loopback mode
27334
 E1000_RCTL_DTYP_MASKE1000_RCTL_DTYP_MASK 0x00000C00 e1000_defines.h Descriptor type mask
27335
 E1000_RCTL_DTYP_PSE1000_RCTL_DTYP_PS 0x00000400 e1000_defines.h Packet Split descriptor
27336
 E1000_RCTL_RDMTS_HALFE1000_RCTL_RDMTS_HALF 0x00000000 e1000_defines.h rx desc min thresh size
27337
 E1000_RCTL_RDMTS_QUATE1000_RCTL_RDMTS_QUAT 0x00000100 e1000_defines.h rx desc min thresh size
27338
 E1000_RCTL_RDMTS_EIGTHE1000_RCTL_RDMTS_EIGTH 0x00000200 e1000_defines.h rx desc min thresh size
27339
 E1000_RCTL_MO_SHIFTE1000_RCTL_MO_SHIFT 12 e1000_defines.h multicast offset shift
27340
 E1000_RCTL_MO_0E1000_RCTL_MO_0 0x00000000 e1000_defines.h multicast offset 11:0
27341
 E1000_RCTL_MO_1E1000_RCTL_MO_1 0x00001000 e1000_defines.h multicast offset 12:1
27342
 E1000_RCTL_MO_2E1000_RCTL_MO_2 0x00002000 e1000_defines.h multicast offset 13:2
27343
 E1000_RCTL_MO_3E1000_RCTL_MO_3 0x00003000 e1000_defines.h multicast offset 15:4
27344
 E1000_RCTL_MDRE1000_RCTL_MDR 0x00004000 e1000_defines.h multicast desc ring 0
27345
 E1000_RCTL_BAME1000_RCTL_BAM 0x00008000 e1000_defines.h broadcast enable
27346
 E1000_RCTL_SZ_2048E1000_RCTL_SZ_2048 0x00000000 e1000_defines.h rx buffer size 2048
27347
 E1000_RCTL_SZ_1024E1000_RCTL_SZ_1024 0x00010000 e1000_defines.h rx buffer size 1024
27348
 E1000_RCTL_SZ_512E1000_RCTL_SZ_512 0x00020000 e1000_defines.h rx buffer size 512
27349
 E1000_RCTL_SZ_256E1000_RCTL_SZ_256 0x00030000 e1000_defines.h rx buffer size 256
27350
 E1000_RCTL_SZ_16384E1000_RCTL_SZ_16384 0x00010000 e1000_defines.h rx buffer size 16384
27351
 E1000_RCTL_SZ_8192E1000_RCTL_SZ_8192 0x00020000 e1000_defines.h rx buffer size 8192
27352
 E1000_RCTL_SZ_4096E1000_RCTL_SZ_4096 0x00030000 e1000_defines.h rx buffer size 4096
27353
 E1000_RCTL_VFEE1000_RCTL_VFE 0x00040000 e1000_defines.h vlan filter enable
27354
 E1000_RCTL_CFIENE1000_RCTL_CFIEN 0x00080000 e1000_defines.h canonical form enable
27355
 E1000_RCTL_CFIE1000_RCTL_CFI 0x00100000 e1000_defines.h canonical form indicator
27356
 E1000_RCTL_DPFE1000_RCTL_DPF 0x00400000 e1000_defines.h discard pause frames
27357
 E1000_RCTL_PMCFE1000_RCTL_PMCF 0x00800000 e1000_defines.h pass MAC control frames
27358
 E1000_RCTL_BSEXE1000_RCTL_BSEX 0x02000000 e1000_defines.h Buffer size extension
27359
 E1000_RCTL_SECRCE1000_RCTL_SECRC 0x04000000 e1000_defines.h Strip Ethernet CRC
27360
 E1000_RCTL_FLXBUF_MASKE1000_RCTL_FLXBUF_MASK 0x78000000 e1000_defines.h Flexible buffer size
27361
 E1000_RCTL_FLXBUF_SHIFTE1000_RCTL_FLXBUF_SHIFT 27 e1000_defines.h Flexible buffer shift
27362
 E1000_PSRCTL_BSIZE0_MASKE1000_PSRCTL_BSIZE0_MASK 0x0000007F e1000_defines.h 　
27363
 E1000_PSRCTL_BSIZE1_MASKE1000_PSRCTL_BSIZE1_MASK 0x00003F00 e1000_defines.h 　
27364
 E1000_PSRCTL_BSIZE2_MASKE1000_PSRCTL_BSIZE2_MASK 0x003F0000 e1000_defines.h 　
27365
 E1000_PSRCTL_BSIZE3_MASKE1000_PSRCTL_BSIZE3_MASK 0x3F000000 e1000_defines.h 　
27366
 E1000_PSRCTL_BSIZE0_SHIFTE1000_PSRCTL_BSIZE0_SHIFT 7 e1000_defines.h Shift _right_ 7
27367
 E1000_PSRCTL_BSIZE1_SHIFTE1000_PSRCTL_BSIZE1_SHIFT 2 e1000_defines.h Shift _right_ 2
27368
 E1000_PSRCTL_BSIZE2_SHIFTE1000_PSRCTL_BSIZE2_SHIFT 6 e1000_defines.h Shift _left_ 6
27369
 E1000_PSRCTL_BSIZE3_SHIFTE1000_PSRCTL_BSIZE3_SHIFT 14 e1000_defines.h Shift _left_ 14
27370
 E1000_SWFW_EEP_SME1000_SWFW_EEP_SM 0x01 e1000_defines.h 　
27371
 E1000_SWFW_PHY0_SME1000_SWFW_PHY0_SM 0x02 e1000_defines.h 　
27372
 E1000_SWFW_PHY1_SME1000_SWFW_PHY1_SM 0x04 e1000_defines.h 　
27373
 E1000_SWFW_CSR_SME1000_SWFW_CSR_SM 0x08 e1000_defines.h 　
27374
 E1000_FACTPS_LFSE1000_FACTPS_LFS 0x40000000 e1000_defines.h LAN Function Select
27375
 E1000_CTRL_FDE1000_CTRL_FD 0x00000001 e1000_defines.h Full duplex.0=half; 1=full
27376
 E1000_CTRL_BEME1000_CTRL_BEM 0x00000002 e1000_defines.h Endian Mode.0=little,1=big
27377
 E1000_CTRL_PRIORE1000_CTRL_PRIOR 0x00000004 e1000_defines.h Priority on PCI. 0=rx,1=fair
27378
 E1000_CTRL_GIO_MASTER_DISABLEE1000_CTRL_GIO_MASTER_DISABLE 0x00000004 e1000_defines.h Blocks new Master reqs
27379
 E1000_CTRL_LRSTE1000_CTRL_LRST 0x00000008 e1000_defines.h Link reset. 0=normal,1=reset
27380
 E1000_CTRL_TMEE1000_CTRL_TME 0x00000010 e1000_defines.h Test mode. 0=normal,1=test
27381
 E1000_CTRL_SLEE1000_CTRL_SLE 0x00000020 e1000_defines.h Serial Link on 0=dis,1=en
27382
 E1000_CTRL_ASDEE1000_CTRL_ASDE 0x00000020 e1000_defines.h Auto-speed detect enable
27383
 E1000_CTRL_SLUE1000_CTRL_SLU 0x00000040 e1000_defines.h Set link up (Force Link)
27384
 E1000_CTRL_ILOSE1000_CTRL_ILOS 0x00000080 e1000_defines.h Invert Loss-Of Signal
27385
 E1000_CTRL_SPD_SELE1000_CTRL_SPD_SEL 0x00000300 e1000_defines.h Speed Select Mask
27386
 E1000_CTRL_SPD_10E1000_CTRL_SPD_10 0x00000000 e1000_defines.h Force 10Mb
27387
 E1000_CTRL_SPD_100E1000_CTRL_SPD_100 0x00000100 e1000_defines.h Force 100Mb
27388
 E1000_CTRL_SPD_1000E1000_CTRL_SPD_1000 0x00000200 e1000_defines.h Force 1Gb
27389
 E1000_CTRL_BEM32E1000_CTRL_BEM32 0x00000400 e1000_defines.h Big Endian 32 mode
27390
 E1000_CTRL_FRCSPDE1000_CTRL_FRCSPD 0x00000800 e1000_defines.h Force Speed
27391
 E1000_CTRL_FRCDPXE1000_CTRL_FRCDPX 0x00001000 e1000_defines.h Force Duplex
27392
 E1000_CTRL_D_UD_ENE1000_CTRL_D_UD_EN 0x00002000 e1000_defines.h Dock/Undock enable
27393
 E1000_CTRL_D_UD_POLARITYE1000_CTRL_D_UD_POLARITY 0x00004000 e1000_defines.h Defined polarity of Dock/Undock
27394
 E1000_CTRL_FORCE_PHY_RESETE1000_CTRL_FORCE_PHY_RESET 0x00008000 e1000_defines.h Reset both PHY ports, through
27395
 E1000_CTRL_EXT_LINK_ENE1000_CTRL_EXT_LINK_EN 0x00010000 e1000_defines.h enable link status from external
27396
 E1000_CTRL_SWDPIN0E1000_CTRL_SWDPIN0 0x00040000 e1000_defines.h SWDPIN 0 value
27397
 E1000_CTRL_SWDPIN1E1000_CTRL_SWDPIN1 0x00080000 e1000_defines.h SWDPIN 1 value
27398
 E1000_CTRL_SWDPIN2E1000_CTRL_SWDPIN2 0x00100000 e1000_defines.h SWDPIN 2 value
27399
 E1000_CTRL_SWDPIN3E1000_CTRL_SWDPIN3 0x00200000 e1000_defines.h SWDPIN 3 value
27400
 E1000_CTRL_SWDPIO0E1000_CTRL_SWDPIO0 0x00400000 e1000_defines.h SWDPIN 0 Input or output
27401
 E1000_CTRL_SWDPIO1E1000_CTRL_SWDPIO1 0x00800000 e1000_defines.h SWDPIN 1 input or output
27402
 E1000_CTRL_SWDPIO2E1000_CTRL_SWDPIO2 0x01000000 e1000_defines.h SWDPIN 2 input or output
27403
 E1000_CTRL_SWDPIO3E1000_CTRL_SWDPIO3 0x02000000 e1000_defines.h SWDPIN 3 input or output
27404
 E1000_CTRL_RSTE1000_CTRL_RST 0x04000000 e1000_defines.h Global reset
27405
 E1000_CTRL_RFCEE1000_CTRL_RFCE 0x08000000 e1000_defines.h Receive Flow Control enable
27406
 E1000_CTRL_TFCEE1000_CTRL_TFCE 0x10000000 e1000_defines.h Transmit flow control enable
27407
 E1000_CTRL_RTEE1000_CTRL_RTE 0x20000000 e1000_defines.h Routing tag enable
27408
 E1000_CTRL_VMEE1000_CTRL_VME 0x40000000 e1000_defines.h IEEE VLAN mode enable
27409
 E1000_CTRL_PHY_RSTE1000_CTRL_PHY_RST 0x80000000 e1000_defines.h PHY Reset
27410
 E1000_CTRL_SW2FW_INTE1000_CTRL_SW2FW_INT 0x02000000 e1000_defines.h Initiate an interrupt to ME
27411
 E1000_CTRL_I2C_ENAE1000_CTRL_I2C_ENA 0x02000000 e1000_defines.h I2C enable
27412
 E1000_CTRL_PHY_RESET_DIRE1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 e1000_defines.h 　
27413
 E1000_CTRL_PHY_RESETE1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 e1000_defines.h 　
27414
 E1000_CTRL_MDIO_DIRE1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 e1000_defines.h 　
27415
 E1000_CTRL_MDIOE1000_CTRL_MDIO E1000_CTRL_SWDPIN2 e1000_defines.h 　
27416
 E1000_CTRL_MDC_DIRE1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 e1000_defines.h 　
27417
 E1000_CTRL_MDCE1000_CTRL_MDC E1000_CTRL_SWDPIN3 e1000_defines.h 　
27418
 E1000_CTRL_PHY_RESET_DIR4E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR e1000_defines.h 　
27419
 E1000_CTRL_PHY_RESET4E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA e1000_defines.h 　
27420
 E1000_CONNSW_ENRGSRCE1000_CONNSW_ENRGSRC 0x4 e1000_defines.h 　
27421
 E1000_PCS_CFG_PCS_ENE1000_PCS_CFG_PCS_EN 8 e1000_defines.h 　
27422
 E1000_PCS_LCTL_FLV_LINK_UPE1000_PCS_LCTL_FLV_LINK_UP 1 e1000_defines.h 　
27423
 E1000_PCS_LCTL_FSV_10E1000_PCS_LCTL_FSV_10 0 e1000_defines.h 　
27424
 E1000_PCS_LCTL_FSV_100E1000_PCS_LCTL_FSV_100 2 e1000_defines.h 　
27425
 E1000_PCS_LCTL_FSV_1000E1000_PCS_LCTL_FSV_1000 4 e1000_defines.h 　
27426
 E1000_PCS_LCTL_FDV_FULLE1000_PCS_LCTL_FDV_FULL 8 e1000_defines.h 　
27427
 E1000_PCS_LCTL_FSDE1000_PCS_LCTL_FSD 0x10 e1000_defines.h 　
27428
 E1000_PCS_LCTL_FORCE_LINKE1000_PCS_LCTL_FORCE_LINK 0x20 e1000_defines.h 　
27429
 E1000_PCS_LCTL_LOW_LINK_LATCHE1000_PCS_LCTL_LOW_LINK_LATCH 0x40 e1000_defines.h 　
27430
 E1000_PCS_LCTL_FORCE_FCTRLE1000_PCS_LCTL_FORCE_FCTRL 0x80 e1000_defines.h 　
27431
 E1000_PCS_LCTL_AN_ENABLEE1000_PCS_LCTL_AN_ENABLE 0x10000 e1000_defines.h 　
27432
 E1000_PCS_LCTL_AN_RESTARTE1000_PCS_LCTL_AN_RESTART 0x20000 e1000_defines.h 　
27433
 E1000_PCS_LCTL_AN_TIMEOUTE1000_PCS_LCTL_AN_TIMEOUT 0x40000 e1000_defines.h 　
27434
 E1000_PCS_LCTL_AN_SGMII_BYPASSE1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 e1000_defines.h 　
27435
 E1000_PCS_LCTL_AN_SGMII_TRIGGERE1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 e1000_defines.h 　
27436
 E1000_PCS_LCTL_FAST_LINK_TIMERE1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 e1000_defines.h 　
27437
 E1000_PCS_LCTL_LINK_OK_FIXE1000_PCS_LCTL_LINK_OK_FIX 0x2000000 e1000_defines.h 　
27438
 E1000_PCS_LCTL_CRS_ON_NIE1000_PCS_LCTL_CRS_ON_NI 0x4000000 e1000_defines.h 　
27439
 E1000_ENABLE_SERDES_LOOPBACKE1000_ENABLE_SERDES_LOOPBACK 0x0410 e1000_defines.h 　
27440
 E1000_PCS_LSTS_LINK_OKE1000_PCS_LSTS_LINK_OK 1 e1000_defines.h 　
27441
 E1000_PCS_LSTS_SPEED_10E1000_PCS_LSTS_SPEED_10 0 e1000_defines.h 　
27442
 E1000_PCS_LSTS_SPEED_100E1000_PCS_LSTS_SPEED_100 2 e1000_defines.h 　
27443
 E1000_PCS_LSTS_SPEED_1000E1000_PCS_LSTS_SPEED_1000 4 e1000_defines.h 　
27444
 E1000_PCS_LSTS_DUPLEX_FULLE1000_PCS_LSTS_DUPLEX_FULL 8 e1000_defines.h 　
27445
 E1000_PCS_LSTS_SYNK_OKE1000_PCS_LSTS_SYNK_OK 0x10 e1000_defines.h 　
27446
 E1000_PCS_LSTS_AN_COMPLETEE1000_PCS_LSTS_AN_COMPLETE 0x10000 e1000_defines.h 　
27447
 E1000_PCS_LSTS_AN_PAGE_RXE1000_PCS_LSTS_AN_PAGE_RX 0x20000 e1000_defines.h 　
27448
 E1000_PCS_LSTS_AN_TIMED_OUTE1000_PCS_LSTS_AN_TIMED_OUT 0x40000 e1000_defines.h 　
27449
 E1000_PCS_LSTS_AN_REMOTE_FAULTE1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 e1000_defines.h 　
27450
 E1000_PCS_LSTS_AN_ERROR_RWSE1000_PCS_LSTS_AN_ERROR_RWS 0x100000 e1000_defines.h 　
27451
 E1000_STATUS_FDE1000_STATUS_FD 0x00000001 e1000_defines.h Full duplex.0=half,1=full
27452
 E1000_STATUS_LUE1000_STATUS_LU 0x00000002 e1000_defines.h Link up.0=no,1=link
27453
 E1000_STATUS_FUNC_MASKE1000_STATUS_FUNC_MASK 0x0000000C e1000_defines.h PCI Function Mask
27454
 E1000_STATUS_FUNC_SHIFTE1000_STATUS_FUNC_SHIFT 2 e1000_defines.h 　
27455
 E1000_STATUS_FUNC_0E1000_STATUS_FUNC_0 0x00000000 e1000_defines.h Function 0
27456
 E1000_STATUS_FUNC_1E1000_STATUS_FUNC_1 0x00000004 e1000_defines.h Function 1
27457
 E1000_STATUS_TXOFFE1000_STATUS_TXOFF 0x00000010 e1000_defines.h transmission paused
27458
 E1000_STATUS_TBIMODEE1000_STATUS_TBIMODE 0x00000020 e1000_defines.h TBI mode
27459
 E1000_STATUS_SPEED_MASKE1000_STATUS_SPEED_MASK 0x000000C0 e1000_defines.h 　
27460
 E1000_STATUS_SPEED_10E1000_STATUS_SPEED_10 0x00000000 e1000_defines.h Speed 10Mb/s
27461
 E1000_STATUS_SPEED_100E1000_STATUS_SPEED_100 0x00000040 e1000_defines.h Speed 100Mb/s
27462
 E1000_STATUS_SPEED_1000E1000_STATUS_SPEED_1000 0x00000080 e1000_defines.h Speed 1000Mb/s
27463
 E1000_STATUS_LAN_INIT_DONEE1000_STATUS_LAN_INIT_DONE 0x00000200 e1000_defines.h Lan Init Completion by NVM
27464
 E1000_STATUS_ASDVE1000_STATUS_ASDV 0x00000300 e1000_defines.h Auto speed detect value
27465
 E1000_STATUS_PHYRAE1000_STATUS_PHYRA 0x00000400 e1000_defines.h PHY Reset Asserted
27466
 E1000_STATUS_DOCK_CIE1000_STATUS_DOCK_CI 0x00000800 e1000_defines.h Change in Dock/Undock state.
27467
 E1000_STATUS_GIO_MASTER_ENABLEE1000_STATUS_GIO_MASTER_ENABLE 0x00080000 e1000_defines.h Master request status
27468
 E1000_STATUS_MTXCKOKE1000_STATUS_MTXCKOK 0x00000400 e1000_defines.h MTX clock running OK
27469
 E1000_STATUS_PCI66E1000_STATUS_PCI66 0x00000800 e1000_defines.h In 66Mhz slot
27470
 E1000_STATUS_BUS64E1000_STATUS_BUS64 0x00001000 e1000_defines.h In 64 bit slot
27471
 E1000_STATUS_PCIX_MODEE1000_STATUS_PCIX_MODE 0x00002000 e1000_defines.h PCI-X mode
27472
 E1000_STATUS_PCIX_SPEEDE1000_STATUS_PCIX_SPEED 0x0000C000 e1000_defines.h PCI-X bus speed
27473
 E1000_STATUS_BMC_SKU_0E1000_STATUS_BMC_SKU_0 0x00100000 e1000_defines.h BMC USB redirect disabled
27474
 E1000_STATUS_BMC_SKU_1E1000_STATUS_BMC_SKU_1 0x00200000 e1000_defines.h BMC SRAM disabled
27475
 E1000_STATUS_BMC_SKU_2E1000_STATUS_BMC_SKU_2 0x00400000 e1000_defines.h BMC SDRAM disabled
27476
 E1000_STATUS_BMC_CRYPTOE1000_STATUS_BMC_CRYPTO 0x00800000 e1000_defines.h BMC crypto disabled
27477
 E1000_STATUS_BMC_LITEE1000_STATUS_BMC_LITE 0x01000000 e1000_defines.h BMC external code execution
27478
 E1000_STATUS_RGMII_ENABLEE1000_STATUS_RGMII_ENABLE 0x02000000 e1000_defines.h RGMII disabled
27479
 E1000_STATUS_FUSE_8E1000_STATUS_FUSE_8 0x04000000 e1000_defines.h 　
27480
 E1000_STATUS_FUSE_9E1000_STATUS_FUSE_9 0x08000000 e1000_defines.h 　
27481
 E1000_STATUS_SERDES0_DISE1000_STATUS_SERDES0_DIS 0x10000000 e1000_defines.h SERDES disabled on port 0
27482
 E1000_STATUS_SERDES1_DISE1000_STATUS_SERDES1_DIS 0x20000000 e1000_defines.h SERDES disabled on port 1
27483
 E1000_STATUS_PCIX_SPEED_66E1000_STATUS_PCIX_SPEED_66 0x00000000 e1000_defines.h PCI-X bus speed 50-66 MHz
27484
 E1000_STATUS_PCIX_SPEED_100E1000_STATUS_PCIX_SPEED_100 0x00004000 e1000_defines.h PCI-X bus speed 66-100 MHz
27485
 E1000_STATUS_PCIX_SPEED_133E1000_STATUS_PCIX_SPEED_133 0x00008000 e1000_defines.h PCI-X bus speed 100-133 MHz
27486
 SPEED_10SPEED_10 10 e1000_defines.h 　
27487
 SPEED_100SPEED_100 100 e1000_defines.h 　
27488
 SPEED_1000SPEED_1000 1000 e1000_defines.h 　
27489
 HALF_DUPLEXHALF_DUPLEX 1 e1000_defines.h 　
27490
 FULL_DUPLEXFULL_DUPLEX 2 e1000_defines.h 　
27491
 PHY_FORCE_TIMEPHY_FORCE_TIME 20 e1000_defines.h 　
27492
 ADVERTISE_10_HALFADVERTISE_10_HALF 0x0001 e1000_defines.h 　
27493
 ADVERTISE_10_FULLADVERTISE_10_FULL 0x0002 e1000_defines.h 　
27494
 ADVERTISE_100_HALFADVERTISE_100_HALF 0x0004 e1000_defines.h 　
27495
 ADVERTISE_100_FULLADVERTISE_100_FULL 0x0008 e1000_defines.h 　
27496
 ADVERTISE_1000_HALFADVERTISE_1000_HALF 0x0010 e1000_defines.h Not used, just FYI
27497
 ADVERTISE_1000_FULLADVERTISE_1000_FULL 0x0020 e1000_defines.h 　
27498
 E1000_ALL_SPEED_DUPLEXE1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) e1000_defines.h 　
27499
 E1000_ALL_NOT_GIGE1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL) e1000_defines.h 　
27500
 E1000_ALL_100_SPEEDE1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) e1000_defines.h 　
27501
 E1000_ALL_10_SPEEDE1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) e1000_defines.h 　
27502
 E1000_ALL_FULL_DUPLEXE1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) e1000_defines.h 　
27503
 E1000_ALL_HALF_DUPLEXE1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) e1000_defines.h 　
27504
 AUTONEG_ADVERTISE_SPEED_DEFAULTAUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX e1000_defines.h 　
27505
 E1000_LEDCTL_LED0_MODE_MASKE1000_LEDCTL_LED0_MODE_MASK 0x0000000F e1000_defines.h 　
27506
 E1000_LEDCTL_LED0_MODE_SHIFTE1000_LEDCTL_LED0_MODE_SHIFT 0 e1000_defines.h 　
27507
 E1000_LEDCTL_LED0_BLINK_RATEE1000_LEDCTL_LED0_BLINK_RATE 0x00000020 e1000_defines.h 　
27508
 E1000_LEDCTL_LED0_IVRTE1000_LEDCTL_LED0_IVRT 0x00000040 e1000_defines.h 　
27509
 E1000_LEDCTL_LED0_BLINKE1000_LEDCTL_LED0_BLINK 0x00000080 e1000_defines.h 　
27510
 E1000_LEDCTL_LED1_MODE_MASKE1000_LEDCTL_LED1_MODE_MASK 0x00000F00 e1000_defines.h 　
27511
 E1000_LEDCTL_LED1_MODE_SHIFTE1000_LEDCTL_LED1_MODE_SHIFT 8 e1000_defines.h 　
27512
 E1000_LEDCTL_LED1_BLINK_RATEE1000_LEDCTL_LED1_BLINK_RATE 0x00002000 e1000_defines.h 　
27513
 E1000_LEDCTL_LED1_IVRTE1000_LEDCTL_LED1_IVRT 0x00004000 e1000_defines.h 　
27514
 E1000_LEDCTL_LED1_BLINKE1000_LEDCTL_LED1_BLINK 0x00008000 e1000_defines.h 　
27515
 E1000_LEDCTL_LED2_MODE_MASKE1000_LEDCTL_LED2_MODE_MASK 0x000F0000 e1000_defines.h 　
27516
 E1000_LEDCTL_LED2_MODE_SHIFTE1000_LEDCTL_LED2_MODE_SHIFT 16 e1000_defines.h 　
27517
 E1000_LEDCTL_LED2_BLINK_RATEE1000_LEDCTL_LED2_BLINK_RATE 0x00200000 e1000_defines.h 　
27518
 E1000_LEDCTL_LED2_IVRTE1000_LEDCTL_LED2_IVRT 0x00400000 e1000_defines.h 　
27519
 E1000_LEDCTL_LED2_BLINKE1000_LEDCTL_LED2_BLINK 0x00800000 e1000_defines.h 　
27520
 E1000_LEDCTL_LED3_MODE_MASKE1000_LEDCTL_LED3_MODE_MASK 0x0F000000 e1000_defines.h 　
27521
 E1000_LEDCTL_LED3_MODE_SHIFTE1000_LEDCTL_LED3_MODE_SHIFT 24 e1000_defines.h 　
27522
 E1000_LEDCTL_LED3_BLINK_RATEE1000_LEDCTL_LED3_BLINK_RATE 0x20000000 e1000_defines.h 　
27523
 E1000_LEDCTL_LED3_IVRTE1000_LEDCTL_LED3_IVRT 0x40000000 e1000_defines.h 　
27524
 E1000_LEDCTL_LED3_BLINKE1000_LEDCTL_LED3_BLINK 0x80000000 e1000_defines.h 　
27525
 E1000_LEDCTL_MODE_LINK_10_1000E1000_LEDCTL_MODE_LINK_10_1000 0x0 e1000_defines.h 　
27526
 E1000_LEDCTL_MODE_LINK_100_1000E1000_LEDCTL_MODE_LINK_100_1000 0x1 e1000_defines.h 　
27527
 E1000_LEDCTL_MODE_LINK_UPE1000_LEDCTL_MODE_LINK_UP 0x2 e1000_defines.h 　
27528
 E1000_LEDCTL_MODE_ACTIVITYE1000_LEDCTL_MODE_ACTIVITY 0x3 e1000_defines.h 　
27529
 E1000_LEDCTL_MODE_LINK_ACTIVITYE1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 e1000_defines.h 　
27530
 E1000_LEDCTL_MODE_LINK_10E1000_LEDCTL_MODE_LINK_10 0x5 e1000_defines.h 　
27531
 E1000_LEDCTL_MODE_LINK_100E1000_LEDCTL_MODE_LINK_100 0x6 e1000_defines.h 　
27532
 E1000_LEDCTL_MODE_LINK_1000E1000_LEDCTL_MODE_LINK_1000 0x7 e1000_defines.h 　
27533
 E1000_LEDCTL_MODE_PCIX_MODEE1000_LEDCTL_MODE_PCIX_MODE 0x8 e1000_defines.h 　
27534
 E1000_LEDCTL_MODE_FULL_DUPLEXE1000_LEDCTL_MODE_FULL_DUPLEX 0x9 e1000_defines.h 　
27535
 E1000_LEDCTL_MODE_COLLISIONE1000_LEDCTL_MODE_COLLISION 0xA e1000_defines.h 　
27536
 E1000_LEDCTL_MODE_BUS_SPEEDE1000_LEDCTL_MODE_BUS_SPEED 0xB e1000_defines.h 　
27537
 E1000_LEDCTL_MODE_BUS_SIZEE1000_LEDCTL_MODE_BUS_SIZE 0xC e1000_defines.h 　
27538
 E1000_LEDCTL_MODE_PAUSEDE1000_LEDCTL_MODE_PAUSED 0xD e1000_defines.h 　
27539
 E1000_LEDCTL_MODE_LED_ONE1000_LEDCTL_MODE_LED_ON 0xE e1000_defines.h 　
27540
 E1000_LEDCTL_MODE_LED_OFFE1000_LEDCTL_MODE_LED_OFF 0xF e1000_defines.h 　
27541
 E1000_TXD_DTYP_DE1000_TXD_DTYP_D 0x00100000 e1000_defines.h Data Descriptor
27542
 E1000_TXD_DTYP_CE1000_TXD_DTYP_C 0x00000000 e1000_defines.h Context Descriptor
27543
 E1000_TXD_POPTS_SHIFTE1000_TXD_POPTS_SHIFT 8 e1000_defines.h POPTS shift
27544
 E1000_TXD_POPTS_IXSME1000_TXD_POPTS_IXSM 0x01 e1000_defines.h Insert IP checksum
27545
 E1000_TXD_POPTS_TXSME1000_TXD_POPTS_TXSM 0x02 e1000_defines.h Insert TCP/UDP checksum
27546
 E1000_TXD_CMD_EOPE1000_TXD_CMD_EOP 0x01000000 e1000_defines.h End of Packet
27547
 E1000_TXD_CMD_IFCSE1000_TXD_CMD_IFCS 0x02000000 e1000_defines.h Insert FCS (Ethernet CRC)
27548
 E1000_TXD_CMD_ICE1000_TXD_CMD_IC 0x04000000 e1000_defines.h Insert Checksum
27549
 E1000_TXD_CMD_RSE1000_TXD_CMD_RS 0x08000000 e1000_defines.h Report Status
27550
 E1000_TXD_CMD_RPSE1000_TXD_CMD_RPS 0x10000000 e1000_defines.h Report Packet Sent
27551
 E1000_TXD_CMD_DEXTE1000_TXD_CMD_DEXT 0x20000000 e1000_defines.h Descriptor extension (0 = legacy)
27552
 E1000_TXD_CMD_VLEE1000_TXD_CMD_VLE 0x40000000 e1000_defines.h Add VLAN tag
27553
 E1000_TXD_CMD_IDEE1000_TXD_CMD_IDE 0x80000000 e1000_defines.h Enable Tidv register
27554
 E1000_TXD_STAT_DDE1000_TXD_STAT_DD 0x00000001 e1000_defines.h Descriptor Done
27555
 E1000_TXD_STAT_ECE1000_TXD_STAT_EC 0x00000002 e1000_defines.h Excess Collisions
27556
 E1000_TXD_STAT_LCE1000_TXD_STAT_LC 0x00000004 e1000_defines.h Late Collisions
27557
 E1000_TXD_STAT_TUE1000_TXD_STAT_TU 0x00000008 e1000_defines.h Transmit underrun
27558
 E1000_TXD_CMD_TCPE1000_TXD_CMD_TCP 0x01000000 e1000_defines.h TCP packet
27559
 E1000_TXD_CMD_IPE1000_TXD_CMD_IP 0x02000000 e1000_defines.h IP packet
27560
 E1000_TXD_CMD_TSEE1000_TXD_CMD_TSE 0x04000000 e1000_defines.h TCP Seg enable
27561
 E1000_TXD_STAT_TCE1000_TXD_STAT_TC 0x00000004 e1000_defines.h Tx Underrun
27562
 E1000_TCTL_RSTE1000_TCTL_RST 0x00000001 e1000_defines.h software reset
27563
 E1000_TCTL_ENE1000_TCTL_EN 0x00000002 e1000_defines.h enable tx
27564
 E1000_TCTL_BCEE1000_TCTL_BCE 0x00000004 e1000_defines.h busy check enable
27565
 E1000_TCTL_PSPE1000_TCTL_PSP 0x00000008 e1000_defines.h pad short packets
27566
 E1000_TCTL_CTE1000_TCTL_CT 0x00000ff0 e1000_defines.h collision threshold
27567
 E1000_TCTL_COLDE1000_TCTL_COLD 0x003ff000 e1000_defines.h collision distance
27568
 E1000_TCTL_SWXOFFE1000_TCTL_SWXOFF 0x00400000 e1000_defines.h SW Xoff transmission
27569
 E1000_TCTL_PBEE1000_TCTL_PBE 0x00800000 e1000_defines.h Packet Burst Enable
27570
 E1000_TCTL_RTLCE1000_TCTL_RTLC 0x01000000 e1000_defines.h Re-transmit on late collision
27571
 E1000_TCTL_NRTUE1000_TCTL_NRTU 0x02000000 e1000_defines.h No Re-transmit on underrun
27572
 E1000_TCTL_MULRE1000_TCTL_MULR 0x10000000 e1000_defines.h Multiple request support
27573
 E1000_TARC0_ENABLEE1000_TARC0_ENABLE 0x00000400 e1000_defines.h Enable Tx Queue 0
27574
 E1000_SCTL_DISABLE_SERDES_LOOPBE1000_SCTL_DISABLE_SERDES_LOOPB 0x0400 e1000_defines.h 　
27575
 E1000_RXCSUM_PCSS_MASKE1000_RXCSUM_PCSS_MASK 0x000000FF e1000_defines.h Packet Checksum Start
27576
 E1000_RXCSUM_IPOFLE1000_RXCSUM_IPOFL 0x00000100 e1000_defines.h IPv4 checksum offload
27577
 E1000_RXCSUM_TUOFLE1000_RXCSUM_TUOFL 0x00000200 e1000_defines.h TCP / UDP checksum offload
27578
 E1000_RXCSUM_IPV6OFLE1000_RXCSUM_IPV6OFL 0x00000400 e1000_defines.h IPv6 checksum offload
27579
 E1000_RXCSUM_CRCOFLE1000_RXCSUM_CRCOFL 0x00000800 e1000_defines.h CRC32 offload enable
27580
 E1000_RXCSUM_IPPCSEE1000_RXCSUM_IPPCSE 0x00001000 e1000_defines.h IP payload checksum enable
27581
 E1000_RXCSUM_PCSDE1000_RXCSUM_PCSD 0x00002000 e1000_defines.h packet checksum disabled
27582
 E1000_RFCTL_ISCSI_DISE1000_RFCTL_ISCSI_DIS 0x00000001 e1000_defines.h 　
27583
 E1000_RFCTL_ISCSI_DWC_MASKE1000_RFCTL_ISCSI_DWC_MASK 0x0000003E e1000_defines.h 　
27584
 E1000_RFCTL_ISCSI_DWC_SHIFTE1000_RFCTL_ISCSI_DWC_SHIFT 1 e1000_defines.h 　
27585
 E1000_RFCTL_NFSW_DISE1000_RFCTL_NFSW_DIS 0x00000040 e1000_defines.h 　
27586
 E1000_RFCTL_NFSR_DISE1000_RFCTL_NFSR_DIS 0x00000080 e1000_defines.h 　
27587
 E1000_RFCTL_NFS_VER_MASKE1000_RFCTL_NFS_VER_MASK 0x00000300 e1000_defines.h 　
27588
 E1000_RFCTL_NFS_VER_SHIFTE1000_RFCTL_NFS_VER_SHIFT 8 e1000_defines.h 　
27589
 E1000_RFCTL_IPV6_DISE1000_RFCTL_IPV6_DIS 0x00000400 e1000_defines.h 　
27590
 E1000_RFCTL_IPV6_XSUM_DISE1000_RFCTL_IPV6_XSUM_DIS 0x00000800 e1000_defines.h 　
27591
 E1000_RFCTL_ACK_DISE1000_RFCTL_ACK_DIS 0x00001000 e1000_defines.h 　
27592
 E1000_RFCTL_ACKD_DISE1000_RFCTL_ACKD_DIS 0x00002000 e1000_defines.h 　
27593
 E1000_RFCTL_IPFRSP_DISE1000_RFCTL_IPFRSP_DIS 0x00004000 e1000_defines.h 　
27594
 E1000_RFCTL_EXTENE1000_RFCTL_EXTEN 0x00008000 e1000_defines.h 　
27595
 E1000_RFCTL_IPV6_EX_DISE1000_RFCTL_IPV6_EX_DIS 0x00010000 e1000_defines.h 　
27596
 E1000_RFCTL_NEW_IPV6_EXT_DISE1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 e1000_defines.h 　
27597
 E1000_RFCTL_LEFE1000_RFCTL_LEF 0x00040000 e1000_defines.h 　
27598
 E1000_COLLISION_THRESHOLDE1000_COLLISION_THRESHOLD 15 e1000_defines.h 　
27599
 E1000_CT_SHIFTE1000_CT_SHIFT 4 e1000_defines.h 　
27600
 E1000_COLLISION_DISTANCEE1000_COLLISION_DISTANCE 63 e1000_defines.h 　
27601
 E1000_COLD_SHIFTE1000_COLD_SHIFT 12 e1000_defines.h 　
27602
 DEFAULT_82542_TIPG_IPGTDEFAULT_82542_TIPG_IPGT 10 e1000_defines.h 　
27603
 DEFAULT_82543_TIPG_IPGT_FIBERDEFAULT_82543_TIPG_IPGT_FIBER 9 e1000_defines.h 　
27604
 DEFAULT_82543_TIPG_IPGT_COPPERDEFAULT_82543_TIPG_IPGT_COPPER 8 e1000_defines.h 　
27605
 E1000_TIPG_IPGT_MASKE1000_TIPG_IPGT_MASK 0x000003FF e1000_defines.h 　
27606
 E1000_TIPG_IPGR1_MASKE1000_TIPG_IPGR1_MASK 0x000FFC00 e1000_defines.h 　
27607
 E1000_TIPG_IPGR2_MASKE1000_TIPG_IPGR2_MASK 0x3FF00000 e1000_defines.h 　
27608
 DEFAULT_82542_TIPG_IPGR1DEFAULT_82542_TIPG_IPGR1 2 e1000_defines.h 　
27609
 DEFAULT_82543_TIPG_IPGR1DEFAULT_82543_TIPG_IPGR1 8 e1000_defines.h 　
27610
 E1000_TIPG_IPGR1_SHIFTE1000_TIPG_IPGR1_SHIFT 10 e1000_defines.h 　
27611
 DEFAULT_82542_TIPG_IPGR2DEFAULT_82542_TIPG_IPGR2 10 e1000_defines.h 　
27612
 DEFAULT_82543_TIPG_IPGR2DEFAULT_82543_TIPG_IPGR2 6 e1000_defines.h 　
27613
 DEFAULT_80003ES2LAN_TIPG_IPGR2DEFAULT_80003ES2LAN_TIPG_IPGR2 7 e1000_defines.h 　
27614
 E1000_TIPG_IPGR2_SHIFTE1000_TIPG_IPGR2_SHIFT 20 e1000_defines.h 　
27615
 ETHERNET_IEEE_VLAN_TYPEETHERNET_IEEE_VLAN_TYPE 0x8100 e1000_defines.h 802.3ac packet
27616
 ETHERNET_FCS_SIZEETHERNET_FCS_SIZE 4 e1000_defines.h 　
27617
 MAX_JUMBO_FRAME_SIZEMAX_JUMBO_FRAME_SIZE 0x3F00 e1000_defines.h 　
27618
 E1000_EXTCNF_CTRL_MDIO_SW_OWNERE1000_EXTCNF_CTRL_MDIO_SW_OWNER 0x00000020 e1000_defines.h 　
27619
 E1000_EXTCNF_CTRL_LCD_WRITE_ENAE1000_EXTCNF_CTRL_LCD_WRITE_ENA 0x00000001 e1000_defines.h 　
27620
 E1000_EXTCNF_CTRL_SWFLAGE1000_EXTCNF_CTRL_SWFLAG 0x00000020 e1000_defines.h 　
27621
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 0x00FF0000 e1000_defines.h 　
27622
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 16 e1000_defines.h 　
27623
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 0x0FFF0000 e1000_defines.h 　
27624
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 16 e1000_defines.h 　
27625
 E1000_PHY_CTRL_SPD_ENE1000_PHY_CTRL_SPD_EN 0x00000001 e1000_defines.h 　
27626
 E1000_PHY_CTRL_D0A_LPLUE1000_PHY_CTRL_D0A_LPLU 0x00000002 e1000_defines.h 　
27627
 E1000_PHY_CTRL_NOND0A_LPLUE1000_PHY_CTRL_NOND0A_LPLU 0x00000004 e1000_defines.h 　
27628
 E1000_PHY_CTRL_NOND0A_GBE_DISABE1000_PHY_CTRL_NOND0A_GBE_DISAB 0x00000008 e1000_defines.h 　
27629
 E1000_PHY_CTRL_GBE_DISABLEE1000_PHY_CTRL_GBE_DISABLE 0x00000040 e1000_defines.h 　
27630
 E1000_KABGTXD_BGSQLBIASE1000_KABGTXD_BGSQLBIAS 0x00050000 e1000_defines.h 　
27631
 E1000_PBA_6KE1000_PBA_6K 0x0006 e1000_defines.h 6KB
27632
 E1000_PBA_8KE1000_PBA_8K 0x0008 e1000_defines.h 8KB
27633
 E1000_PBA_10KE1000_PBA_10K 0x000A e1000_defines.h 10KB
27634
 E1000_PBA_12KE1000_PBA_12K 0x000C e1000_defines.h 12KB
27635
 E1000_PBA_14KE1000_PBA_14K 0x000E e1000_defines.h 14KB
27636
 E1000_PBA_16KE1000_PBA_16K 0x0010 e1000_defines.h 16KB
27637
 E1000_PBA_18KE1000_PBA_18K 0x0012 e1000_defines.h 　
27638
 E1000_PBA_20KE1000_PBA_20K 0x0014 e1000_defines.h 　
27639
 E1000_PBA_22KE1000_PBA_22K 0x0016 e1000_defines.h 　
27640
 E1000_PBA_24KE1000_PBA_24K 0x0018 e1000_defines.h 　
27641
 E1000_PBA_26KE1000_PBA_26K 0x001A e1000_defines.h 　
27642
 E1000_PBA_30KE1000_PBA_30K 0x001E e1000_defines.h 　
27643
 E1000_PBA_32KE1000_PBA_32K 0x0020 e1000_defines.h 　
27644
 E1000_PBA_34KE1000_PBA_34K 0x0022 e1000_defines.h 　
27645
 E1000_PBA_35KE1000_PBA_35K 0x0023 e1000_defines.h 　
27646
 E1000_PBA_38KE1000_PBA_38K 0x0026 e1000_defines.h 　
27647
 E1000_PBA_40KE1000_PBA_40K 0x0028 e1000_defines.h 　
27648
 E1000_PBA_48KE1000_PBA_48K 0x0030 e1000_defines.h 48KB
27649
 E1000_PBA_64KE1000_PBA_64K 0x0040 e1000_defines.h 64KB
27650
 E1000_PBS_16KE1000_PBS_16K E1000_PBA_16K e1000_defines.h 　
27651
 E1000_PBS_24KE1000_PBS_24K E1000_PBA_24K e1000_defines.h 　
27652
 IFS_MAXIFS_MAX 80 e1000_defines.h 　
27653
 IFS_MINIFS_MIN 40 e1000_defines.h 　
27654
 IFS_RATIOIFS_RATIO 4 e1000_defines.h 　
27655
 IFS_STEPIFS_STEP 10 e1000_defines.h 　
27656
 MIN_NUM_XMITSMIN_NUM_XMITS 1000 e1000_defines.h 　
27657
 E1000_SWSM_SMBIE1000_SWSM_SMBI 0x00000001 e1000_defines.h Driver Semaphore bit
27658
 E1000_SWSM_SWESMBIE1000_SWSM_SWESMBI 0x00000002 e1000_defines.h FW Semaphore bit
27659
 E1000_SWSM_WMNGE1000_SWSM_WMNG 0x00000004 e1000_defines.h Wake MNG Clock
27660
 E1000_SWSM_DRV_LOADE1000_SWSM_DRV_LOAD 0x00000008 e1000_defines.h Driver Loaded Bit
27661
 E1000_SWSM2_LOCKE1000_SWSM2_LOCK 0x00000002 e1000_defines.h Secondary driver semaphore bit
27662
 E1000_ICR_TXDWE1000_ICR_TXDW 0x00000001 e1000_defines.h Transmit desc written back
27663
 E1000_ICR_TXQEE1000_ICR_TXQE 0x00000002 e1000_defines.h Transmit Queue empty
27664
 E1000_ICR_LSCE1000_ICR_LSC 0x00000004 e1000_defines.h Link Status Change
27665
 E1000_ICR_RXSEQE1000_ICR_RXSEQ 0x00000008 e1000_defines.h rx sequence error
27666
 E1000_ICR_RXDMT0E1000_ICR_RXDMT0 0x00000010 e1000_defines.h rx desc min. threshold (0)
27667
 E1000_ICR_RXOE1000_ICR_RXO 0x00000040 e1000_defines.h rx overrun
27668
 E1000_ICR_RXT0E1000_ICR_RXT0 0x00000080 e1000_defines.h rx timer intr (ring 0)
27669
 E1000_ICR_VMMBE1000_ICR_VMMB 0x00000100 e1000_defines.h VM MB event
27670
 E1000_ICR_MDACE1000_ICR_MDAC 0x00000200 e1000_defines.h MDIO access complete
27671
 E1000_ICR_RXCFGE1000_ICR_RXCFG 0x00000400 e1000_defines.h Rx /c/ ordered set
27672
 E1000_ICR_GPI_EN0E1000_ICR_GPI_EN0 0x00000800 e1000_defines.h GP Int 0
27673
 E1000_ICR_GPI_EN1E1000_ICR_GPI_EN1 0x00001000 e1000_defines.h GP Int 1
27674
 E1000_ICR_GPI_EN2E1000_ICR_GPI_EN2 0x00002000 e1000_defines.h GP Int 2
27675
 E1000_ICR_GPI_EN3E1000_ICR_GPI_EN3 0x00004000 e1000_defines.h GP Int 3
27676
 E1000_ICR_TXD_LOWE1000_ICR_TXD_LOW 0x00008000 e1000_defines.h 　
27677
 E1000_ICR_SRPDE1000_ICR_SRPD 0x00010000 e1000_defines.h 　
27678
 E1000_ICR_ACKE1000_ICR_ACK 0x00020000 e1000_defines.h Receive Ack frame
27679
 E1000_ICR_MNGE1000_ICR_MNG 0x00040000 e1000_defines.h Manageability event
27680
 E1000_ICR_DOCKE1000_ICR_DOCK 0x00080000 e1000_defines.h Dock/Undock
27681
 E1000_ICR_INT_ASSERTEDE1000_ICR_INT_ASSERTED 0x80000000 e1000_defines.h If this bit asserted, the driver
27682
 E1000_ICR_RXD_FIFO_PAR0E1000_ICR_RXD_FIFO_PAR0 0x00100000 e1000_defines.h Q0 Rx desc FIFO parity error
27683
 E1000_ICR_TXD_FIFO_PAR0E1000_ICR_TXD_FIFO_PAR0 0x00200000 e1000_defines.h Q0 Tx desc FIFO parity error
27684
 E1000_ICR_HOST_ARB_PARE1000_ICR_HOST_ARB_PAR 0x00400000 e1000_defines.h host arb read buffer parity err
27685
 E1000_ICR_PB_PARE1000_ICR_PB_PAR 0x00800000 e1000_defines.h packet buffer parity error
27686
 E1000_ICR_RXD_FIFO_PAR1E1000_ICR_RXD_FIFO_PAR1 0x01000000 e1000_defines.h Q1 Rx desc FIFO parity error
27687
 E1000_ICR_TXD_FIFO_PAR1E1000_ICR_TXD_FIFO_PAR1 0x02000000 e1000_defines.h Q1 Tx desc FIFO parity error
27688
 E1000_ICR_ALL_PARITYE1000_ICR_ALL_PARITY 0x03F00000 e1000_defines.h all parity error bits
27689
 E1000_ICR_DSWE1000_ICR_DSW 0x00000020 e1000_defines.h FW changed the status of DISSW
27690
 E1000_ICR_PHYINTE1000_ICR_PHYINT 0x00001000 e1000_defines.h LAN connected device generates
27691
 E1000_ICR_DOUTSYNCE1000_ICR_DOUTSYNC 0x10000000 e1000_defines.h NIC DMA out of sync
27692
 E1000_ICR_EPRSTE1000_ICR_EPRST 0x00100000 e1000_defines.h ME hardware reset occurs
27693
 POLL_IMS_ENABLE_MASKPOLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) e1000_defines.h 　
27694
 IMS_ENABLE_MASKIMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_LSC) e1000_defines.h 　
27695
 E1000_IMS_TXDWE1000_IMS_TXDW E1000_ICR_TXDW e1000_defines.h Tx desc written back
27696
 E1000_IMS_TXQEE1000_IMS_TXQE E1000_ICR_TXQE e1000_defines.h Transmit Queue empty
27697
 E1000_IMS_LSCE1000_IMS_LSC E1000_ICR_LSC e1000_defines.h Link Status Change
27698
 E1000_IMS_VMMBE1000_IMS_VMMB E1000_ICR_VMMB e1000_defines.h Mail box activity
27699
 E1000_IMS_RXSEQE1000_IMS_RXSEQ E1000_ICR_RXSEQ e1000_defines.h rx sequence error
27700
 E1000_IMS_RXDMT0E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 e1000_defines.h rx desc min. threshold
27701
 E1000_IMS_RXOE1000_IMS_RXO E1000_ICR_RXO e1000_defines.h rx overrun
27702
 E1000_IMS_RXT0E1000_IMS_RXT0 E1000_ICR_RXT0 e1000_defines.h rx timer intr
27703
 E1000_IMS_MDACE1000_IMS_MDAC E1000_ICR_MDAC e1000_defines.h MDIO access complete
27704
 E1000_IMS_RXCFGE1000_IMS_RXCFG E1000_ICR_RXCFG e1000_defines.h Rx /c/ ordered set
27705
 E1000_IMS_GPI_EN0E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 e1000_defines.h GP Int 0
27706
 E1000_IMS_GPI_EN1E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 e1000_defines.h GP Int 1
27707
 E1000_IMS_GPI_EN2E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 e1000_defines.h GP Int 2
27708
 E1000_IMS_GPI_EN3E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 e1000_defines.h GP Int 3
27709
 E1000_IMS_TXD_LOWE1000_IMS_TXD_LOW E1000_ICR_TXD_LOW e1000_defines.h 　
27710
 E1000_IMS_SRPDE1000_IMS_SRPD E1000_ICR_SRPD e1000_defines.h 　
27711
 E1000_IMS_ACKE1000_IMS_ACK E1000_ICR_ACK e1000_defines.h Receive Ack frame
27712
 E1000_IMS_MNGE1000_IMS_MNG E1000_ICR_MNG e1000_defines.h Manageability event
27713
 E1000_IMS_DOCKE1000_IMS_DOCK E1000_ICR_DOCK e1000_defines.h Dock/Undock
27714
 E1000_IMS_RXD_FIFO_PAR0E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000_defines.h Q0 Rx desc FIFO
27715
 E1000_IMS_TXD_FIFO_PAR0E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000_defines.h Q0 Tx desc FIFO
27716
 E1000_IMS_HOST_ARB_PARE1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000_defines.h host arb read buffer
27717
 E1000_IMS_PB_PARE1000_IMS_PB_PAR E1000_ICR_PB_PAR e1000_defines.h packet buffer parity
27718
 E1000_IMS_RXD_FIFO_PAR1E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000_defines.h Q1 Rx desc FIFO
27719
 E1000_IMS_TXD_FIFO_PAR1E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000_defines.h Q1 Tx desc FIFO
27720
 E1000_IMS_DSWE1000_IMS_DSW E1000_ICR_DSW e1000_defines.h 　
27721
 E1000_IMS_PHYINTE1000_IMS_PHYINT E1000_ICR_PHYINT e1000_defines.h 　
27722
 E1000_IMS_DOUTSYNCE1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC e1000_defines.h NIC DMA out of sync
27723
 E1000_IMS_EPRSTE1000_IMS_EPRST E1000_ICR_EPRST e1000_defines.h 　
27724
 E1000_ICS_TXDWE1000_ICS_TXDW E1000_ICR_TXDW e1000_defines.h Tx desc written back
27725
 E1000_ICS_TXQEE1000_ICS_TXQE E1000_ICR_TXQE e1000_defines.h Transmit Queue empty
27726
 E1000_ICS_LSCE1000_ICS_LSC E1000_ICR_LSC e1000_defines.h Link Status Change
27727
 E1000_ICS_RXSEQE1000_ICS_RXSEQ E1000_ICR_RXSEQ e1000_defines.h rx sequence error
27728
 E1000_ICS_RXDMT0E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 e1000_defines.h rx desc min. threshold
27729
 E1000_ICS_RXOE1000_ICS_RXO E1000_ICR_RXO e1000_defines.h rx overrun
27730
 E1000_ICS_RXT0E1000_ICS_RXT0 E1000_ICR_RXT0 e1000_defines.h rx timer intr
27731
 E1000_ICS_MDACE1000_ICS_MDAC E1000_ICR_MDAC e1000_defines.h MDIO access complete
27732
 E1000_ICS_RXCFGE1000_ICS_RXCFG E1000_ICR_RXCFG e1000_defines.h Rx /c/ ordered set
27733
 E1000_ICS_GPI_EN0E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 e1000_defines.h GP Int 0
27734
 E1000_ICS_GPI_EN1E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 e1000_defines.h GP Int 1
27735
 E1000_ICS_GPI_EN2E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 e1000_defines.h GP Int 2
27736
 E1000_ICS_GPI_EN3E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 e1000_defines.h GP Int 3
27737
 E1000_ICS_TXD_LOWE1000_ICS_TXD_LOW E1000_ICR_TXD_LOW e1000_defines.h 　
27738
 E1000_ICS_SRPDE1000_ICS_SRPD E1000_ICR_SRPD e1000_defines.h 　
27739
 E1000_ICS_ACKE1000_ICS_ACK E1000_ICR_ACK e1000_defines.h Receive Ack frame
27740
 E1000_ICS_MNGE1000_ICS_MNG E1000_ICR_MNG e1000_defines.h Manageability event
27741
 E1000_ICS_DOCKE1000_ICS_DOCK E1000_ICR_DOCK e1000_defines.h Dock/Undock
27742
 E1000_ICS_RXD_FIFO_PAR0E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000_defines.h Q0 Rx desc FIFO
27743
 E1000_ICS_TXD_FIFO_PAR0E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000_defines.h Q0 Tx desc FIFO
27744
 E1000_ICS_HOST_ARB_PARE1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000_defines.h host arb read buffer
27745
 E1000_ICS_PB_PARE1000_ICS_PB_PAR E1000_ICR_PB_PAR e1000_defines.h packet buffer parity
27746
 E1000_ICS_RXD_FIFO_PAR1E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000_defines.h Q1 Rx desc FIFO
27747
 E1000_ICS_TXD_FIFO_PAR1E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000_defines.h Q1 Tx desc FIFO
27748
 E1000_ICS_DSWE1000_ICS_DSW E1000_ICR_DSW e1000_defines.h 　
27749
 E1000_ICS_DOUTSYNCE1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC e1000_defines.h NIC DMA out of sync
27750
 E1000_ICS_PHYINTE1000_ICS_PHYINT E1000_ICR_PHYINT e1000_defines.h 　
27751
 E1000_ICS_EPRSTE1000_ICS_EPRST E1000_ICR_EPRST e1000_defines.h 　
27752
 E1000_TXDCTL_PTHRESHE1000_TXDCTL_PTHRESH 0x0000003F e1000_defines.h TXDCTL Prefetch Threshold
27753
 E1000_TXDCTL_HTHRESHE1000_TXDCTL_HTHRESH 0x00003F00 e1000_defines.h TXDCTL Host Threshold
27754
 E1000_TXDCTL_WTHRESHE1000_TXDCTL_WTHRESH 0x003F0000 e1000_defines.h TXDCTL Writeback Threshold
27755
 E1000_TXDCTL_GRANE1000_TXDCTL_GRAN 0x01000000 e1000_defines.h TXDCTL Granularity
27756
 E1000_TXDCTL_LWTHRESHE1000_TXDCTL_LWTHRESH 0xFE000000 e1000_defines.h TXDCTL Low Threshold
27757
 E1000_TXDCTL_FULL_TX_DESC_WBE1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 e1000_defines.h GRAN=1, WTHRESH=1
27758
 E1000_TXDCTL_MAX_TX_DESC_PREFETE1000_TXDCTL_MAX_TX_DESC_PREFET 0x0100001F e1000_defines.h GRAN=1, PTHRESH=31
27759
 E1000_TXDCTL_COUNT_DESCE1000_TXDCTL_COUNT_DESC 0x00400000 e1000_defines.h 　
27760
 FLOW_CONTROL_ADDRESS_LOWFLOW_CONTROL_ADDRESS_LOW 0x00C28001 e1000_defines.h 　
27761
 FLOW_CONTROL_ADDRESS_HIGHFLOW_CONTROL_ADDRESS_HIGH 0x00000100 e1000_defines.h 　
27762
 FLOW_CONTROL_TYPEFLOW_CONTROL_TYPE 0x8808 e1000_defines.h 　
27763
 VLAN_TAG_SIZEVLAN_TAG_SIZE 4 e1000_defines.h 802.3ac tag (not DMA'd)
27764
 E1000_VLAN_FILTER_TBL_SIZEE1000_VLAN_FILTER_TBL_SIZE 128 e1000_defines.h VLAN Filter Table (4096 bits)
27765
 E1000_RAR_ENTRIESE1000_RAR_ENTRIES 15 e1000_defines.h 　
27766
 E1000_RAH_AVE1000_RAH_AV 0x80000000 e1000_defines.h Receive descriptor valid
27767
 E1000_RAL_MAC_ADDR_LENE1000_RAL_MAC_ADDR_LEN 4 e1000_defines.h 　
27768
 E1000_RAH_MAC_ADDR_LENE1000_RAH_MAC_ADDR_LEN 2 e1000_defines.h 　
27769
 E1000_RAH_POOL_MASKE1000_RAH_POOL_MASK 0x03FC0000 e1000_defines.h 　
27770
 E1000_RAH_POOL_1E1000_RAH_POOL_1 0x00040000 e1000_defines.h 　
27771
 E1000_SUCCESSE1000_SUCCESS 0 e1000_defines.h 　
27772
 E1000_ERR_NVME1000_ERR_NVM 1 e1000_defines.h 　
27773
 E1000_ERR_PHYE1000_ERR_PHY 2 e1000_defines.h 　
27774
 E1000_ERR_CONFIGE1000_ERR_CONFIG 3 e1000_defines.h 　
27775
 E1000_ERR_PARAME1000_ERR_PARAM 4 e1000_defines.h 　
27776
 E1000_ERR_MAC_INITE1000_ERR_MAC_INIT 5 e1000_defines.h 　
27777
 E1000_ERR_PHY_TYPEE1000_ERR_PHY_TYPE 6 e1000_defines.h 　
27778
 E1000_ERR_RESETE1000_ERR_RESET 9 e1000_defines.h 　
27779
 E1000_ERR_MASTER_REQUESTS_PENDIE1000_ERR_MASTER_REQUESTS_PENDI 10 e1000_defines.h 　
27780
 E1000_ERR_HOST_INTERFACE_COMMANE1000_ERR_HOST_INTERFACE_COMMAN 11 e1000_defines.h 　
27781
 E1000_BLK_PHY_RESETE1000_BLK_PHY_RESET 12 e1000_defines.h 　
27782
 E1000_ERR_SWFW_SYNCE1000_ERR_SWFW_SYNC 13 e1000_defines.h 　
27783
 E1000_NOT_IMPLEMENTEDE1000_NOT_IMPLEMENTED 14 e1000_defines.h 　
27784
 E1000_ERR_MBXE1000_ERR_MBX 15 e1000_defines.h 　
27785
 FIBER_LINK_UP_LIMITFIBER_LINK_UP_LIMIT 50 e1000_defines.h 　
27786
 COPPER_LINK_UP_LIMITCOPPER_LINK_UP_LIMIT 10 e1000_defines.h 　
27787
 PHY_AUTO_NEG_LIMITPHY_AUTO_NEG_LIMIT 45 e1000_defines.h 　
27788
 PHY_FORCE_LIMITPHY_FORCE_LIMIT 20 e1000_defines.h 　
27789
 MASTER_DISABLE_TIMEOUTMASTER_DISABLE_TIMEOUT 800 e1000_defines.h 　
27790
 PHY_CFG_TIMEOUTPHY_CFG_TIMEOUT 100 e1000_defines.h 　
27791
 MDIO_OWNERSHIP_TIMEOUTMDIO_OWNERSHIP_TIMEOUT 10 e1000_defines.h 　
27792
 AUTO_READ_DONE_TIMEOUTAUTO_READ_DONE_TIMEOUT 10 e1000_defines.h 　
27793
 E1000_FCRTH_RTHE1000_FCRTH_RTH 0x0000FFF8 e1000_defines.h Mask Bits[15:3] for RTH
27794
 E1000_FCRTH_XFCEE1000_FCRTH_XFCE 0x80000000 e1000_defines.h External Flow Control Enable
27795
 E1000_FCRTL_RTLE1000_FCRTL_RTL 0x0000FFF8 e1000_defines.h Mask Bits[15:3] for RTL
27796
 E1000_FCRTL_XONEE1000_FCRTL_XONE 0x80000000 e1000_defines.h Enable XON frame transmission
27797
 E1000_TXCW_FDE1000_TXCW_FD 0x00000020 e1000_defines.h TXCW full duplex
27798
 E1000_TXCW_HDE1000_TXCW_HD 0x00000040 e1000_defines.h TXCW half duplex
27799
 E1000_TXCW_PAUSEE1000_TXCW_PAUSE 0x00000080 e1000_defines.h TXCW sym pause request
27800
 E1000_TXCW_ASM_DIRE1000_TXCW_ASM_DIR 0x00000100 e1000_defines.h TXCW astm pause direction
27801
 E1000_TXCW_PAUSE_MASKE1000_TXCW_PAUSE_MASK 0x00000180 e1000_defines.h TXCW pause request mask
27802
 E1000_TXCW_RFE1000_TXCW_RF 0x00003000 e1000_defines.h TXCW remote fault
27803
 E1000_TXCW_NPE1000_TXCW_NP 0x00008000 e1000_defines.h TXCW next page
27804
 E1000_TXCW_CWE1000_TXCW_CW 0x0000ffff e1000_defines.h TxConfigWord mask
27805
 E1000_TXCW_TXCE1000_TXCW_TXC 0x40000000 e1000_defines.h Transmit Config control
27806
 E1000_TXCW_ANEE1000_TXCW_ANE 0x80000000 e1000_defines.h Auto-neg enable
27807
 E1000_RXCW_CWE1000_RXCW_CW 0x0000ffff e1000_defines.h RxConfigWord mask
27808
 E1000_RXCW_NCE1000_RXCW_NC 0x04000000 e1000_defines.h Receive config no carrier
27809
 E1000_RXCW_IVE1000_RXCW_IV 0x08000000 e1000_defines.h Receive config invalid
27810
 E1000_RXCW_CCE1000_RXCW_CC 0x10000000 e1000_defines.h Receive config change
27811
 E1000_RXCW_CE1000_RXCW_C 0x20000000 e1000_defines.h Receive config
27812
 E1000_RXCW_SYNCHE1000_RXCW_SYNCH 0x40000000 e1000_defines.h Receive config synch
27813
 E1000_RXCW_ANCE1000_RXCW_ANC 0x80000000 e1000_defines.h Auto-neg complete
27814
 E1000_GCR_RXD_NO_SNOOPE1000_GCR_RXD_NO_SNOOP 0x00000001 e1000_defines.h 　
27815
 E1000_GCR_RXDSCW_NO_SNOOPE1000_GCR_RXDSCW_NO_SNOOP 0x00000002 e1000_defines.h 　
27816
 E1000_GCR_RXDSCR_NO_SNOOPE1000_GCR_RXDSCR_NO_SNOOP 0x00000004 e1000_defines.h 　
27817
 E1000_GCR_TXD_NO_SNOOPE1000_GCR_TXD_NO_SNOOP 0x00000008 e1000_defines.h 　
27818
 E1000_GCR_TXDSCW_NO_SNOOPE1000_GCR_TXDSCW_NO_SNOOP 0x00000010 e1000_defines.h 　
27819
 E1000_GCR_TXDSCR_NO_SNOOPE1000_GCR_TXDSCR_NO_SNOOP 0x00000020 e1000_defines.h 　
27820
 E1000_GCR_CMPL_TMOUT_MASKE1000_GCR_CMPL_TMOUT_MASK 0x0000F000 e1000_defines.h 　
27821
 E1000_GCR_CMPL_TMOUT_10msE1000_GCR_CMPL_TMOUT_10ms 0x00001000 e1000_defines.h 　
27822
 E1000_GCR_CMPL_TMOUT_RESENDE1000_GCR_CMPL_TMOUT_RESEND 0x00010000 e1000_defines.h 　
27823
 E1000_GCR_CAP_VER2E1000_GCR_CAP_VER2 0x00040000 e1000_defines.h 　
27824
 PCIE_NO_SNOOP_ALLPCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ E1000_GCR_RXDSCW_NO_SNOOP | \ E1000_GCR_RXDSCR_NO_SNOOP | \ E1000_GCR_TXD_NO_SNOO e1000_defines.h 　
27825
 MII_CR_SPEED_SELECT_MSBMII_CR_SPEED_SELECT_MSB 0x0040 e1000_defines.h bits 6,13: 10=1000, 01=100, 00=10
27826
 MII_CR_COLL_TEST_ENABLEMII_CR_COLL_TEST_ENABLE 0x0080 e1000_defines.h Collision test enable
27827
 MII_CR_FULL_DUPLEXMII_CR_FULL_DUPLEX 0x0100 e1000_defines.h FDX =1, half duplex =0
27828
 MII_CR_RESTART_AUTO_NEGMII_CR_RESTART_AUTO_NEG 0x0200 e1000_defines.h Restart auto negotiation
27829
 MII_CR_ISOLATEMII_CR_ISOLATE 0x0400 e1000_defines.h Isolate PHY from MII
27830
 MII_CR_POWER_DOWNMII_CR_POWER_DOWN 0x0800 e1000_defines.h Power down
27831
 MII_CR_AUTO_NEG_ENMII_CR_AUTO_NEG_EN 0x1000 e1000_defines.h Auto Neg Enable
27832
 MII_CR_SPEED_SELECT_LSBMII_CR_SPEED_SELECT_LSB 0x2000 e1000_defines.h bits 6,13: 10=1000, 01=100, 00=10
27833
 MII_CR_LOOPBACKMII_CR_LOOPBACK 0x4000 e1000_defines.h 0 = normal, 1 = loopback
27834
 MII_CR_RESETMII_CR_RESET 0x8000 e1000_defines.h 0 = normal, 1 = PHY reset
27835
 MII_CR_SPEED_1000MII_CR_SPEED_1000 0x0040 e1000_defines.h 　
27836
 MII_CR_SPEED_100MII_CR_SPEED_100 0x2000 e1000_defines.h 　
27837
 MII_CR_SPEED_10MII_CR_SPEED_10 0x0000 e1000_defines.h 　
27838
 MII_SR_EXTENDED_CAPSMII_SR_EXTENDED_CAPS 0x0001 e1000_defines.h Extended register capabilities
27839
 MII_SR_JABBER_DETECTMII_SR_JABBER_DETECT 0x0002 e1000_defines.h Jabber Detected
27840
 MII_SR_LINK_STATUSMII_SR_LINK_STATUS 0x0004 e1000_defines.h Link Status 1 = link
27841
 MII_SR_AUTONEG_CAPSMII_SR_AUTONEG_CAPS 0x0008 e1000_defines.h Auto Neg Capable
27842
 MII_SR_REMOTE_FAULTMII_SR_REMOTE_FAULT 0x0010 e1000_defines.h Remote Fault Detect
27843
 MII_SR_AUTONEG_COMPLETEMII_SR_AUTONEG_COMPLETE 0x0020 e1000_defines.h Auto Neg Complete
27844
 MII_SR_PREAMBLE_SUPPRESSMII_SR_PREAMBLE_SUPPRESS 0x0040 e1000_defines.h Preamble may be suppressed
27845
 MII_SR_EXTENDED_STATUSMII_SR_EXTENDED_STATUS 0x0100 e1000_defines.h Ext. status info in Reg 0x0F
27846
 MII_SR_100T2_HD_CAPSMII_SR_100T2_HD_CAPS 0x0200 e1000_defines.h 100T2 Half Duplex Capable
27847
 MII_SR_100T2_FD_CAPSMII_SR_100T2_FD_CAPS 0x0400 e1000_defines.h 100T2 Full Duplex Capable
27848
 MII_SR_10T_HD_CAPSMII_SR_10T_HD_CAPS 0x0800 e1000_defines.h 10T Half Duplex Capable
27849
 MII_SR_10T_FD_CAPSMII_SR_10T_FD_CAPS 0x1000 e1000_defines.h 10T Full Duplex Capable
27850
 MII_SR_100X_HD_CAPSMII_SR_100X_HD_CAPS 0x2000 e1000_defines.h 100X Half Duplex Capable
27851
 MII_SR_100X_FD_CAPSMII_SR_100X_FD_CAPS 0x4000 e1000_defines.h 100X Full Duplex Capable
27852
 MII_SR_100T4_CAPSMII_SR_100T4_CAPS 0x8000 e1000_defines.h 100T4 Capable
27853
 NWAY_AR_SELECTOR_FIELDNWAY_AR_SELECTOR_FIELD 0x0001 e1000_defines.h indicates IEEE 802.3 CSMA/CD
27854
 NWAY_AR_10T_HD_CAPSNWAY_AR_10T_HD_CAPS 0x0020 e1000_defines.h 10T Half Duplex Capable
27855
 NWAY_AR_10T_FD_CAPSNWAY_AR_10T_FD_CAPS 0x0040 e1000_defines.h 10T Full Duplex Capable
27856
 NWAY_AR_100TX_HD_CAPSNWAY_AR_100TX_HD_CAPS 0x0080 e1000_defines.h 100TX Half Duplex Capable
27857
 NWAY_AR_100TX_FD_CAPSNWAY_AR_100TX_FD_CAPS 0x0100 e1000_defines.h 100TX Full Duplex Capable
27858
 NWAY_AR_100T4_CAPSNWAY_AR_100T4_CAPS 0x0200 e1000_defines.h 100T4 Capable
27859
 NWAY_AR_PAUSENWAY_AR_PAUSE 0x0400 e1000_defines.h Pause operation desired
27860
 NWAY_AR_ASM_DIRNWAY_AR_ASM_DIR 0x0800 e1000_defines.h Asymmetric Pause Direction bit
27861
 NWAY_AR_REMOTE_FAULTNWAY_AR_REMOTE_FAULT 0x2000 e1000_defines.h Remote Fault detected
27862
 NWAY_AR_NEXT_PAGENWAY_AR_NEXT_PAGE 0x8000 e1000_defines.h Next Page ability supported
27863
 NWAY_LPAR_SELECTOR_FIELDNWAY_LPAR_SELECTOR_FIELD 0x0000 e1000_defines.h LP protocol selector field
27864
 NWAY_LPAR_10T_HD_CAPSNWAY_LPAR_10T_HD_CAPS 0x0020 e1000_defines.h LP is 10T Half Duplex Capable
27865
 NWAY_LPAR_10T_FD_CAPSNWAY_LPAR_10T_FD_CAPS 0x0040 e1000_defines.h LP is 10T Full Duplex Capable
27866
 NWAY_LPAR_100TX_HD_CAPSNWAY_LPAR_100TX_HD_CAPS 0x0080 e1000_defines.h LP is 100TX Half Duplex Capable
27867
 NWAY_LPAR_100TX_FD_CAPSNWAY_LPAR_100TX_FD_CAPS 0x0100 e1000_defines.h LP is 100TX Full Duplex Capable
27868
 NWAY_LPAR_100T4_CAPSNWAY_LPAR_100T4_CAPS 0x0200 e1000_defines.h LP is 100T4 Capable
27869
 NWAY_LPAR_PAUSENWAY_LPAR_PAUSE 0x0400 e1000_defines.h LP Pause operation desired
27870
 NWAY_LPAR_ASM_DIRNWAY_LPAR_ASM_DIR 0x0800 e1000_defines.h LP Asymmetric Pause Direction bit
27871
 NWAY_LPAR_REMOTE_FAULTNWAY_LPAR_REMOTE_FAULT 0x2000 e1000_defines.h LP has detected Remote Fault
27872
 NWAY_LPAR_ACKNOWLEDGENWAY_LPAR_ACKNOWLEDGE 0x4000 e1000_defines.h LP has rx'd link code word
27873
 NWAY_LPAR_NEXT_PAGENWAY_LPAR_NEXT_PAGE 0x8000 e1000_defines.h Next Page ability supported
27874
 NWAY_ER_LP_NWAY_CAPSNWAY_ER_LP_NWAY_CAPS 0x0001 e1000_defines.h LP has Auto Neg Capability
27875
 NWAY_ER_PAGE_RXDNWAY_ER_PAGE_RXD 0x0002 e1000_defines.h LP is 10T Half Duplex Capable
27876
 NWAY_ER_NEXT_PAGE_CAPSNWAY_ER_NEXT_PAGE_CAPS 0x0004 e1000_defines.h LP is 10T Full Duplex Capable
27877
 NWAY_ER_LP_NEXT_PAGE_CAPSNWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 e1000_defines.h LP is 100TX Half Duplex Capable
27878
 NWAY_ER_PAR_DETECT_FAULTNWAY_ER_PAR_DETECT_FAULT 0x0010 e1000_defines.h LP is 100TX Full Duplex Capable
27879
 CR_1000T_ASYM_PAUSECR_1000T_ASYM_PAUSE 0x0080 e1000_defines.h Advertise asymmetric pause bit
27880
 CR_1000T_HD_CAPSCR_1000T_HD_CAPS 0x0100 e1000_defines.h Advertise 1000T HD capability
27881
 CR_1000T_FD_CAPSCR_1000T_FD_CAPS 0x0200 e1000_defines.h Advertise 1000T FD capability
27882
 CR_1000T_REPEATER_DTECR_1000T_REPEATER_DTE 0x0400 e1000_defines.h 1=Repeater/switch device port
27883
 CR_1000T_MS_VALUECR_1000T_MS_VALUE 0x0800 e1000_defines.h 1=Configure PHY as Master
27884
 CR_1000T_MS_ENABLECR_1000T_MS_ENABLE 0x1000 e1000_defines.h 1=Master/Slave manual config value
27885
 CR_1000T_TEST_MODE_NORMALCR_1000T_TEST_MODE_NORMAL 0x0000 e1000_defines.h Normal Operation
27886
 CR_1000T_TEST_MODE_1CR_1000T_TEST_MODE_1 0x2000 e1000_defines.h Transmit Waveform test
27887
 CR_1000T_TEST_MODE_2CR_1000T_TEST_MODE_2 0x4000 e1000_defines.h Master Transmit Jitter test
27888
 CR_1000T_TEST_MODE_3CR_1000T_TEST_MODE_3 0x6000 e1000_defines.h Slave Transmit Jitter test
27889
 CR_1000T_TEST_MODE_4CR_1000T_TEST_MODE_4 0x8000 e1000_defines.h Transmitter Distortion test
27890
 SR_1000T_IDLE_ERROR_CNTSR_1000T_IDLE_ERROR_CNT 0x00FF e1000_defines.h Num idle errors since last read
27891
 SR_1000T_ASYM_PAUSE_DIRSR_1000T_ASYM_PAUSE_DIR 0x0100 e1000_defines.h LP asymmetric pause direction bit
27892
 SR_1000T_LP_HD_CAPSSR_1000T_LP_HD_CAPS 0x0400 e1000_defines.h LP is 1000T HD capable
27893
 SR_1000T_LP_FD_CAPSSR_1000T_LP_FD_CAPS 0x0800 e1000_defines.h LP is 1000T FD capable
27894
 SR_1000T_REMOTE_RX_STATUSSR_1000T_REMOTE_RX_STATUS 0x1000 e1000_defines.h Remote receiver OK
27895
 SR_1000T_LOCAL_RX_STATUSSR_1000T_LOCAL_RX_STATUS 0x2000 e1000_defines.h Local receiver OK
27896
 SR_1000T_MS_CONFIG_RESSR_1000T_MS_CONFIG_RES 0x4000 e1000_defines.h 1=Local Tx is Master, 0=Slave
27897
 SR_1000T_MS_CONFIG_FAULTSR_1000T_MS_CONFIG_FAULT 0x8000 e1000_defines.h Master/Slave config fault
27898
 SR_1000T_PHY_EXCESSIVE_IDLE_ERRSR_1000T_PHY_EXCESSIVE_IDLE_ERR 5 e1000_defines.h 　
27899
 PHY_CONTROLPHY_CONTROL 0x00 e1000_defines.h Control Register
27900
 PHY_STATUSPHY_STATUS 0x01 e1000_defines.h Status Register
27901
 PHY_ID1PHY_ID1 0x02 e1000_defines.h Phy Id Reg (word 1)
27902
 PHY_ID2PHY_ID2 0x03 e1000_defines.h Phy Id Reg (word 2)
27903
 PHY_AUTONEG_ADVPHY_AUTONEG_ADV 0x04 e1000_defines.h Autoneg Advertisement
27904
 PHY_LP_ABILITYPHY_LP_ABILITY 0x05 e1000_defines.h Link Partner Ability (Base Page)
27905
 PHY_AUTONEG_EXPPHY_AUTONEG_EXP 0x06 e1000_defines.h Autoneg Expansion Reg
27906
 PHY_NEXT_PAGE_TXPHY_NEXT_PAGE_TX 0x07 e1000_defines.h Next Page Tx
27907
 PHY_LP_NEXT_PAGEPHY_LP_NEXT_PAGE 0x08 e1000_defines.h Link Partner Next Page
27908
 PHY_1000T_CTRLPHY_1000T_CTRL 0x09 e1000_defines.h 1000Base-T Control Reg
27909
 PHY_1000T_STATUSPHY_1000T_STATUS 0x0A e1000_defines.h 1000Base-T Status Reg
27910
 PHY_EXT_STATUSPHY_EXT_STATUS 0x0F e1000_defines.h Extended Status Reg
27911
 PHY_CONTROL_LBPHY_CONTROL_LB 0x4000 e1000_defines.h PHY Loopback bit
27912
 E1000_EECD_SKE1000_EECD_SK 0x00000001 e1000_defines.h NVM Clock
27913
 E1000_EECD_CSE1000_EECD_CS 0x00000002 e1000_defines.h NVM Chip Select
27914
 E1000_EECD_DIE1000_EECD_DI 0x00000004 e1000_defines.h NVM Data In
27915
 E1000_EECD_DOE1000_EECD_DO 0x00000008 e1000_defines.h NVM Data Out
27916
 E1000_EECD_FWE_MASKE1000_EECD_FWE_MASK 0x00000030 e1000_defines.h 　
27917
 E1000_EECD_FWE_DISE1000_EECD_FWE_DIS 0x00000010 e1000_defines.h Disable FLASH writes
27918
 E1000_EECD_FWE_ENE1000_EECD_FWE_EN 0x00000020 e1000_defines.h Enable FLASH writes
27919
 E1000_EECD_FWE_SHIFTE1000_EECD_FWE_SHIFT 4 e1000_defines.h 　
27920
 E1000_EECD_REQE1000_EECD_REQ 0x00000040 e1000_defines.h NVM Access Request
27921
 E1000_EECD_GNTE1000_EECD_GNT 0x00000080 e1000_defines.h NVM Access Grant
27922
 E1000_EECD_PRESE1000_EECD_PRES 0x00000100 e1000_defines.h NVM Present
27923
 E1000_EECD_SIZEE1000_EECD_SIZE 0x00000200 e1000_defines.h NVM Size (0=64 word 1=256 word)
27924
 E1000_EECD_ADDR_BITSE1000_EECD_ADDR_BITS 0x00000400 e1000_defines.h 　
27925
 E1000_EECD_TYPEE1000_EECD_TYPE 0x00002000 e1000_defines.h NVM Type (1-SPI, 0-Microwire)
27926
 E1000_NVM_GRANT_ATTEMPTSE1000_NVM_GRANT_ATTEMPTS 1000 e1000_defines.h NVM # attempts to gain grant
27927
 E1000_EECD_AUTO_RDE1000_EECD_AUTO_RD 0x00000200 e1000_defines.h NVM Auto Read done
27928
 E1000_EECD_SIZE_EX_MASKE1000_EECD_SIZE_EX_MASK 0x00007800 e1000_defines.h NVM Size
27929
 E1000_EECD_SIZE_EX_SHIFTE1000_EECD_SIZE_EX_SHIFT 11 e1000_defines.h 　
27930
 E1000_EECD_NVADDSE1000_EECD_NVADDS 0x00018000 e1000_defines.h NVM Address Size
27931
 E1000_EECD_SELSHADE1000_EECD_SELSHAD 0x00020000 e1000_defines.h Select Shadow RAM
27932
 E1000_EECD_INITSRAME1000_EECD_INITSRAM 0x00040000 e1000_defines.h Initialize Shadow RAM
27933
 E1000_EECD_FLUPDE1000_EECD_FLUPD 0x00080000 e1000_defines.h Update FLASH
27934
 E1000_EECD_AUPDENE1000_EECD_AUPDEN 0x00100000 e1000_defines.h Enable Autonomous FLASH update
27935
 E1000_EECD_SHADVE1000_EECD_SHADV 0x00200000 e1000_defines.h Shadow RAM Data Valid
27936
 E1000_EECD_SEC1VALE1000_EECD_SEC1VAL 0x00400000 e1000_defines.h Sector One Valid
27937
 E1000_EECD_SECVAL_SHIFTE1000_EECD_SECVAL_SHIFT 22 e1000_defines.h 　
27938
 E1000_EECD_SEC1VAL_VALID_MASKE1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) e1000_defines.h 　
27939
 E1000_NVM_SWDPIN0E1000_NVM_SWDPIN0 0x0001 e1000_defines.h SWDPIN 0 NVM Value
27940
 E1000_NVM_LED_LOGICE1000_NVM_LED_LOGIC 0x0020 e1000_defines.h Led Logic Word
27941
 E1000_NVM_RW_REG_DATAE1000_NVM_RW_REG_DATA 16 e1000_defines.h Offset to data in NVM read/write regs
27942
 E1000_NVM_RW_REG_DONEE1000_NVM_RW_REG_DONE 2 e1000_defines.h Offset to READ/WRITE done bit
27943
 E1000_NVM_RW_REG_STARTE1000_NVM_RW_REG_START 1 e1000_defines.h Start operation
27944
 E1000_NVM_RW_ADDR_SHIFTE1000_NVM_RW_ADDR_SHIFT 2 e1000_defines.h Shift to the address bits
27945
 E1000_NVM_POLL_WRITEE1000_NVM_POLL_WRITE 1 e1000_defines.h Flag for polling for write complete
27946
 E1000_NVM_POLL_READE1000_NVM_POLL_READ 0 e1000_defines.h Flag for polling for read complete
27947
 E1000_FLASH_UPDATESE1000_FLASH_UPDATES 2000 e1000_defines.h 　
27948
 NVM_COMPATNVM_COMPAT 0x0003 e1000_defines.h 　
27949
 NVM_ID_LED_SETTINGSNVM_ID_LED_SETTINGS 0x0004 e1000_defines.h 　
27950
 NVM_VERSIONNVM_VERSION 0x0005 e1000_defines.h 　
27951
 NVM_SERDES_AMPLITUDENVM_SERDES_AMPLITUDE 0x0006 e1000_defines.h SERDES output amplitude
27952
 NVM_PHY_CLASS_WORDNVM_PHY_CLASS_WORD 0x0007 e1000_defines.h 　
27953
 NVM_INIT_CONTROL1_REGNVM_INIT_CONTROL1_REG 0x000A e1000_defines.h 　
27954
 NVM_INIT_CONTROL2_REGNVM_INIT_CONTROL2_REG 0x000F e1000_defines.h 　
27955
 NVM_SWDEF_PINS_CTRL_PORT_1NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 e1000_defines.h 　
27956
 NVM_INIT_CONTROL3_PORT_BNVM_INIT_CONTROL3_PORT_B 0x0014 e1000_defines.h 　
27957
 NVM_INIT_3GIO_3NVM_INIT_3GIO_3 0x001A e1000_defines.h 　
27958
 NVM_SWDEF_PINS_CTRL_PORT_0NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 e1000_defines.h 　
27959
 NVM_INIT_CONTROL3_PORT_ANVM_INIT_CONTROL3_PORT_A 0x0024 e1000_defines.h 　
27960
 NVM_CFGNVM_CFG 0x0012 e1000_defines.h 　
27961
 NVM_FLASH_VERSIONNVM_FLASH_VERSION 0x0032 e1000_defines.h 　
27962
 NVM_ALT_MAC_ADDR_PTRNVM_ALT_MAC_ADDR_PTR 0x0037 e1000_defines.h 　
27963
 NVM_CHECKSUM_REGNVM_CHECKSUM_REG 0x003F e1000_defines.h 　
27964
 E1000_NVM_CFG_DONE_PORT_0E1000_NVM_CFG_DONE_PORT_0 0x040000 e1000_defines.h MNG config cycle done
27965
 E1000_NVM_CFG_DONE_PORT_1E1000_NVM_CFG_DONE_PORT_1 0x080000 e1000_defines.h ...for second port
27966
 NVM_WORD0F_PAUSE_MASKNVM_WORD0F_PAUSE_MASK 0x3000 e1000_defines.h 　
27967
 NVM_WORD0F_PAUSENVM_WORD0F_PAUSE 0x1000 e1000_defines.h 　
27968
 NVM_WORD0F_ASM_DIRNVM_WORD0F_ASM_DIR 0x2000 e1000_defines.h 　
27969
 NVM_WORD0F_ANENVM_WORD0F_ANE 0x0800 e1000_defines.h 　
27970
 NVM_WORD0F_SWPDIO_EXT_MASKNVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 e1000_defines.h 　
27971
 NVM_WORD0F_LPLUNVM_WORD0F_LPLU 0x0001 e1000_defines.h 　
27972
 NVM_WORD1A_ASPM_MASKNVM_WORD1A_ASPM_MASK 0x000C e1000_defines.h 　
27973
 NVM_SUMNVM_SUM 0xBABA e1000_defines.h 　
27974
 NVM_MAC_ADDR_OFFSETNVM_MAC_ADDR_OFFSET 0 e1000_defines.h 　
27975
 NVM_PBA_OFFSET_0NVM_PBA_OFFSET_0 8 e1000_defines.h 　
27976
 NVM_PBA_OFFSET_1NVM_PBA_OFFSET_1 9 e1000_defines.h 　
27977
 NVM_RESERVED_WORDNVM_RESERVED_WORD 0xFFFF e1000_defines.h 　
27978
 NVM_PHY_CLASS_ANVM_PHY_CLASS_A 0x8000 e1000_defines.h 　
27979
 NVM_SERDES_AMPLITUDE_MASKNVM_SERDES_AMPLITUDE_MASK 0x000F e1000_defines.h 　
27980
 NVM_SIZE_MASKNVM_SIZE_MASK 0x1C00 e1000_defines.h 　
27981
 NVM_SIZE_SHIFTNVM_SIZE_SHIFT 10 e1000_defines.h 　
27982
 NVM_WORD_SIZE_BASE_SHIFTNVM_WORD_SIZE_BASE_SHIFT 6 e1000_defines.h 　
27983
 NVM_SWDPIO_EXT_SHIFTNVM_SWDPIO_EXT_SHIFT 4 e1000_defines.h 　
27984
 NVM_READ_OPCODE_MICROWIRENVM_READ_OPCODE_MICROWIRE 0x6 e1000_defines.h NVM read opcode
27985
 NVM_WRITE_OPCODE_MICROWIRENVM_WRITE_OPCODE_MICROWIRE 0x5 e1000_defines.h NVM write opcode
27986
 NVM_ERASE_OPCODE_MICROWIRENVM_ERASE_OPCODE_MICROWIRE 0x7 e1000_defines.h NVM erase opcode
27987
 NVM_EWEN_OPCODE_MICROWIRENVM_EWEN_OPCODE_MICROWIRE 0x13 e1000_defines.h NVM erase/write enable
27988
 NVM_EWDS_OPCODE_MICROWIRENVM_EWDS_OPCODE_MICROWIRE 0x10 e1000_defines.h NVM erase/write disable
27989
 NVM_MAX_RETRY_SPINVM_MAX_RETRY_SPI 5000 e1000_defines.h Max wait of 5ms, for RDY signal
27990
 NVM_READ_OPCODE_SPINVM_READ_OPCODE_SPI 0x03 e1000_defines.h NVM read opcode
27991
 NVM_WRITE_OPCODE_SPINVM_WRITE_OPCODE_SPI 0x02 e1000_defines.h NVM write opcode
27992
 NVM_A8_OPCODE_SPINVM_A8_OPCODE_SPI 0x08 e1000_defines.h opcode bit-3 = address bit-8
27993
 NVM_WREN_OPCODE_SPINVM_WREN_OPCODE_SPI 0x06 e1000_defines.h NVM set Write Enable latch
27994
 NVM_WRDI_OPCODE_SPINVM_WRDI_OPCODE_SPI 0x04 e1000_defines.h NVM reset Write Enable latch
27995
 NVM_RDSR_OPCODE_SPINVM_RDSR_OPCODE_SPI 0x05 e1000_defines.h NVM read Status register
27996
 NVM_WRSR_OPCODE_SPINVM_WRSR_OPCODE_SPI 0x01 e1000_defines.h NVM write Status register
27997
 NVM_STATUS_RDY_SPINVM_STATUS_RDY_SPI 0x01 e1000_defines.h 　
27998
 NVM_STATUS_WEN_SPINVM_STATUS_WEN_SPI 0x02 e1000_defines.h 　
27999
 NVM_STATUS_BP0_SPINVM_STATUS_BP0_SPI 0x04 e1000_defines.h 　
28000
 NVM_STATUS_BP1_SPINVM_STATUS_BP1_SPI 0x08 e1000_defines.h 　
28001
 NVM_STATUS_WPEN_SPINVM_STATUS_WPEN_SPI 0x80 e1000_defines.h 　
28002
 ID_LED_RESERVED_0000ID_LED_RESERVED_0000 0x0000 e1000_defines.h 　
28003
 ID_LED_RESERVED_FFFFID_LED_RESERVED_FFFF 0xFFFF e1000_defines.h 　
28004
 ID_LED_DEFAULTID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) e1000_defines.h 　
28005
 ID_LED_DEF1_DEF2ID_LED_DEF1_DEF2 0x1 e1000_defines.h 　
28006
 ID_LED_DEF1_ON2ID_LED_DEF1_ON2 0x2 e1000_defines.h 　
28007
 ID_LED_DEF1_OFF2ID_LED_DEF1_OFF2 0x3 e1000_defines.h 　
28008
 ID_LED_ON1_DEF2ID_LED_ON1_DEF2 0x4 e1000_defines.h 　
28009
 ID_LED_ON1_ON2ID_LED_ON1_ON2 0x5 e1000_defines.h 　
28010
 ID_LED_ON1_OFF2ID_LED_ON1_OFF2 0x6 e1000_defines.h 　
28011
 ID_LED_OFF1_DEF2ID_LED_OFF1_DEF2 0x7 e1000_defines.h 　
28012
 ID_LED_OFF1_ON2ID_LED_OFF1_ON2 0x8 e1000_defines.h 　
28013
 ID_LED_OFF1_OFF2ID_LED_OFF1_OFF2 0x9 e1000_defines.h 　
28014
 IGP_ACTIVITY_LED_MASKIGP_ACTIVITY_LED_MASK 0xFFFFF0FF e1000_defines.h 　
28015
 IGP_ACTIVITY_LED_ENABLEIGP_ACTIVITY_LED_ENABLE 0x0300 e1000_defines.h 　
28016
 IGP_LED3_MODEIGP_LED3_MODE 0x07000000 e1000_defines.h 　
28017
 PCIX_COMMAND_REGISTERPCIX_COMMAND_REGISTER 0xE6 e1000_defines.h 　
28018
 PCIX_STATUS_REGISTER_LOPCIX_STATUS_REGISTER_LO 0xE8 e1000_defines.h 　
28019
 PCIX_STATUS_REGISTER_HIPCIX_STATUS_REGISTER_HI 0xEA e1000_defines.h 　
28020
 PCI_HEADER_TYPE_REGISTERPCI_HEADER_TYPE_REGISTER 0x0E e1000_defines.h 　
28021
 PCIE_LINK_STATUSPCIE_LINK_STATUS 0x12 e1000_defines.h 　
28022
 PCIE_DEVICE_CONTROL2PCIE_DEVICE_CONTROL2 0x28 e1000_defines.h 　
28023
 PCIX_COMMAND_MMRBC_MASKPCIX_COMMAND_MMRBC_MASK 0x000C e1000_defines.h 　
28024
 PCIX_COMMAND_MMRBC_SHIFTPCIX_COMMAND_MMRBC_SHIFT 0x2 e1000_defines.h 　
28025
 PCIX_STATUS_HI_MMRBC_MASKPCIX_STATUS_HI_MMRBC_MASK 0x0060 e1000_defines.h 　
28026
 PCIX_STATUS_HI_MMRBC_SHIFTPCIX_STATUS_HI_MMRBC_SHIFT 0x5 e1000_defines.h 　
28027
 PCIX_STATUS_HI_MMRBC_4KPCIX_STATUS_HI_MMRBC_4K 0x3 e1000_defines.h 　
28028
 PCIX_STATUS_HI_MMRBC_2KPCIX_STATUS_HI_MMRBC_2K 0x2 e1000_defines.h 　
28029
 PCIX_STATUS_LO_FUNC_MASKPCIX_STATUS_LO_FUNC_MASK 0x7 e1000_defines.h 　
28030
 PCI_HEADER_TYPE_MULTIFUNCPCI_HEADER_TYPE_MULTIFUNC 0x80 e1000_defines.h 　
28031
 PCIE_LINK_WIDTH_MASKPCIE_LINK_WIDTH_MASK 0x3F0 e1000_defines.h 　
28032
 PCIE_LINK_WIDTH_SHIFTPCIE_LINK_WIDTH_SHIFT 4 e1000_defines.h 　
28033
 PCIE_DEVICE_CONTROL2_16msPCIE_DEVICE_CONTROL2_16ms 0x0005 e1000_defines.h 　
28034
 ETH_ADDR_LENETH_ADDR_LEN 6 e1000_defines.h 　
28035
 PHY_REVISION_MASKPHY_REVISION_MASK 0xFFFFFFF0 e1000_defines.h 　
28036
 MAX_PHY_REG_ADDRESSMAX_PHY_REG_ADDRESS 0x1F e1000_defines.h 5 bit address bus (0-0x1F)
28037
 MAX_PHY_MULTI_PAGE_REGMAX_PHY_MULTI_PAGE_REG 0xF e1000_defines.h 　
28038
 M88E1000_E_PHY_IDM88E1000_E_PHY_ID 0x01410C50 e1000_defines.h 　
28039
 M88E1000_I_PHY_IDM88E1000_I_PHY_ID 0x01410C30 e1000_defines.h 　
28040
 M88E1011_I_PHY_IDM88E1011_I_PHY_ID 0x01410C20 e1000_defines.h 　
28041
 IGP01E1000_I_PHY_IDIGP01E1000_I_PHY_ID 0x02A80380 e1000_defines.h 　
28042
 M88E1011_I_REV_4M88E1011_I_REV_4 0x04 e1000_defines.h 　
28043
 M88E1111_I_PHY_IDM88E1111_I_PHY_ID 0x01410CC0 e1000_defines.h 　
28044
 GG82563_E_PHY_IDGG82563_E_PHY_ID 0x01410CA0 e1000_defines.h 　
28045
 IGP03E1000_E_PHY_IDIGP03E1000_E_PHY_ID 0x02A80390 e1000_defines.h 　
28046
 IFE_E_PHY_IDIFE_E_PHY_ID 0x02A80330 e1000_defines.h 　
28047
 IFE_PLUS_E_PHY_IDIFE_PLUS_E_PHY_ID 0x02A80320 e1000_defines.h 　
28048
 IFE_C_E_PHY_IDIFE_C_E_PHY_ID 0x02A80310 e1000_defines.h 　
28049
 M88_VENDORM88_VENDOR 0x0141 e1000_defines.h 　
28050
 M88E1000_PHY_SPEC_CTRLM88E1000_PHY_SPEC_CTRL 0x10 e1000_defines.h PHY Specific Control Register
28051
 M88E1000_PHY_SPEC_STATUSM88E1000_PHY_SPEC_STATUS 0x11 e1000_defines.h PHY Specific Status Register
28052
 M88E1000_INT_ENABLEM88E1000_INT_ENABLE 0x12 e1000_defines.h Interrupt Enable Register
28053
 M88E1000_INT_STATUSM88E1000_INT_STATUS 0x13 e1000_defines.h Interrupt Status Register
28054
 M88E1000_EXT_PHY_SPEC_CTRLM88E1000_EXT_PHY_SPEC_CTRL 0x14 e1000_defines.h Extended PHY Specific Control
28055
 M88E1000_RX_ERR_CNTRM88E1000_RX_ERR_CNTR 0x15 e1000_defines.h Receive Error Counter
28056
 M88E1000_PHY_EXT_CTRLM88E1000_PHY_EXT_CTRL 0x1A e1000_defines.h PHY extend control register
28057
 M88E1000_PHY_PAGE_SELECTM88E1000_PHY_PAGE_SELECT 0x1D e1000_defines.h Reg 29 for page number setting
28058
 M88E1000_PHY_GEN_CONTROLM88E1000_PHY_GEN_CONTROL 0x1E e1000_defines.h Its meaning depends on reg 29
28059
 M88E1000_PHY_VCO_REG_BIT8M88E1000_PHY_VCO_REG_BIT8 0x100 e1000_defines.h Bits 8 & 11 are adjusted for
28060
 M88E1000_PHY_VCO_REG_BIT11M88E1000_PHY_VCO_REG_BIT11 0x800 e1000_defines.h improved BER performance
28061
 M88E1000_PSCR_JABBER_DISABLEM88E1000_PSCR_JABBER_DISABLE 0x0001 e1000_defines.h 1=Jabber Function disabled
28062
 M88E1000_PSCR_POLARITY_REVERSALM88E1000_PSCR_POLARITY_REVERSAL 0x0002 e1000_defines.h 1=Polarity Reverse enabled
28063
 M88E1000_PSCR_SQE_TESTM88E1000_PSCR_SQE_TEST 0x0004 e1000_defines.h 1=SQE Test enabled
28064
 M88E1000_PSCR_CLK125_DISABLEM88E1000_PSCR_CLK125_DISABLE 0x0010 e1000_defines.h 　
28065
 M88E1000_PSCR_MDI_MANUAL_MODEM88E1000_PSCR_MDI_MANUAL_MODE 0x0000 e1000_defines.h MDI Crossover Mode bits 6:5
28066
 M88E1000_PSCR_MDIX_MANUAL_MODEM88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 e1000_defines.h Manual MDIX configuration
28067
 M88E1000_PSCR_AUTO_X_1000TM88E1000_PSCR_AUTO_X_1000T 0x0040 e1000_defines.h 　
28068
 M88E1000_PSCR_AUTO_X_MODEM88E1000_PSCR_AUTO_X_MODE 0x0060 e1000_defines.h 　
28069
 M88E1000_PSCR_EN_10BT_EXT_DISTM88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 e1000_defines.h 　
28070
 M88E1000_PSCR_MII_5BIT_ENABLEM88E1000_PSCR_MII_5BIT_ENABLE 0x0100 e1000_defines.h 　
28071
 M88E1000_PSCR_SCRAMBLER_DISABLEM88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 e1000_defines.h 1=Scrambler disable
28072
 M88E1000_PSCR_FORCE_LINK_GOODM88E1000_PSCR_FORCE_LINK_GOOD 0x0400 e1000_defines.h 1=Force link good
28073
 M88E1000_PSCR_ASSERT_CRS_ON_TXM88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 e1000_defines.h 1=Assert CRS on Tx
28074
 M88E1000_PSSR_JABBERM88E1000_PSSR_JABBER 0x0001 e1000_defines.h 1=Jabber
28075
 M88E1000_PSSR_REV_POLARITYM88E1000_PSSR_REV_POLARITY 0x0002 e1000_defines.h 1=Polarity reversed
28076
 M88E1000_PSSR_DOWNSHIFTM88E1000_PSSR_DOWNSHIFT 0x0020 e1000_defines.h 1=Downshifted
28077
 M88E1000_PSSR_MDIXM88E1000_PSSR_MDIX 0x0040 e1000_defines.h 1=MDIX; 0=MDI
28078
 M88E1000_PSSR_CABLE_LENGTHM88E1000_PSSR_CABLE_LENGTH 0x0380 e1000_defines.h 　
28079
 M88E1000_PSSR_LINKM88E1000_PSSR_LINK 0x0400 e1000_defines.h 1=Link up, 0=Link down
28080
 M88E1000_PSSR_SPD_DPLX_RESOLVEDM88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 e1000_defines.h 1=Speed & Duplex resolved
28081
 M88E1000_PSSR_PAGE_RCVDM88E1000_PSSR_PAGE_RCVD 0x1000 e1000_defines.h 1=Page received
28082
 M88E1000_PSSR_DPLXM88E1000_PSSR_DPLX 0x2000 e1000_defines.h 1=Duplex 0=Half Duplex
28083
 M88E1000_PSSR_SPEEDM88E1000_PSSR_SPEED 0xC000 e1000_defines.h Speed, bits 14:15
28084
 M88E1000_PSSR_10MBSM88E1000_PSSR_10MBS 0x0000 e1000_defines.h 00=10Mbs
28085
 M88E1000_PSSR_100MBSM88E1000_PSSR_100MBS 0x4000 e1000_defines.h 01=100Mbs
28086
 M88E1000_PSSR_1000MBSM88E1000_PSSR_1000MBS 0x8000 e1000_defines.h 10=1000Mbs
28087
 M88E1000_PSSR_CABLE_LENGTH_SHIFM88E1000_PSSR_CABLE_LENGTH_SHIF 7 e1000_defines.h 　
28088
 M88E1000_EPSCR_FIBER_LOOPBACKM88E1000_EPSCR_FIBER_LOOPBACK 0x4000 e1000_defines.h 1=Fiber loopback
28089
 M88E1000_EPSCR_DOWN_NO_IDLEM88E1000_EPSCR_DOWN_NO_IDLE 0x8000 e1000_defines.h 　
28090
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 e1000_defines.h 　
28091
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0000 e1000_defines.h 　
28092
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0400 e1000_defines.h 　
28093
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0800 e1000_defines.h 　
28094
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 e1000_defines.h 　
28095
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 e1000_defines.h 　
28096
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0000 e1000_defines.h 　
28097
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0100 e1000_defines.h 　
28098
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0200 e1000_defines.h 　
28099
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 e1000_defines.h 　
28100
 M88E1000_EPSCR_TX_CLK_2_5M88E1000_EPSCR_TX_CLK_2_5 0x0060 e1000_defines.h 2.5 MHz TX_CLK
28101
 M88E1000_EPSCR_TX_CLK_25M88E1000_EPSCR_TX_CLK_25 0x0070 e1000_defines.h 25 MHz TX_CLK
28102
 M88E1000_EPSCR_TX_CLK_0M88E1000_EPSCR_TX_CLK_0 0x0000 e1000_defines.h NO TX_CLK
28103
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 e1000_defines.h 　
28104
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0000 e1000_defines.h 　
28105
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0200 e1000_defines.h 　
28106
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0400 e1000_defines.h 　
28107
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0600 e1000_defines.h 　
28108
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0800 e1000_defines.h 　
28109
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0A00 e1000_defines.h 　
28110
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0C00 e1000_defines.h 　
28111
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 e1000_defines.h 　
28112
 GG82563_PAGE_SHIFTGG82563_PAGE_SHIFT 5 e1000_defines.h 　
28113
 GG82563_MIN_ALT_REGGG82563_MIN_ALT_REG 30 e1000_defines.h 　
28114
 GG82563_PHY_SPEC_CTRLGG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) e1000_defines.h PHY Specific Control
28115
 GG82563_PHY_SPEC_STATUSGG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) e1000_defines.h PHY Specific Status
28116
 GG82563_PHY_INT_ENABLEGG82563_PHY_INT_ENABLE GG82563_REG(0, 18) e1000_defines.h Interrupt Enable
28117
 GG82563_PHY_SPEC_STATUS_2GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) e1000_defines.h PHY Specific Status 2
28118
 GG82563_PHY_RX_ERR_CNTRGG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) e1000_defines.h Receive Error Counter
28119
 GG82563_PHY_PAGE_SELECTGG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) e1000_defines.h Page Select
28120
 GG82563_PHY_SPEC_CTRL_2GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) e1000_defines.h PHY Specific Control 2
28121
 GG82563_PHY_PAGE_SELECT_ALTGG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) e1000_defines.h Alternate Page Select
28122
 GG82563_PHY_TEST_CLK_CTRLGG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) e1000_defines.h Test Clock Control (use reg. 29 to select)
28123
 GG82563_PHY_MAC_SPEC_CTRLGG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) e1000_defines.h MAC Specific Control Register
28124
 GG82563_PHY_MAC_SPEC_CTRL_2GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) e1000_defines.h MAC Specific Control 2
28125
 GG82563_PHY_DSP_DISTANCEGG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) e1000_defines.h DSP Distance
28126
 GG82563_PHY_KMRN_MODE_CTRLGG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) e1000_defines.h Kumeran Mode Control
28127
 GG82563_PHY_PORT_RESETGG82563_PHY_PORT_RESET GG82563_REG(193, 17) e1000_defines.h Port Reset
28128
 GG82563_PHY_REVISION_IDGG82563_PHY_REVISION_ID GG82563_REG(193, 18) e1000_defines.h Revision ID
28129
 GG82563_PHY_DEVICE_IDGG82563_PHY_DEVICE_ID GG82563_REG(193, 19) e1000_defines.h Device ID
28130
 GG82563_PHY_PWR_MGMT_CTRLGG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) e1000_defines.h Power Management Control
28131
 GG82563_PHY_RATE_ADAPT_CTRLGG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) e1000_defines.h Rate Adaptation Control
28132
 GG82563_PHY_KMRN_FIFO_CTRL_STATGG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) e1000_defines.h FIFO's Control/Status
28133
 GG82563_PHY_KMRN_CTRLGG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) e1000_defines.h Control
28134
 GG82563_PHY_INBAND_CTRLGG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) e1000_defines.h Inband Control
28135
 GG82563_PHY_KMRN_DIAGNOSTICGG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) e1000_defines.h Diagnostic
28136
 GG82563_PHY_ACK_TIMEOUTSGG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) e1000_defines.h Acknowledge Timeouts
28137
 GG82563_PHY_ADV_ABILITYGG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) e1000_defines.h Advertised Ability
28138
 GG82563_PHY_LINK_PARTNER_ADV_ABGG82563_PHY_LINK_PARTNER_ADV_AB GG82563_REG(194, 23) e1000_defines.h Link Partner Advertised Ability
28139
 GG82563_PHY_ADV_NEXT_PAGEGG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) e1000_defines.h Advertised Next Page
28140
 GG82563_PHY_LINK_PARTNER_ADV_NEGG82563_PHY_LINK_PARTNER_ADV_NE GG82563_REG(194, 25) e1000_defines.h Link Partner Advertised Next page
28141
 GG82563_PHY_KMRN_MISCGG82563_PHY_KMRN_MISC GG82563_REG(194, 26) e1000_defines.h Misc.
28142
 E1000_MDIC_DATA_MASKE1000_MDIC_DATA_MASK 0x0000FFFF e1000_defines.h 　
28143
 E1000_MDIC_REG_MASKE1000_MDIC_REG_MASK 0x001F0000 e1000_defines.h 　
28144
 E1000_MDIC_REG_SHIFTE1000_MDIC_REG_SHIFT 16 e1000_defines.h 　
28145
 E1000_MDIC_PHY_MASKE1000_MDIC_PHY_MASK 0x03E00000 e1000_defines.h 　
28146
 E1000_MDIC_PHY_SHIFTE1000_MDIC_PHY_SHIFT 21 e1000_defines.h 　
28147
 E1000_MDIC_OP_WRITEE1000_MDIC_OP_WRITE 0x04000000 e1000_defines.h 　
28148
 E1000_MDIC_OP_READE1000_MDIC_OP_READ 0x08000000 e1000_defines.h 　
28149
 E1000_MDIC_READYE1000_MDIC_READY 0x10000000 e1000_defines.h 　
28150
 E1000_MDIC_INT_ENE1000_MDIC_INT_EN 0x20000000 e1000_defines.h 　
28151
 E1000_MDIC_ERRORE1000_MDIC_ERROR 0x40000000 e1000_defines.h 　
28152
 E1000_GEN_CTL_READYE1000_GEN_CTL_READY 0x80000000 e1000_defines.h 　
28153
 E1000_GEN_CTL_ADDRESS_SHIFTE1000_GEN_CTL_ADDRESS_SHIFT 8 e1000_defines.h 　
28154
 E1000_GEN_POLL_TIMEOUTE1000_GEN_POLL_TIMEOUT 640 e1000_defines.h 　
28155
 E1000_DEV_ID_82542E1000_DEV_ID_82542 0x1000 e1000_hw.h 　
28156
 E1000_DEV_ID_82543GC_FIBERE1000_DEV_ID_82543GC_FIBER 0x1001 e1000_hw.h 　
28157
 E1000_DEV_ID_82543GC_COPPERE1000_DEV_ID_82543GC_COPPER 0x1004 e1000_hw.h 　
28158
 E1000_DEV_ID_82544EI_COPPERE1000_DEV_ID_82544EI_COPPER 0x1008 e1000_hw.h 　
28159
 E1000_DEV_ID_82544EI_FIBERE1000_DEV_ID_82544EI_FIBER 0x1009 e1000_hw.h 　
28160
 E1000_DEV_ID_82544GC_COPPERE1000_DEV_ID_82544GC_COPPER 0x100C e1000_hw.h 　
28161
 E1000_DEV_ID_82544GC_LOME1000_DEV_ID_82544GC_LOM 0x100D e1000_hw.h 　
28162
 E1000_DEV_ID_82540EME1000_DEV_ID_82540EM 0x100E e1000_hw.h 　
28163
 E1000_DEV_ID_82540EM_LOME1000_DEV_ID_82540EM_LOM 0x1015 e1000_hw.h 　
28164
 E1000_DEV_ID_82540EP_LOME1000_DEV_ID_82540EP_LOM 0x1016 e1000_hw.h 　
28165
 E1000_DEV_ID_82540EPE1000_DEV_ID_82540EP 0x1017 e1000_hw.h 　
28166
 E1000_DEV_ID_82540EP_LPE1000_DEV_ID_82540EP_LP 0x101E e1000_hw.h 　
28167
 E1000_DEV_ID_82545EM_COPPERE1000_DEV_ID_82545EM_COPPER 0x100F e1000_hw.h 　
28168
 E1000_DEV_ID_82545EM_FIBERE1000_DEV_ID_82545EM_FIBER 0x1011 e1000_hw.h 　
28169
 E1000_DEV_ID_82545GM_COPPERE1000_DEV_ID_82545GM_COPPER 0x1026 e1000_hw.h 　
28170
 E1000_DEV_ID_82545GM_FIBERE1000_DEV_ID_82545GM_FIBER 0x1027 e1000_hw.h 　
28171
 E1000_DEV_ID_82545GM_SERDESE1000_DEV_ID_82545GM_SERDES 0x1028 e1000_hw.h 　
28172
 E1000_DEV_ID_82546EB_COPPERE1000_DEV_ID_82546EB_COPPER 0x1010 e1000_hw.h 　
28173
 E1000_DEV_ID_82546EB_FIBERE1000_DEV_ID_82546EB_FIBER 0x1012 e1000_hw.h 　
28174
 E1000_DEV_ID_82546EB_QUAD_COPPEE1000_DEV_ID_82546EB_QUAD_COPPE 0x101D e1000_hw.h 　
28175
 E1000_DEV_ID_82546GB_COPPERE1000_DEV_ID_82546GB_COPPER 0x1079 e1000_hw.h 　
28176
 E1000_DEV_ID_82546GB_FIBERE1000_DEV_ID_82546GB_FIBER 0x107A e1000_hw.h 　
28177
 E1000_DEV_ID_82546GB_SERDESE1000_DEV_ID_82546GB_SERDES 0x107B e1000_hw.h 　
28178
 E1000_DEV_ID_82546GB_PCIEE1000_DEV_ID_82546GB_PCIE 0x108A e1000_hw.h 　
28179
 E1000_DEV_ID_82546GB_QUAD_COPPEE1000_DEV_ID_82546GB_QUAD_COPPE 0x1099 e1000_hw.h 　
28180
 E1000_DEV_ID_82546GB_QUAD_COPPEE1000_DEV_ID_82546GB_QUAD_COPPE 0x10B5 e1000_hw.h 　
28181
 E1000_DEV_ID_82541EIE1000_DEV_ID_82541EI 0x1013 e1000_hw.h 　
28182
 E1000_DEV_ID_82541EI_MOBILEE1000_DEV_ID_82541EI_MOBILE 0x1018 e1000_hw.h 　
28183
 E1000_DEV_ID_82541ER_LOME1000_DEV_ID_82541ER_LOM 0x1014 e1000_hw.h 　
28184
 E1000_DEV_ID_82541ERE1000_DEV_ID_82541ER 0x1078 e1000_hw.h 　
28185
 E1000_DEV_ID_82541GIE1000_DEV_ID_82541GI 0x1076 e1000_hw.h 　
28186
 E1000_DEV_ID_82541GI_LFE1000_DEV_ID_82541GI_LF 0x107C e1000_hw.h 　
28187
 E1000_DEV_ID_82541GI_MOBILEE1000_DEV_ID_82541GI_MOBILE 0x1077 e1000_hw.h 　
28188
 E1000_DEV_ID_82547EIE1000_DEV_ID_82547EI 0x1019 e1000_hw.h 　
28189
 E1000_DEV_ID_82547EI_MOBILEE1000_DEV_ID_82547EI_MOBILE 0x101A e1000_hw.h 　
28190
 E1000_DEV_ID_82547GIE1000_DEV_ID_82547GI 0x1075 e1000_hw.h 　
28191
 E1000_REVISION_0E1000_REVISION_0 0 e1000_hw.h 　
28192
 E1000_REVISION_1E1000_REVISION_1 1 e1000_hw.h 　
28193
 E1000_REVISION_2E1000_REVISION_2 2 e1000_hw.h 　
28194
 E1000_REVISION_3E1000_REVISION_3 3 e1000_hw.h 　
28195
 E1000_REVISION_4E1000_REVISION_4 4 e1000_hw.h 　
28196
 E1000_FUNC_0E1000_FUNC_0 0 e1000_hw.h 　
28197
 E1000_FUNC_1E1000_FUNC_1 1 e1000_hw.h 　
28198
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 0 e1000_hw.h 　
28199
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 3 e1000_hw.h 　
28200
 MAX_PS_BUFFERSMAX_PS_BUFFERS 4 e1000_hw.h 　
28201
 E1000_HI_MAX_DATA_LENGTHE1000_HI_MAX_DATA_LENGTH 252 e1000_hw.h 　
28202
 E1000_HI_MAX_MNG_DATA_LENGTHE1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 e1000_hw.h 　
28203
 E1000_FACTPS_MNGCGE1000_FACTPS_MNGCG 0x20000000 e1000_manage.h 　
28204
 E1000_FWSM_MODE_MASKE1000_FWSM_MODE_MASK 0xE e1000_manage.h 　
28205
 E1000_FWSM_MODE_SHIFTE1000_FWSM_MODE_SHIFT 1 e1000_manage.h 　
28206
 E1000_MNG_IAMT_MODEE1000_MNG_IAMT_MODE 0x3 e1000_manage.h 　
28207
 E1000_MNG_DHCP_COOKIE_LENGTHE1000_MNG_DHCP_COOKIE_LENGTH 0x10 e1000_manage.h 　
28208
 E1000_MNG_DHCP_COOKIE_OFFSETE1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 e1000_manage.h 　
28209
 E1000_MNG_DHCP_COMMAND_TIMEOUTE1000_MNG_DHCP_COMMAND_TIMEOUT 10 e1000_manage.h 　
28210
 E1000_MNG_DHCP_TX_PAYLOAD_CMDE1000_MNG_DHCP_TX_PAYLOAD_CMD 64 e1000_manage.h 　
28211
 E1000_MNG_DHCP_COOKIE_STATUS_PAE1000_MNG_DHCP_COOKIE_STATUS_PA 0x1 e1000_manage.h 　
28212
 E1000_MNG_DHCP_COOKIE_STATUS_VLE1000_MNG_DHCP_COOKIE_STATUS_VL 0x2 e1000_manage.h 　
28213
 E1000_VFTA_ENTRY_SHIFTE1000_VFTA_ENTRY_SHIFT 5 e1000_manage.h 　
28214
 E1000_VFTA_ENTRY_MASKE1000_VFTA_ENTRY_MASK 0x7F e1000_manage.h 　
28215
 E1000_VFTA_ENTRY_BIT_SHIFT_MASKE1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F e1000_manage.h 　
28216
 E1000_HI_MAX_BLOCK_BYTE_LENGTHE1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 e1000_manage.h Num of bytes in range
28217
 E1000_HI_MAX_BLOCK_DWORD_LENGTHE1000_HI_MAX_BLOCK_DWORD_LENGTH 448 e1000_manage.h Num of dwords in range
28218
 E1000_HI_COMMAND_TIMEOUTE1000_HI_COMMAND_TIMEOUT 500 e1000_manage.h Process HI command limit
28219
 E1000_HICR_ENE1000_HICR_EN 0x01 e1000_manage.h Enable bit - RO
28220
 E1000_HICR_CE1000_HICR_C 0x02 e1000_manage.h 　
28221
 E1000_HICR_SVE1000_HICR_SV 0x04 e1000_manage.h Status Validity
28222
 E1000_HICR_FW_RESET_ENABLEE1000_HICR_FW_RESET_ENABLE 0x40 e1000_manage.h 　
28223
 E1000_HICR_FW_RESETE1000_HICR_FW_RESET 0x80 e1000_manage.h 　
28224
 E1000_IAMT_SIGNATUREE1000_IAMT_SIGNATURE 0x544D4149 e1000_manage.h 　
28225
 E1000_STM_OPCODEE1000_STM_OPCODE 0xDB00 e1000_nvm.h 　
28226
 u8u8 unsigned char e1000_osdep.h 　
28227
 boolbool boolean_t e1000_osdep.h 　
28228
 dma_addr_tdma_addr_t unsigned long e1000_osdep.h 　
28229
 __le16__le16 uint16_t e1000_osdep.h 　
28230
 __le32__le32 uint32_t e1000_osdep.h 　
28231
 __le64__le64 uint64_t e1000_osdep.h 　
28232
 ETH_FCS_LENETH_FCS_LEN 4 e1000_osdep.h 　
28233
 PCI_COMMAND_REGISTERPCI_COMMAND_REGISTER PCI_COMMAND e1000_osdep.h 　
28234
 CMD_MEM_WRT_INVALIDATECMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE e1000_osdep.h 　
28235
 ETH_ADDR_LENETH_ADDR_LEN ETH_ALEN e1000_osdep.h 　
28236
 DEBUGOUT2DEBUGOUT2 DEBUGOUT1 e1000_osdep.h 　
28237
 DEBUGOUT3DEBUGOUT3 DEBUGOUT2 e1000_osdep.h 　
28238
 DEBUGOUT7DEBUGOUT7 DEBUGOUT3 e1000_osdep.h 　
28239
 E1000_READ_REG_ARRAY_DWORDE1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY e1000_osdep.h 　
28240
 E1000_WRITE_REG_ARRAY_DWORDE1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY e1000_osdep.h 　
28241
 E1000_MAX_PHY_ADDRE1000_MAX_PHY_ADDR 4 e1000_phy.h 　
28242
 IGP01E1000_PHY_PORT_CONFIGIGP01E1000_PHY_PORT_CONFIG 0x10 e1000_phy.h Port Config
28243
 IGP01E1000_PHY_PORT_STATUSIGP01E1000_PHY_PORT_STATUS 0x11 e1000_phy.h Status
28244
 IGP01E1000_PHY_PORT_CTRLIGP01E1000_PHY_PORT_CTRL 0x12 e1000_phy.h Control
28245
 IGP01E1000_PHY_LINK_HEALTHIGP01E1000_PHY_LINK_HEALTH 0x13 e1000_phy.h PHY Link Health
28246
 IGP01E1000_GMII_FIFOIGP01E1000_GMII_FIFO 0x14 e1000_phy.h GMII FIFO
28247
 IGP01E1000_PHY_CHANNEL_QUALITYIGP01E1000_PHY_CHANNEL_QUALITY 0x15 e1000_phy.h PHY Channel Quality
28248
 IGP02E1000_PHY_POWER_MGMTIGP02E1000_PHY_POWER_MGMT 0x19 e1000_phy.h Power Management
28249
 IGP01E1000_PHY_PAGE_SELECTIGP01E1000_PHY_PAGE_SELECT 0x1F e1000_phy.h Page Select
28250
 BM_PHY_PAGE_SELECTBM_PHY_PAGE_SELECT 22 e1000_phy.h Page Select for BM
28251
 IGP_PAGE_SHIFTIGP_PAGE_SHIFT 5 e1000_phy.h 　
28252
 PHY_REG_MASKPHY_REG_MASK 0x1F e1000_phy.h 　
28253
 IGP01E1000_PHY_PCS_INIT_REGIGP01E1000_PHY_PCS_INIT_REG 0x00B4 e1000_phy.h 　
28254
 IGP01E1000_PHY_POLARITY_MASKIGP01E1000_PHY_POLARITY_MASK 0x0078 e1000_phy.h 　
28255
 IGP01E1000_PSCR_AUTO_MDIXIGP01E1000_PSCR_AUTO_MDIX 0x1000 e1000_phy.h 　
28256
 IGP01E1000_PSCR_FORCE_MDI_MDIXIGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 e1000_phy.h 0=MDI, 1=MDIX
28257
 IGP01E1000_PSCFR_SMART_SPEEDIGP01E1000_PSCFR_SMART_SPEED 0x0080 e1000_phy.h 　
28258
 IGP01E1000_GMII_FLEX_SPDIGP01E1000_GMII_FLEX_SPD 0x0010 e1000_phy.h 　
28259
 IGP01E1000_GMII_SPDIGP01E1000_GMII_SPD 0x0020 e1000_phy.h Enable SPD
28260
 IGP02E1000_PM_SPDIGP02E1000_PM_SPD 0x0001 e1000_phy.h Smart Power Down
28261
 IGP02E1000_PM_D0_LPLUIGP02E1000_PM_D0_LPLU 0x0002 e1000_phy.h For D0a states
28262
 IGP02E1000_PM_D3_LPLUIGP02E1000_PM_D3_LPLU 0x0004 e1000_phy.h For all other states
28263
 IGP01E1000_PLHR_SS_DOWNGRADEIGP01E1000_PLHR_SS_DOWNGRADE 0x8000 e1000_phy.h 　
28264
 IGP01E1000_PSSR_POLARITY_REVERSIGP01E1000_PSSR_POLARITY_REVERS 0x0002 e1000_phy.h 　
28265
 IGP01E1000_PSSR_MDIXIGP01E1000_PSSR_MDIX 0x0800 e1000_phy.h 　
28266
 IGP01E1000_PSSR_SPEED_MASKIGP01E1000_PSSR_SPEED_MASK 0xC000 e1000_phy.h 　
28267
 IGP01E1000_PSSR_SPEED_1000MBPSIGP01E1000_PSSR_SPEED_1000MBPS 0xC000 e1000_phy.h 　
28268
 IGP02E1000_PHY_CHANNEL_NUMIGP02E1000_PHY_CHANNEL_NUM 4 e1000_phy.h 　
28269
 IGP02E1000_PHY_AGC_AIGP02E1000_PHY_AGC_A 0x11B1 e1000_phy.h 　
28270
 IGP02E1000_PHY_AGC_BIGP02E1000_PHY_AGC_B 0x12B1 e1000_phy.h 　
28271
 IGP02E1000_PHY_AGC_CIGP02E1000_PHY_AGC_C 0x14B1 e1000_phy.h 　
28272
 IGP02E1000_PHY_AGC_DIGP02E1000_PHY_AGC_D 0x18B1 e1000_phy.h 　
28273
 IGP02E1000_AGC_LENGTH_SHIFTIGP02E1000_AGC_LENGTH_SHIFT 9 e1000_phy.h Course - 15:13, Fine - 12:9
28274
 IGP02E1000_AGC_LENGTH_MASKIGP02E1000_AGC_LENGTH_MASK 0x7F e1000_phy.h 　
28275
 IGP02E1000_AGC_RANGEIGP02E1000_AGC_RANGE 15 e1000_phy.h 　
28276
 IGP03E1000_PHY_MISC_CTRLIGP03E1000_PHY_MISC_CTRL 0x1B e1000_phy.h 　
28277
 IGP03E1000_PHY_MISC_DUPLEX_MANUIGP03E1000_PHY_MISC_DUPLEX_MANU 0x1000 e1000_phy.h Manually Set Duplex
28278
 E1000_CABLE_LENGTH_UNDEFINEDE1000_CABLE_LENGTH_UNDEFINED 0xFF e1000_phy.h 　
28279
 E1000_KMRNCTRLSTA_OFFSETE1000_KMRNCTRLSTA_OFFSET 0x001F0000 e1000_phy.h 　
28280
 E1000_KMRNCTRLSTA_OFFSET_SHIFTE1000_KMRNCTRLSTA_OFFSET_SHIFT 16 e1000_phy.h 　
28281
 E1000_KMRNCTRLSTA_RENE1000_KMRNCTRLSTA_REN 0x00200000 e1000_phy.h 　
28282
 E1000_KMRNCTRLSTA_DIAG_OFFSETE1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 e1000_phy.h Kumeran Diagnostic
28283
 E1000_KMRNCTRLSTA_TIMEOUTSE1000_KMRNCTRLSTA_TIMEOUTS 0x4 e1000_phy.h Kumeran Timeouts
28284
 E1000_KMRNCTRLSTA_INBAND_PARAME1000_KMRNCTRLSTA_INBAND_PARAM 0x9 e1000_phy.h Kumeran InBand Parameters
28285
 E1000_KMRNCTRLSTA_DIAG_NELPBKE1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 e1000_phy.h Nearend Loopback mode
28286
 IFE_PHY_EXTENDED_STATUS_CONTROLIFE_PHY_EXTENDED_STATUS_CONTROL 0x10 e1000_phy.h 　
28287
 IFE_PHY_SPECIAL_CONTROLIFE_PHY_SPECIAL_CONTROL 0x11 e1000_phy.h 100BaseTx PHY Special Control
28288
 IFE_PHY_SPECIAL_CONTROL_LEDIFE_PHY_SPECIAL_CONTROL_LED 0x1B e1000_phy.h PHY Special and LED Control
28289
 IFE_PHY_MDIX_CONTROLIFE_PHY_MDIX_CONTROL 0x1C e1000_phy.h MDI/MDI-X Control
28290
 IFE_PESC_POLARITY_REVERSEDIFE_PESC_POLARITY_REVERSED 0x0100 e1000_phy.h 　
28291
 IFE_PSC_AUTO_POLARITY_DISABLEIFE_PSC_AUTO_POLARITY_DISABLE 0x0010 e1000_phy.h 　
28292
 IFE_PSC_FORCE_POLARITYIFE_PSC_FORCE_POLARITY 0x0020 e1000_phy.h 　
28293
 IFE_PSC_DISABLE_DYNAMIC_POWER_DIFE_PSC_DISABLE_DYNAMIC_POWER_D 0x0100 e1000_phy.h 　
28294
 IFE_PSCL_PROBE_MODEIFE_PSCL_PROBE_MODE 0x0020 e1000_phy.h 　
28295
 IFE_PSCL_PROBE_LEDS_OFFIFE_PSCL_PROBE_LEDS_OFF 0x0006 e1000_phy.h Force LEDs 0 and 2 off
28296
 IFE_PSCL_PROBE_LEDS_ONIFE_PSCL_PROBE_LEDS_ON 0x0007 e1000_phy.h Force LEDs 0 and 2 on
28297
 IFE_PMC_MDIX_STATUSIFE_PMC_MDIX_STATUS 0x0020 e1000_phy.h 1=MDI-X, 0=MDI
28298
 IFE_PMC_FORCE_MDIXIFE_PMC_FORCE_MDIX 0x0040 e1000_phy.h 1=force MDI-X, 0=force MDI
28299
 IFE_PMC_AUTO_MDIXIFE_PMC_AUTO_MDIX 0x0080 e1000_phy.h 1=enable auto MDI/MDI-X, 0=disable
28300
 E1000_CTRLE1000_CTRL 0x00000 e1000_regs.h Device Control - RW
28301
 E1000_CTRL_DUPE1000_CTRL_DUP 0x00004 e1000_regs.h Device Control Duplicate (Shadow) - RW
28302
 E1000_STATUSE1000_STATUS 0x00008 e1000_regs.h Device Status - RO
28303
 E1000_EECDE1000_EECD 0x00010 e1000_regs.h EEPROM/Flash Control - RW
28304
 E1000_EERDE1000_EERD 0x00014 e1000_regs.h EEPROM Read - RW
28305
 E1000_CTRL_EXTE1000_CTRL_EXT 0x00018 e1000_regs.h Extended Device Control - RW
28306
 E1000_FLAE1000_FLA 0x0001C e1000_regs.h Flash Access - RW
28307
 E1000_MDICE1000_MDIC 0x00020 e1000_regs.h MDI Control - RW
28308
 E1000_SCTLE1000_SCTL 0x00024 e1000_regs.h SerDes Control - RW
28309
 E1000_FCALE1000_FCAL 0x00028 e1000_regs.h Flow Control Address Low - RW
28310
 E1000_FCAHE1000_FCAH 0x0002C e1000_regs.h Flow Control Address High -RW
28311
 E1000_FEXTE1000_FEXT 0x0002C e1000_regs.h Future Extended - RW
28312
 E1000_FEXTNVME1000_FEXTNVM 0x00028 e1000_regs.h Future Extended NVM - RW
28313
 E1000_FCTE1000_FCT 0x00030 e1000_regs.h Flow Control Type - RW
28314
 E1000_CONNSWE1000_CONNSW 0x00034 e1000_regs.h Copper/Fiber switch control - RW
28315
 E1000_VETE1000_VET 0x00038 e1000_regs.h VLAN Ether Type - RW
28316
 E1000_ICRE1000_ICR 0x000C0 e1000_regs.h Interrupt Cause Read - R/clr
28317
 E1000_ITRE1000_ITR 0x000C4 e1000_regs.h Interrupt Throttling Rate - RW
28318
 E1000_ICSE1000_ICS 0x000C8 e1000_regs.h Interrupt Cause Set - WO
28319
 E1000_IMSE1000_IMS 0x000D0 e1000_regs.h Interrupt Mask Set - RW
28320
 E1000_IMCE1000_IMC 0x000D8 e1000_regs.h Interrupt Mask Clear - WO
28321
 E1000_IAME1000_IAM 0x000E0 e1000_regs.h Interrupt Acknowledge Auto Mask
28322
 E1000_RCTLE1000_RCTL 0x00100 e1000_regs.h Rx Control - RW
28323
 E1000_FCTTVE1000_FCTTV 0x00170 e1000_regs.h Flow Control Transmit Timer Value - RW
28324
 E1000_TXCWE1000_TXCW 0x00178 e1000_regs.h Tx Configuration Word - RW
28325
 E1000_RXCWE1000_RXCW 0x00180 e1000_regs.h Rx Configuration Word - RO
28326
 E1000_TCTLE1000_TCTL 0x00400 e1000_regs.h Tx Control - RW
28327
 E1000_TCTL_EXTE1000_TCTL_EXT 0x00404 e1000_regs.h Extended Tx Control - RW
28328
 E1000_TIPGE1000_TIPG 0x00410 e1000_regs.h Tx Inter-packet gap -RW
28329
 E1000_TBTE1000_TBT 0x00448 e1000_regs.h Tx Burst Timer - RW
28330
 E1000_AITE1000_AIT 0x00458 e1000_regs.h Adaptive Interframe Spacing Throttle - RW
28331
 E1000_LEDCTLE1000_LEDCTL 0x00E00 e1000_regs.h LED Control - RW
28332
 E1000_EXTCNF_CTRLE1000_EXTCNF_CTRL 0x00F00 e1000_regs.h Extended Configuration Control
28333
 E1000_EXTCNF_SIZEE1000_EXTCNF_SIZE 0x00F08 e1000_regs.h Extended Configuration Size
28334
 E1000_PHY_CTRLE1000_PHY_CTRL 0x00F10 e1000_regs.h PHY Control Register in CSR
28335
 E1000_PBAE1000_PBA 0x01000 e1000_regs.h Packet Buffer Allocation - RW
28336
 E1000_PBSE1000_PBS 0x01008 e1000_regs.h Packet Buffer Size
28337
 E1000_EEMNGCTLE1000_EEMNGCTL 0x01010 e1000_regs.h MNG EEprom Control
28338
 E1000_EEARBCE1000_EEARBC 0x01024 e1000_regs.h EEPROM Auto Read Bus Control
28339
 E1000_FLASHTE1000_FLASHT 0x01028 e1000_regs.h FLASH Timer Register
28340
 E1000_EEWRE1000_EEWR 0x0102C e1000_regs.h EEPROM Write Register - RW
28341
 E1000_FLSWCTLE1000_FLSWCTL 0x01030 e1000_regs.h FLASH control register
28342
 E1000_FLSWDATAE1000_FLSWDATA 0x01034 e1000_regs.h FLASH data register
28343
 E1000_FLSWCNTE1000_FLSWCNT 0x01038 e1000_regs.h FLASH Access Counter
28344
 E1000_FLOPE1000_FLOP 0x0103C e1000_regs.h FLASH Opcode Register
28345
 E1000_I2CCMDE1000_I2CCMD 0x01028 e1000_regs.h SFPI2C Command Register - RW
28346
 E1000_I2CPARAMSE1000_I2CPARAMS 0x0102C e1000_regs.h SFPI2C Parameters Register - RW
28347
 E1000_WDSTPE1000_WDSTP 0x01040 e1000_regs.h Watchdog Setup - RW
28348
 E1000_SWDSTSE1000_SWDSTS 0x01044 e1000_regs.h SW Device Status - RW
28349
 E1000_FRTIMERE1000_FRTIMER 0x01048 e1000_regs.h Free Running Timer - RW
28350
 E1000_ERTE1000_ERT 0x02008 e1000_regs.h Early Rx Threshold - RW
28351
 E1000_FCRTLE1000_FCRTL 0x02160 e1000_regs.h Flow Control Receive Threshold Low - RW
28352
 E1000_FCRTHE1000_FCRTH 0x02168 e1000_regs.h Flow Control Receive Threshold High - RW
28353
 E1000_PSRCTLE1000_PSRCTL 0x02170 e1000_regs.h Packet Split Receive Control - RW
28354
 E1000_PBRTHE1000_PBRTH 0x02458 e1000_regs.h PB Rx Arbitration Threshold - RW
28355
 E1000_FCRTVE1000_FCRTV 0x02460 e1000_regs.h Flow Control Refresh Timer Value - RW
28356
 E1000_RDPUMBE1000_RDPUMB 0x025CC e1000_regs.h DMA Rx Descriptor uC Mailbox - RW
28357
 E1000_RDPUADE1000_RDPUAD 0x025D0 e1000_regs.h DMA Rx Descriptor uC Addr Command - RW
28358
 E1000_RDPUWDE1000_RDPUWD 0x025D4 e1000_regs.h DMA Rx Descriptor uC Data Write - RW
28359
 E1000_RDPURDE1000_RDPURD 0x025D8 e1000_regs.h DMA Rx Descriptor uC Data Read - RW
28360
 E1000_RDPUCTLE1000_RDPUCTL 0x025DC e1000_regs.h DMA Rx Descriptor uC Control - RW
28361
 E1000_RDTRE1000_RDTR 0x02820 e1000_regs.h Rx Delay Timer - RW
28362
 E1000_RADVE1000_RADV 0x0282C e1000_regs.h Rx Interrupt Absolute Delay Timer - RW
28363
 E1000_RSRPDE1000_RSRPD 0x02C00 e1000_regs.h Rx Small Packet Detect - RW
28364
 E1000_RAIDE1000_RAID 0x02C08 e1000_regs.h Receive Ack Interrupt Delay - RW
28365
 E1000_TXDMACE1000_TXDMAC 0x03000 e1000_regs.h Tx DMA Control - RW
28366
 E1000_KABGTXDE1000_KABGTXD 0x03004 e1000_regs.h AFE Band Gap Transmit Ref Data
28367
 E1000_TDFHE1000_TDFH 0x03410 e1000_regs.h Tx Data FIFO Head - RW
28368
 E1000_TDFTE1000_TDFT 0x03418 e1000_regs.h Tx Data FIFO Tail - RW
28369
 E1000_TDFHSE1000_TDFHS 0x03420 e1000_regs.h Tx Data FIFO Head Saved - RW
28370
 E1000_TDFTSE1000_TDFTS 0x03428 e1000_regs.h Tx Data FIFO Tail Saved - RW
28371
 E1000_TDFPCE1000_TDFPC 0x03430 e1000_regs.h Tx Data FIFO Packet Count - RW
28372
 E1000_TDPUMBE1000_TDPUMB 0x0357C e1000_regs.h DMA Tx Descriptor uC Mail Box - RW
28373
 E1000_TDPUADE1000_TDPUAD 0x03580 e1000_regs.h DMA Tx Descriptor uC Addr Command - RW
28374
 E1000_TDPUWDE1000_TDPUWD 0x03584 e1000_regs.h DMA Tx Descriptor uC Data Write - RW
28375
 E1000_TDPURDE1000_TDPURD 0x03588 e1000_regs.h DMA Tx Descriptor uC Data Read - RW
28376
 E1000_TDPUCTLE1000_TDPUCTL 0x0358C e1000_regs.h DMA Tx Descriptor uC Control - RW
28377
 E1000_DTXCTLE1000_DTXCTL 0x03590 e1000_regs.h DMA Tx Control - RW
28378
 E1000_TIDVE1000_TIDV 0x03820 e1000_regs.h Tx Interrupt Delay Value - RW
28379
 E1000_TADVE1000_TADV 0x0382C e1000_regs.h Tx Interrupt Absolute Delay Val - RW
28380
 E1000_TSPMTE1000_TSPMT 0x03830 e1000_regs.h TCP Segmentation PAD & Min Threshold - RW
28381
 E1000_CRCERRSE1000_CRCERRS 0x04000 e1000_regs.h CRC Error Count - R/clr
28382
 E1000_ALGNERRCE1000_ALGNERRC 0x04004 e1000_regs.h Alignment Error Count - R/clr
28383
 E1000_SYMERRSE1000_SYMERRS 0x04008 e1000_regs.h Symbol Error Count - R/clr
28384
 E1000_RXERRCE1000_RXERRC 0x0400C e1000_regs.h Receive Error Count - R/clr
28385
 E1000_MPCE1000_MPC 0x04010 e1000_regs.h Missed Packet Count - R/clr
28386
 E1000_SCCE1000_SCC 0x04014 e1000_regs.h Single Collision Count - R/clr
28387
 E1000_ECOLE1000_ECOL 0x04018 e1000_regs.h Excessive Collision Count - R/clr
28388
 E1000_MCCE1000_MCC 0x0401C e1000_regs.h Multiple Collision Count - R/clr
28389
 E1000_LATECOLE1000_LATECOL 0x04020 e1000_regs.h Late Collision Count - R/clr
28390
 E1000_COLCE1000_COLC 0x04028 e1000_regs.h Collision Count - R/clr
28391
 E1000_DCE1000_DC 0x04030 e1000_regs.h Defer Count - R/clr
28392
 E1000_TNCRSE1000_TNCRS 0x04034 e1000_regs.h Tx-No CRS - R/clr
28393
 E1000_SECE1000_SEC 0x04038 e1000_regs.h Sequence Error Count - R/clr
28394
 E1000_CEXTERRE1000_CEXTERR 0x0403C e1000_regs.h Carrier Extension Error Count - R/clr
28395
 E1000_RLECE1000_RLEC 0x04040 e1000_regs.h Receive Length Error Count - R/clr
28396
 E1000_XONRXCE1000_XONRXC 0x04048 e1000_regs.h XON Rx Count - R/clr
28397
 E1000_XONTXCE1000_XONTXC 0x0404C e1000_regs.h XON Tx Count - R/clr
28398
 E1000_XOFFRXCE1000_XOFFRXC 0x04050 e1000_regs.h XOFF Rx Count - R/clr
28399
 E1000_XOFFTXCE1000_XOFFTXC 0x04054 e1000_regs.h XOFF Tx Count - R/clr
28400
 E1000_FCRUCE1000_FCRUC 0x04058 e1000_regs.h Flow Control Rx Unsupported Count- R/clr
28401
 E1000_PRC64E1000_PRC64 0x0405C e1000_regs.h Packets Rx (64 bytes) - R/clr
28402
 E1000_PRC127E1000_PRC127 0x04060 e1000_regs.h Packets Rx (65-127 bytes) - R/clr
28403
 E1000_PRC255E1000_PRC255 0x04064 e1000_regs.h Packets Rx (128-255 bytes) - R/clr
28404
 E1000_PRC511E1000_PRC511 0x04068 e1000_regs.h Packets Rx (255-511 bytes) - R/clr
28405
 E1000_PRC1023E1000_PRC1023 0x0406C e1000_regs.h Packets Rx (512-1023 bytes) - R/clr
28406
 E1000_PRC1522E1000_PRC1522 0x04070 e1000_regs.h Packets Rx (1024-1522 bytes) - R/clr
28407
 E1000_GPRCE1000_GPRC 0x04074 e1000_regs.h Good Packets Rx Count - R/clr
28408
 E1000_BPRCE1000_BPRC 0x04078 e1000_regs.h Broadcast Packets Rx Count - R/clr
28409
 E1000_MPRCE1000_MPRC 0x0407C e1000_regs.h Multicast Packets Rx Count - R/clr
28410
 E1000_GPTCE1000_GPTC 0x04080 e1000_regs.h Good Packets Tx Count - R/clr
28411
 E1000_GORCLE1000_GORCL 0x04088 e1000_regs.h Good Octets Rx Count Low - R/clr
28412
 E1000_GORCHE1000_GORCH 0x0408C e1000_regs.h Good Octets Rx Count High - R/clr
28413
 E1000_GOTCLE1000_GOTCL 0x04090 e1000_regs.h Good Octets Tx Count Low - R/clr
28414
 E1000_GOTCHE1000_GOTCH 0x04094 e1000_regs.h Good Octets Tx Count High - R/clr
28415
 E1000_RNBCE1000_RNBC 0x040A0 e1000_regs.h Rx No Buffers Count - R/clr
28416
 E1000_RUCE1000_RUC 0x040A4 e1000_regs.h Rx Undersize Count - R/clr
28417
 E1000_RFCE1000_RFC 0x040A8 e1000_regs.h Rx Fragment Count - R/clr
28418
 E1000_ROCE1000_ROC 0x040AC e1000_regs.h Rx Oversize Count - R/clr
28419
 E1000_RJCE1000_RJC 0x040B0 e1000_regs.h Rx Jabber Count - R/clr
28420
 E1000_MGTPRCE1000_MGTPRC 0x040B4 e1000_regs.h Management Packets Rx Count - R/clr
28421
 E1000_MGTPDCE1000_MGTPDC 0x040B8 e1000_regs.h Management Packets Dropped Count - R/clr
28422
 E1000_MGTPTCE1000_MGTPTC 0x040BC e1000_regs.h Management Packets Tx Count - R/clr
28423
 E1000_TORLE1000_TORL 0x040C0 e1000_regs.h Total Octets Rx Low - R/clr
28424
 E1000_TORHE1000_TORH 0x040C4 e1000_regs.h Total Octets Rx High - R/clr
28425
 E1000_TOTLE1000_TOTL 0x040C8 e1000_regs.h Total Octets Tx Low - R/clr
28426
 E1000_TOTHE1000_TOTH 0x040CC e1000_regs.h Total Octets Tx High - R/clr
28427
 E1000_TPRE1000_TPR 0x040D0 e1000_regs.h Total Packets Rx - R/clr
28428
 E1000_TPTE1000_TPT 0x040D4 e1000_regs.h Total Packets Tx - R/clr
28429
 E1000_PTC64E1000_PTC64 0x040D8 e1000_regs.h Packets Tx (64 bytes) - R/clr
28430
 E1000_PTC127E1000_PTC127 0x040DC e1000_regs.h Packets Tx (65-127 bytes) - R/clr
28431
 E1000_PTC255E1000_PTC255 0x040E0 e1000_regs.h Packets Tx (128-255 bytes) - R/clr
28432
 E1000_PTC511E1000_PTC511 0x040E4 e1000_regs.h Packets Tx (256-511 bytes) - R/clr
28433
 E1000_PTC1023E1000_PTC1023 0x040E8 e1000_regs.h Packets Tx (512-1023 bytes) - R/clr
28434
 E1000_PTC1522E1000_PTC1522 0x040EC e1000_regs.h Packets Tx (1024-1522 Bytes) - R/clr
28435
 E1000_MPTCE1000_MPTC 0x040F0 e1000_regs.h Multicast Packets Tx Count - R/clr
28436
 E1000_BPTCE1000_BPTC 0x040F4 e1000_regs.h Broadcast Packets Tx Count - R/clr
28437
 E1000_TSCTCE1000_TSCTC 0x040F8 e1000_regs.h TCP Segmentation Context Tx - R/clr
28438
 E1000_TSCTFCE1000_TSCTFC 0x040FC e1000_regs.h TCP Segmentation Context Tx Fail - R/clr
28439
 E1000_IACE1000_IAC 0x04100 e1000_regs.h Interrupt Assertion Count
28440
 E1000_ICRXPTCE1000_ICRXPTC 0x04104 e1000_regs.h Interrupt Cause Rx Pkt Timer Expire Count
28441
 E1000_ICRXATCE1000_ICRXATC 0x04108 e1000_regs.h Interrupt Cause Rx Abs Timer Expire Count
28442
 E1000_ICTXPTCE1000_ICTXPTC 0x0410C e1000_regs.h Interrupt Cause Tx Pkt Timer Expire Count
28443
 E1000_ICTXATCE1000_ICTXATC 0x04110 e1000_regs.h Interrupt Cause Tx Abs Timer Expire Count
28444
 E1000_ICTXQECE1000_ICTXQEC 0x04118 e1000_regs.h Interrupt Cause Tx Queue Empty Count
28445
 E1000_ICTXQMTCE1000_ICTXQMTC 0x0411C e1000_regs.h Interrupt Cause Tx Queue Min Thresh Count
28446
 E1000_ICRXDMTCE1000_ICRXDMTC 0x04120 e1000_regs.h Interrupt Cause Rx Desc Min Thresh Count
28447
 E1000_ICRXOCE1000_ICRXOC 0x04124 e1000_regs.h Interrupt Cause Receiver Overrun Count
28448
 E1000_PCS_CFG0E1000_PCS_CFG0 0x04200 e1000_regs.h PCS Configuration 0 - RW
28449
 E1000_PCS_LCTLE1000_PCS_LCTL 0x04208 e1000_regs.h PCS Link Control - RW
28450
 E1000_PCS_LSTATE1000_PCS_LSTAT 0x0420C e1000_regs.h PCS Link Status - RO
28451
 E1000_CBTMPCE1000_CBTMPC 0x0402C e1000_regs.h Circuit Breaker Tx Packet Count
28452
 E1000_HTDPMCE1000_HTDPMC 0x0403C e1000_regs.h Host Transmit Discarded Packets
28453
 E1000_CBRDPCE1000_CBRDPC 0x04044 e1000_regs.h Circuit Breaker Rx Dropped Count
28454
 E1000_CBRMPCE1000_CBRMPC 0x040FC e1000_regs.h Circuit Breaker Rx Packet Count
28455
 E1000_RPTHCE1000_RPTHC 0x04104 e1000_regs.h Rx Packets To Host
28456
 E1000_HGPTCE1000_HGPTC 0x04118 e1000_regs.h Host Good Packets Tx Count
28457
 E1000_HTCBDPCE1000_HTCBDPC 0x04124 e1000_regs.h Host Tx Circuit Breaker Dropped Count
28458
 E1000_HGORCLE1000_HGORCL 0x04128 e1000_regs.h Host Good Octets Received Count Low
28459
 E1000_HGORCHE1000_HGORCH 0x0412C e1000_regs.h Host Good Octets Received Count High
28460
 E1000_HGOTCLE1000_HGOTCL 0x04130 e1000_regs.h Host Good Octets Transmit Count Low
28461
 E1000_HGOTCHE1000_HGOTCH 0x04134 e1000_regs.h Host Good Octets Transmit Count High
28462
 E1000_LENERRSE1000_LENERRS 0x04138 e1000_regs.h Length Errors Count
28463
 E1000_SCVPCE1000_SCVPC 0x04228 e1000_regs.h SerDes/SGMII Code Violation Pkt Count
28464
 E1000_HRMPCE1000_HRMPC 0x0A018 e1000_regs.h Header Redirection Missed Packet Count
28465
 E1000_PCS_ANADVE1000_PCS_ANADV 0x04218 e1000_regs.h AN advertisement - RW
28466
 E1000_PCS_LPABE1000_PCS_LPAB 0x0421C e1000_regs.h Link Partner Ability - RW
28467
 E1000_PCS_NPTXE1000_PCS_NPTX 0x04220 e1000_regs.h AN Next Page Transmit - RW
28468
 E1000_PCS_LPABNPE1000_PCS_LPABNP 0x04224 e1000_regs.h Link Partner Ability Next Page - RW
28469
 E1000_1GSTAT_RCVE1000_1GSTAT_RCV 0x04228 e1000_regs.h 1GSTAT Code Violation Packet Count - RW
28470
 E1000_RXCSUME1000_RXCSUM 0x05000 e1000_regs.h Rx Checksum Control - RW
28471
 E1000_RLPMLE1000_RLPML 0x05004 e1000_regs.h Rx Long Packet Max Length
28472
 E1000_RFCTLE1000_RFCTL 0x05008 e1000_regs.h Receive Filter Control
28473
 E1000_MTAE1000_MTA 0x05200 e1000_regs.h Multicast Table Array - RW Array
28474
 E1000_RAE1000_RA 0x05400 e1000_regs.h Receive Address - RW Array
28475
 E1000_VFTAE1000_VFTA 0x05600 e1000_regs.h VLAN Filter Table Array - RW Array
28476
 E1000_VT_CTLE1000_VT_CTL 0x0581C e1000_regs.h VMDq Control - RW
28477
 E1000_VFQA0E1000_VFQA0 0x0B000 e1000_regs.h VLAN Filter Queue Array 0 - RW Array
28478
 E1000_VFQA1E1000_VFQA1 0x0B200 e1000_regs.h VLAN Filter Queue Array 1 - RW Array
28479
 E1000_WUCE1000_WUC 0x05800 e1000_regs.h Wakeup Control - RW
28480
 E1000_WUFCE1000_WUFC 0x05808 e1000_regs.h Wakeup Filter Control - RW
28481
 E1000_WUSE1000_WUS 0x05810 e1000_regs.h Wakeup Status - RO
28482
 E1000_MANCE1000_MANC 0x05820 e1000_regs.h Management Control - RW
28483
 E1000_IPAVE1000_IPAV 0x05838 e1000_regs.h IP Address Valid - RW
28484
 E1000_IP4ATE1000_IP4AT 0x05840 e1000_regs.h IPv4 Address Table - RW Array
28485
 E1000_IP6ATE1000_IP6AT 0x05880 e1000_regs.h IPv6 Address Table - RW Array
28486
 E1000_WUPLE1000_WUPL 0x05900 e1000_regs.h Wakeup Packet Length - RW
28487
 E1000_WUPME1000_WUPM 0x05A00 e1000_regs.h Wakeup Packet Memory - RO A
28488
 E1000_PBACLE1000_PBACL 0x05B68 e1000_regs.h MSIx PBA Clear - Read/Write 1's to clear
28489
 E1000_FFLTE1000_FFLT 0x05F00 e1000_regs.h Flexible Filter Length Table - RW Array
28490
 E1000_HOST_IFE1000_HOST_IF 0x08800 e1000_regs.h Host Interface
28491
 E1000_FFMTE1000_FFMT 0x09000 e1000_regs.h Flexible Filter Mask Table - RW Array
28492
 E1000_FFVTE1000_FFVT 0x09800 e1000_regs.h Flexible Filter Value Table - RW Array
28493
 E1000_KMRNCTRLSTAE1000_KMRNCTRLSTA 0x00034 e1000_regs.h MAC-PHY interface - RW
28494
 E1000_MDPHYAE1000_MDPHYA 0x0003C e1000_regs.h PHY address - RW
28495
 E1000_MANC2HE1000_MANC2H 0x05860 e1000_regs.h Management Control To Host - RW
28496
 E1000_SW_FW_SYNCE1000_SW_FW_SYNC 0x05B5C e1000_regs.h Software-Firmware Synchronization - RW
28497
 E1000_CCMCTLE1000_CCMCTL 0x05B48 e1000_regs.h CCM Control Register
28498
 E1000_GIOCTLE1000_GIOCTL 0x05B44 e1000_regs.h GIO Analog Control Register
28499
 E1000_SCCTLE1000_SCCTL 0x05B4C e1000_regs.h PCIc PLL Configuration Register
28500
 E1000_GCRE1000_GCR 0x05B00 e1000_regs.h PCI-Ex Control
28501
 E1000_GCR2E1000_GCR2 0x05B64 e1000_regs.h PCI-Ex Control #2
28502
 E1000_GSCL_1E1000_GSCL_1 0x05B10 e1000_regs.h PCI-Ex Statistic Control #1
28503
 E1000_GSCL_2E1000_GSCL_2 0x05B14 e1000_regs.h PCI-Ex Statistic Control #2
28504
 E1000_GSCL_3E1000_GSCL_3 0x05B18 e1000_regs.h PCI-Ex Statistic Control #3
28505
 E1000_GSCL_4E1000_GSCL_4 0x05B1C e1000_regs.h PCI-Ex Statistic Control #4
28506
 E1000_FACTPSE1000_FACTPS 0x05B30 e1000_regs.h Function Active and Power State to MNG
28507
 E1000_SWSME1000_SWSM 0x05B50 e1000_regs.h SW Semaphore
28508
 E1000_FWSME1000_FWSM 0x05B54 e1000_regs.h FW Semaphore
28509
 E1000_SWSM2E1000_SWSM2 0x05B58 e1000_regs.h Driver-only SW semaphore (not used by BOOT agents)
28510
 E1000_DCA_IDE1000_DCA_ID 0x05B70 e1000_regs.h DCA Requester ID Information - RO
28511
 E1000_DCA_CTRLE1000_DCA_CTRL 0x05B74 e1000_regs.h DCA Control - RW
28512
 E1000_FFLT_DBGE1000_FFLT_DBG 0x05F04 e1000_regs.h Debug Register
28513
 E1000_HICRE1000_HICR 0x08F00 e1000_regs.h Host Interface Control
28514
 E1000_CPUVECE1000_CPUVEC 0x02C10 e1000_regs.h CPU Vector Register - RW
28515
 E1000_MRQCE1000_MRQC 0x05818 e1000_regs.h Multiple Receive Control - RW
28516
 E1000_IMIRVPE1000_IMIRVP 0x05AC0 e1000_regs.h Immediate Interrupt Rx VLAN Priority - RW
28517
 E1000_MSIXPBAE1000_MSIXPBA 0x0E000 e1000_regs.h MSI-X Pending bit array
28518
 E1000_RSSIME1000_RSSIM 0x05864 e1000_regs.h RSS Interrupt Mask
28519
 E1000_RSSIRE1000_RSSIR 0x05868 e1000_regs.h RSS Interrupt Request
28520
 GG82563_CABLE_LENGTH_TABLE_SIZEGG82563_CABLE_LENGTH_TABLE_SIZE (sizeof(e1000_gg82563_cable_length_table) / \ sizeof(e1000_gg82563_cable_length_table[0])) e1000e_80003es2lan.c 　
28521
 M88E1000_CABLE_LENGTH_TABLE_SIZM88E1000_CABLE_LENGTH_TABLE_SIZ (sizeof(e1000_m88_cable_length_table) / \ sizeof(e1000_m88_cable_length_table[0])) e1000e_phy.c 　
28522
 IGP02E1000_CABLE_LENGTH_TABLE_SIGP02E1000_CABLE_LENGTH_TABLE_S (sizeof(e1000_igp_2_cable_length_table) / \ sizeof(e1000_igp_2_cable_length_table[0])) e1000e_phy.c 　
28523
 u8u8 unsigned char e1000e.h 　
28524
 boolbool boolean_t e1000e.h 　
28525
 dma_addr_tdma_addr_t unsigned long e1000e.h 　
28526
 __le16__le16 uint16_t e1000e.h 　
28527
 __le32__le32 uint32_t e1000e.h 　
28528
 __le64__le64 uint64_t e1000e.h 　
28529
 ETH_FCS_LENETH_FCS_LEN 4 e1000e.h 　
28530
 E1000_TX_FLAGS_CSUME1000_TX_FLAGS_CSUM 0x00000001 e1000e.h 　
28531
 E1000_TX_FLAGS_VLANE1000_TX_FLAGS_VLAN 0x00000002 e1000e.h 　
28532
 E1000_TX_FLAGS_TSOE1000_TX_FLAGS_TSO 0x00000004 e1000e.h 　
28533
 E1000_TX_FLAGS_IPV4E1000_TX_FLAGS_IPV4 0x00000008 e1000e.h 　
28534
 E1000_TX_FLAGS_VLAN_MASKE1000_TX_FLAGS_VLAN_MASK 0xffff0000 e1000e.h 　
28535
 E1000_TX_FLAGS_VLAN_SHIFTE1000_TX_FLAGS_VLAN_SHIFT 16 e1000e.h 　
28536
 E1000_MAX_PER_TXDE1000_MAX_PER_TXD 8192 e1000e.h 　
28537
 E1000_MAX_TXD_PWRE1000_MAX_TXD_PWR 12 e1000e.h 　
28538
 MINIMUM_DHCP_PACKET_SIZEMINIMUM_DHCP_PACKET_SIZE 282 e1000e.h 　
28539
 E1000E_INT_MODE_LEGACYE1000E_INT_MODE_LEGACY 0 e1000e.h 　
28540
 E1000E_INT_MODE_MSIE1000E_INT_MODE_MSI 1 e1000e.h 　
28541
 E1000E_INT_MODE_MSIXE1000E_INT_MODE_MSIX 2 e1000e.h 　
28542
 E1000_MAX_INTRE1000_MAX_INTR 10 e1000e.h 　
28543
 E1000_DEFAULT_TXDE1000_DEFAULT_TXD 256 e1000e.h 　
28544
 E1000_MAX_TXDE1000_MAX_TXD 4096 e1000e.h 　
28545
 E1000_MIN_TXDE1000_MIN_TXD 64 e1000e.h 　
28546
 E1000_DEFAULT_RXDE1000_DEFAULT_RXD 256 e1000e.h 　
28547
 E1000_MAX_RXDE1000_MAX_RXD 4096 e1000e.h 　
28548
 E1000_MIN_RXDE1000_MIN_RXD 64 e1000e.h 　
28549
 E1000_MIN_ITR_USECSE1000_MIN_ITR_USECS 10 e1000e.h 100000 irq/sec
28550
 E1000_MAX_ITR_USECSE1000_MAX_ITR_USECS 10000 e1000e.h 100 irq/sec
28551
 E1000_ERT_2048E1000_ERT_2048 0x100 e1000e.h 　
28552
 E1000_FC_PAUSE_TIMEE1000_FC_PAUSE_TIME 0x0680 e1000e.h 858 usec
28553
 E1000_RX_BUFFER_WRITEE1000_RX_BUFFER_WRITE 16 e1000e.h Must be power of 2
28554
 AUTO_ALL_MODESAUTO_ALL_MODES 0 e1000e.h 　
28555
 E1000_EEPROM_APMEE1000_EEPROM_APME 0x0400 e1000e.h 　
28556
 E1000_MNG_VLAN_NONEE1000_MNG_VLAN_NONE (-1) e1000e.h 　
28557
 PS_PAGE_BUFFERSPS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1) e1000e.h 　
28558
 MAXIMUM_ETHERNET_VLAN_SIZEMAXIMUM_ETHERNET_VLAN_SIZE 1522 e1000e.h 　
28559
 DEFAULT_JUMBODEFAULT_JUMBO 9234 e1000e.h 　
28560
 FLAG_HAS_AMTFLAG_HAS_AMT (1 << 0) e1000e.h 　
28561
 FLAG_HAS_FLASHFLAG_HAS_FLASH (1 << 1) e1000e.h 　
28562
 FLAG_HAS_HW_VLAN_FILTERFLAG_HAS_HW_VLAN_FILTER (1 << 2) e1000e.h 　
28563
 FLAG_HAS_WOLFLAG_HAS_WOL (1 << 3) e1000e.h 　
28564
 FLAG_HAS_ERTFLAG_HAS_ERT (1 << 4) e1000e.h 　
28565
 FLAG_HAS_CTRLEXT_ON_LOADFLAG_HAS_CTRLEXT_ON_LOAD (1 << 5) e1000e.h 　
28566
 FLAG_HAS_SWSM_ON_LOADFLAG_HAS_SWSM_ON_LOAD (1 << 6) e1000e.h 　
28567
 FLAG_HAS_JUMBO_FRAMESFLAG_HAS_JUMBO_FRAMES (1 << 7) e1000e.h 　
28568
 FLAG_IS_ICHFLAG_IS_ICH (1 << 9) e1000e.h 　
28569
 FLAG_HAS_MSIXFLAG_HAS_MSIX (1 << 10) e1000e.h 　
28570
 FLAG_HAS_SMART_POWER_DOWNFLAG_HAS_SMART_POWER_DOWN (1 << 11) e1000e.h 　
28571
 FLAG_IS_QUAD_PORT_AFLAG_IS_QUAD_PORT_A (1 << 12) e1000e.h 　
28572
 FLAG_IS_QUAD_PORTFLAG_IS_QUAD_PORT (1 << 13) e1000e.h 　
28573
 FLAG_TIPG_MEDIUM_FOR_80003ESLANFLAG_TIPG_MEDIUM_FOR_80003ESLAN (1 << 14) e1000e.h 　
28574
 FLAG_APME_IN_WUCFLAG_APME_IN_WUC (1 << 15) e1000e.h 　
28575
 FLAG_APME_IN_CTRL3FLAG_APME_IN_CTRL3 (1 << 16) e1000e.h 　
28576
 FLAG_APME_CHECK_PORT_BFLAG_APME_CHECK_PORT_B (1 << 17) e1000e.h 　
28577
 FLAG_DISABLE_FC_PAUSE_TIMEFLAG_DISABLE_FC_PAUSE_TIME (1 << 18) e1000e.h 　
28578
 FLAG_NO_WAKE_UCASTFLAG_NO_WAKE_UCAST (1 << 19) e1000e.h 　
28579
 FLAG_MNG_PT_ENABLEDFLAG_MNG_PT_ENABLED (1 << 20) e1000e.h 　
28580
 FLAG_RESET_OVERWRITES_LAAFLAG_RESET_OVERWRITES_LAA (1 << 21) e1000e.h 　
28581
 FLAG_TARC_SPEED_MODE_BITFLAG_TARC_SPEED_MODE_BIT (1 << 22) e1000e.h 　
28582
 FLAG_TARC_SET_BIT_ZEROFLAG_TARC_SET_BIT_ZERO (1 << 23) e1000e.h 　
28583
 FLAG_RX_NEEDS_RESTARTFLAG_RX_NEEDS_RESTART (1 << 24) e1000e.h 　
28584
 FLAG_LSC_GIG_SPEED_DROPFLAG_LSC_GIG_SPEED_DROP (1 << 25) e1000e.h 　
28585
 FLAG_SMART_POWER_DOWNFLAG_SMART_POWER_DOWN (1 << 26) e1000e.h 　
28586
 FLAG_MSI_ENABLEDFLAG_MSI_ENABLED (1 << 27) e1000e.h 　
28587
 FLAG_RX_CSUM_ENABLEDFLAG_RX_CSUM_ENABLED (1 << 28) e1000e.h 　
28588
 FLAG_TSO_FORCEFLAG_TSO_FORCE (1 << 29) e1000e.h 　
28589
 FLAG_RX_RESTART_NOWFLAG_RX_RESTART_NOW (1 << 30) e1000e.h 　
28590
 FLAG_MSI_TEST_FAILEDFLAG_MSI_TEST_FAILED (1 << 31) e1000e.h 　
28591
 FLAG2_CRC_STRIPPINGFLAG2_CRC_STRIPPING (1 << 0) e1000e.h 　
28592
 FLAG2_HAS_PHY_WAKEUPFLAG2_HAS_PHY_WAKEUP (1 << 1) e1000e.h 　
28593
 E1000_READ_REG_ARRAY_DWORDE1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY e1000e.h 　
28594
 E1000_WRITE_REG_ARRAY_DWORDE1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY e1000e.h 　
28595
 E1000_KMRNCTRLSTA_OFFSET_FIFO_CE1000_KMRNCTRLSTA_OFFSET_FIFO_C 0x00 e1000e_80003es2lan.h 　
28596
 E1000_KMRNCTRLSTA_OFFSET_INB_CTE1000_KMRNCTRLSTA_OFFSET_INB_CT 0x02 e1000e_80003es2lan.h 　
28597
 E1000_KMRNCTRLSTA_OFFSET_HD_CTRE1000_KMRNCTRLSTA_OFFSET_HD_CTR 0x10 e1000e_80003es2lan.h 　
28598
 E1000_KMRNCTRLSTA_OFFSET_MAC2PHE1000_KMRNCTRLSTA_OFFSET_MAC2PH 0x1F e1000e_80003es2lan.h 　
28599
 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_E1000_KMRNCTRLSTA_FIFO_CTRL_RX_ 0x0008 e1000e_80003es2lan.h 　
28600
 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_E1000_KMRNCTRLSTA_FIFO_CTRL_TX_ 0x0800 e1000e_80003es2lan.h 　
28601
 E1000_KMRNCTRLSTA_INB_CTRL_DIS_E1000_KMRNCTRLSTA_INB_CTRL_DIS_ 0x0010 e1000e_80003es2lan.h 　
28602
 E1000_KMRNCTRLSTA_HD_CTRL_10_10E1000_KMRNCTRLSTA_HD_CTRL_10_10 0x0004 e1000e_80003es2lan.h 　
28603
 E1000_KMRNCTRLSTA_HD_CTRL_1000_E1000_KMRNCTRLSTA_HD_CTRL_1000_ 0x0000 e1000e_80003es2lan.h 　
28604
 E1000_KMRNCTRLSTA_OPMODE_E_IDLEE1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000 e1000e_80003es2lan.h 　
28605
 E1000_KMRNCTRLSTA_OPMODE_MASKE1000_KMRNCTRLSTA_OPMODE_MASK 0x000C e1000e_80003es2lan.h 　
28606
 E1000_KMRNCTRLSTA_OPMODE_INBANDE1000_KMRNCTRLSTA_OPMODE_INBAND 0x0004 e1000e_80003es2lan.h 　
28607
 E1000_TCTL_EXT_GCEX_MASKE1000_TCTL_EXT_GCEX_MASK 0x000FFC00 e1000e_80003es2lan.h Gigabit Carry Extend Padding
28608
 DEFAULT_TCTL_EXT_GCEX_80003ES2LDEFAULT_TCTL_EXT_GCEX_80003ES2L 0x00010000 e1000e_80003es2lan.h 　
28609
 DEFAULT_TIPG_IPGT_1000_80003ES2DEFAULT_TIPG_IPGT_1000_80003ES2 0x8 e1000e_80003es2lan.h 　
28610
 DEFAULT_TIPG_IPGT_10_100_80003EDEFAULT_TIPG_IPGT_10_100_80003E 0x9 e1000e_80003es2lan.h 　
28611
 GG82563_PSCR_POLARITY_REVERSAL_GG82563_PSCR_POLARITY_REVERSAL_ 0x0002 e1000e_80003es2lan.h 1=Reversal Disabled
28612
 GG82563_PSCR_CROSSOVER_MODE_MASGG82563_PSCR_CROSSOVER_MODE_MAS 0x0060 e1000e_80003es2lan.h 　
28613
 GG82563_PSCR_CROSSOVER_MODE_MDIGG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 e1000e_80003es2lan.h 00=Manual MDI
28614
 GG82563_PSCR_CROSSOVER_MODE_MDIGG82563_PSCR_CROSSOVER_MODE_MDI 0x0020 e1000e_80003es2lan.h 01=Manual MDIX
28615
 GG82563_PSCR_CROSSOVER_MODE_AUTGG82563_PSCR_CROSSOVER_MODE_AUT 0x0060 e1000e_80003es2lan.h 11=Auto crossover
28616
 GG82563_PSCR2_REVERSE_AUTO_NEGGG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 e1000e_80003es2lan.h 　
28617
 GG82563_MSCR_TX_CLK_MASKGG82563_MSCR_TX_CLK_MASK 0x0007 e1000e_80003es2lan.h 　
28618
 GG82563_MSCR_TX_CLK_10MBPS_2_5GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004 e1000e_80003es2lan.h 　
28619
 GG82563_MSCR_TX_CLK_100MBPS_25GG82563_MSCR_TX_CLK_100MBPS_25 0x0005 e1000e_80003es2lan.h 　
28620
 GG82563_MSCR_TX_CLK_1000MBPS_2_GG82563_MSCR_TX_CLK_1000MBPS_2_ 0x0006 e1000e_80003es2lan.h 　
28621
 GG82563_MSCR_TX_CLK_1000MBPS_25GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007 e1000e_80003es2lan.h 　
28622
 GG82563_MSCR_ASSERT_CRS_ON_TXGG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 e1000e_80003es2lan.h 1=Assert
28623
 GG82563_DSPD_CABLE_LENGTHGG82563_DSPD_CABLE_LENGTH 0x0007 e1000e_80003es2lan.h 　
28624
 GG82563_KMCR_PASS_FALSE_CARRIERGG82563_KMCR_PASS_FALSE_CARRIER 0x0800 e1000e_80003es2lan.h 　
28625
 GG82563_MAX_KMRN_RETRYGG82563_MAX_KMRN_RETRY 0x5 e1000e_80003es2lan.h 　
28626
 GG82563_PMCR_ENABLE_ELECTRICAL_GG82563_PMCR_ENABLE_ELECTRICAL_ 0x0001 e1000e_80003es2lan.h 　
28627
 GG82563_ICR_DIS_PADDINGGG82563_ICR_DIS_PADDING 0x0010 e1000e_80003es2lan.h Disable Padding
28628
 ID_LED_RESERVED_F746ID_LED_RESERVED_F746 0xF746 e1000e_82571.h 　
28629
 ID_LED_DEFAULT_82573ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_OFF1_ON2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) e1000e_82571.h 　
28630
 E1000_GCR_L1_ACT_WITHOUT_L0S_RXE1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 e1000e_82571.h 　
28631
 E1000_EIAC_82574E1000_EIAC_82574 0x000DC e1000e_82571.h Ext. Interrupt Auto Clear - RW
28632
 E1000_EIAC_MASK_82574E1000_EIAC_MASK_82574 0x01F00000 e1000e_82571.h 　
28633
 E1000_NVM_INIT_CTRL2_MNGME1000_NVM_INIT_CTRL2_MNGM 0x6000 e1000e_82571.h Manageability Operation Mode mask
28634
 E1000_RXCFGLE1000_RXCFGL 0x0B634 e1000e_82571.h TimeSync Rx EtherType & Msg Type Reg - RW
28635
 REQ_TX_DESCRIPTOR_MULTIPLEREQ_TX_DESCRIPTOR_MULTIPLE 8 e1000e_defines.h 　
28636
 REQ_RX_DESCRIPTOR_MULTIPLEREQ_RX_DESCRIPTOR_MULTIPLE 8 e1000e_defines.h 　
28637
 E1000_WUC_APMEE1000_WUC_APME 0x00000001 e1000e_defines.h APM Enable
28638
 E1000_WUC_PME_ENE1000_WUC_PME_EN 0x00000002 e1000e_defines.h PME Enable
28639
 E1000_WUC_PME_STATUSE1000_WUC_PME_STATUS 0x00000004 e1000e_defines.h PME Status
28640
 E1000_WUC_APMPMEE1000_WUC_APMPME 0x00000008 e1000e_defines.h Assert PME on APM Wakeup
28641
 E1000_WUC_LSCWEE1000_WUC_LSCWE 0x00000010 e1000e_defines.h Link Status wake up enable
28642
 E1000_WUC_LSCWOE1000_WUC_LSCWO 0x00000020 e1000e_defines.h Link Status wake up override
28643
 E1000_WUC_SPME1000_WUC_SPM 0x80000000 e1000e_defines.h Enable SPM
28644
 E1000_WUC_PHY_WAKEE1000_WUC_PHY_WAKE 0x00000100 e1000e_defines.h if PHY supports wakeup
28645
 E1000_WUFC_LNKCE1000_WUFC_LNKC 0x00000001 e1000e_defines.h Link Status Change Wakeup Enable
28646
 E1000_WUFC_MAGE1000_WUFC_MAG 0x00000002 e1000e_defines.h Magic Packet Wakeup Enable
28647
 E1000_WUFC_EXE1000_WUFC_EX 0x00000004 e1000e_defines.h Directed Exact Wakeup Enable
28648
 E1000_WUFC_MCE1000_WUFC_MC 0x00000008 e1000e_defines.h Directed Multicast Wakeup Enable
28649
 E1000_WUFC_BCE1000_WUFC_BC 0x00000010 e1000e_defines.h Broadcast Wakeup Enable
28650
 E1000_WUFC_ARPE1000_WUFC_ARP 0x00000020 e1000e_defines.h ARP Request Packet Wakeup Enable
28651
 E1000_WUFC_IPV4E1000_WUFC_IPV4 0x00000040 e1000e_defines.h Directed IPv4 Packet Wakeup Enable
28652
 E1000_WUFC_IPV6E1000_WUFC_IPV6 0x00000080 e1000e_defines.h Directed IPv6 Packet Wakeup Enable
28653
 E1000_WUFC_IGNORE_TCO_PHYE1000_WUFC_IGNORE_TCO_PHY 0x00000800 e1000e_defines.h Ignore WakeOn TCO packets
28654
 E1000_WUFC_FLX0_PHYE1000_WUFC_FLX0_PHY 0x00001000 e1000e_defines.h Flexible Filter 0 Enable
28655
 E1000_WUFC_FLX1_PHYE1000_WUFC_FLX1_PHY 0x00002000 e1000e_defines.h Flexible Filter 1 Enable
28656
 E1000_WUFC_FLX2_PHYE1000_WUFC_FLX2_PHY 0x00004000 e1000e_defines.h Flexible Filter 2 Enable
28657
 E1000_WUFC_FLX3_PHYE1000_WUFC_FLX3_PHY 0x00008000 e1000e_defines.h Flexible Filter 3 Enable
28658
 E1000_WUFC_FLX4_PHYE1000_WUFC_FLX4_PHY 0x00000200 e1000e_defines.h Flexible Filter 4 Enable
28659
 E1000_WUFC_FLX5_PHYE1000_WUFC_FLX5_PHY 0x00000400 e1000e_defines.h Flexible Filter 5 Enable
28660
 E1000_WUFC_IGNORE_TCOE1000_WUFC_IGNORE_TCO 0x00008000 e1000e_defines.h Ignore WakeOn TCO packets
28661
 E1000_WUFC_FLX0E1000_WUFC_FLX0 0x00010000 e1000e_defines.h Flexible Filter 0 Enable
28662
 E1000_WUFC_FLX1E1000_WUFC_FLX1 0x00020000 e1000e_defines.h Flexible Filter 1 Enable
28663
 E1000_WUFC_FLX2E1000_WUFC_FLX2 0x00040000 e1000e_defines.h Flexible Filter 2 Enable
28664
 E1000_WUFC_FLX3E1000_WUFC_FLX3 0x00080000 e1000e_defines.h Flexible Filter 3 Enable
28665
 E1000_WUFC_FLX4E1000_WUFC_FLX4 0x00100000 e1000e_defines.h Flexible Filter 4 Enable
28666
 E1000_WUFC_FLX5E1000_WUFC_FLX5 0x00200000 e1000e_defines.h Flexible Filter 5 Enable
28667
 E1000_WUFC_ALL_FILTERS_PHY_4E1000_WUFC_ALL_FILTERS_PHY_4 0x0000F0FF e1000e_defines.h Mask for all wakeup filters
28668
 E1000_WUFC_FLX_OFFSET_PHYE1000_WUFC_FLX_OFFSET_PHY 12 e1000e_defines.h Offset to the Flexible Filters bits
28669
 E1000_WUFC_FLX_FILTERS_PHY_4E1000_WUFC_FLX_FILTERS_PHY_4 0x0000F000 e1000e_defines.h Mask for 4 flexible filters
28670
 E1000_WUFC_ALL_FILTERS_PHY_6E1000_WUFC_ALL_FILTERS_PHY_6 0x0000F6FF e1000e_defines.h Mask for 6 wakeup filters
28671
 E1000_WUFC_FLX_FILTERS_PHY_6E1000_WUFC_FLX_FILTERS_PHY_6 0x0000F600 e1000e_defines.h Mask for 6 flexible filters
28672
 E1000_WUFC_ALL_FILTERSE1000_WUFC_ALL_FILTERS 0x000F00FF e1000e_defines.h Mask for all wakeup filters
28673
 E1000_WUFC_ALL_FILTERS_6E1000_WUFC_ALL_FILTERS_6 0x003F00FF e1000e_defines.h Mask for all 6 wakeup filters
28674
 E1000_WUFC_FLX_OFFSETE1000_WUFC_FLX_OFFSET 16 e1000e_defines.h Offset to the Flexible Filters bits
28675
 E1000_WUFC_FLX_FILTERSE1000_WUFC_FLX_FILTERS 0x000F0000 e1000e_defines.h Mask for the 4 flexible filters
28676
 E1000_WUFC_FLX_FILTERS_6E1000_WUFC_FLX_FILTERS_6 0x003F0000 e1000e_defines.h Mask for 6 flexible filters
28677
 E1000_WUS_LNKCE1000_WUS_LNKC E1000_WUFC_LNKC e1000e_defines.h 　
28678
 E1000_WUS_MAGE1000_WUS_MAG E1000_WUFC_MAG e1000e_defines.h 　
28679
 E1000_WUS_EXE1000_WUS_EX E1000_WUFC_EX e1000e_defines.h 　
28680
 E1000_WUS_MCE1000_WUS_MC E1000_WUFC_MC e1000e_defines.h 　
28681
 E1000_WUS_BCE1000_WUS_BC E1000_WUFC_BC e1000e_defines.h 　
28682
 E1000_WUS_ARPE1000_WUS_ARP E1000_WUFC_ARP e1000e_defines.h 　
28683
 E1000_WUS_IPV4E1000_WUS_IPV4 E1000_WUFC_IPV4 e1000e_defines.h 　
28684
 E1000_WUS_IPV6E1000_WUS_IPV6 E1000_WUFC_IPV6 e1000e_defines.h 　
28685
 E1000_WUS_FLX0_PHYE1000_WUS_FLX0_PHY E1000_WUFC_FLX0_PHY e1000e_defines.h 　
28686
 E1000_WUS_FLX1_PHYE1000_WUS_FLX1_PHY E1000_WUFC_FLX1_PHY e1000e_defines.h 　
28687
 E1000_WUS_FLX2_PHYE1000_WUS_FLX2_PHY E1000_WUFC_FLX2_PHY e1000e_defines.h 　
28688
 E1000_WUS_FLX3_PHYE1000_WUS_FLX3_PHY E1000_WUFC_FLX3_PHY e1000e_defines.h 　
28689
 E1000_WUS_FLX_FILTERS_PHY_4E1000_WUS_FLX_FILTERS_PHY_4 E1000_WUFC_FLX_FILTERS_PHY_4 e1000e_defines.h 　
28690
 E1000_WUS_FLX0E1000_WUS_FLX0 E1000_WUFC_FLX0 e1000e_defines.h 　
28691
 E1000_WUS_FLX1E1000_WUS_FLX1 E1000_WUFC_FLX1 e1000e_defines.h 　
28692
 E1000_WUS_FLX2E1000_WUS_FLX2 E1000_WUFC_FLX2 e1000e_defines.h 　
28693
 E1000_WUS_FLX3E1000_WUS_FLX3 E1000_WUFC_FLX3 e1000e_defines.h 　
28694
 E1000_WUS_FLX4E1000_WUS_FLX4 E1000_WUFC_FLX4 e1000e_defines.h 　
28695
 E1000_WUS_FLX5E1000_WUS_FLX5 E1000_WUFC_FLX5 e1000e_defines.h 　
28696
 E1000_WUS_FLX4_PHYE1000_WUS_FLX4_PHY E1000_WUFC_FLX4_PHY e1000e_defines.h 　
28697
 E1000_WUS_FLX5_PHYE1000_WUS_FLX5_PHY E1000_WUFC_FLX5_PHY e1000e_defines.h 　
28698
 E1000_WUS_FLX_FILTERSE1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS e1000e_defines.h 　
28699
 E1000_WUS_FLX_FILTERS_6E1000_WUS_FLX_FILTERS_6 E1000_WUFC_FLX_FILTERS_6 e1000e_defines.h 　
28700
 E1000_WUS_FLX_FILTERS_PHY_6E1000_WUS_FLX_FILTERS_PHY_6 E1000_WUFC_FLX_FILTERS_PHY_6 e1000e_defines.h 　
28701
 E1000_WUPL_LENGTH_MASKE1000_WUPL_LENGTH_MASK 0x0FFF e1000e_defines.h Only the lower 12 bits are valid
28702
 E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 4 e1000e_defines.h 　
28703
 E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 6 e1000e_defines.h 　
28704
 E1000_FLEXIBLE_FILTER_SIZE_MAXE1000_FLEXIBLE_FILTER_SIZE_MAX 128 e1000e_defines.h 　
28705
 E1000_FFLT_SIZEE1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX e1000e_defines.h 　
28706
 E1000_FFLT_SIZE_6E1000_FFLT_SIZE_6 E1000_FLEXIBLE_FILTER_COUNT_MAX_6 e1000e_defines.h 　
28707
 E1000_FFMT_SIZEE1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000e_defines.h 　
28708
 E1000_FFVT_SIZEE1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX e1000e_defines.h 　
28709
 E1000_CTRL_EXT_GPI0_ENE1000_CTRL_EXT_GPI0_EN 0x00000001 e1000e_defines.h Maps SDP4 to GPI0
28710
 E1000_CTRL_EXT_GPI1_ENE1000_CTRL_EXT_GPI1_EN 0x00000002 e1000e_defines.h Maps SDP5 to GPI1
28711
 E1000_CTRL_EXT_PHYINT_ENE1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN e1000e_defines.h 　
28712
 E1000_CTRL_EXT_GPI2_ENE1000_CTRL_EXT_GPI2_EN 0x00000004 e1000e_defines.h Maps SDP6 to GPI2
28713
 E1000_CTRL_EXT_GPI3_ENE1000_CTRL_EXT_GPI3_EN 0x00000008 e1000e_defines.h Maps SDP7 to GPI3
28714
 E1000_CTRL_EXT_SDP4_DATAE1000_CTRL_EXT_SDP4_DATA 0x00000010 e1000e_defines.h Value of SW Definable Pin 4
28715
 E1000_CTRL_EXT_SDP5_DATAE1000_CTRL_EXT_SDP5_DATA 0x00000020 e1000e_defines.h Value of SW Definable Pin 5
28716
 E1000_CTRL_EXT_PHY_INTE1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA e1000e_defines.h 　
28717
 E1000_CTRL_EXT_SDP6_DATAE1000_CTRL_EXT_SDP6_DATA 0x00000040 e1000e_defines.h Value of SW Definable Pin 6
28718
 E1000_CTRL_EXT_SDP3_DATAE1000_CTRL_EXT_SDP3_DATA 0x00000080 e1000e_defines.h Value of SW Definable Pin 3
28719
 E1000_CTRL_EXT_SDP4_DIRE1000_CTRL_EXT_SDP4_DIR 0x00000100 e1000e_defines.h Direction of SDP4 0=in 1=out
28720
 E1000_CTRL_EXT_SDP5_DIRE1000_CTRL_EXT_SDP5_DIR 0x00000200 e1000e_defines.h Direction of SDP5 0=in 1=out
28721
 E1000_CTRL_EXT_SDP6_DIRE1000_CTRL_EXT_SDP6_DIR 0x00000400 e1000e_defines.h Direction of SDP6 0=in 1=out
28722
 E1000_CTRL_EXT_SDP3_DIRE1000_CTRL_EXT_SDP3_DIR 0x00000800 e1000e_defines.h Direction of SDP3 0=in 1=out
28723
 E1000_CTRL_EXT_ASDCHKE1000_CTRL_EXT_ASDCHK 0x00001000 e1000e_defines.h Initiate an ASD sequence
28724
 E1000_CTRL_EXT_EE_RSTE1000_CTRL_EXT_EE_RST 0x00002000 e1000e_defines.h Reinitialize from EEPROM
28725
 E1000_CTRL_EXT_IPSE1000_CTRL_EXT_IPS 0x00004000 e1000e_defines.h Invert Power State
28726
 E1000_CTRL_EXT_SPD_BYPSE1000_CTRL_EXT_SPD_BYPS 0x00008000 e1000e_defines.h Speed Select Bypass
28727
 E1000_CTRL_EXT_RO_DISE1000_CTRL_EXT_RO_DIS 0x00020000 e1000e_defines.h Relaxed Ordering disable
28728
 E1000_CTRL_EXT_DMA_DYN_CLK_ENE1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 e1000e_defines.h DMA Dynamic Clock Gating
28729
 E1000_CTRL_EXT_LINK_MODE_MASKE1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 e1000e_defines.h 　
28730
 E1000_CTRL_EXT_LINK_MODE_GMIIE1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 e1000e_defines.h 　
28731
 E1000_CTRL_EXT_LINK_MODE_TBIE1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 e1000e_defines.h 　
28732
 E1000_CTRL_EXT_LINK_MODE_KMRNE1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 e1000e_defines.h 　
28733
 E1000_CTRL_EXT_LINK_MODE_PCIE_SE1000_CTRL_EXT_LINK_MODE_PCIE_S 0x00C00000 e1000e_defines.h 　
28734
 E1000_CTRL_EXT_LINK_MODE_PCIX_SE1000_CTRL_EXT_LINK_MODE_PCIX_S 0x00800000 e1000e_defines.h 　
28735
 E1000_CTRL_EXT_LINK_MODE_SGMIIE1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 e1000e_defines.h 　
28736
 E1000_CTRL_EXT_EIAMEE1000_CTRL_EXT_EIAME 0x01000000 e1000e_defines.h 　
28737
 E1000_CTRL_EXT_IRCAE1000_CTRL_EXT_IRCA 0x00000001 e1000e_defines.h 　
28738
 E1000_CTRL_EXT_WR_WMARK_MASKE1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 e1000e_defines.h 　
28739
 E1000_CTRL_EXT_WR_WMARK_256E1000_CTRL_EXT_WR_WMARK_256 0x00000000 e1000e_defines.h 　
28740
 E1000_CTRL_EXT_WR_WMARK_320E1000_CTRL_EXT_WR_WMARK_320 0x01000000 e1000e_defines.h 　
28741
 E1000_CTRL_EXT_WR_WMARK_384E1000_CTRL_EXT_WR_WMARK_384 0x02000000 e1000e_defines.h 　
28742
 E1000_CTRL_EXT_WR_WMARK_448E1000_CTRL_EXT_WR_WMARK_448 0x03000000 e1000e_defines.h 　
28743
 E1000_CTRL_EXT_CANCE1000_CTRL_EXT_CANC 0x04000000 e1000e_defines.h Int delay cancellation
28744
 E1000_CTRL_EXT_DRV_LOADE1000_CTRL_EXT_DRV_LOAD 0x10000000 e1000e_defines.h Driver loaded bit for FW
28745
 E1000_CTRL_EXT_IAMEE1000_CTRL_EXT_IAME 0x08000000 e1000e_defines.h Int acknowledge Auto-mask
28746
 E1000_CRTL_EXT_PB_PARENE1000_CRTL_EXT_PB_PAREN 0x01000000 e1000e_defines.h packet buffer parity error
28747
 E1000_CTRL_EXT_DF_PARENE1000_CTRL_EXT_DF_PAREN 0x02000000 e1000e_defines.h descriptor FIFO parity
28748
 E1000_CTRL_EXT_GHOST_PARENE1000_CTRL_EXT_GHOST_PAREN 0x40000000 e1000e_defines.h 　
28749
 E1000_CTRL_EXT_PBA_CLRE1000_CTRL_EXT_PBA_CLR 0x80000000 e1000e_defines.h PBA Clear
28750
 E1000_CTRL_EXT_LSECCKE1000_CTRL_EXT_LSECCK 0x00001000 e1000e_defines.h 　
28751
 E1000_CTRL_EXT_PHYPDENE1000_CTRL_EXT_PHYPDEN 0x00100000 e1000e_defines.h 　
28752
 E1000_I2CCMD_REG_ADDR_SHIFTE1000_I2CCMD_REG_ADDR_SHIFT 16 e1000e_defines.h 　
28753
 E1000_I2CCMD_REG_ADDRE1000_I2CCMD_REG_ADDR 0x00FF0000 e1000e_defines.h 　
28754
 E1000_I2CCMD_PHY_ADDR_SHIFTE1000_I2CCMD_PHY_ADDR_SHIFT 24 e1000e_defines.h 　
28755
 E1000_I2CCMD_PHY_ADDRE1000_I2CCMD_PHY_ADDR 0x07000000 e1000e_defines.h 　
28756
 E1000_I2CCMD_OPCODE_READE1000_I2CCMD_OPCODE_READ 0x08000000 e1000e_defines.h 　
28757
 E1000_I2CCMD_OPCODE_WRITEE1000_I2CCMD_OPCODE_WRITE 0x00000000 e1000e_defines.h 　
28758
 E1000_I2CCMD_RESETE1000_I2CCMD_RESET 0x10000000 e1000e_defines.h 　
28759
 E1000_I2CCMD_READYE1000_I2CCMD_READY 0x20000000 e1000e_defines.h 　
28760
 E1000_I2CCMD_INTERRUPT_ENAE1000_I2CCMD_INTERRUPT_ENA 0x40000000 e1000e_defines.h 　
28761
 E1000_I2CCMD_ERRORE1000_I2CCMD_ERROR 0x80000000 e1000e_defines.h 　
28762
 E1000_MAX_SGMII_PHY_REG_ADDRE1000_MAX_SGMII_PHY_REG_ADDR 255 e1000e_defines.h 　
28763
 E1000_I2CCMD_PHY_TIMEOUTE1000_I2CCMD_PHY_TIMEOUT 200 e1000e_defines.h 　
28764
 E1000_RXD_STAT_DDE1000_RXD_STAT_DD 0x01 e1000e_defines.h Descriptor Done
28765
 E1000_RXD_STAT_EOPE1000_RXD_STAT_EOP 0x02 e1000e_defines.h End of Packet
28766
 E1000_RXD_STAT_IXSME1000_RXD_STAT_IXSM 0x04 e1000e_defines.h Ignore checksum
28767
 E1000_RXD_STAT_VPE1000_RXD_STAT_VP 0x08 e1000e_defines.h IEEE VLAN Packet
28768
 E1000_RXD_STAT_UDPCSE1000_RXD_STAT_UDPCS 0x10 e1000e_defines.h UDP xsum calculated
28769
 E1000_RXD_STAT_TCPCSE1000_RXD_STAT_TCPCS 0x20 e1000e_defines.h TCP xsum calculated
28770
 E1000_RXD_STAT_IPCSE1000_RXD_STAT_IPCS 0x40 e1000e_defines.h IP xsum calculated
28771
 E1000_RXD_STAT_PIFE1000_RXD_STAT_PIF 0x80 e1000e_defines.h passed in-exact filter
28772
 E1000_RXD_STAT_CRCVE1000_RXD_STAT_CRCV 0x100 e1000e_defines.h Speculative CRC Valid
28773
 E1000_RXD_STAT_IPIDVE1000_RXD_STAT_IPIDV 0x200 e1000e_defines.h IP identification valid
28774
 E1000_RXD_STAT_UDPVE1000_RXD_STAT_UDPV 0x400 e1000e_defines.h Valid UDP checksum
28775
 E1000_RXD_STAT_DYNINTE1000_RXD_STAT_DYNINT 0x800 e1000e_defines.h Pkt caused INT via DYNINT
28776
 E1000_RXD_STAT_ACKE1000_RXD_STAT_ACK 0x8000 e1000e_defines.h ACK Packet indication
28777
 E1000_RXD_ERR_CEE1000_RXD_ERR_CE 0x01 e1000e_defines.h CRC Error
28778
 E1000_RXD_ERR_SEE1000_RXD_ERR_SE 0x02 e1000e_defines.h Symbol Error
28779
 E1000_RXD_ERR_SEQE1000_RXD_ERR_SEQ 0x04 e1000e_defines.h Sequence Error
28780
 E1000_RXD_ERR_CXEE1000_RXD_ERR_CXE 0x10 e1000e_defines.h Carrier Extension Error
28781
 E1000_RXD_ERR_TCPEE1000_RXD_ERR_TCPE 0x20 e1000e_defines.h TCP/UDP Checksum Error
28782
 E1000_RXD_ERR_IPEE1000_RXD_ERR_IPE 0x40 e1000e_defines.h IP Checksum Error
28783
 E1000_RXD_ERR_RXEE1000_RXD_ERR_RXE 0x80 e1000e_defines.h Rx Data Error
28784
 E1000_RXD_SPC_VLAN_MASKE1000_RXD_SPC_VLAN_MASK 0x0FFF e1000e_defines.h VLAN ID is in lower 12 bits
28785
 E1000_RXD_SPC_PRI_MASKE1000_RXD_SPC_PRI_MASK 0xE000 e1000e_defines.h Priority is in upper 3 bits
28786
 E1000_RXD_SPC_PRI_SHIFTE1000_RXD_SPC_PRI_SHIFT 13 e1000e_defines.h 　
28787
 E1000_RXD_SPC_CFI_MASKE1000_RXD_SPC_CFI_MASK 0x1000 e1000e_defines.h CFI is bit 12
28788
 E1000_RXD_SPC_CFI_SHIFTE1000_RXD_SPC_CFI_SHIFT 12 e1000e_defines.h 　
28789
 E1000_RXDEXT_STATERR_CEE1000_RXDEXT_STATERR_CE 0x01000000 e1000e_defines.h 　
28790
 E1000_RXDEXT_STATERR_SEE1000_RXDEXT_STATERR_SE 0x02000000 e1000e_defines.h 　
28791
 E1000_RXDEXT_STATERR_SEQE1000_RXDEXT_STATERR_SEQ 0x04000000 e1000e_defines.h 　
28792
 E1000_RXDEXT_STATERR_CXEE1000_RXDEXT_STATERR_CXE 0x10000000 e1000e_defines.h 　
28793
 E1000_RXDEXT_STATERR_TCPEE1000_RXDEXT_STATERR_TCPE 0x20000000 e1000e_defines.h 　
28794
 E1000_RXDEXT_STATERR_IPEE1000_RXDEXT_STATERR_IPE 0x40000000 e1000e_defines.h 　
28795
 E1000_RXDEXT_STATERR_RXEE1000_RXDEXT_STATERR_RXE 0x80000000 e1000e_defines.h 　
28796
 E1000_RXDEXT_LSECHE1000_RXDEXT_LSECH 0x01000000 e1000e_defines.h 　
28797
 E1000_RXDEXT_LSECE_MASKE1000_RXDEXT_LSECE_MASK 0x60000000 e1000e_defines.h 　
28798
 E1000_RXDEXT_LSECE_NO_ERRORE1000_RXDEXT_LSECE_NO_ERROR 0x00000000 e1000e_defines.h 　
28799
 E1000_RXDEXT_LSECE_NO_SA_MATCHE1000_RXDEXT_LSECE_NO_SA_MATCH 0x20000000 e1000e_defines.h 　
28800
 E1000_RXDEXT_LSECE_REPLAY_DETECE1000_RXDEXT_LSECE_REPLAY_DETEC 0x40000000 e1000e_defines.h 　
28801
 E1000_RXDEXT_LSECE_BAD_SIGE1000_RXDEXT_LSECE_BAD_SIG 0x60000000 e1000e_defines.h 　
28802
 E1000_RXD_ERR_FRAME_ERR_MASKE1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ E1000_RXD_ERR_SE | \ E1000_RXD_ERR_SEQ | \ E1000_RXD_ER e1000e_defines.h 　
28803
 E1000_RXDEXT_ERR_FRAME_ERR_MASKE1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_SE | \ E1000_RXDEXT_STATERR_SEQ | \ E10 e1000e_defines.h 　
28804
 E1000_MRQC_ENABLE_MASKE1000_MRQC_ENABLE_MASK 0x00000007 e1000e_defines.h 　
28805
 E1000_MRQC_ENABLE_RSS_2QE1000_MRQC_ENABLE_RSS_2Q 0x00000001 e1000e_defines.h 　
28806
 E1000_MRQC_ENABLE_RSS_INTE1000_MRQC_ENABLE_RSS_INT 0x00000004 e1000e_defines.h 　
28807
 E1000_MRQC_RSS_FIELD_MASKE1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 e1000e_defines.h 　
28808
 E1000_MRQC_RSS_FIELD_IPV4_TCPE1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 e1000e_defines.h 　
28809
 E1000_MRQC_RSS_FIELD_IPV4E1000_MRQC_RSS_FIELD_IPV4 0x00020000 e1000e_defines.h 　
28810
 E1000_MRQC_RSS_FIELD_IPV6_TCP_EE1000_MRQC_RSS_FIELD_IPV6_TCP_E 0x00040000 e1000e_defines.h 　
28811
 E1000_MRQC_RSS_FIELD_IPV6_EXE1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 e1000e_defines.h 　
28812
 E1000_MRQC_RSS_FIELD_IPV6E1000_MRQC_RSS_FIELD_IPV6 0x00100000 e1000e_defines.h 　
28813
 E1000_MRQC_RSS_FIELD_IPV6_TCPE1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 e1000e_defines.h 　
28814
 E1000_RXDPS_HDRSTAT_HDRSPE1000_RXDPS_HDRSTAT_HDRSP 0x00008000 e1000e_defines.h 　
28815
 E1000_RXDPS_HDRSTAT_HDRLEN_MASKE1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF e1000e_defines.h 　
28816
 E1000_MANC_SMBUS_ENE1000_MANC_SMBUS_EN 0x00000001 e1000e_defines.h SMBus Enabled - RO
28817
 E1000_MANC_ASF_ENE1000_MANC_ASF_EN 0x00000002 e1000e_defines.h ASF Enabled - RO
28818
 E1000_MANC_R_ON_FORCEE1000_MANC_R_ON_FORCE 0x00000004 e1000e_defines.h Reset on Force TCO - RO
28819
 E1000_MANC_RMCP_ENE1000_MANC_RMCP_EN 0x00000100 e1000e_defines.h Enable RCMP 026Fh Filtering
28820
 E1000_MANC_0298_ENE1000_MANC_0298_EN 0x00000200 e1000e_defines.h Enable RCMP 0298h Filtering
28821
 E1000_MANC_IPV4_ENE1000_MANC_IPV4_EN 0x00000400 e1000e_defines.h Enable IPv4
28822
 E1000_MANC_IPV6_ENE1000_MANC_IPV6_EN 0x00000800 e1000e_defines.h Enable IPv6
28823
 E1000_MANC_SNAP_ENE1000_MANC_SNAP_EN 0x00001000 e1000e_defines.h Accept LLC/SNAP
28824
 E1000_MANC_ARP_ENE1000_MANC_ARP_EN 0x00002000 e1000e_defines.h Enable ARP Request Filtering
28825
 E1000_MANC_NEIGHBOR_ENE1000_MANC_NEIGHBOR_EN 0x00004000 e1000e_defines.h 　
28826
 E1000_MANC_ARP_RES_ENE1000_MANC_ARP_RES_EN 0x00008000 e1000e_defines.h Enable ARP response Filtering
28827
 E1000_MANC_TCO_RESETE1000_MANC_TCO_RESET 0x00010000 e1000e_defines.h TCO Reset Occurred
28828
 E1000_MANC_RCV_TCO_ENE1000_MANC_RCV_TCO_EN 0x00020000 e1000e_defines.h Receive TCO Packets Enabled
28829
 E1000_MANC_REPORT_STATUSE1000_MANC_REPORT_STATUS 0x00040000 e1000e_defines.h Status Reporting Enabled
28830
 E1000_MANC_RCV_ALLE1000_MANC_RCV_ALL 0x00080000 e1000e_defines.h Receive All Enabled
28831
 E1000_MANC_BLK_PHY_RST_ON_IDEE1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 e1000e_defines.h Block phy resets
28832
 E1000_MANC_EN_MAC_ADDR_FILTERE1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 e1000e_defines.h 　
28833
 E1000_MANC_EN_MNG2HOSTE1000_MANC_EN_MNG2HOST 0x00200000 e1000e_defines.h 　
28834
 E1000_MANC_EN_IP_ADDR_FILTERE1000_MANC_EN_IP_ADDR_FILTER 0x00400000 e1000e_defines.h 　
28835
 E1000_MANC_EN_XSUM_FILTERE1000_MANC_EN_XSUM_FILTER 0x00800000 e1000e_defines.h Enable checksum filtering
28836
 E1000_MANC_BR_ENE1000_MANC_BR_EN 0x01000000 e1000e_defines.h Enable broadcast filtering
28837
 E1000_MANC_SMB_REQE1000_MANC_SMB_REQ 0x01000000 e1000e_defines.h SMBus Request
28838
 E1000_MANC_SMB_GNTE1000_MANC_SMB_GNT 0x02000000 e1000e_defines.h SMBus Grant
28839
 E1000_MANC_SMB_CLK_INE1000_MANC_SMB_CLK_IN 0x04000000 e1000e_defines.h SMBus Clock In
28840
 E1000_MANC_SMB_DATA_INE1000_MANC_SMB_DATA_IN 0x08000000 e1000e_defines.h SMBus Data In
28841
 E1000_MANC_SMB_DATA_OUTE1000_MANC_SMB_DATA_OUT 0x10000000 e1000e_defines.h SMBus Data Out
28842
 E1000_MANC_SMB_CLK_OUTE1000_MANC_SMB_CLK_OUT 0x20000000 e1000e_defines.h SMBus Clock Out
28843
 E1000_MANC_SMB_DATA_OUT_SHIFTE1000_MANC_SMB_DATA_OUT_SHIFT 28 e1000e_defines.h SMBus Data Out Shift
28844
 E1000_MANC_SMB_CLK_OUT_SHIFTE1000_MANC_SMB_CLK_OUT_SHIFT 29 e1000e_defines.h SMBus Clock Out Shift
28845
 E1000_RCTL_RSTE1000_RCTL_RST 0x00000001 e1000e_defines.h Software reset
28846
 E1000_RCTL_ENE1000_RCTL_EN 0x00000002 e1000e_defines.h enable
28847
 E1000_RCTL_SBPE1000_RCTL_SBP 0x00000004 e1000e_defines.h store bad packet
28848
 E1000_RCTL_UPEE1000_RCTL_UPE 0x00000008 e1000e_defines.h unicast promisc enable
28849
 E1000_RCTL_MPEE1000_RCTL_MPE 0x00000010 e1000e_defines.h multicast promisc enable
28850
 E1000_RCTL_LPEE1000_RCTL_LPE 0x00000020 e1000e_defines.h long packet enable
28851
 E1000_RCTL_LBM_NOE1000_RCTL_LBM_NO 0x00000000 e1000e_defines.h no loopback mode
28852
 E1000_RCTL_LBM_MACE1000_RCTL_LBM_MAC 0x00000040 e1000e_defines.h MAC loopback mode
28853
 E1000_RCTL_LBM_SLPE1000_RCTL_LBM_SLP 0x00000080 e1000e_defines.h serial link loopback mode
28854
 E1000_RCTL_LBM_TCVRE1000_RCTL_LBM_TCVR 0x000000C0 e1000e_defines.h tcvr loopback mode
28855
 E1000_RCTL_DTYP_MASKE1000_RCTL_DTYP_MASK 0x00000C00 e1000e_defines.h Descriptor type mask
28856
 E1000_RCTL_DTYP_PSE1000_RCTL_DTYP_PS 0x00000400 e1000e_defines.h Packet Split descriptor
28857
 E1000_RCTL_RDMTS_HALFE1000_RCTL_RDMTS_HALF 0x00000000 e1000e_defines.h rx desc min thresh size
28858
 E1000_RCTL_RDMTS_QUATE1000_RCTL_RDMTS_QUAT 0x00000100 e1000e_defines.h rx desc min thresh size
28859
 E1000_RCTL_RDMTS_EIGTHE1000_RCTL_RDMTS_EIGTH 0x00000200 e1000e_defines.h rx desc min thresh size
28860
 E1000_RCTL_MO_SHIFTE1000_RCTL_MO_SHIFT 12 e1000e_defines.h multicast offset shift
28861
 E1000_RCTL_MO_0E1000_RCTL_MO_0 0x00000000 e1000e_defines.h multicast offset 11:0
28862
 E1000_RCTL_MO_1E1000_RCTL_MO_1 0x00001000 e1000e_defines.h multicast offset 12:1
28863
 E1000_RCTL_MO_2E1000_RCTL_MO_2 0x00002000 e1000e_defines.h multicast offset 13:2
28864
 E1000_RCTL_MO_3E1000_RCTL_MO_3 0x00003000 e1000e_defines.h multicast offset 15:4
28865
 E1000_RCTL_MDRE1000_RCTL_MDR 0x00004000 e1000e_defines.h multicast desc ring 0
28866
 E1000_RCTL_BAME1000_RCTL_BAM 0x00008000 e1000e_defines.h broadcast enable
28867
 E1000_RCTL_SZ_2048E1000_RCTL_SZ_2048 0x00000000 e1000e_defines.h rx buffer size 2048
28868
 E1000_RCTL_SZ_1024E1000_RCTL_SZ_1024 0x00010000 e1000e_defines.h rx buffer size 1024
28869
 E1000_RCTL_SZ_512E1000_RCTL_SZ_512 0x00020000 e1000e_defines.h rx buffer size 512
28870
 E1000_RCTL_SZ_256E1000_RCTL_SZ_256 0x00030000 e1000e_defines.h rx buffer size 256
28871
 E1000_RCTL_SZ_16384E1000_RCTL_SZ_16384 0x00010000 e1000e_defines.h rx buffer size 16384
28872
 E1000_RCTL_SZ_8192E1000_RCTL_SZ_8192 0x00020000 e1000e_defines.h rx buffer size 8192
28873
 E1000_RCTL_SZ_4096E1000_RCTL_SZ_4096 0x00030000 e1000e_defines.h rx buffer size 4096
28874
 E1000_RCTL_VFEE1000_RCTL_VFE 0x00040000 e1000e_defines.h vlan filter enable
28875
 E1000_RCTL_CFIENE1000_RCTL_CFIEN 0x00080000 e1000e_defines.h canonical form enable
28876
 E1000_RCTL_CFIE1000_RCTL_CFI 0x00100000 e1000e_defines.h canonical form indicator
28877
 E1000_RCTL_DPFE1000_RCTL_DPF 0x00400000 e1000e_defines.h discard pause frames
28878
 E1000_RCTL_PMCFE1000_RCTL_PMCF 0x00800000 e1000e_defines.h pass MAC control frames
28879
 E1000_RCTL_BSEXE1000_RCTL_BSEX 0x02000000 e1000e_defines.h Buffer size extension
28880
 E1000_RCTL_SECRCE1000_RCTL_SECRC 0x04000000 e1000e_defines.h Strip Ethernet CRC
28881
 E1000_RCTL_FLXBUF_MASKE1000_RCTL_FLXBUF_MASK 0x78000000 e1000e_defines.h Flexible buffer size
28882
 E1000_RCTL_FLXBUF_SHIFTE1000_RCTL_FLXBUF_SHIFT 27 e1000e_defines.h Flexible buffer shift
28883
 E1000_PSRCTL_BSIZE0_MASKE1000_PSRCTL_BSIZE0_MASK 0x0000007F e1000e_defines.h 　
28884
 E1000_PSRCTL_BSIZE1_MASKE1000_PSRCTL_BSIZE1_MASK 0x00003F00 e1000e_defines.h 　
28885
 E1000_PSRCTL_BSIZE2_MASKE1000_PSRCTL_BSIZE2_MASK 0x003F0000 e1000e_defines.h 　
28886
 E1000_PSRCTL_BSIZE3_MASKE1000_PSRCTL_BSIZE3_MASK 0x3F000000 e1000e_defines.h 　
28887
 E1000_PSRCTL_BSIZE0_SHIFTE1000_PSRCTL_BSIZE0_SHIFT 7 e1000e_defines.h Shift _right_ 7
28888
 E1000_PSRCTL_BSIZE1_SHIFTE1000_PSRCTL_BSIZE1_SHIFT 2 e1000e_defines.h Shift _right_ 2
28889
 E1000_PSRCTL_BSIZE2_SHIFTE1000_PSRCTL_BSIZE2_SHIFT 6 e1000e_defines.h Shift _left_ 6
28890
 E1000_PSRCTL_BSIZE3_SHIFTE1000_PSRCTL_BSIZE3_SHIFT 14 e1000e_defines.h Shift _left_ 14
28891
 E1000_SWFW_EEP_SME1000_SWFW_EEP_SM 0x01 e1000e_defines.h 　
28892
 E1000_SWFW_PHY0_SME1000_SWFW_PHY0_SM 0x02 e1000e_defines.h 　
28893
 E1000_SWFW_PHY1_SME1000_SWFW_PHY1_SM 0x04 e1000e_defines.h 　
28894
 E1000_SWFW_CSR_SME1000_SWFW_CSR_SM 0x08 e1000e_defines.h 　
28895
 E1000_FACTPS_LFSE1000_FACTPS_LFS 0x40000000 e1000e_defines.h LAN Function Select
28896
 E1000_CTRL_FDE1000_CTRL_FD 0x00000001 e1000e_defines.h Full duplex.0=half; 1=full
28897
 E1000_CTRL_BEME1000_CTRL_BEM 0x00000002 e1000e_defines.h Endian Mode.0=little,1=big
28898
 E1000_CTRL_PRIORE1000_CTRL_PRIOR 0x00000004 e1000e_defines.h Priority on PCI. 0=rx,1=fair
28899
 E1000_CTRL_GIO_MASTER_DISABLEE1000_CTRL_GIO_MASTER_DISABLE 0x00000004 e1000e_defines.h Blocks new Master reqs
28900
 E1000_CTRL_LRSTE1000_CTRL_LRST 0x00000008 e1000e_defines.h Link reset. 0=normal,1=reset
28901
 E1000_CTRL_TMEE1000_CTRL_TME 0x00000010 e1000e_defines.h Test mode. 0=normal,1=test
28902
 E1000_CTRL_SLEE1000_CTRL_SLE 0x00000020 e1000e_defines.h Serial Link on 0=dis,1=en
28903
 E1000_CTRL_ASDEE1000_CTRL_ASDE 0x00000020 e1000e_defines.h Auto-speed detect enable
28904
 E1000_CTRL_SLUE1000_CTRL_SLU 0x00000040 e1000e_defines.h Set link up (Force Link)
28905
 E1000_CTRL_ILOSE1000_CTRL_ILOS 0x00000080 e1000e_defines.h Invert Loss-Of Signal
28906
 E1000_CTRL_SPD_SELE1000_CTRL_SPD_SEL 0x00000300 e1000e_defines.h Speed Select Mask
28907
 E1000_CTRL_SPD_10E1000_CTRL_SPD_10 0x00000000 e1000e_defines.h Force 10Mb
28908
 E1000_CTRL_SPD_100E1000_CTRL_SPD_100 0x00000100 e1000e_defines.h Force 100Mb
28909
 E1000_CTRL_SPD_1000E1000_CTRL_SPD_1000 0x00000200 e1000e_defines.h Force 1Gb
28910
 E1000_CTRL_BEM32E1000_CTRL_BEM32 0x00000400 e1000e_defines.h Big Endian 32 mode
28911
 E1000_CTRL_FRCSPDE1000_CTRL_FRCSPD 0x00000800 e1000e_defines.h Force Speed
28912
 E1000_CTRL_FRCDPXE1000_CTRL_FRCDPX 0x00001000 e1000e_defines.h Force Duplex
28913
 E1000_CTRL_D_UD_ENE1000_CTRL_D_UD_EN 0x00002000 e1000e_defines.h Dock/Undock enable
28914
 E1000_CTRL_D_UD_POLARITYE1000_CTRL_D_UD_POLARITY 0x00004000 e1000e_defines.h Defined polarity of Dock/Undock
28915
 E1000_CTRL_FORCE_PHY_RESETE1000_CTRL_FORCE_PHY_RESET 0x00008000 e1000e_defines.h Reset both PHY ports, through
28916
 E1000_CTRL_EXT_LINK_ENE1000_CTRL_EXT_LINK_EN 0x00010000 e1000e_defines.h enable link status from external
28917
 E1000_CTRL_SWDPIN0E1000_CTRL_SWDPIN0 0x00040000 e1000e_defines.h SWDPIN 0 value
28918
 E1000_CTRL_SWDPIN1E1000_CTRL_SWDPIN1 0x00080000 e1000e_defines.h SWDPIN 1 value
28919
 E1000_CTRL_SWDPIN2E1000_CTRL_SWDPIN2 0x00100000 e1000e_defines.h SWDPIN 2 value
28920
 E1000_CTRL_SWDPIN3E1000_CTRL_SWDPIN3 0x00200000 e1000e_defines.h SWDPIN 3 value
28921
 E1000_CTRL_SWDPIO0E1000_CTRL_SWDPIO0 0x00400000 e1000e_defines.h SWDPIN 0 Input or output
28922
 E1000_CTRL_SWDPIO1E1000_CTRL_SWDPIO1 0x00800000 e1000e_defines.h SWDPIN 1 input or output
28923
 E1000_CTRL_SWDPIO2E1000_CTRL_SWDPIO2 0x01000000 e1000e_defines.h SWDPIN 2 input or output
28924
 E1000_CTRL_SWDPIO3E1000_CTRL_SWDPIO3 0x02000000 e1000e_defines.h SWDPIN 3 input or output
28925
 E1000_CTRL_RSTE1000_CTRL_RST 0x04000000 e1000e_defines.h Global reset
28926
 E1000_CTRL_RFCEE1000_CTRL_RFCE 0x08000000 e1000e_defines.h Receive Flow Control enable
28927
 E1000_CTRL_TFCEE1000_CTRL_TFCE 0x10000000 e1000e_defines.h Transmit flow control enable
28928
 E1000_CTRL_RTEE1000_CTRL_RTE 0x20000000 e1000e_defines.h Routing tag enable
28929
 E1000_CTRL_VMEE1000_CTRL_VME 0x40000000 e1000e_defines.h IEEE VLAN mode enable
28930
 E1000_CTRL_PHY_RSTE1000_CTRL_PHY_RST 0x80000000 e1000e_defines.h PHY Reset
28931
 E1000_CTRL_SW2FW_INTE1000_CTRL_SW2FW_INT 0x02000000 e1000e_defines.h Initiate an interrupt to ME
28932
 E1000_CTRL_I2C_ENAE1000_CTRL_I2C_ENA 0x02000000 e1000e_defines.h I2C enable
28933
 E1000_CTRL_PHY_RESET_DIRE1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 e1000e_defines.h 　
28934
 E1000_CTRL_PHY_RESETE1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 e1000e_defines.h 　
28935
 E1000_CTRL_MDIO_DIRE1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 e1000e_defines.h 　
28936
 E1000_CTRL_MDIOE1000_CTRL_MDIO E1000_CTRL_SWDPIN2 e1000e_defines.h 　
28937
 E1000_CTRL_MDC_DIRE1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 e1000e_defines.h 　
28938
 E1000_CTRL_MDCE1000_CTRL_MDC E1000_CTRL_SWDPIN3 e1000e_defines.h 　
28939
 E1000_CTRL_PHY_RESET_DIR4E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR e1000e_defines.h 　
28940
 E1000_CTRL_PHY_RESET4E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA e1000e_defines.h 　
28941
 E1000_CONNSW_ENRGSRCE1000_CONNSW_ENRGSRC 0x4 e1000e_defines.h 　
28942
 E1000_PCS_CFG_PCS_ENE1000_PCS_CFG_PCS_EN 8 e1000e_defines.h 　
28943
 E1000_PCS_LCTL_FLV_LINK_UPE1000_PCS_LCTL_FLV_LINK_UP 1 e1000e_defines.h 　
28944
 E1000_PCS_LCTL_FSV_10E1000_PCS_LCTL_FSV_10 0 e1000e_defines.h 　
28945
 E1000_PCS_LCTL_FSV_100E1000_PCS_LCTL_FSV_100 2 e1000e_defines.h 　
28946
 E1000_PCS_LCTL_FSV_1000E1000_PCS_LCTL_FSV_1000 4 e1000e_defines.h 　
28947
 E1000_PCS_LCTL_FDV_FULLE1000_PCS_LCTL_FDV_FULL 8 e1000e_defines.h 　
28948
 E1000_PCS_LCTL_FSDE1000_PCS_LCTL_FSD 0x10 e1000e_defines.h 　
28949
 E1000_PCS_LCTL_FORCE_LINKE1000_PCS_LCTL_FORCE_LINK 0x20 e1000e_defines.h 　
28950
 E1000_PCS_LCTL_LOW_LINK_LATCHE1000_PCS_LCTL_LOW_LINK_LATCH 0x40 e1000e_defines.h 　
28951
 E1000_PCS_LCTL_FORCE_FCTRLE1000_PCS_LCTL_FORCE_FCTRL 0x80 e1000e_defines.h 　
28952
 E1000_PCS_LCTL_AN_ENABLEE1000_PCS_LCTL_AN_ENABLE 0x10000 e1000e_defines.h 　
28953
 E1000_PCS_LCTL_AN_RESTARTE1000_PCS_LCTL_AN_RESTART 0x20000 e1000e_defines.h 　
28954
 E1000_PCS_LCTL_AN_TIMEOUTE1000_PCS_LCTL_AN_TIMEOUT 0x40000 e1000e_defines.h 　
28955
 E1000_PCS_LCTL_AN_SGMII_BYPASSE1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 e1000e_defines.h 　
28956
 E1000_PCS_LCTL_AN_SGMII_TRIGGERE1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 e1000e_defines.h 　
28957
 E1000_PCS_LCTL_FAST_LINK_TIMERE1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 e1000e_defines.h 　
28958
 E1000_PCS_LCTL_LINK_OK_FIXE1000_PCS_LCTL_LINK_OK_FIX 0x2000000 e1000e_defines.h 　
28959
 E1000_PCS_LCTL_CRS_ON_NIE1000_PCS_LCTL_CRS_ON_NI 0x4000000 e1000e_defines.h 　
28960
 E1000_ENABLE_SERDES_LOOPBACKE1000_ENABLE_SERDES_LOOPBACK 0x0410 e1000e_defines.h 　
28961
 E1000_PCS_LSTS_LINK_OKE1000_PCS_LSTS_LINK_OK 1 e1000e_defines.h 　
28962
 E1000_PCS_LSTS_SPEED_10E1000_PCS_LSTS_SPEED_10 0 e1000e_defines.h 　
28963
 E1000_PCS_LSTS_SPEED_100E1000_PCS_LSTS_SPEED_100 2 e1000e_defines.h 　
28964
 E1000_PCS_LSTS_SPEED_1000E1000_PCS_LSTS_SPEED_1000 4 e1000e_defines.h 　
28965
 E1000_PCS_LSTS_DUPLEX_FULLE1000_PCS_LSTS_DUPLEX_FULL 8 e1000e_defines.h 　
28966
 E1000_PCS_LSTS_SYNK_OKE1000_PCS_LSTS_SYNK_OK 0x10 e1000e_defines.h 　
28967
 E1000_PCS_LSTS_AN_COMPLETEE1000_PCS_LSTS_AN_COMPLETE 0x10000 e1000e_defines.h 　
28968
 E1000_PCS_LSTS_AN_PAGE_RXE1000_PCS_LSTS_AN_PAGE_RX 0x20000 e1000e_defines.h 　
28969
 E1000_PCS_LSTS_AN_TIMED_OUTE1000_PCS_LSTS_AN_TIMED_OUT 0x40000 e1000e_defines.h 　
28970
 E1000_PCS_LSTS_AN_REMOTE_FAULTE1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 e1000e_defines.h 　
28971
 E1000_PCS_LSTS_AN_ERROR_RWSE1000_PCS_LSTS_AN_ERROR_RWS 0x100000 e1000e_defines.h 　
28972
 E1000_STATUS_FDE1000_STATUS_FD 0x00000001 e1000e_defines.h Full duplex.0=half,1=full
28973
 E1000_STATUS_LUE1000_STATUS_LU 0x00000002 e1000e_defines.h Link up.0=no,1=link
28974
 E1000_STATUS_FUNC_MASKE1000_STATUS_FUNC_MASK 0x0000000C e1000e_defines.h PCI Function Mask
28975
 E1000_STATUS_FUNC_SHIFTE1000_STATUS_FUNC_SHIFT 2 e1000e_defines.h 　
28976
 E1000_STATUS_FUNC_0E1000_STATUS_FUNC_0 0x00000000 e1000e_defines.h Function 0
28977
 E1000_STATUS_FUNC_1E1000_STATUS_FUNC_1 0x00000004 e1000e_defines.h Function 1
28978
 E1000_STATUS_TXOFFE1000_STATUS_TXOFF 0x00000010 e1000e_defines.h transmission paused
28979
 E1000_STATUS_TBIMODEE1000_STATUS_TBIMODE 0x00000020 e1000e_defines.h TBI mode
28980
 E1000_STATUS_SPEED_MASKE1000_STATUS_SPEED_MASK 0x000000C0 e1000e_defines.h 　
28981
 E1000_STATUS_SPEED_10E1000_STATUS_SPEED_10 0x00000000 e1000e_defines.h Speed 10Mb/s
28982
 E1000_STATUS_SPEED_100E1000_STATUS_SPEED_100 0x00000040 e1000e_defines.h Speed 100Mb/s
28983
 E1000_STATUS_SPEED_1000E1000_STATUS_SPEED_1000 0x00000080 e1000e_defines.h Speed 1000Mb/s
28984
 E1000_STATUS_LAN_INIT_DONEE1000_STATUS_LAN_INIT_DONE 0x00000200 e1000e_defines.h Lan Init Completion by NVM
28985
 E1000_STATUS_ASDVE1000_STATUS_ASDV 0x00000300 e1000e_defines.h Auto speed detect value
28986
 E1000_STATUS_PHYRAE1000_STATUS_PHYRA 0x00000400 e1000e_defines.h PHY Reset Asserted
28987
 E1000_STATUS_DOCK_CIE1000_STATUS_DOCK_CI 0x00000800 e1000e_defines.h Change in Dock/Undock state.
28988
 E1000_STATUS_GIO_MASTER_ENABLEE1000_STATUS_GIO_MASTER_ENABLE 0x00080000 e1000e_defines.h Master request status
28989
 E1000_STATUS_MTXCKOKE1000_STATUS_MTXCKOK 0x00000400 e1000e_defines.h MTX clock running OK
28990
 E1000_STATUS_PCI66E1000_STATUS_PCI66 0x00000800 e1000e_defines.h In 66Mhz slot
28991
 E1000_STATUS_BUS64E1000_STATUS_BUS64 0x00001000 e1000e_defines.h In 64 bit slot
28992
 E1000_STATUS_PCIX_MODEE1000_STATUS_PCIX_MODE 0x00002000 e1000e_defines.h PCI-X mode
28993
 E1000_STATUS_PCIX_SPEEDE1000_STATUS_PCIX_SPEED 0x0000C000 e1000e_defines.h PCI-X bus speed
28994
 E1000_STATUS_BMC_SKU_0E1000_STATUS_BMC_SKU_0 0x00100000 e1000e_defines.h BMC USB redirect disabled
28995
 E1000_STATUS_BMC_SKU_1E1000_STATUS_BMC_SKU_1 0x00200000 e1000e_defines.h BMC SRAM disabled
28996
 E1000_STATUS_BMC_SKU_2E1000_STATUS_BMC_SKU_2 0x00400000 e1000e_defines.h BMC SDRAM disabled
28997
 E1000_STATUS_BMC_CRYPTOE1000_STATUS_BMC_CRYPTO 0x00800000 e1000e_defines.h BMC crypto disabled
28998
 E1000_STATUS_BMC_LITEE1000_STATUS_BMC_LITE 0x01000000 e1000e_defines.h BMC external code execution
28999
 E1000_STATUS_RGMII_ENABLEE1000_STATUS_RGMII_ENABLE 0x02000000 e1000e_defines.h RGMII disabled
29000
 E1000_STATUS_FUSE_8E1000_STATUS_FUSE_8 0x04000000 e1000e_defines.h 　
29001
 E1000_STATUS_FUSE_9E1000_STATUS_FUSE_9 0x08000000 e1000e_defines.h 　
29002
 E1000_STATUS_SERDES0_DISE1000_STATUS_SERDES0_DIS 0x10000000 e1000e_defines.h SERDES disabled on port 0
29003
 E1000_STATUS_SERDES1_DISE1000_STATUS_SERDES1_DIS 0x20000000 e1000e_defines.h SERDES disabled on port 1
29004
 E1000_STATUS_PCIX_SPEED_66E1000_STATUS_PCIX_SPEED_66 0x00000000 e1000e_defines.h PCI-X bus speed 50-66 MHz
29005
 E1000_STATUS_PCIX_SPEED_100E1000_STATUS_PCIX_SPEED_100 0x00004000 e1000e_defines.h PCI-X bus speed 66-100 MHz
29006
 E1000_STATUS_PCIX_SPEED_133E1000_STATUS_PCIX_SPEED_133 0x00008000 e1000e_defines.h PCI-X bus speed 100-133 MHz
29007
 SPEED_10SPEED_10 10 e1000e_defines.h 　
29008
 SPEED_100SPEED_100 100 e1000e_defines.h 　
29009
 SPEED_1000SPEED_1000 1000 e1000e_defines.h 　
29010
 HALF_DUPLEXHALF_DUPLEX 1 e1000e_defines.h 　
29011
 FULL_DUPLEXFULL_DUPLEX 2 e1000e_defines.h 　
29012
 PHY_FORCE_TIMEPHY_FORCE_TIME 20 e1000e_defines.h 　
29013
 ADVERTISE_10_HALFADVERTISE_10_HALF 0x0001 e1000e_defines.h 　
29014
 ADVERTISE_10_FULLADVERTISE_10_FULL 0x0002 e1000e_defines.h 　
29015
 ADVERTISE_100_HALFADVERTISE_100_HALF 0x0004 e1000e_defines.h 　
29016
 ADVERTISE_100_FULLADVERTISE_100_FULL 0x0008 e1000e_defines.h 　
29017
 ADVERTISE_1000_HALFADVERTISE_1000_HALF 0x0010 e1000e_defines.h Not used, just FYI
29018
 ADVERTISE_1000_FULLADVERTISE_1000_FULL 0x0020 e1000e_defines.h 　
29019
 E1000_ALL_SPEED_DUPLEXE1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) e1000e_defines.h 　
29020
 E1000_ALL_NOT_GIGE1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL) e1000e_defines.h 　
29021
 E1000_ALL_100_SPEEDE1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) e1000e_defines.h 　
29022
 E1000_ALL_10_SPEEDE1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) e1000e_defines.h 　
29023
 E1000_ALL_FULL_DUPLEXE1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) e1000e_defines.h 　
29024
 E1000_ALL_HALF_DUPLEXE1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) e1000e_defines.h 　
29025
 AUTONEG_ADVERTISE_SPEED_DEFAULTAUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX e1000e_defines.h 　
29026
 E1000_PHY_LED0_MODE_MASKE1000_PHY_LED0_MODE_MASK 0x00000007 e1000e_defines.h 　
29027
 E1000_PHY_LED0_IVRTE1000_PHY_LED0_IVRT 0x00000008 e1000e_defines.h 　
29028
 E1000_PHY_LED0_BLINKE1000_PHY_LED0_BLINK 0x00000010 e1000e_defines.h 　
29029
 E1000_PHY_LED0_MASKE1000_PHY_LED0_MASK 0x0000001F e1000e_defines.h 　
29030
 E1000_LEDCTL_LED0_MODE_MASKE1000_LEDCTL_LED0_MODE_MASK 0x0000000F e1000e_defines.h 　
29031
 E1000_LEDCTL_LED0_MODE_SHIFTE1000_LEDCTL_LED0_MODE_SHIFT 0 e1000e_defines.h 　
29032
 E1000_LEDCTL_LED0_BLINK_RATEE1000_LEDCTL_LED0_BLINK_RATE 0x00000020 e1000e_defines.h 　
29033
 E1000_LEDCTL_LED0_IVRTE1000_LEDCTL_LED0_IVRT 0x00000040 e1000e_defines.h 　
29034
 E1000_LEDCTL_LED0_BLINKE1000_LEDCTL_LED0_BLINK 0x00000080 e1000e_defines.h 　
29035
 E1000_LEDCTL_LED1_MODE_MASKE1000_LEDCTL_LED1_MODE_MASK 0x00000F00 e1000e_defines.h 　
29036
 E1000_LEDCTL_LED1_MODE_SHIFTE1000_LEDCTL_LED1_MODE_SHIFT 8 e1000e_defines.h 　
29037
 E1000_LEDCTL_LED1_BLINK_RATEE1000_LEDCTL_LED1_BLINK_RATE 0x00002000 e1000e_defines.h 　
29038
 E1000_LEDCTL_LED1_IVRTE1000_LEDCTL_LED1_IVRT 0x00004000 e1000e_defines.h 　
29039
 E1000_LEDCTL_LED1_BLINKE1000_LEDCTL_LED1_BLINK 0x00008000 e1000e_defines.h 　
29040
 E1000_LEDCTL_LED2_MODE_MASKE1000_LEDCTL_LED2_MODE_MASK 0x000F0000 e1000e_defines.h 　
29041
 E1000_LEDCTL_LED2_MODE_SHIFTE1000_LEDCTL_LED2_MODE_SHIFT 16 e1000e_defines.h 　
29042
 E1000_LEDCTL_LED2_BLINK_RATEE1000_LEDCTL_LED2_BLINK_RATE 0x00200000 e1000e_defines.h 　
29043
 E1000_LEDCTL_LED2_IVRTE1000_LEDCTL_LED2_IVRT 0x00400000 e1000e_defines.h 　
29044
 E1000_LEDCTL_LED2_BLINKE1000_LEDCTL_LED2_BLINK 0x00800000 e1000e_defines.h 　
29045
 E1000_LEDCTL_LED3_MODE_MASKE1000_LEDCTL_LED3_MODE_MASK 0x0F000000 e1000e_defines.h 　
29046
 E1000_LEDCTL_LED3_MODE_SHIFTE1000_LEDCTL_LED3_MODE_SHIFT 24 e1000e_defines.h 　
29047
 E1000_LEDCTL_LED3_BLINK_RATEE1000_LEDCTL_LED3_BLINK_RATE 0x20000000 e1000e_defines.h 　
29048
 E1000_LEDCTL_LED3_IVRTE1000_LEDCTL_LED3_IVRT 0x40000000 e1000e_defines.h 　
29049
 E1000_LEDCTL_LED3_BLINKE1000_LEDCTL_LED3_BLINK 0x80000000 e1000e_defines.h 　
29050
 E1000_LEDCTL_MODE_LINK_10_1000E1000_LEDCTL_MODE_LINK_10_1000 0x0 e1000e_defines.h 　
29051
 E1000_LEDCTL_MODE_LINK_100_1000E1000_LEDCTL_MODE_LINK_100_1000 0x1 e1000e_defines.h 　
29052
 E1000_LEDCTL_MODE_LINK_UPE1000_LEDCTL_MODE_LINK_UP 0x2 e1000e_defines.h 　
29053
 E1000_LEDCTL_MODE_ACTIVITYE1000_LEDCTL_MODE_ACTIVITY 0x3 e1000e_defines.h 　
29054
 E1000_LEDCTL_MODE_LINK_ACTIVITYE1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 e1000e_defines.h 　
29055
 E1000_LEDCTL_MODE_LINK_10E1000_LEDCTL_MODE_LINK_10 0x5 e1000e_defines.h 　
29056
 E1000_LEDCTL_MODE_LINK_100E1000_LEDCTL_MODE_LINK_100 0x6 e1000e_defines.h 　
29057
 E1000_LEDCTL_MODE_LINK_1000E1000_LEDCTL_MODE_LINK_1000 0x7 e1000e_defines.h 　
29058
 E1000_LEDCTL_MODE_PCIX_MODEE1000_LEDCTL_MODE_PCIX_MODE 0x8 e1000e_defines.h 　
29059
 E1000_LEDCTL_MODE_FULL_DUPLEXE1000_LEDCTL_MODE_FULL_DUPLEX 0x9 e1000e_defines.h 　
29060
 E1000_LEDCTL_MODE_COLLISIONE1000_LEDCTL_MODE_COLLISION 0xA e1000e_defines.h 　
29061
 E1000_LEDCTL_MODE_BUS_SPEEDE1000_LEDCTL_MODE_BUS_SPEED 0xB e1000e_defines.h 　
29062
 E1000_LEDCTL_MODE_BUS_SIZEE1000_LEDCTL_MODE_BUS_SIZE 0xC e1000e_defines.h 　
29063
 E1000_LEDCTL_MODE_PAUSEDE1000_LEDCTL_MODE_PAUSED 0xD e1000e_defines.h 　
29064
 E1000_LEDCTL_MODE_LED_ONE1000_LEDCTL_MODE_LED_ON 0xE e1000e_defines.h 　
29065
 E1000_LEDCTL_MODE_LED_OFFE1000_LEDCTL_MODE_LED_OFF 0xF e1000e_defines.h 　
29066
 E1000_TXD_DTYP_DE1000_TXD_DTYP_D 0x00100000 e1000e_defines.h Data Descriptor
29067
 E1000_TXD_DTYP_CE1000_TXD_DTYP_C 0x00000000 e1000e_defines.h Context Descriptor
29068
 E1000_TXD_POPTS_SHIFTE1000_TXD_POPTS_SHIFT 8 e1000e_defines.h POPTS shift
29069
 E1000_TXD_POPTS_IXSME1000_TXD_POPTS_IXSM 0x01 e1000e_defines.h Insert IP checksum
29070
 E1000_TXD_POPTS_TXSME1000_TXD_POPTS_TXSM 0x02 e1000e_defines.h Insert TCP/UDP checksum
29071
 E1000_TXD_CMD_EOPE1000_TXD_CMD_EOP 0x01000000 e1000e_defines.h End of Packet
29072
 E1000_TXD_CMD_IFCSE1000_TXD_CMD_IFCS 0x02000000 e1000e_defines.h Insert FCS (Ethernet CRC)
29073
 E1000_TXD_CMD_ICE1000_TXD_CMD_IC 0x04000000 e1000e_defines.h Insert Checksum
29074
 E1000_TXD_CMD_RSE1000_TXD_CMD_RS 0x08000000 e1000e_defines.h Report Status
29075
 E1000_TXD_CMD_RPSE1000_TXD_CMD_RPS 0x10000000 e1000e_defines.h Report Packet Sent
29076
 E1000_TXD_CMD_DEXTE1000_TXD_CMD_DEXT 0x20000000 e1000e_defines.h Descriptor extension (0 = legacy)
29077
 E1000_TXD_CMD_VLEE1000_TXD_CMD_VLE 0x40000000 e1000e_defines.h Add VLAN tag
29078
 E1000_TXD_CMD_IDEE1000_TXD_CMD_IDE 0x80000000 e1000e_defines.h Enable Tidv register
29079
 E1000_TXD_STAT_DDE1000_TXD_STAT_DD 0x00000001 e1000e_defines.h Descriptor Done
29080
 E1000_TXD_STAT_ECE1000_TXD_STAT_EC 0x00000002 e1000e_defines.h Excess Collisions
29081
 E1000_TXD_STAT_LCE1000_TXD_STAT_LC 0x00000004 e1000e_defines.h Late Collisions
29082
 E1000_TXD_STAT_TUE1000_TXD_STAT_TU 0x00000008 e1000e_defines.h Transmit underrun
29083
 E1000_TXD_CMD_TCPE1000_TXD_CMD_TCP 0x01000000 e1000e_defines.h TCP packet
29084
 E1000_TXD_CMD_IPE1000_TXD_CMD_IP 0x02000000 e1000e_defines.h IP packet
29085
 E1000_TXD_CMD_TSEE1000_TXD_CMD_TSE 0x04000000 e1000e_defines.h TCP Seg enable
29086
 E1000_TXD_STAT_TCE1000_TXD_STAT_TC 0x00000004 e1000e_defines.h Tx Underrun
29087
 E1000_TXD_CMD_LINKSECE1000_TXD_CMD_LINKSEC 0x10000000 e1000e_defines.h Apply LinkSec on packet
29088
 E1000_TXD_EXTCMD_TSTAMPE1000_TXD_EXTCMD_TSTAMP 0x00000010 e1000e_defines.h IEEE1588 Timestamp packet
29089
 E1000_TCTL_RSTE1000_TCTL_RST 0x00000001 e1000e_defines.h software reset
29090
 E1000_TCTL_ENE1000_TCTL_EN 0x00000002 e1000e_defines.h enable tx
29091
 E1000_TCTL_BCEE1000_TCTL_BCE 0x00000004 e1000e_defines.h busy check enable
29092
 E1000_TCTL_PSPE1000_TCTL_PSP 0x00000008 e1000e_defines.h pad short packets
29093
 E1000_TCTL_CTE1000_TCTL_CT 0x00000ff0 e1000e_defines.h collision threshold
29094
 E1000_TCTL_COLDE1000_TCTL_COLD 0x003ff000 e1000e_defines.h collision distance
29095
 E1000_TCTL_SWXOFFE1000_TCTL_SWXOFF 0x00400000 e1000e_defines.h SW Xoff transmission
29096
 E1000_TCTL_PBEE1000_TCTL_PBE 0x00800000 e1000e_defines.h Packet Burst Enable
29097
 E1000_TCTL_RTLCE1000_TCTL_RTLC 0x01000000 e1000e_defines.h Re-transmit on late collision
29098
 E1000_TCTL_NRTUE1000_TCTL_NRTU 0x02000000 e1000e_defines.h No Re-transmit on underrun
29099
 E1000_TCTL_MULRE1000_TCTL_MULR 0x10000000 e1000e_defines.h Multiple request support
29100
 E1000_TARC0_ENABLEE1000_TARC0_ENABLE 0x00000400 e1000e_defines.h Enable Tx Queue 0
29101
 E1000_SCTL_DISABLE_SERDES_LOOPBE1000_SCTL_DISABLE_SERDES_LOOPB 0x0400 e1000e_defines.h 　
29102
 E1000_RXCSUM_PCSS_MASKE1000_RXCSUM_PCSS_MASK 0x000000FF e1000e_defines.h Packet Checksum Start
29103
 E1000_RXCSUM_IPOFLE1000_RXCSUM_IPOFL 0x00000100 e1000e_defines.h IPv4 checksum offload
29104
 E1000_RXCSUM_TUOFLE1000_RXCSUM_TUOFL 0x00000200 e1000e_defines.h TCP / UDP checksum offload
29105
 E1000_RXCSUM_IPV6OFLE1000_RXCSUM_IPV6OFL 0x00000400 e1000e_defines.h IPv6 checksum offload
29106
 E1000_RXCSUM_CRCOFLE1000_RXCSUM_CRCOFL 0x00000800 e1000e_defines.h CRC32 offload enable
29107
 E1000_RXCSUM_IPPCSEE1000_RXCSUM_IPPCSE 0x00001000 e1000e_defines.h IP payload checksum enable
29108
 E1000_RXCSUM_PCSDE1000_RXCSUM_PCSD 0x00002000 e1000e_defines.h packet checksum disabled
29109
 E1000_RFCTL_ISCSI_DISE1000_RFCTL_ISCSI_DIS 0x00000001 e1000e_defines.h 　
29110
 E1000_RFCTL_ISCSI_DWC_MASKE1000_RFCTL_ISCSI_DWC_MASK 0x0000003E e1000e_defines.h 　
29111
 E1000_RFCTL_ISCSI_DWC_SHIFTE1000_RFCTL_ISCSI_DWC_SHIFT 1 e1000e_defines.h 　
29112
 E1000_RFCTL_NFSW_DISE1000_RFCTL_NFSW_DIS 0x00000040 e1000e_defines.h 　
29113
 E1000_RFCTL_NFSR_DISE1000_RFCTL_NFSR_DIS 0x00000080 e1000e_defines.h 　
29114
 E1000_RFCTL_NFS_VER_MASKE1000_RFCTL_NFS_VER_MASK 0x00000300 e1000e_defines.h 　
29115
 E1000_RFCTL_NFS_VER_SHIFTE1000_RFCTL_NFS_VER_SHIFT 8 e1000e_defines.h 　
29116
 E1000_RFCTL_IPV6_DISE1000_RFCTL_IPV6_DIS 0x00000400 e1000e_defines.h 　
29117
 E1000_RFCTL_IPV6_XSUM_DISE1000_RFCTL_IPV6_XSUM_DIS 0x00000800 e1000e_defines.h 　
29118
 E1000_RFCTL_ACK_DISE1000_RFCTL_ACK_DIS 0x00001000 e1000e_defines.h 　
29119
 E1000_RFCTL_ACKD_DISE1000_RFCTL_ACKD_DIS 0x00002000 e1000e_defines.h 　
29120
 E1000_RFCTL_IPFRSP_DISE1000_RFCTL_IPFRSP_DIS 0x00004000 e1000e_defines.h 　
29121
 E1000_RFCTL_EXTENE1000_RFCTL_EXTEN 0x00008000 e1000e_defines.h 　
29122
 E1000_RFCTL_IPV6_EX_DISE1000_RFCTL_IPV6_EX_DIS 0x00010000 e1000e_defines.h 　
29123
 E1000_RFCTL_NEW_IPV6_EXT_DISE1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 e1000e_defines.h 　
29124
 E1000_RFCTL_LEFE1000_RFCTL_LEF 0x00040000 e1000e_defines.h 　
29125
 E1000_COLLISION_THRESHOLDE1000_COLLISION_THRESHOLD 15 e1000e_defines.h 　
29126
 E1000_CT_SHIFTE1000_CT_SHIFT 4 e1000e_defines.h 　
29127
 E1000_COLLISION_DISTANCEE1000_COLLISION_DISTANCE 63 e1000e_defines.h 　
29128
 E1000_COLD_SHIFTE1000_COLD_SHIFT 12 e1000e_defines.h 　
29129
 DEFAULT_82543_TIPG_IPGT_FIBERDEFAULT_82543_TIPG_IPGT_FIBER 9 e1000e_defines.h 　
29130
 DEFAULT_82543_TIPG_IPGT_COPPERDEFAULT_82543_TIPG_IPGT_COPPER 8 e1000e_defines.h 　
29131
 E1000_TIPG_IPGT_MASKE1000_TIPG_IPGT_MASK 0x000003FF e1000e_defines.h 　
29132
 E1000_TIPG_IPGR1_MASKE1000_TIPG_IPGR1_MASK 0x000FFC00 e1000e_defines.h 　
29133
 E1000_TIPG_IPGR2_MASKE1000_TIPG_IPGR2_MASK 0x3FF00000 e1000e_defines.h 　
29134
 DEFAULT_82543_TIPG_IPGR1DEFAULT_82543_TIPG_IPGR1 8 e1000e_defines.h 　
29135
 E1000_TIPG_IPGR1_SHIFTE1000_TIPG_IPGR1_SHIFT 10 e1000e_defines.h 　
29136
 DEFAULT_82543_TIPG_IPGR2DEFAULT_82543_TIPG_IPGR2 6 e1000e_defines.h 　
29137
 DEFAULT_80003ES2LAN_TIPG_IPGR2DEFAULT_80003ES2LAN_TIPG_IPGR2 7 e1000e_defines.h 　
29138
 E1000_TIPG_IPGR2_SHIFTE1000_TIPG_IPGR2_SHIFT 20 e1000e_defines.h 　
29139
 ETHERNET_IEEE_VLAN_TYPEETHERNET_IEEE_VLAN_TYPE 0x8100 e1000e_defines.h 802.3ac packet
29140
 ETHERNET_FCS_SIZEETHERNET_FCS_SIZE 4 e1000e_defines.h 　
29141
 MAX_JUMBO_FRAME_SIZEMAX_JUMBO_FRAME_SIZE 0x3F00 e1000e_defines.h 　
29142
 E1000_EXTCNF_CTRL_MDIO_SW_OWNERE1000_EXTCNF_CTRL_MDIO_SW_OWNER 0x00000020 e1000e_defines.h 　
29143
 E1000_EXTCNF_CTRL_LCD_WRITE_ENAE1000_EXTCNF_CTRL_LCD_WRITE_ENA 0x00000001 e1000e_defines.h 　
29144
 E1000_EXTCNF_CTRL_OEM_WRITE_ENAE1000_EXTCNF_CTRL_OEM_WRITE_ENA 0x00000008 e1000e_defines.h 　
29145
 E1000_EXTCNF_CTRL_SWFLAGE1000_EXTCNF_CTRL_SWFLAG 0x00000020 e1000e_defines.h 　
29146
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 0x00FF0000 e1000e_defines.h 　
29147
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 16 e1000e_defines.h 　
29148
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 0x0FFF0000 e1000e_defines.h 　
29149
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 16 e1000e_defines.h 　
29150
 E1000_PHY_CTRL_SPD_ENE1000_PHY_CTRL_SPD_EN 0x00000001 e1000e_defines.h 　
29151
 E1000_PHY_CTRL_D0A_LPLUE1000_PHY_CTRL_D0A_LPLU 0x00000002 e1000e_defines.h 　
29152
 E1000_PHY_CTRL_NOND0A_LPLUE1000_PHY_CTRL_NOND0A_LPLU 0x00000004 e1000e_defines.h 　
29153
 E1000_PHY_CTRL_NOND0A_GBE_DISABE1000_PHY_CTRL_NOND0A_GBE_DISAB 0x00000008 e1000e_defines.h 　
29154
 E1000_PHY_CTRL_GBE_DISABLEE1000_PHY_CTRL_GBE_DISABLE 0x00000040 e1000e_defines.h 　
29155
 E1000_KABGTXD_BGSQLBIASE1000_KABGTXD_BGSQLBIAS 0x00050000 e1000e_defines.h 　
29156
 E1000_PBA_6KE1000_PBA_6K 0x0006 e1000e_defines.h 6KB
29157
 E1000_PBA_8KE1000_PBA_8K 0x0008 e1000e_defines.h 8KB
29158
 E1000_PBA_10KE1000_PBA_10K 0x000A e1000e_defines.h 10KB
29159
 E1000_PBA_12KE1000_PBA_12K 0x000C e1000e_defines.h 12KB
29160
 E1000_PBA_14KE1000_PBA_14K 0x000E e1000e_defines.h 14KB
29161
 E1000_PBA_16KE1000_PBA_16K 0x0010 e1000e_defines.h 16KB
29162
 E1000_PBA_18KE1000_PBA_18K 0x0012 e1000e_defines.h 　
29163
 E1000_PBA_20KE1000_PBA_20K 0x0014 e1000e_defines.h 　
29164
 E1000_PBA_22KE1000_PBA_22K 0x0016 e1000e_defines.h 　
29165
 E1000_PBA_24KE1000_PBA_24K 0x0018 e1000e_defines.h 　
29166
 E1000_PBA_26KE1000_PBA_26K 0x001A e1000e_defines.h 　
29167
 E1000_PBA_30KE1000_PBA_30K 0x001E e1000e_defines.h 　
29168
 E1000_PBA_32KE1000_PBA_32K 0x0020 e1000e_defines.h 　
29169
 E1000_PBA_34KE1000_PBA_34K 0x0022 e1000e_defines.h 　
29170
 E1000_PBA_35KE1000_PBA_35K 0x0023 e1000e_defines.h 　
29171
 E1000_PBA_38KE1000_PBA_38K 0x0026 e1000e_defines.h 　
29172
 E1000_PBA_40KE1000_PBA_40K 0x0028 e1000e_defines.h 　
29173
 E1000_PBA_48KE1000_PBA_48K 0x0030 e1000e_defines.h 48KB
29174
 E1000_PBA_64KE1000_PBA_64K 0x0040 e1000e_defines.h 64KB
29175
 E1000_PBS_16KE1000_PBS_16K E1000_PBA_16K e1000e_defines.h 　
29176
 E1000_PBS_24KE1000_PBS_24K E1000_PBA_24K e1000e_defines.h 　
29177
 IFS_MAXIFS_MAX 80 e1000e_defines.h 　
29178
 IFS_MINIFS_MIN 40 e1000e_defines.h 　
29179
 IFS_RATIOIFS_RATIO 4 e1000e_defines.h 　
29180
 IFS_STEPIFS_STEP 10 e1000e_defines.h 　
29181
 MIN_NUM_XMITSMIN_NUM_XMITS 1000 e1000e_defines.h 　
29182
 E1000_SWSM_SMBIE1000_SWSM_SMBI 0x00000001 e1000e_defines.h Driver Semaphore bit
29183
 E1000_SWSM_SWESMBIE1000_SWSM_SWESMBI 0x00000002 e1000e_defines.h FW Semaphore bit
29184
 E1000_SWSM_WMNGE1000_SWSM_WMNG 0x00000004 e1000e_defines.h Wake MNG Clock
29185
 E1000_SWSM_DRV_LOADE1000_SWSM_DRV_LOAD 0x00000008 e1000e_defines.h Driver Loaded Bit
29186
 E1000_SWSM2_LOCKE1000_SWSM2_LOCK 0x00000002 e1000e_defines.h Secondary driver semaphore bit
29187
 E1000_ICR_TXDWE1000_ICR_TXDW 0x00000001 e1000e_defines.h Transmit desc written back
29188
 E1000_ICR_TXQEE1000_ICR_TXQE 0x00000002 e1000e_defines.h Transmit Queue empty
29189
 E1000_ICR_LSCE1000_ICR_LSC 0x00000004 e1000e_defines.h Link Status Change
29190
 E1000_ICR_RXSEQE1000_ICR_RXSEQ 0x00000008 e1000e_defines.h rx sequence error
29191
 E1000_ICR_RXDMT0E1000_ICR_RXDMT0 0x00000010 e1000e_defines.h rx desc min. threshold (0)
29192
 E1000_ICR_RXOE1000_ICR_RXO 0x00000040 e1000e_defines.h rx overrun
29193
 E1000_ICR_RXT0E1000_ICR_RXT0 0x00000080 e1000e_defines.h rx timer intr (ring 0)
29194
 E1000_ICR_VMMBE1000_ICR_VMMB 0x00000100 e1000e_defines.h VM MB event
29195
 E1000_ICR_MDACE1000_ICR_MDAC 0x00000200 e1000e_defines.h MDIO access complete
29196
 E1000_ICR_RXCFGE1000_ICR_RXCFG 0x00000400 e1000e_defines.h Rx /c/ ordered set
29197
 E1000_ICR_GPI_EN0E1000_ICR_GPI_EN0 0x00000800 e1000e_defines.h GP Int 0
29198
 E1000_ICR_GPI_EN1E1000_ICR_GPI_EN1 0x00001000 e1000e_defines.h GP Int 1
29199
 E1000_ICR_GPI_EN2E1000_ICR_GPI_EN2 0x00002000 e1000e_defines.h GP Int 2
29200
 E1000_ICR_GPI_EN3E1000_ICR_GPI_EN3 0x00004000 e1000e_defines.h GP Int 3
29201
 E1000_ICR_TXD_LOWE1000_ICR_TXD_LOW 0x00008000 e1000e_defines.h 　
29202
 E1000_ICR_SRPDE1000_ICR_SRPD 0x00010000 e1000e_defines.h 　
29203
 E1000_ICR_ACKE1000_ICR_ACK 0x00020000 e1000e_defines.h Receive Ack frame
29204
 E1000_ICR_MNGE1000_ICR_MNG 0x00040000 e1000e_defines.h Manageability event
29205
 E1000_ICR_DOCKE1000_ICR_DOCK 0x00080000 e1000e_defines.h Dock/Undock
29206
 E1000_ICR_INT_ASSERTEDE1000_ICR_INT_ASSERTED 0x80000000 e1000e_defines.h If this bit asserted, the driver
29207
 E1000_ICR_RXD_FIFO_PAR0E1000_ICR_RXD_FIFO_PAR0 0x00100000 e1000e_defines.h Q0 Rx desc FIFO parity error
29208
 E1000_ICR_TXD_FIFO_PAR0E1000_ICR_TXD_FIFO_PAR0 0x00200000 e1000e_defines.h Q0 Tx desc FIFO parity error
29209
 E1000_ICR_HOST_ARB_PARE1000_ICR_HOST_ARB_PAR 0x00400000 e1000e_defines.h host arb read buffer parity err
29210
 E1000_ICR_PB_PARE1000_ICR_PB_PAR 0x00800000 e1000e_defines.h packet buffer parity error
29211
 E1000_ICR_RXD_FIFO_PAR1E1000_ICR_RXD_FIFO_PAR1 0x01000000 e1000e_defines.h Q1 Rx desc FIFO parity error
29212
 E1000_ICR_TXD_FIFO_PAR1E1000_ICR_TXD_FIFO_PAR1 0x02000000 e1000e_defines.h Q1 Tx desc FIFO parity error
29213
 E1000_ICR_ALL_PARITYE1000_ICR_ALL_PARITY 0x03F00000 e1000e_defines.h all parity error bits
29214
 E1000_ICR_DSWE1000_ICR_DSW 0x00000020 e1000e_defines.h FW changed the status of DISSW
29215
 E1000_ICR_PHYINTE1000_ICR_PHYINT 0x00001000 e1000e_defines.h LAN connected device generates
29216
 E1000_ICR_DOUTSYNCE1000_ICR_DOUTSYNC 0x10000000 e1000e_defines.h NIC DMA out of sync
29217
 E1000_ICR_EPRSTE1000_ICR_EPRST 0x00100000 e1000e_defines.h ME hardware reset occurs
29218
 E1000_ICR_RXQ0E1000_ICR_RXQ0 0x00100000 e1000e_defines.h Rx Queue 0 Interrupt
29219
 E1000_ICR_RXQ1E1000_ICR_RXQ1 0x00200000 e1000e_defines.h Rx Queue 1 Interrupt
29220
 E1000_ICR_TXQ0E1000_ICR_TXQ0 0x00400000 e1000e_defines.h Tx Queue 0 Interrupt
29221
 E1000_ICR_TXQ1E1000_ICR_TXQ1 0x00800000 e1000e_defines.h Tx Queue 1 Interrupt
29222
 E1000_ICR_OTHERE1000_ICR_OTHER 0x01000000 e1000e_defines.h Other Interrupts
29223
 E1000_PBA_ECC_COUNTER_MASKE1000_PBA_ECC_COUNTER_MASK 0xFFF00000 e1000e_defines.h ECC counter mask
29224
 E1000_PBA_ECC_COUNTER_SHIFTE1000_PBA_ECC_COUNTER_SHIFT 20 e1000e_defines.h ECC counter shift value
29225
 E1000_PBA_ECC_CORR_ENE1000_PBA_ECC_CORR_EN 0x00000001 e1000e_defines.h Enable ECC error correction
29226
 E1000_PBA_ECC_STAT_CLRE1000_PBA_ECC_STAT_CLR 0x00000002 e1000e_defines.h Clear ECC error counter
29227
 E1000_PBA_ECC_INT_ENE1000_PBA_ECC_INT_EN 0x00000004 e1000e_defines.h Enable ICR bit 5 on ECC error
29228
 POLL_IMS_ENABLE_MASKPOLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) e1000e_defines.h 　
29229
 IMS_ENABLE_MASKIMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_LSC) e1000e_defines.h 　
29230
 E1000_IMS_TXDWE1000_IMS_TXDW E1000_ICR_TXDW e1000e_defines.h Tx desc written back
29231
 E1000_IMS_TXQEE1000_IMS_TXQE E1000_ICR_TXQE e1000e_defines.h Transmit Queue empty
29232
 E1000_IMS_LSCE1000_IMS_LSC E1000_ICR_LSC e1000e_defines.h Link Status Change
29233
 E1000_IMS_VMMBE1000_IMS_VMMB E1000_ICR_VMMB e1000e_defines.h Mail box activity
29234
 E1000_IMS_RXSEQE1000_IMS_RXSEQ E1000_ICR_RXSEQ e1000e_defines.h rx sequence error
29235
 E1000_IMS_RXDMT0E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 e1000e_defines.h rx desc min. threshold
29236
 E1000_IMS_RXOE1000_IMS_RXO E1000_ICR_RXO e1000e_defines.h rx overrun
29237
 E1000_IMS_RXT0E1000_IMS_RXT0 E1000_ICR_RXT0 e1000e_defines.h rx timer intr
29238
 E1000_IMS_MDACE1000_IMS_MDAC E1000_ICR_MDAC e1000e_defines.h MDIO access complete
29239
 E1000_IMS_RXCFGE1000_IMS_RXCFG E1000_ICR_RXCFG e1000e_defines.h Rx /c/ ordered set
29240
 E1000_IMS_GPI_EN0E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 e1000e_defines.h GP Int 0
29241
 E1000_IMS_GPI_EN1E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 e1000e_defines.h GP Int 1
29242
 E1000_IMS_GPI_EN2E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 e1000e_defines.h GP Int 2
29243
 E1000_IMS_GPI_EN3E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 e1000e_defines.h GP Int 3
29244
 E1000_IMS_TXD_LOWE1000_IMS_TXD_LOW E1000_ICR_TXD_LOW e1000e_defines.h 　
29245
 E1000_IMS_SRPDE1000_IMS_SRPD E1000_ICR_SRPD e1000e_defines.h 　
29246
 E1000_IMS_ACKE1000_IMS_ACK E1000_ICR_ACK e1000e_defines.h Receive Ack frame
29247
 E1000_IMS_MNGE1000_IMS_MNG E1000_ICR_MNG e1000e_defines.h Manageability event
29248
 E1000_IMS_DOCKE1000_IMS_DOCK E1000_ICR_DOCK e1000e_defines.h Dock/Undock
29249
 E1000_IMS_RXD_FIFO_PAR0E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000e_defines.h Q0 Rx desc FIFO
29250
 E1000_IMS_TXD_FIFO_PAR0E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000e_defines.h Q0 Tx desc FIFO
29251
 E1000_IMS_HOST_ARB_PARE1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000e_defines.h host arb read buffer
29252
 E1000_IMS_PB_PARE1000_IMS_PB_PAR E1000_ICR_PB_PAR e1000e_defines.h packet buffer parity
29253
 E1000_IMS_RXD_FIFO_PAR1E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000e_defines.h Q1 Rx desc FIFO
29254
 E1000_IMS_TXD_FIFO_PAR1E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000e_defines.h Q1 Tx desc FIFO
29255
 E1000_IMS_DSWE1000_IMS_DSW E1000_ICR_DSW e1000e_defines.h 　
29256
 E1000_IMS_PHYINTE1000_IMS_PHYINT E1000_ICR_PHYINT e1000e_defines.h 　
29257
 E1000_IMS_DOUTSYNCE1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC e1000e_defines.h NIC DMA out of sync
29258
 E1000_IMS_EPRSTE1000_IMS_EPRST E1000_ICR_EPRST e1000e_defines.h 　
29259
 E1000_IMS_RXQ0E1000_IMS_RXQ0 E1000_ICR_RXQ0 e1000e_defines.h Rx Queue 0 Interrupt
29260
 E1000_IMS_RXQ1E1000_IMS_RXQ1 E1000_ICR_RXQ1 e1000e_defines.h Rx Queue 1 Interrupt
29261
 E1000_IMS_TXQ0E1000_IMS_TXQ0 E1000_ICR_TXQ0 e1000e_defines.h Tx Queue 0 Interrupt
29262
 E1000_IMS_TXQ1E1000_IMS_TXQ1 E1000_ICR_TXQ1 e1000e_defines.h Tx Queue 1 Interrupt
29263
 E1000_IMS_OTHERE1000_IMS_OTHER E1000_ICR_OTHER e1000e_defines.h Other Interrupts
29264
 E1000_ICS_TXDWE1000_ICS_TXDW E1000_ICR_TXDW e1000e_defines.h Tx desc written back
29265
 E1000_ICS_TXQEE1000_ICS_TXQE E1000_ICR_TXQE e1000e_defines.h Transmit Queue empty
29266
 E1000_ICS_LSCE1000_ICS_LSC E1000_ICR_LSC e1000e_defines.h Link Status Change
29267
 E1000_ICS_RXSEQE1000_ICS_RXSEQ E1000_ICR_RXSEQ e1000e_defines.h rx sequence error
29268
 E1000_ICS_RXDMT0E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 e1000e_defines.h rx desc min. threshold
29269
 E1000_ICS_RXOE1000_ICS_RXO E1000_ICR_RXO e1000e_defines.h rx overrun
29270
 E1000_ICS_RXT0E1000_ICS_RXT0 E1000_ICR_RXT0 e1000e_defines.h rx timer intr
29271
 E1000_ICS_MDACE1000_ICS_MDAC E1000_ICR_MDAC e1000e_defines.h MDIO access complete
29272
 E1000_ICS_RXCFGE1000_ICS_RXCFG E1000_ICR_RXCFG e1000e_defines.h Rx /c/ ordered set
29273
 E1000_ICS_GPI_EN0E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 e1000e_defines.h GP Int 0
29274
 E1000_ICS_GPI_EN1E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 e1000e_defines.h GP Int 1
29275
 E1000_ICS_GPI_EN2E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 e1000e_defines.h GP Int 2
29276
 E1000_ICS_GPI_EN3E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 e1000e_defines.h GP Int 3
29277
 E1000_ICS_TXD_LOWE1000_ICS_TXD_LOW E1000_ICR_TXD_LOW e1000e_defines.h 　
29278
 E1000_ICS_SRPDE1000_ICS_SRPD E1000_ICR_SRPD e1000e_defines.h 　
29279
 E1000_ICS_ACKE1000_ICS_ACK E1000_ICR_ACK e1000e_defines.h Receive Ack frame
29280
 E1000_ICS_MNGE1000_ICS_MNG E1000_ICR_MNG e1000e_defines.h Manageability event
29281
 E1000_ICS_DOCKE1000_ICS_DOCK E1000_ICR_DOCK e1000e_defines.h Dock/Undock
29282
 E1000_ICS_RXD_FIFO_PAR0E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 e1000e_defines.h Q0 Rx desc FIFO
29283
 E1000_ICS_TXD_FIFO_PAR0E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 e1000e_defines.h Q0 Tx desc FIFO
29284
 E1000_ICS_HOST_ARB_PARE1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR e1000e_defines.h host arb read buffer
29285
 E1000_ICS_PB_PARE1000_ICS_PB_PAR E1000_ICR_PB_PAR e1000e_defines.h packet buffer parity
29286
 E1000_ICS_RXD_FIFO_PAR1E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 e1000e_defines.h Q1 Rx desc FIFO
29287
 E1000_ICS_TXD_FIFO_PAR1E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 e1000e_defines.h Q1 Tx desc FIFO
29288
 E1000_ICS_DSWE1000_ICS_DSW E1000_ICR_DSW e1000e_defines.h 　
29289
 E1000_ICS_DOUTSYNCE1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC e1000e_defines.h NIC DMA out of sync
29290
 E1000_ICS_PHYINTE1000_ICS_PHYINT E1000_ICR_PHYINT e1000e_defines.h 　
29291
 E1000_ICS_EPRSTE1000_ICS_EPRST E1000_ICR_EPRST e1000e_defines.h 　
29292
 E1000_TXDCTL_PTHRESHE1000_TXDCTL_PTHRESH 0x0000003F e1000e_defines.h TXDCTL Prefetch Threshold
29293
 E1000_TXDCTL_HTHRESHE1000_TXDCTL_HTHRESH 0x00003F00 e1000e_defines.h TXDCTL Host Threshold
29294
 E1000_TXDCTL_WTHRESHE1000_TXDCTL_WTHRESH 0x003F0000 e1000e_defines.h TXDCTL Writeback Threshold
29295
 E1000_TXDCTL_GRANE1000_TXDCTL_GRAN 0x01000000 e1000e_defines.h TXDCTL Granularity
29296
 E1000_TXDCTL_LWTHRESHE1000_TXDCTL_LWTHRESH 0xFE000000 e1000e_defines.h TXDCTL Low Threshold
29297
 E1000_TXDCTL_FULL_TX_DESC_WBE1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 e1000e_defines.h GRAN=1, WTHRESH=1
29298
 E1000_TXDCTL_MAX_TX_DESC_PREFETE1000_TXDCTL_MAX_TX_DESC_PREFET 0x0100001F e1000e_defines.h GRAN=1, PTHRESH=31
29299
 E1000_TXDCTL_COUNT_DESCE1000_TXDCTL_COUNT_DESC 0x00400000 e1000e_defines.h 　
29300
 FLOW_CONTROL_ADDRESS_LOWFLOW_CONTROL_ADDRESS_LOW 0x00C28001 e1000e_defines.h 　
29301
 FLOW_CONTROL_ADDRESS_HIGHFLOW_CONTROL_ADDRESS_HIGH 0x00000100 e1000e_defines.h 　
29302
 FLOW_CONTROL_TYPEFLOW_CONTROL_TYPE 0x8808 e1000e_defines.h 　
29303
 VLAN_TAG_SIZEVLAN_TAG_SIZE 4 e1000e_defines.h 802.3ac tag (not DMA'd)
29304
 E1000_VLAN_FILTER_TBL_SIZEE1000_VLAN_FILTER_TBL_SIZE 128 e1000e_defines.h VLAN Filter Table (4096 bits)
29305
 E1000_RAR_ENTRIESE1000_RAR_ENTRIES 15 e1000e_defines.h 　
29306
 E1000_RAH_AVE1000_RAH_AV 0x80000000 e1000e_defines.h Receive descriptor valid
29307
 E1000_RAL_MAC_ADDR_LENE1000_RAL_MAC_ADDR_LEN 4 e1000e_defines.h 　
29308
 E1000_RAH_MAC_ADDR_LENE1000_RAH_MAC_ADDR_LEN 2 e1000e_defines.h 　
29309
 E1000_RAH_POOL_MASKE1000_RAH_POOL_MASK 0x03FC0000 e1000e_defines.h 　
29310
 E1000_RAH_POOL_1E1000_RAH_POOL_1 0x00040000 e1000e_defines.h 　
29311
 E1000_SUCCESSE1000_SUCCESS 0 e1000e_defines.h 　
29312
 E1000_ERR_NVME1000_ERR_NVM 1 e1000e_defines.h 　
29313
 E1000_ERR_PHYE1000_ERR_PHY 2 e1000e_defines.h 　
29314
 E1000_ERR_CONFIGE1000_ERR_CONFIG 3 e1000e_defines.h 　
29315
 E1000_ERR_PARAME1000_ERR_PARAM 4 e1000e_defines.h 　
29316
 E1000_ERR_MAC_INITE1000_ERR_MAC_INIT 5 e1000e_defines.h 　
29317
 E1000_ERR_PHY_TYPEE1000_ERR_PHY_TYPE 6 e1000e_defines.h 　
29318
 E1000_ERR_RESETE1000_ERR_RESET 9 e1000e_defines.h 　
29319
 E1000_ERR_MASTER_REQUESTS_PENDIE1000_ERR_MASTER_REQUESTS_PENDI 10 e1000e_defines.h 　
29320
 E1000_ERR_HOST_INTERFACE_COMMANE1000_ERR_HOST_INTERFACE_COMMAN 11 e1000e_defines.h 　
29321
 E1000_BLK_PHY_RESETE1000_BLK_PHY_RESET 12 e1000e_defines.h 　
29322
 E1000_ERR_SWFW_SYNCE1000_ERR_SWFW_SYNC 13 e1000e_defines.h 　
29323
 E1000_NOT_IMPLEMENTEDE1000_NOT_IMPLEMENTED 14 e1000e_defines.h 　
29324
 E1000_ERR_MBXE1000_ERR_MBX 15 e1000e_defines.h 　
29325
 FIBER_LINK_UP_LIMITFIBER_LINK_UP_LIMIT 50 e1000e_defines.h 　
29326
 COPPER_LINK_UP_LIMITCOPPER_LINK_UP_LIMIT 10 e1000e_defines.h 　
29327
 PHY_AUTO_NEG_LIMITPHY_AUTO_NEG_LIMIT 45 e1000e_defines.h 　
29328
 PHY_FORCE_LIMITPHY_FORCE_LIMIT 20 e1000e_defines.h 　
29329
 MASTER_DISABLE_TIMEOUTMASTER_DISABLE_TIMEOUT 800 e1000e_defines.h 　
29330
 PHY_CFG_TIMEOUTPHY_CFG_TIMEOUT 100 e1000e_defines.h 　
29331
 MDIO_OWNERSHIP_TIMEOUTMDIO_OWNERSHIP_TIMEOUT 10 e1000e_defines.h 　
29332
 AUTO_READ_DONE_TIMEOUTAUTO_READ_DONE_TIMEOUT 10 e1000e_defines.h 　
29333
 E1000_FCRTH_RTHE1000_FCRTH_RTH 0x0000FFF8 e1000e_defines.h Mask Bits[15:3] for RTH
29334
 E1000_FCRTH_XFCEE1000_FCRTH_XFCE 0x80000000 e1000e_defines.h External Flow Control Enable
29335
 E1000_FCRTL_RTLE1000_FCRTL_RTL 0x0000FFF8 e1000e_defines.h Mask Bits[15:3] for RTL
29336
 E1000_FCRTL_XONEE1000_FCRTL_XONE 0x80000000 e1000e_defines.h Enable XON frame transmission
29337
 E1000_TXCW_FDE1000_TXCW_FD 0x00000020 e1000e_defines.h TXCW full duplex
29338
 E1000_TXCW_HDE1000_TXCW_HD 0x00000040 e1000e_defines.h TXCW half duplex
29339
 E1000_TXCW_PAUSEE1000_TXCW_PAUSE 0x00000080 e1000e_defines.h TXCW sym pause request
29340
 E1000_TXCW_ASM_DIRE1000_TXCW_ASM_DIR 0x00000100 e1000e_defines.h TXCW astm pause direction
29341
 E1000_TXCW_PAUSE_MASKE1000_TXCW_PAUSE_MASK 0x00000180 e1000e_defines.h TXCW pause request mask
29342
 E1000_TXCW_RFE1000_TXCW_RF 0x00003000 e1000e_defines.h TXCW remote fault
29343
 E1000_TXCW_NPE1000_TXCW_NP 0x00008000 e1000e_defines.h TXCW next page
29344
 E1000_TXCW_CWE1000_TXCW_CW 0x0000ffff e1000e_defines.h TxConfigWord mask
29345
 E1000_TXCW_TXCE1000_TXCW_TXC 0x40000000 e1000e_defines.h Transmit Config control
29346
 E1000_TXCW_ANEE1000_TXCW_ANE 0x80000000 e1000e_defines.h Auto-neg enable
29347
 E1000_RXCW_CWE1000_RXCW_CW 0x0000ffff e1000e_defines.h RxConfigWord mask
29348
 E1000_RXCW_NCE1000_RXCW_NC 0x04000000 e1000e_defines.h Receive config no carrier
29349
 E1000_RXCW_IVE1000_RXCW_IV 0x08000000 e1000e_defines.h Receive config invalid
29350
 E1000_RXCW_CCE1000_RXCW_CC 0x10000000 e1000e_defines.h Receive config change
29351
 E1000_RXCW_CE1000_RXCW_C 0x20000000 e1000e_defines.h Receive config
29352
 E1000_RXCW_SYNCHE1000_RXCW_SYNCH 0x40000000 e1000e_defines.h Receive config synch
29353
 E1000_RXCW_ANCE1000_RXCW_ANC 0x80000000 e1000e_defines.h Auto-neg complete
29354
 E1000_GCR_RXD_NO_SNOOPE1000_GCR_RXD_NO_SNOOP 0x00000001 e1000e_defines.h 　
29355
 E1000_GCR_RXDSCW_NO_SNOOPE1000_GCR_RXDSCW_NO_SNOOP 0x00000002 e1000e_defines.h 　
29356
 E1000_GCR_RXDSCR_NO_SNOOPE1000_GCR_RXDSCR_NO_SNOOP 0x00000004 e1000e_defines.h 　
29357
 E1000_GCR_TXD_NO_SNOOPE1000_GCR_TXD_NO_SNOOP 0x00000008 e1000e_defines.h 　
29358
 E1000_GCR_TXDSCW_NO_SNOOPE1000_GCR_TXDSCW_NO_SNOOP 0x00000010 e1000e_defines.h 　
29359
 E1000_GCR_TXDSCR_NO_SNOOPE1000_GCR_TXDSCR_NO_SNOOP 0x00000020 e1000e_defines.h 　
29360
 E1000_GCR_CMPL_TMOUT_MASKE1000_GCR_CMPL_TMOUT_MASK 0x0000F000 e1000e_defines.h 　
29361
 E1000_GCR_CMPL_TMOUT_10msE1000_GCR_CMPL_TMOUT_10ms 0x00001000 e1000e_defines.h 　
29362
 E1000_GCR_CMPL_TMOUT_RESENDE1000_GCR_CMPL_TMOUT_RESEND 0x00010000 e1000e_defines.h 　
29363
 E1000_GCR_CAP_VER2E1000_GCR_CAP_VER2 0x00040000 e1000e_defines.h 　
29364
 PCIE_NO_SNOOP_ALLPCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ E1000_GCR_RXDSCW_NO_SNOOP | \ E1000_GCR_RXDSCR_NO_SNOOP | \ E1000_GCR_TXD_NO_SNOO e1000e_defines.h 　
29365
 MII_CR_SPEED_SELECT_MSBMII_CR_SPEED_SELECT_MSB 0x0040 e1000e_defines.h bits 6,13: 10=1000, 01=100, 00=10
29366
 MII_CR_COLL_TEST_ENABLEMII_CR_COLL_TEST_ENABLE 0x0080 e1000e_defines.h Collision test enable
29367
 MII_CR_FULL_DUPLEXMII_CR_FULL_DUPLEX 0x0100 e1000e_defines.h FDX =1, half duplex =0
29368
 MII_CR_RESTART_AUTO_NEGMII_CR_RESTART_AUTO_NEG 0x0200 e1000e_defines.h Restart auto negotiation
29369
 MII_CR_ISOLATEMII_CR_ISOLATE 0x0400 e1000e_defines.h Isolate PHY from MII
29370
 MII_CR_POWER_DOWNMII_CR_POWER_DOWN 0x0800 e1000e_defines.h Power down
29371
 MII_CR_AUTO_NEG_ENMII_CR_AUTO_NEG_EN 0x1000 e1000e_defines.h Auto Neg Enable
29372
 MII_CR_SPEED_SELECT_LSBMII_CR_SPEED_SELECT_LSB 0x2000 e1000e_defines.h bits 6,13: 10=1000, 01=100, 00=10
29373
 MII_CR_LOOPBACKMII_CR_LOOPBACK 0x4000 e1000e_defines.h 0 = normal, 1 = loopback
29374
 MII_CR_RESETMII_CR_RESET 0x8000 e1000e_defines.h 0 = normal, 1 = PHY reset
29375
 MII_CR_SPEED_1000MII_CR_SPEED_1000 0x0040 e1000e_defines.h 　
29376
 MII_CR_SPEED_100MII_CR_SPEED_100 0x2000 e1000e_defines.h 　
29377
 MII_CR_SPEED_10MII_CR_SPEED_10 0x0000 e1000e_defines.h 　
29378
 MII_SR_EXTENDED_CAPSMII_SR_EXTENDED_CAPS 0x0001 e1000e_defines.h Extended register capabilities
29379
 MII_SR_JABBER_DETECTMII_SR_JABBER_DETECT 0x0002 e1000e_defines.h Jabber Detected
29380
 MII_SR_LINK_STATUSMII_SR_LINK_STATUS 0x0004 e1000e_defines.h Link Status 1 = link
29381
 MII_SR_AUTONEG_CAPSMII_SR_AUTONEG_CAPS 0x0008 e1000e_defines.h Auto Neg Capable
29382
 MII_SR_REMOTE_FAULTMII_SR_REMOTE_FAULT 0x0010 e1000e_defines.h Remote Fault Detect
29383
 MII_SR_AUTONEG_COMPLETEMII_SR_AUTONEG_COMPLETE 0x0020 e1000e_defines.h Auto Neg Complete
29384
 MII_SR_PREAMBLE_SUPPRESSMII_SR_PREAMBLE_SUPPRESS 0x0040 e1000e_defines.h Preamble may be suppressed
29385
 MII_SR_EXTENDED_STATUSMII_SR_EXTENDED_STATUS 0x0100 e1000e_defines.h Ext. status info in Reg 0x0F
29386
 MII_SR_100T2_HD_CAPSMII_SR_100T2_HD_CAPS 0x0200 e1000e_defines.h 100T2 Half Duplex Capable
29387
 MII_SR_100T2_FD_CAPSMII_SR_100T2_FD_CAPS 0x0400 e1000e_defines.h 100T2 Full Duplex Capable
29388
 MII_SR_10T_HD_CAPSMII_SR_10T_HD_CAPS 0x0800 e1000e_defines.h 10T Half Duplex Capable
29389
 MII_SR_10T_FD_CAPSMII_SR_10T_FD_CAPS 0x1000 e1000e_defines.h 10T Full Duplex Capable
29390
 MII_SR_100X_HD_CAPSMII_SR_100X_HD_CAPS 0x2000 e1000e_defines.h 100X Half Duplex Capable
29391
 MII_SR_100X_FD_CAPSMII_SR_100X_FD_CAPS 0x4000 e1000e_defines.h 100X Full Duplex Capable
29392
 MII_SR_100T4_CAPSMII_SR_100T4_CAPS 0x8000 e1000e_defines.h 100T4 Capable
29393
 NWAY_AR_SELECTOR_FIELDNWAY_AR_SELECTOR_FIELD 0x0001 e1000e_defines.h indicates IEEE 802.3 CSMA/CD
29394
 NWAY_AR_10T_HD_CAPSNWAY_AR_10T_HD_CAPS 0x0020 e1000e_defines.h 10T Half Duplex Capable
29395
 NWAY_AR_10T_FD_CAPSNWAY_AR_10T_FD_CAPS 0x0040 e1000e_defines.h 10T Full Duplex Capable
29396
 NWAY_AR_100TX_HD_CAPSNWAY_AR_100TX_HD_CAPS 0x0080 e1000e_defines.h 100TX Half Duplex Capable
29397
 NWAY_AR_100TX_FD_CAPSNWAY_AR_100TX_FD_CAPS 0x0100 e1000e_defines.h 100TX Full Duplex Capable
29398
 NWAY_AR_100T4_CAPSNWAY_AR_100T4_CAPS 0x0200 e1000e_defines.h 100T4 Capable
29399
 NWAY_AR_PAUSENWAY_AR_PAUSE 0x0400 e1000e_defines.h Pause operation desired
29400
 NWAY_AR_ASM_DIRNWAY_AR_ASM_DIR 0x0800 e1000e_defines.h Asymmetric Pause Direction bit
29401
 NWAY_AR_REMOTE_FAULTNWAY_AR_REMOTE_FAULT 0x2000 e1000e_defines.h Remote Fault detected
29402
 NWAY_AR_NEXT_PAGENWAY_AR_NEXT_PAGE 0x8000 e1000e_defines.h Next Page ability supported
29403
 NWAY_LPAR_SELECTOR_FIELDNWAY_LPAR_SELECTOR_FIELD 0x0000 e1000e_defines.h LP protocol selector field
29404
 NWAY_LPAR_10T_HD_CAPSNWAY_LPAR_10T_HD_CAPS 0x0020 e1000e_defines.h LP is 10T Half Duplex Capable
29405
 NWAY_LPAR_10T_FD_CAPSNWAY_LPAR_10T_FD_CAPS 0x0040 e1000e_defines.h LP is 10T Full Duplex Capable
29406
 NWAY_LPAR_100TX_HD_CAPSNWAY_LPAR_100TX_HD_CAPS 0x0080 e1000e_defines.h LP is 100TX Half Duplex Capable
29407
 NWAY_LPAR_100TX_FD_CAPSNWAY_LPAR_100TX_FD_CAPS 0x0100 e1000e_defines.h LP is 100TX Full Duplex Capable
29408
 NWAY_LPAR_100T4_CAPSNWAY_LPAR_100T4_CAPS 0x0200 e1000e_defines.h LP is 100T4 Capable
29409
 NWAY_LPAR_PAUSENWAY_LPAR_PAUSE 0x0400 e1000e_defines.h LP Pause operation desired
29410
 NWAY_LPAR_ASM_DIRNWAY_LPAR_ASM_DIR 0x0800 e1000e_defines.h LP Asymmetric Pause Direction bit
29411
 NWAY_LPAR_REMOTE_FAULTNWAY_LPAR_REMOTE_FAULT 0x2000 e1000e_defines.h LP has detected Remote Fault
29412
 NWAY_LPAR_ACKNOWLEDGENWAY_LPAR_ACKNOWLEDGE 0x4000 e1000e_defines.h LP has rx'd link code word
29413
 NWAY_LPAR_NEXT_PAGENWAY_LPAR_NEXT_PAGE 0x8000 e1000e_defines.h Next Page ability supported
29414
 NWAY_ER_LP_NWAY_CAPSNWAY_ER_LP_NWAY_CAPS 0x0001 e1000e_defines.h LP has Auto Neg Capability
29415
 NWAY_ER_PAGE_RXDNWAY_ER_PAGE_RXD 0x0002 e1000e_defines.h LP is 10T Half Duplex Capable
29416
 NWAY_ER_NEXT_PAGE_CAPSNWAY_ER_NEXT_PAGE_CAPS 0x0004 e1000e_defines.h LP is 10T Full Duplex Capable
29417
 NWAY_ER_LP_NEXT_PAGE_CAPSNWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 e1000e_defines.h LP is 100TX Half Duplex Capable
29418
 NWAY_ER_PAR_DETECT_FAULTNWAY_ER_PAR_DETECT_FAULT 0x0010 e1000e_defines.h LP is 100TX Full Duplex Capable
29419
 CR_1000T_ASYM_PAUSECR_1000T_ASYM_PAUSE 0x0080 e1000e_defines.h Advertise asymmetric pause bit
29420
 CR_1000T_HD_CAPSCR_1000T_HD_CAPS 0x0100 e1000e_defines.h Advertise 1000T HD capability
29421
 CR_1000T_FD_CAPSCR_1000T_FD_CAPS 0x0200 e1000e_defines.h Advertise 1000T FD capability
29422
 CR_1000T_REPEATER_DTECR_1000T_REPEATER_DTE 0x0400 e1000e_defines.h 1=Repeater/switch device port
29423
 CR_1000T_MS_VALUECR_1000T_MS_VALUE 0x0800 e1000e_defines.h 1=Configure PHY as Master
29424
 CR_1000T_MS_ENABLECR_1000T_MS_ENABLE 0x1000 e1000e_defines.h 1=Master/Slave manual config value
29425
 CR_1000T_TEST_MODE_NORMALCR_1000T_TEST_MODE_NORMAL 0x0000 e1000e_defines.h Normal Operation
29426
 CR_1000T_TEST_MODE_1CR_1000T_TEST_MODE_1 0x2000 e1000e_defines.h Transmit Waveform test
29427
 CR_1000T_TEST_MODE_2CR_1000T_TEST_MODE_2 0x4000 e1000e_defines.h Master Transmit Jitter test
29428
 CR_1000T_TEST_MODE_3CR_1000T_TEST_MODE_3 0x6000 e1000e_defines.h Slave Transmit Jitter test
29429
 CR_1000T_TEST_MODE_4CR_1000T_TEST_MODE_4 0x8000 e1000e_defines.h Transmitter Distortion test
29430
 SR_1000T_IDLE_ERROR_CNTSR_1000T_IDLE_ERROR_CNT 0x00FF e1000e_defines.h Num idle errors since last read
29431
 SR_1000T_ASYM_PAUSE_DIRSR_1000T_ASYM_PAUSE_DIR 0x0100 e1000e_defines.h LP asymmetric pause direction bit
29432
 SR_1000T_LP_HD_CAPSSR_1000T_LP_HD_CAPS 0x0400 e1000e_defines.h LP is 1000T HD capable
29433
 SR_1000T_LP_FD_CAPSSR_1000T_LP_FD_CAPS 0x0800 e1000e_defines.h LP is 1000T FD capable
29434
 SR_1000T_REMOTE_RX_STATUSSR_1000T_REMOTE_RX_STATUS 0x1000 e1000e_defines.h Remote receiver OK
29435
 SR_1000T_LOCAL_RX_STATUSSR_1000T_LOCAL_RX_STATUS 0x2000 e1000e_defines.h Local receiver OK
29436
 SR_1000T_MS_CONFIG_RESSR_1000T_MS_CONFIG_RES 0x4000 e1000e_defines.h 1=Local Tx is Master, 0=Slave
29437
 SR_1000T_MS_CONFIG_FAULTSR_1000T_MS_CONFIG_FAULT 0x8000 e1000e_defines.h Master/Slave config fault
29438
 SR_1000T_PHY_EXCESSIVE_IDLE_ERRSR_1000T_PHY_EXCESSIVE_IDLE_ERR 5 e1000e_defines.h 　
29439
 PHY_CONTROLPHY_CONTROL 0x00 e1000e_defines.h Control Register
29440
 PHY_STATUSPHY_STATUS 0x01 e1000e_defines.h Status Register
29441
 PHY_ID1PHY_ID1 0x02 e1000e_defines.h Phy Id Reg (word 1)
29442
 PHY_ID2PHY_ID2 0x03 e1000e_defines.h Phy Id Reg (word 2)
29443
 PHY_AUTONEG_ADVPHY_AUTONEG_ADV 0x04 e1000e_defines.h Autoneg Advertisement
29444
 PHY_LP_ABILITYPHY_LP_ABILITY 0x05 e1000e_defines.h Link Partner Ability (Base Page)
29445
 PHY_AUTONEG_EXPPHY_AUTONEG_EXP 0x06 e1000e_defines.h Autoneg Expansion Reg
29446
 PHY_NEXT_PAGE_TXPHY_NEXT_PAGE_TX 0x07 e1000e_defines.h Next Page Tx
29447
 PHY_LP_NEXT_PAGEPHY_LP_NEXT_PAGE 0x08 e1000e_defines.h Link Partner Next Page
29448
 PHY_1000T_CTRLPHY_1000T_CTRL 0x09 e1000e_defines.h 1000Base-T Control Reg
29449
 PHY_1000T_STATUSPHY_1000T_STATUS 0x0A e1000e_defines.h 1000Base-T Status Reg
29450
 PHY_EXT_STATUSPHY_EXT_STATUS 0x0F e1000e_defines.h Extended Status Reg
29451
 PHY_CONTROL_LBPHY_CONTROL_LB 0x4000 e1000e_defines.h PHY Loopback bit
29452
 E1000_EECD_SKE1000_EECD_SK 0x00000001 e1000e_defines.h NVM Clock
29453
 E1000_EECD_CSE1000_EECD_CS 0x00000002 e1000e_defines.h NVM Chip Select
29454
 E1000_EECD_DIE1000_EECD_DI 0x00000004 e1000e_defines.h NVM Data In
29455
 E1000_EECD_DOE1000_EECD_DO 0x00000008 e1000e_defines.h NVM Data Out
29456
 E1000_EECD_FWE_MASKE1000_EECD_FWE_MASK 0x00000030 e1000e_defines.h 　
29457
 E1000_EECD_FWE_DISE1000_EECD_FWE_DIS 0x00000010 e1000e_defines.h Disable FLASH writes
29458
 E1000_EECD_FWE_ENE1000_EECD_FWE_EN 0x00000020 e1000e_defines.h Enable FLASH writes
29459
 E1000_EECD_FWE_SHIFTE1000_EECD_FWE_SHIFT 4 e1000e_defines.h 　
29460
 E1000_EECD_REQE1000_EECD_REQ 0x00000040 e1000e_defines.h NVM Access Request
29461
 E1000_EECD_GNTE1000_EECD_GNT 0x00000080 e1000e_defines.h NVM Access Grant
29462
 E1000_EECD_PRESE1000_EECD_PRES 0x00000100 e1000e_defines.h NVM Present
29463
 E1000_EECD_SIZEE1000_EECD_SIZE 0x00000200 e1000e_defines.h NVM Size (0=64 word 1=256 word)
29464
 E1000_EECD_ADDR_BITSE1000_EECD_ADDR_BITS 0x00000400 e1000e_defines.h 　
29465
 E1000_EECD_TYPEE1000_EECD_TYPE 0x00002000 e1000e_defines.h NVM Type (1-SPI, 0-Microwire)
29466
 E1000_NVM_GRANT_ATTEMPTSE1000_NVM_GRANT_ATTEMPTS 1000 e1000e_defines.h NVM # attempts to gain grant
29467
 E1000_EECD_AUTO_RDE1000_EECD_AUTO_RD 0x00000200 e1000e_defines.h NVM Auto Read done
29468
 E1000_EECD_SIZE_EX_MASKE1000_EECD_SIZE_EX_MASK 0x00007800 e1000e_defines.h NVM Size
29469
 E1000_EECD_SIZE_EX_SHIFTE1000_EECD_SIZE_EX_SHIFT 11 e1000e_defines.h 　
29470
 E1000_EECD_NVADDSE1000_EECD_NVADDS 0x00018000 e1000e_defines.h NVM Address Size
29471
 E1000_EECD_SELSHADE1000_EECD_SELSHAD 0x00020000 e1000e_defines.h Select Shadow RAM
29472
 E1000_EECD_INITSRAME1000_EECD_INITSRAM 0x00040000 e1000e_defines.h Initialize Shadow RAM
29473
 E1000_EECD_FLUPDE1000_EECD_FLUPD 0x00080000 e1000e_defines.h Update FLASH
29474
 E1000_EECD_AUPDENE1000_EECD_AUPDEN 0x00100000 e1000e_defines.h Enable Autonomous FLASH update
29475
 E1000_EECD_SHADVE1000_EECD_SHADV 0x00200000 e1000e_defines.h Shadow RAM Data Valid
29476
 E1000_EECD_SEC1VALE1000_EECD_SEC1VAL 0x00400000 e1000e_defines.h Sector One Valid
29477
 E1000_EECD_SECVAL_SHIFTE1000_EECD_SECVAL_SHIFT 22 e1000e_defines.h 　
29478
 E1000_EECD_SEC1VAL_VALID_MASKE1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) e1000e_defines.h 　
29479
 E1000_NVM_SWDPIN0E1000_NVM_SWDPIN0 0x0001 e1000e_defines.h SWDPIN 0 NVM Value
29480
 E1000_NVM_LED_LOGICE1000_NVM_LED_LOGIC 0x0020 e1000e_defines.h Led Logic Word
29481
 E1000_NVM_RW_REG_DATAE1000_NVM_RW_REG_DATA 16 e1000e_defines.h Offset to data in NVM read/write regs
29482
 E1000_NVM_RW_REG_DONEE1000_NVM_RW_REG_DONE 2 e1000e_defines.h Offset to READ/WRITE done bit
29483
 E1000_NVM_RW_REG_STARTE1000_NVM_RW_REG_START 1 e1000e_defines.h Start operation
29484
 E1000_NVM_RW_ADDR_SHIFTE1000_NVM_RW_ADDR_SHIFT 2 e1000e_defines.h Shift to the address bits
29485
 E1000_NVM_POLL_WRITEE1000_NVM_POLL_WRITE 1 e1000e_defines.h Flag for polling for write complete
29486
 E1000_NVM_POLL_READE1000_NVM_POLL_READ 0 e1000e_defines.h Flag for polling for read complete
29487
 E1000_FLASH_UPDATESE1000_FLASH_UPDATES 2000 e1000e_defines.h 　
29488
 NVM_COMPATNVM_COMPAT 0x0003 e1000e_defines.h 　
29489
 NVM_ID_LED_SETTINGSNVM_ID_LED_SETTINGS 0x0004 e1000e_defines.h 　
29490
 NVM_VERSIONNVM_VERSION 0x0005 e1000e_defines.h 　
29491
 NVM_SERDES_AMPLITUDENVM_SERDES_AMPLITUDE 0x0006 e1000e_defines.h SERDES output amplitude
29492
 NVM_PHY_CLASS_WORDNVM_PHY_CLASS_WORD 0x0007 e1000e_defines.h 　
29493
 NVM_INIT_CONTROL1_REGNVM_INIT_CONTROL1_REG 0x000A e1000e_defines.h 　
29494
 NVM_INIT_CONTROL2_REGNVM_INIT_CONTROL2_REG 0x000F e1000e_defines.h 　
29495
 NVM_SWDEF_PINS_CTRL_PORT_1NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 e1000e_defines.h 　
29496
 NVM_INIT_CONTROL3_PORT_BNVM_INIT_CONTROL3_PORT_B 0x0014 e1000e_defines.h 　
29497
 NVM_INIT_3GIO_3NVM_INIT_3GIO_3 0x001A e1000e_defines.h 　
29498
 NVM_SWDEF_PINS_CTRL_PORT_0NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 e1000e_defines.h 　
29499
 NVM_INIT_CONTROL3_PORT_ANVM_INIT_CONTROL3_PORT_A 0x0024 e1000e_defines.h 　
29500
 NVM_CFGNVM_CFG 0x0012 e1000e_defines.h 　
29501
 NVM_FLASH_VERSIONNVM_FLASH_VERSION 0x0032 e1000e_defines.h 　
29502
 NVM_ALT_MAC_ADDR_PTRNVM_ALT_MAC_ADDR_PTR 0x0037 e1000e_defines.h 　
29503
 NVM_CHECKSUM_REGNVM_CHECKSUM_REG 0x003F e1000e_defines.h 　
29504
 E1000_NVM_CFG_DONE_PORT_0E1000_NVM_CFG_DONE_PORT_0 0x040000 e1000e_defines.h MNG config cycle done
29505
 E1000_NVM_CFG_DONE_PORT_1E1000_NVM_CFG_DONE_PORT_1 0x080000 e1000e_defines.h ...for second port
29506
 NVM_WORD0F_PAUSE_MASKNVM_WORD0F_PAUSE_MASK 0x3000 e1000e_defines.h 　
29507
 NVM_WORD0F_PAUSENVM_WORD0F_PAUSE 0x1000 e1000e_defines.h 　
29508
 NVM_WORD0F_ASM_DIRNVM_WORD0F_ASM_DIR 0x2000 e1000e_defines.h 　
29509
 NVM_WORD0F_ANENVM_WORD0F_ANE 0x0800 e1000e_defines.h 　
29510
 NVM_WORD0F_SWPDIO_EXT_MASKNVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 e1000e_defines.h 　
29511
 NVM_WORD0F_LPLUNVM_WORD0F_LPLU 0x0001 e1000e_defines.h 　
29512
 NVM_WORD1A_ASPM_MASKNVM_WORD1A_ASPM_MASK 0x000C e1000e_defines.h 　
29513
 NVM_SUMNVM_SUM 0xBABA e1000e_defines.h 　
29514
 NVM_MAC_ADDR_OFFSETNVM_MAC_ADDR_OFFSET 0 e1000e_defines.h 　
29515
 NVM_PBA_OFFSET_0NVM_PBA_OFFSET_0 8 e1000e_defines.h 　
29516
 NVM_PBA_OFFSET_1NVM_PBA_OFFSET_1 9 e1000e_defines.h 　
29517
 NVM_RESERVED_WORDNVM_RESERVED_WORD 0xFFFF e1000e_defines.h 　
29518
 NVM_PHY_CLASS_ANVM_PHY_CLASS_A 0x8000 e1000e_defines.h 　
29519
 NVM_SERDES_AMPLITUDE_MASKNVM_SERDES_AMPLITUDE_MASK 0x000F e1000e_defines.h 　
29520
 NVM_SIZE_MASKNVM_SIZE_MASK 0x1C00 e1000e_defines.h 　
29521
 NVM_SIZE_SHIFTNVM_SIZE_SHIFT 10 e1000e_defines.h 　
29522
 NVM_WORD_SIZE_BASE_SHIFTNVM_WORD_SIZE_BASE_SHIFT 6 e1000e_defines.h 　
29523
 NVM_SWDPIO_EXT_SHIFTNVM_SWDPIO_EXT_SHIFT 4 e1000e_defines.h 　
29524
 NVM_MAX_RETRY_SPINVM_MAX_RETRY_SPI 5000 e1000e_defines.h Max wait of 5ms, for RDY signal
29525
 NVM_READ_OPCODE_SPINVM_READ_OPCODE_SPI 0x03 e1000e_defines.h NVM read opcode
29526
 NVM_WRITE_OPCODE_SPINVM_WRITE_OPCODE_SPI 0x02 e1000e_defines.h NVM write opcode
29527
 NVM_A8_OPCODE_SPINVM_A8_OPCODE_SPI 0x08 e1000e_defines.h opcode bit-3 = address bit-8
29528
 NVM_WREN_OPCODE_SPINVM_WREN_OPCODE_SPI 0x06 e1000e_defines.h NVM set Write Enable latch
29529
 NVM_WRDI_OPCODE_SPINVM_WRDI_OPCODE_SPI 0x04 e1000e_defines.h NVM reset Write Enable latch
29530
 NVM_RDSR_OPCODE_SPINVM_RDSR_OPCODE_SPI 0x05 e1000e_defines.h NVM read Status register
29531
 NVM_WRSR_OPCODE_SPINVM_WRSR_OPCODE_SPI 0x01 e1000e_defines.h NVM write Status register
29532
 NVM_STATUS_RDY_SPINVM_STATUS_RDY_SPI 0x01 e1000e_defines.h 　
29533
 NVM_STATUS_WEN_SPINVM_STATUS_WEN_SPI 0x02 e1000e_defines.h 　
29534
 NVM_STATUS_BP0_SPINVM_STATUS_BP0_SPI 0x04 e1000e_defines.h 　
29535
 NVM_STATUS_BP1_SPINVM_STATUS_BP1_SPI 0x08 e1000e_defines.h 　
29536
 NVM_STATUS_WPEN_SPINVM_STATUS_WPEN_SPI 0x80 e1000e_defines.h 　
29537
 ID_LED_RESERVED_0000ID_LED_RESERVED_0000 0x0000 e1000e_defines.h 　
29538
 ID_LED_RESERVED_FFFFID_LED_RESERVED_FFFF 0xFFFF e1000e_defines.h 　
29539
 ID_LED_DEFAULTID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) e1000e_defines.h 　
29540
 ID_LED_DEF1_DEF2ID_LED_DEF1_DEF2 0x1 e1000e_defines.h 　
29541
 ID_LED_DEF1_ON2ID_LED_DEF1_ON2 0x2 e1000e_defines.h 　
29542
 ID_LED_DEF1_OFF2ID_LED_DEF1_OFF2 0x3 e1000e_defines.h 　
29543
 ID_LED_ON1_DEF2ID_LED_ON1_DEF2 0x4 e1000e_defines.h 　
29544
 ID_LED_ON1_ON2ID_LED_ON1_ON2 0x5 e1000e_defines.h 　
29545
 ID_LED_ON1_OFF2ID_LED_ON1_OFF2 0x6 e1000e_defines.h 　
29546
 ID_LED_OFF1_DEF2ID_LED_OFF1_DEF2 0x7 e1000e_defines.h 　
29547
 ID_LED_OFF1_ON2ID_LED_OFF1_ON2 0x8 e1000e_defines.h 　
29548
 ID_LED_OFF1_OFF2ID_LED_OFF1_OFF2 0x9 e1000e_defines.h 　
29549
 IGP_ACTIVITY_LED_MASKIGP_ACTIVITY_LED_MASK 0xFFFFF0FF e1000e_defines.h 　
29550
 IGP_ACTIVITY_LED_ENABLEIGP_ACTIVITY_LED_ENABLE 0x0300 e1000e_defines.h 　
29551
 IGP_LED3_MODEIGP_LED3_MODE 0x07000000 e1000e_defines.h 　
29552
 PCI_HEADER_TYPE_REGISTERPCI_HEADER_TYPE_REGISTER 0x0E e1000e_defines.h 　
29553
 PCIE_LINK_STATUSPCIE_LINK_STATUS 0x12 e1000e_defines.h 　
29554
 PCIE_DEVICE_CONTROL2PCIE_DEVICE_CONTROL2 0x28 e1000e_defines.h 　
29555
 PCI_HEADER_TYPE_MULTIFUNCPCI_HEADER_TYPE_MULTIFUNC 0x80 e1000e_defines.h 　
29556
 PCIE_LINK_WIDTH_MASKPCIE_LINK_WIDTH_MASK 0x3F0 e1000e_defines.h 　
29557
 PCIE_LINK_WIDTH_SHIFTPCIE_LINK_WIDTH_SHIFT 4 e1000e_defines.h 　
29558
 PCIE_DEVICE_CONTROL2_16msPCIE_DEVICE_CONTROL2_16ms 0x0005 e1000e_defines.h 　
29559
 ETH_ADDR_LENETH_ADDR_LEN 6 e1000e_defines.h 　
29560
 PHY_REVISION_MASKPHY_REVISION_MASK 0xFFFFFFF0 e1000e_defines.h 　
29561
 MAX_PHY_REG_ADDRESSMAX_PHY_REG_ADDRESS 0x1F e1000e_defines.h 5 bit address bus (0-0x1F)
29562
 MAX_PHY_MULTI_PAGE_REGMAX_PHY_MULTI_PAGE_REG 0xF e1000e_defines.h 　
29563
 M88E1000_E_PHY_IDM88E1000_E_PHY_ID 0x01410C50 e1000e_defines.h 　
29564
 M88E1000_I_PHY_IDM88E1000_I_PHY_ID 0x01410C30 e1000e_defines.h 　
29565
 M88E1011_I_PHY_IDM88E1011_I_PHY_ID 0x01410C20 e1000e_defines.h 　
29566
 IGP01E1000_I_PHY_IDIGP01E1000_I_PHY_ID 0x02A80380 e1000e_defines.h 　
29567
 M88E1011_I_REV_4M88E1011_I_REV_4 0x04 e1000e_defines.h 　
29568
 M88E1111_I_PHY_IDM88E1111_I_PHY_ID 0x01410CC0 e1000e_defines.h 　
29569
 GG82563_E_PHY_IDGG82563_E_PHY_ID 0x01410CA0 e1000e_defines.h 　
29570
 IGP03E1000_E_PHY_IDIGP03E1000_E_PHY_ID 0x02A80390 e1000e_defines.h 　
29571
 IFE_E_PHY_IDIFE_E_PHY_ID 0x02A80330 e1000e_defines.h 　
29572
 IFE_PLUS_E_PHY_IDIFE_PLUS_E_PHY_ID 0x02A80320 e1000e_defines.h 　
29573
 IFE_C_E_PHY_IDIFE_C_E_PHY_ID 0x02A80310 e1000e_defines.h 　
29574
 BME1000_E_PHY_IDBME1000_E_PHY_ID 0x01410CB0 e1000e_defines.h 　
29575
 BME1000_E_PHY_ID_R2BME1000_E_PHY_ID_R2 0x01410CB1 e1000e_defines.h 　
29576
 I82577_E_PHY_IDI82577_E_PHY_ID 0x01540050 e1000e_defines.h 　
29577
 I82578_E_PHY_IDI82578_E_PHY_ID 0x004DD040 e1000e_defines.h 　
29578
 M88_VENDORM88_VENDOR 0x0141 e1000e_defines.h 　
29579
 M88E1000_PHY_SPEC_CTRLM88E1000_PHY_SPEC_CTRL 0x10 e1000e_defines.h PHY Specific Control Register
29580
 M88E1000_PHY_SPEC_STATUSM88E1000_PHY_SPEC_STATUS 0x11 e1000e_defines.h PHY Specific Status Register
29581
 M88E1000_INT_ENABLEM88E1000_INT_ENABLE 0x12 e1000e_defines.h Interrupt Enable Register
29582
 M88E1000_INT_STATUSM88E1000_INT_STATUS 0x13 e1000e_defines.h Interrupt Status Register
29583
 M88E1000_EXT_PHY_SPEC_CTRLM88E1000_EXT_PHY_SPEC_CTRL 0x14 e1000e_defines.h Extended PHY Specific Control
29584
 M88E1000_RX_ERR_CNTRM88E1000_RX_ERR_CNTR 0x15 e1000e_defines.h Receive Error Counter
29585
 M88E1000_PHY_EXT_CTRLM88E1000_PHY_EXT_CTRL 0x1A e1000e_defines.h PHY extend control register
29586
 M88E1000_PHY_PAGE_SELECTM88E1000_PHY_PAGE_SELECT 0x1D e1000e_defines.h Reg 29 for page number setting
29587
 M88E1000_PHY_GEN_CONTROLM88E1000_PHY_GEN_CONTROL 0x1E e1000e_defines.h Its meaning depends on reg 29
29588
 M88E1000_PHY_VCO_REG_BIT8M88E1000_PHY_VCO_REG_BIT8 0x100 e1000e_defines.h Bits 8 & 11 are adjusted for
29589
 M88E1000_PHY_VCO_REG_BIT11M88E1000_PHY_VCO_REG_BIT11 0x800 e1000e_defines.h improved BER performance
29590
 M88E1000_PSCR_JABBER_DISABLEM88E1000_PSCR_JABBER_DISABLE 0x0001 e1000e_defines.h 1=Jabber Function disabled
29591
 M88E1000_PSCR_POLARITY_REVERSALM88E1000_PSCR_POLARITY_REVERSAL 0x0002 e1000e_defines.h 1=Polarity Reverse enabled
29592
 M88E1000_PSCR_SQE_TESTM88E1000_PSCR_SQE_TEST 0x0004 e1000e_defines.h 1=SQE Test enabled
29593
 M88E1000_PSCR_CLK125_DISABLEM88E1000_PSCR_CLK125_DISABLE 0x0010 e1000e_defines.h 　
29594
 M88E1000_PSCR_MDI_MANUAL_MODEM88E1000_PSCR_MDI_MANUAL_MODE 0x0000 e1000e_defines.h MDI Crossover Mode bits 6:5
29595
 M88E1000_PSCR_MDIX_MANUAL_MODEM88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 e1000e_defines.h Manual MDIX configuration
29596
 M88E1000_PSCR_AUTO_X_1000TM88E1000_PSCR_AUTO_X_1000T 0x0040 e1000e_defines.h 　
29597
 M88E1000_PSCR_AUTO_X_MODEM88E1000_PSCR_AUTO_X_MODE 0x0060 e1000e_defines.h 　
29598
 M88E1000_PSCR_EN_10BT_EXT_DISTM88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 e1000e_defines.h 　
29599
 M88E1000_PSCR_MII_5BIT_ENABLEM88E1000_PSCR_MII_5BIT_ENABLE 0x0100 e1000e_defines.h 　
29600
 M88E1000_PSCR_SCRAMBLER_DISABLEM88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 e1000e_defines.h 1=Scrambler disable
29601
 M88E1000_PSCR_FORCE_LINK_GOODM88E1000_PSCR_FORCE_LINK_GOOD 0x0400 e1000e_defines.h 1=Force link good
29602
 M88E1000_PSCR_ASSERT_CRS_ON_TXM88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 e1000e_defines.h 1=Assert CRS on Tx
29603
 M88E1000_PSSR_JABBERM88E1000_PSSR_JABBER 0x0001 e1000e_defines.h 1=Jabber
29604
 M88E1000_PSSR_REV_POLARITYM88E1000_PSSR_REV_POLARITY 0x0002 e1000e_defines.h 1=Polarity reversed
29605
 M88E1000_PSSR_DOWNSHIFTM88E1000_PSSR_DOWNSHIFT 0x0020 e1000e_defines.h 1=Downshifted
29606
 M88E1000_PSSR_MDIXM88E1000_PSSR_MDIX 0x0040 e1000e_defines.h 1=MDIX; 0=MDI
29607
 M88E1000_PSSR_CABLE_LENGTHM88E1000_PSSR_CABLE_LENGTH 0x0380 e1000e_defines.h 　
29608
 M88E1000_PSSR_LINKM88E1000_PSSR_LINK 0x0400 e1000e_defines.h 1=Link up, 0=Link down
29609
 M88E1000_PSSR_SPD_DPLX_RESOLVEDM88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 e1000e_defines.h 1=Speed & Duplex resolved
29610
 M88E1000_PSSR_PAGE_RCVDM88E1000_PSSR_PAGE_RCVD 0x1000 e1000e_defines.h 1=Page received
29611
 M88E1000_PSSR_DPLXM88E1000_PSSR_DPLX 0x2000 e1000e_defines.h 1=Duplex 0=Half Duplex
29612
 M88E1000_PSSR_SPEEDM88E1000_PSSR_SPEED 0xC000 e1000e_defines.h Speed, bits 14:15
29613
 M88E1000_PSSR_10MBSM88E1000_PSSR_10MBS 0x0000 e1000e_defines.h 00=10Mbs
29614
 M88E1000_PSSR_100MBSM88E1000_PSSR_100MBS 0x4000 e1000e_defines.h 01=100Mbs
29615
 M88E1000_PSSR_1000MBSM88E1000_PSSR_1000MBS 0x8000 e1000e_defines.h 10=1000Mbs
29616
 M88E1000_PSSR_CABLE_LENGTH_SHIFM88E1000_PSSR_CABLE_LENGTH_SHIF 7 e1000e_defines.h 　
29617
 M88E1000_EPSCR_FIBER_LOOPBACKM88E1000_EPSCR_FIBER_LOOPBACK 0x4000 e1000e_defines.h 1=Fiber loopback
29618
 M88E1000_EPSCR_DOWN_NO_IDLEM88E1000_EPSCR_DOWN_NO_IDLE 0x8000 e1000e_defines.h 　
29619
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 e1000e_defines.h 　
29620
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0000 e1000e_defines.h 　
29621
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0400 e1000e_defines.h 　
29622
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0800 e1000e_defines.h 　
29623
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 e1000e_defines.h 　
29624
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 e1000e_defines.h 　
29625
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0000 e1000e_defines.h 　
29626
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0100 e1000e_defines.h 　
29627
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0200 e1000e_defines.h 　
29628
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 e1000e_defines.h 　
29629
 M88E1000_EPSCR_TX_CLK_2_5M88E1000_EPSCR_TX_CLK_2_5 0x0060 e1000e_defines.h 2.5 MHz TX_CLK
29630
 M88E1000_EPSCR_TX_CLK_25M88E1000_EPSCR_TX_CLK_25 0x0070 e1000e_defines.h 25 MHz TX_CLK
29631
 M88E1000_EPSCR_TX_CLK_0M88E1000_EPSCR_TX_CLK_0 0x0000 e1000e_defines.h NO TX_CLK
29632
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 e1000e_defines.h 　
29633
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0000 e1000e_defines.h 　
29634
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0200 e1000e_defines.h 　
29635
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0400 e1000e_defines.h 　
29636
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0600 e1000e_defines.h 　
29637
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0800 e1000e_defines.h 　
29638
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0A00 e1000e_defines.h 　
29639
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0C00 e1000e_defines.h 　
29640
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 e1000e_defines.h 　
29641
 I82578_EPSCR_DOWNSHIFT_ENABLEI82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 e1000e_defines.h 　
29642
 I82578_EPSCR_DOWNSHIFT_COUNTER_I82578_EPSCR_DOWNSHIFT_COUNTER_ 0x001C e1000e_defines.h 　
29643
 BME1000_PSCR_ENABLE_DOWNSHIFTBME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 e1000e_defines.h 1 = enable downshift
29644
 GG82563_PAGE_SHIFTGG82563_PAGE_SHIFT 5 e1000e_defines.h 　
29645
 GG82563_MIN_ALT_REGGG82563_MIN_ALT_REG 30 e1000e_defines.h 　
29646
 GG82563_PHY_SPEC_CTRLGG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) e1000e_defines.h PHY Specific Control
29647
 GG82563_PHY_SPEC_STATUSGG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) e1000e_defines.h PHY Specific Status
29648
 GG82563_PHY_INT_ENABLEGG82563_PHY_INT_ENABLE GG82563_REG(0, 18) e1000e_defines.h Interrupt Enable
29649
 GG82563_PHY_SPEC_STATUS_2GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) e1000e_defines.h PHY Specific Status 2
29650
 GG82563_PHY_RX_ERR_CNTRGG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) e1000e_defines.h Receive Error Counter
29651
 GG82563_PHY_PAGE_SELECTGG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) e1000e_defines.h Page Select
29652
 GG82563_PHY_SPEC_CTRL_2GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) e1000e_defines.h PHY Specific Control 2
29653
 GG82563_PHY_PAGE_SELECT_ALTGG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) e1000e_defines.h Alternate Page Select
29654
 GG82563_PHY_TEST_CLK_CTRLGG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) e1000e_defines.h Test Clock Control (use reg. 29 to select)
29655
 GG82563_PHY_MAC_SPEC_CTRLGG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) e1000e_defines.h MAC Specific Control Register
29656
 GG82563_PHY_MAC_SPEC_CTRL_2GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) e1000e_defines.h MAC Specific Control 2
29657
 GG82563_PHY_DSP_DISTANCEGG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) e1000e_defines.h DSP Distance
29658
 GG82563_PHY_KMRN_MODE_CTRLGG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) e1000e_defines.h Kumeran Mode Control
29659
 GG82563_PHY_PORT_RESETGG82563_PHY_PORT_RESET GG82563_REG(193, 17) e1000e_defines.h Port Reset
29660
 GG82563_PHY_REVISION_IDGG82563_PHY_REVISION_ID GG82563_REG(193, 18) e1000e_defines.h Revision ID
29661
 GG82563_PHY_DEVICE_IDGG82563_PHY_DEVICE_ID GG82563_REG(193, 19) e1000e_defines.h Device ID
29662
 GG82563_PHY_PWR_MGMT_CTRLGG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) e1000e_defines.h Power Management Control
29663
 GG82563_PHY_RATE_ADAPT_CTRLGG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) e1000e_defines.h Rate Adaptation Control
29664
 GG82563_PHY_KMRN_FIFO_CTRL_STATGG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) e1000e_defines.h FIFO's Control/Status
29665
 GG82563_PHY_KMRN_CTRLGG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) e1000e_defines.h Control
29666
 GG82563_PHY_INBAND_CTRLGG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) e1000e_defines.h Inband Control
29667
 GG82563_PHY_KMRN_DIAGNOSTICGG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) e1000e_defines.h Diagnostic
29668
 GG82563_PHY_ACK_TIMEOUTSGG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) e1000e_defines.h Acknowledge Timeouts
29669
 GG82563_PHY_ADV_ABILITYGG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) e1000e_defines.h Advertised Ability
29670
 GG82563_PHY_LINK_PARTNER_ADV_ABGG82563_PHY_LINK_PARTNER_ADV_AB GG82563_REG(194, 23) e1000e_defines.h Link Partner Advertised Ability
29671
 GG82563_PHY_ADV_NEXT_PAGEGG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) e1000e_defines.h Advertised Next Page
29672
 GG82563_PHY_LINK_PARTNER_ADV_NEGG82563_PHY_LINK_PARTNER_ADV_NE GG82563_REG(194, 25) e1000e_defines.h Link Partner Advertised Next page
29673
 GG82563_PHY_KMRN_MISCGG82563_PHY_KMRN_MISC GG82563_REG(194, 26) e1000e_defines.h Misc.
29674
 E1000_MDIC_DATA_MASKE1000_MDIC_DATA_MASK 0x0000FFFF e1000e_defines.h 　
29675
 E1000_MDIC_REG_MASKE1000_MDIC_REG_MASK 0x001F0000 e1000e_defines.h 　
29676
 E1000_MDIC_REG_SHIFTE1000_MDIC_REG_SHIFT 16 e1000e_defines.h 　
29677
 E1000_MDIC_PHY_MASKE1000_MDIC_PHY_MASK 0x03E00000 e1000e_defines.h 　
29678
 E1000_MDIC_PHY_SHIFTE1000_MDIC_PHY_SHIFT 21 e1000e_defines.h 　
29679
 E1000_MDIC_OP_WRITEE1000_MDIC_OP_WRITE 0x04000000 e1000e_defines.h 　
29680
 E1000_MDIC_OP_READE1000_MDIC_OP_READ 0x08000000 e1000e_defines.h 　
29681
 E1000_MDIC_READYE1000_MDIC_READY 0x10000000 e1000e_defines.h 　
29682
 E1000_MDIC_INT_ENE1000_MDIC_INT_EN 0x20000000 e1000e_defines.h 　
29683
 E1000_MDIC_ERRORE1000_MDIC_ERROR 0x40000000 e1000e_defines.h 　
29684
 E1000_GEN_CTL_READYE1000_GEN_CTL_READY 0x80000000 e1000e_defines.h 　
29685
 E1000_GEN_CTL_ADDRESS_SHIFTE1000_GEN_CTL_ADDRESS_SHIFT 8 e1000e_defines.h 　
29686
 E1000_GEN_POLL_TIMEOUTE1000_GEN_POLL_TIMEOUT 640 e1000e_defines.h 　
29687
 E1000_DEV_ID_82571EB_COPPERE1000_DEV_ID_82571EB_COPPER 0x105E e1000e_hw.h 　
29688
 E1000_DEV_ID_82571EB_FIBERE1000_DEV_ID_82571EB_FIBER 0x105F e1000e_hw.h 　
29689
 E1000_DEV_ID_82571EB_SERDESE1000_DEV_ID_82571EB_SERDES 0x1060 e1000e_hw.h 　
29690
 E1000_DEV_ID_82571EB_SERDES_DUAE1000_DEV_ID_82571EB_SERDES_DUA 0x10D9 e1000e_hw.h 　
29691
 E1000_DEV_ID_82571EB_SERDES_QUAE1000_DEV_ID_82571EB_SERDES_QUA 0x10DA e1000e_hw.h 　
29692
 E1000_DEV_ID_82571EB_QUAD_COPPEE1000_DEV_ID_82571EB_QUAD_COPPE 0x10A4 e1000e_hw.h 　
29693
 E1000_DEV_ID_82571PT_QUAD_COPPEE1000_DEV_ID_82571PT_QUAD_COPPE 0x10D5 e1000e_hw.h 　
29694
 E1000_DEV_ID_82571EB_QUAD_FIBERE1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 e1000e_hw.h 　
29695
 E1000_DEV_ID_82571EB_QUAD_COPPEE1000_DEV_ID_82571EB_QUAD_COPPE 0x10BC e1000e_hw.h 　
29696
 E1000_DEV_ID_82572EI_COPPERE1000_DEV_ID_82572EI_COPPER 0x107D e1000e_hw.h 　
29697
 E1000_DEV_ID_82572EI_FIBERE1000_DEV_ID_82572EI_FIBER 0x107E e1000e_hw.h 　
29698
 E1000_DEV_ID_82572EI_SERDESE1000_DEV_ID_82572EI_SERDES 0x107F e1000e_hw.h 　
29699
 E1000_DEV_ID_82572EIE1000_DEV_ID_82572EI 0x10B9 e1000e_hw.h 　
29700
 E1000_DEV_ID_82573EE1000_DEV_ID_82573E 0x108B e1000e_hw.h 　
29701
 E1000_DEV_ID_82573E_IAMTE1000_DEV_ID_82573E_IAMT 0x108C e1000e_hw.h 　
29702
 E1000_DEV_ID_82573LE1000_DEV_ID_82573L 0x109A e1000e_hw.h 　
29703
 E1000_DEV_ID_82574LE1000_DEV_ID_82574L 0x10D3 e1000e_hw.h 　
29704
 E1000_DEV_ID_82574LAE1000_DEV_ID_82574LA 0x10F6 e1000e_hw.h 　
29705
 E1000_DEV_ID_82583VE1000_DEV_ID_82583V 0x150C e1000e_hw.h 　
29706
 E1000_DEV_ID_80003ES2LAN_COPPERE1000_DEV_ID_80003ES2LAN_COPPER 0x1096 e1000e_hw.h 　
29707
 E1000_DEV_ID_80003ES2LAN_SERDESE1000_DEV_ID_80003ES2LAN_SERDES 0x1098 e1000e_hw.h 　
29708
 E1000_DEV_ID_80003ES2LAN_COPPERE1000_DEV_ID_80003ES2LAN_COPPER 0x10BA e1000e_hw.h 　
29709
 E1000_DEV_ID_80003ES2LAN_SERDESE1000_DEV_ID_80003ES2LAN_SERDES 0x10BB e1000e_hw.h 　
29710
 E1000_DEV_ID_ICH8_82567V_3E1000_DEV_ID_ICH8_82567V_3 0x1501 e1000e_hw.h 　
29711
 E1000_DEV_ID_ICH8_IGP_M_AMTE1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 e1000e_hw.h 　
29712
 E1000_DEV_ID_ICH8_IGP_AMTE1000_DEV_ID_ICH8_IGP_AMT 0x104A e1000e_hw.h 　
29713
 E1000_DEV_ID_ICH8_IGP_CE1000_DEV_ID_ICH8_IGP_C 0x104B e1000e_hw.h 　
29714
 E1000_DEV_ID_ICH8_IFEE1000_DEV_ID_ICH8_IFE 0x104C e1000e_hw.h 　
29715
 E1000_DEV_ID_ICH8_IFE_GTE1000_DEV_ID_ICH8_IFE_GT 0x10C4 e1000e_hw.h 　
29716
 E1000_DEV_ID_ICH8_IFE_GE1000_DEV_ID_ICH8_IFE_G 0x10C5 e1000e_hw.h 　
29717
 E1000_DEV_ID_ICH8_IGP_ME1000_DEV_ID_ICH8_IGP_M 0x104D e1000e_hw.h 　
29718
 E1000_DEV_ID_ICH9_IGP_ME1000_DEV_ID_ICH9_IGP_M 0x10BF e1000e_hw.h 　
29719
 E1000_DEV_ID_ICH9_IGP_M_AMTE1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 e1000e_hw.h 　
29720
 E1000_DEV_ID_ICH9_IGP_M_VE1000_DEV_ID_ICH9_IGP_M_V 0x10CB e1000e_hw.h 　
29721
 E1000_DEV_ID_ICH9_IGP_AMTE1000_DEV_ID_ICH9_IGP_AMT 0x10BD e1000e_hw.h 　
29722
 E1000_DEV_ID_ICH9_BME1000_DEV_ID_ICH9_BM 0x10E5 e1000e_hw.h 　
29723
 E1000_DEV_ID_ICH9_IGP_CE1000_DEV_ID_ICH9_IGP_C 0x294C e1000e_hw.h 　
29724
 E1000_DEV_ID_ICH9_IFEE1000_DEV_ID_ICH9_IFE 0x10C0 e1000e_hw.h 　
29725
 E1000_DEV_ID_ICH9_IFE_GTE1000_DEV_ID_ICH9_IFE_GT 0x10C3 e1000e_hw.h 　
29726
 E1000_DEV_ID_ICH9_IFE_GE1000_DEV_ID_ICH9_IFE_G 0x10C2 e1000e_hw.h 　
29727
 E1000_DEV_ID_ICH10_R_BM_LME1000_DEV_ID_ICH10_R_BM_LM 0x10CC e1000e_hw.h 　
29728
 E1000_DEV_ID_ICH10_R_BM_LFE1000_DEV_ID_ICH10_R_BM_LF 0x10CD e1000e_hw.h 　
29729
 E1000_DEV_ID_ICH10_R_BM_VE1000_DEV_ID_ICH10_R_BM_V 0x10CE e1000e_hw.h 　
29730
 E1000_DEV_ID_ICH10_D_BM_LME1000_DEV_ID_ICH10_D_BM_LM 0x10DE e1000e_hw.h 　
29731
 E1000_DEV_ID_ICH10_D_BM_LFE1000_DEV_ID_ICH10_D_BM_LF 0x10DF e1000e_hw.h 　
29732
 E1000_DEV_ID_PCH_M_HV_LME1000_DEV_ID_PCH_M_HV_LM 0x10EA e1000e_hw.h 　
29733
 E1000_DEV_ID_PCH_M_HV_LCE1000_DEV_ID_PCH_M_HV_LC 0x10EB e1000e_hw.h 　
29734
 E1000_DEV_ID_PCH_D_HV_DME1000_DEV_ID_PCH_D_HV_DM 0x10EF e1000e_hw.h 　
29735
 E1000_DEV_ID_PCH_D_HV_DCE1000_DEV_ID_PCH_D_HV_DC 0x10F0 e1000e_hw.h 　
29736
 E1000_REVISION_0E1000_REVISION_0 0 e1000e_hw.h 　
29737
 E1000_REVISION_1E1000_REVISION_1 1 e1000e_hw.h 　
29738
 E1000_REVISION_2E1000_REVISION_2 2 e1000e_hw.h 　
29739
 E1000_REVISION_3E1000_REVISION_3 3 e1000e_hw.h 　
29740
 E1000_REVISION_4E1000_REVISION_4 4 e1000e_hw.h 　
29741
 E1000_FUNC_0E1000_FUNC_0 0 e1000e_hw.h 　
29742
 E1000_FUNC_1E1000_FUNC_1 1 e1000e_hw.h 　
29743
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 0 e1000e_hw.h 　
29744
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 3 e1000e_hw.h 　
29745
 MAX_PS_BUFFERSMAX_PS_BUFFERS 4 e1000e_hw.h 　
29746
 E1000_HI_MAX_DATA_LENGTHE1000_HI_MAX_DATA_LENGTH 252 e1000e_hw.h 　
29747
 E1000_HI_MAX_MNG_DATA_LENGTHE1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 e1000e_hw.h 　
29748
 E1000_ICH8_SHADOW_RAM_WORDSE1000_ICH8_SHADOW_RAM_WORDS 2048 e1000e_hw.h 　
29749
 ICH_FLASH_GFPREGICH_FLASH_GFPREG 0x0000 e1000e_ich8lan.h 　
29750
 ICH_FLASH_HSFSTSICH_FLASH_HSFSTS 0x0004 e1000e_ich8lan.h 　
29751
 ICH_FLASH_HSFCTLICH_FLASH_HSFCTL 0x0006 e1000e_ich8lan.h 　
29752
 ICH_FLASH_FADDRICH_FLASH_FADDR 0x0008 e1000e_ich8lan.h 　
29753
 ICH_FLASH_FDATA0ICH_FLASH_FDATA0 0x0010 e1000e_ich8lan.h 　
29754
 ICH_FLASH_READ_COMMAND_TIMEOUTICH_FLASH_READ_COMMAND_TIMEOUT 10000000 e1000e_ich8lan.h 　
29755
 ICH_FLASH_WRITE_COMMAND_TIMEOUTICH_FLASH_WRITE_COMMAND_TIMEOUT 10000000 e1000e_ich8lan.h 　
29756
 ICH_FLASH_ERASE_COMMAND_TIMEOUTICH_FLASH_ERASE_COMMAND_TIMEOUT 10000000 e1000e_ich8lan.h 　
29757
 ICH_FLASH_LINEAR_ADDR_MASKICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF e1000e_ich8lan.h 　
29758
 ICH_FLASH_CYCLE_REPEAT_COUNTICH_FLASH_CYCLE_REPEAT_COUNT 10 e1000e_ich8lan.h 　
29759
 ICH_CYCLE_READICH_CYCLE_READ 0 e1000e_ich8lan.h 　
29760
 ICH_CYCLE_WRITEICH_CYCLE_WRITE 2 e1000e_ich8lan.h 　
29761
 ICH_CYCLE_ERASEICH_CYCLE_ERASE 3 e1000e_ich8lan.h 　
29762
 FLASH_GFPREG_BASE_MASKFLASH_GFPREG_BASE_MASK 0x1FFF e1000e_ich8lan.h 　
29763
 FLASH_SECTOR_ADDR_SHIFTFLASH_SECTOR_ADDR_SHIFT 12 e1000e_ich8lan.h 　
29764
 ICH_FLASH_SEG_SIZE_256ICH_FLASH_SEG_SIZE_256 256 e1000e_ich8lan.h 　
29765
 ICH_FLASH_SEG_SIZE_4KICH_FLASH_SEG_SIZE_4K 4096 e1000e_ich8lan.h 　
29766
 ICH_FLASH_SEG_SIZE_8KICH_FLASH_SEG_SIZE_8K 8192 e1000e_ich8lan.h 　
29767
 ICH_FLASH_SEG_SIZE_64KICH_FLASH_SEG_SIZE_64K 65536 e1000e_ich8lan.h 　
29768
 ICH_FLASH_SECTOR_SIZEICH_FLASH_SECTOR_SIZE 4096 e1000e_ich8lan.h 　
29769
 ICH_FLASH_REG_MAPSIZEICH_FLASH_REG_MAPSIZE 0x00A0 e1000e_ich8lan.h 　
29770
 E1000_ICH_FWSM_RSPCIPHYE1000_ICH_FWSM_RSPCIPHY 0x00000040 e1000e_ich8lan.h Reset PHY on PCI Reset
29771
 E1000_ICH_FWSM_DISSWE1000_ICH_FWSM_DISSW 0x10000000 e1000e_ich8lan.h FW Disables SW Writes
29772
 E1000_ICH_FWSM_FW_VALIDE1000_ICH_FWSM_FW_VALID 0x00008000 e1000e_ich8lan.h 　
29773
 E1000_ICH_MNG_IAMT_MODEE1000_ICH_MNG_IAMT_MODE 0x2 e1000e_ich8lan.h 　
29774
 ID_LED_DEFAULT_ICH8LANID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_OFF1_ON2 << 4) | \ (ID_LED_DEF1_DEF2)) e1000e_ich8lan.h 　
29775
 E1000_ICH_NVM_SIG_WORDE1000_ICH_NVM_SIG_WORD 0x13 e1000e_ich8lan.h 　
29776
 E1000_ICH_NVM_SIG_MASKE1000_ICH_NVM_SIG_MASK 0xC000 e1000e_ich8lan.h 　
29777
 E1000_ICH_NVM_VALID_SIG_MASKE1000_ICH_NVM_VALID_SIG_MASK 0xC0 e1000e_ich8lan.h 　
29778
 E1000_ICH_NVM_SIG_VALUEE1000_ICH_NVM_SIG_VALUE 0x80 e1000e_ich8lan.h 　
29779
 E1000_ICH8_LAN_INIT_TIMEOUTE1000_ICH8_LAN_INIT_TIMEOUT 1500 e1000e_ich8lan.h 　
29780
 E1000_FEXTNVM_SW_CONFIGE1000_FEXTNVM_SW_CONFIG 1 e1000e_ich8lan.h 　
29781
 E1000_FEXTNVM_SW_CONFIG_ICH8ME1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) e1000e_ich8lan.h Bit redefined for ICH8M
29782
 PCIE_ICH8_SNOOP_ALLPCIE_ICH8_SNOOP_ALL PCIE_NO_SNOOP_ALL e1000e_ich8lan.h 　
29783
 E1000_ICH_RAR_ENTRIESE1000_ICH_RAR_ENTRIES 7 e1000e_ich8lan.h 　
29784
 PHY_PAGE_SHIFTPHY_PAGE_SHIFT 5 e1000e_ich8lan.h 　
29785
 IGP3_KMRN_DIAGIGP3_KMRN_DIAG PHY_REG(770, 19) e1000e_ich8lan.h KMRN Diagnostic
29786
 IGP3_VR_CTRLIGP3_VR_CTRL PHY_REG(776, 18) e1000e_ich8lan.h Voltage Regulator Control
29787
 IGP3_CAPABILITYIGP3_CAPABILITY PHY_REG(776, 19) e1000e_ich8lan.h Capability
29788
 IGP3_PM_CTRLIGP3_PM_CTRL PHY_REG(769, 20) e1000e_ich8lan.h Power Management Control
29789
 IGP3_KMRN_DIAG_PCS_LOCK_LOSSIGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 e1000e_ich8lan.h 　
29790
 IGP3_VR_CTRL_DEV_POWERDOWN_MODEIGP3_VR_CTRL_DEV_POWERDOWN_MODE 0x0300 e1000e_ich8lan.h 　
29791
 IGP3_VR_CTRL_MODE_SHUTDOWNIGP3_VR_CTRL_MODE_SHUTDOWN 0x0200 e1000e_ich8lan.h 　
29792
 IGP3_PM_CTRL_FORCE_PWR_DOWNIGP3_PM_CTRL_FORCE_PWR_DOWN 0x0020 e1000e_ich8lan.h 　
29793
 BM_RCTLBM_RCTL PHY_REG(BM_WUC_PAGE, 0) e1000e_ich8lan.h 　
29794
 BM_WUCBM_WUC PHY_REG(BM_WUC_PAGE, 1) e1000e_ich8lan.h 　
29795
 BM_WUFCBM_WUFC PHY_REG(BM_WUC_PAGE, 2) e1000e_ich8lan.h 　
29796
 BM_WUSBM_WUS PHY_REG(BM_WUC_PAGE, 3) e1000e_ich8lan.h 　
29797
 BM_RCTL_UPEBM_RCTL_UPE 0x0001 e1000e_ich8lan.h Unicast Promiscuous Mode
29798
 BM_RCTL_MPEBM_RCTL_MPE 0x0002 e1000e_ich8lan.h Multicast Promiscuous Mode
29799
 BM_RCTL_MO_SHIFTBM_RCTL_MO_SHIFT 3 e1000e_ich8lan.h Multicast Offset Shift
29800
 BM_RCTL_MO_MASKBM_RCTL_MO_MASK (3 << 3) e1000e_ich8lan.h Multicast Offset Mask
29801
 BM_RCTL_BAMBM_RCTL_BAM 0x0020 e1000e_ich8lan.h Broadcast Accept Mode
29802
 BM_RCTL_PMCFBM_RCTL_PMCF 0x0040 e1000e_ich8lan.h Pass MAC Control Frames
29803
 BM_RCTL_RFCEBM_RCTL_RFCE 0x0080 e1000e_ich8lan.h Rx Flow Control Enable
29804
 HV_LED_CONFIGHV_LED_CONFIG PHY_REG(768, 30) e1000e_ich8lan.h LED Configuration
29805
 HV_MUX_DATA_CTRLHV_MUX_DATA_CTRL PHY_REG(776, 16) e1000e_ich8lan.h 　
29806
 HV_MUX_DATA_CTRL_GEN_TO_MACHV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 e1000e_ich8lan.h 　
29807
 HV_MUX_DATA_CTRL_FORCE_SPEEDHV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 e1000e_ich8lan.h 　
29808
 HV_SCC_UPPERHV_SCC_UPPER PHY_REG(778, 16) e1000e_ich8lan.h Single Collision Count
29809
 HV_SCC_LOWERHV_SCC_LOWER PHY_REG(778, 17) e1000e_ich8lan.h 　
29810
 HV_ECOL_UPPERHV_ECOL_UPPER PHY_REG(778, 18) e1000e_ich8lan.h Excessive Collision Count
29811
 HV_ECOL_LOWERHV_ECOL_LOWER PHY_REG(778, 19) e1000e_ich8lan.h 　
29812
 HV_MCC_UPPERHV_MCC_UPPER PHY_REG(778, 20) e1000e_ich8lan.h Multiple Collision Count
29813
 HV_MCC_LOWERHV_MCC_LOWER PHY_REG(778, 21) e1000e_ich8lan.h 　
29814
 HV_LATECOL_UPPERHV_LATECOL_UPPER PHY_REG(778, 23) e1000e_ich8lan.h Late Collision Count
29815
 HV_LATECOL_LOWERHV_LATECOL_LOWER PHY_REG(778, 24) e1000e_ich8lan.h 　
29816
 HV_COLC_UPPERHV_COLC_UPPER PHY_REG(778, 25) e1000e_ich8lan.h Collision Count
29817
 HV_COLC_LOWERHV_COLC_LOWER PHY_REG(778, 26) e1000e_ich8lan.h 　
29818
 HV_DC_UPPERHV_DC_UPPER PHY_REG(778, 27) e1000e_ich8lan.h Defer Count
29819
 HV_DC_LOWERHV_DC_LOWER PHY_REG(778, 28) e1000e_ich8lan.h 　
29820
 HV_TNCRS_UPPERHV_TNCRS_UPPER PHY_REG(778, 29) e1000e_ich8lan.h Transmit with no CRS
29821
 HV_TNCRS_LOWERHV_TNCRS_LOWER PHY_REG(778, 30) e1000e_ich8lan.h 　
29822
 E1000_FCRTV_PCHE1000_FCRTV_PCH 0x05F40 e1000e_ich8lan.h PCH Flow Control Refresh Timer Value
29823
 E1000_NVM_K1_CONFIGE1000_NVM_K1_CONFIG 0x1B e1000e_ich8lan.h NVM K1 Config Word
29824
 E1000_NVM_K1_ENABLEE1000_NVM_K1_ENABLE 0x1 e1000e_ich8lan.h NVM Enable K1 bit
29825
 HV_SMB_ADDRHV_SMB_ADDR PHY_REG(768, 26) e1000e_ich8lan.h 　
29826
 HV_SMB_ADDR_PEC_ENHV_SMB_ADDR_PEC_EN 0x0200 e1000e_ich8lan.h 　
29827
 HV_SMB_ADDR_VALIDHV_SMB_ADDR_VALID 0x0080 e1000e_ich8lan.h 　
29828
 E1000_STRAPE1000_STRAP 0x0000C e1000e_ich8lan.h 　
29829
 E1000_STRAP_SMBUS_ADDRESS_MASKE1000_STRAP_SMBUS_ADDRESS_MASK 0x00FE0000 e1000e_ich8lan.h 　
29830
 E1000_STRAP_SMBUS_ADDRESS_SHIFTE1000_STRAP_SMBUS_ADDRESS_SHIFT 17 e1000e_ich8lan.h 　
29831
 HV_OEM_BITSHV_OEM_BITS PHY_REG(768, 25) e1000e_ich8lan.h 　
29832
 HV_OEM_BITS_LPLUHV_OEM_BITS_LPLU 0x0004 e1000e_ich8lan.h Low Power Link Up
29833
 HV_OEM_BITS_GBE_DISHV_OEM_BITS_GBE_DIS 0x0040 e1000e_ich8lan.h Gigabit Disable
29834
 HV_OEM_BITS_RESTART_ANHV_OEM_BITS_RESTART_AN 0x0400 e1000e_ich8lan.h Restart Auto-negotiation
29835
 LCD_CFG_PHY_ADDR_BITLCD_CFG_PHY_ADDR_BIT 0x0020 e1000e_ich8lan.h Phy address bit from LCD Config word
29836
 SW_FLAG_TIMEOUTSW_FLAG_TIMEOUT 1000 e1000e_ich8lan.h SW Semaphore flag timeout in milliseconds
29837
 IMS_ICH_ENABLE_MASKIMS_ICH_ENABLE_MASK (\ E1000_IMS_DSW | \ E1000_IMS_PHYINT | \ E1000_IMS_EPRST) e1000e_ich8lan.h 　
29838
 E1000_ICR_LSECPNCE1000_ICR_LSECPNC 0x00004000 e1000e_ich8lan.h PN threshold - client
29839
 E1000_IMS_LSECPNCE1000_IMS_LSECPNC E1000_ICR_LSECPNC e1000e_ich8lan.h PN threshold - client
29840
 E1000_ICS_LSECPNCE1000_ICS_LSECPNC E1000_ICR_LSECPNC e1000e_ich8lan.h PN threshold - client
29841
 E1000_RXDEXT_LINKSEC_STATUS_LSEE1000_RXDEXT_LINKSEC_STATUS_LSE 0x01000000 e1000e_ich8lan.h 　
29842
 E1000_RXDEXT_LINKSEC_ERROR_BIT_E1000_RXDEXT_LINKSEC_ERROR_BIT_ 0x60000000 e1000e_ich8lan.h 　
29843
 E1000_RXDEXT_LINKSEC_ERROR_NO_SE1000_RXDEXT_LINKSEC_ERROR_NO_S 0x20000000 e1000e_ich8lan.h 　
29844
 E1000_RXDEXT_LINKSEC_ERROR_REPLE1000_RXDEXT_LINKSEC_ERROR_REPL 0x40000000 e1000e_ich8lan.h 　
29845
 E1000_RXDEXT_LINKSEC_ERROR_BAD_E1000_RXDEXT_LINKSEC_ERROR_BAD_ 0x60000000 e1000e_ich8lan.h 　
29846
 E1000_FACTPS_MNGCGE1000_FACTPS_MNGCG 0x20000000 e1000e_manage.h 　
29847
 E1000_FWSM_MODE_MASKE1000_FWSM_MODE_MASK 0xE e1000e_manage.h 　
29848
 E1000_FWSM_MODE_SHIFTE1000_FWSM_MODE_SHIFT 1 e1000e_manage.h 　
29849
 E1000_MNG_IAMT_MODEE1000_MNG_IAMT_MODE 0x3 e1000e_manage.h 　
29850
 E1000_MNG_DHCP_COOKIE_LENGTHE1000_MNG_DHCP_COOKIE_LENGTH 0x10 e1000e_manage.h 　
29851
 E1000_MNG_DHCP_COOKIE_OFFSETE1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 e1000e_manage.h 　
29852
 E1000_MNG_DHCP_COMMAND_TIMEOUTE1000_MNG_DHCP_COMMAND_TIMEOUT 10 e1000e_manage.h 　
29853
 E1000_MNG_DHCP_TX_PAYLOAD_CMDE1000_MNG_DHCP_TX_PAYLOAD_CMD 64 e1000e_manage.h 　
29854
 E1000_MNG_DHCP_COOKIE_STATUS_PAE1000_MNG_DHCP_COOKIE_STATUS_PA 0x1 e1000e_manage.h 　
29855
 E1000_MNG_DHCP_COOKIE_STATUS_VLE1000_MNG_DHCP_COOKIE_STATUS_VL 0x2 e1000e_manage.h 　
29856
 E1000_VFTA_ENTRY_SHIFTE1000_VFTA_ENTRY_SHIFT 5 e1000e_manage.h 　
29857
 E1000_VFTA_ENTRY_MASKE1000_VFTA_ENTRY_MASK 0x7F e1000e_manage.h 　
29858
 E1000_VFTA_ENTRY_BIT_SHIFT_MASKE1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F e1000e_manage.h 　
29859
 E1000_HI_MAX_BLOCK_BYTE_LENGTHE1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 e1000e_manage.h Num of bytes in range
29860
 E1000_HI_MAX_BLOCK_DWORD_LENGTHE1000_HI_MAX_BLOCK_DWORD_LENGTH 448 e1000e_manage.h Num of dwords in range
29861
 E1000_HI_COMMAND_TIMEOUTE1000_HI_COMMAND_TIMEOUT 500 e1000e_manage.h Process HI command limit
29862
 E1000_HICR_ENE1000_HICR_EN 0x01 e1000e_manage.h Enable bit - RO
29863
 E1000_HICR_CE1000_HICR_C 0x02 e1000e_manage.h 　
29864
 E1000_HICR_SVE1000_HICR_SV 0x04 e1000e_manage.h Status Validity
29865
 E1000_HICR_FW_RESET_ENABLEE1000_HICR_FW_RESET_ENABLE 0x40 e1000e_manage.h 　
29866
 E1000_HICR_FW_RESETE1000_HICR_FW_RESET 0x80 e1000e_manage.h 　
29867
 E1000_IAMT_SIGNATUREE1000_IAMT_SIGNATURE 0x544D4149 e1000e_manage.h 　
29868
 E1000_STM_OPCODEE1000_STM_OPCODE 0xDB00 e1000e_nvm.h 　
29869
 E1000_MAX_PHY_ADDRE1000_MAX_PHY_ADDR 4 e1000e_phy.h 　
29870
 IGP01E1000_PHY_PORT_CONFIGIGP01E1000_PHY_PORT_CONFIG 0x10 e1000e_phy.h Port Config
29871
 IGP01E1000_PHY_PORT_STATUSIGP01E1000_PHY_PORT_STATUS 0x11 e1000e_phy.h Status
29872
 IGP01E1000_PHY_PORT_CTRLIGP01E1000_PHY_PORT_CTRL 0x12 e1000e_phy.h Control
29873
 IGP01E1000_PHY_LINK_HEALTHIGP01E1000_PHY_LINK_HEALTH 0x13 e1000e_phy.h PHY Link Health
29874
 IGP01E1000_GMII_FIFOIGP01E1000_GMII_FIFO 0x14 e1000e_phy.h GMII FIFO
29875
 IGP01E1000_PHY_CHANNEL_QUALITYIGP01E1000_PHY_CHANNEL_QUALITY 0x15 e1000e_phy.h PHY Channel Quality
29876
 IGP02E1000_PHY_POWER_MGMTIGP02E1000_PHY_POWER_MGMT 0x19 e1000e_phy.h Power Management
29877
 IGP01E1000_PHY_PAGE_SELECTIGP01E1000_PHY_PAGE_SELECT 0x1F e1000e_phy.h Page Select
29878
 BM_PHY_PAGE_SELECTBM_PHY_PAGE_SELECT 22 e1000e_phy.h Page Select for BM
29879
 IGP_PAGE_SHIFTIGP_PAGE_SHIFT 5 e1000e_phy.h 　
29880
 PHY_REG_MASKPHY_REG_MASK 0x1F e1000e_phy.h 　
29881
 BM_PORT_CTRL_PAGEBM_PORT_CTRL_PAGE 769 e1000e_phy.h 　
29882
 BM_PCIE_PAGEBM_PCIE_PAGE 770 e1000e_phy.h 　
29883
 BM_WUC_PAGEBM_WUC_PAGE 800 e1000e_phy.h 　
29884
 BM_WUC_ADDRESS_OPCODEBM_WUC_ADDRESS_OPCODE 0x11 e1000e_phy.h 　
29885
 BM_WUC_DATA_OPCODEBM_WUC_DATA_OPCODE 0x12 e1000e_phy.h 　
29886
 BM_WUC_ENABLE_PAGEBM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE e1000e_phy.h 　
29887
 BM_WUC_ENABLE_REGBM_WUC_ENABLE_REG 17 e1000e_phy.h 　
29888
 BM_WUC_ENABLE_BITBM_WUC_ENABLE_BIT (1 << 2) e1000e_phy.h 　
29889
 BM_WUC_HOST_WU_BITBM_WUC_HOST_WU_BIT (1 << 4) e1000e_phy.h 　
29890
 PHY_UPPER_SHIFTPHY_UPPER_SHIFT 21 e1000e_phy.h 　
29891
 HV_INTC_FC_PAGE_STARTHV_INTC_FC_PAGE_START 768 e1000e_phy.h 　
29892
 I82578_ADDR_REGI82578_ADDR_REG 29 e1000e_phy.h 　
29893
 I82577_ADDR_REGI82577_ADDR_REG 16 e1000e_phy.h 　
29894
 I82577_CFG_REGI82577_CFG_REG 22 e1000e_phy.h 　
29895
 I82577_CFG_ASSERT_CRS_ON_TXI82577_CFG_ASSERT_CRS_ON_TX (1 << 15) e1000e_phy.h 　
29896
 I82577_CFG_ENABLE_DOWNSHIFTI82577_CFG_ENABLE_DOWNSHIFT (3 << 10) e1000e_phy.h auto downshift 100/10
29897
 I82577_CTRL_REGI82577_CTRL_REG 23 e1000e_phy.h 　
29898
 I82577_PHY_CTRL_2I82577_PHY_CTRL_2 18 e1000e_phy.h 　
29899
 I82577_PHY_LBK_CTRLI82577_PHY_LBK_CTRL 19 e1000e_phy.h 　
29900
 I82577_PHY_STATUS_2I82577_PHY_STATUS_2 26 e1000e_phy.h 　
29901
 I82577_PHY_DIAG_STATUSI82577_PHY_DIAG_STATUS 31 e1000e_phy.h 　
29902
 I82577_PHY_STATUS2_REV_POLARITYI82577_PHY_STATUS2_REV_POLARITY 0x0400 e1000e_phy.h 　
29903
 I82577_PHY_STATUS2_MDIXI82577_PHY_STATUS2_MDIX 0x0800 e1000e_phy.h 　
29904
 I82577_PHY_STATUS2_SPEED_MASKI82577_PHY_STATUS2_SPEED_MASK 0x0300 e1000e_phy.h 　
29905
 I82577_PHY_STATUS2_SPEED_1000MBI82577_PHY_STATUS2_SPEED_1000MB 0x0200 e1000e_phy.h 　
29906
 I82577_PHY_STATUS2_SPEED_100MBPI82577_PHY_STATUS2_SPEED_100MBP 0x0100 e1000e_phy.h 　
29907
 I82577_PHY_CTRL2_AUTO_MDIXI82577_PHY_CTRL2_AUTO_MDIX 0x0400 e1000e_phy.h 　
29908
 I82577_PHY_CTRL2_FORCE_MDI_MDIXI82577_PHY_CTRL2_FORCE_MDI_MDIX 0x0200 e1000e_phy.h 　
29909
 I82577_DSTATUS_CABLE_LENGTHI82577_DSTATUS_CABLE_LENGTH 0x03FC e1000e_phy.h 　
29910
 I82577_DSTATUS_CABLE_LENGTH_SHII82577_DSTATUS_CABLE_LENGTH_SHI 2 e1000e_phy.h 　
29911
 BM_CS_CTRL1BM_CS_CTRL1 16 e1000e_phy.h 　
29912
 BM_CS_CTRL1_ENERGY_DETECTBM_CS_CTRL1_ENERGY_DETECT 0x0300 e1000e_phy.h Enable Energy Detect
29913
 BM_CS_STATUSBM_CS_STATUS 17 e1000e_phy.h 　
29914
 BM_CS_STATUS_ENERGY_DETECTBM_CS_STATUS_ENERGY_DETECT 0x0010 e1000e_phy.h Energy Detect Status
29915
 BM_CS_STATUS_LINK_UPBM_CS_STATUS_LINK_UP 0x0400 e1000e_phy.h 　
29916
 BM_CS_STATUS_RESOLVEDBM_CS_STATUS_RESOLVED 0x0800 e1000e_phy.h 　
29917
 BM_CS_STATUS_SPEED_MASKBM_CS_STATUS_SPEED_MASK 0xC000 e1000e_phy.h 　
29918
 BM_CS_STATUS_SPEED_1000BM_CS_STATUS_SPEED_1000 0x8000 e1000e_phy.h 　
29919
 HV_M_STATUSHV_M_STATUS 26 e1000e_phy.h 　
29920
 HV_M_STATUS_AUTONEG_COMPLETEHV_M_STATUS_AUTONEG_COMPLETE 0x1000 e1000e_phy.h 　
29921
 HV_M_STATUS_SPEED_MASKHV_M_STATUS_SPEED_MASK 0x0300 e1000e_phy.h 　
29922
 HV_M_STATUS_SPEED_1000HV_M_STATUS_SPEED_1000 0x0200 e1000e_phy.h 　
29923
 HV_M_STATUS_LINK_UPHV_M_STATUS_LINK_UP 0x0040 e1000e_phy.h 　
29924
 IGP01E1000_PHY_PCS_INIT_REGIGP01E1000_PHY_PCS_INIT_REG 0x00B4 e1000e_phy.h 　
29925
 IGP01E1000_PHY_POLARITY_MASKIGP01E1000_PHY_POLARITY_MASK 0x0078 e1000e_phy.h 　
29926
 IGP01E1000_PSCR_AUTO_MDIXIGP01E1000_PSCR_AUTO_MDIX 0x1000 e1000e_phy.h 　
29927
 IGP01E1000_PSCR_FORCE_MDI_MDIXIGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 e1000e_phy.h 0=MDI, 1=MDIX
29928
 IGP01E1000_PSCFR_SMART_SPEEDIGP01E1000_PSCFR_SMART_SPEED 0x0080 e1000e_phy.h 　
29929
 IGP01E1000_GMII_FLEX_SPDIGP01E1000_GMII_FLEX_SPD 0x0010 e1000e_phy.h 　
29930
 IGP01E1000_GMII_SPDIGP01E1000_GMII_SPD 0x0020 e1000e_phy.h Enable SPD
29931
 IGP02E1000_PM_SPDIGP02E1000_PM_SPD 0x0001 e1000e_phy.h Smart Power Down
29932
 IGP02E1000_PM_D0_LPLUIGP02E1000_PM_D0_LPLU 0x0002 e1000e_phy.h For D0a states
29933
 IGP02E1000_PM_D3_LPLUIGP02E1000_PM_D3_LPLU 0x0004 e1000e_phy.h For all other states
29934
 IGP01E1000_PLHR_SS_DOWNGRADEIGP01E1000_PLHR_SS_DOWNGRADE 0x8000 e1000e_phy.h 　
29935
 IGP01E1000_PSSR_POLARITY_REVERSIGP01E1000_PSSR_POLARITY_REVERS 0x0002 e1000e_phy.h 　
29936
 IGP01E1000_PSSR_MDIXIGP01E1000_PSSR_MDIX 0x0800 e1000e_phy.h 　
29937
 IGP01E1000_PSSR_SPEED_MASKIGP01E1000_PSSR_SPEED_MASK 0xC000 e1000e_phy.h 　
29938
 IGP01E1000_PSSR_SPEED_1000MBPSIGP01E1000_PSSR_SPEED_1000MBPS 0xC000 e1000e_phy.h 　
29939
 IGP02E1000_PHY_CHANNEL_NUMIGP02E1000_PHY_CHANNEL_NUM 4 e1000e_phy.h 　
29940
 IGP02E1000_PHY_AGC_AIGP02E1000_PHY_AGC_A 0x11B1 e1000e_phy.h 　
29941
 IGP02E1000_PHY_AGC_BIGP02E1000_PHY_AGC_B 0x12B1 e1000e_phy.h 　
29942
 IGP02E1000_PHY_AGC_CIGP02E1000_PHY_AGC_C 0x14B1 e1000e_phy.h 　
29943
 IGP02E1000_PHY_AGC_DIGP02E1000_PHY_AGC_D 0x18B1 e1000e_phy.h 　
29944
 IGP02E1000_AGC_LENGTH_SHIFTIGP02E1000_AGC_LENGTH_SHIFT 9 e1000e_phy.h Course - 15:13, Fine - 12:9
29945
 IGP02E1000_AGC_LENGTH_MASKIGP02E1000_AGC_LENGTH_MASK 0x7F e1000e_phy.h 　
29946
 IGP02E1000_AGC_RANGEIGP02E1000_AGC_RANGE 15 e1000e_phy.h 　
29947
 IGP03E1000_PHY_MISC_CTRLIGP03E1000_PHY_MISC_CTRL 0x1B e1000e_phy.h 　
29948
 IGP03E1000_PHY_MISC_DUPLEX_MANUIGP03E1000_PHY_MISC_DUPLEX_MANU 0x1000 e1000e_phy.h Manually Set Duplex
29949
 E1000_CABLE_LENGTH_UNDEFINEDE1000_CABLE_LENGTH_UNDEFINED 0xFF e1000e_phy.h 　
29950
 E1000_KMRNCTRLSTA_OFFSETE1000_KMRNCTRLSTA_OFFSET 0x001F0000 e1000e_phy.h 　
29951
 E1000_KMRNCTRLSTA_OFFSET_SHIFTE1000_KMRNCTRLSTA_OFFSET_SHIFT 16 e1000e_phy.h 　
29952
 E1000_KMRNCTRLSTA_RENE1000_KMRNCTRLSTA_REN 0x00200000 e1000e_phy.h 　
29953
 E1000_KMRNCTRLSTA_DIAG_OFFSETE1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 e1000e_phy.h Kumeran Diagnostic
29954
 E1000_KMRNCTRLSTA_TIMEOUTSE1000_KMRNCTRLSTA_TIMEOUTS 0x4 e1000e_phy.h Kumeran Timeouts
29955
 E1000_KMRNCTRLSTA_INBAND_PARAME1000_KMRNCTRLSTA_INBAND_PARAM 0x9 e1000e_phy.h Kumeran InBand Parameters
29956
 E1000_KMRNCTRLSTA_DIAG_NELPBKE1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 e1000e_phy.h Nearend Loopback mode
29957
 E1000_KMRNCTRLSTA_K1_CONFIGE1000_KMRNCTRLSTA_K1_CONFIG 0x7 e1000e_phy.h 　
29958
 E1000_KMRNCTRLSTA_K1_ENABLEE1000_KMRNCTRLSTA_K1_ENABLE 0x0002 e1000e_phy.h 　
29959
 IFE_PHY_EXTENDED_STATUS_CONTROLIFE_PHY_EXTENDED_STATUS_CONTROL 0x10 e1000e_phy.h 　
29960
 IFE_PHY_SPECIAL_CONTROLIFE_PHY_SPECIAL_CONTROL 0x11 e1000e_phy.h 100BaseTx PHY Special Control
29961
 IFE_PHY_SPECIAL_CONTROL_LEDIFE_PHY_SPECIAL_CONTROL_LED 0x1B e1000e_phy.h PHY Special and LED Control
29962
 IFE_PHY_MDIX_CONTROLIFE_PHY_MDIX_CONTROL 0x1C e1000e_phy.h MDI/MDI-X Control
29963
 IFE_PESC_POLARITY_REVERSEDIFE_PESC_POLARITY_REVERSED 0x0100 e1000e_phy.h 　
29964
 IFE_PSC_AUTO_POLARITY_DISABLEIFE_PSC_AUTO_POLARITY_DISABLE 0x0010 e1000e_phy.h 　
29965
 IFE_PSC_FORCE_POLARITYIFE_PSC_FORCE_POLARITY 0x0020 e1000e_phy.h 　
29966
 IFE_PSC_DISABLE_DYNAMIC_POWER_DIFE_PSC_DISABLE_DYNAMIC_POWER_D 0x0100 e1000e_phy.h 　
29967
 IFE_PSCL_PROBE_MODEIFE_PSCL_PROBE_MODE 0x0020 e1000e_phy.h 　
29968
 IFE_PSCL_PROBE_LEDS_OFFIFE_PSCL_PROBE_LEDS_OFF 0x0006 e1000e_phy.h Force LEDs 0 and 2 off
29969
 IFE_PSCL_PROBE_LEDS_ONIFE_PSCL_PROBE_LEDS_ON 0x0007 e1000e_phy.h Force LEDs 0 and 2 on
29970
 IFE_PMC_MDIX_STATUSIFE_PMC_MDIX_STATUS 0x0020 e1000e_phy.h 1=MDI-X, 0=MDI
29971
 IFE_PMC_FORCE_MDIXIFE_PMC_FORCE_MDIX 0x0040 e1000e_phy.h 1=force MDI-X, 0=force MDI
29972
 IFE_PMC_AUTO_MDIXIFE_PMC_AUTO_MDIX 0x0080 e1000e_phy.h 1=enable auto MDI/MDI-X, 0=disable
29973
 E1000_CTRLE1000_CTRL 0x00000 e1000e_regs.h Device Control - RW
29974
 E1000_CTRL_DUPE1000_CTRL_DUP 0x00004 e1000e_regs.h Device Control Duplicate (Shadow) - RW
29975
 E1000_STATUSE1000_STATUS 0x00008 e1000e_regs.h Device Status - RO
29976
 E1000_EECDE1000_EECD 0x00010 e1000e_regs.h EEPROM/Flash Control - RW
29977
 E1000_EERDE1000_EERD 0x00014 e1000e_regs.h EEPROM Read - RW
29978
 E1000_CTRL_EXTE1000_CTRL_EXT 0x00018 e1000e_regs.h Extended Device Control - RW
29979
 E1000_FLAE1000_FLA 0x0001C e1000e_regs.h Flash Access - RW
29980
 E1000_MDICE1000_MDIC 0x00020 e1000e_regs.h MDI Control - RW
29981
 E1000_SCTLE1000_SCTL 0x00024 e1000e_regs.h SerDes Control - RW
29982
 E1000_FCALE1000_FCAL 0x00028 e1000e_regs.h Flow Control Address Low - RW
29983
 E1000_FCAHE1000_FCAH 0x0002C e1000e_regs.h Flow Control Address High -RW
29984
 E1000_FEXTE1000_FEXT 0x0002C e1000e_regs.h Future Extended - RW
29985
 E1000_FEXTNVME1000_FEXTNVM 0x00028 e1000e_regs.h Future Extended NVM - RW
29986
 E1000_FCTE1000_FCT 0x00030 e1000e_regs.h Flow Control Type - RW
29987
 E1000_CONNSWE1000_CONNSW 0x00034 e1000e_regs.h Copper/Fiber switch control - RW
29988
 E1000_VETE1000_VET 0x00038 e1000e_regs.h VLAN Ether Type - RW
29989
 E1000_ICRE1000_ICR 0x000C0 e1000e_regs.h Interrupt Cause Read - R/clr
29990
 E1000_ITRE1000_ITR 0x000C4 e1000e_regs.h Interrupt Throttling Rate - RW
29991
 E1000_ICSE1000_ICS 0x000C8 e1000e_regs.h Interrupt Cause Set - WO
29992
 E1000_IMSE1000_IMS 0x000D0 e1000e_regs.h Interrupt Mask Set - RW
29993
 E1000_IMCE1000_IMC 0x000D8 e1000e_regs.h Interrupt Mask Clear - WO
29994
 E1000_IAME1000_IAM 0x000E0 e1000e_regs.h Interrupt Acknowledge Auto Mask
29995
 E1000_IVARE1000_IVAR 0x000E4 e1000e_regs.h Interrupt Vector Allocation Register - RW
29996
 E1000_SVCRE1000_SVCR 0x000F0 e1000e_regs.h 　
29997
 E1000_SVTE1000_SVT 0x000F4 e1000e_regs.h 　
29998
 E1000_RCTLE1000_RCTL 0x00100 e1000e_regs.h Rx Control - RW
29999
 E1000_FCTTVE1000_FCTTV 0x00170 e1000e_regs.h Flow Control Transmit Timer Value - RW
30000
 E1000_TXCWE1000_TXCW 0x00178 e1000e_regs.h Tx Configuration Word - RW
30001
 E1000_RXCWE1000_RXCW 0x00180 e1000e_regs.h Rx Configuration Word - RO
30002
 E1000_PBA_ECCE1000_PBA_ECC 0x01100 e1000e_regs.h PBA ECC Register
30003
 E1000_TCTLE1000_TCTL 0x00400 e1000e_regs.h Tx Control - RW
30004
 E1000_TCTL_EXTE1000_TCTL_EXT 0x00404 e1000e_regs.h Extended Tx Control - RW
30005
 E1000_TIPGE1000_TIPG 0x00410 e1000e_regs.h Tx Inter-packet gap -RW
30006
 E1000_TBTE1000_TBT 0x00448 e1000e_regs.h Tx Burst Timer - RW
30007
 E1000_AITE1000_AIT 0x00458 e1000e_regs.h Adaptive Interframe Spacing Throttle - RW
30008
 E1000_LEDCTLE1000_LEDCTL 0x00E00 e1000e_regs.h LED Control - RW
30009
 E1000_EXTCNF_CTRLE1000_EXTCNF_CTRL 0x00F00 e1000e_regs.h Extended Configuration Control
30010
 E1000_EXTCNF_SIZEE1000_EXTCNF_SIZE 0x00F08 e1000e_regs.h Extended Configuration Size
30011
 E1000_PHY_CTRLE1000_PHY_CTRL 0x00F10 e1000e_regs.h PHY Control Register in CSR
30012
 E1000_PBAE1000_PBA 0x01000 e1000e_regs.h Packet Buffer Allocation - RW
30013
 E1000_PBSE1000_PBS 0x01008 e1000e_regs.h Packet Buffer Size
30014
 E1000_EEMNGCTLE1000_EEMNGCTL 0x01010 e1000e_regs.h MNG EEprom Control
30015
 E1000_EEARBCE1000_EEARBC 0x01024 e1000e_regs.h EEPROM Auto Read Bus Control
30016
 E1000_FLASHTE1000_FLASHT 0x01028 e1000e_regs.h FLASH Timer Register
30017
 E1000_EEWRE1000_EEWR 0x0102C e1000e_regs.h EEPROM Write Register - RW
30018
 E1000_FLSWCTLE1000_FLSWCTL 0x01030 e1000e_regs.h FLASH control register
30019
 E1000_FLSWDATAE1000_FLSWDATA 0x01034 e1000e_regs.h FLASH data register
30020
 E1000_FLSWCNTE1000_FLSWCNT 0x01038 e1000e_regs.h FLASH Access Counter
30021
 E1000_FLOPE1000_FLOP 0x0103C e1000e_regs.h FLASH Opcode Register
30022
 E1000_I2CCMDE1000_I2CCMD 0x01028 e1000e_regs.h SFPI2C Command Register - RW
30023
 E1000_I2CPARAMSE1000_I2CPARAMS 0x0102C e1000e_regs.h SFPI2C Parameters Register - RW
30024
 E1000_WDSTPE1000_WDSTP 0x01040 e1000e_regs.h Watchdog Setup - RW
30025
 E1000_SWDSTSE1000_SWDSTS 0x01044 e1000e_regs.h SW Device Status - RW
30026
 E1000_FRTIMERE1000_FRTIMER 0x01048 e1000e_regs.h Free Running Timer - RW
30027
 E1000_ERTE1000_ERT 0x02008 e1000e_regs.h Early Rx Threshold - RW
30028
 E1000_FCRTLE1000_FCRTL 0x02160 e1000e_regs.h Flow Control Receive Threshold Low - RW
30029
 E1000_FCRTHE1000_FCRTH 0x02168 e1000e_regs.h Flow Control Receive Threshold High - RW
30030
 E1000_PSRCTLE1000_PSRCTL 0x02170 e1000e_regs.h Packet Split Receive Control - RW
30031
 E1000_PBRTHE1000_PBRTH 0x02458 e1000e_regs.h PB Rx Arbitration Threshold - RW
30032
 E1000_FCRTVE1000_FCRTV 0x02460 e1000e_regs.h Flow Control Refresh Timer Value - RW
30033
 E1000_RDPUMBE1000_RDPUMB 0x025CC e1000e_regs.h DMA Rx Descriptor uC Mailbox - RW
30034
 E1000_RDPUADE1000_RDPUAD 0x025D0 e1000e_regs.h DMA Rx Descriptor uC Addr Command - RW
30035
 E1000_RDPUWDE1000_RDPUWD 0x025D4 e1000e_regs.h DMA Rx Descriptor uC Data Write - RW
30036
 E1000_RDPURDE1000_RDPURD 0x025D8 e1000e_regs.h DMA Rx Descriptor uC Data Read - RW
30037
 E1000_RDPUCTLE1000_RDPUCTL 0x025DC e1000e_regs.h DMA Rx Descriptor uC Control - RW
30038
 E1000_RDTRE1000_RDTR 0x02820 e1000e_regs.h Rx Delay Timer - RW
30039
 E1000_RADVE1000_RADV 0x0282C e1000e_regs.h Rx Interrupt Absolute Delay Timer - RW
30040
 E1000_RSRPDE1000_RSRPD 0x02C00 e1000e_regs.h Rx Small Packet Detect - RW
30041
 E1000_RAIDE1000_RAID 0x02C08 e1000e_regs.h Receive Ack Interrupt Delay - RW
30042
 E1000_TXDMACE1000_TXDMAC 0x03000 e1000e_regs.h Tx DMA Control - RW
30043
 E1000_KABGTXDE1000_KABGTXD 0x03004 e1000e_regs.h AFE Band Gap Transmit Ref Data
30044
 E1000_TDFHE1000_TDFH 0x03410 e1000e_regs.h Tx Data FIFO Head - RW
30045
 E1000_TDFTE1000_TDFT 0x03418 e1000e_regs.h Tx Data FIFO Tail - RW
30046
 E1000_TDFHSE1000_TDFHS 0x03420 e1000e_regs.h Tx Data FIFO Head Saved - RW
30047
 E1000_TDFTSE1000_TDFTS 0x03428 e1000e_regs.h Tx Data FIFO Tail Saved - RW
30048
 E1000_TDFPCE1000_TDFPC 0x03430 e1000e_regs.h Tx Data FIFO Packet Count - RW
30049
 E1000_TDPUMBE1000_TDPUMB 0x0357C e1000e_regs.h DMA Tx Descriptor uC Mail Box - RW
30050
 E1000_TDPUADE1000_TDPUAD 0x03580 e1000e_regs.h DMA Tx Descriptor uC Addr Command - RW
30051
 E1000_TDPUWDE1000_TDPUWD 0x03584 e1000e_regs.h DMA Tx Descriptor uC Data Write - RW
30052
 E1000_TDPURDE1000_TDPURD 0x03588 e1000e_regs.h DMA Tx Descriptor uC Data Read - RW
30053
 E1000_TDPUCTLE1000_TDPUCTL 0x0358C e1000e_regs.h DMA Tx Descriptor uC Control - RW
30054
 E1000_DTXCTLE1000_DTXCTL 0x03590 e1000e_regs.h DMA Tx Control - RW
30055
 E1000_TIDVE1000_TIDV 0x03820 e1000e_regs.h Tx Interrupt Delay Value - RW
30056
 E1000_TADVE1000_TADV 0x0382C e1000e_regs.h Tx Interrupt Absolute Delay Val - RW
30057
 E1000_TSPMTE1000_TSPMT 0x03830 e1000e_regs.h TCP Segmentation PAD & Min Threshold - RW
30058
 E1000_CRCERRSE1000_CRCERRS 0x04000 e1000e_regs.h CRC Error Count - R/clr
30059
 E1000_ALGNERRCE1000_ALGNERRC 0x04004 e1000e_regs.h Alignment Error Count - R/clr
30060
 E1000_SYMERRSE1000_SYMERRS 0x04008 e1000e_regs.h Symbol Error Count - R/clr
30061
 E1000_RXERRCE1000_RXERRC 0x0400C e1000e_regs.h Receive Error Count - R/clr
30062
 E1000_MPCE1000_MPC 0x04010 e1000e_regs.h Missed Packet Count - R/clr
30063
 E1000_SCCE1000_SCC 0x04014 e1000e_regs.h Single Collision Count - R/clr
30064
 E1000_ECOLE1000_ECOL 0x04018 e1000e_regs.h Excessive Collision Count - R/clr
30065
 E1000_MCCE1000_MCC 0x0401C e1000e_regs.h Multiple Collision Count - R/clr
30066
 E1000_LATECOLE1000_LATECOL 0x04020 e1000e_regs.h Late Collision Count - R/clr
30067
 E1000_COLCE1000_COLC 0x04028 e1000e_regs.h Collision Count - R/clr
30068
 E1000_DCE1000_DC 0x04030 e1000e_regs.h Defer Count - R/clr
30069
 E1000_TNCRSE1000_TNCRS 0x04034 e1000e_regs.h Tx-No CRS - R/clr
30070
 E1000_SECE1000_SEC 0x04038 e1000e_regs.h Sequence Error Count - R/clr
30071
 E1000_CEXTERRE1000_CEXTERR 0x0403C e1000e_regs.h Carrier Extension Error Count - R/clr
30072
 E1000_RLECE1000_RLEC 0x04040 e1000e_regs.h Receive Length Error Count - R/clr
30073
 E1000_XONRXCE1000_XONRXC 0x04048 e1000e_regs.h XON Rx Count - R/clr
30074
 E1000_XONTXCE1000_XONTXC 0x0404C e1000e_regs.h XON Tx Count - R/clr
30075
 E1000_XOFFRXCE1000_XOFFRXC 0x04050 e1000e_regs.h XOFF Rx Count - R/clr
30076
 E1000_XOFFTXCE1000_XOFFTXC 0x04054 e1000e_regs.h XOFF Tx Count - R/clr
30077
 E1000_FCRUCE1000_FCRUC 0x04058 e1000e_regs.h Flow Control Rx Unsupported Count- R/clr
30078
 E1000_PRC64E1000_PRC64 0x0405C e1000e_regs.h Packets Rx (64 bytes) - R/clr
30079
 E1000_PRC127E1000_PRC127 0x04060 e1000e_regs.h Packets Rx (65-127 bytes) - R/clr
30080
 E1000_PRC255E1000_PRC255 0x04064 e1000e_regs.h Packets Rx (128-255 bytes) - R/clr
30081
 E1000_PRC511E1000_PRC511 0x04068 e1000e_regs.h Packets Rx (255-511 bytes) - R/clr
30082
 E1000_PRC1023E1000_PRC1023 0x0406C e1000e_regs.h Packets Rx (512-1023 bytes) - R/clr
30083
 E1000_PRC1522E1000_PRC1522 0x04070 e1000e_regs.h Packets Rx (1024-1522 bytes) - R/clr
30084
 E1000_GPRCE1000_GPRC 0x04074 e1000e_regs.h Good Packets Rx Count - R/clr
30085
 E1000_BPRCE1000_BPRC 0x04078 e1000e_regs.h Broadcast Packets Rx Count - R/clr
30086
 E1000_MPRCE1000_MPRC 0x0407C e1000e_regs.h Multicast Packets Rx Count - R/clr
30087
 E1000_GPTCE1000_GPTC 0x04080 e1000e_regs.h Good Packets Tx Count - R/clr
30088
 E1000_GORCLE1000_GORCL 0x04088 e1000e_regs.h Good Octets Rx Count Low - R/clr
30089
 E1000_GORCHE1000_GORCH 0x0408C e1000e_regs.h Good Octets Rx Count High - R/clr
30090
 E1000_GOTCLE1000_GOTCL 0x04090 e1000e_regs.h Good Octets Tx Count Low - R/clr
30091
 E1000_GOTCHE1000_GOTCH 0x04094 e1000e_regs.h Good Octets Tx Count High - R/clr
30092
 E1000_RNBCE1000_RNBC 0x040A0 e1000e_regs.h Rx No Buffers Count - R/clr
30093
 E1000_RUCE1000_RUC 0x040A4 e1000e_regs.h Rx Undersize Count - R/clr
30094
 E1000_RFCE1000_RFC 0x040A8 e1000e_regs.h Rx Fragment Count - R/clr
30095
 E1000_ROCE1000_ROC 0x040AC e1000e_regs.h Rx Oversize Count - R/clr
30096
 E1000_RJCE1000_RJC 0x040B0 e1000e_regs.h Rx Jabber Count - R/clr
30097
 E1000_MGTPRCE1000_MGTPRC 0x040B4 e1000e_regs.h Management Packets Rx Count - R/clr
30098
 E1000_MGTPDCE1000_MGTPDC 0x040B8 e1000e_regs.h Management Packets Dropped Count - R/clr
30099
 E1000_MGTPTCE1000_MGTPTC 0x040BC e1000e_regs.h Management Packets Tx Count - R/clr
30100
 E1000_TORLE1000_TORL 0x040C0 e1000e_regs.h Total Octets Rx Low - R/clr
30101
 E1000_TORHE1000_TORH 0x040C4 e1000e_regs.h Total Octets Rx High - R/clr
30102
 E1000_TOTLE1000_TOTL 0x040C8 e1000e_regs.h Total Octets Tx Low - R/clr
30103
 E1000_TOTHE1000_TOTH 0x040CC e1000e_regs.h Total Octets Tx High - R/clr
30104
 E1000_TPRE1000_TPR 0x040D0 e1000e_regs.h Total Packets Rx - R/clr
30105
 E1000_TPTE1000_TPT 0x040D4 e1000e_regs.h Total Packets Tx - R/clr
30106
 E1000_PTC64E1000_PTC64 0x040D8 e1000e_regs.h Packets Tx (64 bytes) - R/clr
30107
 E1000_PTC127E1000_PTC127 0x040DC e1000e_regs.h Packets Tx (65-127 bytes) - R/clr
30108
 E1000_PTC255E1000_PTC255 0x040E0 e1000e_regs.h Packets Tx (128-255 bytes) - R/clr
30109
 E1000_PTC511E1000_PTC511 0x040E4 e1000e_regs.h Packets Tx (256-511 bytes) - R/clr
30110
 E1000_PTC1023E1000_PTC1023 0x040E8 e1000e_regs.h Packets Tx (512-1023 bytes) - R/clr
30111
 E1000_PTC1522E1000_PTC1522 0x040EC e1000e_regs.h Packets Tx (1024-1522 Bytes) - R/clr
30112
 E1000_MPTCE1000_MPTC 0x040F0 e1000e_regs.h Multicast Packets Tx Count - R/clr
30113
 E1000_BPTCE1000_BPTC 0x040F4 e1000e_regs.h Broadcast Packets Tx Count - R/clr
30114
 E1000_TSCTCE1000_TSCTC 0x040F8 e1000e_regs.h TCP Segmentation Context Tx - R/clr
30115
 E1000_TSCTFCE1000_TSCTFC 0x040FC e1000e_regs.h TCP Segmentation Context Tx Fail - R/clr
30116
 E1000_IACE1000_IAC 0x04100 e1000e_regs.h Interrupt Assertion Count
30117
 E1000_ICRXPTCE1000_ICRXPTC 0x04104 e1000e_regs.h Interrupt Cause Rx Pkt Timer Expire Count
30118
 E1000_ICRXATCE1000_ICRXATC 0x04108 e1000e_regs.h Interrupt Cause Rx Abs Timer Expire Count
30119
 E1000_ICTXPTCE1000_ICTXPTC 0x0410C e1000e_regs.h Interrupt Cause Tx Pkt Timer Expire Count
30120
 E1000_ICTXATCE1000_ICTXATC 0x04110 e1000e_regs.h Interrupt Cause Tx Abs Timer Expire Count
30121
 E1000_ICTXQECE1000_ICTXQEC 0x04118 e1000e_regs.h Interrupt Cause Tx Queue Empty Count
30122
 E1000_ICTXQMTCE1000_ICTXQMTC 0x0411C e1000e_regs.h Interrupt Cause Tx Queue Min Thresh Count
30123
 E1000_ICRXDMTCE1000_ICRXDMTC 0x04120 e1000e_regs.h Interrupt Cause Rx Desc Min Thresh Count
30124
 E1000_ICRXOCE1000_ICRXOC 0x04124 e1000e_regs.h Interrupt Cause Receiver Overrun Count
30125
 E1000_CRC_OFFSETE1000_CRC_OFFSET 0x05F50 e1000e_regs.h CRC Offset register
30126
 E1000_PCS_CFG0E1000_PCS_CFG0 0x04200 e1000e_regs.h PCS Configuration 0 - RW
30127
 E1000_PCS_LCTLE1000_PCS_LCTL 0x04208 e1000e_regs.h PCS Link Control - RW
30128
 E1000_PCS_LSTATE1000_PCS_LSTAT 0x0420C e1000e_regs.h PCS Link Status - RO
30129
 E1000_CBTMPCE1000_CBTMPC 0x0402C e1000e_regs.h Circuit Breaker Tx Packet Count
30130
 E1000_HTDPMCE1000_HTDPMC 0x0403C e1000e_regs.h Host Transmit Discarded Packets
30131
 E1000_CBRDPCE1000_CBRDPC 0x04044 e1000e_regs.h Circuit Breaker Rx Dropped Count
30132
 E1000_CBRMPCE1000_CBRMPC 0x040FC e1000e_regs.h Circuit Breaker Rx Packet Count
30133
 E1000_RPTHCE1000_RPTHC 0x04104 e1000e_regs.h Rx Packets To Host
30134
 E1000_HGPTCE1000_HGPTC 0x04118 e1000e_regs.h Host Good Packets Tx Count
30135
 E1000_HTCBDPCE1000_HTCBDPC 0x04124 e1000e_regs.h Host Tx Circuit Breaker Dropped Count
30136
 E1000_HGORCLE1000_HGORCL 0x04128 e1000e_regs.h Host Good Octets Received Count Low
30137
 E1000_HGORCHE1000_HGORCH 0x0412C e1000e_regs.h Host Good Octets Received Count High
30138
 E1000_HGOTCLE1000_HGOTCL 0x04130 e1000e_regs.h Host Good Octets Transmit Count Low
30139
 E1000_HGOTCHE1000_HGOTCH 0x04134 e1000e_regs.h Host Good Octets Transmit Count High
30140
 E1000_LENERRSE1000_LENERRS 0x04138 e1000e_regs.h Length Errors Count
30141
 E1000_SCVPCE1000_SCVPC 0x04228 e1000e_regs.h SerDes/SGMII Code Violation Pkt Count
30142
 E1000_HRMPCE1000_HRMPC 0x0A018 e1000e_regs.h Header Redirection Missed Packet Count
30143
 E1000_PCS_ANADVE1000_PCS_ANADV 0x04218 e1000e_regs.h AN advertisement - RW
30144
 E1000_PCS_LPABE1000_PCS_LPAB 0x0421C e1000e_regs.h Link Partner Ability - RW
30145
 E1000_PCS_NPTXE1000_PCS_NPTX 0x04220 e1000e_regs.h AN Next Page Transmit - RW
30146
 E1000_PCS_LPABNPE1000_PCS_LPABNP 0x04224 e1000e_regs.h Link Partner Ability Next Page - RW
30147
 E1000_1GSTAT_RCVE1000_1GSTAT_RCV 0x04228 e1000e_regs.h 1GSTAT Code Violation Packet Count - RW
30148
 E1000_RXCSUME1000_RXCSUM 0x05000 e1000e_regs.h Rx Checksum Control - RW
30149
 E1000_RLPMLE1000_RLPML 0x05004 e1000e_regs.h Rx Long Packet Max Length
30150
 E1000_RFCTLE1000_RFCTL 0x05008 e1000e_regs.h Receive Filter Control
30151
 E1000_MTAE1000_MTA 0x05200 e1000e_regs.h Multicast Table Array - RW Array
30152
 E1000_RAE1000_RA 0x05400 e1000e_regs.h Receive Address - RW Array
30153
 E1000_VFTAE1000_VFTA 0x05600 e1000e_regs.h VLAN Filter Table Array - RW Array
30154
 E1000_VT_CTLE1000_VT_CTL 0x0581C e1000e_regs.h VMDq Control - RW
30155
 E1000_VFQA0E1000_VFQA0 0x0B000 e1000e_regs.h VLAN Filter Queue Array 0 - RW Array
30156
 E1000_VFQA1E1000_VFQA1 0x0B200 e1000e_regs.h VLAN Filter Queue Array 1 - RW Array
30157
 E1000_WUCE1000_WUC 0x05800 e1000e_regs.h Wakeup Control - RW
30158
 E1000_WUFCE1000_WUFC 0x05808 e1000e_regs.h Wakeup Filter Control - RW
30159
 E1000_WUSE1000_WUS 0x05810 e1000e_regs.h Wakeup Status - RO
30160
 E1000_MANCE1000_MANC 0x05820 e1000e_regs.h Management Control - RW
30161
 E1000_IPAVE1000_IPAV 0x05838 e1000e_regs.h IP Address Valid - RW
30162
 E1000_IP4ATE1000_IP4AT 0x05840 e1000e_regs.h IPv4 Address Table - RW Array
30163
 E1000_IP6ATE1000_IP6AT 0x05880 e1000e_regs.h IPv6 Address Table - RW Array
30164
 E1000_WUPLE1000_WUPL 0x05900 e1000e_regs.h Wakeup Packet Length - RW
30165
 E1000_WUPME1000_WUPM 0x05A00 e1000e_regs.h Wakeup Packet Memory - RO A
30166
 E1000_PBACLE1000_PBACL 0x05B68 e1000e_regs.h MSIx PBA Clear - Read/Write 1's to clear
30167
 E1000_FFLTE1000_FFLT 0x05F00 e1000e_regs.h Flexible Filter Length Table - RW Array
30168
 E1000_HOST_IFE1000_HOST_IF 0x08800 e1000e_regs.h Host Interface
30169
 E1000_FFMTE1000_FFMT 0x09000 e1000e_regs.h Flexible Filter Mask Table - RW Array
30170
 E1000_FFVTE1000_FFVT 0x09800 e1000e_regs.h Flexible Filter Value Table - RW Array
30171
 E1000_KMRNCTRLSTAE1000_KMRNCTRLSTA 0x00034 e1000e_regs.h MAC-PHY interface - RW
30172
 E1000_MDPHYAE1000_MDPHYA 0x0003C e1000e_regs.h PHY address - RW
30173
 E1000_MANC2HE1000_MANC2H 0x05860 e1000e_regs.h Management Control To Host - RW
30174
 E1000_SW_FW_SYNCE1000_SW_FW_SYNC 0x05B5C e1000e_regs.h Software-Firmware Synchronization - RW
30175
 E1000_CCMCTLE1000_CCMCTL 0x05B48 e1000e_regs.h CCM Control Register
30176
 E1000_GIOCTLE1000_GIOCTL 0x05B44 e1000e_regs.h GIO Analog Control Register
30177
 E1000_SCCTLE1000_SCCTL 0x05B4C e1000e_regs.h PCIc PLL Configuration Register
30178
 E1000_GCRE1000_GCR 0x05B00 e1000e_regs.h PCI-Ex Control
30179
 E1000_GCR2E1000_GCR2 0x05B64 e1000e_regs.h PCI-Ex Control #2
30180
 E1000_GSCL_1E1000_GSCL_1 0x05B10 e1000e_regs.h PCI-Ex Statistic Control #1
30181
 E1000_GSCL_2E1000_GSCL_2 0x05B14 e1000e_regs.h PCI-Ex Statistic Control #2
30182
 E1000_GSCL_3E1000_GSCL_3 0x05B18 e1000e_regs.h PCI-Ex Statistic Control #3
30183
 E1000_GSCL_4E1000_GSCL_4 0x05B1C e1000e_regs.h PCI-Ex Statistic Control #4
30184
 E1000_FACTPSE1000_FACTPS 0x05B30 e1000e_regs.h Function Active and Power State to MNG
30185
 E1000_SWSME1000_SWSM 0x05B50 e1000e_regs.h SW Semaphore
30186
 E1000_FWSME1000_FWSM 0x05B54 e1000e_regs.h FW Semaphore
30187
 E1000_SWSM2E1000_SWSM2 0x05B58 e1000e_regs.h Driver-only SW semaphore (not used by BOOT agents)
30188
 E1000_DCA_IDE1000_DCA_ID 0x05B70 e1000e_regs.h DCA Requester ID Information - RO
30189
 E1000_DCA_CTRLE1000_DCA_CTRL 0x05B74 e1000e_regs.h DCA Control - RW
30190
 E1000_FFLT_DBGE1000_FFLT_DBG 0x05F04 e1000e_regs.h Debug Register
30191
 E1000_HICRE1000_HICR 0x08F00 e1000e_regs.h Host Interface Control
30192
 E1000_CPUVECE1000_CPUVEC 0x02C10 e1000e_regs.h CPU Vector Register - RW
30193
 E1000_MRQCE1000_MRQC 0x05818 e1000e_regs.h Multiple Receive Control - RW
30194
 E1000_IMIRVPE1000_IMIRVP 0x05AC0 e1000e_regs.h Immediate Interrupt Rx VLAN Priority - RW
30195
 E1000_MSIXPBAE1000_MSIXPBA 0x0E000 e1000e_regs.h MSI-X Pending bit array
30196
 E1000_RSSIME1000_RSSIM 0x05864 e1000e_regs.h RSS Interrupt Mask
30197
 E1000_RSSIRE1000_RSSIR 0x05868 e1000e_regs.h RSS Interrupt Request
30198
 E1000_RXMTRLE1000_RXMTRL 0x0B634 e1000e_regs.h Time sync Rx EtherType and Msg Type - RW
30199
 E1000_RXUDPE1000_RXUDP 0x0B638 e1000e_regs.h Time Sync Rx UDP Port - RW
30200
 M88E1000_CABLE_LENGTH_TABLE_SIZM88E1000_CABLE_LENGTH_TABLE_SIZ (sizeof(e1000_m88_cable_length_table) / \ sizeof(e1000_m88_cable_length_table[0])) igb_phy.c 　
30201
 IGP02E1000_CABLE_LENGTH_TABLE_SIGP02E1000_CABLE_LENGTH_TABLE_S (sizeof(e1000_igp_2_cable_length_table) / \ sizeof(e1000_igp_2_cable_length_table[0])) igb_phy.c 　
30202
 IGB_START_ITRIGB_START_ITR 648 igb.h ~6000 ints/sec
30203
 IGB_INT_MODE_LEGACYIGB_INT_MODE_LEGACY 0 igb.h 　
30204
 IGB_INT_MODE_MSIIGB_INT_MODE_MSI 1 igb.h 　
30205
 IGB_INT_MODE_MSIXIGB_INT_MODE_MSIX 2 igb.h 　
30206
 IGB_DEFAULT_TXDIGB_DEFAULT_TXD 256 igb.h 　
30207
 IGB_MIN_TXDIGB_MIN_TXD 80 igb.h 　
30208
 IGB_MAX_TXDIGB_MAX_TXD 4096 igb.h 　
30209
 IGB_DEFAULT_RXDIGB_DEFAULT_RXD 256 igb.h 　
30210
 IGB_MIN_RXDIGB_MIN_RXD 80 igb.h 　
30211
 IGB_MAX_RXDIGB_MAX_RXD 4096 igb.h 　
30212
 IGB_MIN_ITR_USECSIGB_MIN_ITR_USECS 10 igb.h 100k irq/sec
30213
 IGB_MAX_ITR_USECSIGB_MAX_ITR_USECS 8191 igb.h 120 irq/sec
30214
 NON_Q_VECTORSNON_Q_VECTORS 1 igb.h 　
30215
 MAX_Q_VECTORSMAX_Q_VECTORS 8 igb.h 　
30216
 IGB_MAX_RX_QUEUESIGB_MAX_RX_QUEUES (adapter->vfs_allocated_count ? 2 : \ (hw->mac.type > e1000_82575 ? 8 : 4)) igb.h 　
30217
 IGB_ABS_MAX_TX_QUEUESIGB_ABS_MAX_TX_QUEUES 8 igb.h 　
30218
 IGB_MAX_TX_QUEUESIGB_MAX_TX_QUEUES IGB_MAX_RX_QUEUES igb.h 　
30219
 IGB_MAX_VF_MC_ENTRIESIGB_MAX_VF_MC_ENTRIES 30 igb.h 　
30220
 IGB_MAX_VF_FUNCTIONSIGB_MAX_VF_FUNCTIONS 8 igb.h 　
30221
 IGB_MAX_VFTA_ENTRIESIGB_MAX_VFTA_ENTRIES 128 igb.h 　
30222
 IGB_MAX_UTA_ENTRIESIGB_MAX_UTA_ENTRIES 128 igb.h 　
30223
 MAX_EMULATION_MAC_ADDRSMAX_EMULATION_MAC_ADDRS 16 igb.h 　
30224
 OUI_LENOUI_LEN 3 igb.h 　
30225
 IGB_VF_FLAG_CTSIGB_VF_FLAG_CTS 0x00000001 igb.h VF is clear to send data
30226
 IGB_VF_FLAG_UNI_PROMISCIGB_VF_FLAG_UNI_PROMISC 0x00000002 igb.h VF has unicast promisc
30227
 IGB_VF_FLAG_MULTI_PROMISCIGB_VF_FLAG_MULTI_PROMISC 0x00000004 igb.h VF has multicast promisc
30228
 IGB_RX_PTHRESHIGB_RX_PTHRESH (hw->mac.type <= e1000_82576 ? 16 : 8) igb.h 　
30229
 IGB_RX_HTHRESHIGB_RX_HTHRESH 8 igb.h 　
30230
 IGB_RX_WTHRESHIGB_RX_WTHRESH 1 igb.h 　
30231
 IGB_TX_PTHRESHIGB_TX_PTHRESH 8 igb.h 　
30232
 IGB_TX_HTHRESHIGB_TX_HTHRESH 1 igb.h 　
30233
 IGB_TX_WTHRESHIGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ adapter->msix_entries) ? 0 : 16) igb.h 　
30234
 MAXIMUM_ETHERNET_VLAN_SIZEMAXIMUM_ETHERNET_VLAN_SIZE 1522 igb.h 　
30235
 IGB_RXBUFFER_128IGB_RXBUFFER_128 128 igb.h Used for packet split
30236
 IGB_RXBUFFER_256IGB_RXBUFFER_256 256 igb.h Used for packet split
30237
 IGB_RXBUFFER_512IGB_RXBUFFER_512 512 igb.h 　
30238
 IGB_RXBUFFER_1024IGB_RXBUFFER_1024 1024 igb.h 　
30239
 IGB_RXBUFFER_2048IGB_RXBUFFER_2048 2048 igb.h 　
30240
 IGB_RXBUFFER_4096IGB_RXBUFFER_4096 4096 igb.h 　
30241
 IGB_RXBUFFER_8192IGB_RXBUFFER_8192 8192 igb.h 　
30242
 IGB_RXBUFFER_16384IGB_RXBUFFER_16384 16384 igb.h 　
30243
 IGB_PBA_BYTES_SHIFTIGB_PBA_BYTES_SHIFT 0xA igb.h 　
30244
 IGB_TX_HEAD_ADDR_SHIFTIGB_TX_HEAD_ADDR_SHIFT 7 igb.h 　
30245
 IGB_PBA_TX_MASKIGB_PBA_TX_MASK 0xFFFF0000 igb.h 　
30246
 IGB_FC_PAUSE_TIMEIGB_FC_PAUSE_TIME 0x0680 igb.h 858 usec
30247
 IGB_TX_QUEUE_WAKEIGB_TX_QUEUE_WAKE 32 igb.h 　
30248
 IGB_RX_BUFFER_WRITEIGB_RX_BUFFER_WRITE 16 igb.h Must be power of 2
30249
 AUTO_ALL_MODESAUTO_ALL_MODES 0 igb.h 　
30250
 IGB_EEPROM_APMEIGB_EEPROM_APME 0x0400 igb.h 　
30251
 IGB_MASTER_SLAVEIGB_MASTER_SLAVE e1000_ms_hw_default igb.h 　
30252
 IGB_MNG_VLAN_NONEIGB_MNG_VLAN_NONE -1 igb.h 　
30253
 IGB_ADVTXD_DCMDIGB_ADVTXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) igb.h 　
30254
 MAX_MSIX_COUNTMAX_MSIX_COUNT 10 igb.h 　
30255
 IGB_FLAG_HAS_MSIIGB_FLAG_HAS_MSI (1 << 0) igb.h 　
30256
 IGB_FLAG_MSI_ENABLEIGB_FLAG_MSI_ENABLE (1 << 1) igb.h 　
30257
 IGB_FLAG_DCA_ENABLEDIGB_FLAG_DCA_ENABLED (1 << 3) igb.h 　
30258
 IGB_FLAG_LLI_PUSHIGB_FLAG_LLI_PUSH (1 << 4) igb.h 　
30259
 IGB_FLAG_IN_NETPOLLIGB_FLAG_IN_NETPOLL (1 << 5) igb.h 　
30260
 IGB_FLAG_QUAD_PORT_AIGB_FLAG_QUAD_PORT_A (1 << 6) igb.h 　
30261
 IGB_FLAG_QUEUE_PAIRSIGB_FLAG_QUEUE_PAIRS (1 << 7) igb.h 　
30262
 IGB_82576_TSYNC_SHIFTIGB_82576_TSYNC_SHIFT 19 igb.h 　
30263
 ID_LED_DEFAULT_82575_SERDESID_LED_DEFAULT_82575_SERDES ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_DEF1_DEF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_OFF1_ON2)) igb_82575.h 　
30264
 E1000_RAR_ENTRIES_82575E1000_RAR_ENTRIES_82575 16 igb_82575.h 　
30265
 E1000_RAR_ENTRIES_82576E1000_RAR_ENTRIES_82576 24 igb_82575.h 　
30266
 E1000_TXD_DTYP_ADV_CE1000_TXD_DTYP_ADV_C 0x2 igb_82575.h Advanced Context Descriptor
30267
 E1000_TXD_DTYP_ADV_DE1000_TXD_DTYP_ADV_D 0x3 igb_82575.h Advanced Data Descriptor
30268
 E1000_ADV_TXD_CMD_DEXTE1000_ADV_TXD_CMD_DEXT 0x20 igb_82575.h Descriptor extension (0 = legacy)
30269
 E1000_ADV_TUCMD_IPV4E1000_ADV_TUCMD_IPV4 0x2 igb_82575.h IP Packet Type: 1=IPv4
30270
 E1000_ADV_TUCMD_IPV6E1000_ADV_TUCMD_IPV6 0x0 igb_82575.h IP Packet Type: 0=IPv6
30271
 E1000_ADV_TUCMD_L4T_UDPE1000_ADV_TUCMD_L4T_UDP 0x0 igb_82575.h L4 Packet TYPE of UDP
30272
 E1000_ADV_TUCMD_L4T_TCPE1000_ADV_TUCMD_L4T_TCP 0x4 igb_82575.h L4 Packet TYPE of TCP
30273
 E1000_ADV_TUCMD_MKRREQE1000_ADV_TUCMD_MKRREQ 0x10 igb_82575.h Indicates markers are required
30274
 E1000_ADV_DCMD_EOPE1000_ADV_DCMD_EOP 0x1 igb_82575.h End of Packet
30275
 E1000_ADV_DCMD_IFCSE1000_ADV_DCMD_IFCS 0x2 igb_82575.h Insert FCS (Ethernet CRC)
30276
 E1000_ADV_DCMD_RSE1000_ADV_DCMD_RS 0x8 igb_82575.h Report Status
30277
 E1000_ADV_DCMD_VLEE1000_ADV_DCMD_VLE 0x40 igb_82575.h Add VLAN tag
30278
 E1000_ADV_DCMD_TSEE1000_ADV_DCMD_TSE 0x80 igb_82575.h TCP Seg enable
30279
 E1000_CTRL_EXT_NSICRE1000_CTRL_EXT_NSICR 0x00000001 igb_82575.h Disable Intr Clear all on read
30280
 E1000_SRRCTL_BSIZEPKT_SHIFTE1000_SRRCTL_BSIZEPKT_SHIFT 10 igb_82575.h Shift _right_
30281
 E1000_SRRCTL_BSIZEHDRSIZE_MASKE1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 igb_82575.h 　
30282
 E1000_SRRCTL_BSIZEHDRSIZE_SHIFTE1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 igb_82575.h Shift _left_
30283
 E1000_SRRCTL_DESCTYPE_LEGACYE1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 igb_82575.h 　
30284
 E1000_SRRCTL_DESCTYPE_ADV_ONEBUE1000_SRRCTL_DESCTYPE_ADV_ONEBU 0x02000000 igb_82575.h 　
30285
 E1000_SRRCTL_DESCTYPE_HDR_SPLITE1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 igb_82575.h 　
30286
 E1000_SRRCTL_DESCTYPE_HDR_SPLITE1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x0A000000 igb_82575.h 　
30287
 E1000_SRRCTL_DESCTYPE_HDR_REPLIE1000_SRRCTL_DESCTYPE_HDR_REPLI 0x06000000 igb_82575.h 　
30288
 E1000_SRRCTL_DESCTYPE_HDR_REPLIE1000_SRRCTL_DESCTYPE_HDR_REPLI 0x08000000 igb_82575.h 　
30289
 E1000_SRRCTL_DESCTYPE_MASKE1000_SRRCTL_DESCTYPE_MASK 0x0E000000 igb_82575.h 　
30290
 E1000_SRRCTL_DROP_ENE1000_SRRCTL_DROP_EN 0x80000000 igb_82575.h 　
30291
 E1000_SRRCTL_BSIZEPKT_MASKE1000_SRRCTL_BSIZEPKT_MASK 0x0000007F igb_82575.h 　
30292
 E1000_SRRCTL_BSIZEHDR_MASKE1000_SRRCTL_BSIZEHDR_MASK 0x00003F00 igb_82575.h 　
30293
 E1000_TX_HEAD_WB_ENABLEE1000_TX_HEAD_WB_ENABLE 0x1 igb_82575.h 　
30294
 E1000_TX_SEQNUM_WB_ENABLEE1000_TX_SEQNUM_WB_ENABLE 0x2 igb_82575.h 　
30295
 E1000_MRQC_ENABLE_RSS_4QE1000_MRQC_ENABLE_RSS_4Q 0x00000002 igb_82575.h 　
30296
 E1000_MRQC_ENABLE_VMDQE1000_MRQC_ENABLE_VMDQ 0x00000003 igb_82575.h 　
30297
 E1000_MRQC_ENABLE_VMDQ_RSS_2QE1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 igb_82575.h 　
30298
 E1000_MRQC_RSS_FIELD_IPV4_UDPE1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 igb_82575.h 　
30299
 E1000_MRQC_RSS_FIELD_IPV6_UDPE1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 igb_82575.h 　
30300
 E1000_MRQC_RSS_FIELD_IPV6_UDP_EE1000_MRQC_RSS_FIELD_IPV6_UDP_E 0x01000000 igb_82575.h 　
30301
 E1000_VMRCTL_MIRROR_PORT_SHIFTE1000_VMRCTL_MIRROR_PORT_SHIFT 8 igb_82575.h 　
30302
 E1000_VMRCTL_MIRROR_DSTPORT_MASE1000_VMRCTL_MIRROR_DSTPORT_MAS (7 << E1000_VMRCTL_MIRROR_PORT_SHIFT) igb_82575.h 　
30303
 E1000_VMRCTL_POOL_MIRROR_ENABLEE1000_VMRCTL_POOL_MIRROR_ENABLE (1 << 0) igb_82575.h 　
30304
 E1000_VMRCTL_UPLINK_MIRROR_ENABE1000_VMRCTL_UPLINK_MIRROR_ENAB (1 << 1) igb_82575.h 　
30305
 E1000_VMRCTL_DOWNLINK_MIRROR_ENE1000_VMRCTL_DOWNLINK_MIRROR_EN (1 << 2) igb_82575.h 　
30306
 E1000_EICR_TX_QUEUEE1000_EICR_TX_QUEUE ( \ E1000_EICR_TX_QUEUE0 | \ E1000_EICR_TX_QUEUE1 | \ E1000_EICR_TX_QUEUE2 | \ E1000_EICR_TX_QUEUE3) igb_82575.h 　
30307
 E1000_EICR_RX_QUEUEE1000_EICR_RX_QUEUE ( \ E1000_EICR_RX_QUEUE0 | \ E1000_EICR_RX_QUEUE1 | \ E1000_EICR_RX_QUEUE2 | \ E1000_EICR_RX_QUEUE3) igb_82575.h 　
30308
 E1000_EIMS_RX_QUEUEE1000_EIMS_RX_QUEUE E1000_EICR_RX_QUEUE igb_82575.h 　
30309
 E1000_EIMS_TX_QUEUEE1000_EIMS_TX_QUEUE E1000_EICR_TX_QUEUE igb_82575.h 　
30310
 EIMS_ENABLE_MASKEIMS_ENABLE_MASK ( \ E1000_EIMS_RX_QUEUE | \ E1000_EIMS_TX_QUEUE | \ E1000_EIMS_TCP_TIMER | \ E1000_EIMS_OTHER) igb_82575.h 　
30311
 E1000_IMIR_PORT_IM_ENE1000_IMIR_PORT_IM_EN 0x00010000 igb_82575.h TCP port enable
30312
 E1000_IMIR_PORT_BPE1000_IMIR_PORT_BP 0x00020000 igb_82575.h TCP port check bypass
30313
 E1000_IMIREXT_SIZE_BPE1000_IMIREXT_SIZE_BP 0x00001000 igb_82575.h Packet size bypass
30314
 E1000_IMIREXT_CTRL_URGE1000_IMIREXT_CTRL_URG 0x00002000 igb_82575.h Check URG bit in header
30315
 E1000_IMIREXT_CTRL_ACKE1000_IMIREXT_CTRL_ACK 0x00004000 igb_82575.h Check ACK bit in header
30316
 E1000_IMIREXT_CTRL_PSHE1000_IMIREXT_CTRL_PSH 0x00008000 igb_82575.h Check PSH bit in header
30317
 E1000_IMIREXT_CTRL_RSTE1000_IMIREXT_CTRL_RST 0x00010000 igb_82575.h Check RST bit in header
30318
 E1000_IMIREXT_CTRL_SYNE1000_IMIREXT_CTRL_SYN 0x00020000 igb_82575.h Check SYN bit in header
30319
 E1000_IMIREXT_CTRL_FINE1000_IMIREXT_CTRL_FIN 0x00040000 igb_82575.h Check FIN bit in header
30320
 E1000_IMIREXT_CTRL_BPE1000_IMIREXT_CTRL_BP 0x00080000 igb_82575.h Bypass check of ctrl bits
30321
 E1000_RXDADV_RSSTYPE_MASKE1000_RXDADV_RSSTYPE_MASK 0x0000000F igb_82575.h 　
30322
 E1000_RXDADV_RSSTYPE_SHIFTE1000_RXDADV_RSSTYPE_SHIFT 12 igb_82575.h 　
30323
 E1000_RXDADV_HDRBUFLEN_MASKE1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 igb_82575.h 　
30324
 E1000_RXDADV_HDRBUFLEN_SHIFTE1000_RXDADV_HDRBUFLEN_SHIFT 5 igb_82575.h 　
30325
 E1000_RXDADV_SPLITHEADER_ENE1000_RXDADV_SPLITHEADER_EN 0x00001000 igb_82575.h 　
30326
 E1000_RXDADV_SPHE1000_RXDADV_SPH 0x8000 igb_82575.h 　
30327
 E1000_RXDADV_STAT_TSE1000_RXDADV_STAT_TS 0x10000 igb_82575.h Pkt was time stamped
30328
 E1000_RXDADV_ERR_HBOE1000_RXDADV_ERR_HBO 0x00800000 igb_82575.h 　
30329
 E1000_RXDADV_RSSTYPE_NONEE1000_RXDADV_RSSTYPE_NONE 0x00000000 igb_82575.h 　
30330
 E1000_RXDADV_RSSTYPE_IPV4_TCPE1000_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 igb_82575.h 　
30331
 E1000_RXDADV_RSSTYPE_IPV4E1000_RXDADV_RSSTYPE_IPV4 0x00000002 igb_82575.h 　
30332
 E1000_RXDADV_RSSTYPE_IPV6_TCPE1000_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 igb_82575.h 　
30333
 E1000_RXDADV_RSSTYPE_IPV6_EXE1000_RXDADV_RSSTYPE_IPV6_EX 0x00000004 igb_82575.h 　
30334
 E1000_RXDADV_RSSTYPE_IPV6E1000_RXDADV_RSSTYPE_IPV6 0x00000005 igb_82575.h 　
30335
 E1000_RXDADV_RSSTYPE_IPV6_TCP_EE1000_RXDADV_RSSTYPE_IPV6_TCP_E 0x00000006 igb_82575.h 　
30336
 E1000_RXDADV_RSSTYPE_IPV4_UDPE1000_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 igb_82575.h 　
30337
 E1000_RXDADV_RSSTYPE_IPV6_UDPE1000_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 igb_82575.h 　
30338
 E1000_RXDADV_RSSTYPE_IPV6_UDP_EE1000_RXDADV_RSSTYPE_IPV6_UDP_E 0x00000009 igb_82575.h 　
30339
 E1000_RXDADV_PKTTYPE_NONEE1000_RXDADV_PKTTYPE_NONE 0x00000000 igb_82575.h 　
30340
 E1000_RXDADV_PKTTYPE_IPV4E1000_RXDADV_PKTTYPE_IPV4 0x00000010 igb_82575.h IPV4 hdr present
30341
 E1000_RXDADV_PKTTYPE_IPV4_EXE1000_RXDADV_PKTTYPE_IPV4_EX 0x00000020 igb_82575.h IPV4 hdr + extensions
30342
 E1000_RXDADV_PKTTYPE_IPV6E1000_RXDADV_PKTTYPE_IPV6 0x00000040 igb_82575.h IPV6 hdr present
30343
 E1000_RXDADV_PKTTYPE_IPV6_EXE1000_RXDADV_PKTTYPE_IPV6_EX 0x00000080 igb_82575.h IPV6 hdr + extensions
30344
 E1000_RXDADV_PKTTYPE_TCPE1000_RXDADV_PKTTYPE_TCP 0x00000100 igb_82575.h TCP hdr present
30345
 E1000_RXDADV_PKTTYPE_UDPE1000_RXDADV_PKTTYPE_UDP 0x00000200 igb_82575.h UDP hdr present
30346
 E1000_RXDADV_PKTTYPE_SCTPE1000_RXDADV_PKTTYPE_SCTP 0x00000400 igb_82575.h SCTP hdr present
30347
 E1000_RXDADV_PKTTYPE_NFSE1000_RXDADV_PKTTYPE_NFS 0x00000800 igb_82575.h NFS hdr present
30348
 E1000_RXDADV_PKTTYPE_IPSEC_ESPE1000_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 igb_82575.h IPSec ESP
30349
 E1000_RXDADV_PKTTYPE_IPSEC_AHE1000_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 igb_82575.h IPSec AH
30350
 E1000_RXDADV_PKTTYPE_LINKSECE1000_RXDADV_PKTTYPE_LINKSEC 0x00004000 igb_82575.h LinkSec Encap
30351
 E1000_RXDADV_PKTTYPE_ETQFE1000_RXDADV_PKTTYPE_ETQF 0x00008000 igb_82575.h PKTTYPE is ETQF index
30352
 E1000_RXDADV_PKTTYPE_ETQF_MASKE1000_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 igb_82575.h ETQF has 8 indices
30353
 E1000_RXDADV_PKTTYPE_ETQF_SHIFTE1000_RXDADV_PKTTYPE_ETQF_SHIFT 4 igb_82575.h Right-shift 4 bits
30354
 E1000_RXDADV_LNKSEC_STATUS_SECPE1000_RXDADV_LNKSEC_STATUS_SECP 0x00020000 igb_82575.h 　
30355
 E1000_RXDADV_LNKSEC_ERROR_BIT_ME1000_RXDADV_LNKSEC_ERROR_BIT_M 0x18000000 igb_82575.h 　
30356
 E1000_RXDADV_LNKSEC_ERROR_NO_SAE1000_RXDADV_LNKSEC_ERROR_NO_SA 0x08000000 igb_82575.h 　
30357
 E1000_RXDADV_LNKSEC_ERROR_REPLAE1000_RXDADV_LNKSEC_ERROR_REPLA 0x10000000 igb_82575.h 　
30358
 E1000_RXDADV_LNKSEC_ERROR_BAD_SE1000_RXDADV_LNKSEC_ERROR_BAD_S 0x18000000 igb_82575.h 　
30359
 E1000_RXDADV_IPSEC_STATUS_SECPE1000_RXDADV_IPSEC_STATUS_SECP 0x00020000 igb_82575.h 　
30360
 E1000_RXDADV_IPSEC_ERROR_BIT_MAE1000_RXDADV_IPSEC_ERROR_BIT_MA 0x18000000 igb_82575.h 　
30361
 E1000_RXDADV_IPSEC_ERROR_INVALIE1000_RXDADV_IPSEC_ERROR_INVALI 0x08000000 igb_82575.h 　
30362
 E1000_RXDADV_IPSEC_ERROR_INVALIE1000_RXDADV_IPSEC_ERROR_INVALI 0x10000000 igb_82575.h 　
30363
 E1000_RXDADV_IPSEC_ERROR_AUTHENE1000_RXDADV_IPSEC_ERROR_AUTHEN 0x18000000 igb_82575.h 　
30364
 E1000_ADVTXD_DTYP_CTXTE1000_ADVTXD_DTYP_CTXT 0x00200000 igb_82575.h Advanced Context Descriptor
30365
 E1000_ADVTXD_DTYP_DATAE1000_ADVTXD_DTYP_DATA 0x00300000 igb_82575.h Advanced Data Descriptor
30366
 E1000_ADVTXD_DCMD_EOPE1000_ADVTXD_DCMD_EOP 0x01000000 igb_82575.h End of Packet
30367
 E1000_ADVTXD_DCMD_IFCSE1000_ADVTXD_DCMD_IFCS 0x02000000 igb_82575.h Insert FCS (Ethernet CRC)
30368
 E1000_ADVTXD_DCMD_RSE1000_ADVTXD_DCMD_RS 0x08000000 igb_82575.h Report Status
30369
 E1000_ADVTXD_DCMD_DDTYP_ISCSIE1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 igb_82575.h DDP hdr type or iSCSI
30370
 E1000_ADVTXD_DCMD_DEXTE1000_ADVTXD_DCMD_DEXT 0x20000000 igb_82575.h Descriptor extension (1=Adv)
30371
 E1000_ADVTXD_DCMD_VLEE1000_ADVTXD_DCMD_VLE 0x40000000 igb_82575.h VLAN pkt enable
30372
 E1000_ADVTXD_DCMD_TSEE1000_ADVTXD_DCMD_TSE 0x80000000 igb_82575.h TCP Seg enable
30373
 E1000_ADVTXD_MAC_LINKSECE1000_ADVTXD_MAC_LINKSEC 0x00040000 igb_82575.h Apply LinkSec on packet
30374
 E1000_ADVTXD_MAC_TSTAMPE1000_ADVTXD_MAC_TSTAMP 0x00080000 igb_82575.h IEEE1588 Timestamp packet
30375
 E1000_ADVTXD_STAT_SN_CRCE1000_ADVTXD_STAT_SN_CRC 0x00000002 igb_82575.h NXTSEQ/SEED present in WB
30376
 E1000_ADVTXD_IDX_SHIFTE1000_ADVTXD_IDX_SHIFT 4 igb_82575.h Adv desc Index shift
30377
 E1000_ADVTXD_POPTS_ISCO_1STE1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 igb_82575.h 1st TSO of iSCSI PDU
30378
 E1000_ADVTXD_POPTS_ISCO_MDLE1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 igb_82575.h Middle TSO of iSCSI PDU
30379
 E1000_ADVTXD_POPTS_ISCO_LASTE1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 igb_82575.h Last TSO of iSCSI PDU
30380
 E1000_ADVTXD_POPTS_ISCO_FULLE1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 igb_82575.h 1st&Last TSO-full iSCSI PDU
30381
 E1000_ADVTXD_POPTS_IPSECE1000_ADVTXD_POPTS_IPSEC 0x00000400 igb_82575.h IPSec offload request
30382
 E1000_ADVTXD_PAYLEN_SHIFTE1000_ADVTXD_PAYLEN_SHIFT 14 igb_82575.h Adv desc PAYLEN shift
30383
 E1000_ADVTXD_MACLEN_SHIFTE1000_ADVTXD_MACLEN_SHIFT 9 igb_82575.h Adv ctxt desc mac len shift
30384
 E1000_ADVTXD_VLAN_SHIFTE1000_ADVTXD_VLAN_SHIFT 16 igb_82575.h Adv ctxt vlan tag shift
30385
 E1000_ADVTXD_TUCMD_IPV4E1000_ADVTXD_TUCMD_IPV4 0x00000400 igb_82575.h IP Packet Type: 1=IPv4
30386
 E1000_ADVTXD_TUCMD_IPV6E1000_ADVTXD_TUCMD_IPV6 0x00000000 igb_82575.h IP Packet Type: 0=IPv6
30387
 E1000_ADVTXD_TUCMD_L4T_UDPE1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 igb_82575.h L4 Packet TYPE of UDP
30388
 E1000_ADVTXD_TUCMD_L4T_TCPE1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 igb_82575.h L4 Packet TYPE of TCP
30389
 E1000_ADVTXD_TUCMD_L4T_SCTPE1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 igb_82575.h L4 Packet TYPE of SCTP
30390
 E1000_ADVTXD_TUCMD_IPSEC_TYPE_EE1000_ADVTXD_TUCMD_IPSEC_TYPE_E 0x00002000 igb_82575.h IPSec Type ESP
30391
 E1000_ADVTXD_TUCMD_IPSEC_ENCRYPE1000_ADVTXD_TUCMD_IPSEC_ENCRYP 0x00004000 igb_82575.h 　
30392
 E1000_ADVTXD_TUCMD_MKRREQE1000_ADVTXD_TUCMD_MKRREQ 0x00002000 igb_82575.h Req requires Markers and CRC
30393
 E1000_ADVTXD_L4LEN_SHIFTE1000_ADVTXD_L4LEN_SHIFT 8 igb_82575.h Adv ctxt L4LEN shift
30394
 E1000_ADVTXD_MSS_SHIFTE1000_ADVTXD_MSS_SHIFT 16 igb_82575.h Adv ctxt MSS shift
30395
 E1000_ADVTXD_IPSEC_SA_INDEX_MASE1000_ADVTXD_IPSEC_SA_INDEX_MAS 0x000000FF igb_82575.h 　
30396
 E1000_ADVTXD_IPSEC_ESP_LEN_MASKE1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF igb_82575.h 　
30397
 E1000_TXDCTL_QUEUE_ENABLEE1000_TXDCTL_QUEUE_ENABLE 0x02000000 igb_82575.h Enable specific Tx Queue
30398
 E1000_TXDCTL_SWFLSHE1000_TXDCTL_SWFLSH 0x04000000 igb_82575.h Tx Desc. write-back flushing
30399
 E1000_TXDCTL_PRIORITYE1000_TXDCTL_PRIORITY 0x08000000 igb_82575.h 　
30400
 E1000_RXDCTL_QUEUE_ENABLEE1000_RXDCTL_QUEUE_ENABLE 0x02000000 igb_82575.h Enable specific Rx Queue
30401
 E1000_RXDCTL_SWFLSHE1000_RXDCTL_SWFLSH 0x04000000 igb_82575.h Rx Desc. write-back flushing
30402
 E1000_DCA_CTRL_DCA_ENABLEE1000_DCA_CTRL_DCA_ENABLE 0x00000000 igb_82575.h DCA Enable
30403
 E1000_DCA_CTRL_DCA_DISABLEE1000_DCA_CTRL_DCA_DISABLE 0x00000001 igb_82575.h DCA Disable
30404
 E1000_DCA_CTRL_DCA_MODE_CB1E1000_DCA_CTRL_DCA_MODE_CB1 0x00 igb_82575.h DCA Mode CB1
30405
 E1000_DCA_CTRL_DCA_MODE_CB2E1000_DCA_CTRL_DCA_MODE_CB2 0x02 igb_82575.h DCA Mode CB2
30406
 E1000_DCA_RXCTRL_CPUID_MASKE1000_DCA_RXCTRL_CPUID_MASK 0x0000001F igb_82575.h Rx CPUID Mask
30407
 E1000_DCA_RXCTRL_DESC_DCA_ENE1000_DCA_RXCTRL_DESC_DCA_EN (1 << 5) igb_82575.h DCA Rx Desc enable
30408
 E1000_DCA_RXCTRL_HEAD_DCA_ENE1000_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) igb_82575.h DCA Rx Desc header enable
30409
 E1000_DCA_RXCTRL_DATA_DCA_ENE1000_DCA_RXCTRL_DATA_DCA_EN (1 << 7) igb_82575.h DCA Rx Desc payload enable
30410
 E1000_DCA_TXCTRL_CPUID_MASKE1000_DCA_TXCTRL_CPUID_MASK 0x0000001F igb_82575.h Tx CPUID Mask
30411
 E1000_DCA_TXCTRL_DESC_DCA_ENE1000_DCA_TXCTRL_DESC_DCA_EN (1 << 5) igb_82575.h DCA Tx Desc enable
30412
 E1000_DCA_TXCTRL_TX_WB_RO_ENE1000_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) igb_82575.h Tx Desc writeback RO bit
30413
 E1000_DCA_TXCTRL_CPUID_MASK_825E1000_DCA_TXCTRL_CPUID_MASK_825 0xFF000000 igb_82575.h Tx CPUID Mask
30414
 E1000_DCA_RXCTRL_CPUID_MASK_825E1000_DCA_RXCTRL_CPUID_MASK_825 0xFF000000 igb_82575.h Rx CPUID Mask
30415
 E1000_DCA_TXCTRL_CPUID_SHIFT_82E1000_DCA_TXCTRL_CPUID_SHIFT_82 24 igb_82575.h Tx CPUID
30416
 E1000_DCA_RXCTRL_CPUID_SHIFT_82E1000_DCA_RXCTRL_CPUID_SHIFT_82 24 igb_82575.h Rx CPUID
30417
 E1000_ICR_LSECPNSE1000_ICR_LSECPNS 0x00000020 igb_82575.h PN threshold - server
30418
 E1000_IMS_LSECPNSE1000_IMS_LSECPNS E1000_ICR_LSECPNS igb_82575.h PN threshold - server
30419
 E1000_ICS_LSECPNSE1000_ICS_LSECPNS E1000_ICR_LSECPNS igb_82575.h PN threshold - server
30420
 E1000_ETQF_FILTER_ENABLEE1000_ETQF_FILTER_ENABLE (1 << 26) igb_82575.h 　
30421
 E1000_ETQF_IMM_INTE1000_ETQF_IMM_INT (1 << 29) igb_82575.h 　
30422
 E1000_ETQF_1588E1000_ETQF_1588 (1 << 30) igb_82575.h 　
30423
 E1000_ETQF_QUEUE_ENABLEE1000_ETQF_QUEUE_ENABLE (1 << 31) igb_82575.h 　
30424
 E1000_ETQF_FILTER_EAPOLE1000_ETQF_FILTER_EAPOL 0 igb_82575.h 　
30425
 E1000_FTQF_VF_BPE1000_FTQF_VF_BP 0x00008000 igb_82575.h 　
30426
 E1000_FTQF_1588_TIME_STAMPE1000_FTQF_1588_TIME_STAMP 0x08000000 igb_82575.h 　
30427
 E1000_FTQF_MASKE1000_FTQF_MASK 0xF0000000 igb_82575.h 　
30428
 E1000_FTQF_MASK_PROTO_BPE1000_FTQF_MASK_PROTO_BP 0x10000000 igb_82575.h 　
30429
 E1000_FTQF_MASK_SOURCE_ADDR_BPE1000_FTQF_MASK_SOURCE_ADDR_BP 0x20000000 igb_82575.h 　
30430
 E1000_FTQF_MASK_DEST_ADDR_BPE1000_FTQF_MASK_DEST_ADDR_BP 0x40000000 igb_82575.h 　
30431
 E1000_FTQF_MASK_SOURCE_PORT_BPE1000_FTQF_MASK_SOURCE_PORT_BP 0x80000000 igb_82575.h 　
30432
 E1000_NVM_APME_82575E1000_NVM_APME_82575 0x0400 igb_82575.h 　
30433
 MAX_NUM_VFSMAX_NUM_VFS 8 igb_82575.h 　
30434
 E1000_DTXSWC_MAC_SPOOF_MASKE1000_DTXSWC_MAC_SPOOF_MASK 0x000000FF igb_82575.h Per VF MAC spoof control
30435
 E1000_DTXSWC_VLAN_SPOOF_MASKE1000_DTXSWC_VLAN_SPOOF_MASK 0x0000FF00 igb_82575.h Per VF VLAN spoof control
30436
 E1000_DTXSWC_LLE_MASKE1000_DTXSWC_LLE_MASK 0x00FF0000 igb_82575.h Per VF Local LB enables
30437
 E1000_DTXSWC_VLAN_SPOOF_SHIFTE1000_DTXSWC_VLAN_SPOOF_SHIFT 8 igb_82575.h 　
30438
 E1000_DTXSWC_LLE_SHIFTE1000_DTXSWC_LLE_SHIFT 16 igb_82575.h 　
30439
 E1000_DTXSWC_VMDQ_LOOPBACK_ENE1000_DTXSWC_VMDQ_LOOPBACK_EN (1 << 31) igb_82575.h global VF LB enable
30440
 E1000_VT_CTL_DEFAULT_POOL_SHIFTE1000_VT_CTL_DEFAULT_POOL_SHIFT 7 igb_82575.h 　
30441
 E1000_VT_CTL_DEFAULT_POOL_MASKE1000_VT_CTL_DEFAULT_POOL_MASK (0x7 << E1000_VT_CTL_DEFAULT_POOL_SHIFT) igb_82575.h 　
30442
 E1000_VT_CTL_IGNORE_MACE1000_VT_CTL_IGNORE_MAC (1 << 28) igb_82575.h 　
30443
 E1000_VT_CTL_DISABLE_DEF_POOLE1000_VT_CTL_DISABLE_DEF_POOL (1 << 29) igb_82575.h 　
30444
 E1000_VT_CTL_VM_REPL_ENE1000_VT_CTL_VM_REPL_EN (1 << 30) igb_82575.h 　
30445
 E1000_VMOLR_RLPML_MASKE1000_VMOLR_RLPML_MASK 0x00003FFF igb_82575.h Long Packet Maximum Length mask
30446
 E1000_VMOLR_LPEE1000_VMOLR_LPE 0x00010000 igb_82575.h Accept Long packet
30447
 E1000_VMOLR_RSSEE1000_VMOLR_RSSE 0x00020000 igb_82575.h Enable RSS
30448
 E1000_VMOLR_AUPEE1000_VMOLR_AUPE 0x01000000 igb_82575.h Accept untagged packets
30449
 E1000_VMOLR_ROMPEE1000_VMOLR_ROMPE 0x02000000 igb_82575.h Accept overflow multicast
30450
 E1000_VMOLR_ROPEE1000_VMOLR_ROPE 0x04000000 igb_82575.h Accept overflow unicast
30451
 E1000_VMOLR_BAME1000_VMOLR_BAM 0x08000000 igb_82575.h Accept Broadcast packets
30452
 E1000_VMOLR_MPMEE1000_VMOLR_MPME 0x10000000 igb_82575.h Multicast promiscuous mode
30453
 E1000_VMOLR_STRVLANE1000_VMOLR_STRVLAN 0x40000000 igb_82575.h Vlan stripping enable
30454
 E1000_VMOLR_STRCRCE1000_VMOLR_STRCRC 0x80000000 igb_82575.h CRC stripping enable
30455
 E1000_VLVF_ARRAY_SIZEE1000_VLVF_ARRAY_SIZE 32 igb_82575.h 　
30456
 E1000_VLVF_VLANID_MASKE1000_VLVF_VLANID_MASK 0x00000FFF igb_82575.h 　
30457
 E1000_VLVF_POOLSEL_SHIFTE1000_VLVF_POOLSEL_SHIFT 12 igb_82575.h 　
30458
 E1000_VLVF_POOLSEL_MASKE1000_VLVF_POOLSEL_MASK (0xFF << E1000_VLVF_POOLSEL_SHIFT) igb_82575.h 　
30459
 E1000_VLVF_LVLANE1000_VLVF_LVLAN 0x00100000 igb_82575.h 　
30460
 E1000_VLVF_VLANID_ENABLEE1000_VLVF_VLANID_ENABLE 0x80000000 igb_82575.h 　
30461
 E1000_VF_INIT_TIMEOUTE1000_VF_INIT_TIMEOUT 200 igb_82575.h Number of retries to clear RSTI
30462
 E1000_IOVCTLE1000_IOVCTL 0x05BBC igb_82575.h 　
30463
 E1000_IOVCTL_REUSE_VFQE1000_IOVCTL_REUSE_VFQ 0x00000001 igb_82575.h 　
30464
 E1000_RPLOLR_STRVLANE1000_RPLOLR_STRVLAN 0x40000000 igb_82575.h 　
30465
 E1000_RPLOLR_STRCRCE1000_RPLOLR_STRCRC 0x80000000 igb_82575.h 　
30466
 E1000_DTXCTL_8023LLE1000_DTXCTL_8023LL 0x0004 igb_82575.h 　
30467
 E1000_DTXCTL_VLAN_ADDEDE1000_DTXCTL_VLAN_ADDED 0x0008 igb_82575.h 　
30468
 E1000_DTXCTL_OOS_ENABLEE1000_DTXCTL_OOS_ENABLE 0x0010 igb_82575.h 　
30469
 E1000_DTXCTL_MDP_ENE1000_DTXCTL_MDP_EN 0x0020 igb_82575.h 　
30470
 E1000_DTXCTL_SPOOF_INTE1000_DTXCTL_SPOOF_INT 0x0040 igb_82575.h 　
30471
 ALL_QUEUESALL_QUEUES 0xFFFF igb_82575.h 　
30472
 E1000_RXPBS_SIZE_MASK_82576E1000_RXPBS_SIZE_MASK_82576 0x0000007F igb_82575.h 　
30473
 CARRIER_EXTENSIONCARRIER_EXTENSION 0x0F igb_api.h 　
30474
 REQ_TX_DESCRIPTOR_MULTIPLEREQ_TX_DESCRIPTOR_MULTIPLE 8 igb_defines.h 　
30475
 REQ_RX_DESCRIPTOR_MULTIPLEREQ_RX_DESCRIPTOR_MULTIPLE 8 igb_defines.h 　
30476
 E1000_WUC_APMEE1000_WUC_APME 0x00000001 igb_defines.h APM Enable
30477
 E1000_WUC_PME_ENE1000_WUC_PME_EN 0x00000002 igb_defines.h PME Enable
30478
 E1000_WUC_PME_STATUSE1000_WUC_PME_STATUS 0x00000004 igb_defines.h PME Status
30479
 E1000_WUC_APMPMEE1000_WUC_APMPME 0x00000008 igb_defines.h Assert PME on APM Wakeup
30480
 E1000_WUC_LSCWEE1000_WUC_LSCWE 0x00000010 igb_defines.h Link Status wake up enable
30481
 E1000_WUC_LSCWOE1000_WUC_LSCWO 0x00000020 igb_defines.h Link Status wake up override
30482
 E1000_WUC_SPME1000_WUC_SPM 0x80000000 igb_defines.h Enable SPM
30483
 E1000_WUC_PHY_WAKEE1000_WUC_PHY_WAKE 0x00000100 igb_defines.h if PHY supports wakeup
30484
 E1000_WUFC_LNKCE1000_WUFC_LNKC 0x00000001 igb_defines.h Link Status Change Wakeup Enable
30485
 E1000_WUFC_MAGE1000_WUFC_MAG 0x00000002 igb_defines.h Magic Packet Wakeup Enable
30486
 E1000_WUFC_EXE1000_WUFC_EX 0x00000004 igb_defines.h Directed Exact Wakeup Enable
30487
 E1000_WUFC_MCE1000_WUFC_MC 0x00000008 igb_defines.h Directed Multicast Wakeup Enable
30488
 E1000_WUFC_BCE1000_WUFC_BC 0x00000010 igb_defines.h Broadcast Wakeup Enable
30489
 E1000_WUFC_ARPE1000_WUFC_ARP 0x00000020 igb_defines.h ARP Request Packet Wakeup Enable
30490
 E1000_WUFC_IPV4E1000_WUFC_IPV4 0x00000040 igb_defines.h Directed IPv4 Packet Wakeup Enable
30491
 E1000_WUFC_IPV6E1000_WUFC_IPV6 0x00000080 igb_defines.h Directed IPv6 Packet Wakeup Enable
30492
 E1000_WUFC_IGNORE_TCOE1000_WUFC_IGNORE_TCO 0x00008000 igb_defines.h Ignore WakeOn TCO packets
30493
 E1000_WUFC_FLX0E1000_WUFC_FLX0 0x00010000 igb_defines.h Flexible Filter 0 Enable
30494
 E1000_WUFC_FLX1E1000_WUFC_FLX1 0x00020000 igb_defines.h Flexible Filter 1 Enable
30495
 E1000_WUFC_FLX2E1000_WUFC_FLX2 0x00040000 igb_defines.h Flexible Filter 2 Enable
30496
 E1000_WUFC_FLX3E1000_WUFC_FLX3 0x00080000 igb_defines.h Flexible Filter 3 Enable
30497
 E1000_WUFC_FLX4E1000_WUFC_FLX4 0x00100000 igb_defines.h Flexible Filter 4 Enable
30498
 E1000_WUFC_FLX5E1000_WUFC_FLX5 0x00200000 igb_defines.h Flexible Filter 5 Enable
30499
 E1000_WUFC_ALL_FILTERSE1000_WUFC_ALL_FILTERS 0x000F00FF igb_defines.h Mask for all wakeup filters
30500
 E1000_WUFC_FLX_OFFSETE1000_WUFC_FLX_OFFSET 16 igb_defines.h Offset to the Flexible Filters bits
30501
 E1000_WUFC_FLX_FILTERSE1000_WUFC_FLX_FILTERS 0x000F0000 igb_defines.h Mask for the 4 flexible filters
30502
 E1000_WUFC_EXT_FLX_FILTERSE1000_WUFC_EXT_FLX_FILTERS 0x00300000 igb_defines.h Ext. FLX filter mask
30503
 E1000_WUS_LNKCE1000_WUS_LNKC E1000_WUFC_LNKC igb_defines.h 　
30504
 E1000_WUS_MAGE1000_WUS_MAG E1000_WUFC_MAG igb_defines.h 　
30505
 E1000_WUS_EXE1000_WUS_EX E1000_WUFC_EX igb_defines.h 　
30506
 E1000_WUS_MCE1000_WUS_MC E1000_WUFC_MC igb_defines.h 　
30507
 E1000_WUS_BCE1000_WUS_BC E1000_WUFC_BC igb_defines.h 　
30508
 E1000_WUS_ARPE1000_WUS_ARP E1000_WUFC_ARP igb_defines.h 　
30509
 E1000_WUS_IPV4E1000_WUS_IPV4 E1000_WUFC_IPV4 igb_defines.h 　
30510
 E1000_WUS_IPV6E1000_WUS_IPV6 E1000_WUFC_IPV6 igb_defines.h 　
30511
 E1000_WUS_FLX0E1000_WUS_FLX0 E1000_WUFC_FLX0 igb_defines.h 　
30512
 E1000_WUS_FLX1E1000_WUS_FLX1 E1000_WUFC_FLX1 igb_defines.h 　
30513
 E1000_WUS_FLX2E1000_WUS_FLX2 E1000_WUFC_FLX2 igb_defines.h 　
30514
 E1000_WUS_FLX3E1000_WUS_FLX3 E1000_WUFC_FLX3 igb_defines.h 　
30515
 E1000_WUS_FLX_FILTERSE1000_WUS_FLX_FILTERS E1000_WUFC_FLX_FILTERS igb_defines.h 　
30516
 E1000_WUPL_LENGTH_MASKE1000_WUPL_LENGTH_MASK 0x0FFF igb_defines.h Only the lower 12 bits are valid
30517
 E1000_FLEXIBLE_FILTER_COUNT_MAXE1000_FLEXIBLE_FILTER_COUNT_MAX 4 igb_defines.h 　
30518
 E1000_EXT_FLEXIBLE_FILTER_COUNTE1000_EXT_FLEXIBLE_FILTER_COUNT 2 igb_defines.h 　
30519
 E1000_FHFT_LENGTH_OFFSETE1000_FHFT_LENGTH_OFFSET 0xFC igb_defines.h Length byte in FHFT
30520
 E1000_FHFT_LENGTH_MASKE1000_FHFT_LENGTH_MASK 0x0FF igb_defines.h Length in lower byte
30521
 E1000_FLEXIBLE_FILTER_SIZE_MAXE1000_FLEXIBLE_FILTER_SIZE_MAX 128 igb_defines.h 　
30522
 E1000_FFLT_SIZEE1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX igb_defines.h 　
30523
 E1000_FFMT_SIZEE1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX igb_defines.h 　
30524
 E1000_FFVT_SIZEE1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX igb_defines.h 　
30525
 E1000_CTRL_EXT_GPI0_ENE1000_CTRL_EXT_GPI0_EN 0x00000001 igb_defines.h Maps SDP4 to GPI0
30526
 E1000_CTRL_EXT_GPI1_ENE1000_CTRL_EXT_GPI1_EN 0x00000002 igb_defines.h Maps SDP5 to GPI1
30527
 E1000_CTRL_EXT_PHYINT_ENE1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN igb_defines.h 　
30528
 E1000_CTRL_EXT_GPI2_ENE1000_CTRL_EXT_GPI2_EN 0x00000004 igb_defines.h Maps SDP6 to GPI2
30529
 E1000_CTRL_EXT_GPI3_ENE1000_CTRL_EXT_GPI3_EN 0x00000008 igb_defines.h Maps SDP7 to GPI3
30530
 E1000_CTRL_EXT_SDP4_DATAE1000_CTRL_EXT_SDP4_DATA 0x00000010 igb_defines.h Value of SW Definable Pin 4
30531
 E1000_CTRL_EXT_SDP5_DATAE1000_CTRL_EXT_SDP5_DATA 0x00000020 igb_defines.h Value of SW Definable Pin 5
30532
 E1000_CTRL_EXT_PHY_INTE1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA igb_defines.h 　
30533
 E1000_CTRL_EXT_SDP6_DATAE1000_CTRL_EXT_SDP6_DATA 0x00000040 igb_defines.h Value of SW Definable Pin 6
30534
 E1000_CTRL_EXT_SDP3_DATAE1000_CTRL_EXT_SDP3_DATA 0x00000080 igb_defines.h Value of SW Definable Pin 3
30535
 E1000_CTRL_EXT_SDP4_DIRE1000_CTRL_EXT_SDP4_DIR 0x00000100 igb_defines.h Direction of SDP4 0=in 1=out
30536
 E1000_CTRL_EXT_SDP5_DIRE1000_CTRL_EXT_SDP5_DIR 0x00000200 igb_defines.h Direction of SDP5 0=in 1=out
30537
 E1000_CTRL_EXT_SDP6_DIRE1000_CTRL_EXT_SDP6_DIR 0x00000400 igb_defines.h Direction of SDP6 0=in 1=out
30538
 E1000_CTRL_EXT_SDP3_DIRE1000_CTRL_EXT_SDP3_DIR 0x00000800 igb_defines.h Direction of SDP3 0=in 1=out
30539
 E1000_CTRL_EXT_ASDCHKE1000_CTRL_EXT_ASDCHK 0x00001000 igb_defines.h Initiate an ASD sequence
30540
 E1000_CTRL_EXT_EE_RSTE1000_CTRL_EXT_EE_RST 0x00002000 igb_defines.h Reinitialize from EEPROM
30541
 E1000_CTRL_EXT_IPSE1000_CTRL_EXT_IPS 0x00004000 igb_defines.h Invert Power State
30542
 E1000_CTRL_EXT_PFRSTDE1000_CTRL_EXT_PFRSTD 0x00004000 igb_defines.h 　
30543
 E1000_CTRL_EXT_SPD_BYPSE1000_CTRL_EXT_SPD_BYPS 0x00008000 igb_defines.h Speed Select Bypass
30544
 E1000_CTRL_EXT_RO_DISE1000_CTRL_EXT_RO_DIS 0x00020000 igb_defines.h Relaxed Ordering disable
30545
 E1000_CTRL_EXT_DMA_DYN_CLK_ENE1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 igb_defines.h DMA Dynamic Clock Gating
30546
 E1000_CTRL_EXT_LINK_MODE_MASKE1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 igb_defines.h 　
30547
 E1000_CTRL_EXT_LINK_MODE_GMIIE1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 igb_defines.h 　
30548
 E1000_CTRL_EXT_LINK_MODE_TBIE1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 igb_defines.h 　
30549
 E1000_CTRL_EXT_LINK_MODE_KMRNE1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 igb_defines.h 　
30550
 E1000_CTRL_EXT_LINK_MODE_PCIE_SE1000_CTRL_EXT_LINK_MODE_PCIE_S 0x00C00000 igb_defines.h 　
30551
 E1000_CTRL_EXT_LINK_MODE_PCIX_SE1000_CTRL_EXT_LINK_MODE_PCIX_S 0x00800000 igb_defines.h 　
30552
 E1000_CTRL_EXT_LINK_MODE_SGMIIE1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 igb_defines.h 　
30553
 E1000_CTRL_EXT_EIAMEE1000_CTRL_EXT_EIAME 0x01000000 igb_defines.h 　
30554
 E1000_CTRL_EXT_IRCAE1000_CTRL_EXT_IRCA 0x00000001 igb_defines.h 　
30555
 E1000_CTRL_EXT_WR_WMARK_MASKE1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 igb_defines.h 　
30556
 E1000_CTRL_EXT_WR_WMARK_256E1000_CTRL_EXT_WR_WMARK_256 0x00000000 igb_defines.h 　
30557
 E1000_CTRL_EXT_WR_WMARK_320E1000_CTRL_EXT_WR_WMARK_320 0x01000000 igb_defines.h 　
30558
 E1000_CTRL_EXT_WR_WMARK_384E1000_CTRL_EXT_WR_WMARK_384 0x02000000 igb_defines.h 　
30559
 E1000_CTRL_EXT_WR_WMARK_448E1000_CTRL_EXT_WR_WMARK_448 0x03000000 igb_defines.h 　
30560
 E1000_CTRL_EXT_CANCE1000_CTRL_EXT_CANC 0x04000000 igb_defines.h Int delay cancellation
30561
 E1000_CTRL_EXT_DRV_LOADE1000_CTRL_EXT_DRV_LOAD 0x10000000 igb_defines.h Driver loaded bit for FW
30562
 E1000_CTRL_EXT_IAMEE1000_CTRL_EXT_IAME 0x08000000 igb_defines.h Int acknowledge Auto-mask
30563
 E1000_CRTL_EXT_PB_PARENE1000_CRTL_EXT_PB_PAREN 0x01000000 igb_defines.h packet buffer parity error
30564
 E1000_CTRL_EXT_DF_PARENE1000_CTRL_EXT_DF_PAREN 0x02000000 igb_defines.h descriptor FIFO parity
30565
 E1000_CTRL_EXT_GHOST_PARENE1000_CTRL_EXT_GHOST_PAREN 0x40000000 igb_defines.h 　
30566
 E1000_CTRL_EXT_PBA_CLRE1000_CTRL_EXT_PBA_CLR 0x80000000 igb_defines.h PBA Clear
30567
 E1000_I2CCMD_REG_ADDR_SHIFTE1000_I2CCMD_REG_ADDR_SHIFT 16 igb_defines.h 　
30568
 E1000_I2CCMD_REG_ADDRE1000_I2CCMD_REG_ADDR 0x00FF0000 igb_defines.h 　
30569
 E1000_I2CCMD_PHY_ADDR_SHIFTE1000_I2CCMD_PHY_ADDR_SHIFT 24 igb_defines.h 　
30570
 E1000_I2CCMD_PHY_ADDRE1000_I2CCMD_PHY_ADDR 0x07000000 igb_defines.h 　
30571
 E1000_I2CCMD_OPCODE_READE1000_I2CCMD_OPCODE_READ 0x08000000 igb_defines.h 　
30572
 E1000_I2CCMD_OPCODE_WRITEE1000_I2CCMD_OPCODE_WRITE 0x00000000 igb_defines.h 　
30573
 E1000_I2CCMD_RESETE1000_I2CCMD_RESET 0x10000000 igb_defines.h 　
30574
 E1000_I2CCMD_READYE1000_I2CCMD_READY 0x20000000 igb_defines.h 　
30575
 E1000_I2CCMD_INTERRUPT_ENAE1000_I2CCMD_INTERRUPT_ENA 0x40000000 igb_defines.h 　
30576
 E1000_I2CCMD_ERRORE1000_I2CCMD_ERROR 0x80000000 igb_defines.h 　
30577
 E1000_MAX_SGMII_PHY_REG_ADDRE1000_MAX_SGMII_PHY_REG_ADDR 255 igb_defines.h 　
30578
 E1000_I2CCMD_PHY_TIMEOUTE1000_I2CCMD_PHY_TIMEOUT 200 igb_defines.h 　
30579
 E1000_IVAR_VALIDE1000_IVAR_VALID 0x80 igb_defines.h 　
30580
 E1000_GPIE_NSICRE1000_GPIE_NSICR 0x00000001 igb_defines.h 　
30581
 E1000_GPIE_MSIX_MODEE1000_GPIE_MSIX_MODE 0x00000010 igb_defines.h 　
30582
 E1000_GPIE_EIAMEE1000_GPIE_EIAME 0x40000000 igb_defines.h 　
30583
 E1000_GPIE_PBAE1000_GPIE_PBA 0x80000000 igb_defines.h 　
30584
 E1000_RXD_STAT_DDE1000_RXD_STAT_DD 0x01 igb_defines.h Descriptor Done
30585
 E1000_RXD_STAT_EOPE1000_RXD_STAT_EOP 0x02 igb_defines.h End of Packet
30586
 E1000_RXD_STAT_IXSME1000_RXD_STAT_IXSM 0x04 igb_defines.h Ignore checksum
30587
 E1000_RXD_STAT_VPE1000_RXD_STAT_VP 0x08 igb_defines.h IEEE VLAN Packet
30588
 E1000_RXD_STAT_UDPCSE1000_RXD_STAT_UDPCS 0x10 igb_defines.h UDP xsum calculated
30589
 E1000_RXD_STAT_TCPCSE1000_RXD_STAT_TCPCS 0x20 igb_defines.h TCP xsum calculated
30590
 E1000_RXD_STAT_IPCSE1000_RXD_STAT_IPCS 0x40 igb_defines.h IP xsum calculated
30591
 E1000_RXD_STAT_PIFE1000_RXD_STAT_PIF 0x80 igb_defines.h passed in-exact filter
30592
 E1000_RXD_STAT_CRCVE1000_RXD_STAT_CRCV 0x100 igb_defines.h Speculative CRC Valid
30593
 E1000_RXD_STAT_IPIDVE1000_RXD_STAT_IPIDV 0x200 igb_defines.h IP identification valid
30594
 E1000_RXD_STAT_UDPVE1000_RXD_STAT_UDPV 0x400 igb_defines.h Valid UDP checksum
30595
 E1000_RXD_STAT_DYNINTE1000_RXD_STAT_DYNINT 0x800 igb_defines.h Pkt caused INT via DYNINT
30596
 E1000_RXD_STAT_ACKE1000_RXD_STAT_ACK 0x8000 igb_defines.h ACK Packet indication
30597
 E1000_RXD_ERR_CEE1000_RXD_ERR_CE 0x01 igb_defines.h CRC Error
30598
 E1000_RXD_ERR_SEE1000_RXD_ERR_SE 0x02 igb_defines.h Symbol Error
30599
 E1000_RXD_ERR_SEQE1000_RXD_ERR_SEQ 0x04 igb_defines.h Sequence Error
30600
 E1000_RXD_ERR_CXEE1000_RXD_ERR_CXE 0x10 igb_defines.h Carrier Extension Error
30601
 E1000_RXD_ERR_TCPEE1000_RXD_ERR_TCPE 0x20 igb_defines.h TCP/UDP Checksum Error
30602
 E1000_RXD_ERR_IPEE1000_RXD_ERR_IPE 0x40 igb_defines.h IP Checksum Error
30603
 E1000_RXD_ERR_RXEE1000_RXD_ERR_RXE 0x80 igb_defines.h Rx Data Error
30604
 E1000_RXD_SPC_VLAN_MASKE1000_RXD_SPC_VLAN_MASK 0x0FFF igb_defines.h VLAN ID is in lower 12 bits
30605
 E1000_RXD_SPC_PRI_MASKE1000_RXD_SPC_PRI_MASK 0xE000 igb_defines.h Priority is in upper 3 bits
30606
 E1000_RXD_SPC_PRI_SHIFTE1000_RXD_SPC_PRI_SHIFT 13 igb_defines.h 　
30607
 E1000_RXD_SPC_CFI_MASKE1000_RXD_SPC_CFI_MASK 0x1000 igb_defines.h CFI is bit 12
30608
 E1000_RXD_SPC_CFI_SHIFTE1000_RXD_SPC_CFI_SHIFT 12 igb_defines.h 　
30609
 E1000_RXDEXT_STATERR_CEE1000_RXDEXT_STATERR_CE 0x01000000 igb_defines.h 　
30610
 E1000_RXDEXT_STATERR_SEE1000_RXDEXT_STATERR_SE 0x02000000 igb_defines.h 　
30611
 E1000_RXDEXT_STATERR_SEQE1000_RXDEXT_STATERR_SEQ 0x04000000 igb_defines.h 　
30612
 E1000_RXDEXT_STATERR_CXEE1000_RXDEXT_STATERR_CXE 0x10000000 igb_defines.h 　
30613
 E1000_RXDEXT_STATERR_TCPEE1000_RXDEXT_STATERR_TCPE 0x20000000 igb_defines.h 　
30614
 E1000_RXDEXT_STATERR_IPEE1000_RXDEXT_STATERR_IPE 0x40000000 igb_defines.h 　
30615
 E1000_RXDEXT_STATERR_RXEE1000_RXDEXT_STATERR_RXE 0x80000000 igb_defines.h 　
30616
 E1000_RXD_ERR_FRAME_ERR_MASKE1000_RXD_ERR_FRAME_ERR_MASK ( \ E1000_RXD_ERR_CE | \ E1000_RXD_ERR_SE | \ E1000_RXD_ERR_SEQ | \ E1000_RXD_ER igb_defines.h 　
30617
 E1000_RXDEXT_ERR_FRAME_ERR_MASKE1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ E1000_RXDEXT_STATERR_CE | \ E1000_RXDEXT_STATERR_SE | \ E1000_RXDEXT_STATERR_SEQ | \ E10 igb_defines.h 　
30618
 E1000_MRQC_ENABLE_MASKE1000_MRQC_ENABLE_MASK 0x00000007 igb_defines.h 　
30619
 E1000_MRQC_ENABLE_RSS_2QE1000_MRQC_ENABLE_RSS_2Q 0x00000001 igb_defines.h 　
30620
 E1000_MRQC_ENABLE_RSS_INTE1000_MRQC_ENABLE_RSS_INT 0x00000004 igb_defines.h 　
30621
 E1000_MRQC_RSS_FIELD_MASKE1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 igb_defines.h 　
30622
 E1000_MRQC_RSS_FIELD_IPV4_TCPE1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 igb_defines.h 　
30623
 E1000_MRQC_RSS_FIELD_IPV4E1000_MRQC_RSS_FIELD_IPV4 0x00020000 igb_defines.h 　
30624
 E1000_MRQC_RSS_FIELD_IPV6_TCP_EE1000_MRQC_RSS_FIELD_IPV6_TCP_E 0x00040000 igb_defines.h 　
30625
 E1000_MRQC_RSS_FIELD_IPV6_EXE1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 igb_defines.h 　
30626
 E1000_MRQC_RSS_FIELD_IPV6E1000_MRQC_RSS_FIELD_IPV6 0x00100000 igb_defines.h 　
30627
 E1000_MRQC_RSS_FIELD_IPV6_TCPE1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 igb_defines.h 　
30628
 E1000_RXDPS_HDRSTAT_HDRSPE1000_RXDPS_HDRSTAT_HDRSP 0x00008000 igb_defines.h 　
30629
 E1000_RXDPS_HDRSTAT_HDRLEN_MASKE1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF igb_defines.h 　
30630
 E1000_MANC_SMBUS_ENE1000_MANC_SMBUS_EN 0x00000001 igb_defines.h SMBus Enabled - RO
30631
 E1000_MANC_ASF_ENE1000_MANC_ASF_EN 0x00000002 igb_defines.h ASF Enabled - RO
30632
 E1000_MANC_R_ON_FORCEE1000_MANC_R_ON_FORCE 0x00000004 igb_defines.h Reset on Force TCO - RO
30633
 E1000_MANC_RMCP_ENE1000_MANC_RMCP_EN 0x00000100 igb_defines.h Enable RCMP 026Fh Filtering
30634
 E1000_MANC_0298_ENE1000_MANC_0298_EN 0x00000200 igb_defines.h Enable RCMP 0298h Filtering
30635
 E1000_MANC_IPV4_ENE1000_MANC_IPV4_EN 0x00000400 igb_defines.h Enable IPv4
30636
 E1000_MANC_IPV6_ENE1000_MANC_IPV6_EN 0x00000800 igb_defines.h Enable IPv6
30637
 E1000_MANC_SNAP_ENE1000_MANC_SNAP_EN 0x00001000 igb_defines.h Accept LLC/SNAP
30638
 E1000_MANC_ARP_ENE1000_MANC_ARP_EN 0x00002000 igb_defines.h Enable ARP Request Filtering
30639
 E1000_MANC_NEIGHBOR_ENE1000_MANC_NEIGHBOR_EN 0x00004000 igb_defines.h 　
30640
 E1000_MANC_ARP_RES_ENE1000_MANC_ARP_RES_EN 0x00008000 igb_defines.h Enable ARP response Filtering
30641
 E1000_MANC_TCO_RESETE1000_MANC_TCO_RESET 0x00010000 igb_defines.h TCO Reset Occurred
30642
 E1000_MANC_RCV_TCO_ENE1000_MANC_RCV_TCO_EN 0x00020000 igb_defines.h Receive TCO Packets Enabled
30643
 E1000_MANC_REPORT_STATUSE1000_MANC_REPORT_STATUS 0x00040000 igb_defines.h Status Reporting Enabled
30644
 E1000_MANC_RCV_ALLE1000_MANC_RCV_ALL 0x00080000 igb_defines.h Receive All Enabled
30645
 E1000_MANC_BLK_PHY_RST_ON_IDEE1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 igb_defines.h Block phy resets
30646
 E1000_MANC_EN_MAC_ADDR_FILTERE1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 igb_defines.h 　
30647
 E1000_MANC_EN_MNG2HOSTE1000_MANC_EN_MNG2HOST 0x00200000 igb_defines.h 　
30648
 E1000_MANC_EN_IP_ADDR_FILTERE1000_MANC_EN_IP_ADDR_FILTER 0x00400000 igb_defines.h 　
30649
 E1000_MANC_EN_XSUM_FILTERE1000_MANC_EN_XSUM_FILTER 0x00800000 igb_defines.h Enable checksum filtering
30650
 E1000_MANC_BR_ENE1000_MANC_BR_EN 0x01000000 igb_defines.h Enable broadcast filtering
30651
 E1000_MANC_SMB_REQE1000_MANC_SMB_REQ 0x01000000 igb_defines.h SMBus Request
30652
 E1000_MANC_SMB_GNTE1000_MANC_SMB_GNT 0x02000000 igb_defines.h SMBus Grant
30653
 E1000_MANC_SMB_CLK_INE1000_MANC_SMB_CLK_IN 0x04000000 igb_defines.h SMBus Clock In
30654
 E1000_MANC_SMB_DATA_INE1000_MANC_SMB_DATA_IN 0x08000000 igb_defines.h SMBus Data In
30655
 E1000_MANC_SMB_DATA_OUTE1000_MANC_SMB_DATA_OUT 0x10000000 igb_defines.h SMBus Data Out
30656
 E1000_MANC_SMB_CLK_OUTE1000_MANC_SMB_CLK_OUT 0x20000000 igb_defines.h SMBus Clock Out
30657
 E1000_MANC_SMB_DATA_OUT_SHIFTE1000_MANC_SMB_DATA_OUT_SHIFT 28 igb_defines.h SMBus Data Out Shift
30658
 E1000_MANC_SMB_CLK_OUT_SHIFTE1000_MANC_SMB_CLK_OUT_SHIFT 29 igb_defines.h SMBus Clock Out Shift
30659
 E1000_RCTL_RSTE1000_RCTL_RST 0x00000001 igb_defines.h Software reset
30660
 E1000_RCTL_ENE1000_RCTL_EN 0x00000002 igb_defines.h enable
30661
 E1000_RCTL_SBPE1000_RCTL_SBP 0x00000004 igb_defines.h store bad packet
30662
 E1000_RCTL_UPEE1000_RCTL_UPE 0x00000008 igb_defines.h unicast promisc enable
30663
 E1000_RCTL_MPEE1000_RCTL_MPE 0x00000010 igb_defines.h multicast promisc enable
30664
 E1000_RCTL_LPEE1000_RCTL_LPE 0x00000020 igb_defines.h long packet enable
30665
 E1000_RCTL_LBM_NOE1000_RCTL_LBM_NO 0x00000000 igb_defines.h no loopback mode
30666
 E1000_RCTL_LBM_MACE1000_RCTL_LBM_MAC 0x00000040 igb_defines.h MAC loopback mode
30667
 E1000_RCTL_LBM_SLPE1000_RCTL_LBM_SLP 0x00000080 igb_defines.h serial link loopback mode
30668
 E1000_RCTL_LBM_TCVRE1000_RCTL_LBM_TCVR 0x000000C0 igb_defines.h tcvr loopback mode
30669
 E1000_RCTL_DTYP_MASKE1000_RCTL_DTYP_MASK 0x00000C00 igb_defines.h Descriptor type mask
30670
 E1000_RCTL_DTYP_PSE1000_RCTL_DTYP_PS 0x00000400 igb_defines.h Packet Split descriptor
30671
 E1000_RCTL_RDMTS_HALFE1000_RCTL_RDMTS_HALF 0x00000000 igb_defines.h rx desc min thresh size
30672
 E1000_RCTL_RDMTS_QUATE1000_RCTL_RDMTS_QUAT 0x00000100 igb_defines.h rx desc min thresh size
30673
 E1000_RCTL_RDMTS_EIGTHE1000_RCTL_RDMTS_EIGTH 0x00000200 igb_defines.h rx desc min thresh size
30674
 E1000_RCTL_MO_SHIFTE1000_RCTL_MO_SHIFT 12 igb_defines.h multicast offset shift
30675
 E1000_RCTL_MO_0E1000_RCTL_MO_0 0x00000000 igb_defines.h multicast offset 11:0
30676
 E1000_RCTL_MO_1E1000_RCTL_MO_1 0x00001000 igb_defines.h multicast offset 12:1
30677
 E1000_RCTL_MO_2E1000_RCTL_MO_2 0x00002000 igb_defines.h multicast offset 13:2
30678
 E1000_RCTL_MO_3E1000_RCTL_MO_3 0x00003000 igb_defines.h multicast offset 15:4
30679
 E1000_RCTL_MDRE1000_RCTL_MDR 0x00004000 igb_defines.h multicast desc ring 0
30680
 E1000_RCTL_BAME1000_RCTL_BAM 0x00008000 igb_defines.h broadcast enable
30681
 E1000_RCTL_SZ_2048E1000_RCTL_SZ_2048 0x00000000 igb_defines.h rx buffer size 2048
30682
 E1000_RCTL_SZ_1024E1000_RCTL_SZ_1024 0x00010000 igb_defines.h rx buffer size 1024
30683
 E1000_RCTL_SZ_512E1000_RCTL_SZ_512 0x00020000 igb_defines.h rx buffer size 512
30684
 E1000_RCTL_SZ_256E1000_RCTL_SZ_256 0x00030000 igb_defines.h rx buffer size 256
30685
 E1000_RCTL_SZ_16384E1000_RCTL_SZ_16384 0x00010000 igb_defines.h rx buffer size 16384
30686
 E1000_RCTL_SZ_8192E1000_RCTL_SZ_8192 0x00020000 igb_defines.h rx buffer size 8192
30687
 E1000_RCTL_SZ_4096E1000_RCTL_SZ_4096 0x00030000 igb_defines.h rx buffer size 4096
30688
 E1000_RCTL_VFEE1000_RCTL_VFE 0x00040000 igb_defines.h vlan filter enable
30689
 E1000_RCTL_CFIENE1000_RCTL_CFIEN 0x00080000 igb_defines.h canonical form enable
30690
 E1000_RCTL_CFIE1000_RCTL_CFI 0x00100000 igb_defines.h canonical form indicator
30691
 E1000_RCTL_DPFE1000_RCTL_DPF 0x00400000 igb_defines.h discard pause frames
30692
 E1000_RCTL_PMCFE1000_RCTL_PMCF 0x00800000 igb_defines.h pass MAC control frames
30693
 E1000_RCTL_BSEXE1000_RCTL_BSEX 0x02000000 igb_defines.h Buffer size extension
30694
 E1000_RCTL_SECRCE1000_RCTL_SECRC 0x04000000 igb_defines.h Strip Ethernet CRC
30695
 E1000_RCTL_FLXBUF_MASKE1000_RCTL_FLXBUF_MASK 0x78000000 igb_defines.h Flexible buffer size
30696
 E1000_RCTL_FLXBUF_SHIFTE1000_RCTL_FLXBUF_SHIFT 27 igb_defines.h Flexible buffer shift
30697
 E1000_PSRCTL_BSIZE0_MASKE1000_PSRCTL_BSIZE0_MASK 0x0000007F igb_defines.h 　
30698
 E1000_PSRCTL_BSIZE1_MASKE1000_PSRCTL_BSIZE1_MASK 0x00003F00 igb_defines.h 　
30699
 E1000_PSRCTL_BSIZE2_MASKE1000_PSRCTL_BSIZE2_MASK 0x003F0000 igb_defines.h 　
30700
 E1000_PSRCTL_BSIZE3_MASKE1000_PSRCTL_BSIZE3_MASK 0x3F000000 igb_defines.h 　
30701
 E1000_PSRCTL_BSIZE0_SHIFTE1000_PSRCTL_BSIZE0_SHIFT 7 igb_defines.h Shift _right_ 7
30702
 E1000_PSRCTL_BSIZE1_SHIFTE1000_PSRCTL_BSIZE1_SHIFT 2 igb_defines.h Shift _right_ 2
30703
 E1000_PSRCTL_BSIZE2_SHIFTE1000_PSRCTL_BSIZE2_SHIFT 6 igb_defines.h Shift _left_ 6
30704
 E1000_PSRCTL_BSIZE3_SHIFTE1000_PSRCTL_BSIZE3_SHIFT 14 igb_defines.h Shift _left_ 14
30705
 E1000_SWFW_EEP_SME1000_SWFW_EEP_SM 0x01 igb_defines.h 　
30706
 E1000_SWFW_PHY0_SME1000_SWFW_PHY0_SM 0x02 igb_defines.h 　
30707
 E1000_SWFW_PHY1_SME1000_SWFW_PHY1_SM 0x04 igb_defines.h 　
30708
 E1000_SWFW_CSR_SME1000_SWFW_CSR_SM 0x08 igb_defines.h 　
30709
 E1000_FACTPS_LFSE1000_FACTPS_LFS 0x40000000 igb_defines.h LAN Function Select
30710
 E1000_CTRL_FDE1000_CTRL_FD 0x00000001 igb_defines.h Full duplex.0=half; 1=full
30711
 E1000_CTRL_BEME1000_CTRL_BEM 0x00000002 igb_defines.h Endian Mode.0=little,1=big
30712
 E1000_CTRL_PRIORE1000_CTRL_PRIOR 0x00000004 igb_defines.h Priority on PCI. 0=rx,1=fair
30713
 E1000_CTRL_GIO_MASTER_DISABLEE1000_CTRL_GIO_MASTER_DISABLE 0x00000004 igb_defines.h Blocks new Master reqs
30714
 E1000_CTRL_LRSTE1000_CTRL_LRST 0x00000008 igb_defines.h Link reset. 0=normal,1=reset
30715
 E1000_CTRL_TMEE1000_CTRL_TME 0x00000010 igb_defines.h Test mode. 0=normal,1=test
30716
 E1000_CTRL_SLEE1000_CTRL_SLE 0x00000020 igb_defines.h Serial Link on 0=dis,1=en
30717
 E1000_CTRL_ASDEE1000_CTRL_ASDE 0x00000020 igb_defines.h Auto-speed detect enable
30718
 E1000_CTRL_SLUE1000_CTRL_SLU 0x00000040 igb_defines.h Set link up (Force Link)
30719
 E1000_CTRL_ILOSE1000_CTRL_ILOS 0x00000080 igb_defines.h Invert Loss-Of Signal
30720
 E1000_CTRL_SPD_SELE1000_CTRL_SPD_SEL 0x00000300 igb_defines.h Speed Select Mask
30721
 E1000_CTRL_SPD_10E1000_CTRL_SPD_10 0x00000000 igb_defines.h Force 10Mb
30722
 E1000_CTRL_SPD_100E1000_CTRL_SPD_100 0x00000100 igb_defines.h Force 100Mb
30723
 E1000_CTRL_SPD_1000E1000_CTRL_SPD_1000 0x00000200 igb_defines.h Force 1Gb
30724
 E1000_CTRL_BEM32E1000_CTRL_BEM32 0x00000400 igb_defines.h Big Endian 32 mode
30725
 E1000_CTRL_FRCSPDE1000_CTRL_FRCSPD 0x00000800 igb_defines.h Force Speed
30726
 E1000_CTRL_FRCDPXE1000_CTRL_FRCDPX 0x00001000 igb_defines.h Force Duplex
30727
 E1000_CTRL_D_UD_ENE1000_CTRL_D_UD_EN 0x00002000 igb_defines.h Dock/Undock enable
30728
 E1000_CTRL_D_UD_POLARITYE1000_CTRL_D_UD_POLARITY 0x00004000 igb_defines.h Defined polarity of Dock/Undock
30729
 E1000_CTRL_FORCE_PHY_RESETE1000_CTRL_FORCE_PHY_RESET 0x00008000 igb_defines.h Reset both PHY ports, through
30730
 E1000_CTRL_EXT_LINK_ENE1000_CTRL_EXT_LINK_EN 0x00010000 igb_defines.h enable link status from external
30731
 E1000_CTRL_SWDPIN0E1000_CTRL_SWDPIN0 0x00040000 igb_defines.h SWDPIN 0 value
30732
 E1000_CTRL_SWDPIN1E1000_CTRL_SWDPIN1 0x00080000 igb_defines.h SWDPIN 1 value
30733
 E1000_CTRL_SWDPIN2E1000_CTRL_SWDPIN2 0x00100000 igb_defines.h SWDPIN 2 value
30734
 E1000_CTRL_ADVD3WUCE1000_CTRL_ADVD3WUC 0x00100000 igb_defines.h D3 WUC
30735
 E1000_CTRL_SWDPIN3E1000_CTRL_SWDPIN3 0x00200000 igb_defines.h SWDPIN 3 value
30736
 E1000_CTRL_SWDPIO0E1000_CTRL_SWDPIO0 0x00400000 igb_defines.h SWDPIN 0 Input or output
30737
 E1000_CTRL_SWDPIO1E1000_CTRL_SWDPIO1 0x00800000 igb_defines.h SWDPIN 1 input or output
30738
 E1000_CTRL_SWDPIO2E1000_CTRL_SWDPIO2 0x01000000 igb_defines.h SWDPIN 2 input or output
30739
 E1000_CTRL_SWDPIO3E1000_CTRL_SWDPIO3 0x02000000 igb_defines.h SWDPIN 3 input or output
30740
 E1000_CTRL_RSTE1000_CTRL_RST 0x04000000 igb_defines.h Global reset
30741
 E1000_CTRL_RFCEE1000_CTRL_RFCE 0x08000000 igb_defines.h Receive Flow Control enable
30742
 E1000_CTRL_TFCEE1000_CTRL_TFCE 0x10000000 igb_defines.h Transmit flow control enable
30743
 E1000_CTRL_RTEE1000_CTRL_RTE 0x20000000 igb_defines.h Routing tag enable
30744
 E1000_CTRL_VMEE1000_CTRL_VME 0x40000000 igb_defines.h IEEE VLAN mode enable
30745
 E1000_CTRL_PHY_RSTE1000_CTRL_PHY_RST 0x80000000 igb_defines.h PHY Reset
30746
 E1000_CTRL_SW2FW_INTE1000_CTRL_SW2FW_INT 0x02000000 igb_defines.h Initiate an interrupt to ME
30747
 E1000_CTRL_I2C_ENAE1000_CTRL_I2C_ENA 0x02000000 igb_defines.h I2C enable
30748
 E1000_CTRL_PHY_RESET_DIRE1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 igb_defines.h 　
30749
 E1000_CTRL_PHY_RESETE1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 igb_defines.h 　
30750
 E1000_CTRL_MDIO_DIRE1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 igb_defines.h 　
30751
 E1000_CTRL_MDIOE1000_CTRL_MDIO E1000_CTRL_SWDPIN2 igb_defines.h 　
30752
 E1000_CTRL_MDC_DIRE1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 igb_defines.h 　
30753
 E1000_CTRL_MDCE1000_CTRL_MDC E1000_CTRL_SWDPIN3 igb_defines.h 　
30754
 E1000_CTRL_PHY_RESET_DIR4E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR igb_defines.h 　
30755
 E1000_CTRL_PHY_RESET4E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA igb_defines.h 　
30756
 E1000_CONNSW_ENRGSRCE1000_CONNSW_ENRGSRC 0x4 igb_defines.h 　
30757
 E1000_PCS_CFG_PCS_ENE1000_PCS_CFG_PCS_EN 8 igb_defines.h 　
30758
 E1000_PCS_LCTL_FLV_LINK_UPE1000_PCS_LCTL_FLV_LINK_UP 1 igb_defines.h 　
30759
 E1000_PCS_LCTL_FSV_10E1000_PCS_LCTL_FSV_10 0 igb_defines.h 　
30760
 E1000_PCS_LCTL_FSV_100E1000_PCS_LCTL_FSV_100 2 igb_defines.h 　
30761
 E1000_PCS_LCTL_FSV_1000E1000_PCS_LCTL_FSV_1000 4 igb_defines.h 　
30762
 E1000_PCS_LCTL_FDV_FULLE1000_PCS_LCTL_FDV_FULL 8 igb_defines.h 　
30763
 E1000_PCS_LCTL_FSDE1000_PCS_LCTL_FSD 0x10 igb_defines.h 　
30764
 E1000_PCS_LCTL_FORCE_LINKE1000_PCS_LCTL_FORCE_LINK 0x20 igb_defines.h 　
30765
 E1000_PCS_LCTL_LOW_LINK_LATCHE1000_PCS_LCTL_LOW_LINK_LATCH 0x40 igb_defines.h 　
30766
 E1000_PCS_LCTL_FORCE_FCTRLE1000_PCS_LCTL_FORCE_FCTRL 0x80 igb_defines.h 　
30767
 E1000_PCS_LCTL_AN_ENABLEE1000_PCS_LCTL_AN_ENABLE 0x10000 igb_defines.h 　
30768
 E1000_PCS_LCTL_AN_RESTARTE1000_PCS_LCTL_AN_RESTART 0x20000 igb_defines.h 　
30769
 E1000_PCS_LCTL_AN_TIMEOUTE1000_PCS_LCTL_AN_TIMEOUT 0x40000 igb_defines.h 　
30770
 E1000_PCS_LCTL_AN_SGMII_BYPASSE1000_PCS_LCTL_AN_SGMII_BYPASS 0x80000 igb_defines.h 　
30771
 E1000_PCS_LCTL_AN_SGMII_TRIGGERE1000_PCS_LCTL_AN_SGMII_TRIGGER 0x100000 igb_defines.h 　
30772
 E1000_PCS_LCTL_FAST_LINK_TIMERE1000_PCS_LCTL_FAST_LINK_TIMER 0x1000000 igb_defines.h 　
30773
 E1000_PCS_LCTL_LINK_OK_FIXE1000_PCS_LCTL_LINK_OK_FIX 0x2000000 igb_defines.h 　
30774
 E1000_PCS_LCTL_CRS_ON_NIE1000_PCS_LCTL_CRS_ON_NI 0x4000000 igb_defines.h 　
30775
 E1000_ENABLE_SERDES_LOOPBACKE1000_ENABLE_SERDES_LOOPBACK 0x0410 igb_defines.h 　
30776
 E1000_PCS_LSTS_LINK_OKE1000_PCS_LSTS_LINK_OK 1 igb_defines.h 　
30777
 E1000_PCS_LSTS_SPEED_10E1000_PCS_LSTS_SPEED_10 0 igb_defines.h 　
30778
 E1000_PCS_LSTS_SPEED_100E1000_PCS_LSTS_SPEED_100 2 igb_defines.h 　
30779
 E1000_PCS_LSTS_SPEED_1000E1000_PCS_LSTS_SPEED_1000 4 igb_defines.h 　
30780
 E1000_PCS_LSTS_DUPLEX_FULLE1000_PCS_LSTS_DUPLEX_FULL 8 igb_defines.h 　
30781
 E1000_PCS_LSTS_SYNK_OKE1000_PCS_LSTS_SYNK_OK 0x10 igb_defines.h 　
30782
 E1000_PCS_LSTS_AN_COMPLETEE1000_PCS_LSTS_AN_COMPLETE 0x10000 igb_defines.h 　
30783
 E1000_PCS_LSTS_AN_PAGE_RXE1000_PCS_LSTS_AN_PAGE_RX 0x20000 igb_defines.h 　
30784
 E1000_PCS_LSTS_AN_TIMED_OUTE1000_PCS_LSTS_AN_TIMED_OUT 0x40000 igb_defines.h 　
30785
 E1000_PCS_LSTS_AN_REMOTE_FAULTE1000_PCS_LSTS_AN_REMOTE_FAULT 0x80000 igb_defines.h 　
30786
 E1000_PCS_LSTS_AN_ERROR_RWSE1000_PCS_LSTS_AN_ERROR_RWS 0x100000 igb_defines.h 　
30787
 E1000_STATUS_FDE1000_STATUS_FD 0x00000001 igb_defines.h Full duplex.0=half,1=full
30788
 E1000_STATUS_LUE1000_STATUS_LU 0x00000002 igb_defines.h Link up.0=no,1=link
30789
 E1000_STATUS_FUNC_MASKE1000_STATUS_FUNC_MASK 0x0000000C igb_defines.h PCI Function Mask
30790
 E1000_STATUS_FUNC_SHIFTE1000_STATUS_FUNC_SHIFT 2 igb_defines.h 　
30791
 E1000_STATUS_FUNC_0E1000_STATUS_FUNC_0 0x00000000 igb_defines.h Function 0
30792
 E1000_STATUS_FUNC_1E1000_STATUS_FUNC_1 0x00000004 igb_defines.h Function 1
30793
 E1000_STATUS_TXOFFE1000_STATUS_TXOFF 0x00000010 igb_defines.h transmission paused
30794
 E1000_STATUS_TBIMODEE1000_STATUS_TBIMODE 0x00000020 igb_defines.h TBI mode
30795
 E1000_STATUS_SPEED_MASKE1000_STATUS_SPEED_MASK 0x000000C0 igb_defines.h 　
30796
 E1000_STATUS_SPEED_10E1000_STATUS_SPEED_10 0x00000000 igb_defines.h Speed 10Mb/s
30797
 E1000_STATUS_SPEED_100E1000_STATUS_SPEED_100 0x00000040 igb_defines.h Speed 100Mb/s
30798
 E1000_STATUS_SPEED_1000E1000_STATUS_SPEED_1000 0x00000080 igb_defines.h Speed 1000Mb/s
30799
 E1000_STATUS_LAN_INIT_DONEE1000_STATUS_LAN_INIT_DONE 0x00000200 igb_defines.h Lan Init Completion by NVM
30800
 E1000_STATUS_ASDVE1000_STATUS_ASDV 0x00000300 igb_defines.h Auto speed detect value
30801
 E1000_STATUS_PHYRAE1000_STATUS_PHYRA 0x00000400 igb_defines.h PHY Reset Asserted
30802
 E1000_STATUS_DOCK_CIE1000_STATUS_DOCK_CI 0x00000800 igb_defines.h Change in Dock/Undock state.
30803
 E1000_STATUS_GIO_MASTER_ENABLEE1000_STATUS_GIO_MASTER_ENABLE 0x00080000 igb_defines.h Master request status
30804
 E1000_STATUS_MTXCKOKE1000_STATUS_MTXCKOK 0x00000400 igb_defines.h MTX clock running OK
30805
 E1000_STATUS_PCI66E1000_STATUS_PCI66 0x00000800 igb_defines.h In 66Mhz slot
30806
 E1000_STATUS_BUS64E1000_STATUS_BUS64 0x00001000 igb_defines.h In 64 bit slot
30807
 E1000_STATUS_PCIX_MODEE1000_STATUS_PCIX_MODE 0x00002000 igb_defines.h PCI-X mode
30808
 E1000_STATUS_PCIX_SPEEDE1000_STATUS_PCIX_SPEED 0x0000C000 igb_defines.h PCI-X bus speed
30809
 E1000_STATUS_BMC_SKU_0E1000_STATUS_BMC_SKU_0 0x00100000 igb_defines.h BMC USB redirect disabled
30810
 E1000_STATUS_BMC_SKU_1E1000_STATUS_BMC_SKU_1 0x00200000 igb_defines.h BMC SRAM disabled
30811
 E1000_STATUS_BMC_SKU_2E1000_STATUS_BMC_SKU_2 0x00400000 igb_defines.h BMC SDRAM disabled
30812
 E1000_STATUS_BMC_CRYPTOE1000_STATUS_BMC_CRYPTO 0x00800000 igb_defines.h BMC crypto disabled
30813
 E1000_STATUS_BMC_LITEE1000_STATUS_BMC_LITE 0x01000000 igb_defines.h BMC external code execution
30814
 E1000_STATUS_RGMII_ENABLEE1000_STATUS_RGMII_ENABLE 0x02000000 igb_defines.h RGMII disabled
30815
 E1000_STATUS_FUSE_8E1000_STATUS_FUSE_8 0x04000000 igb_defines.h 　
30816
 E1000_STATUS_FUSE_9E1000_STATUS_FUSE_9 0x08000000 igb_defines.h 　
30817
 E1000_STATUS_SERDES0_DISE1000_STATUS_SERDES0_DIS 0x10000000 igb_defines.h SERDES disabled on port 0
30818
 E1000_STATUS_SERDES1_DISE1000_STATUS_SERDES1_DIS 0x20000000 igb_defines.h SERDES disabled on port 1
30819
 E1000_STATUS_PCIX_SPEED_66E1000_STATUS_PCIX_SPEED_66 0x00000000 igb_defines.h PCI-X bus speed 50-66 MHz
30820
 E1000_STATUS_PCIX_SPEED_100E1000_STATUS_PCIX_SPEED_100 0x00004000 igb_defines.h PCI-X bus speed 66-100 MHz
30821
 E1000_STATUS_PCIX_SPEED_133E1000_STATUS_PCIX_SPEED_133 0x00008000 igb_defines.h PCI-X bus speed 100-133 MHz
30822
 SPEED_10SPEED_10 10 igb_defines.h 　
30823
 SPEED_100SPEED_100 100 igb_defines.h 　
30824
 SPEED_1000SPEED_1000 1000 igb_defines.h 　
30825
 HALF_DUPLEXHALF_DUPLEX 1 igb_defines.h 　
30826
 FULL_DUPLEXFULL_DUPLEX 2 igb_defines.h 　
30827
 PHY_FORCE_TIMEPHY_FORCE_TIME 20 igb_defines.h 　
30828
 ADVERTISE_10_HALFADVERTISE_10_HALF 0x0001 igb_defines.h 　
30829
 ADVERTISE_10_FULLADVERTISE_10_FULL 0x0002 igb_defines.h 　
30830
 ADVERTISE_100_HALFADVERTISE_100_HALF 0x0004 igb_defines.h 　
30831
 ADVERTISE_100_FULLADVERTISE_100_FULL 0x0008 igb_defines.h 　
30832
 ADVERTISE_1000_HALFADVERTISE_1000_HALF 0x0010 igb_defines.h Not used, just FYI
30833
 ADVERTISE_1000_FULLADVERTISE_1000_FULL 0x0020 igb_defines.h 　
30834
 E1000_ALL_SPEED_DUPLEXE1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) igb_defines.h 　
30835
 E1000_ALL_NOT_GIGE1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ ADVERTISE_100_HALF | ADVERTISE_100_FULL) igb_defines.h 　
30836
 E1000_ALL_100_SPEEDE1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) igb_defines.h 　
30837
 E1000_ALL_10_SPEEDE1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) igb_defines.h 　
30838
 E1000_ALL_FULL_DUPLEXE1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ ADVERTISE_1000_FULL) igb_defines.h 　
30839
 E1000_ALL_HALF_DUPLEXE1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) igb_defines.h 　
30840
 AUTONEG_ADVERTISE_SPEED_DEFAULTAUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX igb_defines.h 　
30841
 E1000_LEDCTL_LED0_MODE_MASKE1000_LEDCTL_LED0_MODE_MASK 0x0000000F igb_defines.h 　
30842
 E1000_LEDCTL_LED0_MODE_SHIFTE1000_LEDCTL_LED0_MODE_SHIFT 0 igb_defines.h 　
30843
 E1000_LEDCTL_LED0_BLINK_RATEE1000_LEDCTL_LED0_BLINK_RATE 0x00000020 igb_defines.h 　
30844
 E1000_LEDCTL_LED0_IVRTE1000_LEDCTL_LED0_IVRT 0x00000040 igb_defines.h 　
30845
 E1000_LEDCTL_LED0_BLINKE1000_LEDCTL_LED0_BLINK 0x00000080 igb_defines.h 　
30846
 E1000_LEDCTL_LED1_MODE_MASKE1000_LEDCTL_LED1_MODE_MASK 0x00000F00 igb_defines.h 　
30847
 E1000_LEDCTL_LED1_MODE_SHIFTE1000_LEDCTL_LED1_MODE_SHIFT 8 igb_defines.h 　
30848
 E1000_LEDCTL_LED1_BLINK_RATEE1000_LEDCTL_LED1_BLINK_RATE 0x00002000 igb_defines.h 　
30849
 E1000_LEDCTL_LED1_IVRTE1000_LEDCTL_LED1_IVRT 0x00004000 igb_defines.h 　
30850
 E1000_LEDCTL_LED1_BLINKE1000_LEDCTL_LED1_BLINK 0x00008000 igb_defines.h 　
30851
 E1000_LEDCTL_LED2_MODE_MASKE1000_LEDCTL_LED2_MODE_MASK 0x000F0000 igb_defines.h 　
30852
 E1000_LEDCTL_LED2_MODE_SHIFTE1000_LEDCTL_LED2_MODE_SHIFT 16 igb_defines.h 　
30853
 E1000_LEDCTL_LED2_BLINK_RATEE1000_LEDCTL_LED2_BLINK_RATE 0x00200000 igb_defines.h 　
30854
 E1000_LEDCTL_LED2_IVRTE1000_LEDCTL_LED2_IVRT 0x00400000 igb_defines.h 　
30855
 E1000_LEDCTL_LED2_BLINKE1000_LEDCTL_LED2_BLINK 0x00800000 igb_defines.h 　
30856
 E1000_LEDCTL_LED3_MODE_MASKE1000_LEDCTL_LED3_MODE_MASK 0x0F000000 igb_defines.h 　
30857
 E1000_LEDCTL_LED3_MODE_SHIFTE1000_LEDCTL_LED3_MODE_SHIFT 24 igb_defines.h 　
30858
 E1000_LEDCTL_LED3_BLINK_RATEE1000_LEDCTL_LED3_BLINK_RATE 0x20000000 igb_defines.h 　
30859
 E1000_LEDCTL_LED3_IVRTE1000_LEDCTL_LED3_IVRT 0x40000000 igb_defines.h 　
30860
 E1000_LEDCTL_LED3_BLINKE1000_LEDCTL_LED3_BLINK 0x80000000 igb_defines.h 　
30861
 E1000_LEDCTL_MODE_LINK_10_1000E1000_LEDCTL_MODE_LINK_10_1000 0x0 igb_defines.h 　
30862
 E1000_LEDCTL_MODE_LINK_100_1000E1000_LEDCTL_MODE_LINK_100_1000 0x1 igb_defines.h 　
30863
 E1000_LEDCTL_MODE_LINK_UPE1000_LEDCTL_MODE_LINK_UP 0x2 igb_defines.h 　
30864
 E1000_LEDCTL_MODE_ACTIVITYE1000_LEDCTL_MODE_ACTIVITY 0x3 igb_defines.h 　
30865
 E1000_LEDCTL_MODE_LINK_ACTIVITYE1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 igb_defines.h 　
30866
 E1000_LEDCTL_MODE_LINK_10E1000_LEDCTL_MODE_LINK_10 0x5 igb_defines.h 　
30867
 E1000_LEDCTL_MODE_LINK_100E1000_LEDCTL_MODE_LINK_100 0x6 igb_defines.h 　
30868
 E1000_LEDCTL_MODE_LINK_1000E1000_LEDCTL_MODE_LINK_1000 0x7 igb_defines.h 　
30869
 E1000_LEDCTL_MODE_PCIX_MODEE1000_LEDCTL_MODE_PCIX_MODE 0x8 igb_defines.h 　
30870
 E1000_LEDCTL_MODE_FULL_DUPLEXE1000_LEDCTL_MODE_FULL_DUPLEX 0x9 igb_defines.h 　
30871
 E1000_LEDCTL_MODE_COLLISIONE1000_LEDCTL_MODE_COLLISION 0xA igb_defines.h 　
30872
 E1000_LEDCTL_MODE_BUS_SPEEDE1000_LEDCTL_MODE_BUS_SPEED 0xB igb_defines.h 　
30873
 E1000_LEDCTL_MODE_BUS_SIZEE1000_LEDCTL_MODE_BUS_SIZE 0xC igb_defines.h 　
30874
 E1000_LEDCTL_MODE_PAUSEDE1000_LEDCTL_MODE_PAUSED 0xD igb_defines.h 　
30875
 E1000_LEDCTL_MODE_LED_ONE1000_LEDCTL_MODE_LED_ON 0xE igb_defines.h 　
30876
 E1000_LEDCTL_MODE_LED_OFFE1000_LEDCTL_MODE_LED_OFF 0xF igb_defines.h 　
30877
 E1000_TXD_DTYP_DE1000_TXD_DTYP_D 0x00100000 igb_defines.h Data Descriptor
30878
 E1000_TXD_DTYP_CE1000_TXD_DTYP_C 0x00000000 igb_defines.h Context Descriptor
30879
 E1000_TXD_POPTS_SHIFTE1000_TXD_POPTS_SHIFT 8 igb_defines.h POPTS shift
30880
 E1000_TXD_POPTS_IXSME1000_TXD_POPTS_IXSM 0x01 igb_defines.h Insert IP checksum
30881
 E1000_TXD_POPTS_TXSME1000_TXD_POPTS_TXSM 0x02 igb_defines.h Insert TCP/UDP checksum
30882
 E1000_TXD_CMD_EOPE1000_TXD_CMD_EOP 0x01000000 igb_defines.h End of Packet
30883
 E1000_TXD_CMD_IFCSE1000_TXD_CMD_IFCS 0x02000000 igb_defines.h Insert FCS (Ethernet CRC)
30884
 E1000_TXD_CMD_ICE1000_TXD_CMD_IC 0x04000000 igb_defines.h Insert Checksum
30885
 E1000_TXD_CMD_RSE1000_TXD_CMD_RS 0x08000000 igb_defines.h Report Status
30886
 E1000_TXD_CMD_RPSE1000_TXD_CMD_RPS 0x10000000 igb_defines.h Report Packet Sent
30887
 E1000_TXD_CMD_DEXTE1000_TXD_CMD_DEXT 0x20000000 igb_defines.h Descriptor extension (0 = legacy)
30888
 E1000_TXD_CMD_VLEE1000_TXD_CMD_VLE 0x40000000 igb_defines.h Add VLAN tag
30889
 E1000_TXD_CMD_IDEE1000_TXD_CMD_IDE 0x80000000 igb_defines.h Enable Tidv register
30890
 E1000_TXD_STAT_DDE1000_TXD_STAT_DD 0x00000001 igb_defines.h Descriptor Done
30891
 E1000_TXD_STAT_ECE1000_TXD_STAT_EC 0x00000002 igb_defines.h Excess Collisions
30892
 E1000_TXD_STAT_LCE1000_TXD_STAT_LC 0x00000004 igb_defines.h Late Collisions
30893
 E1000_TXD_STAT_TUE1000_TXD_STAT_TU 0x00000008 igb_defines.h Transmit underrun
30894
 E1000_TXD_CMD_TCPE1000_TXD_CMD_TCP 0x01000000 igb_defines.h TCP packet
30895
 E1000_TXD_CMD_IPE1000_TXD_CMD_IP 0x02000000 igb_defines.h IP packet
30896
 E1000_TXD_CMD_TSEE1000_TXD_CMD_TSE 0x04000000 igb_defines.h TCP Seg enable
30897
 E1000_TXD_STAT_TCE1000_TXD_STAT_TC 0x00000004 igb_defines.h Tx Underrun
30898
 E1000_TCTL_RSTE1000_TCTL_RST 0x00000001 igb_defines.h software reset
30899
 E1000_TCTL_ENE1000_TCTL_EN 0x00000002 igb_defines.h enable tx
30900
 E1000_TCTL_BCEE1000_TCTL_BCE 0x00000004 igb_defines.h busy check enable
30901
 E1000_TCTL_PSPE1000_TCTL_PSP 0x00000008 igb_defines.h pad short packets
30902
 E1000_TCTL_CTE1000_TCTL_CT 0x00000ff0 igb_defines.h collision threshold
30903
 E1000_TCTL_COLDE1000_TCTL_COLD 0x003ff000 igb_defines.h collision distance
30904
 E1000_TCTL_SWXOFFE1000_TCTL_SWXOFF 0x00400000 igb_defines.h SW Xoff transmission
30905
 E1000_TCTL_PBEE1000_TCTL_PBE 0x00800000 igb_defines.h Packet Burst Enable
30906
 E1000_TCTL_RTLCE1000_TCTL_RTLC 0x01000000 igb_defines.h Re-transmit on late collision
30907
 E1000_TCTL_NRTUE1000_TCTL_NRTU 0x02000000 igb_defines.h No Re-transmit on underrun
30908
 E1000_TCTL_MULRE1000_TCTL_MULR 0x10000000 igb_defines.h Multiple request support
30909
 E1000_TARC0_ENABLEE1000_TARC0_ENABLE 0x00000400 igb_defines.h Enable Tx Queue 0
30910
 E1000_SCTL_DISABLE_SERDES_LOOPBE1000_SCTL_DISABLE_SERDES_LOOPB 0x0400 igb_defines.h 　
30911
 E1000_RXCSUM_PCSS_MASKE1000_RXCSUM_PCSS_MASK 0x000000FF igb_defines.h Packet Checksum Start
30912
 E1000_RXCSUM_IPOFLE1000_RXCSUM_IPOFL 0x00000100 igb_defines.h IPv4 checksum offload
30913
 E1000_RXCSUM_TUOFLE1000_RXCSUM_TUOFL 0x00000200 igb_defines.h TCP / UDP checksum offload
30914
 E1000_RXCSUM_IPV6OFLE1000_RXCSUM_IPV6OFL 0x00000400 igb_defines.h IPv6 checksum offload
30915
 E1000_RXCSUM_CRCOFLE1000_RXCSUM_CRCOFL 0x00000800 igb_defines.h CRC32 offload enable
30916
 E1000_RXCSUM_IPPCSEE1000_RXCSUM_IPPCSE 0x00001000 igb_defines.h IP payload checksum enable
30917
 E1000_RXCSUM_PCSDE1000_RXCSUM_PCSD 0x00002000 igb_defines.h packet checksum disabled
30918
 E1000_RFCTL_ISCSI_DISE1000_RFCTL_ISCSI_DIS 0x00000001 igb_defines.h 　
30919
 E1000_RFCTL_ISCSI_DWC_MASKE1000_RFCTL_ISCSI_DWC_MASK 0x0000003E igb_defines.h 　
30920
 E1000_RFCTL_ISCSI_DWC_SHIFTE1000_RFCTL_ISCSI_DWC_SHIFT 1 igb_defines.h 　
30921
 E1000_RFCTL_NFSW_DISE1000_RFCTL_NFSW_DIS 0x00000040 igb_defines.h 　
30922
 E1000_RFCTL_NFSR_DISE1000_RFCTL_NFSR_DIS 0x00000080 igb_defines.h 　
30923
 E1000_RFCTL_NFS_VER_MASKE1000_RFCTL_NFS_VER_MASK 0x00000300 igb_defines.h 　
30924
 E1000_RFCTL_NFS_VER_SHIFTE1000_RFCTL_NFS_VER_SHIFT 8 igb_defines.h 　
30925
 E1000_RFCTL_IPV6_DISE1000_RFCTL_IPV6_DIS 0x00000400 igb_defines.h 　
30926
 E1000_RFCTL_IPV6_XSUM_DISE1000_RFCTL_IPV6_XSUM_DIS 0x00000800 igb_defines.h 　
30927
 E1000_RFCTL_ACK_DISE1000_RFCTL_ACK_DIS 0x00001000 igb_defines.h 　
30928
 E1000_RFCTL_ACKD_DISE1000_RFCTL_ACKD_DIS 0x00002000 igb_defines.h 　
30929
 E1000_RFCTL_IPFRSP_DISE1000_RFCTL_IPFRSP_DIS 0x00004000 igb_defines.h 　
30930
 E1000_RFCTL_EXTENE1000_RFCTL_EXTEN 0x00008000 igb_defines.h 　
30931
 E1000_RFCTL_IPV6_EX_DISE1000_RFCTL_IPV6_EX_DIS 0x00010000 igb_defines.h 　
30932
 E1000_RFCTL_NEW_IPV6_EXT_DISE1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 igb_defines.h 　
30933
 E1000_RFCTL_LEFE1000_RFCTL_LEF 0x00040000 igb_defines.h 　
30934
 E1000_COLLISION_THRESHOLDE1000_COLLISION_THRESHOLD 15 igb_defines.h 　
30935
 E1000_CT_SHIFTE1000_CT_SHIFT 4 igb_defines.h 　
30936
 E1000_COLLISION_DISTANCEE1000_COLLISION_DISTANCE 63 igb_defines.h 　
30937
 E1000_COLD_SHIFTE1000_COLD_SHIFT 12 igb_defines.h 　
30938
 DEFAULT_82543_TIPG_IPGT_FIBERDEFAULT_82543_TIPG_IPGT_FIBER 9 igb_defines.h 　
30939
 DEFAULT_82543_TIPG_IPGT_COPPERDEFAULT_82543_TIPG_IPGT_COPPER 8 igb_defines.h 　
30940
 E1000_TIPG_IPGT_MASKE1000_TIPG_IPGT_MASK 0x000003FF igb_defines.h 　
30941
 E1000_TIPG_IPGR1_MASKE1000_TIPG_IPGR1_MASK 0x000FFC00 igb_defines.h 　
30942
 E1000_TIPG_IPGR2_MASKE1000_TIPG_IPGR2_MASK 0x3FF00000 igb_defines.h 　
30943
 DEFAULT_82543_TIPG_IPGR1DEFAULT_82543_TIPG_IPGR1 8 igb_defines.h 　
30944
 E1000_TIPG_IPGR1_SHIFTE1000_TIPG_IPGR1_SHIFT 10 igb_defines.h 　
30945
 DEFAULT_82543_TIPG_IPGR2DEFAULT_82543_TIPG_IPGR2 6 igb_defines.h 　
30946
 DEFAULT_80003ES2LAN_TIPG_IPGR2DEFAULT_80003ES2LAN_TIPG_IPGR2 7 igb_defines.h 　
30947
 E1000_TIPG_IPGR2_SHIFTE1000_TIPG_IPGR2_SHIFT 20 igb_defines.h 　
30948
 ETHERNET_IEEE_VLAN_TYPEETHERNET_IEEE_VLAN_TYPE 0x8100 igb_defines.h 802.3ac packet
30949
 ETHERNET_FCS_SIZEETHERNET_FCS_SIZE 4 igb_defines.h 　
30950
 MAX_JUMBO_FRAME_SIZEMAX_JUMBO_FRAME_SIZE 0x3F00 igb_defines.h 　
30951
 E1000_EXTCNF_CTRL_MDIO_SW_OWNERE1000_EXTCNF_CTRL_MDIO_SW_OWNER 0x00000020 igb_defines.h 　
30952
 E1000_EXTCNF_CTRL_LCD_WRITE_ENAE1000_EXTCNF_CTRL_LCD_WRITE_ENA 0x00000001 igb_defines.h 　
30953
 E1000_EXTCNF_CTRL_OEM_WRITE_ENAE1000_EXTCNF_CTRL_OEM_WRITE_ENA 0x00000008 igb_defines.h 　
30954
 E1000_EXTCNF_CTRL_SWFLAGE1000_EXTCNF_CTRL_SWFLAG 0x00000020 igb_defines.h 　
30955
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 0x00FF0000 igb_defines.h 　
30956
 E1000_EXTCNF_SIZE_EXT_PCIE_LENGE1000_EXTCNF_SIZE_EXT_PCIE_LENG 16 igb_defines.h 　
30957
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 0x0FFF0000 igb_defines.h 　
30958
 E1000_EXTCNF_CTRL_EXT_CNF_POINTE1000_EXTCNF_CTRL_EXT_CNF_POINT 16 igb_defines.h 　
30959
 E1000_PHY_CTRL_SPD_ENE1000_PHY_CTRL_SPD_EN 0x00000001 igb_defines.h 　
30960
 E1000_PHY_CTRL_D0A_LPLUE1000_PHY_CTRL_D0A_LPLU 0x00000002 igb_defines.h 　
30961
 E1000_PHY_CTRL_NOND0A_LPLUE1000_PHY_CTRL_NOND0A_LPLU 0x00000004 igb_defines.h 　
30962
 E1000_PHY_CTRL_NOND0A_GBE_DISABE1000_PHY_CTRL_NOND0A_GBE_DISAB 0x00000008 igb_defines.h 　
30963
 E1000_PHY_CTRL_GBE_DISABLEE1000_PHY_CTRL_GBE_DISABLE 0x00000040 igb_defines.h 　
30964
 E1000_KABGTXD_BGSQLBIASE1000_KABGTXD_BGSQLBIAS 0x00050000 igb_defines.h 　
30965
 E1000_PBA_6KE1000_PBA_6K 0x0006 igb_defines.h 6KB
30966
 E1000_PBA_8KE1000_PBA_8K 0x0008 igb_defines.h 8KB
30967
 E1000_PBA_10KE1000_PBA_10K 0x000A igb_defines.h 10KB
30968
 E1000_PBA_12KE1000_PBA_12K 0x000C igb_defines.h 12KB
30969
 E1000_PBA_14KE1000_PBA_14K 0x000E igb_defines.h 14KB
30970
 E1000_PBA_16KE1000_PBA_16K 0x0010 igb_defines.h 16KB
30971
 E1000_PBA_18KE1000_PBA_18K 0x0012 igb_defines.h 　
30972
 E1000_PBA_20KE1000_PBA_20K 0x0014 igb_defines.h 　
30973
 E1000_PBA_22KE1000_PBA_22K 0x0016 igb_defines.h 　
30974
 E1000_PBA_24KE1000_PBA_24K 0x0018 igb_defines.h 　
30975
 E1000_PBA_26KE1000_PBA_26K 0x001A igb_defines.h 　
30976
 E1000_PBA_30KE1000_PBA_30K 0x001E igb_defines.h 　
30977
 E1000_PBA_32KE1000_PBA_32K 0x0020 igb_defines.h 　
30978
 E1000_PBA_34KE1000_PBA_34K 0x0022 igb_defines.h 　
30979
 E1000_PBA_35KE1000_PBA_35K 0x0023 igb_defines.h 　
30980
 E1000_PBA_38KE1000_PBA_38K 0x0026 igb_defines.h 　
30981
 E1000_PBA_40KE1000_PBA_40K 0x0028 igb_defines.h 　
30982
 E1000_PBA_48KE1000_PBA_48K 0x0030 igb_defines.h 48KB
30983
 E1000_PBA_64KE1000_PBA_64K 0x0040 igb_defines.h 64KB
30984
 E1000_PBS_16KE1000_PBS_16K E1000_PBA_16K igb_defines.h 　
30985
 E1000_PBS_24KE1000_PBS_24K E1000_PBA_24K igb_defines.h 　
30986
 IFS_MAXIFS_MAX 80 igb_defines.h 　
30987
 IFS_MINIFS_MIN 40 igb_defines.h 　
30988
 IFS_RATIOIFS_RATIO 4 igb_defines.h 　
30989
 IFS_STEPIFS_STEP 10 igb_defines.h 　
30990
 MIN_NUM_XMITSMIN_NUM_XMITS 1000 igb_defines.h 　
30991
 E1000_SWSM_SMBIE1000_SWSM_SMBI 0x00000001 igb_defines.h Driver Semaphore bit
30992
 E1000_SWSM_SWESMBIE1000_SWSM_SWESMBI 0x00000002 igb_defines.h FW Semaphore bit
30993
 E1000_SWSM_WMNGE1000_SWSM_WMNG 0x00000004 igb_defines.h Wake MNG Clock
30994
 E1000_SWSM_DRV_LOADE1000_SWSM_DRV_LOAD 0x00000008 igb_defines.h Driver Loaded Bit
30995
 E1000_SWSM2_LOCKE1000_SWSM2_LOCK 0x00000002 igb_defines.h Secondary driver semaphore bit
30996
 E1000_ICR_TXDWE1000_ICR_TXDW 0x00000001 igb_defines.h Transmit desc written back
30997
 E1000_ICR_TXQEE1000_ICR_TXQE 0x00000002 igb_defines.h Transmit Queue empty
30998
 E1000_ICR_LSCE1000_ICR_LSC 0x00000004 igb_defines.h Link Status Change
30999
 E1000_ICR_RXSEQE1000_ICR_RXSEQ 0x00000008 igb_defines.h rx sequence error
31000
 E1000_ICR_RXDMT0E1000_ICR_RXDMT0 0x00000010 igb_defines.h rx desc min. threshold (0)
31001
 E1000_ICR_RXOE1000_ICR_RXO 0x00000040 igb_defines.h rx overrun
31002
 E1000_ICR_RXT0E1000_ICR_RXT0 0x00000080 igb_defines.h rx timer intr (ring 0)
31003
 E1000_ICR_VMMBE1000_ICR_VMMB 0x00000100 igb_defines.h VM MB event
31004
 E1000_ICR_MDACE1000_ICR_MDAC 0x00000200 igb_defines.h MDIO access complete
31005
 E1000_ICR_RXCFGE1000_ICR_RXCFG 0x00000400 igb_defines.h Rx /c/ ordered set
31006
 E1000_ICR_GPI_EN0E1000_ICR_GPI_EN0 0x00000800 igb_defines.h GP Int 0
31007
 E1000_ICR_GPI_EN1E1000_ICR_GPI_EN1 0x00001000 igb_defines.h GP Int 1
31008
 E1000_ICR_GPI_EN2E1000_ICR_GPI_EN2 0x00002000 igb_defines.h GP Int 2
31009
 E1000_ICR_GPI_EN3E1000_ICR_GPI_EN3 0x00004000 igb_defines.h GP Int 3
31010
 E1000_ICR_TXD_LOWE1000_ICR_TXD_LOW 0x00008000 igb_defines.h 　
31011
 E1000_ICR_SRPDE1000_ICR_SRPD 0x00010000 igb_defines.h 　
31012
 E1000_ICR_ACKE1000_ICR_ACK 0x00020000 igb_defines.h Receive Ack frame
31013
 E1000_ICR_MNGE1000_ICR_MNG 0x00040000 igb_defines.h Manageability event
31014
 E1000_ICR_DOCKE1000_ICR_DOCK 0x00080000 igb_defines.h Dock/Undock
31015
 E1000_ICR_INT_ASSERTEDE1000_ICR_INT_ASSERTED 0x80000000 igb_defines.h If this bit asserted, the driver
31016
 E1000_ICR_RXD_FIFO_PAR0E1000_ICR_RXD_FIFO_PAR0 0x00100000 igb_defines.h Q0 Rx desc FIFO parity error
31017
 E1000_ICR_TXD_FIFO_PAR0E1000_ICR_TXD_FIFO_PAR0 0x00200000 igb_defines.h Q0 Tx desc FIFO parity error
31018
 E1000_ICR_HOST_ARB_PARE1000_ICR_HOST_ARB_PAR 0x00400000 igb_defines.h host arb read buffer parity err
31019
 E1000_ICR_PB_PARE1000_ICR_PB_PAR 0x00800000 igb_defines.h packet buffer parity error
31020
 E1000_ICR_RXD_FIFO_PAR1E1000_ICR_RXD_FIFO_PAR1 0x01000000 igb_defines.h Q1 Rx desc FIFO parity error
31021
 E1000_ICR_TXD_FIFO_PAR1E1000_ICR_TXD_FIFO_PAR1 0x02000000 igb_defines.h Q1 Tx desc FIFO parity error
31022
 E1000_ICR_ALL_PARITYE1000_ICR_ALL_PARITY 0x03F00000 igb_defines.h all parity error bits
31023
 E1000_ICR_DSWE1000_ICR_DSW 0x00000020 igb_defines.h FW changed the status of DISSW
31024
 E1000_ICR_PHYINTE1000_ICR_PHYINT 0x00001000 igb_defines.h LAN connected device generates
31025
 E1000_ICR_DOUTSYNCE1000_ICR_DOUTSYNC 0x10000000 igb_defines.h NIC DMA out of sync
31026
 E1000_ICR_EPRSTE1000_ICR_EPRST 0x00100000 igb_defines.h ME hardware reset occurs
31027
 E1000_EICR_RX_QUEUE0E1000_EICR_RX_QUEUE0 0x00000001 igb_defines.h Rx Queue 0 Interrupt
31028
 E1000_EICR_RX_QUEUE1E1000_EICR_RX_QUEUE1 0x00000002 igb_defines.h Rx Queue 1 Interrupt
31029
 E1000_EICR_RX_QUEUE2E1000_EICR_RX_QUEUE2 0x00000004 igb_defines.h Rx Queue 2 Interrupt
31030
 E1000_EICR_RX_QUEUE3E1000_EICR_RX_QUEUE3 0x00000008 igb_defines.h Rx Queue 3 Interrupt
31031
 E1000_EICR_TX_QUEUE0E1000_EICR_TX_QUEUE0 0x00000100 igb_defines.h Tx Queue 0 Interrupt
31032
 E1000_EICR_TX_QUEUE1E1000_EICR_TX_QUEUE1 0x00000200 igb_defines.h Tx Queue 1 Interrupt
31033
 E1000_EICR_TX_QUEUE2E1000_EICR_TX_QUEUE2 0x00000400 igb_defines.h Tx Queue 2 Interrupt
31034
 E1000_EICR_TX_QUEUE3E1000_EICR_TX_QUEUE3 0x00000800 igb_defines.h Tx Queue 3 Interrupt
31035
 E1000_EICR_TCP_TIMERE1000_EICR_TCP_TIMER 0x40000000 igb_defines.h TCP Timer
31036
 E1000_EICR_OTHERE1000_EICR_OTHER 0x80000000 igb_defines.h Interrupt Cause Active
31037
 E1000_TCPTIMER_KSE1000_TCPTIMER_KS 0x00000100 igb_defines.h KickStart
31038
 E1000_TCPTIMER_COUNT_ENABLEE1000_TCPTIMER_COUNT_ENABLE 0x00000200 igb_defines.h Count Enable
31039
 E1000_TCPTIMER_COUNT_FINISHE1000_TCPTIMER_COUNT_FINISH 0x00000400 igb_defines.h Count finish
31040
 E1000_TCPTIMER_LOOPE1000_TCPTIMER_LOOP 0x00000800 igb_defines.h Loop
31041
 POLL_IMS_ENABLE_MASKPOLL_IMS_ENABLE_MASK ( \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ) igb_defines.h 　
31042
 IMS_ENABLE_MASKIMS_ENABLE_MASK ( \ E1000_IMS_RXT0 | \ E1000_IMS_TXDW | \ E1000_IMS_RXDMT0 | \ E1000_IMS_RXSEQ | \ E1000_IMS_LSC) igb_defines.h 　
31043
 E1000_IMS_TXDWE1000_IMS_TXDW E1000_ICR_TXDW igb_defines.h Tx desc written back
31044
 E1000_IMS_TXQEE1000_IMS_TXQE E1000_ICR_TXQE igb_defines.h Transmit Queue empty
31045
 E1000_IMS_LSCE1000_IMS_LSC E1000_ICR_LSC igb_defines.h Link Status Change
31046
 E1000_IMS_VMMBE1000_IMS_VMMB E1000_ICR_VMMB igb_defines.h Mail box activity
31047
 E1000_IMS_RXSEQE1000_IMS_RXSEQ E1000_ICR_RXSEQ igb_defines.h rx sequence error
31048
 E1000_IMS_RXDMT0E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 igb_defines.h rx desc min. threshold
31049
 E1000_IMS_RXOE1000_IMS_RXO E1000_ICR_RXO igb_defines.h rx overrun
31050
 E1000_IMS_RXT0E1000_IMS_RXT0 E1000_ICR_RXT0 igb_defines.h rx timer intr
31051
 E1000_IMS_MDACE1000_IMS_MDAC E1000_ICR_MDAC igb_defines.h MDIO access complete
31052
 E1000_IMS_RXCFGE1000_IMS_RXCFG E1000_ICR_RXCFG igb_defines.h Rx /c/ ordered set
31053
 E1000_IMS_GPI_EN0E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 igb_defines.h GP Int 0
31054
 E1000_IMS_GPI_EN1E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 igb_defines.h GP Int 1
31055
 E1000_IMS_GPI_EN2E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 igb_defines.h GP Int 2
31056
 E1000_IMS_GPI_EN3E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 igb_defines.h GP Int 3
31057
 E1000_IMS_TXD_LOWE1000_IMS_TXD_LOW E1000_ICR_TXD_LOW igb_defines.h 　
31058
 E1000_IMS_SRPDE1000_IMS_SRPD E1000_ICR_SRPD igb_defines.h 　
31059
 E1000_IMS_ACKE1000_IMS_ACK E1000_ICR_ACK igb_defines.h Receive Ack frame
31060
 E1000_IMS_MNGE1000_IMS_MNG E1000_ICR_MNG igb_defines.h Manageability event
31061
 E1000_IMS_DOCKE1000_IMS_DOCK E1000_ICR_DOCK igb_defines.h Dock/Undock
31062
 E1000_IMS_RXD_FIFO_PAR0E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 igb_defines.h Q0 Rx desc FIFO
31063
 E1000_IMS_TXD_FIFO_PAR0E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 igb_defines.h Q0 Tx desc FIFO
31064
 E1000_IMS_HOST_ARB_PARE1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR igb_defines.h host arb read buffer
31065
 E1000_IMS_PB_PARE1000_IMS_PB_PAR E1000_ICR_PB_PAR igb_defines.h packet buffer parity
31066
 E1000_IMS_RXD_FIFO_PAR1E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 igb_defines.h Q1 Rx desc FIFO
31067
 E1000_IMS_TXD_FIFO_PAR1E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 igb_defines.h Q1 Tx desc FIFO
31068
 E1000_IMS_DSWE1000_IMS_DSW E1000_ICR_DSW igb_defines.h 　
31069
 E1000_IMS_PHYINTE1000_IMS_PHYINT E1000_ICR_PHYINT igb_defines.h 　
31070
 E1000_IMS_DOUTSYNCE1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC igb_defines.h NIC DMA out of sync
31071
 E1000_IMS_EPRSTE1000_IMS_EPRST E1000_ICR_EPRST igb_defines.h 　
31072
 E1000_EIMS_RX_QUEUE0E1000_EIMS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 igb_defines.h Rx Queue 0 Interrupt
31073
 E1000_EIMS_RX_QUEUE1E1000_EIMS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 igb_defines.h Rx Queue 1 Interrupt
31074
 E1000_EIMS_RX_QUEUE2E1000_EIMS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 igb_defines.h Rx Queue 2 Interrupt
31075
 E1000_EIMS_RX_QUEUE3E1000_EIMS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 igb_defines.h Rx Queue 3 Interrupt
31076
 E1000_EIMS_TX_QUEUE0E1000_EIMS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 igb_defines.h Tx Queue 0 Interrupt
31077
 E1000_EIMS_TX_QUEUE1E1000_EIMS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 igb_defines.h Tx Queue 1 Interrupt
31078
 E1000_EIMS_TX_QUEUE2E1000_EIMS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 igb_defines.h Tx Queue 2 Interrupt
31079
 E1000_EIMS_TX_QUEUE3E1000_EIMS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 igb_defines.h Tx Queue 3 Interrupt
31080
 E1000_EIMS_TCP_TIMERE1000_EIMS_TCP_TIMER E1000_EICR_TCP_TIMER igb_defines.h TCP Timer
31081
 E1000_EIMS_OTHERE1000_EIMS_OTHER E1000_EICR_OTHER igb_defines.h Interrupt Cause Active
31082
 E1000_ICS_TXDWE1000_ICS_TXDW E1000_ICR_TXDW igb_defines.h Tx desc written back
31083
 E1000_ICS_TXQEE1000_ICS_TXQE E1000_ICR_TXQE igb_defines.h Transmit Queue empty
31084
 E1000_ICS_LSCE1000_ICS_LSC E1000_ICR_LSC igb_defines.h Link Status Change
31085
 E1000_ICS_RXSEQE1000_ICS_RXSEQ E1000_ICR_RXSEQ igb_defines.h rx sequence error
31086
 E1000_ICS_RXDMT0E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 igb_defines.h rx desc min. threshold
31087
 E1000_ICS_RXOE1000_ICS_RXO E1000_ICR_RXO igb_defines.h rx overrun
31088
 E1000_ICS_RXT0E1000_ICS_RXT0 E1000_ICR_RXT0 igb_defines.h rx timer intr
31089
 E1000_ICS_MDACE1000_ICS_MDAC E1000_ICR_MDAC igb_defines.h MDIO access complete
31090
 E1000_ICS_RXCFGE1000_ICS_RXCFG E1000_ICR_RXCFG igb_defines.h Rx /c/ ordered set
31091
 E1000_ICS_GPI_EN0E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 igb_defines.h GP Int 0
31092
 E1000_ICS_GPI_EN1E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 igb_defines.h GP Int 1
31093
 E1000_ICS_GPI_EN2E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 igb_defines.h GP Int 2
31094
 E1000_ICS_GPI_EN3E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 igb_defines.h GP Int 3
31095
 E1000_ICS_TXD_LOWE1000_ICS_TXD_LOW E1000_ICR_TXD_LOW igb_defines.h 　
31096
 E1000_ICS_SRPDE1000_ICS_SRPD E1000_ICR_SRPD igb_defines.h 　
31097
 E1000_ICS_ACKE1000_ICS_ACK E1000_ICR_ACK igb_defines.h Receive Ack frame
31098
 E1000_ICS_MNGE1000_ICS_MNG E1000_ICR_MNG igb_defines.h Manageability event
31099
 E1000_ICS_DOCKE1000_ICS_DOCK E1000_ICR_DOCK igb_defines.h Dock/Undock
31100
 E1000_ICS_RXD_FIFO_PAR0E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 igb_defines.h Q0 Rx desc FIFO
31101
 E1000_ICS_TXD_FIFO_PAR0E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 igb_defines.h Q0 Tx desc FIFO
31102
 E1000_ICS_HOST_ARB_PARE1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR igb_defines.h host arb read buffer
31103
 E1000_ICS_PB_PARE1000_ICS_PB_PAR E1000_ICR_PB_PAR igb_defines.h packet buffer parity
31104
 E1000_ICS_RXD_FIFO_PAR1E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 igb_defines.h Q1 Rx desc FIFO
31105
 E1000_ICS_TXD_FIFO_PAR1E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 igb_defines.h Q1 Tx desc FIFO
31106
 E1000_ICS_DSWE1000_ICS_DSW E1000_ICR_DSW igb_defines.h 　
31107
 E1000_ICS_DOUTSYNCE1000_ICS_DOUTSYNC E1000_ICR_DOUTSYNC igb_defines.h NIC DMA out of sync
31108
 E1000_ICS_PHYINTE1000_ICS_PHYINT E1000_ICR_PHYINT igb_defines.h 　
31109
 E1000_ICS_EPRSTE1000_ICS_EPRST E1000_ICR_EPRST igb_defines.h 　
31110
 E1000_EICS_RX_QUEUE0E1000_EICS_RX_QUEUE0 E1000_EICR_RX_QUEUE0 igb_defines.h Rx Queue 0 Interrupt
31111
 E1000_EICS_RX_QUEUE1E1000_EICS_RX_QUEUE1 E1000_EICR_RX_QUEUE1 igb_defines.h Rx Queue 1 Interrupt
31112
 E1000_EICS_RX_QUEUE2E1000_EICS_RX_QUEUE2 E1000_EICR_RX_QUEUE2 igb_defines.h Rx Queue 2 Interrupt
31113
 E1000_EICS_RX_QUEUE3E1000_EICS_RX_QUEUE3 E1000_EICR_RX_QUEUE3 igb_defines.h Rx Queue 3 Interrupt
31114
 E1000_EICS_TX_QUEUE0E1000_EICS_TX_QUEUE0 E1000_EICR_TX_QUEUE0 igb_defines.h Tx Queue 0 Interrupt
31115
 E1000_EICS_TX_QUEUE1E1000_EICS_TX_QUEUE1 E1000_EICR_TX_QUEUE1 igb_defines.h Tx Queue 1 Interrupt
31116
 E1000_EICS_TX_QUEUE2E1000_EICS_TX_QUEUE2 E1000_EICR_TX_QUEUE2 igb_defines.h Tx Queue 2 Interrupt
31117
 E1000_EICS_TX_QUEUE3E1000_EICS_TX_QUEUE3 E1000_EICR_TX_QUEUE3 igb_defines.h Tx Queue 3 Interrupt
31118
 E1000_EICS_TCP_TIMERE1000_EICS_TCP_TIMER E1000_EICR_TCP_TIMER igb_defines.h TCP Timer
31119
 E1000_EICS_OTHERE1000_EICS_OTHER E1000_EICR_OTHER igb_defines.h Interrupt Cause Active
31120
 E1000_EITR_ITR_INT_MASKE1000_EITR_ITR_INT_MASK 0x0000FFFF igb_defines.h 　
31121
 E1000_TXDCTL_PTHRESHE1000_TXDCTL_PTHRESH 0x0000003F igb_defines.h TXDCTL Prefetch Threshold
31122
 E1000_TXDCTL_HTHRESHE1000_TXDCTL_HTHRESH 0x00003F00 igb_defines.h TXDCTL Host Threshold
31123
 E1000_TXDCTL_WTHRESHE1000_TXDCTL_WTHRESH 0x003F0000 igb_defines.h TXDCTL Writeback Threshold
31124
 E1000_TXDCTL_GRANE1000_TXDCTL_GRAN 0x01000000 igb_defines.h TXDCTL Granularity
31125
 E1000_TXDCTL_LWTHRESHE1000_TXDCTL_LWTHRESH 0xFE000000 igb_defines.h TXDCTL Low Threshold
31126
 E1000_TXDCTL_FULL_TX_DESC_WBE1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 igb_defines.h GRAN=1, WTHRESH=1
31127
 E1000_TXDCTL_MAX_TX_DESC_PREFETE1000_TXDCTL_MAX_TX_DESC_PREFET 0x0100001F igb_defines.h GRAN=1, PTHRESH=31
31128
 E1000_TXDCTL_COUNT_DESCE1000_TXDCTL_COUNT_DESC 0x00400000 igb_defines.h 　
31129
 FLOW_CONTROL_ADDRESS_LOWFLOW_CONTROL_ADDRESS_LOW 0x00C28001 igb_defines.h 　
31130
 FLOW_CONTROL_ADDRESS_HIGHFLOW_CONTROL_ADDRESS_HIGH 0x00000100 igb_defines.h 　
31131
 FLOW_CONTROL_TYPEFLOW_CONTROL_TYPE 0x8808 igb_defines.h 　
31132
 VLAN_TAG_SIZEVLAN_TAG_SIZE 4 igb_defines.h 802.3ac tag (not DMA'd)
31133
 E1000_VLAN_FILTER_TBL_SIZEE1000_VLAN_FILTER_TBL_SIZE 128 igb_defines.h VLAN Filter Table (4096 bits)
31134
 E1000_RAR_ENTRIESE1000_RAR_ENTRIES 15 igb_defines.h 　
31135
 E1000_RAH_AVE1000_RAH_AV 0x80000000 igb_defines.h Receive descriptor valid
31136
 E1000_RAL_MAC_ADDR_LENE1000_RAL_MAC_ADDR_LEN 4 igb_defines.h 　
31137
 E1000_RAH_MAC_ADDR_LENE1000_RAH_MAC_ADDR_LEN 2 igb_defines.h 　
31138
 E1000_RAH_POOL_MASKE1000_RAH_POOL_MASK 0x03FC0000 igb_defines.h 　
31139
 E1000_RAH_POOL_1E1000_RAH_POOL_1 0x00040000 igb_defines.h 　
31140
 E1000_SUCCESSE1000_SUCCESS 0 igb_defines.h 　
31141
 E1000_ERR_NVME1000_ERR_NVM 1 igb_defines.h 　
31142
 E1000_ERR_PHYE1000_ERR_PHY 2 igb_defines.h 　
31143
 E1000_ERR_CONFIGE1000_ERR_CONFIG 3 igb_defines.h 　
31144
 E1000_ERR_PARAME1000_ERR_PARAM 4 igb_defines.h 　
31145
 E1000_ERR_MAC_INITE1000_ERR_MAC_INIT 5 igb_defines.h 　
31146
 E1000_ERR_PHY_TYPEE1000_ERR_PHY_TYPE 6 igb_defines.h 　
31147
 E1000_ERR_RESETE1000_ERR_RESET 9 igb_defines.h 　
31148
 E1000_ERR_MASTER_REQUESTS_PENDIE1000_ERR_MASTER_REQUESTS_PENDI 10 igb_defines.h 　
31149
 E1000_ERR_HOST_INTERFACE_COMMANE1000_ERR_HOST_INTERFACE_COMMAN 11 igb_defines.h 　
31150
 E1000_BLK_PHY_RESETE1000_BLK_PHY_RESET 12 igb_defines.h 　
31151
 E1000_ERR_SWFW_SYNCE1000_ERR_SWFW_SYNC 13 igb_defines.h 　
31152
 E1000_NOT_IMPLEMENTEDE1000_NOT_IMPLEMENTED 14 igb_defines.h 　
31153
 E1000_ERR_MBXE1000_ERR_MBX 15 igb_defines.h 　
31154
 FIBER_LINK_UP_LIMITFIBER_LINK_UP_LIMIT 50 igb_defines.h 　
31155
 COPPER_LINK_UP_LIMITCOPPER_LINK_UP_LIMIT 10 igb_defines.h 　
31156
 PHY_AUTO_NEG_LIMITPHY_AUTO_NEG_LIMIT 45 igb_defines.h 　
31157
 PHY_FORCE_LIMITPHY_FORCE_LIMIT 20 igb_defines.h 　
31158
 MASTER_DISABLE_TIMEOUTMASTER_DISABLE_TIMEOUT 800 igb_defines.h 　
31159
 PHY_CFG_TIMEOUTPHY_CFG_TIMEOUT 100 igb_defines.h 　
31160
 MDIO_OWNERSHIP_TIMEOUTMDIO_OWNERSHIP_TIMEOUT 10 igb_defines.h 　
31161
 AUTO_READ_DONE_TIMEOUTAUTO_READ_DONE_TIMEOUT 10 igb_defines.h 　
31162
 E1000_FCRTH_RTHE1000_FCRTH_RTH 0x0000FFF8 igb_defines.h Mask Bits[15:3] for RTH
31163
 E1000_FCRTH_XFCEE1000_FCRTH_XFCE 0x80000000 igb_defines.h External Flow Control Enable
31164
 E1000_FCRTL_RTLE1000_FCRTL_RTL 0x0000FFF8 igb_defines.h Mask Bits[15:3] for RTL
31165
 E1000_FCRTL_XONEE1000_FCRTL_XONE 0x80000000 igb_defines.h Enable XON frame transmission
31166
 E1000_TXCW_FDE1000_TXCW_FD 0x00000020 igb_defines.h TXCW full duplex
31167
 E1000_TXCW_HDE1000_TXCW_HD 0x00000040 igb_defines.h TXCW half duplex
31168
 E1000_TXCW_PAUSEE1000_TXCW_PAUSE 0x00000080 igb_defines.h TXCW sym pause request
31169
 E1000_TXCW_ASM_DIRE1000_TXCW_ASM_DIR 0x00000100 igb_defines.h TXCW astm pause direction
31170
 E1000_TXCW_PAUSE_MASKE1000_TXCW_PAUSE_MASK 0x00000180 igb_defines.h TXCW pause request mask
31171
 E1000_TXCW_RFE1000_TXCW_RF 0x00003000 igb_defines.h TXCW remote fault
31172
 E1000_TXCW_NPE1000_TXCW_NP 0x00008000 igb_defines.h TXCW next page
31173
 E1000_TXCW_CWE1000_TXCW_CW 0x0000ffff igb_defines.h TxConfigWord mask
31174
 E1000_TXCW_TXCE1000_TXCW_TXC 0x40000000 igb_defines.h Transmit Config control
31175
 E1000_TXCW_ANEE1000_TXCW_ANE 0x80000000 igb_defines.h Auto-neg enable
31176
 E1000_RXCW_CWE1000_RXCW_CW 0x0000ffff igb_defines.h RxConfigWord mask
31177
 E1000_RXCW_NCE1000_RXCW_NC 0x04000000 igb_defines.h Receive config no carrier
31178
 E1000_RXCW_IVE1000_RXCW_IV 0x08000000 igb_defines.h Receive config invalid
31179
 E1000_RXCW_CCE1000_RXCW_CC 0x10000000 igb_defines.h Receive config change
31180
 E1000_RXCW_CE1000_RXCW_C 0x20000000 igb_defines.h Receive config
31181
 E1000_RXCW_SYNCHE1000_RXCW_SYNCH 0x40000000 igb_defines.h Receive config synch
31182
 E1000_RXCW_ANCE1000_RXCW_ANC 0x80000000 igb_defines.h Auto-neg complete
31183
 E1000_TSYNCTXCTL_VALIDE1000_TSYNCTXCTL_VALID 0x00000001 igb_defines.h tx timestamp valid
31184
 E1000_TSYNCTXCTL_ENABLEDE1000_TSYNCTXCTL_ENABLED 0x00000010 igb_defines.h enable tx timestampping
31185
 E1000_TSYNCRXCTL_VALIDE1000_TSYNCRXCTL_VALID 0x00000001 igb_defines.h rx timestamp valid
31186
 E1000_TSYNCRXCTL_TYPE_MASKE1000_TSYNCRXCTL_TYPE_MASK 0x0000000E igb_defines.h rx type mask
31187
 E1000_TSYNCRXCTL_TYPE_L2_V2E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 igb_defines.h 　
31188
 E1000_TSYNCRXCTL_TYPE_L4_V1E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 igb_defines.h 　
31189
 E1000_TSYNCRXCTL_TYPE_L2_L4_V2E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 igb_defines.h 　
31190
 E1000_TSYNCRXCTL_TYPE_ALLE1000_TSYNCRXCTL_TYPE_ALL 0x08 igb_defines.h 　
31191
 E1000_TSYNCRXCTL_TYPE_EVENT_V2E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A igb_defines.h 　
31192
 E1000_TSYNCRXCTL_ENABLEDE1000_TSYNCRXCTL_ENABLED 0x00000010 igb_defines.h enable rx timestampping
31193
 E1000_TSYNCRXCFG_PTP_V1_CTRLT_ME1000_TSYNCRXCFG_PTP_V1_CTRLT_M 0x000000FF igb_defines.h 　
31194
 E1000_TSYNCRXCFG_PTP_V1_SYNC_MEE1000_TSYNCRXCFG_PTP_V1_SYNC_ME 0x00 igb_defines.h 　
31195
 E1000_TSYNCRXCFG_PTP_V1_DELAY_RE1000_TSYNCRXCFG_PTP_V1_DELAY_R 0x01 igb_defines.h 　
31196
 E1000_TSYNCRXCFG_PTP_V1_FOLLOWUE1000_TSYNCRXCFG_PTP_V1_FOLLOWU 0x02 igb_defines.h 　
31197
 E1000_TSYNCRXCFG_PTP_V1_DELAY_RE1000_TSYNCRXCFG_PTP_V1_DELAY_R 0x03 igb_defines.h 　
31198
 E1000_TSYNCRXCFG_PTP_V1_MANAGEME1000_TSYNCRXCFG_PTP_V1_MANAGEM 0x04 igb_defines.h 　
31199
 E1000_TSYNCRXCFG_PTP_V2_MSGID_ME1000_TSYNCRXCFG_PTP_V2_MSGID_M 0x00000F00 igb_defines.h 　
31200
 E1000_TSYNCRXCFG_PTP_V2_SYNC_MEE1000_TSYNCRXCFG_PTP_V2_SYNC_ME 0x0000 igb_defines.h 　
31201
 E1000_TSYNCRXCFG_PTP_V2_DELAY_RE1000_TSYNCRXCFG_PTP_V2_DELAY_R 0x0100 igb_defines.h 　
31202
 E1000_TSYNCRXCFG_PTP_V2_PATH_DEE1000_TSYNCRXCFG_PTP_V2_PATH_DE 0x0200 igb_defines.h 　
31203
 E1000_TSYNCRXCFG_PTP_V2_PATH_DEE1000_TSYNCRXCFG_PTP_V2_PATH_DE 0x0300 igb_defines.h 　
31204
 E1000_TSYNCRXCFG_PTP_V2_FOLLOWUE1000_TSYNCRXCFG_PTP_V2_FOLLOWU 0x0800 igb_defines.h 　
31205
 E1000_TSYNCRXCFG_PTP_V2_DELAY_RE1000_TSYNCRXCFG_PTP_V2_DELAY_R 0x0900 igb_defines.h 　
31206
 E1000_TSYNCRXCFG_PTP_V2_PATH_DEE1000_TSYNCRXCFG_PTP_V2_PATH_DE 0x0A00 igb_defines.h 　
31207
 E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE1000_TSYNCRXCFG_PTP_V2_ANNOUNC 0x0B00 igb_defines.h 　
31208
 E1000_TSYNCRXCFG_PTP_V2_SIGNALLE1000_TSYNCRXCFG_PTP_V2_SIGNALL 0x0C00 igb_defines.h 　
31209
 E1000_TSYNCRXCFG_PTP_V2_MANAGEME1000_TSYNCRXCFG_PTP_V2_MANAGEM 0x0D00 igb_defines.h 　
31210
 E1000_TIMINCA_16NS_SHIFTE1000_TIMINCA_16NS_SHIFT 24 igb_defines.h 　
31211
 E1000_GCR_RXD_NO_SNOOPE1000_GCR_RXD_NO_SNOOP 0x00000001 igb_defines.h 　
31212
 E1000_GCR_RXDSCW_NO_SNOOPE1000_GCR_RXDSCW_NO_SNOOP 0x00000002 igb_defines.h 　
31213
 E1000_GCR_RXDSCR_NO_SNOOPE1000_GCR_RXDSCR_NO_SNOOP 0x00000004 igb_defines.h 　
31214
 E1000_GCR_TXD_NO_SNOOPE1000_GCR_TXD_NO_SNOOP 0x00000008 igb_defines.h 　
31215
 E1000_GCR_TXDSCW_NO_SNOOPE1000_GCR_TXDSCW_NO_SNOOP 0x00000010 igb_defines.h 　
31216
 E1000_GCR_TXDSCR_NO_SNOOPE1000_GCR_TXDSCR_NO_SNOOP 0x00000020 igb_defines.h 　
31217
 E1000_GCR_CMPL_TMOUT_MASKE1000_GCR_CMPL_TMOUT_MASK 0x0000F000 igb_defines.h 　
31218
 E1000_GCR_CMPL_TMOUT_10msE1000_GCR_CMPL_TMOUT_10ms 0x00001000 igb_defines.h 　
31219
 E1000_GCR_CMPL_TMOUT_RESENDE1000_GCR_CMPL_TMOUT_RESEND 0x00010000 igb_defines.h 　
31220
 E1000_GCR_CAP_VER2E1000_GCR_CAP_VER2 0x00040000 igb_defines.h 　
31221
 PCIE_NO_SNOOP_ALLPCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ E1000_GCR_RXDSCW_NO_SNOOP | \ E1000_GCR_RXDSCR_NO_SNOOP | \ E1000_GCR_TXD_NO_SNOO igb_defines.h 　
31222
 MII_CR_SPEED_SELECT_MSBMII_CR_SPEED_SELECT_MSB 0x0040 igb_defines.h bits 6,13: 10=1000, 01=100, 00=10
31223
 MII_CR_COLL_TEST_ENABLEMII_CR_COLL_TEST_ENABLE 0x0080 igb_defines.h Collision test enable
31224
 MII_CR_FULL_DUPLEXMII_CR_FULL_DUPLEX 0x0100 igb_defines.h FDX =1, half duplex =0
31225
 MII_CR_RESTART_AUTO_NEGMII_CR_RESTART_AUTO_NEG 0x0200 igb_defines.h Restart auto negotiation
31226
 MII_CR_ISOLATEMII_CR_ISOLATE 0x0400 igb_defines.h Isolate PHY from MII
31227
 MII_CR_POWER_DOWNMII_CR_POWER_DOWN 0x0800 igb_defines.h Power down
31228
 MII_CR_AUTO_NEG_ENMII_CR_AUTO_NEG_EN 0x1000 igb_defines.h Auto Neg Enable
31229
 MII_CR_SPEED_SELECT_LSBMII_CR_SPEED_SELECT_LSB 0x2000 igb_defines.h bits 6,13: 10=1000, 01=100, 00=10
31230
 MII_CR_LOOPBACKMII_CR_LOOPBACK 0x4000 igb_defines.h 0 = normal, 1 = loopback
31231
 MII_CR_RESETMII_CR_RESET 0x8000 igb_defines.h 0 = normal, 1 = PHY reset
31232
 MII_CR_SPEED_1000MII_CR_SPEED_1000 0x0040 igb_defines.h 　
31233
 MII_CR_SPEED_100MII_CR_SPEED_100 0x2000 igb_defines.h 　
31234
 MII_CR_SPEED_10MII_CR_SPEED_10 0x0000 igb_defines.h 　
31235
 MII_SR_EXTENDED_CAPSMII_SR_EXTENDED_CAPS 0x0001 igb_defines.h Extended register capabilities
31236
 MII_SR_JABBER_DETECTMII_SR_JABBER_DETECT 0x0002 igb_defines.h Jabber Detected
31237
 MII_SR_LINK_STATUSMII_SR_LINK_STATUS 0x0004 igb_defines.h Link Status 1 = link
31238
 MII_SR_AUTONEG_CAPSMII_SR_AUTONEG_CAPS 0x0008 igb_defines.h Auto Neg Capable
31239
 MII_SR_REMOTE_FAULTMII_SR_REMOTE_FAULT 0x0010 igb_defines.h Remote Fault Detect
31240
 MII_SR_AUTONEG_COMPLETEMII_SR_AUTONEG_COMPLETE 0x0020 igb_defines.h Auto Neg Complete
31241
 MII_SR_PREAMBLE_SUPPRESSMII_SR_PREAMBLE_SUPPRESS 0x0040 igb_defines.h Preamble may be suppressed
31242
 MII_SR_EXTENDED_STATUSMII_SR_EXTENDED_STATUS 0x0100 igb_defines.h Ext. status info in Reg 0x0F
31243
 MII_SR_100T2_HD_CAPSMII_SR_100T2_HD_CAPS 0x0200 igb_defines.h 100T2 Half Duplex Capable
31244
 MII_SR_100T2_FD_CAPSMII_SR_100T2_FD_CAPS 0x0400 igb_defines.h 100T2 Full Duplex Capable
31245
 MII_SR_10T_HD_CAPSMII_SR_10T_HD_CAPS 0x0800 igb_defines.h 10T Half Duplex Capable
31246
 MII_SR_10T_FD_CAPSMII_SR_10T_FD_CAPS 0x1000 igb_defines.h 10T Full Duplex Capable
31247
 MII_SR_100X_HD_CAPSMII_SR_100X_HD_CAPS 0x2000 igb_defines.h 100X Half Duplex Capable
31248
 MII_SR_100X_FD_CAPSMII_SR_100X_FD_CAPS 0x4000 igb_defines.h 100X Full Duplex Capable
31249
 MII_SR_100T4_CAPSMII_SR_100T4_CAPS 0x8000 igb_defines.h 100T4 Capable
31250
 NWAY_AR_SELECTOR_FIELDNWAY_AR_SELECTOR_FIELD 0x0001 igb_defines.h indicates IEEE 802.3 CSMA/CD
31251
 NWAY_AR_10T_HD_CAPSNWAY_AR_10T_HD_CAPS 0x0020 igb_defines.h 10T Half Duplex Capable
31252
 NWAY_AR_10T_FD_CAPSNWAY_AR_10T_FD_CAPS 0x0040 igb_defines.h 10T Full Duplex Capable
31253
 NWAY_AR_100TX_HD_CAPSNWAY_AR_100TX_HD_CAPS 0x0080 igb_defines.h 100TX Half Duplex Capable
31254
 NWAY_AR_100TX_FD_CAPSNWAY_AR_100TX_FD_CAPS 0x0100 igb_defines.h 100TX Full Duplex Capable
31255
 NWAY_AR_100T4_CAPSNWAY_AR_100T4_CAPS 0x0200 igb_defines.h 100T4 Capable
31256
 NWAY_AR_PAUSENWAY_AR_PAUSE 0x0400 igb_defines.h Pause operation desired
31257
 NWAY_AR_ASM_DIRNWAY_AR_ASM_DIR 0x0800 igb_defines.h Asymmetric Pause Direction bit
31258
 NWAY_AR_REMOTE_FAULTNWAY_AR_REMOTE_FAULT 0x2000 igb_defines.h Remote Fault detected
31259
 NWAY_AR_NEXT_PAGENWAY_AR_NEXT_PAGE 0x8000 igb_defines.h Next Page ability supported
31260
 NWAY_LPAR_SELECTOR_FIELDNWAY_LPAR_SELECTOR_FIELD 0x0000 igb_defines.h LP protocol selector field
31261
 NWAY_LPAR_10T_HD_CAPSNWAY_LPAR_10T_HD_CAPS 0x0020 igb_defines.h LP is 10T Half Duplex Capable
31262
 NWAY_LPAR_10T_FD_CAPSNWAY_LPAR_10T_FD_CAPS 0x0040 igb_defines.h LP is 10T Full Duplex Capable
31263
 NWAY_LPAR_100TX_HD_CAPSNWAY_LPAR_100TX_HD_CAPS 0x0080 igb_defines.h LP is 100TX Half Duplex Capable
31264
 NWAY_LPAR_100TX_FD_CAPSNWAY_LPAR_100TX_FD_CAPS 0x0100 igb_defines.h LP is 100TX Full Duplex Capable
31265
 NWAY_LPAR_100T4_CAPSNWAY_LPAR_100T4_CAPS 0x0200 igb_defines.h LP is 100T4 Capable
31266
 NWAY_LPAR_PAUSENWAY_LPAR_PAUSE 0x0400 igb_defines.h LP Pause operation desired
31267
 NWAY_LPAR_ASM_DIRNWAY_LPAR_ASM_DIR 0x0800 igb_defines.h LP Asymmetric Pause Direction bit
31268
 NWAY_LPAR_REMOTE_FAULTNWAY_LPAR_REMOTE_FAULT 0x2000 igb_defines.h LP has detected Remote Fault
31269
 NWAY_LPAR_ACKNOWLEDGENWAY_LPAR_ACKNOWLEDGE 0x4000 igb_defines.h LP has rx'd link code word
31270
 NWAY_LPAR_NEXT_PAGENWAY_LPAR_NEXT_PAGE 0x8000 igb_defines.h Next Page ability supported
31271
 NWAY_ER_LP_NWAY_CAPSNWAY_ER_LP_NWAY_CAPS 0x0001 igb_defines.h LP has Auto Neg Capability
31272
 NWAY_ER_PAGE_RXDNWAY_ER_PAGE_RXD 0x0002 igb_defines.h LP is 10T Half Duplex Capable
31273
 NWAY_ER_NEXT_PAGE_CAPSNWAY_ER_NEXT_PAGE_CAPS 0x0004 igb_defines.h LP is 10T Full Duplex Capable
31274
 NWAY_ER_LP_NEXT_PAGE_CAPSNWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 igb_defines.h LP is 100TX Half Duplex Capable
31275
 NWAY_ER_PAR_DETECT_FAULTNWAY_ER_PAR_DETECT_FAULT 0x0010 igb_defines.h LP is 100TX Full Duplex Capable
31276
 CR_1000T_ASYM_PAUSECR_1000T_ASYM_PAUSE 0x0080 igb_defines.h Advertise asymmetric pause bit
31277
 CR_1000T_HD_CAPSCR_1000T_HD_CAPS 0x0100 igb_defines.h Advertise 1000T HD capability
31278
 CR_1000T_FD_CAPSCR_1000T_FD_CAPS 0x0200 igb_defines.h Advertise 1000T FD capability
31279
 CR_1000T_REPEATER_DTECR_1000T_REPEATER_DTE 0x0400 igb_defines.h 1=Repeater/switch device port
31280
 CR_1000T_MS_VALUECR_1000T_MS_VALUE 0x0800 igb_defines.h 1=Configure PHY as Master
31281
 CR_1000T_MS_ENABLECR_1000T_MS_ENABLE 0x1000 igb_defines.h 1=Master/Slave manual config value
31282
 CR_1000T_TEST_MODE_NORMALCR_1000T_TEST_MODE_NORMAL 0x0000 igb_defines.h Normal Operation
31283
 CR_1000T_TEST_MODE_1CR_1000T_TEST_MODE_1 0x2000 igb_defines.h Transmit Waveform test
31284
 CR_1000T_TEST_MODE_2CR_1000T_TEST_MODE_2 0x4000 igb_defines.h Master Transmit Jitter test
31285
 CR_1000T_TEST_MODE_3CR_1000T_TEST_MODE_3 0x6000 igb_defines.h Slave Transmit Jitter test
31286
 CR_1000T_TEST_MODE_4CR_1000T_TEST_MODE_4 0x8000 igb_defines.h Transmitter Distortion test
31287
 SR_1000T_IDLE_ERROR_CNTSR_1000T_IDLE_ERROR_CNT 0x00FF igb_defines.h Num idle errors since last read
31288
 SR_1000T_ASYM_PAUSE_DIRSR_1000T_ASYM_PAUSE_DIR 0x0100 igb_defines.h LP asymmetric pause direction bit
31289
 SR_1000T_LP_HD_CAPSSR_1000T_LP_HD_CAPS 0x0400 igb_defines.h LP is 1000T HD capable
31290
 SR_1000T_LP_FD_CAPSSR_1000T_LP_FD_CAPS 0x0800 igb_defines.h LP is 1000T FD capable
31291
 SR_1000T_REMOTE_RX_STATUSSR_1000T_REMOTE_RX_STATUS 0x1000 igb_defines.h Remote receiver OK
31292
 SR_1000T_LOCAL_RX_STATUSSR_1000T_LOCAL_RX_STATUS 0x2000 igb_defines.h Local receiver OK
31293
 SR_1000T_MS_CONFIG_RESSR_1000T_MS_CONFIG_RES 0x4000 igb_defines.h 1=Local Tx is Master, 0=Slave
31294
 SR_1000T_MS_CONFIG_FAULTSR_1000T_MS_CONFIG_FAULT 0x8000 igb_defines.h Master/Slave config fault
31295
 SR_1000T_PHY_EXCESSIVE_IDLE_ERRSR_1000T_PHY_EXCESSIVE_IDLE_ERR 5 igb_defines.h 　
31296
 PHY_CONTROLPHY_CONTROL 0x00 igb_defines.h Control Register
31297
 PHY_STATUSPHY_STATUS 0x01 igb_defines.h Status Register
31298
 PHY_ID1PHY_ID1 0x02 igb_defines.h Phy Id Reg (word 1)
31299
 PHY_ID2PHY_ID2 0x03 igb_defines.h Phy Id Reg (word 2)
31300
 PHY_AUTONEG_ADVPHY_AUTONEG_ADV 0x04 igb_defines.h Autoneg Advertisement
31301
 PHY_LP_ABILITYPHY_LP_ABILITY 0x05 igb_defines.h Link Partner Ability (Base Page)
31302
 PHY_AUTONEG_EXPPHY_AUTONEG_EXP 0x06 igb_defines.h Autoneg Expansion Reg
31303
 PHY_NEXT_PAGE_TXPHY_NEXT_PAGE_TX 0x07 igb_defines.h Next Page Tx
31304
 PHY_LP_NEXT_PAGEPHY_LP_NEXT_PAGE 0x08 igb_defines.h Link Partner Next Page
31305
 PHY_1000T_CTRLPHY_1000T_CTRL 0x09 igb_defines.h 1000Base-T Control Reg
31306
 PHY_1000T_STATUSPHY_1000T_STATUS 0x0A igb_defines.h 1000Base-T Status Reg
31307
 PHY_EXT_STATUSPHY_EXT_STATUS 0x0F igb_defines.h Extended Status Reg
31308
 PHY_CONTROL_LBPHY_CONTROL_LB 0x4000 igb_defines.h PHY Loopback bit
31309
 E1000_EECD_SKE1000_EECD_SK 0x00000001 igb_defines.h NVM Clock
31310
 E1000_EECD_CSE1000_EECD_CS 0x00000002 igb_defines.h NVM Chip Select
31311
 E1000_EECD_DIE1000_EECD_DI 0x00000004 igb_defines.h NVM Data In
31312
 E1000_EECD_DOE1000_EECD_DO 0x00000008 igb_defines.h NVM Data Out
31313
 E1000_EECD_FWE_MASKE1000_EECD_FWE_MASK 0x00000030 igb_defines.h 　
31314
 E1000_EECD_FWE_DISE1000_EECD_FWE_DIS 0x00000010 igb_defines.h Disable FLASH writes
31315
 E1000_EECD_FWE_ENE1000_EECD_FWE_EN 0x00000020 igb_defines.h Enable FLASH writes
31316
 E1000_EECD_FWE_SHIFTE1000_EECD_FWE_SHIFT 4 igb_defines.h 　
31317
 E1000_EECD_REQE1000_EECD_REQ 0x00000040 igb_defines.h NVM Access Request
31318
 E1000_EECD_GNTE1000_EECD_GNT 0x00000080 igb_defines.h NVM Access Grant
31319
 E1000_EECD_PRESE1000_EECD_PRES 0x00000100 igb_defines.h NVM Present
31320
 E1000_EECD_SIZEE1000_EECD_SIZE 0x00000200 igb_defines.h NVM Size (0=64 word 1=256 word)
31321
 E1000_EECD_ADDR_BITSE1000_EECD_ADDR_BITS 0x00000400 igb_defines.h 　
31322
 E1000_EECD_TYPEE1000_EECD_TYPE 0x00002000 igb_defines.h NVM Type (1-SPI, 0-Microwire)
31323
 E1000_NVM_GRANT_ATTEMPTSE1000_NVM_GRANT_ATTEMPTS 1000 igb_defines.h NVM # attempts to gain grant
31324
 E1000_EECD_AUTO_RDE1000_EECD_AUTO_RD 0x00000200 igb_defines.h NVM Auto Read done
31325
 E1000_EECD_SIZE_EX_MASKE1000_EECD_SIZE_EX_MASK 0x00007800 igb_defines.h NVM Size
31326
 E1000_EECD_SIZE_EX_SHIFTE1000_EECD_SIZE_EX_SHIFT 11 igb_defines.h 　
31327
 E1000_EECD_NVADDSE1000_EECD_NVADDS 0x00018000 igb_defines.h NVM Address Size
31328
 E1000_EECD_SELSHADE1000_EECD_SELSHAD 0x00020000 igb_defines.h Select Shadow RAM
31329
 E1000_EECD_INITSRAME1000_EECD_INITSRAM 0x00040000 igb_defines.h Initialize Shadow RAM
31330
 E1000_EECD_FLUPDE1000_EECD_FLUPD 0x00080000 igb_defines.h Update FLASH
31331
 E1000_EECD_AUPDENE1000_EECD_AUPDEN 0x00100000 igb_defines.h Enable Autonomous FLASH update
31332
 E1000_EECD_SHADVE1000_EECD_SHADV 0x00200000 igb_defines.h Shadow RAM Data Valid
31333
 E1000_EECD_SEC1VALE1000_EECD_SEC1VAL 0x00400000 igb_defines.h Sector One Valid
31334
 E1000_EECD_SECVAL_SHIFTE1000_EECD_SECVAL_SHIFT 22 igb_defines.h 　
31335
 E1000_EECD_SEC1VAL_VALID_MASKE1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) igb_defines.h 　
31336
 E1000_NVM_SWDPIN0E1000_NVM_SWDPIN0 0x0001 igb_defines.h SWDPIN 0 NVM Value
31337
 E1000_NVM_LED_LOGICE1000_NVM_LED_LOGIC 0x0020 igb_defines.h Led Logic Word
31338
 E1000_NVM_RW_REG_DATAE1000_NVM_RW_REG_DATA 16 igb_defines.h Offset to data in NVM read/write regs
31339
 E1000_NVM_RW_REG_DONEE1000_NVM_RW_REG_DONE 2 igb_defines.h Offset to READ/WRITE done bit
31340
 E1000_NVM_RW_REG_STARTE1000_NVM_RW_REG_START 1 igb_defines.h Start operation
31341
 E1000_NVM_RW_ADDR_SHIFTE1000_NVM_RW_ADDR_SHIFT 2 igb_defines.h Shift to the address bits
31342
 E1000_NVM_POLL_WRITEE1000_NVM_POLL_WRITE 1 igb_defines.h Flag for polling for write complete
31343
 E1000_NVM_POLL_READE1000_NVM_POLL_READ 0 igb_defines.h Flag for polling for read complete
31344
 E1000_FLASH_UPDATESE1000_FLASH_UPDATES 2000 igb_defines.h 　
31345
 NVM_COMPATNVM_COMPAT 0x0003 igb_defines.h 　
31346
 NVM_ID_LED_SETTINGSNVM_ID_LED_SETTINGS 0x0004 igb_defines.h 　
31347
 NVM_VERSIONNVM_VERSION 0x0005 igb_defines.h 　
31348
 NVM_SERDES_AMPLITUDENVM_SERDES_AMPLITUDE 0x0006 igb_defines.h SERDES output amplitude
31349
 NVM_PHY_CLASS_WORDNVM_PHY_CLASS_WORD 0x0007 igb_defines.h 　
31350
 NVM_INIT_CONTROL1_REGNVM_INIT_CONTROL1_REG 0x000A igb_defines.h 　
31351
 NVM_INIT_CONTROL2_REGNVM_INIT_CONTROL2_REG 0x000F igb_defines.h 　
31352
 NVM_SWDEF_PINS_CTRL_PORT_1NVM_SWDEF_PINS_CTRL_PORT_1 0x0010 igb_defines.h 　
31353
 NVM_INIT_CONTROL3_PORT_BNVM_INIT_CONTROL3_PORT_B 0x0014 igb_defines.h 　
31354
 NVM_INIT_3GIO_3NVM_INIT_3GIO_3 0x001A igb_defines.h 　
31355
 NVM_SWDEF_PINS_CTRL_PORT_0NVM_SWDEF_PINS_CTRL_PORT_0 0x0020 igb_defines.h 　
31356
 NVM_INIT_CONTROL3_PORT_ANVM_INIT_CONTROL3_PORT_A 0x0024 igb_defines.h 　
31357
 NVM_CFGNVM_CFG 0x0012 igb_defines.h 　
31358
 NVM_FLASH_VERSIONNVM_FLASH_VERSION 0x0032 igb_defines.h 　
31359
 NVM_ALT_MAC_ADDR_PTRNVM_ALT_MAC_ADDR_PTR 0x0037 igb_defines.h 　
31360
 NVM_CHECKSUM_REGNVM_CHECKSUM_REG 0x003F igb_defines.h 　
31361
 E1000_NVM_CFG_DONE_PORT_0E1000_NVM_CFG_DONE_PORT_0 0x040000 igb_defines.h MNG config cycle done
31362
 E1000_NVM_CFG_DONE_PORT_1E1000_NVM_CFG_DONE_PORT_1 0x080000 igb_defines.h ...for second port
31363
 NVM_WORD0F_PAUSE_MASKNVM_WORD0F_PAUSE_MASK 0x3000 igb_defines.h 　
31364
 NVM_WORD0F_PAUSENVM_WORD0F_PAUSE 0x1000 igb_defines.h 　
31365
 NVM_WORD0F_ASM_DIRNVM_WORD0F_ASM_DIR 0x2000 igb_defines.h 　
31366
 NVM_WORD0F_ANENVM_WORD0F_ANE 0x0800 igb_defines.h 　
31367
 NVM_WORD0F_SWPDIO_EXT_MASKNVM_WORD0F_SWPDIO_EXT_MASK 0x00F0 igb_defines.h 　
31368
 NVM_WORD0F_LPLUNVM_WORD0F_LPLU 0x0001 igb_defines.h 　
31369
 NVM_WORD1A_ASPM_MASKNVM_WORD1A_ASPM_MASK 0x000C igb_defines.h 　
31370
 NVM_SUMNVM_SUM 0xBABA igb_defines.h 　
31371
 NVM_MAC_ADDR_OFFSETNVM_MAC_ADDR_OFFSET 0 igb_defines.h 　
31372
 NVM_PBA_OFFSET_0NVM_PBA_OFFSET_0 8 igb_defines.h 　
31373
 NVM_PBA_OFFSET_1NVM_PBA_OFFSET_1 9 igb_defines.h 　
31374
 NVM_RESERVED_WORDNVM_RESERVED_WORD 0xFFFF igb_defines.h 　
31375
 NVM_PHY_CLASS_ANVM_PHY_CLASS_A 0x8000 igb_defines.h 　
31376
 NVM_SERDES_AMPLITUDE_MASKNVM_SERDES_AMPLITUDE_MASK 0x000F igb_defines.h 　
31377
 NVM_SIZE_MASKNVM_SIZE_MASK 0x1C00 igb_defines.h 　
31378
 NVM_SIZE_SHIFTNVM_SIZE_SHIFT 10 igb_defines.h 　
31379
 NVM_WORD_SIZE_BASE_SHIFTNVM_WORD_SIZE_BASE_SHIFT 6 igb_defines.h 　
31380
 NVM_SWDPIO_EXT_SHIFTNVM_SWDPIO_EXT_SHIFT 4 igb_defines.h 　
31381
 NVM_MAX_RETRY_SPINVM_MAX_RETRY_SPI 5000 igb_defines.h Max wait of 5ms, for RDY signal
31382
 NVM_READ_OPCODE_SPINVM_READ_OPCODE_SPI 0x03 igb_defines.h NVM read opcode
31383
 NVM_WRITE_OPCODE_SPINVM_WRITE_OPCODE_SPI 0x02 igb_defines.h NVM write opcode
31384
 NVM_A8_OPCODE_SPINVM_A8_OPCODE_SPI 0x08 igb_defines.h opcode bit-3 = address bit-8
31385
 NVM_WREN_OPCODE_SPINVM_WREN_OPCODE_SPI 0x06 igb_defines.h NVM set Write Enable latch
31386
 NVM_WRDI_OPCODE_SPINVM_WRDI_OPCODE_SPI 0x04 igb_defines.h NVM reset Write Enable latch
31387
 NVM_RDSR_OPCODE_SPINVM_RDSR_OPCODE_SPI 0x05 igb_defines.h NVM read Status register
31388
 NVM_WRSR_OPCODE_SPINVM_WRSR_OPCODE_SPI 0x01 igb_defines.h NVM write Status register
31389
 NVM_STATUS_RDY_SPINVM_STATUS_RDY_SPI 0x01 igb_defines.h 　
31390
 NVM_STATUS_WEN_SPINVM_STATUS_WEN_SPI 0x02 igb_defines.h 　
31391
 NVM_STATUS_BP0_SPINVM_STATUS_BP0_SPI 0x04 igb_defines.h 　
31392
 NVM_STATUS_BP1_SPINVM_STATUS_BP1_SPI 0x08 igb_defines.h 　
31393
 NVM_STATUS_WPEN_SPINVM_STATUS_WPEN_SPI 0x80 igb_defines.h 　
31394
 ID_LED_RESERVED_0000ID_LED_RESERVED_0000 0x0000 igb_defines.h 　
31395
 ID_LED_RESERVED_FFFFID_LED_RESERVED_FFFF 0xFFFF igb_defines.h 　
31396
 ID_LED_DEFAULTID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_DEF1_DEF2 << 4) | \ (ID_LED_DEF1_DEF2)) igb_defines.h 　
31397
 ID_LED_DEF1_DEF2ID_LED_DEF1_DEF2 0x1 igb_defines.h 　
31398
 ID_LED_DEF1_ON2ID_LED_DEF1_ON2 0x2 igb_defines.h 　
31399
 ID_LED_DEF1_OFF2ID_LED_DEF1_OFF2 0x3 igb_defines.h 　
31400
 ID_LED_ON1_DEF2ID_LED_ON1_DEF2 0x4 igb_defines.h 　
31401
 ID_LED_ON1_ON2ID_LED_ON1_ON2 0x5 igb_defines.h 　
31402
 ID_LED_ON1_OFF2ID_LED_ON1_OFF2 0x6 igb_defines.h 　
31403
 ID_LED_OFF1_DEF2ID_LED_OFF1_DEF2 0x7 igb_defines.h 　
31404
 ID_LED_OFF1_ON2ID_LED_OFF1_ON2 0x8 igb_defines.h 　
31405
 ID_LED_OFF1_OFF2ID_LED_OFF1_OFF2 0x9 igb_defines.h 　
31406
 IGP_ACTIVITY_LED_MASKIGP_ACTIVITY_LED_MASK 0xFFFFF0FF igb_defines.h 　
31407
 IGP_ACTIVITY_LED_ENABLEIGP_ACTIVITY_LED_ENABLE 0x0300 igb_defines.h 　
31408
 IGP_LED3_MODEIGP_LED3_MODE 0x07000000 igb_defines.h 　
31409
 PCI_HEADER_TYPE_REGISTERPCI_HEADER_TYPE_REGISTER 0x0E igb_defines.h 　
31410
 PCIE_LINK_STATUSPCIE_LINK_STATUS 0x12 igb_defines.h 　
31411
 PCIE_DEVICE_CONTROL2PCIE_DEVICE_CONTROL2 0x28 igb_defines.h 　
31412
 PCI_HEADER_TYPE_MULTIFUNCPCI_HEADER_TYPE_MULTIFUNC 0x80 igb_defines.h 　
31413
 PCIE_LINK_WIDTH_MASKPCIE_LINK_WIDTH_MASK 0x3F0 igb_defines.h 　
31414
 PCIE_LINK_WIDTH_SHIFTPCIE_LINK_WIDTH_SHIFT 4 igb_defines.h 　
31415
 PCIE_DEVICE_CONTROL2_16msPCIE_DEVICE_CONTROL2_16ms 0x0005 igb_defines.h 　
31416
 ETH_ADDR_LENETH_ADDR_LEN 6 igb_defines.h 　
31417
 PHY_REVISION_MASKPHY_REVISION_MASK 0xFFFFFFF0 igb_defines.h 　
31418
 MAX_PHY_REG_ADDRESSMAX_PHY_REG_ADDRESS 0x1F igb_defines.h 5 bit address bus (0-0x1F)
31419
 MAX_PHY_MULTI_PAGE_REGMAX_PHY_MULTI_PAGE_REG 0xF igb_defines.h 　
31420
 M88E1000_E_PHY_IDM88E1000_E_PHY_ID 0x01410C50 igb_defines.h 　
31421
 M88E1000_I_PHY_IDM88E1000_I_PHY_ID 0x01410C30 igb_defines.h 　
31422
 M88E1011_I_PHY_IDM88E1011_I_PHY_ID 0x01410C20 igb_defines.h 　
31423
 IGP01E1000_I_PHY_IDIGP01E1000_I_PHY_ID 0x02A80380 igb_defines.h 　
31424
 M88E1011_I_REV_4M88E1011_I_REV_4 0x04 igb_defines.h 　
31425
 M88E1111_I_PHY_IDM88E1111_I_PHY_ID 0x01410CC0 igb_defines.h 　
31426
 GG82563_E_PHY_IDGG82563_E_PHY_ID 0x01410CA0 igb_defines.h 　
31427
 IGP03E1000_E_PHY_IDIGP03E1000_E_PHY_ID 0x02A80390 igb_defines.h 　
31428
 IFE_E_PHY_IDIFE_E_PHY_ID 0x02A80330 igb_defines.h 　
31429
 IFE_PLUS_E_PHY_IDIFE_PLUS_E_PHY_ID 0x02A80320 igb_defines.h 　
31430
 IFE_C_E_PHY_IDIFE_C_E_PHY_ID 0x02A80310 igb_defines.h 　
31431
 IGP04E1000_E_PHY_IDIGP04E1000_E_PHY_ID 0x02A80391 igb_defines.h 　
31432
 M88_VENDORM88_VENDOR 0x0141 igb_defines.h 　
31433
 M88E1000_PHY_SPEC_CTRLM88E1000_PHY_SPEC_CTRL 0x10 igb_defines.h PHY Specific Control Register
31434
 M88E1000_PHY_SPEC_STATUSM88E1000_PHY_SPEC_STATUS 0x11 igb_defines.h PHY Specific Status Register
31435
 M88E1000_INT_ENABLEM88E1000_INT_ENABLE 0x12 igb_defines.h Interrupt Enable Register
31436
 M88E1000_INT_STATUSM88E1000_INT_STATUS 0x13 igb_defines.h Interrupt Status Register
31437
 M88E1000_EXT_PHY_SPEC_CTRLM88E1000_EXT_PHY_SPEC_CTRL 0x14 igb_defines.h Extended PHY Specific Control
31438
 M88E1000_RX_ERR_CNTRM88E1000_RX_ERR_CNTR 0x15 igb_defines.h Receive Error Counter
31439
 M88E1000_PHY_EXT_CTRLM88E1000_PHY_EXT_CTRL 0x1A igb_defines.h PHY extend control register
31440
 M88E1000_PHY_PAGE_SELECTM88E1000_PHY_PAGE_SELECT 0x1D igb_defines.h Reg 29 for page number setting
31441
 M88E1000_PHY_GEN_CONTROLM88E1000_PHY_GEN_CONTROL 0x1E igb_defines.h Its meaning depends on reg 29
31442
 M88E1000_PHY_VCO_REG_BIT8M88E1000_PHY_VCO_REG_BIT8 0x100 igb_defines.h Bits 8 & 11 are adjusted for
31443
 M88E1000_PHY_VCO_REG_BIT11M88E1000_PHY_VCO_REG_BIT11 0x800 igb_defines.h improved BER performance
31444
 M88E1000_PSCR_JABBER_DISABLEM88E1000_PSCR_JABBER_DISABLE 0x0001 igb_defines.h 1=Jabber Function disabled
31445
 M88E1000_PSCR_POLARITY_REVERSALM88E1000_PSCR_POLARITY_REVERSAL 0x0002 igb_defines.h 1=Polarity Reverse enabled
31446
 M88E1000_PSCR_SQE_TESTM88E1000_PSCR_SQE_TEST 0x0004 igb_defines.h 1=SQE Test enabled
31447
 M88E1000_PSCR_CLK125_DISABLEM88E1000_PSCR_CLK125_DISABLE 0x0010 igb_defines.h 　
31448
 M88E1000_PSCR_MDI_MANUAL_MODEM88E1000_PSCR_MDI_MANUAL_MODE 0x0000 igb_defines.h MDI Crossover Mode bits 6:5
31449
 M88E1000_PSCR_MDIX_MANUAL_MODEM88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 igb_defines.h Manual MDIX configuration
31450
 M88E1000_PSCR_AUTO_X_1000TM88E1000_PSCR_AUTO_X_1000T 0x0040 igb_defines.h 　
31451
 M88E1000_PSCR_AUTO_X_MODEM88E1000_PSCR_AUTO_X_MODE 0x0060 igb_defines.h 　
31452
 M88E1000_PSCR_EN_10BT_EXT_DISTM88E1000_PSCR_EN_10BT_EXT_DIST 0x0080 igb_defines.h 　
31453
 M88E1000_PSCR_MII_5BIT_ENABLEM88E1000_PSCR_MII_5BIT_ENABLE 0x0100 igb_defines.h 　
31454
 M88E1000_PSCR_SCRAMBLER_DISABLEM88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 igb_defines.h 1=Scrambler disable
31455
 M88E1000_PSCR_FORCE_LINK_GOODM88E1000_PSCR_FORCE_LINK_GOOD 0x0400 igb_defines.h 1=Force link good
31456
 M88E1000_PSCR_ASSERT_CRS_ON_TXM88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 igb_defines.h 1=Assert CRS on Tx
31457
 M88E1000_PSSR_JABBERM88E1000_PSSR_JABBER 0x0001 igb_defines.h 1=Jabber
31458
 M88E1000_PSSR_REV_POLARITYM88E1000_PSSR_REV_POLARITY 0x0002 igb_defines.h 1=Polarity reversed
31459
 M88E1000_PSSR_DOWNSHIFTM88E1000_PSSR_DOWNSHIFT 0x0020 igb_defines.h 1=Downshifted
31460
 M88E1000_PSSR_MDIXM88E1000_PSSR_MDIX 0x0040 igb_defines.h 1=MDIX; 0=MDI
31461
 M88E1000_PSSR_CABLE_LENGTHM88E1000_PSSR_CABLE_LENGTH 0x0380 igb_defines.h 　
31462
 M88E1000_PSSR_LINKM88E1000_PSSR_LINK 0x0400 igb_defines.h 1=Link up, 0=Link down
31463
 M88E1000_PSSR_SPD_DPLX_RESOLVEDM88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 igb_defines.h 1=Speed & Duplex resolved
31464
 M88E1000_PSSR_PAGE_RCVDM88E1000_PSSR_PAGE_RCVD 0x1000 igb_defines.h 1=Page received
31465
 M88E1000_PSSR_DPLXM88E1000_PSSR_DPLX 0x2000 igb_defines.h 1=Duplex 0=Half Duplex
31466
 M88E1000_PSSR_SPEEDM88E1000_PSSR_SPEED 0xC000 igb_defines.h Speed, bits 14:15
31467
 M88E1000_PSSR_10MBSM88E1000_PSSR_10MBS 0x0000 igb_defines.h 00=10Mbs
31468
 M88E1000_PSSR_100MBSM88E1000_PSSR_100MBS 0x4000 igb_defines.h 01=100Mbs
31469
 M88E1000_PSSR_1000MBSM88E1000_PSSR_1000MBS 0x8000 igb_defines.h 10=1000Mbs
31470
 M88E1000_PSSR_CABLE_LENGTH_SHIFM88E1000_PSSR_CABLE_LENGTH_SHIF 7 igb_defines.h 　
31471
 M88E1000_EPSCR_FIBER_LOOPBACKM88E1000_EPSCR_FIBER_LOOPBACK 0x4000 igb_defines.h 1=Fiber loopback
31472
 M88E1000_EPSCR_DOWN_NO_IDLEM88E1000_EPSCR_DOWN_NO_IDLE 0x8000 igb_defines.h 　
31473
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 igb_defines.h 　
31474
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0000 igb_defines.h 　
31475
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0400 igb_defines.h 　
31476
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0800 igb_defines.h 　
31477
 M88E1000_EPSCR_MASTER_DOWNSHIFTM88E1000_EPSCR_MASTER_DOWNSHIFT 0x0C00 igb_defines.h 　
31478
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 igb_defines.h 　
31479
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0000 igb_defines.h 　
31480
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0100 igb_defines.h 　
31481
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0200 igb_defines.h 　
31482
 M88E1000_EPSCR_SLAVE_DOWNSHIFT_M88E1000_EPSCR_SLAVE_DOWNSHIFT_ 0x0300 igb_defines.h 　
31483
 M88E1000_EPSCR_TX_CLK_2_5M88E1000_EPSCR_TX_CLK_2_5 0x0060 igb_defines.h 2.5 MHz TX_CLK
31484
 M88E1000_EPSCR_TX_CLK_25M88E1000_EPSCR_TX_CLK_25 0x0070 igb_defines.h 25 MHz TX_CLK
31485
 M88E1000_EPSCR_TX_CLK_0M88E1000_EPSCR_TX_CLK_0 0x0000 igb_defines.h NO TX_CLK
31486
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 igb_defines.h 　
31487
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0000 igb_defines.h 　
31488
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0200 igb_defines.h 　
31489
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0400 igb_defines.h 　
31490
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0600 igb_defines.h 　
31491
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0800 igb_defines.h 　
31492
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0A00 igb_defines.h 　
31493
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0C00 igb_defines.h 　
31494
 M88EC018_EPSCR_DOWNSHIFT_COUNTEM88EC018_EPSCR_DOWNSHIFT_COUNTE 0x0E00 igb_defines.h 　
31495
 GG82563_PAGE_SHIFTGG82563_PAGE_SHIFT 5 igb_defines.h 　
31496
 GG82563_MIN_ALT_REGGG82563_MIN_ALT_REG 30 igb_defines.h 　
31497
 GG82563_PHY_SPEC_CTRLGG82563_PHY_SPEC_CTRL GG82563_REG(0, 16) igb_defines.h PHY Specific Control
31498
 GG82563_PHY_SPEC_STATUSGG82563_PHY_SPEC_STATUS GG82563_REG(0, 17) igb_defines.h PHY Specific Status
31499
 GG82563_PHY_INT_ENABLEGG82563_PHY_INT_ENABLE GG82563_REG(0, 18) igb_defines.h Interrupt Enable
31500
 GG82563_PHY_SPEC_STATUS_2GG82563_PHY_SPEC_STATUS_2 GG82563_REG(0, 19) igb_defines.h PHY Specific Status 2
31501
 GG82563_PHY_RX_ERR_CNTRGG82563_PHY_RX_ERR_CNTR GG82563_REG(0, 21) igb_defines.h Receive Error Counter
31502
 GG82563_PHY_PAGE_SELECTGG82563_PHY_PAGE_SELECT GG82563_REG(0, 22) igb_defines.h Page Select
31503
 GG82563_PHY_SPEC_CTRL_2GG82563_PHY_SPEC_CTRL_2 GG82563_REG(0, 26) igb_defines.h PHY Specific Control 2
31504
 GG82563_PHY_PAGE_SELECT_ALTGG82563_PHY_PAGE_SELECT_ALT GG82563_REG(0, 29) igb_defines.h Alternate Page Select
31505
 GG82563_PHY_TEST_CLK_CTRLGG82563_PHY_TEST_CLK_CTRL GG82563_REG(0, 30) igb_defines.h Test Clock Control (use reg. 29 to select)
31506
 GG82563_PHY_MAC_SPEC_CTRLGG82563_PHY_MAC_SPEC_CTRL GG82563_REG(2, 21) igb_defines.h MAC Specific Control Register
31507
 GG82563_PHY_MAC_SPEC_CTRL_2GG82563_PHY_MAC_SPEC_CTRL_2 GG82563_REG(2, 26) igb_defines.h MAC Specific Control 2
31508
 GG82563_PHY_DSP_DISTANCEGG82563_PHY_DSP_DISTANCE GG82563_REG(5, 26) igb_defines.h DSP Distance
31509
 GG82563_PHY_KMRN_MODE_CTRLGG82563_PHY_KMRN_MODE_CTRL GG82563_REG(193, 16) igb_defines.h Kumeran Mode Control
31510
 GG82563_PHY_PORT_RESETGG82563_PHY_PORT_RESET GG82563_REG(193, 17) igb_defines.h Port Reset
31511
 GG82563_PHY_REVISION_IDGG82563_PHY_REVISION_ID GG82563_REG(193, 18) igb_defines.h Revision ID
31512
 GG82563_PHY_DEVICE_IDGG82563_PHY_DEVICE_ID GG82563_REG(193, 19) igb_defines.h Device ID
31513
 GG82563_PHY_PWR_MGMT_CTRLGG82563_PHY_PWR_MGMT_CTRL GG82563_REG(193, 20) igb_defines.h Power Management Control
31514
 GG82563_PHY_RATE_ADAPT_CTRLGG82563_PHY_RATE_ADAPT_CTRL GG82563_REG(193, 25) igb_defines.h Rate Adaptation Control
31515
 GG82563_PHY_KMRN_FIFO_CTRL_STATGG82563_PHY_KMRN_FIFO_CTRL_STAT GG82563_REG(194, 16) igb_defines.h FIFO's Control/Status
31516
 GG82563_PHY_KMRN_CTRLGG82563_PHY_KMRN_CTRL GG82563_REG(194, 17) igb_defines.h Control
31517
 GG82563_PHY_INBAND_CTRLGG82563_PHY_INBAND_CTRL GG82563_REG(194, 18) igb_defines.h Inband Control
31518
 GG82563_PHY_KMRN_DIAGNOSTICGG82563_PHY_KMRN_DIAGNOSTIC GG82563_REG(194, 19) igb_defines.h Diagnostic
31519
 GG82563_PHY_ACK_TIMEOUTSGG82563_PHY_ACK_TIMEOUTS GG82563_REG(194, 20) igb_defines.h Acknowledge Timeouts
31520
 GG82563_PHY_ADV_ABILITYGG82563_PHY_ADV_ABILITY GG82563_REG(194, 21) igb_defines.h Advertised Ability
31521
 GG82563_PHY_LINK_PARTNER_ADV_ABGG82563_PHY_LINK_PARTNER_ADV_AB GG82563_REG(194, 23) igb_defines.h Link Partner Advertised Ability
31522
 GG82563_PHY_ADV_NEXT_PAGEGG82563_PHY_ADV_NEXT_PAGE GG82563_REG(194, 24) igb_defines.h Advertised Next Page
31523
 GG82563_PHY_LINK_PARTNER_ADV_NEGG82563_PHY_LINK_PARTNER_ADV_NE GG82563_REG(194, 25) igb_defines.h Link Partner Advertised Next page
31524
 GG82563_PHY_KMRN_MISCGG82563_PHY_KMRN_MISC GG82563_REG(194, 26) igb_defines.h Misc.
31525
 E1000_MDIC_DATA_MASKE1000_MDIC_DATA_MASK 0x0000FFFF igb_defines.h 　
31526
 E1000_MDIC_REG_MASKE1000_MDIC_REG_MASK 0x001F0000 igb_defines.h 　
31527
 E1000_MDIC_REG_SHIFTE1000_MDIC_REG_SHIFT 16 igb_defines.h 　
31528
 E1000_MDIC_PHY_MASKE1000_MDIC_PHY_MASK 0x03E00000 igb_defines.h 　
31529
 E1000_MDIC_PHY_SHIFTE1000_MDIC_PHY_SHIFT 21 igb_defines.h 　
31530
 E1000_MDIC_OP_WRITEE1000_MDIC_OP_WRITE 0x04000000 igb_defines.h 　
31531
 E1000_MDIC_OP_READE1000_MDIC_OP_READ 0x08000000 igb_defines.h 　
31532
 E1000_MDIC_READYE1000_MDIC_READY 0x10000000 igb_defines.h 　
31533
 E1000_MDIC_INT_ENE1000_MDIC_INT_EN 0x20000000 igb_defines.h 　
31534
 E1000_MDIC_ERRORE1000_MDIC_ERROR 0x40000000 igb_defines.h 　
31535
 E1000_GEN_CTL_READYE1000_GEN_CTL_READY 0x80000000 igb_defines.h 　
31536
 E1000_GEN_CTL_ADDRESS_SHIFTE1000_GEN_CTL_ADDRESS_SHIFT 8 igb_defines.h 　
31537
 E1000_GEN_POLL_TIMEOUTE1000_GEN_POLL_TIMEOUT 640 igb_defines.h 　
31538
 E1000_LSECTXCAP_SUM_MASKE1000_LSECTXCAP_SUM_MASK 0x00FF0000 igb_defines.h 　
31539
 E1000_LSECTXCAP_SUM_SHIFTE1000_LSECTXCAP_SUM_SHIFT 16 igb_defines.h 　
31540
 E1000_LSECRXCAP_SUM_MASKE1000_LSECRXCAP_SUM_MASK 0x00FF0000 igb_defines.h 　
31541
 E1000_LSECRXCAP_SUM_SHIFTE1000_LSECRXCAP_SUM_SHIFT 16 igb_defines.h 　
31542
 E1000_LSECTXCTRL_EN_MASKE1000_LSECTXCTRL_EN_MASK 0x00000003 igb_defines.h 　
31543
 E1000_LSECTXCTRL_DISABLEE1000_LSECTXCTRL_DISABLE 0x0 igb_defines.h 　
31544
 E1000_LSECTXCTRL_AUTHE1000_LSECTXCTRL_AUTH 0x1 igb_defines.h 　
31545
 E1000_LSECTXCTRL_AUTH_ENCRYPTE1000_LSECTXCTRL_AUTH_ENCRYPT 0x2 igb_defines.h 　
31546
 E1000_LSECTXCTRL_AISCIE1000_LSECTXCTRL_AISCI 0x00000020 igb_defines.h 　
31547
 E1000_LSECTXCTRL_PNTHRSH_MASKE1000_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 igb_defines.h 　
31548
 E1000_LSECTXCTRL_RSV_MASKE1000_LSECTXCTRL_RSV_MASK 0x000000D8 igb_defines.h 　
31549
 E1000_LSECRXCTRL_EN_MASKE1000_LSECRXCTRL_EN_MASK 0x0000000C igb_defines.h 　
31550
 E1000_LSECRXCTRL_EN_SHIFTE1000_LSECRXCTRL_EN_SHIFT 2 igb_defines.h 　
31551
 E1000_LSECRXCTRL_DISABLEE1000_LSECRXCTRL_DISABLE 0x0 igb_defines.h 　
31552
 E1000_LSECRXCTRL_CHECKE1000_LSECRXCTRL_CHECK 0x1 igb_defines.h 　
31553
 E1000_LSECRXCTRL_STRICTE1000_LSECRXCTRL_STRICT 0x2 igb_defines.h 　
31554
 E1000_LSECRXCTRL_DROPE1000_LSECRXCTRL_DROP 0x3 igb_defines.h 　
31555
 E1000_LSECRXCTRL_PLSHE1000_LSECRXCTRL_PLSH 0x00000040 igb_defines.h 　
31556
 E1000_LSECRXCTRL_RPE1000_LSECRXCTRL_RP 0x00000080 igb_defines.h 　
31557
 E1000_LSECRXCTRL_RSV_MASKE1000_LSECRXCTRL_RSV_MASK 0xFFFFFF33 igb_defines.h 　
31558
 E1000_DEV_ID_82576E1000_DEV_ID_82576 0x10C9 igb_hw.h 　
31559
 E1000_DEV_ID_82576_FIBERE1000_DEV_ID_82576_FIBER 0x10E6 igb_hw.h 　
31560
 E1000_DEV_ID_82576_SERDESE1000_DEV_ID_82576_SERDES 0x10E7 igb_hw.h 　
31561
 E1000_DEV_ID_82576_QUAD_COPPERE1000_DEV_ID_82576_QUAD_COPPER 0x10E8 igb_hw.h 　
31562
 E1000_DEV_ID_82576_NSE1000_DEV_ID_82576_NS 0x150A igb_hw.h 　
31563
 E1000_DEV_ID_82576_NS_SERDESE1000_DEV_ID_82576_NS_SERDES 0x1518 igb_hw.h 　
31564
 E1000_DEV_ID_82576_SERDES_QUADE1000_DEV_ID_82576_SERDES_QUAD 0x150D igb_hw.h 　
31565
 E1000_DEV_ID_82575EB_COPPERE1000_DEV_ID_82575EB_COPPER 0x10A7 igb_hw.h 　
31566
 E1000_DEV_ID_82575EB_FIBER_SERDE1000_DEV_ID_82575EB_FIBER_SERD 0x10A9 igb_hw.h 　
31567
 E1000_DEV_ID_82575GB_QUAD_COPPEE1000_DEV_ID_82575GB_QUAD_COPPE 0x10D6 igb_hw.h 　
31568
 E1000_REVISION_0E1000_REVISION_0 0 igb_hw.h 　
31569
 E1000_REVISION_1E1000_REVISION_1 1 igb_hw.h 　
31570
 E1000_REVISION_2E1000_REVISION_2 2 igb_hw.h 　
31571
 E1000_REVISION_3E1000_REVISION_3 3 igb_hw.h 　
31572
 E1000_REVISION_4E1000_REVISION_4 4 igb_hw.h 　
31573
 E1000_FUNC_0E1000_FUNC_0 0 igb_hw.h 　
31574
 E1000_FUNC_1E1000_FUNC_1 1 igb_hw.h 　
31575
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 0 igb_hw.h 　
31576
 E1000_ALT_MAC_ADDRESS_OFFSET_LAE1000_ALT_MAC_ADDRESS_OFFSET_LA 3 igb_hw.h 　
31577
 MAX_PS_BUFFERSMAX_PS_BUFFERS 4 igb_hw.h 　
31578
 E1000_HI_MAX_DATA_LENGTHE1000_HI_MAX_DATA_LENGTH 252 igb_hw.h 　
31579
 E1000_HI_MAX_MNG_DATA_LENGTHE1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 igb_hw.h 　
31580
 E1000_FACTPS_MNGCGE1000_FACTPS_MNGCG 0x20000000 igb_manage.h 　
31581
 E1000_FWSM_MODE_MASKE1000_FWSM_MODE_MASK 0xE igb_manage.h 　
31582
 E1000_FWSM_MODE_SHIFTE1000_FWSM_MODE_SHIFT 1 igb_manage.h 　
31583
 E1000_MNG_IAMT_MODEE1000_MNG_IAMT_MODE 0x3 igb_manage.h 　
31584
 E1000_MNG_DHCP_COOKIE_LENGTHE1000_MNG_DHCP_COOKIE_LENGTH 0x10 igb_manage.h 　
31585
 E1000_MNG_DHCP_COOKIE_OFFSETE1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 igb_manage.h 　
31586
 E1000_MNG_DHCP_COMMAND_TIMEOUTE1000_MNG_DHCP_COMMAND_TIMEOUT 10 igb_manage.h 　
31587
 E1000_MNG_DHCP_TX_PAYLOAD_CMDE1000_MNG_DHCP_TX_PAYLOAD_CMD 64 igb_manage.h 　
31588
 E1000_MNG_DHCP_COOKIE_STATUS_PAE1000_MNG_DHCP_COOKIE_STATUS_PA 0x1 igb_manage.h 　
31589
 E1000_MNG_DHCP_COOKIE_STATUS_VLE1000_MNG_DHCP_COOKIE_STATUS_VL 0x2 igb_manage.h 　
31590
 E1000_VFTA_ENTRY_SHIFTE1000_VFTA_ENTRY_SHIFT 5 igb_manage.h 　
31591
 E1000_VFTA_ENTRY_MASKE1000_VFTA_ENTRY_MASK 0x7F igb_manage.h 　
31592
 E1000_VFTA_ENTRY_BIT_SHIFT_MASKE1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F igb_manage.h 　
31593
 E1000_HI_MAX_BLOCK_BYTE_LENGTHE1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 igb_manage.h Num of bytes in range
31594
 E1000_HI_MAX_BLOCK_DWORD_LENGTHE1000_HI_MAX_BLOCK_DWORD_LENGTH 448 igb_manage.h Num of dwords in range
31595
 E1000_HI_COMMAND_TIMEOUTE1000_HI_COMMAND_TIMEOUT 500 igb_manage.h Process HI command limit
31596
 E1000_HICR_ENE1000_HICR_EN 0x01 igb_manage.h Enable bit - RO
31597
 E1000_HICR_CE1000_HICR_C 0x02 igb_manage.h 　
31598
 E1000_HICR_SVE1000_HICR_SV 0x04 igb_manage.h Status Validity
31599
 E1000_HICR_FW_RESET_ENABLEE1000_HICR_FW_RESET_ENABLE 0x40 igb_manage.h 　
31600
 E1000_HICR_FW_RESETE1000_HICR_FW_RESET 0x80 igb_manage.h 　
31601
 E1000_IAMT_SIGNATUREE1000_IAMT_SIGNATURE 0x544D4149 igb_manage.h 　
31602
 E1000_STM_OPCODEE1000_STM_OPCODE 0xDB00 igb_nvm.h 　
31603
 u8u8 unsigned char igb_osdep.h 　
31604
 boolbool boolean_t igb_osdep.h 　
31605
 dma_addr_tdma_addr_t unsigned long igb_osdep.h 　
31606
 __le16__le16 uint16_t igb_osdep.h 　
31607
 __le32__le32 uint32_t igb_osdep.h 　
31608
 __le64__le64 uint64_t igb_osdep.h 　
31609
 ETH_FCS_LENETH_FCS_LEN 4 igb_osdep.h 　
31610
 TRUETRUE 1 igb_osdep.h 　
31611
 FALSEFALSE 0 igb_osdep.h 　
31612
 PCI_COMMAND_REGISTERPCI_COMMAND_REGISTER PCI_COMMAND igb_osdep.h 　
31613
 CMD_MEM_WRT_INVALIDATECMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE igb_osdep.h 　
31614
 ETH_ADDR_LENETH_ADDR_LEN ETH_ALEN igb_osdep.h 　
31615
 E1000_BIG_ENDIANE1000_BIG_ENDIAN __BIG_ENDIAN igb_osdep.h 　
31616
 DEBUGOUT2DEBUGOUT2 DEBUGOUT1 igb_osdep.h 　
31617
 DEBUGOUT3DEBUGOUT3 DEBUGOUT2 igb_osdep.h 　
31618
 DEBUGOUT7DEBUGOUT7 DEBUGOUT3 igb_osdep.h 　
31619
 E1000_READ_REG_ARRAY_DWORDE1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY igb_osdep.h 　
31620
 E1000_WRITE_REG_ARRAY_DWORDE1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY igb_osdep.h 　
31621
 E1000_MAX_PHY_ADDRE1000_MAX_PHY_ADDR 4 igb_phy.h 　
31622
 IGP01E1000_PHY_PORT_CONFIGIGP01E1000_PHY_PORT_CONFIG 0x10 igb_phy.h Port Config
31623
 IGP01E1000_PHY_PORT_STATUSIGP01E1000_PHY_PORT_STATUS 0x11 igb_phy.h Status
31624
 IGP01E1000_PHY_PORT_CTRLIGP01E1000_PHY_PORT_CTRL 0x12 igb_phy.h Control
31625
 IGP01E1000_PHY_LINK_HEALTHIGP01E1000_PHY_LINK_HEALTH 0x13 igb_phy.h PHY Link Health
31626
 IGP01E1000_GMII_FIFOIGP01E1000_GMII_FIFO 0x14 igb_phy.h GMII FIFO
31627
 IGP01E1000_PHY_CHANNEL_QUALITYIGP01E1000_PHY_CHANNEL_QUALITY 0x15 igb_phy.h PHY Channel Quality
31628
 IGP02E1000_PHY_POWER_MGMTIGP02E1000_PHY_POWER_MGMT 0x19 igb_phy.h Power Management
31629
 IGP01E1000_PHY_PAGE_SELECTIGP01E1000_PHY_PAGE_SELECT 0x1F igb_phy.h Page Select
31630
 BM_PHY_PAGE_SELECTBM_PHY_PAGE_SELECT 22 igb_phy.h Page Select for BM
31631
 IGP_PAGE_SHIFTIGP_PAGE_SHIFT 5 igb_phy.h 　
31632
 PHY_REG_MASKPHY_REG_MASK 0x1F igb_phy.h 　
31633
 IGP01E1000_PHY_PCS_INIT_REGIGP01E1000_PHY_PCS_INIT_REG 0x00B4 igb_phy.h 　
31634
 IGP01E1000_PHY_POLARITY_MASKIGP01E1000_PHY_POLARITY_MASK 0x0078 igb_phy.h 　
31635
 IGP01E1000_PSCR_AUTO_MDIXIGP01E1000_PSCR_AUTO_MDIX 0x1000 igb_phy.h 　
31636
 IGP01E1000_PSCR_FORCE_MDI_MDIXIGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 igb_phy.h 0=MDI, 1=MDIX
31637
 IGP01E1000_PSCFR_SMART_SPEEDIGP01E1000_PSCFR_SMART_SPEED 0x0080 igb_phy.h 　
31638
 IGP01E1000_GMII_FLEX_SPDIGP01E1000_GMII_FLEX_SPD 0x0010 igb_phy.h 　
31639
 IGP01E1000_GMII_SPDIGP01E1000_GMII_SPD 0x0020 igb_phy.h Enable SPD
31640
 IGP02E1000_PM_SPDIGP02E1000_PM_SPD 0x0001 igb_phy.h Smart Power Down
31641
 IGP02E1000_PM_D0_LPLUIGP02E1000_PM_D0_LPLU 0x0002 igb_phy.h For D0a states
31642
 IGP02E1000_PM_D3_LPLUIGP02E1000_PM_D3_LPLU 0x0004 igb_phy.h For all other states
31643
 IGP01E1000_PLHR_SS_DOWNGRADEIGP01E1000_PLHR_SS_DOWNGRADE 0x8000 igb_phy.h 　
31644
 IGP01E1000_PSSR_POLARITY_REVERSIGP01E1000_PSSR_POLARITY_REVERS 0x0002 igb_phy.h 　
31645
 IGP01E1000_PSSR_MDIXIGP01E1000_PSSR_MDIX 0x0800 igb_phy.h 　
31646
 IGP01E1000_PSSR_SPEED_MASKIGP01E1000_PSSR_SPEED_MASK 0xC000 igb_phy.h 　
31647
 IGP01E1000_PSSR_SPEED_1000MBPSIGP01E1000_PSSR_SPEED_1000MBPS 0xC000 igb_phy.h 　
31648
 IGP02E1000_PHY_CHANNEL_NUMIGP02E1000_PHY_CHANNEL_NUM 4 igb_phy.h 　
31649
 IGP02E1000_PHY_AGC_AIGP02E1000_PHY_AGC_A 0x11B1 igb_phy.h 　
31650
 IGP02E1000_PHY_AGC_BIGP02E1000_PHY_AGC_B 0x12B1 igb_phy.h 　
31651
 IGP02E1000_PHY_AGC_CIGP02E1000_PHY_AGC_C 0x14B1 igb_phy.h 　
31652
 IGP02E1000_PHY_AGC_DIGP02E1000_PHY_AGC_D 0x18B1 igb_phy.h 　
31653
 IGP02E1000_AGC_LENGTH_SHIFTIGP02E1000_AGC_LENGTH_SHIFT 9 igb_phy.h Course - 15:13, Fine - 12:9
31654
 IGP02E1000_AGC_LENGTH_MASKIGP02E1000_AGC_LENGTH_MASK 0x7F igb_phy.h 　
31655
 IGP02E1000_AGC_RANGEIGP02E1000_AGC_RANGE 15 igb_phy.h 　
31656
 IGP03E1000_PHY_MISC_CTRLIGP03E1000_PHY_MISC_CTRL 0x1B igb_phy.h 　
31657
 IGP03E1000_PHY_MISC_DUPLEX_MANUIGP03E1000_PHY_MISC_DUPLEX_MANU 0x1000 igb_phy.h Manually Set Duplex
31658
 E1000_CABLE_LENGTH_UNDEFINEDE1000_CABLE_LENGTH_UNDEFINED 0xFF igb_phy.h 　
31659
 E1000_KMRNCTRLSTA_OFFSETE1000_KMRNCTRLSTA_OFFSET 0x001F0000 igb_phy.h 　
31660
 E1000_KMRNCTRLSTA_OFFSET_SHIFTE1000_KMRNCTRLSTA_OFFSET_SHIFT 16 igb_phy.h 　
31661
 E1000_KMRNCTRLSTA_RENE1000_KMRNCTRLSTA_REN 0x00200000 igb_phy.h 　
31662
 E1000_KMRNCTRLSTA_DIAG_OFFSETE1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 igb_phy.h Kumeran Diagnostic
31663
 E1000_KMRNCTRLSTA_TIMEOUTSE1000_KMRNCTRLSTA_TIMEOUTS 0x4 igb_phy.h Kumeran Timeouts
31664
 E1000_KMRNCTRLSTA_INBAND_PARAME1000_KMRNCTRLSTA_INBAND_PARAM 0x9 igb_phy.h Kumeran InBand Parameters
31665
 E1000_KMRNCTRLSTA_DIAG_NELPBKE1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 igb_phy.h Nearend Loopback mode
31666
 IFE_PHY_EXTENDED_STATUS_CONTROLIFE_PHY_EXTENDED_STATUS_CONTROL 0x10 igb_phy.h 　
31667
 IFE_PHY_SPECIAL_CONTROLIFE_PHY_SPECIAL_CONTROL 0x11 igb_phy.h 100BaseTx PHY Special Control
31668
 IFE_PHY_SPECIAL_CONTROL_LEDIFE_PHY_SPECIAL_CONTROL_LED 0x1B igb_phy.h PHY Special and LED Control
31669
 IFE_PHY_MDIX_CONTROLIFE_PHY_MDIX_CONTROL 0x1C igb_phy.h MDI/MDI-X Control
31670
 IFE_PESC_POLARITY_REVERSEDIFE_PESC_POLARITY_REVERSED 0x0100 igb_phy.h 　
31671
 IFE_PSC_AUTO_POLARITY_DISABLEIFE_PSC_AUTO_POLARITY_DISABLE 0x0010 igb_phy.h 　
31672
 IFE_PSC_FORCE_POLARITYIFE_PSC_FORCE_POLARITY 0x0020 igb_phy.h 　
31673
 IFE_PSC_DISABLE_DYNAMIC_POWER_DIFE_PSC_DISABLE_DYNAMIC_POWER_D 0x0100 igb_phy.h 　
31674
 IFE_PSCL_PROBE_MODEIFE_PSCL_PROBE_MODE 0x0020 igb_phy.h 　
31675
 IFE_PSCL_PROBE_LEDS_OFFIFE_PSCL_PROBE_LEDS_OFF 0x0006 igb_phy.h Force LEDs 0 and 2 off
31676
 IFE_PSCL_PROBE_LEDS_ONIFE_PSCL_PROBE_LEDS_ON 0x0007 igb_phy.h Force LEDs 0 and 2 on
31677
 IFE_PMC_MDIX_STATUSIFE_PMC_MDIX_STATUS 0x0020 igb_phy.h 1=MDI-X, 0=MDI
31678
 IFE_PMC_FORCE_MDIXIFE_PMC_FORCE_MDIX 0x0040 igb_phy.h 1=force MDI-X, 0=force MDI
31679
 IFE_PMC_AUTO_MDIXIFE_PMC_AUTO_MDIX 0x0080 igb_phy.h 1=enable auto MDI/MDI-X, 0=disable
31680
 E1000_CTRLE1000_CTRL 0x00000 igb_regs.h Device Control - RW
31681
 E1000_CTRL_DUPE1000_CTRL_DUP 0x00004 igb_regs.h Device Control Duplicate (Shadow) - RW
31682
 E1000_STATUSE1000_STATUS 0x00008 igb_regs.h Device Status - RO
31683
 E1000_EECDE1000_EECD 0x00010 igb_regs.h EEPROM/Flash Control - RW
31684
 E1000_EERDE1000_EERD 0x00014 igb_regs.h EEPROM Read - RW
31685
 E1000_CTRL_EXTE1000_CTRL_EXT 0x00018 igb_regs.h Extended Device Control - RW
31686
 E1000_FLAE1000_FLA 0x0001C igb_regs.h Flash Access - RW
31687
 E1000_MDICE1000_MDIC 0x00020 igb_regs.h MDI Control - RW
31688
 E1000_SCTLE1000_SCTL 0x00024 igb_regs.h SerDes Control - RW
31689
 E1000_FCALE1000_FCAL 0x00028 igb_regs.h Flow Control Address Low - RW
31690
 E1000_FCAHE1000_FCAH 0x0002C igb_regs.h Flow Control Address High -RW
31691
 E1000_FEXTE1000_FEXT 0x0002C igb_regs.h Future Extended - RW
31692
 E1000_FEXTNVME1000_FEXTNVM 0x00028 igb_regs.h Future Extended NVM - RW
31693
 E1000_FCTE1000_FCT 0x00030 igb_regs.h Flow Control Type - RW
31694
 E1000_CONNSWE1000_CONNSW 0x00034 igb_regs.h Copper/Fiber switch control - RW
31695
 E1000_VETE1000_VET 0x00038 igb_regs.h VLAN Ether Type - RW
31696
 E1000_ICRE1000_ICR 0x000C0 igb_regs.h Interrupt Cause Read - R/clr
31697
 E1000_ITRE1000_ITR 0x000C4 igb_regs.h Interrupt Throttling Rate - RW
31698
 E1000_ICSE1000_ICS 0x000C8 igb_regs.h Interrupt Cause Set - WO
31699
 E1000_IMSE1000_IMS 0x000D0 igb_regs.h Interrupt Mask Set - RW
31700
 E1000_IMCE1000_IMC 0x000D8 igb_regs.h Interrupt Mask Clear - WO
31701
 E1000_IAME1000_IAM 0x000E0 igb_regs.h Interrupt Acknowledge Auto Mask
31702
 E1000_RCTLE1000_RCTL 0x00100 igb_regs.h Rx Control - RW
31703
 E1000_FCTTVE1000_FCTTV 0x00170 igb_regs.h Flow Control Transmit Timer Value - RW
31704
 E1000_TXCWE1000_TXCW 0x00178 igb_regs.h Tx Configuration Word - RW
31705
 E1000_RXCWE1000_RXCW 0x00180 igb_regs.h Rx Configuration Word - RO
31706
 E1000_EICRE1000_EICR 0x01580 igb_regs.h Ext. Interrupt Cause Read - R/clr
31707
 E1000_EICSE1000_EICS 0x01520 igb_regs.h Ext. Interrupt Cause Set - W0
31708
 E1000_EIMSE1000_EIMS 0x01524 igb_regs.h Ext. Interrupt Mask Set/Read - RW
31709
 E1000_EIMCE1000_EIMC 0x01528 igb_regs.h Ext. Interrupt Mask Clear - WO
31710
 E1000_EIACE1000_EIAC 0x0152C igb_regs.h Ext. Interrupt Auto Clear - RW
31711
 E1000_EIAME1000_EIAM 0x01530 igb_regs.h Ext. Interrupt Ack Auto Clear Mask - RW
31712
 E1000_GPIEE1000_GPIE 0x01514 igb_regs.h General Purpose Interrupt Enable - RW
31713
 E1000_IVAR0E1000_IVAR0 0x01700 igb_regs.h Interrupt Vector Allocation (array) - RW
31714
 E1000_IVAR_MISCE1000_IVAR_MISC 0x01740 igb_regs.h IVAR for "other" causes - RW
31715
 E1000_TCTLE1000_TCTL 0x00400 igb_regs.h Tx Control - RW
31716
 E1000_TCTL_EXTE1000_TCTL_EXT 0x00404 igb_regs.h Extended Tx Control - RW
31717
 E1000_TIPGE1000_TIPG 0x00410 igb_regs.h Tx Inter-packet gap -RW
31718
 E1000_TBTE1000_TBT 0x00448 igb_regs.h Tx Burst Timer - RW
31719
 E1000_AITE1000_AIT 0x00458 igb_regs.h Adaptive Interframe Spacing Throttle - RW
31720
 E1000_LEDCTLE1000_LEDCTL 0x00E00 igb_regs.h LED Control - RW
31721
 E1000_EXTCNF_CTRLE1000_EXTCNF_CTRL 0x00F00 igb_regs.h Extended Configuration Control
31722
 E1000_EXTCNF_SIZEE1000_EXTCNF_SIZE 0x00F08 igb_regs.h Extended Configuration Size
31723
 E1000_PHY_CTRLE1000_PHY_CTRL 0x00F10 igb_regs.h PHY Control Register in CSR
31724
 E1000_PBAE1000_PBA 0x01000 igb_regs.h Packet Buffer Allocation - RW
31725
 E1000_PBSE1000_PBS 0x01008 igb_regs.h Packet Buffer Size
31726
 E1000_EEMNGCTLE1000_EEMNGCTL 0x01010 igb_regs.h MNG EEprom Control
31727
 E1000_EEARBCE1000_EEARBC 0x01024 igb_regs.h EEPROM Auto Read Bus Control
31728
 E1000_FLASHTE1000_FLASHT 0x01028 igb_regs.h FLASH Timer Register
31729
 E1000_EEWRE1000_EEWR 0x0102C igb_regs.h EEPROM Write Register - RW
31730
 E1000_FLSWCTLE1000_FLSWCTL 0x01030 igb_regs.h FLASH control register
31731
 E1000_FLSWDATAE1000_FLSWDATA 0x01034 igb_regs.h FLASH data register
31732
 E1000_FLSWCNTE1000_FLSWCNT 0x01038 igb_regs.h FLASH Access Counter
31733
 E1000_FLOPE1000_FLOP 0x0103C igb_regs.h FLASH Opcode Register
31734
 E1000_I2CCMDE1000_I2CCMD 0x01028 igb_regs.h SFPI2C Command Register - RW
31735
 E1000_I2CPARAMSE1000_I2CPARAMS 0x0102C igb_regs.h SFPI2C Parameters Register - RW
31736
 E1000_WDSTPE1000_WDSTP 0x01040 igb_regs.h Watchdog Setup - RW
31737
 E1000_SWDSTSE1000_SWDSTS 0x01044 igb_regs.h SW Device Status - RW
31738
 E1000_FRTIMERE1000_FRTIMER 0x01048 igb_regs.h Free Running Timer - RW
31739
 E1000_TCPTIMERE1000_TCPTIMER 0x0104C igb_regs.h TCP Timer - RW
31740
 E1000_VPDDIAGE1000_VPDDIAG 0x01060 igb_regs.h VPD Diagnostic - RO
31741
 E1000_ICR_V2E1000_ICR_V2 0x01500 igb_regs.h Interrupt Cause - new location - RC
31742
 E1000_ICS_V2E1000_ICS_V2 0x01504 igb_regs.h Interrupt Cause Set - new location - WO
31743
 E1000_IMS_V2E1000_IMS_V2 0x01508 igb_regs.h Interrupt Mask Set/Read - new location - RW
31744
 E1000_IMC_V2E1000_IMC_V2 0x0150C igb_regs.h Interrupt Mask Clear - new location - WO
31745
 E1000_IAM_V2E1000_IAM_V2 0x01510 igb_regs.h Interrupt Ack Auto Mask - new location - RW
31746
 E1000_ERTE1000_ERT 0x02008 igb_regs.h Early Rx Threshold - RW
31747
 E1000_FCRTLE1000_FCRTL 0x02160 igb_regs.h Flow Control Receive Threshold Low - RW
31748
 E1000_FCRTHE1000_FCRTH 0x02168 igb_regs.h Flow Control Receive Threshold High - RW
31749
 E1000_PSRCTLE1000_PSRCTL 0x02170 igb_regs.h Packet Split Receive Control - RW
31750
 E1000_PBRTHE1000_PBRTH 0x02458 igb_regs.h PB Rx Arbitration Threshold - RW
31751
 E1000_FCRTVE1000_FCRTV 0x02460 igb_regs.h Flow Control Refresh Timer Value - RW
31752
 E1000_RDPUMBE1000_RDPUMB 0x025CC igb_regs.h DMA Rx Descriptor uC Mailbox - RW
31753
 E1000_RDPUADE1000_RDPUAD 0x025D0 igb_regs.h DMA Rx Descriptor uC Addr Command - RW
31754
 E1000_RDPUWDE1000_RDPUWD 0x025D4 igb_regs.h DMA Rx Descriptor uC Data Write - RW
31755
 E1000_RDPURDE1000_RDPURD 0x025D8 igb_regs.h DMA Rx Descriptor uC Data Read - RW
31756
 E1000_RDPUCTLE1000_RDPUCTL 0x025DC igb_regs.h DMA Rx Descriptor uC Control - RW
31757
 E1000_PBDIAGE1000_PBDIAG 0x02458 igb_regs.h Packet Buffer Diagnostic - RW
31758
 E1000_RXPBSE1000_RXPBS 0x02404 igb_regs.h Rx Packet Buffer Size - RW
31759
 E1000_RDTRE1000_RDTR 0x02820 igb_regs.h Rx Delay Timer - RW
31760
 E1000_RADVE1000_RADV 0x0282C igb_regs.h Rx Interrupt Absolute Delay Timer - RW
31761
 E1000_RSRPDE1000_RSRPD 0x02C00 igb_regs.h Rx Small Packet Detect - RW
31762
 E1000_RAIDE1000_RAID 0x02C08 igb_regs.h Receive Ack Interrupt Delay - RW
31763
 E1000_TXDMACE1000_TXDMAC 0x03000 igb_regs.h Tx DMA Control - RW
31764
 E1000_KABGTXDE1000_KABGTXD 0x03004 igb_regs.h AFE Band Gap Transmit Ref Data
31765
 E1000_PBSLACE1000_PBSLAC 0x03100 igb_regs.h Packet Buffer Slave Access Control
31766
 E1000_TXPBSE1000_TXPBS 0x03404 igb_regs.h Tx Packet Buffer Size - RW
31767
 E1000_TDFHE1000_TDFH 0x03410 igb_regs.h Tx Data FIFO Head - RW
31768
 E1000_TDFTE1000_TDFT 0x03418 igb_regs.h Tx Data FIFO Tail - RW
31769
 E1000_TDFHSE1000_TDFHS 0x03420 igb_regs.h Tx Data FIFO Head Saved - RW
31770
 E1000_TDFTSE1000_TDFTS 0x03428 igb_regs.h Tx Data FIFO Tail Saved - RW
31771
 E1000_TDFPCE1000_TDFPC 0x03430 igb_regs.h Tx Data FIFO Packet Count - RW
31772
 E1000_TDPUMBE1000_TDPUMB 0x0357C igb_regs.h DMA Tx Descriptor uC Mail Box - RW
31773
 E1000_TDPUADE1000_TDPUAD 0x03580 igb_regs.h DMA Tx Descriptor uC Addr Command - RW
31774
 E1000_TDPUWDE1000_TDPUWD 0x03584 igb_regs.h DMA Tx Descriptor uC Data Write - RW
31775
 E1000_TDPURDE1000_TDPURD 0x03588 igb_regs.h DMA Tx Descriptor uC Data Read - RW
31776
 E1000_TDPUCTLE1000_TDPUCTL 0x0358C igb_regs.h DMA Tx Descriptor uC Control - RW
31777
 E1000_DTXCTLE1000_DTXCTL 0x03590 igb_regs.h DMA Tx Control - RW
31778
 E1000_DTXTCPFLGLE1000_DTXTCPFLGL 0x0359C igb_regs.h DMA Tx Control flag low - RW
31779
 E1000_DTXTCPFLGHE1000_DTXTCPFLGH 0x035A0 igb_regs.h DMA Tx Control flag high - RW
31780
 E1000_DTXMXSZRQE1000_DTXMXSZRQ 0x03540 igb_regs.h DMA Tx Max Total Allow Size Requests - RW
31781
 E1000_TIDVE1000_TIDV 0x03820 igb_regs.h Tx Interrupt Delay Value - RW
31782
 E1000_TADVE1000_TADV 0x0382C igb_regs.h Tx Interrupt Absolute Delay Val - RW
31783
 E1000_TSPMTE1000_TSPMT 0x03830 igb_regs.h TCP Segmentation PAD & Min Threshold - RW
31784
 E1000_CRCERRSE1000_CRCERRS 0x04000 igb_regs.h CRC Error Count - R/clr
31785
 E1000_ALGNERRCE1000_ALGNERRC 0x04004 igb_regs.h Alignment Error Count - R/clr
31786
 E1000_SYMERRSE1000_SYMERRS 0x04008 igb_regs.h Symbol Error Count - R/clr
31787
 E1000_RXERRCE1000_RXERRC 0x0400C igb_regs.h Receive Error Count - R/clr
31788
 E1000_MPCE1000_MPC 0x04010 igb_regs.h Missed Packet Count - R/clr
31789
 E1000_SCCE1000_SCC 0x04014 igb_regs.h Single Collision Count - R/clr
31790
 E1000_ECOLE1000_ECOL 0x04018 igb_regs.h Excessive Collision Count - R/clr
31791
 E1000_MCCE1000_MCC 0x0401C igb_regs.h Multiple Collision Count - R/clr
31792
 E1000_LATECOLE1000_LATECOL 0x04020 igb_regs.h Late Collision Count - R/clr
31793
 E1000_COLCE1000_COLC 0x04028 igb_regs.h Collision Count - R/clr
31794
 E1000_DCE1000_DC 0x04030 igb_regs.h Defer Count - R/clr
31795
 E1000_TNCRSE1000_TNCRS 0x04034 igb_regs.h Tx-No CRS - R/clr
31796
 E1000_SECE1000_SEC 0x04038 igb_regs.h Sequence Error Count - R/clr
31797
 E1000_CEXTERRE1000_CEXTERR 0x0403C igb_regs.h Carrier Extension Error Count - R/clr
31798
 E1000_RLECE1000_RLEC 0x04040 igb_regs.h Receive Length Error Count - R/clr
31799
 E1000_XONRXCE1000_XONRXC 0x04048 igb_regs.h XON Rx Count - R/clr
31800
 E1000_XONTXCE1000_XONTXC 0x0404C igb_regs.h XON Tx Count - R/clr
31801
 E1000_XOFFRXCE1000_XOFFRXC 0x04050 igb_regs.h XOFF Rx Count - R/clr
31802
 E1000_XOFFTXCE1000_XOFFTXC 0x04054 igb_regs.h XOFF Tx Count - R/clr
31803
 E1000_FCRUCE1000_FCRUC 0x04058 igb_regs.h Flow Control Rx Unsupported Count- R/clr
31804
 E1000_PRC64E1000_PRC64 0x0405C igb_regs.h Packets Rx (64 bytes) - R/clr
31805
 E1000_PRC127E1000_PRC127 0x04060 igb_regs.h Packets Rx (65-127 bytes) - R/clr
31806
 E1000_PRC255E1000_PRC255 0x04064 igb_regs.h Packets Rx (128-255 bytes) - R/clr
31807
 E1000_PRC511E1000_PRC511 0x04068 igb_regs.h Packets Rx (255-511 bytes) - R/clr
31808
 E1000_PRC1023E1000_PRC1023 0x0406C igb_regs.h Packets Rx (512-1023 bytes) - R/clr
31809
 E1000_PRC1522E1000_PRC1522 0x04070 igb_regs.h Packets Rx (1024-1522 bytes) - R/clr
31810
 E1000_GPRCE1000_GPRC 0x04074 igb_regs.h Good Packets Rx Count - R/clr
31811
 E1000_BPRCE1000_BPRC 0x04078 igb_regs.h Broadcast Packets Rx Count - R/clr
31812
 E1000_MPRCE1000_MPRC 0x0407C igb_regs.h Multicast Packets Rx Count - R/clr
31813
 E1000_GPTCE1000_GPTC 0x04080 igb_regs.h Good Packets Tx Count - R/clr
31814
 E1000_GORCLE1000_GORCL 0x04088 igb_regs.h Good Octets Rx Count Low - R/clr
31815
 E1000_GORCHE1000_GORCH 0x0408C igb_regs.h Good Octets Rx Count High - R/clr
31816
 E1000_GOTCLE1000_GOTCL 0x04090 igb_regs.h Good Octets Tx Count Low - R/clr
31817
 E1000_GOTCHE1000_GOTCH 0x04094 igb_regs.h Good Octets Tx Count High - R/clr
31818
 E1000_RNBCE1000_RNBC 0x040A0 igb_regs.h Rx No Buffers Count - R/clr
31819
 E1000_RUCE1000_RUC 0x040A4 igb_regs.h Rx Undersize Count - R/clr
31820
 E1000_RFCE1000_RFC 0x040A8 igb_regs.h Rx Fragment Count - R/clr
31821
 E1000_ROCE1000_ROC 0x040AC igb_regs.h Rx Oversize Count - R/clr
31822
 E1000_RJCE1000_RJC 0x040B0 igb_regs.h Rx Jabber Count - R/clr
31823
 E1000_MGTPRCE1000_MGTPRC 0x040B4 igb_regs.h Management Packets Rx Count - R/clr
31824
 E1000_MGTPDCE1000_MGTPDC 0x040B8 igb_regs.h Management Packets Dropped Count - R/clr
31825
 E1000_MGTPTCE1000_MGTPTC 0x040BC igb_regs.h Management Packets Tx Count - R/clr
31826
 E1000_TORLE1000_TORL 0x040C0 igb_regs.h Total Octets Rx Low - R/clr
31827
 E1000_TORHE1000_TORH 0x040C4 igb_regs.h Total Octets Rx High - R/clr
31828
 E1000_TOTLE1000_TOTL 0x040C8 igb_regs.h Total Octets Tx Low - R/clr
31829
 E1000_TOTHE1000_TOTH 0x040CC igb_regs.h Total Octets Tx High - R/clr
31830
 E1000_TPRE1000_TPR 0x040D0 igb_regs.h Total Packets Rx - R/clr
31831
 E1000_TPTE1000_TPT 0x040D4 igb_regs.h Total Packets Tx - R/clr
31832
 E1000_PTC64E1000_PTC64 0x040D8 igb_regs.h Packets Tx (64 bytes) - R/clr
31833
 E1000_PTC127E1000_PTC127 0x040DC igb_regs.h Packets Tx (65-127 bytes) - R/clr
31834
 E1000_PTC255E1000_PTC255 0x040E0 igb_regs.h Packets Tx (128-255 bytes) - R/clr
31835
 E1000_PTC511E1000_PTC511 0x040E4 igb_regs.h Packets Tx (256-511 bytes) - R/clr
31836
 E1000_PTC1023E1000_PTC1023 0x040E8 igb_regs.h Packets Tx (512-1023 bytes) - R/clr
31837
 E1000_PTC1522E1000_PTC1522 0x040EC igb_regs.h Packets Tx (1024-1522 Bytes) - R/clr
31838
 E1000_MPTCE1000_MPTC 0x040F0 igb_regs.h Multicast Packets Tx Count - R/clr
31839
 E1000_BPTCE1000_BPTC 0x040F4 igb_regs.h Broadcast Packets Tx Count - R/clr
31840
 E1000_TSCTCE1000_TSCTC 0x040F8 igb_regs.h TCP Segmentation Context Tx - R/clr
31841
 E1000_TSCTFCE1000_TSCTFC 0x040FC igb_regs.h TCP Segmentation Context Tx Fail - R/clr
31842
 E1000_IACE1000_IAC 0x04100 igb_regs.h Interrupt Assertion Count
31843
 E1000_ICRXPTCE1000_ICRXPTC 0x04104 igb_regs.h Interrupt Cause Rx Pkt Timer Expire Count
31844
 E1000_ICRXATCE1000_ICRXATC 0x04108 igb_regs.h Interrupt Cause Rx Abs Timer Expire Count
31845
 E1000_ICTXPTCE1000_ICTXPTC 0x0410C igb_regs.h Interrupt Cause Tx Pkt Timer Expire Count
31846
 E1000_ICTXATCE1000_ICTXATC 0x04110 igb_regs.h Interrupt Cause Tx Abs Timer Expire Count
31847
 E1000_ICTXQECE1000_ICTXQEC 0x04118 igb_regs.h Interrupt Cause Tx Queue Empty Count
31848
 E1000_ICTXQMTCE1000_ICTXQMTC 0x0411C igb_regs.h Interrupt Cause Tx Queue Min Thresh Count
31849
 E1000_ICRXDMTCE1000_ICRXDMTC 0x04120 igb_regs.h Interrupt Cause Rx Desc Min Thresh Count
31850
 E1000_ICRXOCE1000_ICRXOC 0x04124 igb_regs.h Interrupt Cause Receiver Overrun Count
31851
 E1000_LSECTXUTE1000_LSECTXUT 0x04300 igb_regs.h LinkSec Tx Untagged Packet Count - OutPktsUntagged
31852
 E1000_LSECTXPKTEE1000_LSECTXPKTE 0x04304 igb_regs.h LinkSec Encrypted Tx Packets Count - OutPktsEncrypted
31853
 E1000_LSECTXPKTPE1000_LSECTXPKTP 0x04308 igb_regs.h LinkSec Protected Tx Packet Count - OutPktsProtected
31854
 E1000_LSECTXOCTEE1000_LSECTXOCTE 0x0430C igb_regs.h LinkSec Encrypted Tx Octets Count - OutOctetsEncrypted
31855
 E1000_LSECTXOCTPE1000_LSECTXOCTP 0x04310 igb_regs.h LinkSec Protected Tx Octets Count - OutOctetsProtected
31856
 E1000_LSECRXUTE1000_LSECRXUT 0x04314 igb_regs.h LinkSec Untagged non-Strict Rx Packet Count - InPktsUntagged/InPktsNoTag
31857
 E1000_LSECRXOCTDE1000_LSECRXOCTD 0x0431C igb_regs.h LinkSec Rx Octets Decrypted Count - InOctetsDecrypted
31858
 E1000_LSECRXOCTVE1000_LSECRXOCTV 0x04320 igb_regs.h LinkSec Rx Octets Validated - InOctetsValidated
31859
 E1000_LSECRXBADE1000_LSECRXBAD 0x04324 igb_regs.h LinkSec Rx Bad Tag - InPktsBadTag
31860
 E1000_LSECRXNOSCIE1000_LSECRXNOSCI 0x04328 igb_regs.h LinkSec Rx Packet No SCI Count - InPktsNoSci
31861
 E1000_LSECRXUNSCIE1000_LSECRXUNSCI 0x0432C igb_regs.h LinkSec Rx Packet Unknown SCI Count - InPktsUnknownSci
31862
 E1000_LSECRXUNCHE1000_LSECRXUNCH 0x04330 igb_regs.h LinkSec Rx Unchecked Packets Count - InPktsUnchecked
31863
 E1000_LSECRXDELAYE1000_LSECRXDELAY 0x04340 igb_regs.h LinkSec Rx Delayed Packet Count - InPktsDelayed
31864
 E1000_LSECRXLATEE1000_LSECRXLATE 0x04350 igb_regs.h LinkSec Rx Late Packets Count - InPktsLate
31865
 E1000_LSECRXUNSAE1000_LSECRXUNSA 0x043C0 igb_regs.h LinkSec Rx Unused SA Count - InPktsUnusedSa
31866
 E1000_LSECRXNUSAE1000_LSECRXNUSA 0x043D0 igb_regs.h LinkSec Rx Not Using SA Count - InPktsNotUsingSa
31867
 E1000_LSECTXCAPE1000_LSECTXCAP 0x0B000 igb_regs.h LinkSec Tx Capabilities Register - RO
31868
 E1000_LSECRXCAPE1000_LSECRXCAP 0x0B300 igb_regs.h LinkSec Rx Capabilities Register - RO
31869
 E1000_LSECTXCTRLE1000_LSECTXCTRL 0x0B004 igb_regs.h LinkSec Tx Control - RW
31870
 E1000_LSECRXCTRLE1000_LSECRXCTRL 0x0B304 igb_regs.h LinkSec Rx Control - RW
31871
 E1000_LSECTXSCLE1000_LSECTXSCL 0x0B008 igb_regs.h LinkSec Tx SCI Low - RW
31872
 E1000_LSECTXSCHE1000_LSECTXSCH 0x0B00C igb_regs.h LinkSec Tx SCI High - RW
31873
 E1000_LSECTXSAE1000_LSECTXSA 0x0B010 igb_regs.h LinkSec Tx SA0 - RW
31874
 E1000_LSECTXPN0E1000_LSECTXPN0 0x0B018 igb_regs.h LinkSec Tx SA PN 0 - RW
31875
 E1000_LSECTXPN1E1000_LSECTXPN1 0x0B01C igb_regs.h LinkSec Tx SA PN 1 - RW
31876
 E1000_LSECRXSCLE1000_LSECRXSCL 0x0B3D0 igb_regs.h LinkSec Rx SCI Low - RW
31877
 E1000_LSECRXSCHE1000_LSECRXSCH 0x0B3E0 igb_regs.h LinkSec Rx SCI High - RW
31878
 E1000_SSVPCE1000_SSVPC 0x041A0 igb_regs.h Switch Security Violation Packet Count
31879
 E1000_IPSCTRLE1000_IPSCTRL 0xB430 igb_regs.h IpSec Control Register
31880
 E1000_IPSRXCMDE1000_IPSRXCMD 0x0B408 igb_regs.h IPSec Rx Command Register - RW
31881
 E1000_IPSRXIDXE1000_IPSRXIDX 0x0B400 igb_regs.h IPSec Rx Index - RW
31882
 E1000_IPSRXSALTE1000_IPSRXSALT 0x0B404 igb_regs.h IPSec Rx Salt - RW
31883
 E1000_IPSRXSPIE1000_IPSRXSPI 0x0B40C igb_regs.h IPSec Rx SPI - RW
31884
 E1000_IPSTXSALTE1000_IPSTXSALT 0x0B454 igb_regs.h IPSec Tx Salt - RW
31885
 E1000_IPSTXIDXE1000_IPSTXIDX 0x0B450 igb_regs.h IPSec Tx SA IDX - RW
31886
 E1000_PCS_CFG0E1000_PCS_CFG0 0x04200 igb_regs.h PCS Configuration 0 - RW
31887
 E1000_PCS_LCTLE1000_PCS_LCTL 0x04208 igb_regs.h PCS Link Control - RW
31888
 E1000_PCS_LSTATE1000_PCS_LSTAT 0x0420C igb_regs.h PCS Link Status - RO
31889
 E1000_CBTMPCE1000_CBTMPC 0x0402C igb_regs.h Circuit Breaker Tx Packet Count
31890
 E1000_HTDPMCE1000_HTDPMC 0x0403C igb_regs.h Host Transmit Discarded Packets
31891
 E1000_CBRDPCE1000_CBRDPC 0x04044 igb_regs.h Circuit Breaker Rx Dropped Count
31892
 E1000_CBRMPCE1000_CBRMPC 0x040FC igb_regs.h Circuit Breaker Rx Packet Count
31893
 E1000_RPTHCE1000_RPTHC 0x04104 igb_regs.h Rx Packets To Host
31894
 E1000_HGPTCE1000_HGPTC 0x04118 igb_regs.h Host Good Packets Tx Count
31895
 E1000_HTCBDPCE1000_HTCBDPC 0x04124 igb_regs.h Host Tx Circuit Breaker Dropped Count
31896
 E1000_HGORCLE1000_HGORCL 0x04128 igb_regs.h Host Good Octets Received Count Low
31897
 E1000_HGORCHE1000_HGORCH 0x0412C igb_regs.h Host Good Octets Received Count High
31898
 E1000_HGOTCLE1000_HGOTCL 0x04130 igb_regs.h Host Good Octets Transmit Count Low
31899
 E1000_HGOTCHE1000_HGOTCH 0x04134 igb_regs.h Host Good Octets Transmit Count High
31900
 E1000_LENERRSE1000_LENERRS 0x04138 igb_regs.h Length Errors Count
31901
 E1000_SCVPCE1000_SCVPC 0x04228 igb_regs.h SerDes/SGMII Code Violation Pkt Count
31902
 E1000_HRMPCE1000_HRMPC 0x0A018 igb_regs.h Header Redirection Missed Packet Count
31903
 E1000_PCS_ANADVE1000_PCS_ANADV 0x04218 igb_regs.h AN advertisement - RW
31904
 E1000_PCS_LPABE1000_PCS_LPAB 0x0421C igb_regs.h Link Partner Ability - RW
31905
 E1000_PCS_NPTXE1000_PCS_NPTX 0x04220 igb_regs.h AN Next Page Transmit - RW
31906
 E1000_PCS_LPABNPE1000_PCS_LPABNP 0x04224 igb_regs.h Link Partner Ability Next Page - RW
31907
 E1000_1GSTAT_RCVE1000_1GSTAT_RCV 0x04228 igb_regs.h 1GSTAT Code Violation Packet Count - RW
31908
 E1000_RXCSUME1000_RXCSUM 0x05000 igb_regs.h Rx Checksum Control - RW
31909
 E1000_RLPMLE1000_RLPML 0x05004 igb_regs.h Rx Long Packet Max Length
31910
 E1000_RFCTLE1000_RFCTL 0x05008 igb_regs.h Receive Filter Control
31911
 E1000_MTAE1000_MTA 0x05200 igb_regs.h Multicast Table Array - RW Array
31912
 E1000_RAE1000_RA 0x05400 igb_regs.h Receive Address - RW Array
31913
 E1000_RA2E1000_RA2 0x054E0 igb_regs.h 2nd half of receive address array - RW Array
31914
 E1000_VFTAE1000_VFTA 0x05600 igb_regs.h VLAN Filter Table Array - RW Array
31915
 E1000_VT_CTLE1000_VT_CTL 0x0581C igb_regs.h VMDq Control - RW
31916
 E1000_VFQA0E1000_VFQA0 0x0B000 igb_regs.h VLAN Filter Queue Array 0 - RW Array
31917
 E1000_VFQA1E1000_VFQA1 0x0B200 igb_regs.h VLAN Filter Queue Array 1 - RW Array
31918
 E1000_WUCE1000_WUC 0x05800 igb_regs.h Wakeup Control - RW
31919
 E1000_WUFCE1000_WUFC 0x05808 igb_regs.h Wakeup Filter Control - RW
31920
 E1000_WUSE1000_WUS 0x05810 igb_regs.h Wakeup Status - RO
31921
 E1000_MANCE1000_MANC 0x05820 igb_regs.h Management Control - RW
31922
 E1000_IPAVE1000_IPAV 0x05838 igb_regs.h IP Address Valid - RW
31923
 E1000_IP4ATE1000_IP4AT 0x05840 igb_regs.h IPv4 Address Table - RW Array
31924
 E1000_IP6ATE1000_IP6AT 0x05880 igb_regs.h IPv6 Address Table - RW Array
31925
 E1000_WUPLE1000_WUPL 0x05900 igb_regs.h Wakeup Packet Length - RW
31926
 E1000_WUPME1000_WUPM 0x05A00 igb_regs.h Wakeup Packet Memory - RO A
31927
 E1000_PBACLE1000_PBACL 0x05B68 igb_regs.h MSIx PBA Clear - Read/Write 1's to clear
31928
 E1000_FFLTE1000_FFLT 0x05F00 igb_regs.h Flexible Filter Length Table - RW Array
31929
 E1000_HOST_IFE1000_HOST_IF 0x08800 igb_regs.h Host Interface
31930
 E1000_FFMTE1000_FFMT 0x09000 igb_regs.h Flexible Filter Mask Table - RW Array
31931
 E1000_FFVTE1000_FFVT 0x09800 igb_regs.h Flexible Filter Value Table - RW Array
31932
 E1000_KMRNCTRLSTAE1000_KMRNCTRLSTA 0x00034 igb_regs.h MAC-PHY interface - RW
31933
 E1000_MDPHYAE1000_MDPHYA 0x0003C igb_regs.h PHY address - RW
31934
 E1000_MANC2HE1000_MANC2H 0x05860 igb_regs.h Management Control To Host - RW
31935
 E1000_SW_FW_SYNCE1000_SW_FW_SYNC 0x05B5C igb_regs.h Software-Firmware Synchronization - RW
31936
 E1000_CCMCTLE1000_CCMCTL 0x05B48 igb_regs.h CCM Control Register
31937
 E1000_GIOCTLE1000_GIOCTL 0x05B44 igb_regs.h GIO Analog Control Register
31938
 E1000_SCCTLE1000_SCCTL 0x05B4C igb_regs.h PCIc PLL Configuration Register
31939
 E1000_GCRE1000_GCR 0x05B00 igb_regs.h PCI-Ex Control
31940
 E1000_GCR2E1000_GCR2 0x05B64 igb_regs.h PCI-Ex Control #2
31941
 E1000_GSCL_1E1000_GSCL_1 0x05B10 igb_regs.h PCI-Ex Statistic Control #1
31942
 E1000_GSCL_2E1000_GSCL_2 0x05B14 igb_regs.h PCI-Ex Statistic Control #2
31943
 E1000_GSCL_3E1000_GSCL_3 0x05B18 igb_regs.h PCI-Ex Statistic Control #3
31944
 E1000_GSCL_4E1000_GSCL_4 0x05B1C igb_regs.h PCI-Ex Statistic Control #4
31945
 E1000_FACTPSE1000_FACTPS 0x05B30 igb_regs.h Function Active and Power State to MNG
31946
 E1000_SWSME1000_SWSM 0x05B50 igb_regs.h SW Semaphore
31947
 E1000_FWSME1000_FWSM 0x05B54 igb_regs.h FW Semaphore
31948
 E1000_SWSM2E1000_SWSM2 0x05B58 igb_regs.h Driver-only SW semaphore (not used by BOOT agents)
31949
 E1000_DCA_IDE1000_DCA_ID 0x05B70 igb_regs.h DCA Requester ID Information - RO
31950
 E1000_DCA_CTRLE1000_DCA_CTRL 0x05B74 igb_regs.h DCA Control - RW
31951
 E1000_FFLT_DBGE1000_FFLT_DBG 0x05F04 igb_regs.h Debug Register
31952
 E1000_HICRE1000_HICR 0x08F00 igb_regs.h Host Interface Control
31953
 E1000_CPUVECE1000_CPUVEC 0x02C10 igb_regs.h CPU Vector Register - RW
31954
 E1000_MRQCE1000_MRQC 0x05818 igb_regs.h Multiple Receive Control - RW
31955
 E1000_IMIRVPE1000_IMIRVP 0x05AC0 igb_regs.h Immediate Interrupt Rx VLAN Priority - RW
31956
 E1000_MSIXPBAE1000_MSIXPBA 0x0E000 igb_regs.h MSI-X Pending bit array
31957
 E1000_RSSIME1000_RSSIM 0x05864 igb_regs.h RSS Interrupt Mask
31958
 E1000_RSSIRE1000_RSSIR 0x05868 igb_regs.h RSS Interrupt Request
31959
 E1000_SWPBSE1000_SWPBS 0x03004 igb_regs.h Switch Packet Buffer Size - RW
31960
 E1000_MBVFICRE1000_MBVFICR 0x00C80 igb_regs.h Mailbox VF Cause - RWC
31961
 E1000_MBVFIMRE1000_MBVFIMR 0x00C84 igb_regs.h Mailbox VF int Mask - RW
31962
 E1000_VFLREE1000_VFLRE 0x00C88 igb_regs.h VF Register Events - RWC
31963
 E1000_VFREE1000_VFRE 0x00C8C igb_regs.h VF Receive Enables
31964
 E1000_VFTEE1000_VFTE 0x00C90 igb_regs.h VF Transmit Enables
31965
 E1000_QDEE1000_QDE 0x02408 igb_regs.h Queue Drop Enable - RW
31966
 E1000_DTXSWCE1000_DTXSWC 0x03500 igb_regs.h DMA Tx Switch Control - RW
31967
 E1000_RPLOLRE1000_RPLOLR 0x05AF0 igb_regs.h Replication Offload - RW
31968
 E1000_UTAE1000_UTA 0x0A000 igb_regs.h Unicast Table Array - RW
31969
 E1000_IOVTCLE1000_IOVTCL 0x05BBC igb_regs.h IOV Control Register
31970
 E1000_VMRCTLE1000_VMRCTL 0X05D80 igb_regs.h Virtual Mirror Rule Control
31971
 E1000_TSYNCRXCTLE1000_TSYNCRXCTL 0x0B620 igb_regs.h Rx Time Sync Control register - RW
31972
 E1000_TSYNCTXCTLE1000_TSYNCTXCTL 0x0B614 igb_regs.h Tx Time Sync Control register - RW
31973
 E1000_TSYNCRXCFGE1000_TSYNCRXCFG 0x05F50 igb_regs.h Time Sync Rx Configuration - RW
31974
 E1000_RXSTMPLE1000_RXSTMPL 0x0B624 igb_regs.h Rx timestamp Low - RO
31975
 E1000_RXSTMPHE1000_RXSTMPH 0x0B628 igb_regs.h Rx timestamp High - RO
31976
 E1000_RXSATRLE1000_RXSATRL 0x0B62C igb_regs.h Rx timestamp attribute low - RO
31977
 E1000_RXSATRHE1000_RXSATRH 0x0B630 igb_regs.h Rx timestamp attribute high - RO
31978
 E1000_TXSTMPLE1000_TXSTMPL 0x0B618 igb_regs.h Tx timestamp value Low - RO
31979
 E1000_TXSTMPHE1000_TXSTMPH 0x0B61C igb_regs.h Tx timestamp value High - RO
31980
 E1000_SYSTIMLE1000_SYSTIML 0x0B600 igb_regs.h System time register Low - RO
31981
 E1000_SYSTIMHE1000_SYSTIMH 0x0B604 igb_regs.h System time register High - RO
31982
 E1000_TIMINCAE1000_TIMINCA 0x0B608 igb_regs.h Increment attributes register - RW
31983
 E1000_RTTDCSE1000_RTTDCS 0x3600 igb_regs.h Reedtown Tx Desc plane control and status
31984
 E1000_RTTPCSE1000_RTTPCS 0x3474 igb_regs.h Reedtown Tx Packet Plane control and status
31985
 E1000_RTRPCSE1000_RTRPCS 0x2474 igb_regs.h Rx packet plane control and status
31986
 E1000_RTRUP2TCE1000_RTRUP2TC 0x05AC4 igb_regs.h Rx User Priority to Traffic Class
31987
 E1000_RTTUP2TCE1000_RTTUP2TC 0x0418 igb_regs.h Transmit User Priority to Traffic Class
31988
 E1000_RTTDQSELE1000_RTTDQSEL 0x3604 igb_regs.h Tx Desc Plane Queue Select
31989
 E1000_RTTDVMRCE1000_RTTDVMRC 0x3608 igb_regs.h Tx Desc Plane VM Rate-Scheduler Config
31990
 E1000_RTTDVMRSE1000_RTTDVMRS 0x360C igb_regs.h Tx Desc Plane VM Rate-Scheduler Status
31991
 E1000_RTTBCNRCE1000_RTTBCNRC 0x36B0 igb_regs.h Tx BCN Rate-Scheduler Config
31992
 E1000_RTTBCNRSE1000_RTTBCNRS 0x36B4 igb_regs.h Tx BCN Rate-Scheduler Status
31993
 E1000_RTTBCNCRE1000_RTTBCNCR 0xB200 igb_regs.h Tx BCN Control Register
31994
 E1000_RTTBCNTGE1000_RTTBCNTG 0x35A4 igb_regs.h Tx BCN Tagging
31995
 E1000_RTTBCNCPE1000_RTTBCNCP 0xB208 igb_regs.h Tx BCN Congestion point
31996
 E1000_RTRBCNCRE1000_RTRBCNCR 0xB20C igb_regs.h Rx BCN Control Register
31997
 E1000_RTTBCNRDE1000_RTTBCNRD 0x36B8 igb_regs.h Tx BCN Rate Drift
31998
 E1000_PFCTOPE1000_PFCTOP 0x1080 igb_regs.h Priority Flow Control Type and Opcode
31999
 E1000_RTTBCNIDXE1000_RTTBCNIDX 0xB204 igb_regs.h Tx BCN Congestion Point
32000
 E1000_RTTBCNACHE1000_RTTBCNACH 0x0B214 igb_regs.h Tx BCN Control High
32001
 E1000_RTTBCNACLE1000_RTTBCNACL 0x0B210 igb_regs.h Tx BCN Control Low
32002
 PHN_MAX_NUM_PORTSPHN_MAX_NUM_PORTS 8 phantom.c 　
32003
 PHN_CMDPEG_INIT_TIMEOUT_SECPHN_CMDPEG_INIT_TIMEOUT_SEC 50 phantom.c 　
32004
 PHN_RCVPEG_INIT_TIMEOUT_SECPHN_RCVPEG_INIT_TIMEOUT_SEC 2 phantom.c 　
32005
 PHN_ISSUE_CMD_TIMEOUT_MSPHN_ISSUE_CMD_TIMEOUT_MS 2000 phantom.c 　
32006
 PHN_TEST_MEM_TIMEOUT_MSPHN_TEST_MEM_TIMEOUT_MS 100 phantom.c 　
32007
 PHN_CLP_CMD_TIMEOUT_MSPHN_CLP_CMD_TIMEOUT_MS 500 phantom.c 　
32008
 PHN_LINK_POLL_FREQUENCYPHN_LINK_POLL_FREQUENCY 4096 phantom.c 　
32009
 PHN_NUM_RDSPHN_NUM_RDS 32 phantom.c 　
32010
 PHN_RDS_MAX_FILLPHN_RDS_MAX_FILL 16 phantom.c 　
32011
 PHN_RX_BUFSIZEPHN_RX_BUFSIZE ( 32 + \ ETH_FRAME_LEN ) phantom.c 　
32012
 PHN_NUM_SDSPHN_NUM_SDS 32 phantom.c 　
32013
 PHN_NUM_CDSPHN_NUM_CDS 8 phantom.c 　
32014
 PHN_CLP_TAG_MAGICPHN_CLP_TAG_MAGIC 0xc19c1900UL phantom.c 　
32015
 PHN_CLP_TAG_MAGIC_MASKPHN_CLP_TAG_MAGIC_MASK 0xffffff00UL phantom.c 　
32016
 PHN_CLP_BLKSIZEPHN_CLP_BLKSIZE ( sizeof ( union phantom_clp_data ) ) phantom.c 　
32017
 NX_CDRP_CLEARNX_CDRP_CLEAR 0x00000000 nxhal_nic_interface.h 　
32018
 NX_CDRP_CMD_BITNX_CDRP_CMD_BIT 0x80000000 nxhal_nic_interface.h 　
32019
 NX_CDRP_RSP_OKNX_CDRP_RSP_OK 0x00000001 nxhal_nic_interface.h 　
32020
 NX_CDRP_RSP_FAILNX_CDRP_RSP_FAIL 0x00000002 nxhal_nic_interface.h 　
32021
 NX_CDRP_RSP_TIMEOUTNX_CDRP_RSP_TIMEOUT 0x00000003 nxhal_nic_interface.h 　
32022
 NX_CDRP_CMD_SUBMIT_CAPABILITIESNX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 nxhal_nic_interface.h 　
32023
 NX_CDRP_CMD_READ_MAX_RDS_PER_CTNX_CDRP_CMD_READ_MAX_RDS_PER_CT 0x00000002 nxhal_nic_interface.h 　
32024
 NX_CDRP_CMD_READ_MAX_SDS_PER_CTNX_CDRP_CMD_READ_MAX_SDS_PER_CT 0x00000003 nxhal_nic_interface.h 　
32025
 NX_CDRP_CMD_READ_MAX_RULES_PER_NX_CDRP_CMD_READ_MAX_RULES_PER_ 0x00000004 nxhal_nic_interface.h 　
32026
 NX_CDRP_CMD_READ_MAX_RX_CTXNX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 nxhal_nic_interface.h 　
32027
 NX_CDRP_CMD_READ_MAX_TX_CTXNX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 nxhal_nic_interface.h 　
32028
 NX_CDRP_CMD_CREATE_RX_CTXNX_CDRP_CMD_CREATE_RX_CTX 0x00000007 nxhal_nic_interface.h 　
32029
 NX_CDRP_CMD_DESTROY_RX_CTXNX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 nxhal_nic_interface.h 　
32030
 NX_CDRP_CMD_CREATE_TX_CTXNX_CDRP_CMD_CREATE_TX_CTX 0x00000009 nxhal_nic_interface.h 　
32031
 NX_CDRP_CMD_DESTROY_TX_CTXNX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a nxhal_nic_interface.h 　
32032
 NX_CDRP_CMD_SETUP_STATISTICSNX_CDRP_CMD_SETUP_STATISTICS 0x0000000e nxhal_nic_interface.h 　
32033
 NX_CDRP_CMD_GET_STATISTICSNX_CDRP_CMD_GET_STATISTICS 0x0000000f nxhal_nic_interface.h 　
32034
 NX_CDRP_CMD_DELETE_STATISTICSNX_CDRP_CMD_DELETE_STATISTICS 0x00000010 nxhal_nic_interface.h 　
32035
 NX_CDRP_CMD_MAXNX_CDRP_CMD_MAX 0x00000011 nxhal_nic_interface.h 　
32036
 NX_CAP0_LEGACY_CONTEXTNX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) nxhal_nic_interface.h 　
32037
 NX_CAP0_MULTI_CONTEXTNX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) nxhal_nic_interface.h 　
32038
 NX_CAP0_LEGACY_MNNX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) nxhal_nic_interface.h 　
32039
 NX_CAP0_LEGACY_MSNX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) nxhal_nic_interface.h 　
32040
 NX_CAP0_CUT_THROUGHNX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) nxhal_nic_interface.h 　
32041
 NX_CAP0_LRONX_CAP0_LRO NX_CAP_BIT(0, 5) nxhal_nic_interface.h 　
32042
 NX_CAP0_LSONX_CAP0_LSO NX_CAP_BIT(0, 6) nxhal_nic_interface.h 　
32043
 NX_CAP1_NICNX_CAP1_NIC NX_CAP_BIT(1, 0) nxhal_nic_interface.h 　
32044
 NX_CAP1_PXENX_CAP1_PXE NX_CAP_BIT(1, 1) nxhal_nic_interface.h 　
32045
 NX_CAP1_CHIMNEYNX_CAP1_CHIMNEY NX_CAP_BIT(1, 2) nxhal_nic_interface.h 　
32046
 NX_CAP1_LSANX_CAP1_LSA NX_CAP_BIT(1, 3) nxhal_nic_interface.h 　
32047
 NX_CAP1_RDMANX_CAP1_RDMA NX_CAP_BIT(1, 4) nxhal_nic_interface.h 　
32048
 NX_CAP1_ISCSINX_CAP1_ISCSI NX_CAP_BIT(1, 5) nxhal_nic_interface.h 　
32049
 NX_CAP1_FCOENX_CAP1_FCOE NX_CAP_BIT(1, 6) nxhal_nic_interface.h 　
32050
 NX_RX_RULETYPE_DEFAULTNX_RX_RULETYPE_DEFAULT 0 nxhal_nic_interface.h 　
32051
 NX_RX_RULETYPE_MACNX_RX_RULETYPE_MAC 1 nxhal_nic_interface.h 　
32052
 NX_RX_RULETYPE_MAC_VLANNX_RX_RULETYPE_MAC_VLAN 2 nxhal_nic_interface.h 　
32053
 NX_RX_RULETYPE_MAC_RSSNX_RX_RULETYPE_MAC_RSS 3 nxhal_nic_interface.h 　
32054
 NX_RX_RULETYPE_MAC_VLAN_RSSNX_RX_RULETYPE_MAC_VLAN_RSS 4 nxhal_nic_interface.h 　
32055
 NX_RX_RULETYPE_MAXNX_RX_RULETYPE_MAX 5 nxhal_nic_interface.h 　
32056
 NX_RX_RULECMD_ADDNX_RX_RULECMD_ADD 0 nxhal_nic_interface.h 　
32057
 NX_RX_RULECMD_REMOVENX_RX_RULECMD_REMOVE 1 nxhal_nic_interface.h 　
32058
 NX_RX_RULECMD_MAXNX_RX_RULECMD_MAX 2 nxhal_nic_interface.h 　
32059
 NX_HOST_CTX_STATE_FREEDNX_HOST_CTX_STATE_FREED 0 nxhal_nic_interface.h Invalid state
32060
 NX_HOST_CTX_STATE_ALLOCATEDNX_HOST_CTX_STATE_ALLOCATED 1 nxhal_nic_interface.h Not committed
32061
 NX_HOST_CTX_STATE_ACTIVENX_HOST_CTX_STATE_ACTIVE 2 nxhal_nic_interface.h 　
32062
 NX_HOST_CTX_STATE_DISABLEDNX_HOST_CTX_STATE_DISABLED 3 nxhal_nic_interface.h 　
32063
 NX_HOST_CTX_STATE_QUIESCEDNX_HOST_CTX_STATE_QUIESCED 4 nxhal_nic_interface.h 　
32064
 NX_HOST_CTX_STATE_MAXNX_HOST_CTX_STATE_MAX 5 nxhal_nic_interface.h 　
32065
 NX_HOST_INT_CRB_MODE_UNIQUENX_HOST_INT_CRB_MODE_UNIQUE 0 nxhal_nic_interface.h 　
32066
 NX_HOST_INT_CRB_MODE_SHAREDNX_HOST_INT_CRB_MODE_SHARED 1 nxhal_nic_interface.h <= LEGACY
32067
 NX_HOST_INT_CRB_MODE_NORXNX_HOST_INT_CRB_MODE_NORX 2 nxhal_nic_interface.h 　
32068
 NX_HOST_INT_CRB_MODE_NOTXNX_HOST_INT_CRB_MODE_NOTX 3 nxhal_nic_interface.h 　
32069
 NX_HOST_INT_CRB_MODE_NORXTXNX_HOST_INT_CRB_MODE_NORXTX 4 nxhal_nic_interface.h 　
32070
 NX_DESTROY_CTX_RESETNX_DESTROY_CTX_RESET 0 nxhal_nic_interface.h 　
32071
 NX_DESTROY_CTX_D3_RESETNX_DESTROY_CTX_D3_RESET 1 nxhal_nic_interface.h 　
32072
 NX_DESTROY_CTX_MAXNX_DESTROY_CTX_MAX 2 nxhal_nic_interface.h 　
32073
 NX_HOST_RDS_CRB_MODE_UNIQUENX_HOST_RDS_CRB_MODE_UNIQUE 0 nxhal_nic_interface.h <= LEGACY
32074
 NX_HOST_RDS_CRB_MODE_SHAREDNX_HOST_RDS_CRB_MODE_SHARED 1 nxhal_nic_interface.h 　
32075
 NX_HOST_RDS_CRB_MODE_CUSTOMNX_HOST_RDS_CRB_MODE_CUSTOM 2 nxhal_nic_interface.h 　
32076
 NX_HOST_RDS_CRB_MODE_MAXNX_HOST_RDS_CRB_MODE_MAX 3 nxhal_nic_interface.h 　
32077
 NX_RDS_RING_TYPE_NORMALNX_RDS_RING_TYPE_NORMAL 0 nxhal_nic_interface.h 　
32078
 NX_RDS_RING_TYPE_JUMBONX_RDS_RING_TYPE_JUMBO 1 nxhal_nic_interface.h 　
32079
 NX_RDS_RING_TYPE_LRONX_RDS_RING_TYPE_LRO 2 nxhal_nic_interface.h 　
32080
 NX_RDS_RING_TYPE_MAXNX_RDS_RING_TYPE_MAX 3 nxhal_nic_interface.h 　
32081
 NX_STATISTICS_MODE_INVALIDNX_STATISTICS_MODE_INVALID 0 nxhal_nic_interface.h 　
32082
 NX_STATISTICS_MODE_PULLNX_STATISTICS_MODE_PULL 1 nxhal_nic_interface.h 　
32083
 NX_STATISTICS_MODE_PUSHNX_STATISTICS_MODE_PUSH 2 nxhal_nic_interface.h 　
32084
 NX_STATISTICS_MODE_SINGLE_SHOTNX_STATISTICS_MODE_SINGLE_SHOT 3 nxhal_nic_interface.h 　
32085
 NX_STATISTICS_MODE_MAXNX_STATISTICS_MODE_MAX 4 nxhal_nic_interface.h 　
32086
 NX_STATISTICS_TYPE_INVALIDNX_STATISTICS_TYPE_INVALID 0 nxhal_nic_interface.h 　
32087
 NX_STATISTICS_TYPE_NIC_RX_CORENX_STATISTICS_TYPE_NIC_RX_CORE 1 nxhal_nic_interface.h 　
32088
 NX_STATISTICS_TYPE_NIC_TX_CORENX_STATISTICS_TYPE_NIC_TX_CORE 2 nxhal_nic_interface.h 　
32089
 NX_STATISTICS_TYPE_NIC_RX_ALLNX_STATISTICS_TYPE_NIC_RX_ALL 3 nxhal_nic_interface.h 　
32090
 NX_STATISTICS_TYPE_NIC_TX_ALLNX_STATISTICS_TYPE_NIC_TX_ALL 4 nxhal_nic_interface.h 　
32091
 NX_STATISTICS_TYPE_MAXNX_STATISTICS_TYPE_MAX 5 nxhal_nic_interface.h 　
32092
 NXHAL_VERSIONNXHAL_VERSION 1 phantom.h 　
32093
 UNM_DMA_BUFFER_ALIGNUNM_DMA_BUFFER_ALIGN 16 phantom.h 　
32094
 __unm_dma_aligned__unm_dma_aligned __attribute__ (( aligned ( UNM_DMA_BUFFER_ALIGN ) )) phantom.h 　
32095
 UNM_128M_CRB_WINDOWUNM_128M_CRB_WINDOW 0x6110210UL phantom.h 　
32096
 UNM_32M_CRB_WINDOWUNM_32M_CRB_WINDOW 0x0110210UL phantom.h 　
32097
 UNM_2M_CRB_WINDOWUNM_2M_CRB_WINDOW 0x0130060UL phantom.h 　
32098
 UNM_CRB_PCIEUNM_CRB_PCIE UNM_CRB_BASE ( UNM_CRB_BLK_PCIE ) phantom.h 　
32099
 UNM_PCIE_SEM2_LOCKUNM_PCIE_SEM2_LOCK ( UNM_CRB_PCIE + 0x1c010 ) phantom.h 　
32100
 UNM_PCIE_SEM2_UNLOCKUNM_PCIE_SEM2_UNLOCK ( UNM_CRB_PCIE + 0x1c014 ) phantom.h 　
32101
 UNM_PCIE_IRQ_VECTORUNM_PCIE_IRQ_VECTOR ( UNM_CRB_PCIE + 0x10100 ) phantom.h 　
32102
 UNM_PCIE_IRQ_STATEUNM_PCIE_IRQ_STATE ( UNM_CRB_PCIE + 0x1206c ) phantom.h 　
32103
 UNM_PCIE_IRQ_MASK_F0UNM_PCIE_IRQ_MASK_F0 ( UNM_CRB_PCIE + 0x10128 ) phantom.h 　
32104
 UNM_PCIE_IRQ_MASK_F1UNM_PCIE_IRQ_MASK_F1 ( UNM_CRB_PCIE + 0x10170 ) phantom.h 　
32105
 UNM_PCIE_IRQ_MASK_F2UNM_PCIE_IRQ_MASK_F2 ( UNM_CRB_PCIE + 0x10174 ) phantom.h 　
32106
 UNM_PCIE_IRQ_MASK_F3UNM_PCIE_IRQ_MASK_F3 ( UNM_CRB_PCIE + 0x10178 ) phantom.h 　
32107
 UNM_PCIE_IRQ_MASK_F4UNM_PCIE_IRQ_MASK_F4 ( UNM_CRB_PCIE + 0x10370 ) phantom.h 　
32108
 UNM_PCIE_IRQ_MASK_F5UNM_PCIE_IRQ_MASK_F5 ( UNM_CRB_PCIE + 0x10374 ) phantom.h 　
32109
 UNM_PCIE_IRQ_MASK_F6UNM_PCIE_IRQ_MASK_F6 ( UNM_CRB_PCIE + 0x10378 ) phantom.h 　
32110
 UNM_PCIE_IRQ_MASK_F7UNM_PCIE_IRQ_MASK_F7 ( UNM_CRB_PCIE + 0x1037c ) phantom.h 　
32111
 UNM_PCIE_IRQ_MASK_MAGICUNM_PCIE_IRQ_MASK_MAGIC 0x0000fbffUL phantom.h 　
32112
 UNM_PCIE_IRQ_STATUS_F0UNM_PCIE_IRQ_STATUS_F0 ( UNM_CRB_PCIE + 0x10118 ) phantom.h 　
32113
 UNM_PCIE_IRQ_STATUS_F1UNM_PCIE_IRQ_STATUS_F1 ( UNM_CRB_PCIE + 0x10160 ) phantom.h 　
32114
 UNM_PCIE_IRQ_STATUS_F2UNM_PCIE_IRQ_STATUS_F2 ( UNM_CRB_PCIE + 0x10164 ) phantom.h 　
32115
 UNM_PCIE_IRQ_STATUS_F3UNM_PCIE_IRQ_STATUS_F3 ( UNM_CRB_PCIE + 0x10168 ) phantom.h 　
32116
 UNM_PCIE_IRQ_STATUS_F4UNM_PCIE_IRQ_STATUS_F4 ( UNM_CRB_PCIE + 0x10360 ) phantom.h 　
32117
 UNM_PCIE_IRQ_STATUS_F5UNM_PCIE_IRQ_STATUS_F5 ( UNM_CRB_PCIE + 0x10364 ) phantom.h 　
32118
 UNM_PCIE_IRQ_STATUS_F6UNM_PCIE_IRQ_STATUS_F6 ( UNM_CRB_PCIE + 0x10368 ) phantom.h 　
32119
 UNM_PCIE_IRQ_STATUS_F7UNM_PCIE_IRQ_STATUS_F7 ( UNM_CRB_PCIE + 0x1036c ) phantom.h 　
32120
 UNM_PCIE_IRQ_STATUS_MAGICUNM_PCIE_IRQ_STATUS_MAGIC 0xffffffffUL phantom.h 　
32121
 UNM_CRB_CAMUNM_CRB_CAM UNM_CRB_BASE ( UNM_CRB_BLK_CAM ) phantom.h 　
32122
 UNM_CAM_RAMUNM_CAM_RAM ( UNM_CRB_CAM + 0x02000 ) phantom.h 　
32123
 UNM_CAM_RAM_PORT_MODEUNM_CAM_RAM_PORT_MODE ( UNM_CAM_RAM + 0x00024 ) phantom.h 　
32124
 UNM_CAM_RAM_PORT_MODE_AUTO_NEGUNM_CAM_RAM_PORT_MODE_AUTO_NEG 4 phantom.h 　
32125
 UNM_CAM_RAM_PORT_MODE_AUTO_NEG_UNM_CAM_RAM_PORT_MODE_AUTO_NEG_ 5 phantom.h 　
32126
 UNM_CAM_RAM_DMESG_SIG_MAGICUNM_CAM_RAM_DMESG_SIG_MAGIC 0xcafebabeUL phantom.h 　
32127
 UNM_CAM_RAM_NUM_DMESG_BUFFERSUNM_CAM_RAM_NUM_DMESG_BUFFERS 5 phantom.h 　
32128
 UNM_CAM_RAM_CLP_COMMANDUNM_CAM_RAM_CLP_COMMAND ( UNM_CAM_RAM + 0x000c0 ) phantom.h 　
32129
 UNM_CAM_RAM_CLP_COMMAND_LASTUNM_CAM_RAM_CLP_COMMAND_LAST 0x00000080UL phantom.h 　
32130
 UNM_CAM_RAM_CLP_DATA_LOUNM_CAM_RAM_CLP_DATA_LO ( UNM_CAM_RAM + 0x000c4 ) phantom.h 　
32131
 UNM_CAM_RAM_CLP_DATA_HIUNM_CAM_RAM_CLP_DATA_HI ( UNM_CAM_RAM + 0x000c8 ) phantom.h 　
32132
 UNM_CAM_RAM_CLP_STATUSUNM_CAM_RAM_CLP_STATUS ( UNM_CAM_RAM + 0x000cc ) phantom.h 　
32133
 UNM_CAM_RAM_CLP_STATUS_STARTUNM_CAM_RAM_CLP_STATUS_START 0x00000001UL phantom.h 　
32134
 UNM_CAM_RAM_CLP_STATUS_DONEUNM_CAM_RAM_CLP_STATUS_DONE 0x00000002UL phantom.h 　
32135
 UNM_CAM_RAM_CLP_STATUS_ERRORUNM_CAM_RAM_CLP_STATUS_ERROR 0x0000ff00UL phantom.h 　
32136
 UNM_CAM_RAM_CLP_STATUS_UNINITIAUNM_CAM_RAM_CLP_STATUS_UNINITIA 0xffffffffUL phantom.h 　
32137
 UNM_CAM_RAM_BOOT_ENABLEUNM_CAM_RAM_BOOT_ENABLE ( UNM_CAM_RAM + 0x000fc ) phantom.h 　
32138
 UNM_CAM_RAM_WOL_PORT_MODEUNM_CAM_RAM_WOL_PORT_MODE ( UNM_CAM_RAM + 0x00198 ) phantom.h 　
32139
 UNM_CAM_RAM_MAC_ADDRSUNM_CAM_RAM_MAC_ADDRS ( UNM_CAM_RAM + 0x001c0 ) phantom.h 　
32140
 UNM_CAM_RAM_COLD_BOOTUNM_CAM_RAM_COLD_BOOT ( UNM_CAM_RAM + 0x001fc ) phantom.h 　
32141
 UNM_CAM_RAM_COLD_BOOT_MAGICUNM_CAM_RAM_COLD_BOOT_MAGIC 0x55555555UL phantom.h 　
32142
 UNM_NIC_REGUNM_NIC_REG ( UNM_CRB_CAM + 0x02200 ) phantom.h 　
32143
 UNM_NIC_REG_NX_CDRPUNM_NIC_REG_NX_CDRP ( UNM_NIC_REG + 0x00018 ) phantom.h 　
32144
 UNM_NIC_REG_NX_ARG1UNM_NIC_REG_NX_ARG1 ( UNM_NIC_REG + 0x0001c ) phantom.h 　
32145
 UNM_NIC_REG_NX_ARG2UNM_NIC_REG_NX_ARG2 ( UNM_NIC_REG + 0x00020 ) phantom.h 　
32146
 UNM_NIC_REG_NX_ARG3UNM_NIC_REG_NX_ARG3 ( UNM_NIC_REG + 0x00024 ) phantom.h 　
32147
 UNM_NIC_REG_NX_SIGNUNM_NIC_REG_NX_SIGN ( UNM_NIC_REG + 0x00028 ) phantom.h 　
32148
 UNM_NIC_REG_DUMMY_BUF_ADDR_HIUNM_NIC_REG_DUMMY_BUF_ADDR_HI ( UNM_NIC_REG + 0x0003c ) phantom.h 　
32149
 UNM_NIC_REG_DUMMY_BUF_ADDR_LOUNM_NIC_REG_DUMMY_BUF_ADDR_LO ( UNM_NIC_REG + 0x00040 ) phantom.h 　
32150
 UNM_NIC_REG_CMDPEG_STATEUNM_NIC_REG_CMDPEG_STATE ( UNM_NIC_REG + 0x00050 ) phantom.h 　
32151
 UNM_NIC_REG_CMDPEG_STATE_INITIAUNM_NIC_REG_CMDPEG_STATE_INITIA 0xff01 phantom.h 　
32152
 UNM_NIC_REG_CMDPEG_STATE_INITIAUNM_NIC_REG_CMDPEG_STATE_INITIA 0xf00f phantom.h 　
32153
 UNM_NIC_REG_DUMMY_BUFUNM_NIC_REG_DUMMY_BUF ( UNM_NIC_REG + 0x000fc ) phantom.h 　
32154
 UNM_NIC_REG_DUMMY_BUF_INITUNM_NIC_REG_DUMMY_BUF_INIT 0 phantom.h 　
32155
 UNM_NIC_REG_XG_STATE_P3UNM_NIC_REG_XG_STATE_P3 ( UNM_NIC_REG + 0x00098 ) phantom.h 　
32156
 UNM_NIC_REG_XG_STATE_P3_LINK_UPUNM_NIC_REG_XG_STATE_P3_LINK_UP 0x01 phantom.h 　
32157
 UNM_NIC_REG_XG_STATE_P3_LINK_DOUNM_NIC_REG_XG_STATE_P3_LINK_DO 0x02 phantom.h 　
32158
 UNM_NIC_REG_RCVPEG_STATEUNM_NIC_REG_RCVPEG_STATE ( UNM_NIC_REG + 0x0013c ) phantom.h 　
32159
 UNM_NIC_REG_RCVPEG_STATE_INITIAUNM_NIC_REG_RCVPEG_STATE_INITIA 0xff01 phantom.h 　
32160
 UNM_CRB_ROMUSBUNM_CRB_ROMUSB UNM_CRB_BASE ( UNM_CRB_BLK_ROMUSB ) phantom.h 　
32161
 UNM_ROMUSB_GLBUNM_ROMUSB_GLB ( UNM_CRB_ROMUSB + 0x00000 ) phantom.h 　
32162
 UNM_ROMUSB_GLB_STATUSUNM_ROMUSB_GLB_STATUS ( UNM_ROMUSB_GLB + 0x00004 ) phantom.h 　
32163
 UNM_ROMUSB_GLB_STATUS_ROM_DONEUNM_ROMUSB_GLB_STATUS_ROM_DONE ( 1 << 1 ) phantom.h 　
32164
 UNM_ROMUSB_GLB_SW_RESETUNM_ROMUSB_GLB_SW_RESET ( UNM_ROMUSB_GLB + 0x00008 ) phantom.h 　
32165
 UNM_ROMUSB_GLB_SW_RESET_MAGICUNM_ROMUSB_GLB_SW_RESET_MAGIC 0x0080000fUL phantom.h 　
32166
 UNM_ROMUSB_GLB_PEGTUNE_DONEUNM_ROMUSB_GLB_PEGTUNE_DONE ( UNM_ROMUSB_GLB + 0x0005c ) phantom.h 　
32167
 UNM_ROMUSB_GLB_PEGTUNE_DONE_MAGUNM_ROMUSB_GLB_PEGTUNE_DONE_MAG 0x31 phantom.h 　
32168
 UNM_ROMUSB_ROMUNM_ROMUSB_ROM ( UNM_CRB_ROMUSB + 0x10000 ) phantom.h 　
32169
 UNM_ROMUSB_ROM_INSTR_OPCODEUNM_ROMUSB_ROM_INSTR_OPCODE ( UNM_ROMUSB_ROM + 0x00004 ) phantom.h 　
32170
 UNM_ROMUSB_ROM_ADDRESSUNM_ROMUSB_ROM_ADDRESS ( UNM_ROMUSB_ROM + 0x00008 ) phantom.h 　
32171
 UNM_ROMUSB_ROM_WDATAUNM_ROMUSB_ROM_WDATA ( UNM_ROMUSB_ROM + 0x0000c ) phantom.h 　
32172
 UNM_ROMUSB_ROM_ABYTE_CNTUNM_ROMUSB_ROM_ABYTE_CNT ( UNM_ROMUSB_ROM + 0x00010 ) phantom.h 　
32173
 UNM_ROMUSB_ROM_DUMMY_BYTE_CNTUNM_ROMUSB_ROM_DUMMY_BYTE_CNT ( UNM_ROMUSB_ROM + 0x00014 ) phantom.h 　
32174
 UNM_ROMUSB_ROM_RDATAUNM_ROMUSB_ROM_RDATA ( UNM_ROMUSB_ROM + 0x00018 ) phantom.h 　
32175
 UNM_CRB_TESTUNM_CRB_TEST UNM_CRB_BASE ( UNM_CRB_BLK_TEST ) phantom.h 　
32176
 UNM_TEST_CONTROLUNM_TEST_CONTROL ( UNM_CRB_TEST + 0x00090 ) phantom.h 　
32177
 UNM_TEST_CONTROL_STARTUNM_TEST_CONTROL_START 0x01 phantom.h 　
32178
 UNM_TEST_CONTROL_ENABLEUNM_TEST_CONTROL_ENABLE 0x02 phantom.h 　
32179
 UNM_TEST_CONTROL_BUSYUNM_TEST_CONTROL_BUSY 0x08 phantom.h 　
32180
 UNM_TEST_ADDR_LOUNM_TEST_ADDR_LO ( UNM_CRB_TEST + 0x00094 ) phantom.h 　
32181
 UNM_TEST_ADDR_HIUNM_TEST_ADDR_HI ( UNM_CRB_TEST + 0x00098 ) phantom.h 　
32182
 UNM_TEST_RDDATA_LOUNM_TEST_RDDATA_LO ( UNM_CRB_TEST + 0x000a8 ) phantom.h 　
32183
 UNM_TEST_RDDATA_HIUNM_TEST_RDDATA_HI ( UNM_CRB_TEST + 0x000ac ) phantom.h 　
32184
 UNM_CRB_PEG_0UNM_CRB_PEG_0 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_0 ) phantom.h 　
32185
 UNM_PEG_0_HALT_STATUSUNM_PEG_0_HALT_STATUS ( UNM_CRB_PEG_0 + 0x00030 ) phantom.h 　
32186
 UNM_PEG_0_HALTUNM_PEG_0_HALT ( UNM_CRB_PEG_0 + 0x0003c ) phantom.h 　
32187
 UNM_CRB_PEG_1UNM_CRB_PEG_1 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_1 ) phantom.h 　
32188
 UNM_PEG_1_HALT_STATUSUNM_PEG_1_HALT_STATUS ( UNM_CRB_PEG_1 + 0x00030 ) phantom.h 　
32189
 UNM_PEG_1_HALTUNM_PEG_1_HALT ( UNM_CRB_PEG_1 + 0x0003c ) phantom.h 　
32190
 UNM_CRB_PEG_2UNM_CRB_PEG_2 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_2 ) phantom.h 　
32191
 UNM_PEG_2_HALT_STATUSUNM_PEG_2_HALT_STATUS ( UNM_CRB_PEG_2 + 0x00030 ) phantom.h 　
32192
 UNM_PEG_2_HALTUNM_PEG_2_HALT ( UNM_CRB_PEG_2 + 0x0003c ) phantom.h 　
32193
 UNM_CRB_PEG_3UNM_CRB_PEG_3 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_3 ) phantom.h 　
32194
 UNM_PEG_3_HALT_STATUSUNM_PEG_3_HALT_STATUS ( UNM_CRB_PEG_3 + 0x00030 ) phantom.h 　
32195
 UNM_PEG_3_HALTUNM_PEG_3_HALT ( UNM_CRB_PEG_3 + 0x0003c ) phantom.h 　
32196
 UNM_CRB_PEG_4UNM_CRB_PEG_4 UNM_CRB_BASE ( UNM_CRB_BLK_PEG_4 ) phantom.h 　
32197
 UNM_PEG_4_HALT_STATUSUNM_PEG_4_HALT_STATUS ( UNM_CRB_PEG_4 + 0x00030 ) phantom.h 　
32198
 UNM_PEG_4_HALTUNM_PEG_4_HALT ( UNM_CRB_PEG_4 + 0x0003c ) phantom.h 　
32199
 GRF5101_ANTENNAGRF5101_ANTENNA 0xA3 rtl8180_grf5101.c 　
32200
 MAXIM_ANTENNAMAXIM_ANTENNA 0xb3 rtl8180_max2820.c 　
32201
 SA2400_ANTENNASA2400_ANTENNA 0x91 rtl8180_sa2400.c 　
32202
 SA2400_DIG_ANAPARAM_PWR1_ONSA2400_DIG_ANAPARAM_PWR1_ON 0x8 rtl8180_sa2400.c 　
32203
 SA2400_ANA_ANAPARAM_PWR1_ONSA2400_ANA_ANAPARAM_PWR1_ON 0x28 rtl8180_sa2400.c 　
32204
 SA2400_ANAPARAM_PWR0_ONSA2400_ANAPARAM_PWR0_ON 0x3 rtl8180_sa2400.c 　
32205
 SA2400_MAX_SENSSA2400_MAX_SENS 85 rtl8180_sa2400.c 　
32206
 SA2400_REG4_FIRDAC_SHIFTSA2400_REG4_FIRDAC_SHIFT 7 rtl8180_sa2400.c 　
32207
 RTL8225_ANAPARAM_ONRTL8225_ANAPARAM_ON 0xa0000b59 rtl8185_rtl8225.c 　
32208
 RTL8225_ANAPARAM2_ONRTL8225_ANAPARAM2_ON 0x860dec11 rtl8185_rtl8225.c 　
32209
 RTL8225_ANAPARAM_OFFRTL8225_ANAPARAM_OFF 0xa00beb59 rtl8185_rtl8225.c 　
32210
 RTL8225_ANAPARAM2_OFFRTL8225_ANAPARAM2_OFF 0x840dec11 rtl8185_rtl8225.c 　
32211
 RTL818X_NR_B_RATESRTL818X_NR_B_RATES 4 rtl818x.c 　
32212
 RTL818X_NR_RATESRTL818X_NR_RATES 12 rtl818x.c 　
32213
 RTL818X_NR_RF_NAMESRTL818X_NR_RF_NAMES 11 rtl818x.c 　
32214
 RTL_ROMRTL_ROM PCI_ROM rtl818x.c 　
32215
 MAX_RX_SIZEMAX_RX_SIZE IEEE80211_MAX_FRAME_LEN rtl818x.h 　
32216
 RF_PARAM_ANALOGPHYRF_PARAM_ANALOGPHY (1 << 0) rtl818x.h 　
32217
 RF_PARAM_ANTBDEFAULTRF_PARAM_ANTBDEFAULT (1 << 1) rtl818x.h 　
32218
 RF_PARAM_CARRIERSENSE1RF_PARAM_CARRIERSENSE1 (1 << 2) rtl818x.h 　
32219
 RF_PARAM_CARRIERSENSE2RF_PARAM_CARRIERSENSE2 (1 << 3) rtl818x.h 　
32220
 BB_ANTATTEN_CHAN14BB_ANTATTEN_CHAN14 0x0C rtl818x.h 　
32221
 BB_ANTENNA_BBB_ANTENNA_B 0x40 rtl818x.h 　
32222
 BB_HOST_BANGBB_HOST_BANG (1 << 30) rtl818x.h 　
32223
 BB_HOST_BANG_ENBB_HOST_BANG_EN (1 << 2) rtl818x.h 　
32224
 BB_HOST_BANG_CLKBB_HOST_BANG_CLK (1 << 1) rtl818x.h 　
32225
 BB_HOST_BANG_DATABB_HOST_BANG_DATA 1 rtl818x.h 　
32226
 ANAPARAM_TXDACOFF_SHIFTANAPARAM_TXDACOFF_SHIFT 27 rtl818x.h 　
32227
 ANAPARAM_PWR0_SHIFTANAPARAM_PWR0_SHIFT 28 rtl818x.h 　
32228
 ANAPARAM_PWR0_MASKANAPARAM_PWR0_MASK (0x07 << ANAPARAM_PWR0_SHIFT) rtl818x.h 　
32229
 ANAPARAM_PWR1_SHIFTANAPARAM_PWR1_SHIFT 20 rtl818x.h 　
32230
 ANAPARAM_PWR1_MASKANAPARAM_PWR1_MASK (0x7F << ANAPARAM_PWR1_SHIFT) rtl818x.h 　
32231
 RTL818X_RX_RING_SIZERTL818X_RX_RING_SIZE 8 rtl818x.h doesn't have to be a power of 2
32232
 RTL818X_TX_RING_SIZERTL818X_TX_RING_SIZE 8 rtl818x.h nor this [but 2^n is very slightly faster]
32233
 RTL818X_RING_ALIGNRTL818X_RING_ALIGN 256 rtl818x.h 　
32234
 RTL818X_MAX_RETRIESRTL818X_MAX_RETRIES 4 rtl818x.h 　
32235
 RTL818X_RF_DRIVERSRTL818X_RF_DRIVERS __table(struct rtl818x_rf_ops, "rtl818x_rf_drivers") rtl818x.h 　
32236
 __rtl818x_rf_driver__rtl818x_rf_driver __table_entry(RTL818X_RF_DRIVERS, 01) rtl818x.h 　

See Also

目次 | ファイル一覧 | 関数一覧 | ネームスペース一覧 | クラス一覧 | #define一覧 | マクロ一覧 | 外部変数一覧 | 構造体一覧 | 共用体一覧 | 列挙体一覧 | Const一覧 | 索引 | サイドメニュー

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